| Document | Document Title |
|---|---|
| US10511440B2 |
Methods of proving validity and determining validity, electronic device, server and computer programs
A device provides a one-time proof of knowledge about a one-time signing key to a server without revealing the one-time signing key by computing a hash as a hash function from the one-time signing key, and transmitting, to the server, the computed hash, an identity associated with the electronic device and a hash path of the hash. The server receives the message from the device and checks whether the hash corresponds to a one-time signing key for a root hash included in a public certificate associated with the identity, checks whether an index corresponding to the hash path from the one-time signing key to the root hash corresponds to a correct time slot, and determines it to be proven that the device is in possession of the correct one-time signing key when the checks are fulfilled. |
| US10511439B2 |
Method for implementing encrypted client-server communication
A method for implementing an encrypted client-server communication, wherein the server includes an entry point, service systems behind the entry point, and a secure system. The method includes incorporating common cryptographic material into the client and into the secure system, deriving key material from the common cryptographic material in the client for an encrypted communication between the client and a service system, deriving key material from the common cryptographic material in the secure system for an encrypted communication between the client and a service system, and transferring the key material into the service system or retaining the key material in the secure system. |
| US10511433B2 |
Timing attack protection in a cryptographic processing system
Apparatus and method for enacting data security in a cryptographic processing system, such as a data storage device. In some embodiments, a timer circuit is initiated to denote an elapsed time interval of predetermined duration responsive to a function call by an initiator circuit to perform a selected cryptographic function upon input data. The selected cryptographic function is executed to generate output data which are temporarily stored in a memory location during a waiting period prior to a conclusion of the elapsed time interval. Additional functions may be performed during the waiting period. A notification from the timer circuit is received at the conclusion of the elapsed time interval, and the output data are transferred from the memory to the initiator circuit. In this way, a timing attack may be defended against by configuring the selected cryptographic function to have the same overall execution time for different input data sets. |
| US10511430B2 |
Spectrum-agile multiple input multiple output system and capacity adaptation between uplink and downlink
A multi-input multi-output rotating frequency division duplexing transceiver in non-contiguous bands comprising an adaptive duplex filter, a controller coupled to the adaptive duplex filter, wherein an uplink band and a downlink band are rotated before each transmission sub-frame, and wherein at least two of the bands are non-contiguous, a multi-output adaptive frequency synthesizer coupled to the controller, a transmit mixer coupled to the adaptive duplex filter and to the multi-output adaptive frequency synthesizer and a receive mixer coupled to the adaptive duplex filter and to the multi-output adaptive frequency synthesizer. |
| US10511429B2 |
Method and device for transmitting and receiving data by using multiple carriers in mobile communication system
To solve the above-mentioned problem, the method for transmitting and receiving a signal by user equipment (UE) through one or more cells, according to one embodiment of the present specification, comprises the steps of: receiving, from a base station, a first message indicating whether one or more cells usable by the UE are enabled; determining which cells to enable or disable on the basis of the first message; and enabling or disabling the selected cells. According to the embodiment of the present specification, by aggregating carriers amongst different base stations, a possibility for the UE to transmit and receive high-speed data through carrier aggregation can increase. |
| US10511427B2 |
Uplink control channel for acknowledging increased number of downlink component carriers
Techniques are described for wireless communication. One method includes determining, based at least in part on a number of downlink component carriers (CCs) scheduled for a user equipment (UE) during a reporting interval, a number of bits to be included in a physical uplink control channel (PUCCH) acknowledgement/non-acknowledgement (ACK/NAK) payload for the reporting interval; and selecting, based at least in part on the determined number of bits, a format of the PUCCH ACK/NAK payload. |
| US10511426B2 |
Method and apparatus for transmitting/receiving positioning reference signal
An apparatus and method for processing positioning reference signal are disclosed. A method may include receiving, by a narrow-band (NB) user equipment (UE), positioning reference signal (PRS) configuration information, determining, by the NB UE, narrowband PRS (NB PRS) configuration information for the NB UE, the NB PRS configuration information comprising information of an NB PRS reference cell that generates an NB PRS for the NB UE, determining, by the NB UE, PRS configuration information for a UE, the UE being assigned to use a frequency band unavailable for the NB UE, and the PRS configuration information comprising information of a PRS reference cell that generates a PRS for the UE, generating, based on the NB PRS configuration information and the PRS configuration information, a reference signal time difference (RSTD) measurement, and transmitting, by the NB UE, the RSTD measurement. |
| US10511423B2 |
Data transmission method, terminal device, and base station
A data transmission method, a terminal device, and a base station are described. The data transmission method determines, by a terminal device, a first reference signal (RS) sequence corresponding to a first time interval, where the first RS sequence is one of N RS sequences, N is a positive integer greater than 1, and the N RS sequences are generated based on at least two root sequences, sends, by the terminal device, the first RS sequence to a base station in the first time interval, determines, by the terminal device from the N RS sequences according to the first RS sequence, one RS sequence as a second RS sequence corresponding to a second time interval, where the second RS sequence is determined according to the first RS sequence, and sends the second RS sequence to the base station in the second time interval. |
| US10511422B2 |
Method and terminal for transmitting reference signal in D2D communication
Suggested is a method for transmitting a reference signal in a device-to-device (D2D) communication. A terminal according to the present invention may transmit a physical sidelink broadcast channel (PSBCH) in which a reference signal is mapped to at least three symbols. The reference signal comprises a demodulation reference signal (DMRS), and may be mapped to orthogonal frequency division multiplexing (OFDM) symbols #4, #6 and #9. |
| US10511421B2 |
CSI-RS design with dynamic subframe structure
Methods, systems, and devices for wireless communication are described. A base station and user equipment (UE) may use subframe configurations that include dynamically scheduled channel state information reference signal (CSI-RS) symbols. For example, a base station may identify a subframe configuration that includes one or more sets of CSI-RS symbols of a subframe. The base station may indicate to a UE whether sets of CSI-RS symbols may be enabled or disabled during the subframe. The UE may receive multiple CSI-RSs at different locations within the subframe as indicated by the base station, and transmit CSI feedback to the base station based on at least one of the received CSI-RSs. In some examples, multiple base stations may coordinate the use of subframe configurations that include CSI-RS symbols that may be enabled or disabled. |
| US10511415B2 |
Uplink ACK resource allocation in new radio
A method and apparatus for enabling an UE to selecting acknowledgement/non-acknowledgement (ACK/NACK) resources from a subset of a gNB resource pool. The example method may receive, from an gNB, a radio resource control (RRC) configuration indicating a UE-specific resource set that is a subset of a gNB resource pool. The UE may determine one or more ACK/NACK resources from the UE-specific resource set for an upcoming physical uplink control channel (PUCCH). In some aspects, the UE may determine the one or more ACK/NACK resources based on receiving, from the gNB, a physical downlink control channel (PDCCH) including a corresponding ACK/NACK resource configuration. In other aspects, the RRC may contain multiple resource subsets and the UE may determine the one or more ACK/NACK resources based on determining a size of a payload for a UCI to be transmitted on the PUCCH. The aspects may thus enable dynamic ACK/NACK resource allocation. |
| US10511413B2 |
Hybrid automatic repeat requests in a wireless device and wireless network
A wireless device receives a grant for one or more subframes. The grant comprises a hybrid automatic repeat request process number (HARQ ID). The wireless device transmits a transport block in a subframe of the one or more subframes employing a first HARQ ID being calculated based on the HARQ ID and a position of the subframe in the one or more subframes. |
| US10511412B2 |
System and method for HARQ in cloud RAN with large front haul latency
A system is enabled to perform error checking and other HARQ processes at a remote radio unit device in cloud RAN systems that have a large front haul latency. The remote radio unit device performs error checking on transmissions received from a mobile device and sends an acknowledgement (ACK) or negative acknowledgement (NACK) to the mobile device based on whether errors are found. |
| US10511408B2 |
Code block segmentation for new radio
According to some embodiments, a method for use in a wireless transmitter of encoding a transport block comprises, upon determining a code rate for transmitting a transport block is less than or equal to R_threshold (R_threshold is between ⅕ and ⅓), selecting new radio (NR) low-density parity-check (LDPC) base graph 2 for encoding the transport block. Otherwise, the method comprises selecting NR LDPC base graph 1 for encoding the transport block, unless a transport block size (TBS) of the transport block is less than or equal to a size threshold (X) and a code rate for transmitting the transport block is less than or equal to ⅔, in which case the method may comprise selecting base graph 2. The method further comprises encoding the transport block using the selected base graph and transmitting the encoded transport block to a wireless receiver. |
| US10511404B2 |
System and method for triggering an alarm during a sensor jamming attack
Methods, systems, and apparatus, including computer programs encoded on a storage device, for triggering an alarm during a sensor jamming attack. In one aspect, a monitoring system sensor unit is disclosed that includes a sensor, a communication unit configured to communicate with a monitoring system using a range of frequencies, and a jamming detection unit. The jamming detection unit may include a processor and a computer storage media storing instructions that, when executed by the processor, cause the processor to perform operations. The operations include detecting a sensor jamming event, selecting a different form of communication other than the range of radio frequencies for the communication unit to communicate with the monitoring system, and providing, to the communication unit, an instruction to communicate with the monitoring system using the form of communication, wherein the communication unit may communicate, to the monitoring system using the form of communication, the sensor data. |
| US10511403B2 |
System and method for controlling time dilation in time-sensitive networks
A system and method determine a clock drift and a clock variance of each node in plural nodes of a time-sensitive Ethernet network. An accumulated clock offset along a time-sensitive network path in the time-sensitive network is determined based on the clock drifts and the clock variances. A guard band having a dynamic size is determined based on the accumulated clock offset. The times at which Ethernet frames are communicated through the nodes are restricted by communicating the guard band with the dynamic size to one or more of the nodes. |
| US10511402B2 |
Method and system for assigning resources in optical transport networks
The proposed invention is in the area of managing resources in optical transport networks, for example in the area of in-operation media channel format and spectrum management. For this purpose, the type of Media Channel Format is determined for each of a plurality of candidate paths, wherein each candidate path connects a pair of nodes in an optical transport network. Then, the expected weight describing traffic volume of each of the candidate paths is determined, and a spectrum share is assigned to each link of each of the candidate paths based on the determined Media Channel Formats and determined weights. In this way, spectrum shares assigned to different links and candidate paths can be used for efficiently assigning a band spectrum to each of the Media Channel Formats of the candidate paths. |
| US10511401B2 |
Optical protection switch with broadcast multi-directional capability
An apparatus includes a first reconfigurable optical add/drop multiplexer (ROADM) to receive a first optical signal and a second ROADM to receive a second optical signal. The apparatus also includes a reconfigurable optical switch that includes a first switch, switchable between a first state and a second state, to transmit the first optical signal at the first state and block the first optical signal at the second state. The reconfigurable optical switch also includes a second switch, switchable between the first state and the second state, to transmit the second optical signal at the first state and block the second optical signal at the second state. The reconfigurable optical switch also includes an output port to transmit an output signal that is a sum of possible optical signals transmitted through the first switch and the second switch. |
| US10511399B2 |
Techniques and apparatuses for downlink control channel design using a top to bottom search space
User equipment associated with a legacy network may utilize a bottom-to-top search technique to identify relevant control channel samples. Generating a control channel that is configured for the bottom-to-top search technique may lead to poor performance in a single-carrier waveform, which may be disadvantageous as networks move toward New Radio. In some aspects, described herein, a base station generates a control channel that is configured to minimize gaps in the control channel, and a user equipment performs a top-to-bottom search technique to identify relevant control channel samples. By using the top-to-bottom search technique, degradation of single-carrier waveforms is reduced and efficiency is improved. |
| US10511393B2 |
Geocast-based file transfer
Geocast-based file transfer may be implemented via use of a Geocast File Transfer (GFT) protocol. A sending device may parse a file into multiple chunks. Respective multiple geocast packets comprising the chunks may be geocast. The sending device may geocast all packets sequentially. Upon geocasting all packets, the sending device may wait a predetermined amount of time. During the period of time, any receiving device that did not receive a chunk of the file may geocast a request for the missing chunk. Receiving devices also may wait various respective amounts of time before geocasting requests. Other receiving devices that may have missed a chunk may hear that the chunk it missed is being requested. And that device need not make a request for the chunk. Rather, that device may wait for the sending device to retransmit a geocast packet that contains the missing chunk. |
| US10511392B2 |
Systems, methods, and computer programs for wireless local area network localization
Disclosed are various embodiments that enable the identification of the location of a computing device based on radio data. A radio map can be identified for an area. The computing device can measure signal strengths to reference points. The signal strengths can be compared to the radio map. The computing device can determine its location based on the comparison of the signal strengths to the radio map. |
| US10511391B1 |
Dynamic recalibration of a beamformer
Methods and systems are provided for dynamically recalibrating a beamformer at a cell site based on changes to various characteristics, including environmental characteristics and signal characteristics. A change in temperature, pressure, moisture level, or wind speed may indicate that a recalibration of the beamformer should be triggered. Additionally, at least the phase and amplitude of a received signal from a beacon station, which is used as a reference point, can be compared to the phase and amplitude of a reference signal to determine if one or both of the phase and amplitude has significantly changed. Based on the analysis of the characteristics, recalibration of the beamformer may be triggered. |
| US10511390B2 |
Data sharing using body coupled communication
Method for sharing data (SD2) between users (11,12). The method comprises initiating body coupled communication (BCC) between first and second devices (21,22) and in response to the body coupled communication (BCC), sending a data request (Q1) from one or both of the devices (21,22) to a remote server (30). The data request (Q1,Q2) comprises first device data (ID1) and the second device data (ID2). The server (30) processes the data request (Q1) and determines shared data (SD2) based at least in part on both the first device data (ID1) and the second device data (ID2). The server sends a data response (R1) to the first device (21), wherein the data response (R1) comprises the shared data (SD2). |
| US10511389B2 |
Piezoelectric module
Provided is a piezoelectric module capable of attempting further miniaturization. In the piezoelectric module, a resonance point is excluded from a frequency band of a transmitted signal to avoid shortening of a signal transmission distance, thereby attempting improvement in stability of communication. In addition, since a resonance space is not provided, further miniaturization may be easily attempted. |
| US10511384B1 |
Devices and methods for optical communication in a rotary platform
In one example, a device includes a first platform having a first side and a second platform having a second side that overlaps the first side. The device also includes an actuator that rotates the first platform relative to the second platform. The device also includes a plurality of light sources mounted to the first platform in a substantially circular arrangement around the axis of rotation of the first platform. The plurality of light sources emit a plurality of light beams such that respective adjacent light beams intersect at least at a predetermined distance to the first side. The first side remains at least at the predetermined distance to the second side in response to the actuator rotating the first platform. The device also includes a light detector mounted to the second platform and positioned to at least partially overlap at least one of the plurality of light beams. |
| US10511382B2 |
Dynamic monitoring and calibration of nodes in an optical networking device
A monitoring and calibration apparatus for an optical networking device such as ROADM is provided. Reflectors are integrated into the device, for example at the ends of optical interconnect cables. The reflectors reflect light in specific monitoring wavelengths and pass other wavelengths such as those used for communication. A light source emits monitoring light which is reflected by the reflector and measured by a detector to measure the integrity of optical paths. The optical paths can include optical cables and cable connectors. Path integrity between different modules of the device can therefore be monitored. Multiple reflectors, reflecting light in different wavelengths, can be placed in series along the same optical path and used to monitor multiple segments of the path. A wavelength selective switch (WSS) of the device can be used to route monitoring light to different optical paths. The WSS also operates to route communication signals in the device. |
| US10511380B2 |
System and method for efficient wideband code division multiplexing in subband domain
System and method for efficient wideband code division multiplexing in subband domain include: aggregating L analog signals received from L antenna elements into a single aggregated signal, by using code division multiplexing with L code words, where L is an integer greater than 1; converting the single aggregated analog signal to a single aggregated digital signal, by a single analog-to-digital converter (ADC); channelizing the single aggregated digital signal into N subbands, where N is an integer greater than 1; performing circular convolutions of the N subbands with the L code words to demultiplex the channelized signal into L elements per subband; and routing each subband signal of the L elements to N beamforming circuits for performing beamforming on each of the N subbands. |
| US10511375B2 |
IP camera with wireless relay function
An IP camera with a wireless relay function includes a lens, a wireless client interface, a wired client interface, a Wi-Fi SoftAP interface, and a bridge interface. The lens receives image data. The wireless client interface transmits the image data to a first wireless client device through a wireless network. The wired client interface transmits the image data to a first wired client device through a wired network. The Wi-Fi SoftAP interface is a virtual interface to be connected to a second wireless client. The bridge interface uses the Wi-Fi SoftAP interface to communicate with the second wireless client, and connects the Wi-Fi SoftAP interface to the wired client interface or the wireless client interface, so that the second wireless client device obtains an IP address and connects to Internet through the wired client interface or the wireless client interface. |
| US10511374B2 |
System and method for control channel beam assumption
Described is an apparatus of an Evolved Node-B (eNB) comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to generate a reference signal transmission for an eNB Transmitting (Tx) beam corresponding with at least a first eNB antenna port having a first polarization and a second eNB antenna port having a second polarization. The second circuitry may be operable to process one or more reporting transmissions carrying at least one of a first signal reception indication for a first UE antenna port and a second signal reception indication for a second UE antenna port. The third circuitry may be operable to determine a transmission hypothesis based upon the one or more reporting transmissions. |
| US10511373B2 |
Dynamic overriding of control beam monitoring configuration
Methods, systems, and devices for wireless communication are described that support overriding a beam monitoring pattern for control channel transmissions based on channel conditions between a user equipment and a base station. A base station may select a beam monitoring pattern for transmitting control channel transmissions, which may include a pattern in which two or more beams are used for control channel transmissions. In the event that a first beam of the beams used in the beam monitoring pattern meets certain metrics, the use of one or more additional beams according to the beam monitoring pattern may be overridden and transmissions continued using the first beam. The metrics for continuing use of the first beam may include channel quality metrics, a number of consecutive successful transmissions using the first beam, one or more other metrics, or any combination thereof. |
| US10511372B2 |
System and method for channel quality reporting
An apparatus of a user equipment (UE) may include a memory and one or more processors operatively coupled to the memory device. The processors determine a reporting mode for the UE based on a message received at the UE from an eNodeB. The UE may generate a channel state information (CSI) reporting message based on the determined reporting mode. The processors may also encode extra-large physical uplink control channel (xPUCCH) data including the CSI reporting message. |
| US10511370B2 |
Method for beam management for wireless communication system with beamforming
A method of group-based beam reporting is proposed. The BS TX beams are grouped into groups to increase beam reporting efficiency. After measuring reference signals for beam management, UE reports RS quality to the network in beam groups. The beam grouping can be done either implicitly or explicitly. The grouping within the beam report is done by the UE with or without help from the network. According to principles of grouping mechanism, the grouping methods can be divided into two different categories. A first category is referred to as beam set based group, where UE groups TX beam information in a beam report based on its RX beam set(s). A second category is referred to as antenna group-based grouping, where UE groups TX beam information in a beam report based on UE antenna group. |
| US10511366B2 |
Signaling transmission method and device for multiple-input multiple-output system
A signaling transmission method and apparatus for a Multiple-Input Multiple-Output MIMO system are provided. The method includes the following steps. Channel-Related Information CRI about a combined channel is formed according to CRI between all receiving antenna ports in a receiving network and a sending antenna port in a sending network. The CRI about the combined channel is sent to the sending network. Herein, the CRI includes one or more of the following: channel information, Channel State Information CSI, and a CSI Reference Signal CSI-RS. |
| US10511359B2 |
Transmission method with double directivity
A transmission method using a massive MIMO (Multiple-Input and Multiple-Output) scheme with an arrangement 108 of Nm×Nb antenna elements at the transmitter, arranged in Nm sets of Nb antenna elements or Nb sets of Nm antenna elements based on SC-FDE (Single-Carrier with Frequency Domain Equalization) schemes with large constellations that is compatible with low-cost, highly-efficient, nonlinear amplifiers 106, while allowing spatial multiplexing gains.The transmission structure of this transmission method decomposes in 103 the modulated symbols from 102 associated to a given constellation as the sum of Nm polar components that are modulated as Nm BPSK (Binary Phase Shift Keying) signals. Each of these BPSK signals can be regarded as an OQPSK (Offset Quadrature Phase Shift Keying) signal in the serial format that is specially designed to have good tradeoffs between reduced envelope fluctuations and a compact spectrum. |
| US10511358B2 |
Beamforming for a multi-user MIMO group
During wireless communication with a multi-user multiple-input multiple-output (MIMO) group, a transmitting device may exclude a receiving device from a subset of the multi-user MIMO group to which it communicates data. In particular, based on responses from receiving devices to sounding packets with beamforming information for the receiving devices, the transmitting device calculates beam-pattern settings for a set of antennas so that, when communicating with the subset, receiving devices in the subset are located on beams within beam patterns formed by the set of antennas while a remainder of the receiving devices (including the receiving device) are located at exclusion zones in the beam patterns. Moreover, a beam pattern for a given receiving device in the subset provides a beam at a location of the given receiving device and provides exclusion zones at locations of the other receiving devices in the multi-user MIMO group. |
| US10511356B2 |
Multi-antenna network system and signal processing method thereof
A multi-antenna network system has a reduced operational complexity for matrix inversion by referring to the variations of the status of a plurality of communication channels at a first time duration and a second time duration. Therefore, the speed for calculating matrix inversion is improved. Accordingly, the amount of servo antennas and/or user antennas operating in the same multi-antenna network system can be increased. |
| US10511355B2 |
Optimized multi-beam antenna array network with an extended radio frequency range
A system, in a radio frequency (RF) transmitter device, dynamically selects one or more reflector devices along a non-line-of-sight (NLOS) radio path based on a defined criteria. Further, the dynamically selected one or more reflector devices are controlled based on one or more conditions. In an RF receiver device, communicates with the dynamically selected one or more reflector devices comprising an active reflector device. The active reflector device comprises at least a first antenna array and a second antenna array. The first antenna array transmits a first set of beams of RF signals to at least the RF transmitter device and the RF receiver device. The second antenna array receives a second set of beams of RF signals from at least the RF transmitter device and the RF receiver device. |
| US10511353B2 |
System for optimizing routing of communication between devices and resource reallocation in a network
Methods, systems, and devices for signal processing and wireless communication are described. For example, a device may include a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip may comprise a first and a second plurality of processing elements. The first plurality of processing elements may be operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements may be communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices. |
| US10511351B2 |
System and method for network uplink measurement based operation using UE centric sounding
Embodiments are provided for uplink measurement based mechanism and control using user equipment (UE) centric sounding signals. The mechanism provides an alternative to DL-measurement dominated system control. Based on UL-measurements at TPs, the network obtains knowledge of users' channel and timing information, traffic, and interference, and is thus able to perform better control, including TP and UE clustering and optimization, and power control and link adaptation. In an embodiment method, a TP receives one-to-one mapping information indicating a plurality of UE IDs and a plurality of sounding channels assigned to the corresponding UE IDs. When the TP detects a sounding reference signal (SRS) from a UE, the TP is able to identify the UE using the detected SRS and the one-to-one mapping information. The TP then obtains measurement information for the identified UE, enabling better control and communications for uplink and downlink transmissions between multiple TPs and the UE. |
| US10511349B2 |
Connector and device for wireless transmission of data and power
The present invention relates to a connector for wireless transmission of data and/or power between separate devices comprising such a connector of a system, in particular of a patient monitoring system, said separate devices comprising such a connector. The connector comprises a data transmission unit (271) arranged for transmitting data to and/or receiving data from another device of the system having a counterpart connector, a magnetic coupling unit (272) for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling, a detection unit (273) for detecting the strength of magnetic coupling between the magnetic coupling unit and a magnetic coupling unit of a counterpart connector, and a control unit (274) for switching the data transmission unit into a low-power mode and/or for enabling the magnetic coupling unit, if the detected magnetic coupling is above a first threshold and/or its increase is above a second threshold, and for switching the data transmission unit into a high-power mode and/or for disabling the magnetic coupling unit, if the detected magnetic coupling is below a third threshold and/or its decrease is above a fourth threshold. |
| US10511348B2 |
Electronic device and method for short range wireless communication in the electronic device
Disclosed are an electronic device and a method of short range wireless communication in an electronic device. The method of operating the electronic device may include: when a cover is connected to the electronic device through a short range wireless communication connection, determining generation of an event related to the cover. The method further comprises, when the event is generated, supplying power to the cover through wireless communication, when the cover is driven by the supplied power, transmitting event information to the cover through the short range wireless communication connection to display the information related to the generated event on the cover, and, when an operation of the cover according to the event is completed, switching to a standby mode after releasing the short range wireless communication connection with the cover. |
| US10511347B2 |
Device detection in contactless communication systems
A near field communication (NFC) reader is disclosed. The NFC reader includes an antenna front-end that includes a low pass filter, a matching circuit and an antenna coil. The NFC reader also includes a NFC controller. The NFC controller includes an oscillator coupled to the antenna front-end and the NFC controller is configured to detect a presence of an object in proximity of the antenna front-end using one or more changes in an output of the oscillator. The antenna front-end creates a tank circuit for the oscillator. |
| US10511346B2 |
Apparatus and methods for inducing electromagnetic waves on an uninsulated conductor
Aspects of the subject disclosure may include, receiving a plurality of communication signals, and generating, by a transmitting device according to the plurality of communication signals, a plurality of wireless signals that induces a plurality of electromagnetic waves that propagates along a pseudo dielectric layer of an uninsulated conductor. The plurality of electromagnetic waves can propagate along the pseudo dielectric layer of the uninsulated conductor without an electrical return path, each electromagnetic wave of the plurality of electromagnetic waves conveying at least a portion of the plurality of communication signals. Other embodiments are disclosed. |
| US10511341B2 |
Sterilizing enclosure for securing a portable electronic device
An enclosure for a portable electronic device includes a frame, a base, and a unitary seal. The frame includes a frame periphery edge and defines a window. A glass panel is attached to the frame adjacent the window, positioned to abut a touchscreen interface of the electronic device. The base comprises a base periphery edge. The base and the frame cooperatively define a closed position of the enclosure for securing the portable electronic device therein. The seal comprises a seal periphery edge, and is fixed to one of the base and the frame and positioned to be engaged by the other in the closed position. The seal periphery edge, the frame periphery edge and the base periphery edge are aligned in the closed position. The seal defines a boundary between a touch zone outside of the seal and a no-touch zone inside of the seal. |
| US10511340B2 |
Protection of a mobile communication device
According to an example embodiment, an arrangement is provided, the arrangement including a mobile communication device including a terminal device for wireless communication with one or more other devices via a communication channel, and a fire retardant sleeve having a shape and size that enable accommodating the mobile communication device therein, wherein at least part of the mobile communication device is enclosed within the fire retardant sleeve. |
| US10511335B2 |
Method and apparatus for adjacent band RF signal reception
A signal processing apparatus for simultaneously receiving and processing a satellite signal and a WCS signal. The system and method is operative to receive the signals, amplify and bandwidth covering both signals, splitting the amplified signal into a first and second portions, filtering the first portion to reduce the WCS signal, amplifying the first portion to amplify the satellite signal in the first portion, and processing the satellite signal in the first portion. The system and method is further operative to processing the WCS signal in the second portion. |
| US10511332B2 |
Transmitting method including bit group interleaving
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. |
| US10511330B2 |
Decoding apparatus, decoding method and program
To reduce the processing amount of a field multiplication. a denotes a k-th order vector whose elements are a0, . . . , ak−1 (a0, . . . , ak−1∈GF(xq)). A denotes an n-by-k matrix formed by vertically connecting a identity matrix and a Vandermonde matrix. b denotes an n-th order vector obtained by multiplying the vector a and the matrix A whose elements are b0, . . . , bn−1 (b0, . . . , bn−1∈GF(xq)). A vector conversion part 11 generates a ϕ-th order vector b′ using ϕ elements bp0, . . . , bpϕ−1 of the vector b. An inverse matrix generation part 12 generates a ϕ-by-ϕ inverse matrix A′−1. A plaintext computation part 13 computes elements ae0, . . . , aeϕ−1 of the vector a by multiplying the vector b′ and the inverse matrix A′−1. |
| US10511323B1 |
Loop filter initialization technique
An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator. |
| US10511321B2 |
Digital-to-analog converter and method for digital-to-analog conversion
A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12). |
| US10511319B2 |
Analog to digital converter
An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. |
| US10511314B2 |
Frequency generator and associated method
A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed. |
| US10511313B1 |
Phase-detecting method and circuit for testing a delay locked loop/delay line
A phase-detecting method for testing an under-test circuit under control of a testing station includes the steps of receiving input and output signals of the under-test circuit, combining the input and output signals with each other and accordingly generating a frequency-doubled signal, comparing the frequency-doubled signal with a reference clock signal at a same clock rate and accordingly generating a difference signal, filtering the difference signal and accordingly generating a filtered signal, and determining whether the filtered signal is in an acceptable range and accordingly report a result to the testing station. |
| US10511305B2 |
Capacitive sensing
In one embodiment, a device includes a multi-channel capacitive sensor and a control circuit. The control circuit is configured to ground a first sense capacitor and a second sense capacitor of the multi-channel capacitive sensor. The first sense capacitor and the second sense capacitor are adapted to be connected to a drive line. The control circuit is configured to charge, by a first voltage provided on a pin of the controller, an in-series combination of a sample capacitor and the first sense capacitor while not charging the second sense capacitor by the first voltage provided on the pin of the controller. The control circuit is further configured to measure a second voltage on the pin of the controller resulting at least in part from charging the in-series combination, the second voltage providing an indication of a capacitance of the first sense capacitor. |
| US10511303B2 |
Gate driver for depletion-mode transistors
The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching. |
| US10511300B2 |
Semiconductor device for radio frequency switch, radio frequency switch, and radio frequency module
Provided is a semiconductor device for radio frequency switch that includes an SOI substrate and a gate electrode. The SOI substrate includes a buried oxide film and a semiconductor layer on a carrier substrate. The gate electrode is provided on the semiconductor layer. The semiconductor layer includes a first area below the gate electrode and a second area other than the first area. A third area is provided in at least part of the second area. A fourth area is provided in at least part of the first area. The fourth area has a different thickness from a thickness of the third area. |
| US10511296B2 |
System and method for modulation and demodulation
The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects. The object can be fulfilled by the analog modulator being formed as a composite phase modulator which composite phase modulator comprises at least one feedback loop which feedback loop determines the width of a low-level discrete signal, which composite phase modulator comprises at least one feed-forward loop, which feed-forward loop determines the width of a high-level discrete signal as a function of the continuous input. Hereby it can be achieved that timing between discrete low-level and high-level forms a discontinuous output signal representing the continuous input. |
| US10511284B2 |
Resonator and related manufacturing method
A resonator may include a first dielectric member, a second dielectric member, a composite member, a first sealer, and a second sealer. The first dielectric member may have a first cavity. The second dielectric member may have a second cavity. The composite member may include a piezoelectric layer and may be positioned between the first cavity and the second cavity. The first sealer may be positioned between two portions of the first dielectric member. The first cavity may be positioned between the first sealer and the composite member. The second sealer may be positioned between two portions of the second dielectric member. The second cavity may be positioned between the second sealer and the composite member. |
| US10511283B2 |
Surface acoustic wave filter, high frequency module, and multiplexer
A surface acoustic wave filter includes resonators, wherein one of the resonator includes four or more regions with different pitches of electrode fingers, the pitch of electrode fingers in each of the four or more regions is constant, the pitch of electrode fingers in first regions, among the four or more regions, disposed at both ends of the resonator in a surface acoustic wave propagation direction is smaller than the pitch of electrode fingers in the regions other than the first regions, and the pitch of electrode fingers in a second region adjacent to the first region and the pitch of electrode fingers in a third region adjacent to the first region are different from each other. |
| US10511282B2 |
Crystal-oscillating device and manufacturing method therefor
A crystal-oscillating device is disclosed with a reduction in size and a favorable Q value. The crystal-oscillating device includes a first packaging material; a crystal resonator mounted on the first packaging material; joining members that join the first packaging material to the crystal resonator; a first sealing frame for joining the second and third packaging materials, the first packaging material, and the second packaging material; and a second sealing frame for joining the second packaging material and the third packaging material to each other. Preferable, the second packaging material is formed in a frame shape to surround an outer peripheral edge of the crystal resonator, and the second packaging material and a crystal substrate of the crystal resonator are formed from the same crystal substrate. |
| US10511279B2 |
Elastic wave device and method for manufacturing the same
An elastic wave device includes a supporting substrate, a high-acoustic-velocity film stacked on the supporting substrate and in which an acoustic velocity of a bulk wave propagating therein is higher than an acoustic velocity of an elastic wave propagating in a piezoelectric film, a low-acoustic-velocity film stacked on the high-acoustic-velocity film and in which an acoustic velocity of a bulk wave propagating therein is lower than an acoustic velocity of a bulk wave propagating in the piezoelectric film, the piezoelectric film is stacked on the low-acoustic-velocity film, and an IDT electrode stacked on a surface of the piezoelectric film. |
| US10511278B2 |
Transformer with high common-mode rejection ratio (CMRR)
Certain aspects of the present disclosure are generally directed to a structure for a balanced-unbalanced (balun) transformer. For example, certain aspects of the present disclosure provide a transformer that generally includes a first winding having a first terminal coupled to an input node and a second terminal coupled to a reference potential node. The transformer may also include a first impedance coupled between a center tap of the first winding and the reference potential node, and a second winding magnetically coupled to the first winding and having a first terminal coupled to a first differential node of a differential output pair, a second terminal coupled to a second differential node of the differential output pair, and a center tap coupled to the reference potential node. |
| US10511276B1 |
Domain-distributed cryogenic signaling amplifier
A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices. |
| US10511274B2 |
Driver circuit
A traveling wave amplifier includes two input-side lines, two output-side lines, and amplification cells. The amplification cells each include a first input terminal, a second input terminal, a first transistor including a base connected to the first input terminal and a collector connected to one output-side line, a second transistor including a base connected to the second input terminal and a collector connected to the other output-side line, a current source connected to an emitter of each of the two transistors, a first series circuit connected between the collector of the second transistor and the base of the first transistor and including a capacitor and a resistor, and a second series of circuit connected between the collector of the first transistor and the base of the second transistor and including a capacitor and a resistor. |
| US10511273B2 |
Power transfer device using an oscillator
A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node. |
| US10511266B2 |
Power amplifier control method and apparatus, and power amplifier control system
A power amplifier control method is disclosed. A phase modulation control signal may be generated according to an envelope signal that is output by a baseband unit. The phase modulation may be performed on a signal of a main power amplifier link and/or an auxiliary power amplifier link in the Doherty power amplifier circuit according to the phase modulation control signal, so that a phase difference between the signal of the main power amplifier link and the signal of the auxiliary power amplifier link after the phase modulation is a specified value corresponding to a current value of the envelope signal, where the specified value is an optimal phase value of a Doherty power amplifier circuit when the supply voltage of the Doherty power amplifier circuit is an envelope voltage corresponding to the current value of the envelope signal. High-efficiency power amplifier technology is realized. |
| US10511265B2 |
Doherty power amplifier circuit
A Doherty power amplifier circuit comprises: a power divider, a carrier amplifier subcircuit, a combiner, and a peaking amplifier subcircuit, wherein a series resonance circuit is disposed between the carrier amplifier subcircuit and the combiner. In this way, reactance that would be introduced during an operating process of a conventional Doherty power amplifier circuit can be neutralized, such that a superior performance of the Doherty power amplifier circuit is ensured, and at the same time, a load-pull effect of the Doherty power amplifier circuit is improved to have a wider bandwidth, thereby realizing a communication device supporting operations in multiple frequency bands and multiple systems at the same time, and effectively lowering manufacturing and operation costs. |
| US10511262B2 |
High speed, high voltage, amplifier output stage using linear or class D topology
Each sub-stage of an amplifier stage includes a resistor coupled to another resistor in an adjacent sub-stage or to a high DC voltage, the resistor and the other resistor forming part of a string of equal valued resistors; an FET having a source coupled to a cathode of a Zener diode coupled in parallel with a capacitor, a drain coupled to another sub-stage in the string, an output node of the amplifier stage, or the high DC voltage; and at least one active device coupled to a gate of the FET and coupled to the resistor for providing high impedance between a voltage on a node of the resistor and the gate of the FET and a low impedance between the at least one active device and the gate of the FET, the at least one active device coupled to both the cathode and an anode of the Zener diode. |
| US10511257B2 |
Photovoltaic cell having polarization characteristic and electronic device having the same
Disclosed is a photovoltaic cell including a first electrode and a second electrode having transparency and disposed facing each other, and a photovoltaic cell layer disposed between the first and second electrodes, and configured to produce electric energy by absorbing a part of incident light, wherein the photovoltaic cell layer includes a plurality of unit cells disposed in a specific distance from each other and formed with a plurality of slits for polarizing the incident light, and a transparent insulator disposed in the plurality of slits. |
| US10511253B1 |
Shingle solar module with integrated backsheet
A photovoltaic module may include a plurality of photovoltaic shingles disposed on and electrically interconnected by an integrated backsheet, to which are attached a plurality of electrically conductive shingle connectors. A plurality of photovoltaic shingles may be installed upon a roof and electrically interconnected in a single step by aligning openings in the shingles with apertures in the backsheet, simplifying module installation. The photovoltaic module may mimic the appearance of asphalt shingles and may be integrated within a roof of a house or other structure. Photovoltaic shingles or arrays of photovoltaic shingles can be pre-manufactured for easier installation or constructed at the application site. |
| US10511249B2 |
Inverter driving device, electric brake apparatus, and electric power steering apparatus
A motor driving device controls driving of an inverter device, detects current values in two phases, and compensates a value. The motor driving device detects current values in two phases, namely, a maximum phase current value and a minimum phase current value, within a single cycle of a PWM carrier frequency. The motor driving device compensates a value obtained by subtracting an absolute value of a difference between two absolute values, namely, the detected maximum phase current value and minimum phase current value, from the smaller value of the absolute values, as the offset current component. |
| US10511248B2 |
Stepping motor, motor drive device and time display device
A stepping motor includes a rotor, a stator and three coils. The rotor is two-pole magnetized in a radius direction. The stator is provided with a rotor receiving section for receiving the rotor. The three coils are magnetically connected with the stator. At least one of the three coils is an integrated coil which is integrally formed with the stator by winding a coil around a part of the stator. |
| US10511246B2 |
Initial rotor position detection device and method based on permanent-magnet synchronous motor
An initial rotor position detection device based on a permanent-magnet synchronous motor, including a host computer, a real-time simulation system, and a control system, where the real-time simulation system is connected to the control system, for determining an encoder pulse signal according to the model parameter of the permanent-magnet synchronous motor, the model parameter of the inverter, and a PWM pulse wave generated by the control system; and the control system is connected to the real-time simulation system, for using a binary search algorithm to determine an initial rotor angle of the permanent-magnet synchronous motor according to the encoder pulse signal sent by the real-time simulation system. A comprehensive closed-loop test circuit can be achieved by setting a host computer, a real-time simulation system, and a control system, and a used binary search algorithm can effectively and quickly detect an initial rotor position of a permanent-magnet synchronous motor. |
| US10511245B2 |
Apparatus and method for sensorless detection of load torque of a stepper motor and for optimizing drive current for efficient operation
A method for controlling the drive current in a stepper motor includes measuring stepper motor current, computing a load angle of the stepper motor, calculating a torque ratio of the stepper motor, generating a reference current as a function of the torque ratio and a maximum current setting for the stepper motor, and setting the drive current of the stepper motor as a function of the reference current. |
| US10511242B2 |
Method for autonomous operation of electricity-generating device
When it is not possible for a power generation device to operate coupled to an electric power system, an autonomous operation of connection and disconnection of a load of the power generation device is performed along an efficiency-characteristics curve within a speed range from a rated speed to a maximum speed in the efficiency-characteristics curve of an energy source. During the autonomous operation, an aperture command is outputted to an inlet valve of a water turbine and a first converter is operated in a converter mode when an operation preparation command is outputted by a control unit, a second converter is operated in an inverter mode when a voltage is established by of a DC linkage unit, and the load is connected when the operation preparation is completed. |
| US10511241B2 |
Motor control device and printer
A motor control device includes a motor driver and a control unit. The motor driver supplies a drive current to a stepping motor. The control unit is configured to control the motor driver to start a supply of the drive current to the stepping motor in response to a start instruction, and increase the drive current to the stepping motor from zero to a predetermined current value stepwise over a predetermined time period. |
| US10511233B2 |
Current estimating device
The voltage detection circuit (33) is a voltage divider circuit including a plurality of resistances (34a to 34c and 35a to 35c) and detects voltages (Vac1, Vac2) correlating with a power source voltage (Vin) of the AC power source (91). The calculation unit (40) obtains the across voltage (VL) of the reactor (29) using detection results (Vac1, Vac2) of the voltage detection circuit (33), and estimates a power source current (Iin) based on the across voltage (VL). The calculation unit (40) corrects gains of the detection results (Vac1, Vac2) so that a value correlating with an average value per predetermined time period of the estimated power source current (Iin) matches a value correlating with an average value per the predetermined time period of a current (Iinv) downstream of the capacitor (26), and obtains the across voltage (VL) using the detection results (Vac1, Vac2). |
| US10511228B2 |
DC-DC converting controller
A DC-DC converting controller coupled to an output stage and an external resistor network and providing a pulse-width-modulation (PWM) signal to control the output stage to provide an output voltage is disclosed. The DC-DC converting controller includes a sensing circuit, a droop current circuit, a first pin and a PWM signal control loop. The sensing circuit, coupled to the output stage, provides a sensing current. The droop current circuit, coupled to the sensing circuit, provides a droop current according to the sensing current. The first pin, coupled to the droop current circuit and external resistor network, provides the droop current to make the external resistor network provide a second reference voltage. The PWM signal control loop, coupled to the external resistor network, generates a PWM signal according to the output voltage and the second reference voltage. The droop current is reduced to a default value with a default time. |
| US10511226B1 |
Systems, methods, and apparatus for regulating a switched mode power supply
Methods, apparatus, systems, and articles of manufacture are disclosed to regulate a switched mode power supply. An example power converter includes a first comparator, a ramp generator coupled to a first input of the first comparator, and a current balance circuit coupled to the ramp generator, the current balance circuit including a transistor including a first current terminal, a second current terminal, and a gate, a multiplier circuit coupled to the first current terminal, a second comparator coupled to the gate, a first current source coupled to the first current terminal and the multiplier circuit, and a second current source coupled to the second current terminal and the second comparator. |
| US10511225B1 |
Low IQ hysteretic-PWM automated hybrid control architecture for a switching converter
A DC-DC switching converter, with a low IQ hysteretic-PWM automated hybrid control architecture, switching from a first mode to a second mode, when load current changes, is described. The DC-DC switching converter provides a simple architecture for a Boost converter, with efficiency high over the entire load range, and with a hybrid hysteretic-PWM control providing a way to automatically switch between modes, without the addition of a sensing element or system complexity. The switching converter uses a voltage comparator to detect the output current is below a certain threshold. A comparator on the error voltage detects the average value of the error signal with relation to the sawtooth signal. If the average value of the error signal is below a threshold for longer than a programmable timer, the main loop is turned off and the system goes into burst mode. |
| US10511224B2 |
Bi-directional multi-mode charge pump
Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval. |
| US10511221B2 |
System for converting a DC electric power into an AC electric power with an energy recovery module
The present invention relates to a DC/AC converter, comprising switching arms, a voltage and current variation modulation circuit, and an electrical energy harvester module. The energy recovery module is linked to the switching arms and to the modulation circuit. |
| US10511218B2 |
Gate drive circuit, that supplies power to a gate of a semiconductor switching element, and carries out a driving on and off of the gate
A gate drive circuit including a drive-on element that applies an on-state voltage to a gate of a drive target semiconductor element and a drive-off element that applies an off-state voltage to the gate is such that a recovery switch, a reactor, and a capacitor are connected in series between output terminals of the gate drive circuit as a recovery circuit that can recover a charge accumulated in input capacitance of the drive target semiconductor element when turning on, and the drive-on element, the drive-off element, and the recovery switch are controlled by a control circuit, whereby power consumption of the gate drive circuit is reduced. |
| US10511217B2 |
Magnetic clutch device
A magnetic clutch device having improved durability and reliability without increasing a size in an axial direction. A fixed member, the first engagement element, and a second engagement element are arranged concentrically to one another in order from a rotational center axis. The first engagement element comprises a first magnet. The fixed member comprises a second magnet in which a polarity is switched between a straight polarity and a reversed polarity, and a coil that switches the polarity of the second magnet depending on a direction of the current applied thereto. |
| US10511211B1 |
Trip reduction tool for a wind turbine power system
A trip reduction tool for a wind turbine power system includes a capacitor assembly configured to provide multiple capacitance levels for the power system, including e.g. a first level of capacitance during a learning phase of the tool. The tool also includes one or more processors communicatively coupled to the capacitor assembly that is configured to monitor a plurality of electrical devices of the power system for trips during the learning phase. When a trip is detected, the processor(s) collects data and determines a location of the trip. When the location of the trip is located in an electrical device that corresponds to a weak link of the power system, the processor(s) determines a second level of capacitance for the power system based on the collected data. In addition, the processor(s) provides the second level of capacitance at the weak link of the power system to reduce future trips of the electrical device. |
| US10511210B2 |
Device for the thermal management of an electric power train
A device for the thermal management of a power train includes a main housing accommodating an electric motor and its cooling circuit and a speed reducer including a lubrication circuit. The main housing includes an oil sump arranged in the lower part of the main housing and a partition separating same into two parts, wherein there are arranged respectively, on the one hand, the motor and its cooling circuit, and on the other hand, the speed reducer and its lubrication circuit, while an oil channel extends in the oil sump through the partition in order to bring the two parts into communication and includes one end on the speed reducer side provided with a valve for regulating the oil flow, controlled by the oil temperature, so as to close the oil passage in the oil channel when the oil temperature on the speed reducer side reaches a predetermined temperature threshold. |
| US10511204B2 |
Cooling fan structure with rotational cylindrical fan blades
A cooling fan structure with rotational cylindrical fan vanes includes a rotary body and multiple rotational cylindrical bodies. The rotary body includes a rotor assembly and a stator assembly corresponding to the rotor assembly for driving the rotor assembly to rotate. The rotor assembly includes a hub. The hub has a top section and a circumferential section. The rotational cylindrical bodies are rotatably disposed on the top section or the circumferential section of the hub. When the rotary body rotates, the rotational cylindrical bodies are driven by the rotary body to self-rotate. |
| US10511198B2 |
Rotary electrical machine, and rotor for rotary electrical machine
There is provided a rotor for a rotary electrical machine for improving mechanical strength of the rotor against centrifugal force. The rotary electrical machine is provided with a stator, and a rotor disposed with a gap from the stator, which has a rotor core. The rotor includes a magnet insertion hole, and a permanent magnet inserted into the magnet insertion hole. A clearance part is formed at a position of the magnet insertion hole corresponding to a corner of the inserted permanent magnet, which has a facing surface that is formed to face a surface of the permanent magnet via a gap. The facing surface of the clearance part has inflection points so that each of obtuse angles is formed by the two facing surfaces contiguous with the inflection points. |
| US10511190B2 |
Power transmission apparatus wirelessly transmitting power to power receiving apparatus
A power transmission apparatus includes a power transmission unit that wirelessly transmits power to an electronic device, a foreign substance detection unit that detects a foreign substance affecting power transmission performed by the power transmission unit, a loop shaped power transmission antenna serving as an antenna for the power transmission unit transmitting power to the electronic device, and a foreign substance detection antenna for the foreign substance detection unit detecting the foreign substance, wherein the foreign substance detection antenna is arranged at a predetermined distance or more from the power transmission antenna in a vertical direction to a loop direction of the power transmission antenna. |
| US10511183B2 |
System, apparatus and method for optimizing wireless charging via load modulation
A wireless charging system, including a power transmitter configured to generate wireless energy, and a power receiver configured to receive wireless energy at a predetermined carrier frequency that could be fixed or tuned during operation. A controller, wherein the controller is configured to activate when the power receiver receives the wireless energy. The controller may be configured to control a load modulation element to generate one or more signals containing relevant information for system operation and performance optimization, and wherein the one or more signals are transmitted via the power receiver. |
| US10511182B2 |
Viral distribution of battery management parameters
A carrier, such as a battery, that queries a memory of a charger or charging circuit, or the memory of equipment or discharging circuit powered by the battery, to determine the relative date or version of data, operating parameters and/or software on both the battery and the equipment, and either provides updated data, operating parameters and/or software to the equipment, or retrieves later dated data, operating parameters and/or software from the equipment to update the memory of the battery and/or further distribute the updated data, operating parameters and/or software to other batteries or equipment. |
| US10511175B2 |
Information processing device, information processing method, and recording medium
An information processing device receives plan necessary information relating to a first power generation device and a second power generation device having a power generation output that is more susceptible to an external environment than a power generation output of the first power generation device; and generates power generator operation plans, for the first power generation device and the second power generation device, that include a power generation curtailment plan to curtail a power generation output in the second power generation device, based on the plan necessary information and an operating cost in a power system including the first power generation device and the second power generation device; transmits a power generator operation plan for the first power generation device; and transmits a power generator operation plan including a power generation curtailment plan for the second power generation device to a device controlling or managing the second power generation device. |
| US10511174B2 |
Microinverter systems and subsystems
An alternating current (AC) module system includes branch circuits and a main service panel to receive power from the branch circuits. A photovoltaic (PV) supervisor is located between the branch circuits and the panel. The PV supervisor aggregates the power from the branch circuits. The PV supervisor also performs a nonredundant operational function for one or more of the branch circuits. The PV supervisor includes a gateway device to permit control of the operational functions. |
| US10511173B2 |
Power controller, power control method, and power control system
A power controller capable of grid interconnection of at least one distributed power source of a first type and at least one distributed power source of a second type together includes: a switch configured to switch between a parallel state in which the at least one distributed power source of the second type is interconnected to a grid together with the at least one distributed power source of the first type and a parallel off state in which the at least one distributed power source of the second type is independent of the at least one distributed power source of the first type and is paralleled off from the grid; and a controller configured to cause the switch to be in the parallel off state when reverse power flow occurs. |
| US10511172B2 |
Systems and methods for integrating distributed energy resources
The present invention is an apparatus and method for using aggregated loads from a plurality of distributed energy resources to perform a function at a power distribution feeder. The invention includes a plurality of distributed energy resources, wherein at least one distributed energy resource includes a renewable energy resource, a communication network, a control device, a power distribution feeder coupled to the control device, and an energy storage system coupled to the power distribution feeder. The control device sends a signal to the plurality of distributed energy resources via the communication network. The signal is a request to switch a status of one or more of the distributed energy resources if one or more distributed energy resources is within a predetermined condition. Loads from the one or more of the distributed energy resources that switched status are aggregated to perform a function at the power distribution feeder. |
| US10511171B2 |
Charging/discharging device and charge/discharge control method for controlling charge or discharge of an electricity storage unit
A charging/discharging device includes an electricity storage unit provided to a transport equipment, a power conversion unit that performs conversion of power exchanged between the electricity storage unit and an external power system, a reception unit that receives an instruction transmitted from a server device that decides a time at which discharge of the electricity storage unit to the power system or charge of the electricity storage unit by power supplied from the power system is performed, the instruction including the time at which the discharge or the charge is performed, and a control unit that starts up or stops based on the time indicated by the instruction received in the reception unit and controls an operation of the power conversion unit. |
| US10511169B2 |
System and method for a dynamic switchable active front end—dynamic switchable active harmonic filtering system
A System and Method for a Dynamic Switchable Active Front End—Dynamic Switchable Active Harmonic Filtering System is disclosed. |
| US10511168B2 |
Intelligent current lead device and operational methods therof
An intelligent current lead device, its design, fabrication, and methods of operation are described in this disclosure. The intelligent current lead device described in this disclosure electrically and thermally connects and disconnects one or more power sources or loads operating at one temperature reservoir with one or more machines or devices operating at either the same or a different temperature reservoir. The intelligent current lead can operate in either an active mode or passive mode. The intelligent current lead device may incorporate the use of multiple types of diagnostic sensors and instrumentation, which can be monitored, interpreted, and analyzed. The program logic of the intelligent current lead may be used to interpret the data obtained from the diagnostic sensors and instrumentation in order to adjust/actuate/switch the current lead so as to optimize its configuration to respond to requirements of an electrical load that changes with time. There are many applications that the intelligent current lead can be used in conjunction with including but not limited to: superconducting magnets, transformers, power cables, energy storage, motors, generators, fault current limiters, circuit breakers, fusion magnets, accelerator magnets, MRI magnets, NMR magnets, induction heaters, magnetic separators, among other applications. |
| US10511165B2 |
Circuit assembly for protecting a unit to be operated from a supply network against overvoltage
The invention relates to a circuit assembly for protecting a unit to be operated from a supply network against overvoltage, comprising an input having a first and a second input connection, which are connected to the supply network, an output having a first and a second output connection, to which the unit to be protected can be connected, and a protection circuit, which is provided between the first and the second input connections in order to limit the voltage present at the first and the second input connections. According to the invention, the protection circuit has a power semiconductor, in particular an IGBT, wherein a series circuit consisting of a diac, i.e., a bidirectional electrode, and a Zener element is connected between the collector and the gate of the power semiconductor, wherein the sum of the Zener voltage and the diac voltage results in a clamping voltage for the power semiconductor, which lies above the voltage of the supply network and defines the protection level. |
| US10511162B2 |
Range extender and circuit protection method
A circuit protection method comprises operating a range extender in a normal mode, wherein the range extender comprises at least one DC-to-DC converter having an input side and an output side and at least one bypass device coupled between the input side and the output side. The operating of the range extender in the normal mode comprises converting an input voltage at the input side into an output voltage at the output side by the DC-to-DC converter, wherein the output voltage is higher than a critical voltage. The method further comprises operating the range extender in a safety mode when the output voltage is lower than the critical voltage. The operating of the range extender in the safety mode comprises bypassing the DC-to-DC converter by the bypass device, wherein the critical voltage is lower than or equal to the input voltage. |
| US10511161B2 |
Diagnostic system for a DC-DC voltage converter
A diagnostic system for a DC-DC voltage converter is provided. A first temperature sensor generates a first temperature signal associated with a buck mode integrated circuit. A first analog multiplexer outputs the first temperature signal to a first analog-to-digital converter which generates a first temperature value. A second temperature sensor generates a second temperature signal associated with a boost mode integrated circuit. A second analog multiplexer outputs the second temperature signal to a second analog-to-digital converter which generates a second temperature value. A microcontroller generates control signals to command first and second bi-directional switches in the DC-DC voltage converter to each transition to an open operational state if the first temperature value is greater than a first threshold temperature value. |
| US10511148B2 |
Tunable laser device
A tunable laser device is provided. The tunable laser device includes an active layer configured to generate first light by a first source; first and second reflective layers spaced apart from each other having the active layer disposed between the first reflective layer and the second reflective layer to form a resonance cavity; and a variable refractive index unit in the resonance cavity and having a refractive index being variable according to a second source, the second source being different from the first source. |
| US10511147B2 |
Laser device and process for fabricating such a laser device
The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3). |
| US10511145B2 |
Generation of high-power spatially-restructurable spectrally-tunable beams in a multi-arm-cavity VECSEL-based laser system
A collinear T-cavity VECSEL system generating intracavity Hermite-Gaussian modes at multiple wavelengths, configured to vary each of these wavelengths individually and independently. A mode converter element and/or an astigmatic mode converter is/are aligned intracavity to reversibly convert the Gaussian modes to HG modes to Laguerre-Gaussian modes, the latter forming the system output having any of the wavelengths provided by the spectrum resulting from nonlinear frequency-mixing intracavity (including generation of UV, visible, mid-IR light). The laser system delivers Watt-level output power in tunable high-order transverse mode distribution. |
| US10511144B2 |
Semiconductor light-emitting device
The present invention comprises: a light-emitting element group configured from columns of serially connected light-emitting elements, one of the ends from each of the columns of the light-emitting elements being collectively connected to a power source; current control elements, provided to correspond to the columns, and being connected to each of the columns of the light-emitting elements at the other end thereof, for controlling the current flowing through the light-emitting elements; a forward voltage monitoring circuit for monitoring, for each of the columns, the total forward voltage across the light-emitting elements; and a control circuit for controlling the current control elements, on the basis of the total forward voltage across the light-emitting elements from each of the columns detected by the forward voltage monitoring circuit, in such a manner that the variations in the total forward voltage across the columns of the light-emitting elements reach a threshold value or lower. |
| US10511132B2 |
Clamping fixture for plug electrode
A clamping fixture for plug electrode, including an upper mold, a lower mold and at least one clamping guide block is provided. The lower mold and the upper mold can be separated from and combined with each other. The upper mold has at least one opening through which at least one plug electrode is inserted. The at least one clamping guide block is disposed between the upper mold and the lower mold for clamping and releasing the at least one plug electrode. The lower mold has an inclined surface. When the upper mold is combined with the lower mold, the upper mold pushes the clamping guide block to move toward the lower mold, and the clamping guide block is guided by the inclined surface to move for clamping the at least one plug electrode. |
| US10511128B2 |
Connector configurable for high performance
An electrical connector for high speed signals. The connector has multiple conductive elements that may serve as signal or ground conductors. A member formed with lossy material and conductive compliant members may be inserted in the connector. The conductive compliant members may be aligned with conductive elements of the connector configured as ground conductors. For a connector configured to carry differential signals, the ground conductors may separate pairs of signal conductors. The member may further include a conductive web, embedded within the lossy material, that interconnects the conductive compliant members. For a receptacle connector, the conductive elements may have mating contact portions aligned along opposing surfaces of a cavity. The conductive elements may have contact tails for attachment to a printed circuit board and intermediate portions connecting the mating contact portions and the contact tails. The conductive compliant members may press against the intermediate portions. |
| US10511127B2 |
High-speed electronic connector
Electrical connectors for connecting various computing devices include a printed circuit board with a plurality of electrical contacts, as well as a ground bar for reducing electromagnetic interference, enclosed within a housing. The counterpart female connector includes a receptacle, disposed within an outer shell and having a cavity configured to receive the connecting plug of the male connector. |
| US10511126B2 |
Movable connector
A movable connector disclosed in the present description includes: a connector having a housing; and a connector mounting part to which the housing is movably mounted. The housing is provided with at least one mounting pin constituted by a plurality of elastic pieces arranged in a circular ring, and the connector mounting part is provided with mounting recesses (mounting tubular portions) that hold the mounting pin in a state in which it is inserted into the corresponding mounting recess. The mounting pin is capable of relative movement inside the mounting recess in directions that intersect a direction in which the mounting pin is mounted into the mounting recess, and the mounting pin is provided on one or two of the outer peripheral sides of the housing. |
| US10511125B2 |
Connector having a lever
A connector comprises a wire cover and a lever pivotally attached to the wire cover. The wire cover has a cover lock and a cover biasing member. The lever is rotatable between an unmated position and a mated position. When the lever is in the mated position, the cover lock locks the lever in the mated position and the cover biasing member biases the lever toward the unmated position. |
| US10511122B2 |
Sensor arrangement for use in process automation
The present disclosure relates to a sensor arrangement for use in process automation, having a sensor, comprising a first coupling body, having at least one sensor element for detecting a measurement value of the process automation, and a first interface for transmitting a signal dependent upon the measurement value, a connection element for transmitting the signal to a superordinate unit, comprising a second coupling body complementary to the first coupling body, having a second interface complementary to the first interface, wherein the first and second interfaces are designed for bi-directional communication between sensor and superordinate unit, where the sensor has at least one light source for transducing the signal dependent upon the measurement value into light of a color corresponding to the measurement value. |
| US10511120B2 |
Cable bushing arrangement
A cable bushing arrangement for an electromotive linear actuating apparatus includes a terminal closure for a hosing of the linear actuating apparatus. The arrangement allows sealed-off routing of a cable from outside through an insertion opening in the terminal closure to a housing interior of the linear actuating apparatus. |
| US10511113B2 |
Modular plug provided with metal shielding cover, and communication cable
A modular plug includes a modular plug body and a metal shielding cover. The modular plug body has an inner chamber. The modular plug body has a first end and an opposite side end. Metal terminals are disposed at the first end. The second end defines an opening in communication with the inner chamber. The opening is configured to allow a cable to be inserted through the opening into the inner chamber. The metal shielding cover is attached around the modular plug body. The modular plug body defines a first aperture in communication with the inner chamber, and the metal shielding cover includes at least one metal spring tab capable of bending and deforming into the first aperture. The modular plug has a simple structure and ingenious design, which can easily achieve the grounding results, has a reduced cost, and is easy to promote its application. |
| US10511111B2 |
Conductor connection structure of laminated wiring body
A conductor connection structure of a laminated wiring body includes a plurality of plate wiring members which are made of a conductive material and stacked to each other, an insulating layer which is arranged between the vertically-adjacent plate wiring members to insulate the vertically-adjacent plate wiring members, a connection portion which is provided in an upper surface of each of the plate wiring members on a way in an extending direction of the plate wiring members, and a leading-out portion which takes out the connection portion of a lower plate wiring member among the plurality of plate wiring member while avoiding an upper plate wiring member among the plurality of plate wiring member, the lower plate wiring member is arranged at a layer lower than the upper plate wiring member in the laminated wiring body. |
| US10511110B2 |
Electric switchboard terminal block with multiple label-holder seats
Electric switchboard terminal block having a body (310) extending in a lengthwise longitudinal direction (X-X), widthwise transverse direction (Y-Y) and heightwise vertical direction (Z-Z), and comprising a front face (310a) and lateral flanks (310b) situated opposite each other in the longitudinal direction (X-X), each flank having a first seat (320) for housing a label (30), and comprising a recess (330) with a substantially trapezium-like vertical cross-section arranged in a central position in the longitudinal direction (X-X) and having a greater base open on the front face (310a) of the terminal block and smaller base open towards the inside thereof, said recess (330) having at least one further seat (331;333) for housing at least one additional label (30). |
| US10511108B1 |
Dual-wire connector
A dual-wire connector (1) includes: an insulation base (10), having a base plate (11) and an enclosing plate (12) formed with two insertion ports (121); an electric conductive terminal (20), fastened on the base plate (11), and having a first lateral plate (211) and a second lateral plate (212); a first electric conductive elastic sheet (30), electrically connected to the electric conductive terminal (20); a second electric conductive elastic sheet (40), separately arranged with respect to the first electric conductive elastic sheet (30), electrically connected to the electric conductive terminal (20); and a pressing member (50), moveably connected to the base plate (11) and having insertion slots (53) corresponding the two insertion ports (121) and a pushing unit (52) formed at one side of the insertion slot (53). Accordingly, the stability and the tightness while being clamped can be enhanced. |
| US10511105B2 |
Electric wire with terminal and method of manufacturing electric wire with terminal
A terminal-equipped electric wire includes a terminal and an electric wire. The terminal includes a conductor bonding part and a sheath supporting part. The electric wire includes a conductor formed of a plurality of strands and a sheath covering the conductor such that the conductor is exposed to a predetermined length. The conductor exposed from the sheath is bonded to the conductor bonding part, and the sheath is supported by the sheath supporting part and is fixed in the terminal. The sheath supporting part is in a state where there is no permanent distortion with respect to a state when the terminal is present alone. |
| US10511104B2 |
Solderable electric connection element
The invention relates to a solderable electric connection element including a crimping portion for receiving a connection cable and a soldering portion for bonding to the surface of an electrically conductive structure. The soldering portion directly adjoins the crimping portion or is offset therefrom by means of a transition portion, and a solder deposit is provided or can be placed on the solder region. According to the invention, an angled section is formed in the section between the crimping and soldering region or in the transition region such that the crimping and soldering region are arranged in a back-to-back position, wherein the free face of the soldering region receives the solder deposit. |
| US10511102B2 |
Feeder circuit
A feeder circuit includes: a first line 103 having first and second ends; a second line 104 having first and second ends; a third line 105 having first and second ends; a first combiner 101 configured to combine signals output from the second ends of the first and second lines 103 and 104; a first coupling portion 115 configured to electrically couple portions of the first and third lines to each other; and a second coupling portion 116 configured to electrically couple portions of the second and third lines to each other in a manner that allows a signal reaching the first combiner from the first end of the third line through the first coupling portion and a signal reaching the first combiner from the first end of the third line through the second coupling portion, to be cancelled out. |
| US10511099B2 |
Dual-band shaped-pattern quadrifilar helix antenna
A compact dual-band air core helix antenna may include two sets of quadrifilar helix antenna elements with each of the antenna elements having different arm lengths. The helix antenna may be configured such that the antenna elements are printed on a foldable printed circuit board. Radiating elements of the antenna elements may be fed with four inputs and each of the four inputs may have a same amplitude and quadrature phase difference (e.g., 0, 90, 180, 270 degree phase shifts). |
| US10511098B2 |
Antennas
An antenna includes a metal tube, a coaxial cable disposed along a central axis of the metal tube, and a variable-impedance transmission wire structure. A dielectric body and a metal part are arranged along an axial direction of the cable. The antenna makes the resulting structure stable and reliable, achieves miniaturization of a multi-band antenna and provides a sufficiently wide bandwidth for each frequency band. The antenna also realizes easy control of the radiation pattern and is convenient for practical applications. |
| US10511096B2 |
Low cost dielectric for electrical transmission and antenna using same
A transmission conduit for RF signal, comprising: a dielectric plate; a conductive circuit positioned on one surface of the dielectric plate; a conductive ground positioned on opposite surface of the dielectric plate; wherein the dielectric plate comprises a sandwich of at least one high-dielectric constant layer and one foam plate. The dielectric plate can be made of a sandwich of glass and foam plate, such as Rohacell®. The glass and foam plates have thickness calculated to give the sandwich the required overall dialectic constant. |
| US10511094B2 |
Antenna assembly for a communication system
A communication system includes an antenna assembly and a housing holding the antenna assembly. The antenna assembly has an antenna element having a substrate and a dual dipole antenna circuit including a low-band ground terminal, a low-band feed terminal, a high-band ground terminal and a high-band feed terminal and a transmission line electrically connected to the dual dipole antenna circuit. The housing includes an upper shell and a lower shell meeting at an interface having upper and lower strain relief components at the interface to receive the transmission line. The upper shell has an upper locating feature and the lower shell has a lower locating feature interfacing to locate the upper shell relative to the lower shell. |
| US10511090B2 |
Wireless telecommunication antenna mount and control system
A remotely controllable antenna mount for use with a wireless telecommunication antenna provides mechanical azimuth and tilt adjustment using AISG compatible motor control units and AISG control and monitoring systems to remotely adjust the physical orientation of the antenna. The mount control units are serially interconnected with AISG antenna control units (ACUs) which adjust electronic tilt mechanisms within the antenna itself. An AISG compatible mount azimuth control unit (MACU) drives rotatable movement of the antenna through a range of azimuth angle positions. The antenna mount further includes a mechanical downtilt assembly interconnected between the antenna interface and the antenna. An AISG compatible mount tilt control unit (MTCU) drives linear expansion of a scissor assembly and corresponding pivoting of the antenna through a range of tilt angle positions. |
| US10511088B2 |
Antenna system
The present invention relates to the field of communications technologies and discloses an antenna system, and the antenna system includes: a radiating element, at least one strip line ground plane and signal cavity, and at least one inner conductor, where the radiating element includes radiation arms, radiation baluns, and feeding inner cores; the strip line ground plane is used as a reflective surface of the radiating element; the baluns of the radiating element are electrically connected to the strip line ground plane, and all of at least two feeding inner cores of the radiating element are electrically connected to one inner conductor. Therefore, a feeding manner of an existing array antenna can be optimized very conveniently, assembly time is greatly reduced, quantities of welding points and cables are reduced, and consistency and reliability are improved. |
| US10511079B2 |
Electronic device and antenna structure thereof
An antenna structure including a conductive housing, a substrate, a ground element and a radiation element is provided. The conductive housing includes an open slot and a conductive segment adjacent to each other. The radiation element is disposed on a first surface of the substrate and is electrically connected to the ground element. A second surface of the substrate faces the open slot and the conductive segment. The ground element is electrically connected to the conductive housing. The radiation element has a feeding point and forms a first path. An orthogonal projection of the radiation element on the conductive housing is partially overlapping with the conductive segment such that the conductive housing and the radiation element form a second path. The antenna structure operates in a first band and a second band through the first path and the second path. |
| US10511075B2 |
Integrated fan-out package including dielectric waveguide
A semiconductor structure is disclosed that includes a dielectric waveguide, a first transmission electrode and a second transmission electrode, and a first receiver electrode and a second receiver electrode. The first transmission electrode and the second transmission electrode that are disposed over and below the dielectric waveguide, respectively, and the first transmission electrode and the second transmission electrode are symmetric with respect to the dielectric waveguide. The first receiver electrode and a second receiver electrode that are disposed over and below the dielectric waveguide, respectively, and the first receiver electrode and the second receiver electrode are symmetric with respect to the dielectric waveguide. The dielectric waveguide is configured to receive a transmission signal from a driver circuit through the first transmission electrode and to transmit the received transmission signal to a receiver circuit through the first receiver electrode. |
| US10511074B2 |
Higher signal isolation solutions for printed circuit board mounted antenna and waveguide interface
Higher isolation solutions for printed circuit board mounted antenna and waveguide interfaces are provided herein. An example device includes any of a dielectric substrate or transmission line, an antenna mounted onto the dielectric substrate, and an elongated waveguide mounted onto the dielectric substrate so as to enclose around a periphery of the antenna and contain radiation produced by the antenna along a path that is coaxial with a centerline of the waveguide, the elongated waveguide having a first cross sectional area and a second cross sectional area, and the first cross sectional area differs from the second cross sectional area. |
| US10511071B2 |
Low-loss, low-profile digital-analog phase shifter
A phase shifter having both digital and analog shifting components is disclosed. The digital-analog phase shifter includes an input/output port configured, in part, for receiving an input radio frequency (RF) signal from an external source and outputting a phase shifted RF signal. A digital shifter performs coarse phase shifts of the input RF signal, while an analog shifter variably shift the phase of the input RF signal relative to the coarse phase shift. This produces a phase shifted RF signal having a total phase range that is output is continuously variable from 0° to 360°. |
| US10511070B2 |
Cooling plate for weight lightening, battery module comprising the same and method for manufacturing the same
Provided is a cooling plate having excellent cooling performance and a low weight, a battery module including the same, and a method for manufacturing the same. The cooling plate is interposed between a cooling unit that is in thermal contact with battery cells on at least one surface of a stack of battery cells and the battery cells, and includes a metal plating layer on the surface of a substrate made of a synthetic resin. |
| US10511069B2 |
Battery
The invention relates to a battery having a cell arrangement. The cell arrangement has a plurality of battery cells. The cell arrangement has battery sections, each including a battery cells. Between adjacent battery sections, an at least partially electrically and thermally conductive contacting section element having a first side and a second side is arranged. The end terminals facing the first side of a contacting section element are electrically and thermally conductively connected to a contacting section of this first side. The end terminals facing the second side of the contacting section element are electrically and thermally conductively connected to a contacting section of this second side. End terminals of the battery cells are electrically and thermally conductively connected to each other via the contacting section element such that an electric current and a heat flow are distributed throughout the entire cell assembly. |
| US10511067B2 |
System and method to divert inductive energy from cells
A power tool/battery pack combination includes an electric motor, one or more electrochemical cells, and a capacitive element. The electric motor is connected in series to a first switch. The series combination of the electric motor and the first switch is connected to a first terminal and a second terminal. The one or more electrochemical cells are connected across a third terminal and a fourth terminal. The third terminal and the fourth terminal are coupled respectively to the first terminal and the second terminal. The one or more electrochemical cells supply power to the electric motor via the first switch. The capacitive element includes one or more capacitors. The capacitive element is connected across the third terminal and the fourth terminal. The capacitive element is capable of storing inductive energy generated by the one or more electrochemical cells. |
| US10511059B1 |
Alkaline pouch cell with coated terminals
A battery cell includes an electrode assembly having a negative electrode, positive electrode, and separator bathed in an alkaline electrolyte, a pouch encapsulating the electrode assembly, and first and second tabs respectively extending from the positive and negative electrodes through the pouch. The first tab has thereon a coating including acrylic paint and the second tab has thereon a coating including lacquer to discourage creepage of the alkaline electrolyte along the first and second tabs and out of the pouch. |
| US10511057B2 |
Non-aqueous electrolyte secondary battery and a method for producing the same
Provided is a method for producing a non-aqueous electrolyte secondary battery with which resistance increase is inhibited during high-temperature storage while good battery properties are retained. The production method of this invention comprises a step of obtaining a positive electrode, a negative electrode and a non-aqueous electrolyte; and a step of placing the positive electrode, the negative electrode and the non-aqueous electrolyte in a battery case. Herein, the non-aqueous electrolyte comprises a fluorine atom-containing supporting salt and a benzothiophene oxide. |
| US10511055B2 |
Metal plating-based electrical energy storage cell
The present disclosure provides an electrochemical storage cell including a battery. The battery includes an alkali metal anode having an anode Fermi energy, an electronically insulating, amorphous, dried solid electrolyte able to conduct alkali metal, having the general formula A3-xHxOX, in which 0≤x≤1, A is the alkali metal, and X is at least one halide, and a cathode including a cathode current collector having a cathode Fermi energy lower than the anode Fermi energy. During operation of the electrochemical storage cell, the alkali metal plates dendrite-free from the solid electrolyte onto the alkali metal anode. Also during operation of the electrochemical storage cell, the alkali metal further plates on the cathode current collector. |
| US10511053B2 |
Solid electrolyte having magnesium ion conductivity and magnesium secondary battery using the same
A solid electrolyte has a composition represented by the formula: MgxSiOyNz, where 1 |
| US10511052B2 |
Electrolyte sheet
An electrolyte sheet including an electrolyte layer that includes electrolyte particles and a binder, and a base material stacked on the electrolyte layer, wherein the electrolyte particles have an ionic conductivity of 1.0×10−5 S/cm or more; the ratio of the electrolyte particles relative to the total weight of the electrolyte particles and the binder is 50 wt % or more and 99.5 wt % or less; and, after transferring the electrolyte layer in a transfer test, the electrolyte particles and the binder do not remain on the base material, and the electrolyte layer is transferred to an object without peeling. |
| US10511048B2 |
Method of preparing negative electrode active material for lithium secondary battery and lithium secondary battery using the same
The present invention relates to a method of preparing a negative electrode active material for a secondary battery which may prevent oxidation during the preparation of nano-sized silicon particles, a negative electrode active material for a secondary battery prepared thereby, and a negative electrode for a secondary battery and a lithium secondary battery including the same. |
| US10511046B2 |
Fuel cell assembling method and fuel cell assembling apparatus
A fuel cell assembling apparatus includes: a tensile load application device that pulls a coupling plate to apply a tensile load to the coupling plate of which a first end portion is fixed to a first end plate, the tensile load application device being temporarily fixed to a second end portion of the coupling plate; a compressive load application device that applies a compressive load to a cell stack of a fuel cell; and a fixing device that fixes the second end portion of the coupling plate to which the tensile load is applied, and a second end plate to each other. The tensile load application device applies the tensile load to the coupling plate by using a reaction force generated in response to the compressive load applied to the cell stack by the compressive load application device. |
| US10511037B2 |
Apparatus for removing moisture of stack enclosure
An apparatus for removing moisture of a stack enclosure includes a protective case accommodating a fuel cell stack therein, a radiation heater mounted at a lower surface of the protective case, the radiation heater enabling discharged air to move toward an upper part of the protective case, and a cooler for cooling air moving along the upper part of the protective case, the cooler guiding cooled air to move toward the lower surface of the protective case. |
| US10511033B2 |
Solid oxide fuel cell
An interconnector made of a lanthanum chromite is provided on a fuel electrode of an SOFC, and a P-type semiconductor film which is a conductive ceramics film is formed on a surface of the interconnector. When a maximum value (maximum joining width) of the “lengths of a plurality of portions at which the interconnector and the P-type semiconductor film are brought into contact with each other” on a “line (boundary line) corresponding to an interface between the interconnector and the P-type semiconductor film in a cross section including the interconnector and the P-type semiconductor film” is 40 μm or less, peeling becomes less liable to occur in a portion corresponding to the maximum joining width at the interface. |
| US10511030B2 |
Anti-corrosion structure and fuel cell employing the same
An anti-corrosion structure and a fuel cell employing the same are provided. The anti-corrosion structure includes an aluminum layer, a first anti-corrosion layer, and an intermediate layer disposed between the aluminum layer and the first anti-corrosion layer. In particular, the first anti-corrosion layer can be a nickel-tin-containing alloy layer, and the intermediate layer can be a nickel-tin-aluminum-containing alloy layer. |
| US10511025B2 |
Electrode manufacturing method
Disclosed is a method for manufacturing an electrode by forming an electrode mixture layer on a surface of a current collector using an electrode mixture composition containing an aqueous polyimide precursor solution composition and a specific crosslinking agent, the aqueous polyimide precursor solution composition being obtained by dissolving a specific polyamide acid in an aqueous solvent together with a specific imidazole, and subsequently performing heat treatment to remove the solvent and perform an imidization reaction of the polyamide acid. It is preferable that the imidazole is an imidazole selected from the group consisting of 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 4-ethyl-2-methylimidazole, and 1-methyl-4-ethylimidazole. |
| US10511020B2 |
Nickel composite hydroxide particle and process for producing the same, positive electrode active material for non-aqueous electrolyte secondary battery and process for producing the same, and non-aqueous electrolyte secondary battery
An objective of the present invention is to provide a non-aqueous electrolyte secondary battery positive electrode active material formed from a lithium-nickel composite oxide which, while retaining high capacity and a high level of safety, has an excellent cycle characteristic by controlling reaction resistance and a method for producing it. [Solution] A lithium-nickel composite oxide is produced by steps (a) to (c) described below: (a) nickel hydroxide and/or nickel oxyhydroxide in a prescribed composition are sintered in a non-reducing atmosphere having 850° C. or lower to give nickel oxide; (b) after the nickel oxide and a lithium compound are mixed in a prescribed molar ratio, the mixture is sintered in an oxygen atmosphere at a temperature of 650 to 850° C.; and (c) after an obtained powder is made to be in a prescribed slurry concentration, it is washed with water during a period of time which satisfies the following formula: B/40 |
| US10511019B2 |
Electrode solutions and electrochemical cells and batteries therefrom
The present disclosure relates to liquid solutions which include particulates that can function as an electrode, thereby forming an electrode solution, useful in the fabrication of liquid flow electrochemical cells and liquid flow batteries. The electrode solutions of the present disclosure may include an electrolyte comprising a liquid medium and at least one redox active specie, wherein the electrolyte has a density, De; and a core-shell particulate (202, 204) having a core, a shell and a density Dp, wherein at least a portion of the shell of the core-shell particulate includes an electrically conductive first metal and wherein 0.8De≤Dp≤1.2De; and wherein a first redox active specie of the at least one redox active specie and the electrically conductive first metal are different elements. The present disclosure also provides electrochemical cells and liquid flow batteries comprising an electrode solution according to the present disclosure. |
| US10511017B2 |
Hollow carbon nanosphere composite based secondary cell electrodes
The present disclosure relates to composites of hollow carbon nanospheres (HCNS) and a metal, a metalloid, an alloy, a compound thereof, or any combination of the foregoing, and the use of such composites for making ion storage materials, such as negative electrode active material for lithium ion batteries. |
| US10511011B2 |
Electrolyte impregnation apparatus
The present invention relates to an electrolyte impregnation apparatus comprising: a pressing unit comprising a pressing plate that presses a battery cell in which an electrode assembly and an electrolyte are accommodated; and an ultrasonic vibration unit installed to a portion or the whole of the pressing plate to apply ultrasonic vibration to the battery cell. |
| US10511003B2 |
Separator for batteries and method for manufacturing the same
A separator which is permeable to hydroxide ion contains at least one Dendrite Stopping Substance such as Ni(OH)2, or its precursor. |
| US10510996B2 |
Battery
According to the present invention, grip feeling of an electronic device to which the battery is mounted may be improved by optimizing a shape of a battery, and miniaturization of the electronic device may be promoted at the same time. In order to achieve the above-described object, a battery is disclosed, the battery including: a first surface having a circumference of a closed curve having a curve; a second surface having a circumference of a closed curve having a curve; and a volume portion configured to connect the first surface to the second surface and defining a volume, wherein at least one of the first surface and the second surface has a circumference of the closed curve defined by connecting ends of each of two curves curved in the same direction to each other, and the first surface has an area different from that of the second surface. |
| US10510995B1 |
Film formation method and method of manufacturing display device using the same
A film formation method of introducing, into a film formation chamber, a vaporized material obtained by vaporizing a liquid-form organic material in a vaporizing chamber and forming a vapor deposition film composed of the vaporized material on a surface of a film formed substrate placed within the film formation chamber. The method includes: holding an internal temperature of the vaporizing chamber at a lower temperature than a reaction temperature at which the organic material polymerizes; holding an internal pressure of the vaporizing chamber at a saturated vapor pressure of the organic material; setting an internal temperature of the film formation chamber to the same temperature as the internal temperature of the vaporizing chamber; and forming the film in a state where the film formed substrate is held at a temperature lower than the internal temperature of the film formation chamber. |
| US10510992B2 |
Method for manufacturing light-emitting device
A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal. |
| US10510991B2 |
Mask structure for pixel layout of OLED panel, OLED panel and method for manufacturing the same
Embodiments of the present disclosure relate to a mask structure for pixel layout of an OLED panel, an OLED panel and a method for manufacturing the same. The mask structure for pixel layout of an OLED panel comprises: a deposition mask patterned on a substrate and surrounding each pixel region, the deposition mask comprising a first deposition wall and a second deposition wall arranged oppositely in pairs in a first direction, a third deposition wall and a fourth deposition wall arranged oppositely in pairs in a second direction intersecting the first direction, as well as a fifth deposition wall and a sixth deposition wall arranged oppositely in pairs in the first direction. The pixel layout comprises a first sub-pixel region adjacent to the second deposition wall, a second sub-pixel region adjacent to the first deposition wall, and a third sub-pixel region adjacent to the fourth deposition wall. |
| US10510990B2 |
Groove structure for printing OLED display and manufacturing method for OLED display
The invention provides a groove structure for printing OLED display and manufacturing method for OLED display. By dividing the causeway surrounding the groove into a first and a second branch causeway layers provided in stack, the inclining inner peripheral surface of groove formed by first branch causeway forms a contact angle ranging 10-45° with the HIL ink, and the inclining inner peripheral surface of groove formed by second branch causeway forms a contact angle ranging 30-60° with the HIL ink, the inclining inner peripheral surface of groove formed by second branch causeway forms a contact angle ranging 10-45° with HTL ink and EML ink to restrict the height of HIL climbing upwards so that the top surface of HIL is flat or has a slightly convex in the middle to prevent current leakage at the edge of HIL, and improve the OLED display quality. |
| US10510989B2 |
Electroluminescent device
An organic EL display device includes a flexible base and an organic EL element (electroluminescent element) provided on the base, and further includes an adjustment layer that has heat dissipating properties and that adjusts a neutral surface of the organic EL display device. The adjustment layer is provided on the organic EL element side relative to the center of the whole organic EL display device in the film thickness direction. |
| US10510981B2 |
Organic light-emitting diode display panel, fabrication method, and electronic apparatus
An organic light-emitting diode (OLED) display panel, a fabrication method thereof, and an electronic apparatus including the OLED display panel are provided. The OLED display panel comprises: a substrate, an organic light-emitting device, and a capping layer. A material of the capping layer includes a compound of a chemical formula (I), L1, L2, L3, and L4 are independently selected from a hydrogen atom, a substituted or -unsubstituted alkyl, a substituted or unsubstituted alkenyl, a substituted or unsubstituted alkynyl, and a substituted or unsubstituted phenyl. A total quantity of benzene rings included in L1, L2, L3, and L4 is from 0 to 6. Y1, Y2, Y3, Y4, Y5, and Y6 are independently selected from a hydrogen atom, a substituted or unsubstituted alkyl, a substituted of unsubstituted alkenyl, and a substituted or unsubstituted alkynyl. |
| US10510979B2 |
Composite transparent electrode, OLED and method for manufacturing thereof, array substrate and display device
A composite transparent electrode, an organic light-emitting diode and a method for manufacturing thereof, an array substrate and a display device. In the composite transparent electrode, a cover layer (12) is provided between a metal layer (11) and a transparent conducting oxide layer (13), the transparent conducting oxide layer (13) is electrically connected to the metal layer (11). The composite transparent electrode can reduce damages to the metal layer (11) or decrease pressure fall during a sputtering process. |
| US10510971B2 |
Vapor-deposited nanoscale ionic liquid gels as gate insulators for low-voltage high-speed thin film transistors
Described are materials and methods for fabricating low-voltage MHz ion-gel-gated thin film transistor devices using patternable defect-free ionic liquid gels. Ionic liquid gels made by the initiated chemical vapor deposition methods described herein exhibit a capacitance of about 1 μF cm−2 at about 1 MHz, and can be as thin as about 20 nm to about 400 nm. |
| US10510969B2 |
Display device having a pixel including semiconductor layers having different semiconductor materials
A display device having an improved display characteristics and reduced manufacturing cost is provided. The display device includes a plurality of pixels arranged on a surface of a substrate. The plurality of pixels each include: a light-emitting element; a driving transistor; a selecting transistor; and a retention capacitor. The driving transistor has a bottom-gate structure. The driving transistor has a semiconductor layer containing a first semiconductor. The retention capacitor has a first electrode and a second electrode. The first electrode doubles as a gate of the driving transistor. The second electrode is disposed at a lower layer than the first electrode and contains a second semiconductor. |
| US10510965B2 |
Composition for forming organic semiconductor film, organic thin film transistor, electronic paper, and display device
A composition for forming an organic semiconductor film that is excellent in printing properties makes it possible to prepare an organic thin film transistor excellent in mobility and insulation reliability. The composition may be used with an organic thin film transistor, electronic paper, and a display device. The composition for forming an organic semiconductor film contains an organic semiconductor material, a phenolic reductant, a polymer compound having a weight-average molecular weight of equal to or greater than 500,000, a surfactant, and an organic solvent having a standard boiling point of equal to or higher than 150° C. A ratio of a content of the organic semiconductor material to a content of the polymer compound is 0.02 to 10 based on mass, and a ratio of a content of the phenolic reductant to the content of the polymer compound is 0.1 to 5 based on mass. |
| US10510963B2 |
Heterocyclic compound and organic light-emitting element comprising same
The present specification provides a hetero-cyclic compound and an organic light emitting device comprising the same. |
| US10510962B2 |
Compound and organic electronic device using the same
The present specification relates to a novel compound and an organic electronic device using the same. |
| US10510959B2 |
Commissioning method and vapor deposition machine
The present invention discloses a commissioning method and a vapor deposition machine, the method is used for adjusting the relative position of a precision mask plate and a substrate to be operated, which comprises: loading a commissioning substrate into a vapor deposition chamber for commissioning; loading a precision mask plate into the vapor deposition chamber for commissioning; turning on the light source in the vapor deposition chamber for commissioning, and irradiating the photochromic layer on the commissioning substrate via the precision mask plate, wherein a partial position of the irradiated photochromic layer is discolored; obtaining a compensation value of the precision mask plate by the location of a partial discolored position of the photochromic layer. The method is possible to omit the organic materials during the commissioning process, and increase the commissioning speed. |
| US10510958B2 |
Mask frame, mask and method for manufacturing the same
A mask frame, a mask body, a mask and a method for manufacturing the same are provided in the embodiments of the disclosure. The mask frame includes a loop shaped frame body comprising an outer boundary and an inner boundary, the inner boundary defining a space for receiving a mask body. The mask frame also includes a forced side and a non-forced side, the forced side being subjected to a pulling force of the mask body, the non-forced side being free from the force of the mask body. A width between the outer boundary of the forced side of the mask frame and the inner boundary corresponding to the outer boundary decreases gradually in a direction from a middle position on the forced side toward the non-forced side. |
| US10510956B2 |
Coupled quantum dot memristor
The present disclosure relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect, the disclosure provides a quantum memristor, including a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein the source electrode and the drain electrode are coupled via quantum tunneling to QD1 and the bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode. |
| US10510955B2 |
Phase change memory
A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element. |
| US10510952B2 |
Storage device with composite spacer and method for manufacturing the same
A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch. |
| US10510948B2 |
Magnetoresistive effect element, magnetic memory, magnetization rotation method, and spin current magnetization rotational element
This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected. |
| US10510944B2 |
Vibration actuator reduced in cost and size, and electronic device
A vibration actuator can be reduced in manufacturing cost and size thereof without using a magnet. An elastic body of a vibration element includes a base portion joined to an electromechanical energy conversion element, and a pair of contact portions extending from the base portion. The contact portions are brought into pressure contact with a driven element, by elastic deformation, in a third direction orthogonal to both of a first direction of relative motion of the vibration element and the driven element and a second direction as a thickness direction of the conversion element. When driving vibration is excited in the vibration element by applying a predetermined AC voltage to the conversion element, the contact portions apply frictional driving forces to the driven element, for moving the vibration element and the driven element relative to each other in the first direction. |
| US10510942B2 |
Process for manufacturing a Josephson junction and associated Josephson junction
The invention relates to a method for manufacturing a Josephson junction comprising a step for providing a substrate, extending along a longitudinal direction, a step for depositing a superconducting layer on the substrate so that this layer extends from the substrate in a transverse direction, perpendicular to the longitudinal direction, and a step for irradiation of ions in a central area of the layer defined in the longitudinal direction, the method being characterized in that it includes, prior to the irradiation step, a step for removing a portion of the central area of the superconducting layer so as to delimit a set of areas of the superconducting layer aligned in the longitudinal direction including the central area and two lateral areas. |
| US10510932B2 |
Optoelectronic modules including optoelectronic device subassemblies and methods of manufacturing the same
The present disclosure describes wafer-level processes for fabricating optoelectronic device subassemblies that can be mounted, for example, to a circuit substrate, such as a flexible cable or printed circuit board, and integrated into optoelectronic modules that include one or more optical subassemblies stacked over the optoelectronic device subassembly. The optoelectronic device subassembly can be mounted onto the circuit substrate using solder reflow technology even if the optical subassemblies are composed of materials that are not reflow compatible. |
| US10510931B2 |
Side-view light emitting diode package structure
A narrower LED package structure with sideways output of light suitable for a light guide plate includes two first electrodes, a package body, a cover layer, and two second electrodes. The LED chip is mounted on the first electrodes. The package body encapsulates the first electrodes, and surrounds the LED chip to define a light emitting region. The cover layer infills the light emitting region and covers the LED chip. The second electrodes are positioned outside the package body. Along a plane parallel to the first electrodes, a surface area of the two second electrodes is greater than a surface area of the portion of the two first electrodes positioned in the light emitting region. |
| US10510930B2 |
Light emitting device
A light-emitting device includes: a package made of a metal material and defining a recess, the package comprising a side wall defining a side of the recess; a plurality of light-emitting elements disposed in the recess; and a cover member disposed so as to close an opening of the recess, the cover member including: a light-transmitting member having a primary surface, a ceramic member having a loop-shape and having a first surface and a second surface opposite the first surface, the first surface bonded to the primary surface of the light-transmitting member via a bonding material, and a metal member having a loop-shape and including: a first portion bonded to the second surface of the ceramic member, and a second portion located outward of the first portion in a plan view and joined to an upper surface of the side wall of the package. |
| US10510929B2 |
Light emitting device and light emitting device package
Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode. |
| US10510923B2 |
Display device and method of manufacturing the same
Disclosed are a display device and a method of manufacturing a display device. The method of a display device according to an exemplary embodiment of the present disclosure includes: a first transferring step of transferring a plurality of LEDs disposed on a wafer onto a plurality of donors; and a second transferring step of transferring the plurality of LEDs transferred onto the plurality of donors onto a display panel, in which in the second transferring step, an area where one of the plurality of donors overlaps the display panel partially overlaps an area where the other one of the plurality of donors overlaps the display panel. Therefore, the plurality of LEDs having different wavelengths is uniformly transferred to reduce a boundary caused by the difference in wavelengths and improve color uniformity. |
| US10510922B2 |
Group III-V quantum dot and manufacturing method thereof
Embodiments disclosed herein relate to group III-V QDs and manufacturing methods thereof. More specifically, the embodiments disclosed herein relate to group III-V QDs that have at least one shell of a group II-VI compound surrounding the group III-V QD core. Thus, the QDs disclosed herein are core/shell QDs and in some embodiments may be a core/shell/shell QD. For example, the group III-V QD core material may be surrounded by a shell of a group II-VI compound, which itself may be surrounded by a shell of a group II-VI compound. |
| US10510921B2 |
Graphene display
A graphene display is provided. The graphene display includes a first graphene light-emitting unit and a second graphene light-emitting unit, which are stacked and overlapped, and a metal shield layer disposed between the first graphene light-emitting unit and the second graphene light-emitting unit. The graphene display is simple in structure, and the colors of the emitted light at the two sides will not change because of the electric field of the gate electrode pattern so as to have more stable color and color reproduction. |
| US10510920B2 |
Silanized ITO electrode with ITO nanoparticles for aqueous sulfide detection
A silanized ITO electrode modified with ITO nanoparticles is described. ITO nanoparticles of cubic and semispherical shapes are immobilized on a silanized ITO film. The electrode may be used in an electrolytic cell to detect aqueous sulfide with a 0.5-1.4 μM limit of detection. The electrode shows high specificity towards aqueous sulfide and a high reproducibility in measurement. |
| US10510919B2 |
Method for enhancing the efficiency of a solar module by subjecting it to extremely-low-freqency EMR
The present invention provides a method for enhancing the efficiency of a photovoltaic module by subjecting it to extremely-low-frequency (ELF) electromagnetic radiation (EMR). The ELF EMR can be provided by a plurality of identical Jacob's ladders and the traveling arcs generated thereby. Alternatively, the ELF EMR can be provided by passing the photovoltaic module over an array of quartz discharge tubes in which arcs are generated between pairs of tungsten electrodes. The photovoltaic module is subjected to multiple passes in order to provide an optimum level of enhancement to the module. |
| US10510918B2 |
Endoscope imaging module
An endoscope includes: an imaging device chip having a chip connection portion; a tubular housing tube used to a scope tip portion of an endoscope; a substrate to which the imaging device chip is fixed, the substrate having a substrate connection portion, the substrate being capable of bending at near the substrate connection portion when the substrate is inserted into the housing tube; a lead wire connecting the substrate connection portion and the chip connection portion; flexible and non-conductive resin covering an entirety of the lead wire; and an imaging module including the substrate provided with the imaging device chip thereon, the imaging module inserted into the housing tube. |
| US10510914B2 |
Transparent energy-harvesting devices
A transparent luminescent solar concentrator is provided. The transparent luminescent solar concentrator has luminophores embedded within a waveguide matrix that both selectively absorb and emit near-infrared light to an edge mounted or embedded solar photovoltaic array. |
| US10510912B2 |
Image sensor device and method
A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. |
| US10510908B2 |
Solar cell panel
A solar cell panel includes a first solar cell and a second solar cell; and a plurality of leads connecting the first solar cell and the second solar cell. Each of the first solar cell and the second solar cell includes: a first electrode including a plurality of finger lines in a first direction and a plurality of first bus bars in a second direction crossing the first direction; and a second electrode including a plurality of second bus bars in the second direction. The plurality of leads have a diameter or width of 100 to 500 μm, and include 6 or more leads arranged at one surface side of the first or second solar cell. The plurality of leads are connected to the plurality of first bus bars of the first solar cell and the plurality of second bus bars of the second solar cell by a solder layer, respectively. |
| US10510903B2 |
Impact ionization semiconductor device and manufacturing method thereof
A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer. |
| US10510895B2 |
Device and method of dielectric layer
A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material. |
| US10510894B2 |
Isolation structure having different distances to adjacent FinFET devices
A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device. |
| US10510891B1 |
Field effect transistor contact with reduced contact resistance using implantation process
Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process. |
| US10510888B2 |
Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region. |
| US10510887B2 |
Method for fabricating a strained structure and structure formed
A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer. |
| US10510886B2 |
Method of providing reacted metal source-drain stressors for tensile channel stress
A method provides a source-drain stressor for a semiconductor device including source and drain regions. Recesses are formed in the source and drain regions. An insulating layer covers the source and drain regions. The recesses extend through the insulating layer above the source and drain regions. An intimate mixture layer of materials A and B is provided. Portions of the intimate mixture layer are in the recesses. The portions of the intimate mixture layer have a height and a width. The height divided by the width is greater than three. A top surface of the portions of the intimate mixture layer in the recesses is free. The intimate mixture layer is reacted to form a reacted intimate mixture layer including a compound AxBy. The compound AxBy occupies less volume than a corresponding portion of the intimate mixture layer. |
| US10510885B1 |
Transistor with asymmetric source/drain overlap
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials. |
| US10510880B2 |
Trench power MOSFET
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. |
| US10510878B1 |
Semiconductor devices and methods for forming the same
A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface. |
| US10510877B2 |
Semiconductor structure
A semiconductor structure includes a substrate, a source/drain region, a composite layer and a plug. The source/drain region and the composite layer are over the substrate. The composite layer includes a first sublayer having a first material, a second sublayer having a second material, and a third sublayer having the first material. A bandgap of the second material is larger than that of the first material. The second sublayer is between the first sublayer and the third sublayer. The plug is through the composite layer, and electrically connected to the source/drain region. The plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, and a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion. |
| US10510876B2 |
Quantum doping method and use in fabrication of nanoscale electronic devices
A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms. |
| US10510861B1 |
Gaseous spacer and methods of forming same
A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack. |
| US10510857B2 |
Thin film transistor, method for manufacturing the same and display device
A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode. |
| US10510856B2 |
Semiconductor device and method
A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel region within the nanowire. In additional embodiments multiple nanowires, multiple bottom contacts, multiple top contacts, and multiple gate contacts are utilized. |
| US10510855B2 |
Transistor layout to reduce kink effect
The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions. |
| US10510853B2 |
FinFET with two fins on STI
A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin. |
| US10510852B2 |
Low-k feature formation processes and structures formed thereby
Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material. |
| US10510851B2 |
Low resistance contact method and structure
A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening. |
| US10510850B2 |
Semiconductor device and method
A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer. |
| US10510848B2 |
Sub-fin sidewall passivation in replacement channel FinFETS
Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage. |
| US10510846B2 |
Semiconductor device with needle-shaped field plate structures in a transistor cell region and in an inner termination region
A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern. |
| US10510844B2 |
Semiconductor device and method of manufacturing same
Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate. |
| US10510839B2 |
Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. |
| US10510838B2 |
High surface dopant concentration formation processes and structures formed thereby
Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region. |
| US10510833B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove. |
| US10510830B2 |
N-type polysilicon crystal, manufacturing method thereof, and N-type polysilicon wafer
An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (Ω·cm), the slope of resistivity is 0 to −1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8. |
| US10510828B2 |
Capacitor with high aspect radio silicon cores
High aspect ratio passive electrical components are presented formed from a single-piece silicon (Si) substrate having a textured surface with at least one high aspect ratio structure. The high aspect ratio structure includes a Si core having a width (CX), a height (CZ), and a minimum aspect ratio of CZ-to-CX of at least 5:1. An electrical conductor layer overlies the Si core. The electrical component may be a capacitor, inductor, or transmission line. In the case of a capacitor, the substrate textured first surface is made up of a plurality of adjacent high aspect ratio conductor-dielectric-Si (CDS) structures. Each CDS structure includes: a Si core, a dielectric layer overlying the Si core, and an electrical conductor layer overlying the dielectric layer. The Si cores may be formed in the geometry of parallel ridges, columns, or as a honeycomb. Each Si core comprises at least 90% of the CDS structure height. |
| US10510827B2 |
Capacitor having multiple graphene structures
A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers. |
| US10510825B2 |
Metal-insulator-metal capacitor with improved time-dependent dielectric breakdown
A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor. |
| US10510818B2 |
Organic light emitting display device
An OLED display device is disclosed, and the metal connection electrode is connected to the auxiliary electrode through a recessed hole; the recessed hole forms a first cavity and a second cavity communicating with each other, and the first cavity extends from an edge line of the second cavity away from the pixel electrode in the same direction; the pixel definition layer is above the array substrate, and reserved with grooves corresponding to the recessed holes and the pixel electrodes; an OLED semiconductor layer on the pixel definition layer covers on the pixel electrode and the metal connection electrode, and also extends into the first cavity to be connected with the auxiliary electrode; a cathode is on the OLED semiconductor layer, and extends into the first cavity to be connected with the auxiliary electrode, and is in a discontinuous connection state with the recessed hole as a breakpoint. |
| US10510814B2 |
OLED display panel and display device
An OLED display panel and a display device are provided. An image sensor is added below OLED light-emitting devices, a light shielding layer including at least one pinhole imaging region is added between the image sensor and the OLED light emitting device, with the pinhole imaging region corresponding to a gap position between the OLED light-emitting devices in the light shielding layer and staggered from light shielding parts in a signal routing and a control device, an object located above the OLED display panel is imaged on the image sensor. |
| US10510813B2 |
Transparent display device
Disclosed is a transparent display device. The transparent display device includes a first display panel, including a transmissive area and an emissive area where a first pixel including a plurality of subpixels displaying an image is provided, and a second display panel including a second pixel provided to overlap the emissive area and the transmissive area of the first display panel, the second display panel being provided on a first surface of the first display panel. The second pixel of the second display panel controls an amount of light incident on the first display panel, thereby preventing a visibility of an image displayed by the first display panel from being reduced by external light. |
| US10510811B2 |
Color filter and white organic light-emitting diode display apparatus
The present invention disclosures a color filter used for a WOLED display apparatus. The color filter includes a red pixel section, a green pixel section, a blue pixel section and a white pixel section. A red photoresist is disposed in the red pixel section, a green photoresist is disposed in the green pixel section, and a blue photoresist is disposed in the blue pixel section. The white pixel section includes a first sub-section, and a red photoresist, a green photoresist or a blue photoresist is disposed in the first sub-section. The present invention further disclosures a WOLED display apparatus including above color filter. The color filter of the present invention can reduce a Y value of chromaticity coordinate of the white pixel. Required brightness of the monochromatic pixels drops at a white image and power consumption is reduced. Accordingly, the life of display devices rises. |
| US10510807B2 |
Display device manufacturing method, and display device
In this manufacturing method, in a blue fluorescent light-emitting layer formation step, a blue fluorescent light-emitting layer is formed in both a subpixel and a subpixel; in a green fluorescent light-emitting layer formation step, a green fluorescent light-emitting layer is formed in both the subpixel and a subpixel; and in a red light-emitting layer formation step, a red light-emitting layer is formed in both the subpixel and a subpixel. In at least two of the abovementioned steps, linear vapor deposition is performed using a slit mask having an opening that is provided so as to extend across a plurality of pixels. |
| US10510803B2 |
Semiconductor memory device and method for fabricating the same
A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line. |
| US10510801B2 |
Image display device with quantum dot
It is an object of the present invention to provide an image display device in which it is possible to adjust the spectrum of light emitted by pixels and adjust the chromaticity of the light emitted by the pixels. Provided is an image display device having a pixel region in which each pixel comprises a plurality of subpixels and the pixels are arranged in a matrix, wherein each of the subpixels includes a plurality of light-emitting layers overlapping each other with an electrode sandwiched therebetween, and the plurality of light-emitting layers each contain a quantum dot material and have different peak emission wavelengths from each other. |
| US10510800B2 |
Device comprising a light-emitting diode and a Schottky barrier diode rectifier, and method of fabrication
An integrated circuit is provided with a (bridge) rectifier circuit configured to couple to an alternating current (AC) supply to a (string of) LEDs monolithically fabricated on substrate, preferably on a patterned sapphire substrate (PSS). The rectifier including at least one schottky barrier diode configured to have a reverse-bias breakdown voltage substantially equal to or greater than half a peak voltage of the AC supply. Further embodiments include a method for fabricating an integrated Schottky barrier diode (SBD) with a LED on a LED wafer. Some embodiments can include etching processes to a wafer that may include a plurality of processing cycles. Some embodiments can further include a wafer having a patterned substrate. The wafer with the patterned substrate may have an interface layer configured to facilitate increasing a forward bias current density of the SBD. |
| US10510798B2 |
Method of forming deep trench isolation in radiation sensing substrate and image sensor device
A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer. |
| US10510797B2 |
Semiconductor image sensor
A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate, and the color filter includes a plurality of second micro structures disposed over the back side of the substrate. |
| US10510796B1 |
Small pixels having dual conversion gain providing high dynamic range
A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel. |
| US10510794B2 |
Semiconductor image sensor
A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, an isolation structure surrounding the pixel sensor and disposed in the substrate, a dielectric layer disposed over the pixel sensor on the front side of the substrate, and a plurality of conductive structures disposed in the dielectric layer and arranged to aligned with the isolation structure. |
| US10510792B2 |
3DIC seal ring structure and methods of forming same
A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip. |
| US10510790B2 |
High-k dielectric liners in shallow trench isolations
A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material. |
| US10510785B2 |
Method for manufacturing TFT substrate and method for manufacturing TFT display apparatus
The present disclosure provides a method for manufacturing a TFT substrate and a method for manufacturing a TFT display apparatus, including the steps of: providing a base substrate; forming a source/drain metal layer on the base substrate; depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer; using a BCl3 gas to remove metal oxides generated on surface of the source/drain metal layer with air; and using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer. |
| US10510783B2 |
TFT array substrate and manufacturing method thereof, display device
A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer. |
| US10510782B2 |
Array substrate and manufacturing method thereof, and display device
An array substrate and a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a first signal line and a second signal line which have a same extension direction and are separated from each other on a base substrate; forming an initial pixel electrode on the base substrate, such that the initial pixel electrode includes a first extension portion, and the initial pixel electrode is connected to the first signal line by the first extension portion and the initial pixel electrode is separated from the second signal line; and removing at least part of the first extension portion of the initial pixel electrode to form the pixel electrode separated from the first signal line. |
| US10510781B2 |
Semiconductor device and method for manufacturing semiconductor device
A method of producing a semiconductor device according to an embodiment of the present invention includes: step (C) of forming an oxide semiconductor layer of a plurality of thin film transistors on a gate dielectric layer; step (F) of forming an aperture in an interlevel dielectric layer, the aperture being located between an active region and a plurality of terminal portions and extending through the interlevel dielectric layer; and step (G) of, after step (F), forming an upper conductive portion on the interlevel dielectric layer. In step (C), a protection layer made of the same oxide semiconductor film as the oxide semiconductor layer is formed above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions. In step (F), the aperture is formed so as to overlap the protection layer. |
| US10510780B2 |
Array substrate and display device
An array substrate and a display are provided. The array substrate includes a plurality of sub-pixel regions arranged in rows and columns. The sub-pixel region includes a pixel aperture region. A conductive pattern is provided between two adjacent sub-pixel regions in a row direction, at least part of the conductive pattern being located between pixel aperture regions of the two adjacent sub-pixel regions in the row direction, and the conductive pattern being connected to a common voltage. |
| US10510778B2 |
Array substrate, display device and wearable device
The present disclosure provides an array substrate, a display device and a wearable device. The array substrate includes a plurality of pixel units. Each of the pixel units includes a pixel electrode and a thin film transistor connected to the pixel electrodes, the plurality of pixel units forms a display region, and the thin film transistor of the pixel unit at an edge of the display region is closer to the edge of the display region than the pixel electrode thereof. |
| US10510771B2 |
Three-dimensional memory devices having plurality of vertical channel structures
A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other. |
| US10510770B2 |
Three-dimensional memory device
A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed. |
| US10510765B2 |
Memory device and method for fabricating the same
A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased. |
| US10510759B2 |
Semiconductor memory device
A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern. |
| US10510757B2 |
Semiconductor device including storage element
An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer. |
| US10510754B2 |
Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same
An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact. |
| US10510748B2 |
Transistor for increasing a range of a swing of a signal
A transistor includes a first doping well, a second doping well, a first doping area, a second doping area, a gate layer, and at least one compensation capacitor. The first doping well and the second doping well are formed in a structure layer. The first doping area and the second doping area are formed in the first doping well and have a first conductivity type, the second doping well has a second conductivity type, and the first doping area is used for transmitting the signal. The at least one compensation capacitor is used for adjusting a voltage drop of a parasitic junction capacitor between the first doping area and the first doping well, a voltage drop of a parasitic junction capacitor between the first doping well and the second doping well, or a voltage drop of a parasitic junction capacitor between the second doping well and the structure layer. |
| US10510747B1 |
BCD semiconductor device and method for manufacturing the same
A BCD semiconductor device includes devices integrated on a single chip. The devices include a first high voltage nLIGBT device, a second high voltage nLIGBT device, a first high voltage nLDMOS device, a second high voltage nLDMOS device, a third high voltage nLDMOS device, a first high voltage pLDMOS device and low voltage NMOS, PMOS and PNP devices, and a diode device. A dielectric isolation is applied to the high voltage nLIGBT, nLDMOS and pLDMOS devices to realize a complete isolation between the high and low voltage devices. The nLIGBT, nLDMOS, NPN and low voltage NMOS and PMOS are integrated on the substrate of a single chip. The isolation region composed of the dielectric, the second conductivity type buried layer, the dielectric trench, and the first conductivity type implanted region realizes full dielectric isolation of high and low voltage devices. The six types of high voltage transistors have multiple channels. |
| US10510733B2 |
Integrated device comprising embedded package on package (PoP) device
A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality. |
| US10510732B2 |
PoP device and method of forming the same
Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV. |
| US10510731B2 |
Package-on-package (PoP) structure including stud bulbs
Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. |
| US10510730B2 |
Stacked semiconductor structure and method
A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. |
| US10510729B2 |
3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug. |
| US10510718B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate; a first die disposed over the substrate; a second die disposed over the substrate; a molding disposed over the substrate and surrounding the first die and the second die; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; and a via extended within the second die and between the dielectric layer and the substrate. |
| US10510713B1 |
Semicondcutor package and method of manufacturing the same
A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device. |
| US10510705B2 |
Semiconductor package structure having a second encapsulant extending in a cavity defined by a first encapsulant
A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a plurality of conductive elements, a first encapsulant and a second encapsulant. The second semiconductor die is disposed on the first semiconductor die. The conductive elements each comprises a first portion and a second portion and are disposed around the first semiconductor die and the second semiconductor die. The first encapsulant surrounds the first semiconductor die and the respective first portions of the conductive elements. The second encapsulant covers a portion of a top portion of the first semiconductor die and surrounds the respective second portions of the conductive elements. |
| US10510704B2 |
Package structure and method of manufacturing the same
A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat. |
| US10510700B2 |
Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan. |
| US10510698B2 |
Semiconductor structure and method of forming
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure. |
| US10510696B2 |
Pad structure and manufacturing method thereof in semiconductor device
A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region. |
| US10510693B2 |
Semiconductor package structure
A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches. |
| US10510690B2 |
Wafer level package (WLP) and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure. |
| US10510687B2 |
Packaging devices and methods for semiconductor devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region. |
| US10510685B2 |
Dishing prevention columns for bipolar junction transistors
In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating. |
| US10510676B2 |
System and method for aligned stitching
A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration. |
| US10510671B2 |
Method for forming semiconductor device structure with conductive line
A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench. |
| US10510670B2 |
Pad structure design in fan-out package
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. |
| US10510669B2 |
Multi-chip package and method of providing die-to-die interconnects in same
A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541). |
| US10510668B1 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A hybrid bonded structure is provided. A cover lid comprising a base portion and at least one dummy portion protruding from the base portion is provided. The at least one dummy portion of the cover lid is bonded to the hybrid bonding structure. The base portion is removed. A redistribution structure over the hybrid bonding structure and the at least one dummy portion is formed. |
| US10510666B2 |
Interconnect structure and method of forming same
An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer. |
| US10510662B2 |
Vertically oriented metal silicide containing e-fuse device and methods of making same
One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse. |
| US10510660B2 |
Semiconductor package devices integrated with inductor
The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface, a first conductive pattern and a second conductive pattern. The first conductive pattern is formed on the first surface. The second conductive pattern is formed on the second surface. The first conductive pattern is connected with the second conductive pattern. |
| US10510656B2 |
Semiconductor device
A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects. |
| US10510655B2 |
Semiconductor devices employing a barrier layer
A semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. A barrier layer on the sidewalls of the trench is formed using a surface modification process and a surface treatment process. |
| US10510654B2 |
Dummy metal with zigzagged edges
A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge. |
| US10510648B2 |
Fan-out package structure and method
A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion. |
| US10510647B2 |
Semiconductor package
A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad. |
| US10510646B2 |
Packae structure, RDL structure and method of forming the same
A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace. |
| US10510638B2 |
Electronic component-embedded board
There is provided an electronic component-embedded board. The electronic component-embedded board includes: a first insulating layer; a metal layer formed on the first insulating layer; a first electronic component disposed on the metal layer; a second insulating layer formed on the first insulating layer and the metal layer such that the first electronic component is buried in the second insulating layer; a second electronic component disposed above the second insulating layer; and a heat radiating member thermally connected to the metal layer exposed from the second insulating layer and thermally connected to the second electronic component. |
| US10510637B2 |
Devices and methods for heat dissipation of semiconductor integrated circuits
A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact. |
| US10510633B1 |
Package and printed circuit board attachment
Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads. |
| US10510629B2 |
Integrated circuit package and method of forming same
A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure. |
| US10510627B2 |
Display device including an adhesive layer
A display device includes a display panel having a display area and a non-display area. A window is disposed on the display panel. A bezel portion is disposed on the window. The bezel portion at least partially overlaps the non-display area. An adhesive layer is disposed between the display panel and the window. An interlayer is disposed between the bezel portion and the adhesive layer. The interlayer has at least one ultrasound transmitting area overlapping the bezel portion. |
| US10510625B2 |
Systems and methods for controlling plasma instability in semiconductor fabrication
An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal. |
| US10510624B2 |
Metrology systems with multiple derivative modules for substrate stress and deformation measurement
Embodiments of the disclosure provide a metrology system. In one example, a metrology system includes a laser source adapted to transmit a light beam, a lens adapted to receive at least a portion of the light beam from the laser source, a first beam splitter positioned to receive at least the portion of the light beam passing through the lens, a first beam displacing device adapted to cause a portion of the light beam received from the beam splitter to be split into two or more sub-light beams a first recording device having a detection surface, and a first polarizer that is positioned between the first displacing device and the first recording device, wherein the first polarizer is configured to cause the two or more sub-light beams provided from the first displacing device to form an interference pattern on the detection surface of the first recording device. |
| US10510623B2 |
Overlay error and process window metrology
A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position. |
| US10510622B1 |
Vertically stacked complementary-FET device with independent gate control
A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode. |
| US10510620B1 |
Work function metal patterning for N-P space between active nanostructures
A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together. |
| US10510618B2 |
FinFET EPI channels having different heights on a stepped substrate
A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET. |
| US10510617B2 |
CMOS VFET contacts with trench solid and liquid phase epitaxy
Embodiments are directed to a complementary metal oxide semiconductor having source and drain contacts formed using trench. An n-type field effect transistor (NFET) includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate. A p-type FET (PFET) includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate. A first gate of the NFET is formed around a channel region of the p-type semiconductor fin and a second gate of the PFET is formed around a channel region of the n-type semiconductor fin. The first gate and the second gate include a dipole layer. The NFET and PFET each has a threshold voltage of about 150 mV to about 250 mV and a difference between the threshold voltages of the NFET and PFET is less than about 50 mV. |
| US10510615B2 |
FinFET devices and methods of forming the same
A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process. |
| US10510605B2 |
Semiconductor die singulation and structures formed thereby
An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. |
| US10510602B2 |
Methods of producing self-aligned vias
Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is selectively etched from some of the filled vias to form via openings to the first conductive line and a trench. |
| US10510601B2 |
Method for reducing metal plug corrosion and device
A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution. |
| US10510599B2 |
FinFET switch
An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin. |
| US10510593B2 |
Contact openings and methods forming same
A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask. |
| US10510591B1 |
Package-on-package structure and method of manufacturing package
A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die. |
| US10510588B2 |
Interconnection structure and manufacturing method thereof
An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via. |
| US10510578B2 |
Protective film forming film, protective film forming sheet and work product manufacturing method
A protective film forming film 1 is provided in which the product of the breaking stress (MPa) measured at a measurement temperature of 0° C. and the breaking strain (unit: %) measured at a measurement temperature of 0° C. in at least one of the protective film forming film 1 and a protective film formed from the protective film forming film 1 is in a range of 1 MPa·% to 250 MPa·%. According to such a protective film forming film 1, the protective film forming film 1 or the protective film formed from the protective film forming film 1 can be suitably divided in an expanding process performed on a workpiece when the workpiece is divided to obtain a work product. |
| US10510577B2 |
Lift off process for chip scale package solid state devices on engineered substrate
A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure. |
| US10510576B2 |
Carrier-bonding methods and articles for semiconductor and interposer processing
A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing. |
| US10510575B2 |
Substrate support with multiple embedded electrodes
A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate. |
| US10510571B2 |
Reticle transfer system and method
A method comprises transporting semiconductor devices between a global system and a local system, wherein an input terminal of the local system is connected to the global system, and wherein the global system comprises a plurality of stockers and a global transportation system connected to the stockers and the local system comprises a first service area, an internal buffer, a second service area and a plurality of lithography apparatuses and transporting a semiconductor device from the first service area to a lithography apparatus in the second service area. |
| US10510570B2 |
Systems, apparatus, and methods for purging a substrate carrier at a factory interface
Embodiments of the present invention provide systems, apparatus, and methods for purging a substrate carrier. Embodiments include a frame configured to sit proximate to a load port door without interfering with operation of a factory interface or equipment front end module robot; one or more inter-substrate nozzle arrays supported by the frame and configured to spray gas into a substrate carrier; and one or more curtain nozzle arrays supported by the frame and configured to spray gas across an opening of the substrate carrier. Numerous additional aspects are disclosed. |
| US10510566B2 |
Cluster tool techniques with improved efficiency
Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock. |
| US10510565B2 |
Thermal treatment system with collector device
A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path. |
| US10510563B2 |
Wafer carrier assembly
A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space. |
| US10510562B2 |
Stacked semiconductor devices and methods of forming same
Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. |
| US10510561B2 |
Semiconductor device package including conformal metal cap contacting each semiconductor die
In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer. |
| US10510556B2 |
Integrated circuit package pad and methods of forming
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. |
| US10510554B2 |
Guard ring structure of semiconductor arrangement
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. |
| US10510548B2 |
Semiconductor structure
Semiconductor structures are provided. The semiconductor structure includes a base including first, second, third, and fourth regions, used for first, second, third, and fourth transistors, respectively. A gate dielectric layer is on the first, second, third and fourth regions of the base. A first material layer is on the gate dielectric layer. A second material layer is on the first material layer above the fourth region. A third material layer is on the first material layer above the third region and on the second material layer above the fourth region. A fourth material layer is on the third material layer above the third and fourth regions and on the first material layer on the second region. The first material layer above the first region is used as a first work function layer for the first transistor. |
| US10510539B2 |
Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same
A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm. |
| US10510537B2 |
Pixel structure and driving method thereof, and display device
A pixel structure, a driving method thereof, and a display device are provided. The accommodation chamber of the pixel structure includes: a first substrate and a second substrate opposite to each other, an accommodation space being formed therebetween; a light absorption layer in the accommodation space, including a flowable insulating liquid layer; a transparent thin film in the accommodation space, located between the insulating liquid layer and the second substrate, a refractive index of the transparent thin film being less than or equal to that of the insulating liquid layer. The accommodation chamber is in one of the at least two following states: in a first state, the insulating liquid layer is separated from the transparent thin film such that light rays from the second substrate are totally reflected; and in a second state, the insulating liquid layer and the transparent thin film at least are partially in direct contact. |
| US10510536B2 |
Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
Methods for depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber are provided. The method may include: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate. Related semiconductor structures are also disclosed. |
| US10510529B2 |
Formation of SiOCN thin films
Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance. |
| US10510527B2 |
Single wafer cleaning tool with H2SO4 recycling
Some embodiments relate to methods and apparatus for mitigating high metal concentrations in photoresist residue and recycling sulfuric acid (H2SO4) in single wafer cleaning tools. In some embodiments, a disclosed single wafer cleaning tool has a processing chamber that houses a semiconductor substrate. A high oxidative treatment unit may apply a high oxidative chemical pre-treatment to the semiconductor substrate to remove a photoresist residue having metal impurities from the semiconductor substrate in a manner that results in a contaminant remainder. A SPM cleaning unit apply a sulfuric-peroxide mixture (SPM) cleaning solution to the semiconductor substrate to remove the contaminant remainder from the semiconductor substrate as an SPM effluent. The SPM effluent is provided to a recycling unit configured to recover sulfuric acid (H2SO4) from the SPM effluent and to provide the recovered H2SO4 to the SPM cleaning unit via a feedback conduit. |
| US10510524B2 |
Ion trap mass spectrometry device and mass spectrometry method using said device
After various ions of sample origin have been captured within an ion trap, unnecessary ions other than a target ion having a specific m/z are ejected from the ion trap (S1, S2). Subsequently, an operation for dissociating the target ion within the ion trap by hydrogen radical dissociation (HAD), and an operation for sequentially ejecting the thereby generated product ions by resonance excitation from the low m/z side to a point located immediately before the m/z of the target ion, are repeated multiple times (S3-S7). The ions ejected by resonance excitation are detected with a detector to acquire MS/MS spectrum data, and the data obtained by performing the ejection by resonance excitation multiple times are accumulated to create the final MS/MS spectrum (S5, S8). |
| US10510520B2 |
Electrically conductive, gas-sealed, aluminum-to-aluminum connection and methods of making same
Various configurations of electrically conductive, gas-sealed connections between two pieces of aluminum are described along with methods of making an electrically conductive, gas-sealed connection between two pieces of aluminum. |
| US10510518B2 |
Methods of dry stripping boron-carbon films
Embodiments of the invention generally relate to methods of dry stripping boron-carbon films. In one embodiment, alternating plasmas of hydrogen and oxygen are used to remove a boron-carbon film. In another embodiment, co-flowed oxygen and hydrogen plasma is used to remove a boron-carbon containing film. A nitrous oxide plasma may be used in addition to or as an alternative to either of the above oxygen plasmas. In another embodiment, a plasma generated from water vapor is used to remove a boron-carbon film. The boron-carbon removal processes may also include an optional polymer removal process prior to removal of the boron-carbon films. The polymer removal process includes exposing the boron-carbon film to NF3 to remove from the surface of the boron-carbon film any carbon-based polymers generated during a substrate etching process. |
| US10510517B2 |
Cleaning apparatus for an exhaust path of a process reaction chamber
A cleaning apparatus of an exhaust path of a process reaction chamber used in a manufacturing of articles including a semiconductor or an LCD. The cleaning apparatus of the exhaust path includes a housing having an inflow pipe, connected to an upstream end of the exhaust path, an outflow pipe, connected to a downstream end of the exhaust path, and a connecting pipe disposed between the inflow pipe and the outflow pipe. A radio frequency generator in the housing applies radio frequency power to the inflow pipe and to the outflow pipe via respective coils. Plasma induced within the inflow and outflow pipes from RF power applied via the respective coils causes the generation of radicals from the exhaust gas flowing within. The radicals act to dislodge accumulated particulates within the exhaust path downstream of the cleaning apparatus. |
| US10510516B2 |
Moving focus ring for plasma etcher
A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber. |
| US10510511B2 |
Apparatus for treating substrate
Provided is an apparatus for treating a substrate which is capable of uniformly controlling a temperature of a support plate. The apparatus for treating the substrate includes a chamber having a treating space with an opened top surface, a support unit disposed within the chamber to support the substrate, a dielectric assembly disposed on the opened top surface of the chamber to cover the opened top surface, and a plasma source disposed above the dielectric assembly, the plasma source including an antenna generating plasma from a gas supplied into the chamber. The dielectric assembly includes a dielectric window, and heating units each of which is formed of a non-metallic material, the heating units being disposed on a top surface of the dielectric window to heat the dielectric window. |
| US10510510B2 |
Treating biomass
Methods and systems are described for processing cellulosic and lignocellulosic materials and useful intermediates and products, such as energy and fuels. For example, irradiating methods and systems are described to aid in the processing of the cellulosic and lignocellulosic materials. The electron beam accelerator has multiple windows foils and these foils are cooled with cooling gas. In one configuration a secondary foil is integral to the electron beam accelerator and in another configuration the secondary foil is part of the enclosure for the biomass conveying system. |
| US10510509B2 |
Edge detection system
An edge detection system is provided that generates a scanning electron microscope (SEM) linescan image of a pattern structure including a feature with edges that require detection. The edge detection system includes an inverse linescan model tool that receives measured linescan information for the feature from the SEM. In response, the inverse linescan model tool provides feature geometry information that includes the position of the detected edges of the feature. |
| US10510503B2 |
Electrically controllable integrated switch
Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure. |
| US10510497B2 |
Removable electric current switching element and electrical switchgear for switching an electric current comprising such a removable switching element
A removable electric current switching element includes a housing including a first bottom plate and a second bottom plate opposite to one another. The housing includes insulating walls which extend around electrically mobile contacts from the second bottom plate and in a direction perpendicular to the second bottom plate. The housing also includes protection walls which at least partially cover internal faces of the insulating walls, these protection walls being formed of a single piece with the second bottom plate. |
| US10510495B2 |
Electrochemical capacitor
A low-cost electrochemical capacitor is provided which has high capacity and excellent charging and discharging characteristics, simultaneously has excellent safety and reliability, and has the basic performance as a capacitor, achieved in that, as the electrolyte between a negative electrode and a positive electrode, a solution of an ambient temperature molten salt and a specific polyether copolymer is allowed to gel using a specific photoreaction initiator and is held between the two electrodes. This low-cost electrochemical capacitor has the basic performance of a capacitor, has high capacity and excellent charging and discharging characteristics without use of a separator, and simultaneously has excellent safety and reliability. |
| US10510493B2 |
Core-shell composite, method for producing the same, electrode material, catalyst, electrode, secondary battery, and electric double-layer capacitor
This core-shell composite (10) is provided with a core (11) formed from a porous carbon body having a large number of pores from the interior through to the surface, and a shell layer (12) formed from conductive polymer nanorods (12a) that extend outward from the cavities of the pores (11a) on the surface of the core. The present invention provides the core-shell composite (10), to which electrolyte ions can be efficiently adsorbed or doped, a method for producing the core-shell composite, as well as an electrode material, a catalyst, an electrode, a secondary battery and an electric double-layer capacitor that use the core-shell composite. |
| US10510486B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes a multilayer body that includes a second main surface defining and functioning as a mounting surface. Outer electrodes include underlying electrode layers including a conductive metal and a glass component and conductive resin layers including a thermosetting resin and a metal component. The underlying electrode layers extend from first and second end surfaces onto at least the second main surface. The conductive resin layers extend onto the underlying electrode layers provided on the second main surface, portions of the second main surface, and portions of the underlying electrode layers provided on the first end surface and the second end surface and cover portions of the first and second end surfaces, the portions including areas corresponding to about 9% or more and about 82% or less of areas of the first and the second end surfaces. |
| US10510482B2 |
Primary sided-arrangement of primary winding structures, a method of manufacturing the primary-sided arrangement, a system for inductive power transfer and a method for inductively supplying power to a vehicle
The invention relates to a primary-sided arrangement (1) of primary winding structures (W1, W2, W3) of a system for inductive power transfer, wherein the primary-sided arrangement (1) comprises at least three phase lines and at least one winding structure (W1, W2, W3) per phase line, wherein each winding structure (W1, W2, W3) comprises at least one subwinding structure (SW1_1, . . . , SW3_3), wherein the winding structures (W1, W2, W3) extend along a longitudinal axis (x) of the primary-sided arrangement (1), wherein a pitch (P12_1, . . . , P32_3) between corresponding subwinding structures (SW1_1, . . . , SW3_3) of the winding structures (W1, W2, W3) varies along the longitudinal axis (x) and/or a length (L_SW1_1, . . . , LSW1_3) of the subwinding structures (SW1_1, . . . , SW3_3) of the winding structures (W1, W2, W3) varies along the longitudinal axis (x). The invention further relates to a system for inductive power transfer, to a method of manufacturing a primary-sided arrangement (1) and to a method for inductively supplying power to a vehicle. |
| US10510481B2 |
Transformer system with dynamic control
The regulation, power-handling capability, and reliability of a transformer is improved by a connected switching network which changes the effective numbers of turns and effective wire size of the windings synchronously during each cycle of an applied AC input voltage. |
| US10510475B2 |
Induction component
The invention proposes an induction component produced using thin film technology which can be used for a variety of functions. It contains, on a magnet core with a ring shape, two coil devices which, for their Part, are in turn constructed from at least two coils. The adjacent end windings of adjacent coils are connected to one another and to a common solder pad within each coil device. This makes it possible to connect individual coils and thus to utilize different functions of the induction component. |
| US10510471B2 |
Composition for bonded magnets, bonded magnet and integrally molded component
A composition for bonded magnets according to the present invention contains from 88% by mass to 91% by mass (inclusive) of a samarium-iron-nitrogen magnet powder having an average particle diameter of from 1.8 μm to 2.8 μm (inclusive), from 0.5% by mass to 2.5% by mass (inclusive) of a polyamide elastomer having a tensile elongation at break of 400% or more and a bending modulus of elasticity of 100 MPa or more, from 0.5% by mass to 2.0% by mass (inclusive) of carbon fibers having fiber diameters of from 10 μm to 12 μm (inclusive) and from 0.3% by mass to 1.0% by mass (inclusive) of a carboxylic acid ester, with the balance made up of a polyamide resin which is composed of a polyamide 12 having a weight average molecular weight (Mw) of from 4,500 to 7,500 (inclusive) as determined by molecular weight distribution measurement. |
| US10510465B1 |
Methods and systems for securely accessing and managing aggregated submarine cable system information
Aggregated, submarine cable system information is securely stored, accessed and managed. Security is assured through the use of multi-factor authentication that is compliant with National Institutes of Standards And Technology and US. Government Defense Federal Acquisition Regulation requirements. Further, real-time audit logs are generated as end-users access controlled unclassified information. |
| US10510464B1 |
Continuously transposed conductors and assemblies
A continuously transposed conductor (CTC) cable may include a plurality of electrically insulated strands arranged in first and second stacks with the plurality of strands successively transposed between the first and second stacks. The plurality of strands may include at least one strand having a plurality of component strands that are arranged in third and fourth stacks with the plurality of component strands successively transposed between the third and fourth stacks. Each of the components strands may include a conductor and insulation formed at least partially around the conductor. |
| US10510463B2 |
Wavy metal nanowire network thin film, stretchable transparent electrode including the metal nanowire network thin film and method for forming the metal nanowire network thin film
A wavy metal nanowire network thin film, a stretchable transparent electrode including the metal nanowire network thin film, and a method for forming the metal nanowire network thin film. More specifically, it relates to a wavy nanowire network structure based on straight metal nanowires, a method for producing the nanowire network structure, and a flexible electrode including the wavy metal nanowire structure. The flexible electrode of the present invention is transparent and stretchable and exhibits stable performance even when subjected to various deformations. |
| US10510458B2 |
Lithiated carbon phosphonitride extended solids
A lithiated carbon phosphonitride material is made by, for example, reacting P(CN)3 with LiN(CN)2 in solution (for example, dimethoxyethane or pyridine), then drying the solution to obtain the product. The material is a thermoset that is stable to over 400° C. and exhibits up to 10−3 S·cm2 of Li+ conductivity. |
| US10510457B2 |
Transparent conductor
The transparent conductor includes a transparent resin substrate, a first metal oxide layer, a metal layer containing a silver alloy, and a second metal oxide layer in the order presented. The first metal oxide layer contains zinc oxide, indium oxide, and titanium oxide, and the content of SnO2 in the first metal oxide layer is 40 mol % or less with respect to the total of four components of zinc oxide, indium oxide, titanium oxide, and tin oxide in terms of ZnO, In2O3, TiO2, and SnO2, respectively. The second metal oxide layer contains the four components, and the content of SnO2 in the second metal oxide layer is 12 to 40 mol % with respect to the total of the four components in terms of ZnO, In2O3, TiO2, and SnO2, respectively. |
| US10510456B2 |
Multi-leaf collimator and driving system
The present disclosure relates to a collimator. The collimator may include a motor, a transmission unit having a first end and a second end, and a leaf unit having a leaf. The first end of the transmission unit may be connected to the motor and the second end of the transmission unit may be connected to the leaf. The present disclosure also relates to a collimator system. The collimator system may include a leaf module having a leaf, a driving module having a motor configured to drive the leaf, and a processing module to generate a movement profile of the leaf. The movement profile of the leaf may include a first speed during a first stage, a second speed of the leaf during a second stage, and a third speed of the leaf during a third stage. |
| US10510452B2 |
Steam generator for nuclear steam supply system
A nuclear steam supply system utilizing gravity-driven natural circulation for primary coolant flow through a fluidly interconnected reactor vessel and a steam generating vessel. In one embodiment, the steam generating vessel includes a plurality of vertically stacked heat exchangers operable to convert a secondary coolant from a saturated liquid to superheated steam by utilizing heat gained by the primary coolant from a nuclear fuel core in the reactor vessel. The secondary coolant may be working fluid associated with a Rankine power cycle turbine-generator set in some embodiments. The steam generating vessel and reactor vessel may each be comprised of vertically elongated shells, which in one embodiment are arranged in lateral adjacent relationship. In one embodiment, the reactor vessel and steam generating vessel are physically discrete self-supporting structures which may be physically located in the same containment vessel. |
| US10510449B1 |
Expert opinion crowdsourcing
An expert opinion crowdsourcing system is disclosed that may enable a person seeking an opinion (or other work product) to efficiently access experts (or other persons) who may provide such opinions (or other work products). For example, the system may enable a person to submit a request to the system, at which point the system may automatically match the request to one or more appropriate experts. The system may then provide the request to the appropriate experts, and receive opinions back from the experts in response to the request. The opinions may then be provided back to the person that submitted the request. The request may include various characteristics and/or criteria that may be matched to, or satisfied by, other characteristics or criteria associated with the experts. The system may include aspects whereby requests and/or opinions may be anonymized and/or combined. |
| US10510447B2 |
Surgical teleoperated device for remote manipulation
A mechanical teleoperated device for remote manipulation includes a slave unit having a number of slave links interconnected by a plurality of slave joints; an end-effector connected to the slave unit; a master unit having a corresponding number of master links interconnected by a plurality of master joints; and a handle connected to a distal end of the master unit. The device further includes first device arranged to kinematically connect the slave unit with the master unit, second device arranged to kinematically connect the end-effector with the handle, and a mechanical constraint device configured to ensure that one master link of the master unit is guided along its longitudinal axis so that the corresponding slave link of the slave unit always translates along a virtual axis parallel to the longitudinal axis of the guided master link in the vicinity of the remote manipulation when the mechanical teleoperated device is operated. |
| US10510446B2 |
Hearing aid user account management
A data system for handling user data for a hearing aid user and at least one hearing aid (10, 11) having a memory for storing personal settings for alleviating a hearing loss for the hearing aid user includes a remote server (25) accessible by means of an Internet enabled computer device. A personal communication device (13) is Internet enabled and is able to act as a gateway to the Internet for the at least one hearing aid. The user may create a user account on the remote server, enter personal information into the user account and store the entered personal information on the remote server, and enter the gateway information to the user account. The personal communication device and the at least one hearing aid are provided with respective transceivers for establishing a wireless connection under guidance of said application software. The least one hearing aid uploads the personal settings for alleviating the hearing loss via the gateway to the remote server for storing in the user account. |
| US10510444B2 |
Care plan administration
Techniques for administering a care plan. Embodiments receive the care plan specifying observation metrics to monitor biometric data collected from a patient. At least one monitoring device available is identified and embodiments receive biometric data collected using the at least one monitoring device, where the biometric data is initially classified as a first type of event by the at least one monitoring device. Additionally, embodiments analyze the received biometric data to reclassify the first event as an occurrence of a second type of even, and, upon determining that the occurrence of the second type of event satisfies at least one threshold condition specified in the care plan, initiate at least one treatment plan specified in the care plan and corresponding to the satisfied at least one threshold value. |
| US10510440B1 |
Method and apparatus for identifying matching record candidates
A method, computing device and computer program product are provided to identify records that are associated with same person, even in instances in which the records are created and stored by different entities. In a method, a plurality of records are received, each having attributes associated with a person. For each record, the method determines a digest by determining a fuzzy representation of one or more of the attributes for the person and then combining representations of the attributes. The method also receives a query relating to a record for the person and determines a digest based upon the attributes of the person. In response to the query, the method identifies one or more records that are associated with respective individuals who are candidates to match the person based upon a comparison of representations of the digests of the records and the person. |
| US10510427B2 |
High reliable OTP memory with low reading voltage
The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals. |
| US10510424B2 |
Semiconductor memory device for improving differences between current characteristics of memory cells
Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation. |
| US10510420B2 |
Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage. |
| US10510419B1 |
Monitoring and charging inhibit bit-line
Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL. |
| US10510418B2 |
Semiconductor device and operating method thereof
A semiconductor memory device includes a cell string, a common source line controller, and a page buffer. The cell string includes a plurality of memory cells coupled in series between a common source line and a bit line. In a read operation, the common source line controller provides a channel current to the cell string through the common source line. The page buffer senses data stored in a selected memory cell among the plurality of memory cells by sensing a current of the bit line when the channel current is provided. The common source line controller precharges the bit line by providing the channel current to the cell string through the common source line. After the bit line is precharged, the page buffer senses the data stored in the selected memory cell by transmitting a voltage of the bit line to a sensing node. |
| US10510417B2 |
Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order. |
| US10510414B2 |
3D NAND memory Z-decoder
Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, including multiple tiers of memory cells, each tier of memory cells including an access line of at least one memory cell. The access line of a first tier of the first unit can be selectively coupled to a first drive transistor through a first decoder transistor, the access line of a first tier of the second unit can be selectively coupled to the first drive transistor through a second decoder transistor, and the access line of the first tier of the first unit can be selectively coupled to the access line of the first tier of the second unit through the first and second decoder transistors. |
| US10510411B2 |
RRAM array with current limiting element
An integrated chip is disclosed. In some embodiments, the integrated chip includes a plurality of resistive random access memory (RRAM) devices respectively having a first electrode and a second electrode. A bit-line decoder is connected to the first electrode of the plurality of RRAM devices by a plurality of bit-lines. A current limiting element is connected to the second electrode of the plurality of RRAM devices by way of a plurality of access transistors. The current limiting element is configured to concurrently limit currents on the plurality of bit-lines. |
| US10510404B2 |
Write assist circuit of memory device
A device including a memory cell is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. During a write operation of the memory cell, the first operational voltage and the second operational voltage are configured at different voltage levels, and the third operational voltage and the fourth operational voltage are configured at the same voltage level. |
| US10510403B2 |
Memory read stability enhancement with short segmented bit line architecture
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines. |
| US10510402B2 |
Mitigating write disturbance in dual port 8T SRAM
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims. |
| US10510401B2 |
Semiconductor memory device using shared data line for read/write operation
A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line. |
| US10510398B2 |
Systems and methods for improving write preambles in DDR memory devices
A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device. |
| US10510395B2 |
Protocol for refresh between a memory controller and a memory
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. |
| US10510392B1 |
Integrated circuits having memory cells with shared bit lines and shared source lines
Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line. |
| US10510391B2 |
Magnetic exchange coupled MTJ free layer having low switching current and high data retention
Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment. |
| US10510390B2 |
Magnetic exchange coupled MTJ free layer having low switching current and high data retention
Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment. |
| US10510385B2 |
Write scheme for a static random access memory (SRAM)
A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side. |
| US10510375B2 |
Friction adjustment mechanisms for optimizing friction between a pad and a disc in an optical disc restoration device
The invention pertains in general to a latching mechanism for maintaining desired friction levels on an optical disc in an optical disc restoration device. In particular the invention pertains to devices, systems and methods for easily maintaining friction levels between pads and an optical disc in an optical disc restoration device for ease of adjusting friction settings during quality control, repair operation or when optimization settings are being set in an optical disc restoration device by a user. |
| US10510372B1 |
Mechanical retention and retrieval for tape storage cartridge
A tape library rack includes partitions defining a slot for receiving a tape cartridge. A hook is coupled with the rack to engage a notch in the cartridge and retain the cartridge within the rack slot. A gripper for retrieving the cartridge includes a ramped surface to engage the hook and laterally displace the hook from the cartridge notch as the hook travels along the ramped surface. The gripper engages the notch from which the hook has been displaced and pulls the cartridge from the slot. |
| US10510371B1 |
Thermally-assisted magnetic recording head having sub-mount with barrier-members sandwich a heater
A light source-unit comprises a laser diode, a sub-mount which the laser diode is joined, and a heater which is joined on a joint surface of the sub-mount. The sub-mount comprises a pair of barrier-members. The barrier-members are formed with lower thermal conductivity material which thermal conductivity is lower than joining metal which is used for joining the laser diode and the sub-mount. The barrier-members are formed on the joint surface so as to sandwich the heater. |
| US10510367B1 |
Method and apparatus for processing multiple servo channels in magnetic recording devices
A method of operating a storage device includes reading data from a storage medium using a detector, processing signals from the detector through a plurality of processing circuits, each respective processing circuit in the plurality of processing circuits being optimized for a different state of a channel condition and providing a respective output metric, selecting a processing circuit from the plurality of processing circuits by comparing the respective output metrics from each processing circuit in a predetermined manner, and designating as output of the detector output of the processing circuit that is selected. The output metrics may be branch metrics or path metrics, and the channel condition may be fly-height or phase shift. The storage device includes a storage medium, and a read channel including a detector, and processing circuits that process signals from the detector. Each respective processing circuit is optimized for a different state of a channel condition. |
| US10510363B2 |
Pitch detection algorithm based on PWVT
A pitch detection method. Such a pitch detection method may apply Pseudo Weigner Ville Transformation (PWVT) as a spectral representation of speech signal. Also, the pitch detection method may take the median value of each frame of the speech signal as a threshold for making the voicing decision. Additionally, the pitch detection method may take a moving average of PWVT as the threshold for voicing decision. |
| US10510358B1 |
Resolution enhancement of speech signals for speech synthesis
An approach to speech synthesis uses two phases in which a relatively low quality waveform is computed, and that waveform is passed through an enhancement phase which generates the waveform that is ultimately used to produce the acoustic signal provided to the user. For example, the first phase and the second phase are each implemented using a separate artificial neural network. The two phases may be computationally preferable to using a direct approach to yield a synthesized waveform of comparable quality. |
| US10510356B2 |
Voice processing method and device
A voice processing method and device, the method comprising: detecting a current voice application scenario in a network (S1); determining the voice quality requirement and the network requirement of the current voice application scenario (S2); based on the voice quality requirement and the network requirement, configuring voice processing parameters corresponding to the voice application scenario (S3); and according to the voice processing parameters, conducting voice processing on the voice signals collected in the voice application scenario (S4). |
| US10510355B2 |
Time-alignment of QMF based processing data
The present document relates to time-alignment of encoded data of an audio encoder with associated metadata, such as spectral band replication (SBR) metadata. An audio decoder (100, 300) configured to determine a reconstructed frame of an audio signal (237) from an access unit (110) of a received data stream is described. The access unit (110) comprises waveform data (111) and metadata (112), wherein the waveform data (111) and the metadata (112) are associated with the same reconstructed frame of the audio signal (127). The audio decoder (100, 300) comprises a waveform processing path (101, 102, 103, 104, 105) configured to generate a plurality of waveform subband signals (123) from the waveform data (111), and a metadata processing path (108, 109) configured to generate decoded metadata (128) from the metadata (111). |
| US10510352B2 |
Detecting replay attacks in voice-based authentication
Disclosed are various embodiments for detecting replay attacks in voice-based authentication systems. In one embodiment, audio is captured via an audio input device. It is then verified that the audio includes a voice authentication factor spoken by a user. The audio is then compared with stored audio spoken by the user. If it is determined that an exact copy of the voice authentication factor is in the stored audio, one or more actions may be performed. |
| US10510348B1 |
Smart medical room optimization of speech recognition systems
A method, computer system, and a computer program product for optimizing speech recognition in a smart medical room. The present invention may include receiving a piece of verbal data associated with a medical encounter from one or more audio recording devices. The present invention may also include accessing a plurality of signals from a plurality of biometric sensors associated with a plurality of medical equipment associated with the smart medical room based on the received piece of verbal data associated with the medical encounter. The present invention may further include selecting, from a database, one or more speech domain models based on the accessed plurality of signals from the plurality of biometric sensors associated with the plurality of medical equipment, wherein the one or more speech domain models are utilized to optimize a transcription of speech during the medical encounter in the smart medical room. |
| US10510344B2 |
Systems and methods of interpreting speech data
Method and systems are provided for interpreting speech data. A method and system for recognizing speech involving a filter module to generate a set of processed audio data based on raw audio data; a translation module to provide a set of translation results for the raw audio data; and a decision module to select the text data that represents the raw audio data. A method for minimizing noise in audio signals received by a microphone array is also described. A method and system of automatic entry of data into one or more data fields involving receiving a processed audio data; and operating a processing module to: search in a trigger dictionary for a field identifier that corresponds to the trigger identifier; identify a data field associated with a data field identifier corresponding to the field identifier; and providing content data associated with the trigger identifier to the identified data field. |
| US10510339B2 |
Selecting media using weighted key words
Techniques are disclosed relating to selecting and/or ranking from among multiple recordings based on determining facial attributes associated with detected words. For example, each recording may be transcribed and analyzed to determine whether the recordings include words in one or more sets of words. Facial analysis may be performed during intervals in the recordings corresponding to recognized words. Counts of the recognized words may be weighted based on detected facial attributes. In various embodiments, disclosed techniques may facilitate accurate selection of relevant media from large data sets. |
| US10510337B2 |
Method and device for voice recognition training
A method on a mobile device for voice recognition training is described. A voice training mode is entered. A voice training sample for a user of the mobile device is recorded. The voice training mode is interrupted to enter a noise indicator mode based on a sample background noise level for the voice training sample and a sample background noise type for the voice training sample. The voice training mode is returned to from the noise indicator mode when the user provides a continuation input that indicates a current background noise level meets an indicator threshold value. |
| US10510336B2 |
Method, apparatus, and system for conflict detection and resolution for competing intent classifiers in modular conversation system
A method, system, and apparatus are provided for resolving conflicts between training data conflicts by retrieving independent training data sets, each comprising a plurality of intents and end-user utterances for use in training one or more classifiers to recognize a corresponding intent from one or more of the end-user utterances, providing a first test end-user utterance associated with a first intent from the first independent training data set to the one or more classifiers to select an output intent generated by the one or more classifiers; identifying a first conflict when the first intent does not match the output intent, and automatically generating, by the system, one or more conflict resolution recommendations for display and selection by an end user to resolve the first conflict. |
| US10510333B1 |
Vehicle and method of controlling the same
Provided are a vehicle capable of detecting an occurrence of a fault of a noise control device of the vehicle and indicating a result of the detection to a user upon occurrence of a fault such that the user handles the fault, and a method of controlling the same, the method including outputting an acoustic signal having a predetermined frequency through a speaker; detecting the acoustic signal output through the speaker; detecting a vibration generated by the acoustic signal output through the speaker; and determining that a fault has occurred when the detected acoustic signal and the detected vibration mismatch the acoustic signal having the predetermined frequency. |
| US10510330B2 |
Device and method for sound deadening a component
A device for deadening the sound of a component having a damping layer of a foamed material and a stiffening layer, which is fixedly connected to the damping layer and which is stiffer than the damping layer, wherein the damping layer is formed by a foamed hot-melt adhesive. |
| US10510329B1 |
Keyboard apparatus
A keyboard apparatus includes a plurality of keys, a frame supporting the plurality of keys arranged in a first direction, a first member, a longitudinal direction of the first member being along the first direction, and a second member including a first section, a second section, and a third section, the first section, the third section, and the second section being arranged in this order in a second direction perpendicular to the first direction, the first section being a plate-shaped member sandwiched between the first member and the frame, the second section being connected to the first member at a position away from the first section, the third section being separated from the first member between the first section and the second section, and a longitudinal direction of the second member being along the first direction. |
| US10510328B2 |
Lyrics analyzer
A lyrics analyzer generates tags and explicitness indicators for a set of tracks. These tags may indicate the genre, mood, occasion, or other features of each track. The lyrics analyzer does so by generating an n-dimensional vector relating to a set of topics extracted from the lyrics and then using those vectors to train a classifier to determine whether each tag applies to each track. The lyrics analyzer may also generate playlists for a user based on a single seed song by comparing the lyrics vector or the lyrics and acoustics vectors of the seed song to other songs to select songs that closely match the seed song. Such a playlist generator may also take into account the tags generated for each track. |
| US10510327B2 |
Musical instrument for input to electrical devices
A musical instrument system is described to operate as a human to machine input device. The musical instrument outputs an audio signal that is processed to control the movement of an indicator in a computer. |
| US10510325B2 |
Rendering method, rendering apparatus, and electronic apparatus
A rendering method includes receiving an input including pixel pattern information of a device configured to display a rendered image, generating a pixel pattern of the rendered image using the received input indicating pixel pattern information, and outputting a pixel value of the rendered image into a frame buffer using the generated pixel pattern. |
| US10510324B2 |
Display controller
A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20. |
| US10510321B2 |
Modular flexible display system and methods
Disclosed are embodiments of flexible display modules and systems of flexible display modules. Display modules have a plurality of light emitting elements arranged in a predetermined pattern and providing a highly uniform visual effect. Alignment and complementary alignment features enable the alignment of adjacent display modules and the creation of large displays from a plurality of aligned display modules. Features to couple to and retain a support frame are provided. Flexible and durable weather resistance features are provided. Modules and systems have features that permit installation and removal from the front side or the back side of the display. A system of modular support frames works cooperatively with the display modules, adapting to different mounting environments, and thereby providing large modular displays with desirable properties. |
| US10510319B2 |
Techniques for imaging a scanned object
A technique for enhancing an image includes manipulating a base image to highlight pixels showing a particular material based on the energy absorption information of each pixel. In another technique, pixels in a base image are each converted to an output value to produce a converted image. Another technique allows imaging an obstructed object within a base image which is made of pixels, each representing a captured signal from a source emitting a source signal I0. An obstruction region contains pixels representing a combined signal I3 having traversed the obstructed object and an obstructive layer. Knowing a layer signal I2 representing a signal having traversed the obstructive layer outside of the obstruction region, the layer signal I2 may be removed from the combined signal I3, in order to reveal the original signal I1 representing an image of the obstructed object. |
| US10510317B2 |
Controlling display performance with target presentation times
Embodiments described herein provide for a display system to generate and display data on a display device, the display system comprising one or more graphics processors to generate one or more frames of data for display on the display device; display logic to receive a request to display the one or more frames of data, the request including a requested presentation time in which the one or more frames of data are to be displayed; and a display engine to present the one or more frames of data to the display device for display at a target presentation time, the target presentation time derived from the requested presentation time, wherein the display engine is to adjust a refresh rate of the display device based on the target presentation time of the one or more frames of data. |
| US10510316B2 |
Control circuit, control method and display apparatus
The present disclosure provides a control circuit, a control method, and a display apparatus. The control sub-circuit is connected to a first voltage input terminal, a second voltage input terminal and the driving sub-circuit, and configured to boost a second voltage input from the second voltage input terminal to obtain a third voltage when it is detected that a first voltage input from the first voltage input terminal is lower than or equal to a first reference voltage, and output the third voltage to the driving sub-circuit; the driving sub-circuit is connected to the control sub-circuit, a fourth voltage input terminal and scan lines of a display panel, and configured to output the third voltage to the scan lines when it is detected that a fourth voltage input from the fourth voltage input terminal is lower than or equal to a second reference voltage. |
| US10510314B2 |
GOA circuit having negative gate-source voltage difference of TFT of pull down module
The invention provides a GOA circuit, comprising a plurality of cascaded GOA units. Each GOA unit comprises: a pull up control module, an output module, a pull down module and a pull down maintenance module; for N-th GOA unit: the 41st TFT of pull down module having a gate receiving a scan signal from (N+4)-th GOA unit, a source connected to a circuit start signal, and a drain connected to the first node, and the circuit start signal having a low voltage level lower than or equal to 0V and higher than the low voltage signal; so that when the scan signal from (N+4)-th GOA unit changing from high voltage to low voltage, the gate-source voltage difference of the 41st TFT being negative to effectively reduce the current leakage and prevent the current leakage from affecting the first node voltage, improve circuit stability, facilitate cost reduction and narrow border. |
| US10510312B2 |
Gate driver, display apparatus including the same and method of driving display panel using the same
A gate driver includes a gate signal generating part, a switching part and a switching controlling part. The gate signal generating part is configured to generate a gate signal including a precharge time and a normal charge time using a compensated gate on voltage and a gate off voltage. The switching part is disposed between the gate signal generating part and a gate line. The switching part is configured to apply a compensated gate signal to the gate line. The switching controlling part is configured to generate a switching control signal for controlling an operation of the switching part. |
| US10510311B2 |
Panel-driving device and display device
The present disclosure provides a technique for supplying different voltages to a plurality of adjacent electrodes, sensing a voltage formed on each electrode, and diagnosing a short-circuit failure of each electrode. |
| US10510310B2 |
Semiconductor device
A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line. |
| US10510307B2 |
Array substrate and display device
The embodiments of the present disclosure provide an array substrate. The array substrate includes a plurality of pixel groups arranged along a column direction. Each of the plurality of pixel groups includes a plurality of sub-pixel rows. Each sub-pixel row includes a plurality of sub-pixels, a first shelter or a second shelter is arranged between two adjacent sub-pixels, and the first shelter and the second shelter are arranged alternately. The first shelter has a first width, and the second shelter has a second width. For each pixel group, the first shelters on at least one of the sub-pixel rows are aligned with the second shelters on at least one of other sub-pixel rows. |
| US10510301B2 |
Scan driver and display apparatus having the same
A scan driver is integrated to include multiple drivers in a peripheral area of a display. The drivers output gate, emission, and/or other signals for driving pixel circuits in the display based on one or more clock signals. |
| US10510296B2 |
Pixel driving circuit and pixel driving method, array substrate and display device
Disclosed is a pixel driving circuit, comprising a driving control circuit, a first driving circuit and a second driving circuit. The driving control circuit is configured to control one of the first driving circuit and the second driving circuit to be turned on under the condition the first scanning line outputs an effective voltage signal, and control the other of the first driving circuit and the second driving circuit to be turned on under the condition the second scanning line outputs an effective voltage signal. The first driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit. The second driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit. |
| US10510294B2 |
Pixel driving circuit, method for driving the same and display device
A pixel driving circuit, a driving method thereof and a display device are provided. The pixel driving circuit includes a driving control unit, a light-emission control signal generation unit and a pixel driving unit. The driving control unit is configured to generate a low resolution control signal or a high resolution control signal. The pixel driving unit includes N pixel driving sub-units. Each pixel driving sub-unit is configured to control M light-emitting elements connected to the pixel driving sub-unit to emit light simultaneously when the light-emission control signal generation unit has received the low resolution control signal, and control the M light-emitting elements to emit light in a time-division manner based on M data voltages applied to a data line in a time-division manner when the light-emission control signal generation unit has received the high resolution control signal, where N and M are both integers greater than 1. |
| US10510290B2 |
Image processing method and apparatus for preventing screen burn-ins and related display apparatus
The present invention provides a display apparatus with display screen burn-ins prevention functions, comprising a calculation module configured to identify a set of to-be-adjusted grayscale edge pixels corresponding to a static display part in a detection area based on a plurality of sets of grayscale edge pixels identified from a plurality of images in the detection area at different time instances; a determination module configured to determine whether the set of to-be-adjusted grayscale edge pixels is an empty set; and an adjustment module configured to adjust intensity levels of the to-be-adjusted grayscale edge pixels when the determination module determines that the set of to-be-adjusted grayscale edge pixels is not an empty set. |
| US10510287B2 |
Transfer method of expanding pitches of device and an apparatus for performing the same
A transfer method for expanding pitches of devices includes: providing a first substrate with micro devices having the pitches being a predetermined value in a first direction and a second direction; transferring the micro devices to a first roller by contacting it with the micro devices, wherein a pitch of contact line portions on the first roller is N times of the predetermined value; transferring the micro devices on the first roller to a second substrate; rotating the second substrate by 90 degrees; transferring the micro devices to a second roller by rolling the second roller to contact the micro devices; and then transferring the micro devices to a third substrate to expand the pitch of the micro devices in both the first and the second directions. The portions in contact with the micro devices all have adhesive layers with different adhesion operation windows. |
| US10510285B2 |
Display device and drive method therefor
A measurement circuit includes a plurality of measurement units, performs, at a same timing, a main measurement for measuring a current or a voltage with respect to a pixel circuit with supplying a measurement voltage to a part of the measurement units and a dummy measurement for measuring a current or a voltage with supplying a dummy signal to remaining measurement units, and performs a calculation on a result of the main measurement and a result of the dummy measurement. As the dummy signal, a signal with which a value to be measured is approximately zero is used. The measurement result of the current or the voltage is used for correcting a video signal. With this, a display device which can remove noise in measurement when measuring the current or the voltage with respect to the pixel circuit is provided. |
| US10510281B2 |
Image processing apparatus and method, and electronic device
An image processing apparatus includes: an analyzer configured to calculate color characteristics by input pixel data, and determine whether the pixel data is achromatic based on the color characteristics; a first renderer configured to perform a first rendering on the pixel data in response to determining that the pixel data is not achromatic; and a second renderer configured to perform a second rendering on the pixel data in response to determining that the pixel data is achromatic. |
| US10510272B1 |
Electronic seal improvement
The present invention consists of a plug bolt and a bolt seat. The plug bolt comprises a conductor and a circuit board; the conductor has a first stuck-buckle, an accommodation-hole, and a top-cover; the circuit board is set with an RFID chip, an upper contact point, and a lower contact point. The RFID chip forms a first far-field antenna loop through the first pin, the upper contact point, the top-cover, and the conductor. The bolt seat is equipped with an elastic device, an internal antenna, an inserting-hole, and a second stuck-buckle, thereby controlling the elastic device to provide a pre-pressure to the internal antenna to electrically connect with the lower contact point. When the RFID chip is activated, the internal antenna forms a second far-field antenna loop and synchronously activate the first one; which the first and second far-field antenna loops can be cut-off when the top-cover is worn. |
| US10510267B2 |
Simulator system for medical procedure training
Implementations relate to medical simulations for medical procedure training. In some implementations, a system includes a simulation processing component including at least one processor and which generates a virtual environment using position signals that describe at least one of a position and a configuration of a physical surgical instrument relative to a physical surgical site. The simulation processing component updates the virtual environment according to changes in the position signals and according to control signals corresponding to inputs by a user of the system. The updating includes moving a virtual surgical instrument within the virtual environment, where an interaction of the virtual surgical instrument with a virtual surgical site is defined at least partly by a physical relationship between the physical surgical instrument and the physical surgical site. The simulation processing component outputs a representation of a simulation state signal indicative of a current state of the virtual environment. |
| US10510265B2 |
System and method for determining and using knowledge about human health
A system and method for predicting a health outcome of a user based on a determination of knowledge the user possesses regarding issues of physiological or mental health. |
| US10510262B1 |
Post guard integrated management system and post guard integrated management method thereof
A post guard integrated management system includes a post guard having an embedded integrated module and installed in a building, and when a collision accident occurs or a fire accident occurs in the post guard, and notifies a manager or an operator of the status and risk of the accident, and a post guard integrated management method thereof. The post guard integrated management system includes a post guard installed in a pillar of a rack and having a sensor to transmit a change in tilt and presence or absence of collision along with position information; and a management server configured to monitor presence or absence of collision and a dangerous condition of the rack or the post guard based on the transmitted presence or absence of collision and dangerous condition of the rack or the post guard and provide detected status information of all post guards to receiving terminals. |
| US10510261B2 |
Application and method for controlling flight of uninhabited airborne vehicle
The present invention is to provide an application for controlling the flight of an uninhabited airborne vehicle that detects a person at low cost and high efficiency and controls a drone to keep from hitting against the detected person. The application for controlling the flight of an uninhabited airborne vehicle runs on a smart device 200 connected with an uninhabited airborne vehicle 100, acquires and analyzes the image taken by a camera unit 20 of the smart device, and controls the flight of the uninhabited airborne vehicle to keep the uninhabited airborne vehicle 100 from hitting against the detected person through the uninhabited airborne vehicle flight control module 224. |
| US10510260B2 |
Air traffic control of unmanned aerial vehicles for delivery applications
An Unmanned Aerial Vehicle (UAV) air traffic control method utilizing wireless networks and concurrently supporting delivery application authorization and management communicating with a plurality of UAVs via a plurality of cell towers associated with the wireless networks, wherein the plurality of UAVs each include hardware and antennas adapted to communicate to the plurality of cell towers; maintaining data associated with flight of each of the plurality of UAVs based on the communicating; processing the maintained data to perform a plurality of functions associated with air traffic control of the plurality of UAVs; and processing the maintained data to perform a plurality of functions for the delivery application authorization and management for each of the plurality of UAVs. |
| US10510259B2 |
Method and system for scheduling a driver service provider for one or more third parties
This disclosure generally relates to a method and system for providing a ride for a third party rider at the request of a user ride requestor. In one embodiment, a driver device may be used to receive a ride request from one or more server computing devices for a third party rider. The driver device may receive information identifying the third party rider, including a password. Further, the driver device may transmit real time ride status information to the ride requestor directly or indirectly via the one or more server computing devices. |
| US10510255B2 |
Method for reducing collision damage
A method for performing an evasive maneuver of a motor vehicle in the event of an imminent collision with at least one collision object comprising at least the following: a) detecting that a collision with the at least one collision object is imminent, b) analyzing the at least one collision object and detecting whether a particularly sensitive upper region of the motor vehicle would be at least partially affected by the collision, and c) outputting a signal for initiating an evasive maneuver if a collision of the motor vehicle with the at least one collision object is imminent by which the particularly sensitive upper region of the motor vehicle would be at least partially affected. |
| US10510249B2 |
Safety driving assistant system, vehicle, and program
A safety driving assistant system according to one aspect of the present disclosure includes: an acquisition unit configured to acquire pieces of probe information from probe vehicles, each piece of probe information including information of a position of the corresponding probe vehicle and information of a time at which the probe vehicle has passed through the position; a detection unit configured to detect a sudden-deceleration-prone spot where sudden deceleration of probe vehicles frequently occurs, based on the pieces of probe information acquired by the acquisition unit; and a provision unit configured to provide information of the sudden-deceleration-prone spot detected by the detection unit, to a target vehicle that receives safety driving assistance. |
| US10510246B2 |
Measurement arrangement and method for temporarily transferring digital data from a source
The present disclosure relates to a measurement arrangement including: a first process automation technology field device, wherein the first field device includes a first inductive interface and a data processing unit, and wherein a second process automation technology field device can be connected to the first interface; and a data transfer device having a second inductive interface that is designed to complement the first interface, wherein the data transfer device can be connected via this to the first field device, wherein the data transfer device includes a data transfer module with which digital data can be transferred from a source to the data processing unit of the first field device via the data transfer device and the first or second inductive interface. The present disclosure likewise relates to a method for temporarily transmitting digital data from a source to a field device. |
| US10510243B2 |
Method for processing an error when performing a predetermined avionics procedure, related computer program and detection and alert system
A method for processing an error when performing a predetermined avionics procedure, related computer program and detection and alert system is disclosed. In one aspect, the method is carried out automatically by the detection and alert system of an aircraft, the method including monitoring the operation of one or several avionics device(s) of the aircraft, the monitoring based on the tracking of a sequence representative of the predetermined avionics procedure being carried out. The method further includes: detecting a break of the sequence due to an incorrect command and/or skipping of at least one expected command according to the predetermined avionics procedure being performed, and retrieving at least one piece of information representative of the break in the sequence. |
| US10510241B2 |
Communication apparatus and data processing method
Provided is a configuration that permits confirmation of emergency information viewing results on a reception apparatus, an endpoint of emergency information such as TV. A data processing section of a reception apparatus such as TV that receives and outputs emergency information generates an emergency information viewing result report that contains a record of emergency information viewing result information and sends the generated emergency information viewing result report to a management server and so on. The data processing section generates an emergency information viewing result report that contains a record of an identifier of emergency information output by the reception apparatus and emergency information output time information in accordance with a CDM (Consumption Data Message) format. The CDM keeps a record of not only emergency information output time information but also reception apparatus position information, emergency information sender information, and so on. |
| US10510240B2 |
Methods and systems for evaluating compliance of communication of a dispatcher
Methods and systems for evaluating compliance of communication of a dispatcher. One system includes an electronic computing device that includes an input device, a transceiver, and one or more electronic processors. The one or more electronic processors are configured to monitor communication between a dispatcher and a caller during a call and determine a type of call. The one or more electronic processors are further configured to determine a conversational procedure based on the type of call and compare a characteristic of the monitored communication to a constraint of the conversational procedure. The one or more electronic processors are further configured to determine that the characteristic of the monitored communication is outside the constraint of the conversational procedure and take an action as a function of determining that the characteristic of the monitored communication is outside the constraint of the conversational procedure. |
| US10510238B1 |
Water detection assembly
The present disclosure relates to a tangible, non-transitory, machine-readable medium, having machine-readable instructions to pair a water detection device of a plurality of water detection devices with a user account via a user device, receive a first signal indicative of a location of the water detection device from the user device, receive a second signal indicative of a personalized message to be sent to the user device upon a detection event of the water detection device, and display a list of the plurality of water detection devices and corresponding locations of each water detection device of the plurality of water detection devices on the user device. |
| US10510234B2 |
Method for generating alerts in a video surveillance system
A method for generating an alert signal in a surveillance system comprising: detecting a targeted individual in a video stream, selecting the targeted individual, and tracking the targeted individual, as first steps. The method also comprises classifying actions of the detected individual over a plurality of image frames in the video stream in response to the identification of the detected object as being a targeted person, and generating an alert signal if the classified action of the object is classified as a predefined alert-generating action. |
| US10510231B2 |
Moving object detection, tracking, and displaying systems
An alert and tracking system implemented on a computing device with a processor is presented. The system comprises a display with a viewing portion and a raster portion comprising a plurality of rasters. The system also comprises an image receiver configured to receive a first image and a second image, wherein the first image is received before the second image is received. The system also comprises a processing unit. The processing unit is configured to receive the second image. The processing unit is also configured to compare the second image to the first image. The processing unit is also configured to detect a change between the second image and the first image, wherein the detected change is indicative a moving object. The processing unit is also configured to update the viewing portion to display the second image. The processing unit is also configured to update the raster portion, wherein updating the raster image comprises adding a new raster to the plurality of rasters, wherein the new raster comprises a row of pixels corresponding to a compressed view of the image. |
| US10510230B1 |
Enclosures for coupling to asset walls
In some examples, an enclosure can include a lever to interact with an asset wall when the enclosure is coupled to the asset wall, an actuator coupled to a switch to interact with the lever, and an aperture to allow the actuator to move with the lever when the enclosure is removed from the asset wall, wherein the actuator provides a signal to the switch when the actuator moves beyond a threshold angle. |
| US10510227B2 |
Merchandise activity sensor system and methods of using same
Apparatus and systems using merchandise activity sensors for increasing the awareness of interactivity with merchandise on retail store displays (shelves, peg hooks, merchandise pushers, and other Point of Purchase displays) in order to facilitate more effective customer service, reduce theft and to provide additional analysis data related to merchandise/shopper interaction. |
| US10510226B2 |
Meter socket with tamper detection assembly
A meter socket with a tamper detection assembly is disclosed. The tamper detection assembly may include a light sensor that enables the detection of tampering caused by an energy thief removing the cover of the meter socket enclosure and/or removing the meter from the meter socket in an effort to access the power supply connectors and steal electricity. The tamper detection assembly may also include an acoustic sensor that enables the detection of tampering caused by an energy thief drilling, cutting, hammering, bending or otherwise attempting to violate the integrity of the meter socket enclosure in an effort to access the power supply connectors and steal electricity. The tamper detection assembly is preferably mounted within a mounting block of the meter socket so as to provide a secure source of power and communications for the assembly. |
| US10510224B2 |
Haptic actuator having movable bodies along an arcuate path of travel and related methods
A haptic actuator may include first and second bodies movable along an arcuate path of travel. The haptic actuator may also include a biasing member coupled between the first and second bodies. At least one electrical coil may be configured to move the first and second bodies to produce a haptic effect. |
| US10510222B2 |
Color-changing lighting dynamic control
A computerized communications system for remotely controlling various color-changing lighting scenes on color-changing lighting fixtures at a premises. The color-changing lighting systems at the remote premises are used to communicate emergency information such as the existence and type of an emergency. |
| US10510221B2 |
System and method for transmitting messages related to operations of electronic devices
A system and method are provided for transmitting messages related to operations of electronic devices. A management apparatus is notified of an event that occurred in a specific one of a plurality of electronic devices. The management apparatus determines one or more target devices in response to notification of the event that occurred in the specific electronic device. An event message corresponding to the event that occurred in the specific electronic device is created. The management apparatus transmits the event message to the one or more target devices. The one or more target devices output the received event message. |
| US10510218B2 |
Information processing apparatus, information processing method, and non-transitory storage medium
A checkout apparatus (10) includes an image data acquisition unit (11) that acquires data of an image; an image analysis unit (12) that recognizes a plurality of products in the image using a feature value of an exterior of each of the products registered in a feature value storage unit (14) and the data of the image; a reading necessity or non-necessity check unit (15) that extracts the product for which it is necessary to read a product code from among the recognized products, using an object-to-be-read storage unit (16) in which the product for which it is necessary to read the product code is registered in advance; and a reading unit (17) that reads the product code of the product extracted by the reading necessity or non-necessity check unit (15). |
| US10510213B2 |
Clock-synchronizing skill competition wagering system
A time-synchronizing wagering system is disclosed. The time-synchronizing wagering system includes an interactive controller; a credit processing controller; a regulated server; and a client station that allows for a skill-based game trigger point to be associated with a timestamp, compare the timestamp against a master timer, and determine a winner based on the comparison of the timestamp against a regulated timestamp. |
| US10510212B2 |
Gaming machine
A gaming machine which makes it possible to avoid monotonous game play is provided. At the start of each game play, gaming machine executes processes of: randomly selecting one of symbol random determination tables in which a probability of rearrangement of each symbol on each reel is defined, based on a symbol random determination table determination table in which a probability of random selection of one of the symbol random determination tables for each of the random determination tables; a symbol random determination process of randomly determining symbols to be rearranged based on the selected symbol random determination table; and displaying the determined symbols on a display device by rearranging the reels. |
| US10510211B2 |
Wagering game including progressive game with unknown randomly generated trigger value
A gaming system includes a game server operating a progressive game thereon and a plurality of player terminals in communication with the central server which operate base games thereon. A contribution amount from base wagers made on the player terminals in relation to the base game also contribute to one or more progressive totals of the progressive game. When one or more progressive totals reaches a secret trigger value, a winning condition is determined and a corresponding winning amount is made to the player terminal from which originated the contribution amount resulting in the secret trigger value being met. Optionally, under the winning condition, the progressive total may continue to increase by contribution amounts from one or more player terminals until eligibility criterium corresponding a second trigger event is met, such as a qualifying hand being dealt to the player terminal from which the winning condition originated. |
| US10510206B2 |
Gaming system and method for providing a gaming machine with dual projection displays
In one aspect, improved gaming machines are disclosed herein, which provides a first projection display for each gaming machine, and a second projector for displaying video on a plurality of the gaming machines. |
| US10510203B2 |
Identification device, identification method, identification program and computer readable medium including the identificatioin program
A device for determining authenticity including processing circuitry which generates a reference image data of a counterfeit prevention medium at an observation angle for comparison with captured image data obtained based on a pattern of light observed from the counterfeit prevention medium at the observation angle between an imaging direction of the captured image data and a reference line of a surface of the counterfeit prevention medium, calculates similarity between the captured image data and the reference image data, and determines authenticity of the counterfeit prevention medium based on whether the similarity exceeds a threshold. |
| US10510200B2 |
System and method for providing hands free operation of at least one vehicle door
A system and method for providing hands free operation of at least one vehicle door that include determining if a portable device is located within at least one local area polling zone of a vehicle. The system and method additionally include determining if the portable device is stationary for a first period of a predetermined period of time within the at least one local area polling zone of the vehicle and providing a notification of a remaining duration of the predetermined period of time to instruct an individual carrying the portable device to remain in a stationary position to allow the portable device to remain stationary for the remaining duration of the predetermined period of time. The system and method further include supplying an amount of power to open or close the at least one vehicle door if it is determined that the portable device remains stationary for the predetermined period of time. |
| US10510199B2 |
Power tool with irreversably lockable compartment
Power tool with irreversably lockable compartment. One power tool includes a housing including a compartment with an irreversible lock. The power tool further includes a wireless communication device including a wireless communication controller including a transceiver. The wireless communication device is configured to be received in the compartment and to engage with the irreversible lock. The power tool further includes a motor within the housing, and the motor is configured to drive an output drive device. The power tool further includes a controller within the housing and having an electronic processor, a memory, and a data connection. The data connection is configured to couple the electronic processor to the wireless communication device when the wireless communication device is inserted into the compartment. The controller is configured to control operation of the motor, and communicate with an external device via the data connection and the wireless communication controller. |
| US10510198B2 |
Multi-band identification and ranging
A long-range power-efficient multiple-band identification system and method includes, for example, a base-station control module and paired electronic key fob. The base-station control module and paired electronic key fob is arranged to provide a UHF (ultra-high frequency) wake transmitter for transmitting a wakeup signal in a UHF frequency range to the paired electronic key. When in range, the electronic key is awakened by the wakeup signal and in response transmits an acknowledgment reply to the base-station control module. After receiving the acknowledgment, the base-station control module transmits a relatively high power localization signal for determining an electronic key location. |
| US10510196B2 |
Remote key fob for motor vehicles
A remote key fob for a vehicle, includes a communications and control device, at least one transmit/receive device and a microcontroller. At least one control surface is arranged on an outer shell of a housing of the remote key fob and is coupled to the communications and control device. A printed circuit board held in the housing is placed beneath the control surface. The control surface is mechanically coupled to a metal detection section. Pressure actuation of the control surface from the outside results in a deformation or change of position of the detection section. A detection coil is located on the printed circuit board, wherein the detection coil is coupled to the communications and control device for forming an inductive proximity switch. The communications and control device determines an actuation of the control surface as a function of the inductivity or quality of the detection coil. |
| US10510194B2 |
Cloud-based connectivity energy budget manager
A storage maintains energy estimates corresponding to function requests for vehicles. A processor of a server is programmed to receive a function request for a vehicle, and direct the vehicle to perform the function request responsive to determining, according to battery information received from the vehicle and an energy estimate corresponding to the function request, that the vehicle has sufficient energy to perform the function request. |
| US10510193B2 |
Method and system for geofencing of vehicle impound yards
A method and system for geofencing of vehicle impound yards. One or more geofences around impound yards are selected. The one or more geofences are associated with one or more vehicles. When a vehicle enters the geofenced area, a user (e.g., an individual, car dealer, finance company, etc.) is immediately notified to prevent excessive impound financial charges. If a vehicle is left in a geofence area, a cumulative time duration and a cumulative finance charge are accurately recorded to reduce or prevent financial fraud. |
| US10510192B2 |
System and method performing job management
A system provides systems and methods for visualizing a computational process. A portion of attributes of a computational process may be displayed on a face of a three-dimensional object. In response to rotation of the object by a user, a different face of the object may be displayed and a different portion of the attributes displayed thereon. Each object may represent a status of a computational cluster, specifically a set of jobs executing on the cluster. A cluster may be selected and the jobs represented by means of graphical indicators arranges on a time axis and a performance axis. The size of a graphical indicator may indicate an amount of processing time consume by the corresponding job. A color of the graphical indicator may indicate a status. A portion of the graphical indicator may be visually distinguished from a remaining portion to indicate a completion percentage of the job. |
| US10510191B2 |
Interactions with 3D virtual objects using poses and multiple-DOF controllers
A wearable system can comprise a display system configured to present virtual content in a three-dimensional space, a user input device configured to receive a user input, and one or more sensors configured to detect a user's pose. The wearable system can support various user interactions with objects in the user's environment based on contextual information. As an example, the wearable system can adjust the size of an aperture of a virtual cone during a cone cast (e.g., with the user's poses) based on the contextual information. As another example, the wearable system can adjust the amount of movement of virtual objects associated with an actuation of the user input device based on the contextual information. |
| US10510189B2 |
Information processing apparatus, information processing system, and information processing method
In an information processing system 1, an information processing apparatus 10 recognizes, when a user moves real bodies 120a and 120b arranged on a play field 19, the movement on the basis of, for example, an image taken by a camera 122 taking an image of the movement to interlock objects of corresponding characters 202a and 202b displayed on a display apparatus 16. In addition, when the user moves the characters 202a and 202b through an input apparatus 14, the information processing apparatus 10 transmits a control signal to the corresponding real bodies 120a and 120b to perform interlocking. When a situation in which interlocking between the real bodies 120a and 120b and the characters 202a and 202b is difficult occurs, an appropriate scenario is selected from the scenarios prepared in advance and realized, thereby maintaining the consistency. |
| US10510188B2 |
Over-rendering techniques in augmented or virtual reality systems
One embodiment is directed to a user display device comprising a housing frame mountable on the head of the user, a lens mountable on the housing frame and a projection sub system coupled to the housing frame to determine a location of appearance of a display object in a field of view of the user based at least in part on at least one of a detection of a head movement of the user and a prediction of a head movement of the user, and to project the display object to the user based on the determined location of appearance of the display object. |
| US10510187B2 |
Method and system for virtual sensor data generation with depth ground truth annotation
Methods and systems for generating virtual sensor data for developing or testing computer vision detection algorithms are described. A system and a method may involve generating a virtual environment. The system and the method may also involve positioning a virtual sensor at a first location in the virtual environment. The system and the method may also involve recording data characterizing the virtual environment, the data corresponding to information generated by the virtual sensor sensing the virtual environment. The system and the method may further involves annotating the data with a depth map characterizing a spatial relationship between the virtual sensor and the virtual environment. |
| US10510181B2 |
System and method for cache management using a cache status table
A clip-cull-viewport (CCV) unit manages information associated with vertices of a primitive as the primitive passes through the CCV unit. The CCV unit includes an index cache and a cache-status table. Vertices of a received primitive are stored in locations within the index cache based on attribute and index fields of the primitive. If a vertex is a reused vertex of another primitive that matches a valid entry in the cache-status table and if the primitive survives being culled, the valid entry in the cache-status table is preserved, the attribute field of the primitive is set to indicate that the vertex is a reused vertex, and the primitive is sent to an output interface for a downstream unit. Otherwise, the attribute field is set to indicate that the vertex is not reused, and the primitive is sent to the output interface for the downstream unit. |
| US10510179B2 |
Method and device for enriching the content of a depth map
A method and device for enriching the content associated with a first element of a depth map, the depth map being associated with a scene according to a point of view. Thereafter, at least a first information representative of a variation of depth in the first element in the space of the depth map is stored into the depth map. |
| US10510178B2 |
Methods and systems for volumetric reconstruction based on a confidence field
An exemplary volumetric reconstruction system accesses captured color and depth data for a surface of an object in a real-world capture space. The captured color and depth data is captured by capture devices positioned with respect to the real-world capture space to have different vantage points of the surface of the object. Based on the captured color and depth data, the volumetric reconstruction system generates reconstructed color and depth data for a volumetric reconstruction of the surface of the object. The generating of the reconstructed color and depth data includes allocating voxel nodes for surface points on the object within a voxel data store, determining and storing a confidence field value for each voxel node that accounts for a distance factor and a noise-reduction factor, and determining the reconstructed color and depth data using a raytracing technique based on the stored confidence field values within the voxel data store. |
| US10510177B2 |
Data processing device
A data processing device applies pattern data to surface data on the basis of projection data, subdividing the surface data into voxels and determining the optimum projection data for each voxel according to its surroundings. |
| US10510172B2 |
Automated combination of multiple data visualizations
A visualization combination engine may be used to combine a first data visualization based on a first data set with a second data visualization based on a second data set. The combination process may be initiated by, for example, clicking and dragging the first data visualization onto the second data visualization. The visualization combination engine may create the combined data visualization without requiring the user to manually combine the first and second data sets. The combination may be carried out by identifying a key that is common between the two data sets and combining the first and second data sets into a combined data set based on the key, and then creating the combined data visualization based on the combined data set. One or more cues may be used during the process to provide helpful information and/or allow user selection of the properties of the combined data visualization. |
| US10510161B2 |
Patient-mounted or patient support-mounted camera for position monitoring during medical procedures
An apparatus for use in a medical procedure includes: a camera configured for attachment to a patient, wherein the camera is configured to detect one or more markers outside and away from the patient; and a processing unit configured to receive an input image from the camera, and to process the input image to monitor a position of a target associated with the patient during the medical procedure. An apparatus for use in a medical procedure includes: a camera configured for attachment to a patient support, wherein the camera is configured to detect one or more markers outside and away from the patient support; and a processing unit configured to receive an input image from the camera, and to process the input image to determine a position associated with the patient support during the medical procedure. |
| US10510159B2 |
Information processing apparatus, control method for information processing apparatus, and non-transitory computer-readable storage medium
An information processing apparatus comprising: a marker detection unit configured to detect one or more markers from an image obtained by capturing a physical space by an image capturing unit; a feature detection unit configured to detect a feature from the image; an estimation unit configured to estimate a position and orientation of the image capturing unit based on a detection result obtained by the marker detection unit and a detection result obtained by the feature detection unit; a stability obtaining unit configured to obtain stability of estimation of the position and orientation when some markers of the one or more markers are removed; and a determination unit configured to determine, based on the stability, whether the some markers are removable. |
| US10510148B2 |
Systems and methods for block based edgel detection with false edge elimination
Methods and systems which provide object edge image representation generation using block based edgel techniques implementing post edgel detection processing to eliminate false edges are described. Embodiments subdivide image data (e.g., image point clouds) to facilitate separate edgel detection processing of a plurality of sub-blocks of the image data. A false edge elimination algorithm of embodiments is applied in recombining the object edge image representation sub-blocks resulting from the sub-block edgel detection processing to eliminate false edge artifacts associated with use of block based edgel detection. |
| US10510147B2 |
Image processing device
An image processing device includes: a plurality of label data generation units which generate label data in which a predetermined label is assigned to each of a plurality of pixels in each of a plurality of divided images; a plurality of label integration information generation units which correspond to the respective label data generation units and generate label integration information representing association of labels included in the label data in order to integrate label data generated by a corresponding label data generation unit and label data generated by another label data generation unit; a plurality of label integration units which generate integrated label data in which respective pieces of label data corresponding to neighboring divided images are integrated; and a label integration processing control unit which distributes the label data to the respective label integration units such that computational loads to integrate the label data are equalized. |
| US10510146B2 |
Neural network for image processing
A method for processing an input in an artificial neural network (ANN) includes receiving, at an operator layer of a set of operator layers, a first feature value based on the input from a decoder convolutional layer of a decoder. The operator layer also receives a second feature value based on the input from an encoder convolutional layer of a encoder. The method also includes determining, at the operator layer, a third feature value based on the input by performing an element-wise operation with the first feature value based on the input and the second feature value based on the input. The method transmits, from the operator layer, the third feature value based on the input to an encoder layer that is subsequent to the encoder convolutional layer. The method generates an output based on the third feature value based on the input. |
| US10510145B2 |
Medical image comparison method and system thereof
A medical image comparison method is firstly to obtain plural images of the same body at different time points. Then, obtain a first feature point group by detecting feature points in the first image captured at a first time point, and a second feature point group by identifying feature points in the second image captured at a second time point. An overlapping image information is generated by aligning the second image with the first image according to the first and second feature point groups. Then, window areas corresponding to a first matching image and a second matching image of the overlapping image information are extracted one by one by sliding a window mask, and an image difference ratio for each of the window areas is calculated. In addition, a medical image comparison system is also provided. |
| US10510144B2 |
System and method for detection of suspicious tissue regions in an endoscopic procedure
An image processing system connected to an endoscope and processing in real-time endoscopic images to identify suspicious tissues such as polyps or cancer. The system applies preprocessing tools to clean the received images and then applies in parallel a plurality of detectors both conventional detectors and models of supervised machine learning-based detectors. A post processing is also applied in order select the regions which are most probable to be suspicious among the detected regions. Frames identified as showing suspicious tissues can be marked on an output video display. Optionally, the size, type and boundaries of the suspected tissue can also be identified and marked. |
| US10510143B1 |
Systems and methods for generating a mask for automated assessment of embryo quality
Systems and methods for generating a mask for automated assessment of embryo quality are disclosed herein. The method for generating a mask for automated assessment of embryo quality can include receiving an image, including a plurality of pixels, of a human embryo from an imaging system. A pixel can be selected and features of the selected pixel can be determined by generating a plurality of random boxes of random sizes and at random locations about the selected pixel. The selected pixel can be identified as one of: inside of a mask area; and outside of the mask area based on the determined features. |
| US10510142B1 |
Estimation using image analysis
Techniques are described for performing estimations based on image analysis. In some implementations, one or more images may be received of at least portion(s) of a physical object, such as a vehicle. The image(s) may show damage that has occurred to the portion(s) of the physical object, such as damage caused by an accident. The image(s) may be transmitted to an estimation engine that performs pre-processing operation(s) on the image(s), such as operation(s) to excerpt one or more portion(s) of the image(s) for subsequent analysis. The image(s), and/or the pre-processed image(s), may be provided to an image analysis service, which may analyze the image(s) and return component state information that describes a state (e.g., damage extent) of the portion(s) of the physical object shown in the image(s). Based on the component state information, the estimation engine may determine a cost estimate to repair and/or replace damaged component(s). |
| US10510141B2 |
Method and apparatus for determining illumination intensity for inspection, and method and apparatus for optical inspection
The present disclosure relates to a method and apparatus for determining an illumination intensity for inspection, and an method and apparatus optical inspection. The method for determining an illumination intensity for inspection comprises: acquiring images of a sample to be inspected taken by each of at least one imaging element at a plurality of illumination intensities; calculating, for each imaging element, a gray standard deviation of each of the images acquired at the plurality of illumination intensities; and determining the illumination intensity of each imaging element for inspection according to the gray standard deviation. The inspection accuracy may be improved by using the illumination intensity determined by the method provided in the present disclosure to inspect an object to be inspected. |
| US10510139B2 |
Image display apparatus
An image processing apparatus includes an image acquirer configured to acquire an input image, and a processor configured to generate the original image by performing for the input image correction processing using correction data according to an optical aberration of the observation optical system. In the correction processing for the oblique view state, the processor uses first correction data according to the optical aberration corresponding to a first position distant from the observation optical system by a distance made by adding a rotating radius of the eye to the first distance, to generate an area other than the specific area in the original image, and uses second correction data according to the optical aberration corresponding to a second position closer to the observation optical system than the first position to generate the specific area. |
| US10510133B2 |
Asymmetric multi-core heterogeneous parallel processing system
A multi-core asymmetric graphics processing unit (GPU) includes a first group and second group of GPU cores. The first group of GPU cores has a first microarchitecture and a first power consumption profile. The first group of GPU cores is configured to execute a subset of instructions of an instruction set architecture (ISA). The second group of GPU cores have a second microarchitecture and a second power consumption profile higher than the first power consumption profile, and are configured to execute the entire ISA. The first group and second group of GPU cores may be further differentiated by a number of pipeline stages, number of registers, branching execution, vectorization units, or combinations thereof. A subset of GPU cores in either group may have a different operation frequency. In some embodiments, an executable instruction may include an indicator to ascertain if execution is performed by the first or second group of GPU cores. |
| US10510132B2 |
Vehicle fleet management method and system with load balancing
A method utilizing real-time location information in a fleet management system. Simultaneous wireless communication connections are maintained between a respectively corresponding number of vehicles in a fleet and a central control center. The messages are received at the central control center, and each one of the messages includes information indicating the geographic location of a respectively corresponding vehicle in real-time or near real-time. The messages are collected and stored in the central control center. In response to a user request, a fleet management tool or report is provided in real-time or near real-time, the management tool or report being based at least in part on the messages indicating the geographic location of the vehicles. |
| US10510131B2 |
Return mail services
In an embodiment, an apparatus comprises one or more processors and one or more memories communicatively coupled to the one or more processors and storing instructions which, when processed by the one or more processors, cause: receiving a digital image of undeliverable mail and storing the digital image in a first database; causing data to be extracted from the digital image using Optical Character Recognition (OCR) or by processing encoded data; in response to causing data to be extracted from the digital image, identifying a sender of the undeliverable mail and a recipient of the undeliverable mail based on the data; causing additional data to be requested from two or more second databases based on the data extracted from the digital image; in response to delivery of the undeliverable mail and using the additional data requested from the two or more second databases, determining delivery hit rates for each of the two or more second databases; assigning, based on a highest hit rate of the delivery hit rates, at least one of the two or more second databases as a primary database from which additional data is requested; and in response to assigning the at least one of the two or more second databases as the primary database, causing additional data to be requested from the primary database. |
| US10510129B2 |
Selecting photographs for a destination or point of interest
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computerized travel services. One of the methods includes identifying photographs using an index of photographs, the photographs being identified from the index as photographs geographically related to a point of interest or destination and having a creation timestamp corresponding to a time of the year; determining for each of the photographs, a relevancy score based at least in part on: selection success data of the photograph for image queries referring to the point of interest or destination, and references to the point of interest or destination in documents associated with the photograph; and selecting a selected photograph from the photographs based at least in part on a respective visual quality score and the respective relevancy scores, the visual quality score representing a degree of visual quality of the respective photographs. |
| US10510126B2 |
Energy consumption alerting system, platform and method
An energy consumption alerting system is provided. The system includes a plurality of sensors deployed at different locations of at least one monitored site, the sensors being able to provide location-specific energy consumption values. The system further includes a data aggregation facility so as to sum up location-specific energy consumption values associated with at least two corresponding predetermined sensors of the plurality of sensors to obtain an aggregated energy consumption value. The system further includes an alerting facility this is able to compare the aggregated energy consumption value with an user-defined threshold level and notify a user if the at least one aggregated energy consumption value exceeds the at least one user-defined threshold level. A cloud-based energy consumption alerting platform and an energy consumption alerting method are also provided. |
| US10510125B2 |
Expense compliance checking based on trajectory detection
A method, system, and computer program storage product determine determining a trajectory information type of a receipt submitted by an employee. Trajectory information associated with the receipt submitted by the employee is retrieved based on the trajectory information type. Trajectory information corresponding to a device associated with the employee is also retrieved. The receipt is determined as a valid receipt in response to the trajectory information associated with the receipt submitted by the employee matching the trajectory information associated with the device associated with the employee. |
| US10510124B1 |
Systems and methods for vehicle accident detection based on intelligent micro devices
Intelligent micro devices on a vehicle can be scanned or read using a reading device. A map or data indicative of the micro devices on the vehicle can be generated by scanning the vehicle. The data or map may be used to determine loss or transfer of one or more micro devices on the vehicle. An accident associated with the vehicle can be determined based on loss or transfer of one or more the micro devices. The micro devices can store data associated with the vehicle, including an identity of the vehicle and a history of the vehicle. The micro devices can be read to determine the identity of the vehicle or another vehicle involved in the accident. |
| US10510120B1 |
System and method for obtaining and/or maintaining insurance coverage
An intermediary entity may act on behalf of consumers to find policy rates and/or other features that best meet the consumers' insurance requirements and/or preferences. For instance, consumers may give affirmative consent or otherwise opt into a program that provides insurance cost savings or discounts. Based upon an analysis of individual consumer characteristics and/or insurance preferences, each individual consumer may be grouped with other insurance consumers having similar characteristics and/or insurance preferences. The insurance consumer groupings may be offered for sale, such as through an online auction. When a winning bid is accepted, the insurance policies of the consumers may be updated or new policies may be provided and/or presented to individual consumers for their approval, thereby providing consumers with lower cost insurance and/or insurance that is more reflective of actual risk (or lack thereof). The consumer groups may be updated over time and re-auctioned. |
| US10510114B2 |
Distributed trading bus architecture
A distributed trading system for handling a plurality of order requests, each order request comprising parameters under which a participant will buy and/or sell a futures contract. A validator component is coupled to a messaging bus and has a first interface for receiving order request and an interface generating a validated order message on the messaging bus related to validated orders, wherein the validator implements processes for validating the order requests. A risk allocation value (RAV) component is coupled to the messaging bus and has an interface for receiving validated order messages from the validator, wherein the RAV component implements processes for evaluating risk associated with an order should that order be completed. A match engine is coupled to the messaging bus and has an interface for receiving validated order messages from the RAV component, wherein the match engine implements processes for matching orders based on the order-specified criteria. A persist component is coupled to the messaging bus and has an interface for receiving messages related to orders and trades, wherein the persist component implements processes for persistently storing information related to orders and trades. |
| US10510113B2 |
Providing financial transaction data to a user
The disclosure extends to computer-implemented personal financial management tools, methods and systems for providing financial transaction data to a user in the form of transaction images, such as check images, deposit images, receipt images, and other transaction related images, which may be incorporated into the personal financial management tool. The disclosure also extends to computer-implemented personal financial management tools, methods and systems for receiving core data, which may include transaction data, from a financial or banking institution and processing the data by cleansing the data, automatically categorizing the data, classifying the data, and then sending that processed data back to the financial or banking institution. The disclosure also extends to receiving and sending such data to and from the financial or banking institution in real-time. |
| US10510111B2 |
Image-based rendering of real spaces
Under an embodiment of the invention, an image capturing and processing system creates 3D image-based rendering (IBR) for real estate. The system provides image-based rendering of real property, the computer system including a user interface for visually presenting an image-based rendering of a real property to a user; and a processor to obtain two or more photorealistic viewpoints from ground truth image data capture locations; combine and process two or more instances of ground truth image data to create a plurality of synthesized viewpoints; and visually present a viewpoint in a virtual model of the real property on the user interface, the virtual model including photorealistic viewpoints and synthesized viewpoints. |
| US10510110B2 |
Home electrical appliance and network system
A network system including a home appliance, a server, and a communication terminal. The home appliance is provided with a control portion configured to control an operating state of the home appliance, an information setting portion configured to set information corresponding to current state of the control portion, and a transmitting portion configured to externally transmit a result of information set by the information setting portion through the communication line. The communication terminal is configured to display a specific advice, the specific advice being based on data, obtained from the multiple entries of data provided by the server, being suitable with a result of information transmitted by the home appliance. |
| US10510107B1 |
System, method, and computer readable media for payment cards with updatable merchant data
Systems and methods for operatively coupling a payment card to a customer database are disclosed. A financial institution computing system includes a customer database, a network interface circuit enabling the financial institution computing system to exchange information over a network, and a data circuit. The customer database stores financial information and non-financial information received from at least one merchant computing system. The data circuit receives non-financial information associated with a customer from at least one merchant computing system and updates the non-financial information in the customer database. The data circuit receives a transaction request generated by the customer at a transaction terminal using a payment card corresponding to a payment card account. The data circuit transmits an approval or a denial of the transaction request and at least some of the non-financial information in the customer database to the transaction terminal to update non-financial information on the payment card. |
| US10510105B2 |
Traveler recommendations
One or more computing devices, systems, and/or methods for providing recommendations to travelers are provided. For example, locational data associated with a device of a user is evaluated to identify a set of location points at which the device was located over time. Location point pairings are generated from the set of location points, where a location point pairing may comprise a departure location point and an arrival location point. The location point pairings are filtered based upon various criteria to remove location point pairings that are not indicative of air flight travel (e.g., a location point pairing not satisfying an air flight speed threshold or an air flight travel distance threshold). The user may be determined as an air flight traveler that has recently used air flight travel to reach a destination location. A recommendation of content for the destination location is provided to the user. |
| US10510104B2 |
Devices and methods for acquiring data comparison information
Devices and methods are provided for acquiring data comparison information. For example, a session window of a preset account is switched to in a social networking application, wherein the preset account is configured to provide an inquiry service for a target account; first commodity information for price comparison input into the session window by a user is acquired, wherein the first commodity information is sent to the preset account by the target account and the target account corresponds to a client account of the social networking application used by the user; the first commodity information for price comparison is sent to a server, so that the server determines whether a price comparison result associated with the first commodity information for price comparison is saved; the price comparison result sent by the server is received; and the price comparison result is displayed in the session window. |
| US10510101B2 |
Merchant management system for adaptive pricing
A merchant management system aims to make product sales by multiple merchants more efficient so that the resulting savings can be passed down to consumers. Specifically, the merchant management system evaluates discounts that the consumer may be eligible for (e.g., being within a certain shipping distance, buying multiple units, or waiving the ability to return the item) in order to present the consumer with the lowest price available. Additionally, the merchant management system may price a product in light of other products and pass down any savings that result from purchasing multiple products from the same merchant (e.g., reduced shipping costs for shipping multiple products in the same box). |
| US10510100B2 |
Impression tracking
A demand side platform DSP is provided which will receive an advertisement bid win notification comprising identity information and time information, The DSP will check the time information to make sure the notification is not too old. If not the DSP will check if the identity information is in a cache. If not, a check is made against a database. If not, the bid win is recorded in the cache and the database. |
| US10510099B2 |
Method and apparatus for providing content in a communication system
Aspects of the subject disclosure may include, for example, a device including a memory and a processor for performing operations including accessing a user persona comprising a plurality of attributes and a plurality of content preferences of a user of a communication device, presenting at an interactive site a plurality of content suggestions that are generated according to the user persona, receiving a content selection from a presentation of the plurality of content suggestions at the interactive site, and updating the plurality of content preferences of the user persona according to the content selection. Other embodiments are disclosed. |
| US10510095B2 |
Searching based on a local density of entities
A method executed by a computing device includes receiving a search criteria and location data from a user device in communication with the computing device, determining a user location based on the location data, and determining a geographical density of entities about the user location. The method optionally includes selecting one or more access mechanisms based on the search criteria and the geographical density. Each access mechanism, when executed by the user device, causes the user device to access a resource identified by the access mechanism. The method also optionally includes transmitting search results containing the one or more selected access mechanisms from the computing device to the user device. |
| US10510094B2 |
Method for transmitting information to device on a network based upon information associated with a different device on the network
Internet advertising to users of web browser personal computer systems is a very large and mature industry. However, many new digital devices such as cellular telephones, table computer systems, and video game console are now presenting an even larger internet advertising market. Although the techniques used for targeting advertisements to web browsers on personal computers are sophisticated, the techniques for accurately targeting internet advertisements to these new digital devices are limited. To improve the quality of targeting advertisements on new digital devices a set of techniques for accurately pairing digital identities is disclosed. Once various digital identities are linked, all of the accumulated digital profile information from these linked digital identities may be used to accurately select advertisements for all of the linked digital devices. |
| US10510089B2 |
Computing estimated value of providing service among geographical regions
A system predicts a value estimate for a user who provides a service that involves moving among geographical regions (e.g., a transportation service). The system determines the value estimate by identifying a sequence of time periods, each time period having an associated set of geographical regions. Possible transitions between geographical regions in different time periods are analyzed, for example, using statistical or machine-learned models, to determine likelihoods that the user will move between the geographical regions from one time period to another, and to determine expected values for a transition. Such models may be trained or developed using historical service data and user profile data stored by the system. Transitions are analyzed over a sequence of time periods to determine accumulated values associated with estimated overall values for each geographical region. The system predicts an overall value estimate for the user based on the accumulated values. |
| US10510088B2 |
Leveraging an artificial intelligence engine to generate customer-specific user experiences based on real-time analysis of customer responses to recommendations
Embodiments leverage an artificial intelligence engine to generate customer-specific user experiences based on real-time analysis of customer responses to recommend and/or experienced features. Some embodiments access a profile of an end user comprising at least one first characteristic associated with the end user and extract end user information from a database of an entity server; identify a first trend related to resource utilization and/or management implemented by the end user based on the extracted end user information; determine an opportunity based on the identified first trend; in response to determining the opportunity, transmit control signals configured to cause the graphical user interface of the device of the end user to display graphically at least one recommendation based on the determined opportunity to the end user; and receive an input selecting or declining at least one recommendation. These inputs may correlate to a modified interface experience. |
| US10510087B2 |
Method and apparatus for conducting an information brokering service
A system and method is provided that provides an early indication of consensus of opinion among a number of users regarding an event or observation indicated by a user. The opinion can be interesting to an information consumer, for determining the outcome of the consensus relating to the event or observation, or for performing surveillance or survey of a particular issue or subject. Such recognition of early events or observations can be useful in different areas, such as healthcare, finance, etc., where initial observations, if provided early, allow resulting decisions to be made much earlier. The opinion can, for instance, be used as an early indicator of problem with a product, company, etc. that would permit an information consumer to perform an action at a much earlier point than if he/she relied on traditional sources of information. Thus, such opinion information can be invaluable as a tool for monitoring events. |
| US10510078B2 |
Anomaly detection in groups of transactions
A payment processing system continuously processes transactions. A group of transactions satisfying criteria within a recent measurement window are extracted from transaction data. A second group of transactions satisfying the criteria within a past baseline window are also extracted. An attribute of transactions is selected for analysis and a risk metric value is calculated for transactions in the measurement window having a particular attribute value. The same risk metric is used to calculate a baseline value for transactions in the baseline window having the same attribute value. The baseline value may be normalized and adjusted. The risk metric value is compared to the baseline value and an alert is generated if the risk metric value is greater. Any of a variety of risk metrics are used. Total dollar amount and total order count from the measurement window compared to similar from the baseline window are also used to inform the alert. |
| US10510074B1 |
One-tap payment using a contactless card
One-tap payment using a contactless card. An application may output an indication specifying to tap a contactless card to complete a transaction initiated in the application. The application may receive encrypted data generated by the contactless card based on a private key stored in the contactless card. The application may transmit a merchant identifier, a transaction identifier, and the encrypted data to an authentication server. The authentication server may verify the encrypted data based on the private key for the contactless card stored by the authentication server. A virtual account number server may generate a virtual account number. A merchant server may receive the merchant identifier, the transaction identifier, the virtual account number, an expiration date, and a card verification value (CVV), and process the transaction using the transaction identifier, the virtual account number, the expiration date, and the CVV. |
| US10510073B2 |
Methods and systems for provisioning mobile devices with payment credentials
Embodiments are described that are directed to optimizing the provisioning of payment account credentials to mobile devices utilizing mobile wallets. In some embodiments, one of multiple provisioning schemes may be selectively chosen for payment account credential provisioning based upon a determined risk involved with a particular provisioning request. A low risk provisioning request leads to an immediate provisioning of a payment credential, whereas a provisioning request of high risk results in the provisioning request being denied. In some embodiments, medium risk provisioning requests will cause an additional user authentication to be performed before the payment account provisioning is finalized. The additional user authentication may occur using a separate communication channel than the channel in which the provisioning request was received. |
| US10510071B2 |
Systems and methods for generating and administering mobile applications using pre-loaded tokens
The disclosed embodiments include computerized methods and systems that provide mobile application programs to devices of users and that administer these mobile application programs using tokens “pre-loaded” with data. In one aspect, the disclosed embodiments may generate a mobile payment product, such as a mobile wallet, that is “pre-loaded” with eligible financial products. For example, the disclosed embodiments may receive a request from a user device to obtain an application program that administers the mobile wallet, and in response to the received request, may obtain information identifying one or more financial products eligible for inclusion in the mobile wallet. The disclosed embodiments may generate a mobile wallet token based on the eligible financial product information and store the mobile wallet token in cloud-based storage. The user device may, upon authenticating the user, obtain the mobile wallet token and provision the mobile wallet with the eligible financial products. |
| US10510070B2 |
System, method, and apparatus for a dynamic transaction card
A dynamic transaction card that includes a number of layers, each of which may be interconnected to one another. For example, a dynamic transaction card may include an outer layer, a potting layer, a sensor layer, a display layer (including, for example, LEDs, a dot matrix display, and the like), a microcontroller/microprocessor storing firmware, Java applets, Java applet integration, and the like, an EMV processor, an energy storage component, one or more antenna (e.g., Bluetooth antenna, NFC antenna, and the like), a power management component, a flexible printed circuit board (PCB), a chassis, and/or a card backing layer. A display layer may include enhanced features such as the use of LED display components as a photosensor. |
| US10510065B2 |
Interacting with an automated teller machine using a user device
A device may receive an indication that an ATM transaction is to be conducted, display prompt(s) for a user to input user authentication credential information and to select an ATM transaction type, detect user input(s) that include a user authentication credential and a selection of a particular ATM transaction type, and receive, from an ATM device, a request to establish a communication session. The ATM device may include a sync button to initiate communicative coupling of the ATM device and the user device. The request may be based on a user selection of the sync button. The device may communicatively couple to the ATM device, and provide, to the ATM device, the user authentication credential and data regarding the particular ATM transaction type to cause the ATM device to perform the ATM transaction. The device may display information regarding the ATM transaction. |
| US10510060B2 |
Systems, methods and apparatus for payment terminal management
Systems, methods and apparatus are disclosed for remote management of payment terminals. Public keys, or other security elements can be received from a certification authority and distributed to the payment terminals. A merchant, or other entity affiliated with the payment terminals, can monitor the status of the software and security elements of the payment terminals. |
| US10510056B2 |
Method and system for multiple payment applications
Methods and systems for receiving a proximity payment account number (PPAN) with payment transaction data for a payment transaction from a mobile device, the PPAN selected from at least one PPAN; mapping the received PPAN to a primary account number (PAN); generating an authorization request for the payment transaction based on the PAN and the payment transaction data; receiving an authorization response message; and providing an output including the authorization response message and the PPAN. |
| US10510055B2 |
Ensuring secure access by a service provider to one of a plurality of mobile electronic wallets
Facilitating exclusive access to a workflow of a service provider via a mobile wallet interface involves, within a client runtime environment, activating through the interface a service provider-specific application so that the service provider-specific application has exclusive access to a secure electronic transaction workflow of the service provider associated with at least one of the service provider-specific application and the wallet, while being denied access by the client runtime environment to any other service provider services or resources. |
| US10510050B2 |
Meetings and events coordinating system and method
Providing dynamic scheduling services without sharing calendar content, involving retrieving real time availability data and terms applied to calendar time cubes for an invitation to an event with one or more invited users, simultaneously synchronizing between calendars of the invited users in a meeting and event coordinating server to find a combination of common available matching time cubes while considering the terms including arrival time calculations (the common available matching time cubes defined as either “free”, “occupied”, “pending”, ane having a lower level of importance than the event currently created), setting the state of the matched time cubes as occupied at the calendar of each invited user; and rescheduling an event that was previously associated with the sequence of “occupied”, “pending” states with the lower level of importance, the already existing events being automatically subject to changes constantly and immediately. |
| US10510044B2 |
Project management system providing digital form-based inspections in the field
Systems and methods provide graphical form-based inspections in the field. The system includes a means for allowing a user to access digitized paper forms, such as inspection forms, in both a simplified, easy-to-complete list of questions and fields displayed in a linear form view, as well as an interactive graphical form completely replicated from the original paper document displayed in a graphical view. The system allows the user to toggle between the linear form and graphical views of the same form on the fly during an inspection process, thereby improving user interaction with and completion of inspection form or also can have a preferred view method based on limitations of a computer device or complexity of the form. The system further includes a means for allow the user to create customized workflows for the completion and tracking of inspection processes. |
| US10510039B2 |
Dynamic assignment of media advertising orders to broadcast inventory
A planning system can receive media advertising orders including flexibility attributes indicating whether the orders are flexible with regard to various different circumstances. The planning system can obtain both booked an unbooked inventory from a traffic and billing system, and determine associations or re-associations between the advertising orders and the booked and unbooked inventory based on the flexibility attributes. The planning system can then generate a non-guaranteed order including the associations or re-associations, and transmit the order to media delivery system. The planning system can obtain feedback and/or real time data that can be used to reassess existing associations, and in some cases adjust the flexibility attribute values. |
| US10510038B2 |
Computer implemented system and method for recognizing and counting products within images
The system and method for recognizing and counting products within images is disclosed. The products are recognized by carrying out a nearest-neighbor search in the template feature space using a k-d tree and the product count is then obtained by using a maximum feature repeatability index for each identified feature. The system also obtains product arrangement by fitting bounding boxes around each identified product. The count of boxes thus obtained may also provide the exact number of discrete products visible in an image. A second stage of grid-based search is also carried out in the neighborhood of each detected product to detect new products that might have been missed out in the previous step. This detection is based on a confidence measure including information like histogram matching and spatial location of products. This system is also useful in verifying planogram compliance for a given product. |
| US10510035B2 |
Limited access invitation handling at a smart-home
This patent specification relates to apparatus, systems, methods, and related computer program products for providing home security/smart home objectives. More particularly, this patent specification relates to a plurality of devices, including intelligent, multi-sensing, network-connected devices, that communicate with each other and/or with a central server or a cloud-computing system to provide any of a variety of useful home security/smart home objectives. |
| US10510029B2 |
Multi-interval dispatch system tools for enabling dispatchers in power grid control centers to manage changes
A system tool that provides dispatchers in power grid control centers with a capability to manage changes. Included is a user interface and a plurality of scheduler engines. Each scheduler engine is configured to look ahead at different time frames to forecast system conditions and alter generation patterns within the different time frames. A comprehensive operating plan holds schedules generated by the plurality of scheduler engines. A relational database is coupled to the comprehensive operating plan. Input data is initially received from the relational database for each scheduling engine, and thereafter the relational database receives data from the scheduling engines relative to forecast system conditions. |
| US10510025B2 |
Adaptive fraud detection
A computer-implemented method includes receiving a new data record associated with a transaction, and generating, using an adaptive model executed by the computer, a score to represent a likelihood that the transaction is associated with fraud. The adaptive model employs feedback from one or more external data sources, the feedback containing information about one or more previous data records associated with fraud and non-fraud by at least one of the one or more external data sources. Further, the adaptive model uses the information about the one or more previous data records as input variables to update scoring parameters used to generate the score for the new data record. |
| US10510024B2 |
Coordinated disruption handling
Systems, methods, and computer program products for coordinating operation of relevant systems after a passenger itinerary disruption. Responsive to a transfer request being received that includes at least a portion of a new travel itinerary to replace a disrupted travel itinerary of each of multiple passengers, an inventory system automatically updates counters based on the disrupted travel itinerary of each passenger and the new travel itinerary, and a reservation system automatically updates one or more reservation records to reflect an association between each passenger and the new travel itinerary. Thereafter, a ticketing system automatically performs a ticketing process for each passenger relative to the new travel itinerary, and a departure control system automatically transfers passenger data stored for each passenger in association with the disrupted travel itinerary of the passenger to a record associated with the new travel itinerary. |
| US10510022B1 |
Machine learning model feature contribution analytic system
Systems and methods for machine learning, models, and related explainability and interpretability are provided. A computing device determines a contribution of a feature to a predicted value. A feature computation dataset is defined based on a selected next selection vector. A prediction value is computed for each observation vector included in the feature computation dataset using a trained predictive model. An expected value is computed for the selected next selection vector based on the prediction values. The feature computation dataset is at least a partial copy of a training dataset with each variable value replaced in each observation vector included in the feature computation dataset based on the selected next selection vector. Each replaced variable value is replaced with a value included in a predefined query for a respective variable. A Shapley estimate value is computed for each variable. |
| US10510014B2 |
Escalation-compatible processing flows for anti-abuse infrastructures
The disclosed embodiments provide a system for processing user actions with a service. During operation, the system uses a statistical model to obtain a first metric associated with a user action received by a service. Next, the system applies a set of static decisions to the metric and one or more attributes of the user action to determine a first response to the user action. The system then uses a set of dynamic rules to produce a first modification to the first response. Finally, the system generates output for applying the first response to the user action. |
| US10510011B2 |
Fact checking method and system utilizing a curved screen
An efficient fact checking system analyzes and determines the factual accuracy of information and/or characterizes the information by comparing the information with source information. The efficient fact checking system automatically monitors information, processes the information, fact checks the information efficiently and/or provides a status of the information. |
| US10510007B2 |
Systems and methods for generating performance prediction model and estimating execution time for applications
Systems and methods for generating performance prediction model and estimating execution time for applications is provided. The system executes synthetic benchmarks for a first dataset on a first cluster. Each synthetic benchmark includes a MapReduce (MR) job. The system further extracts sensitive parameters for each sub-phase of the MR job, generates a linear regression prediction model for each sub-phase to obtain one or more linear regression prediction models, based on which the system further generates a performance prediction model to be utilized for predicting, using the sensitive parameters, a Hive query execution time of a Directed Acyclic Graph (DAG) of one or more MR jobs executed on a second dataset on a second cluster, wherein the first cluster that includes the first dataset is smaller compared to the second cluster that includes the second dataset. |
| US10510006B2 |
Handling of predictive models based on asset location
Disclosed herein is a computer architecture and software that is configured to modify handling of predictive models by an asset-monitoring system based on a location of an asset. In accordance with example embodiments, the asset-monitoring system may maintain data indicative of a location of interest that represents a location in which operating data from assets should be disregarded. The asset-monitoring system may determine whether an asset is within the location of interest. If so, the asset-monitoring system may disregard operating data for the asset when handling a predictive model related to the operation of the asset. |
| US10510004B2 |
Very deep convolutional neural networks for end-to-end speech recognition
A speech recognition neural network system includes an encoder neural network and a decoder neural network. The encoder neural network generates an encoded sequence from an input acoustic sequence that represents an utterance. The input acoustic sequence includes a respective acoustic feature representation at each of a plurality of input time steps, the encoded sequence includes a respective encoded representation at each of a plurality of time reduced time steps, and the number of time reduced time steps is less than the number of input time steps. The encoder neural network includes a time reduction subnetwork, a convolutional LSTM subnetwork, and a network in network subnetwork. The decoder neural network receives the encoded sequence and processes the encoded sequence to generate, for each position in an output sequence order, a set of substring scores that includes a respective substring score for each substring in a set of substrings. |
| US10509994B1 |
Ring for use in near field communication (NFC) and method of making same
A near field communication (NFC) ring and method of making a ring capable of NFC, the method including the steps of: providing an electrically conductive band with two ends separated by a through slit, fitting an NFC coil having an NFC antenna and NFC chip against a sleeve that is smaller in circumference than the NFC coil and is not electrically conductive; and attaching the sleeve to the inside of the band, thereby forming an NFC enabled ring. |
| US10509989B2 |
Method and apparatus for recognizing characters
A method and an apparatus for recognizing characters using an image are provided. A camera is activated according to a character recognition request and a preview mode is set for displaying an image photographed through the camera in real time. An auto focus of the camera is controlled and an image having a predetermined level of clarity is obtained for character recognition from the images obtained in the preview mode. The image for character recognition is character-recognition-processed so as to extract recognition result data. A final recognition character row is drawn that excludes non-character data from the recognition result data. A first word is combined including at least one character of the final recognition character row and a predetermined maximum number of characters. A dictionary database that stores dictionary information on various languages using the first word is searched, so as to provide the user with the corresponding word. |
| US10509986B2 |
Image similarity determination apparatus and image similarity determination method
An image similarity determination apparatus includes a memory and a processor configured to acquire a first image and a second image, perform selection of a first group and a second group from a plurality of feature points included in the first image and perform selection of a third group and a fourth group from a plurality of feature points included in the second image, calculate feature quantity for each feature point included in the first group and the third group on the basis of luminance and calculate feature quantity for each feature point included in the second group and the fourth group on the basis of hue, and determine similarity between the first image and the second image on the basis of both first comparison of the first group with the third group and second comparison of the second group with the fourth group. |
| US10509983B2 |
Operating device, operating system, operating method, and program therefor
A technique for efficiently calibrating a camera is provided. Reference laser scan data is obtained by scanning a building 131 by a laser scanner 115, which is fixed on a vehicle 100 and has known exterior orientation parameters, while the vehicle 100 travels. An image of the building 131 is photographed at a predetermined timing by an onboard camera 113. Reference point cloud position data, in which the reference laser scan data is described in a coordinate system defined on the vehicle 100 at the predetermined timing, is calculated based on the trajectory the vehicle 100 has traveled. Matching points are selected between feature points in the reference point cloud position data and in the image. Exterior orientation parameters of the camera 113 are calculated based on relative relationships between the reference point cloud position data and image coordinate values in the image of the matching points. |
| US10509982B2 |
On-camera image processing based on image luminance data
A camera system processes images based on image luminance data. The camera system includes an image sensor, an image pipeline, an encoder and a memory. The image sensor converts light incident upon the image sensor into raw image data. The image pipeline converts raw image data into color-space image data and calculates luminance levels of the color-space image data. The encoder can determine one or more of quantization levels, determining GOP structure or reference frame spacing for the color-space image data based on the luminance levels. The memory stores the color-space image data and the luminance levels. |
| US10509979B2 |
Inspection methods and systems
An inspection method and system for inspecting whether there is any liquor in goods is provided. The method includes: acquiring a radiation image of goods being inspected; processing on the radiation image to obtain an ROI; inspecting on the ROI using a liquor goods inspection model to determine if the ROI of the radiation image contains liquor goods. The above solution performs liquor inspection on scanned images of goods, especially containers, so as to intelligently assist the image inspectors. |