| Document | Document Title |
|---|---|
| US10277542B2 |
Embedding actionable content in electronic communication
Embedding actionable content in electronic communication includes associating an embedding gadget with an electronic message and modifying the electronic message based on the embedding gadget. |
| US10277540B2 |
Systems and methods for digital video journaling
The invention includes systems and methods of digital video journaling for promoting more meaningful interactions on online social networks. By introducing elements of offline communication including body language, eye contact, and voice tone and inflection, into online communications, the digital journaling platform provides a new social network communication experience. Additionally, the digital video journaling platform described herein focuses content delivery around human emotions such as happiness, sadness, anger, and disgust to enable more personal and meaningful online communication. By combining this emotional emphasis and streaming video conversation platform with image processing techniques, this invention enables unique methods of assembling machine inferred emotional profiles including emotional intensity and affect duration analytics. |
| US10277538B2 |
Method and apparatus for creating booklets and the use of the same
Techniques for creating electronic messages with interactive images and audio are described. The electronic messages can be shared with another user or a group of users, published to a whitewall and iteratively commented in voice. According to one aspect of the present invention, an image is interactively marked while recording a spoken commentary to accompany marks provided by a user. A result of such a electronic message is referred to as a booklet herein. |
| US10277537B2 |
Predicting and updating availability status of a user
Predicting and notifying availability status of a user may include determining, using a processor, an availability status of a user according to historical data for the user and automatically updating the availability status of the user using the processor. |
| US10277536B1 |
Concepts for providing notifications for events of interest
Computer program products, methods, systems, apparatus, and computing entities are provided. In one embodiment, the location of computing entities can be monitored to determine whether they are within a configurable distance from each other. In another embodiment, direct communications with each other can be monitored. The locations or communications can be used to initiate specific actions/steps. |
| US10277527B1 |
Utilization of network tunnel signaling for connection request rate limitation
A device may determine an acceptance rate threshold associated with a network server. The acceptance rate threshold may be a handling capacity of the network server for processing connection requests. The device may determine that a rate at which a set of connection requests are being received exceeds the acceptance rate threshold. The device may cause a portion of the set of connection requests to be transmitted to the network server via a network tunnel based on determining that the rate at which the set of connection requests are being received exceeds the acceptance rate threshold. The portion of the set of connection requests may be caused to be transmitted at a rate not exceeding the acceptance rate threshold. |
| US10277525B2 |
Method and apparatus for disaggregated overlays via application services profiles
Example embodiments of the present invention relate to a method, a system, and a computer program product for creating a dynamically composed compute node. The method includes receiving an application characteristic and generating an infrastructure allocation request according to the application characteristic. The infrastructure allocation request then may be forwarded to a management system associated with a disaggregated infrastructure. |
| US10277521B2 |
Authorizing an action request in a networked computing environment
An approach for authorizing an action requested by a user in a networked computing environment (e.g., a cloud computing environment) is provided. In a typical embodiment, a request for a particular action associated with a computing resource is received. The connected systems which may be affected by the requested action are identified. The actual users of the connected systems are determined. A response from each of the actual users is requested. The responses are collected and weighted to determine if authorization for the requested action is granted. |
| US10277509B2 |
Data processing method executed by network apparatus, and related device
A data processing method and a related device are provided. The method includes receiving, by the ith processing circuit in a first circuit set, a first packet header and data D(1, i−1), obtaining data D′(1, i) based on a first field in the first packet header, and sending the first packet header and data D(1, i) to the (i+1)th processing circuit in the first circuit set, where the data D(1, i) is obtained based on the data D(1, i−1) and the data D′(1, i). The method also includes sending, by the ith processing circuit in the first circuit set, the data D(1, i) to the (i+1)th processing circuit in a second circuit set and sending, by the ith processing circuit in the second circuit set, a second packet header to the (i+1)th processing circuit in the second circuit set. |
| US10277503B2 |
Cross-domain service request placement in a software defined environment (SDE)
Embodiments relate to cross-domain service request placement in a software defined environment (SDE). An aspect includes receiving a service request corresponding to a job to be completed in the SDE. Another aspect includes determining a first computer device in a first domain, and a second computer device in a second domain, that are capable of performing the service request. Another aspect includes determining, for the first and second computer devices, first and second pluralities of available service classes. Another aspect includes determining, for the first and second computer devices, a first and second plurality of costs of performing the service request, wherein each of the first and second plurality of costs corresponds to a single respective service class. Yet another aspect includes selecting one of the first computer device and the second computer device to perform the service request based on the first and second plurality of costs. |
| US10277501B2 |
Methods for handling conflicts in a multicast routing election
A method for handling of conflicts in a multicast routing election in a multicast network is described herein. The multicast network includes a plurality of multicast network devices. A conflict is detected in a Designated Forwarder (DF) election for a link. |
| US10277498B2 |
Analysis of network performance
Methods and apparatus are disclosed for analyzing performance of a network. The method may comprise: obtaining first and second probe measurements resulting respectively from a test-message being sent from a first node and having a second node as the target thereof, and from a test-message being sent from the second node and having the first node as the target thereof, associated probe response-messages triggered by receipt and local processing of the test-messages at the target nodes thereof being sent back to the senders of the test-messages, the measurements relating to a network performance characteristic in respect of the paths taken by the test-messages and response-messages, and being dependent also on the local processing of the test-messages at the respective target nodes; comparing the measurements, assigning a weighting in respect of at least one of the nodes dependent on the comparison; and determining a network performance analysis measure according to a function dependent on at least one of the probe measurements and on the weighting. |
| US10277497B2 |
Systems and methods for testing electronic devices using master-slave test architectures
A system may include a master test system and a plurality of slave test systems coupled to the master test system and/or each other. The system may include devices under test (DUTs) (also referred to herein as units under test (UUTs)) stored in test slots and coupled to the master test system or specific slave test systems over Ethernet, coaxial, or other cables. Each test slot may include a Faraday cage that shields the contents therein from electromagnetic signals outside the test slot. The master test system and/or the slave test systems may test the DUTs using specific sequences of tests according to testing protocols relevant to those DUTs. One or more test controllers, mobile devices, display devices, and/or input devices may be coupled to the test systems and be used to control specific test protocols performed by the test systems. |
| US10277494B2 |
Device and method for antenna alignment using vibrational positioning
A device and method for antenna alignment using vibrational positioning are provided. The device comprises: a controller; a vibrating device; and an antenna. The controller configured monitors a data quality parameter of the antenna. When the data quality parameter meets a first threshold condition, the controller activates the vibrating device. When a second threshold condition is met, after the vibrating device is activated, the controller deactivates the vibrating device. Activation of the vibrating device can cause the device to vibrate to move the device into a minimum energy position on a docking station to align the antenna with a respective antenna of the docking station. The docking station can comprise a wireless charging pad and the alignment of the antenna (e.g. a loop antenna and the like) with the respective antenna of the docking station can assist with charging efficiency of a battery of the device. |
| US10277490B2 |
Monitoring inter-site bandwidth for rebuilding
A dispersed storage network (DSN) includes a DSN memory employing multiple distributed storage (DS) units, e.g., memory devices, operating at multiple different physical sites, with each site having one or more of the memory devices. A monitoring entity can monitor the sites to determine a data loss rate and a threshold communication bandwidth, e.g., a bandwidth available for rebuilding encoded data slices, associated with particular sites. If the data loss rate of a particular site exceeds the threshold communication bandwidth, the monitoring unit can send an alert message notifying, for example, a DSN controller, an integrity processing unit, the DSN memory, about the determination, so that corrective action can be taken. |
| US10277487B2 |
Systems and methods for maintaining network service levels
Described are methods and system for maintaining network service levels. In general, the system identifies, using records of network incidents, a first plurality of network incidents occurring over a first portion of a measurement period and a second plurality of network incidents occurring over a subsequent second portion of the measurement period. The system then determines a plurality of remaining incidence tolerance limits based on an impact of the first and second pluralities of network incidents on corresponding sets of incidence tolerance limits for the measurement period, generates severity metric values for at least a subset of the second network incidents based on aggregate impact characteristics of one or more of the second plurality of network incidents weighted by remaining incidence tolerance limits associated with each of the second network incidents in the subset of the second network incidents, and selects one or more network incidents for remediation. |
| US10277485B1 |
Network device testing using non-destructive techniques
A network topology service receives a request to validate a plurality of network connections of a network topology specified by an administrator or other network technician. The network topology service evaluates the network topology to determine the structure of the network topology, which is used to select an algorithm for organizing the network connections into one or more groups. The network topology service uses these groups to perform one or more non-destructive tests on network devices associated with the plurality of network connections in a manner that does not cause disruption to the network connections. The network topology service compiles the results of these one or more tests and provides these results to the administrator or other network technician. |
| US10277483B2 |
Apparatus for transmitting/receiving data and system comprising the same
Disclosed embodiments relate to apparatuses, systems, and methods for transmitting/receiving data. In some embodiments, a system includes a server operative to collect data from remote apparatuses and transmit the collected data to a client group, and at least one client group including at least one client, the client group checking data received from the server and acquiring data requested by the client. |
| US10277475B2 |
System and method for dynamically testing networked target systems
A computerized method and system for conducting performance testing of a networked target system (NTS). The method comprises receiving at least one instruction and at least one parameter generated respective of a plurality of actions provided in a received test specification; testing the performance of the NTS using the at least one instruction and the at least one parameter; and gathering information respective of the performance testing of the NTS. |
| US10277474B2 |
Computer network planning
The disclosure is directed to a network planning tool for planning a topology of a computer network, e.g., for provisioning network capacity. The network planning tool evaluates various factors, e.g., demand projections between a pair of nodes, existing network topology, existing circuits, failure scenarios, and other constraints, and generates a set of circuits that satisfies various demand projections. The set of circuits is robust under failure scenarios and minimizes latency, costs and/or power consumption involved in satisfying the demand projections. The tool assigns each of the circuits to a spectral resource of a physical communication link, e.g., a wavelength of a fiber optic cable, using which it can propagate data traffic between the pair of nodes. |
| US10277470B2 |
Methods and apparatus to identify network topologies
Methods and apparatus to identify network topologies are disclosed. An example method includes determining a set of network nodes in a set of end-to-end communication paths between a pair of designated nodes based on a configuration of the network and locations of the designated nodes within the network. The set of network nodes excludes a subset of the network nodes that are present in all the end-to-end communication paths. A binary decision table is generated that includes up to 2N entries where N is the number of nodes in the set of network nodes. The respective nodes are represented in respective columns of the binary decision table, and data in the row of the columns indicates distinct combinations of the network nodes. Performance measurement commands are generated for a set of valid combinations of the network nodes that enable monitoring of the network according to the configuration of the network. |
| US10277466B2 |
Network aware dynamic orchestration method and system for multicast services
Presented herein is an exemplified system and method that facilitate network-aware consolidation, by orchestration, of similar sets of virtualized multicast-traffic receivers and/or sources (e.g., Virtual Machines) under a common network fabric element (e.g., same leaf switch and/or spine switch in a data center network fabric), e.g., to reduce network switch work load and/or number of network fabric elements involved with transmission of multicast traffic. The orchestration of scattered- and like-sets of multicast-traffic receivers and/or sources under a common network fabric element (e.g., a single and same leaf switch and/or spine switch) facilitates improvements of the operation of orchestration management technologies and virtualization overlay technologies by, e.g., improving network efficiency for multicast packet switching, reducing control plane traffic (e.g., IGMP queries), and reducing delay- and packet-transfer errors. |
| US10277464B2 |
Client auto-configuration in a multi-switch link aggregation
One embodiment of the present invention provides a switch capable of auto-configuration of client devices for a link aggregation. The switch includes a packet processor, an auto-configuration module, and a link-aggregation management module. During operation, the packet processor extracts an identifier of a client device from a notification message received via a local port. The auto-configuration module, which is coupled to the packet processor, associates the local port with the identifier of the client device. If the packet processor recognizes the identifier of the client device in a message received from a remote switch, the link-aggregation management module forms a multi-switch link aggregation for the client device in conjunction with the remote switch. |
| US10277462B1 |
System, method, and computer program for maintaining versioning of web services associated with a plurality of independent sub-organizations
A system, method, and computer program product are provided for maintaining versioning of web services and XML (Extensible Markup Language) schemas associated with a plurality of independent sub-organizations. In use, a versioning history of a plurality of web services is tracked across a plurality of sub-organizations associated with an organization. Further, a new version of a web service to be introduced in at least one of the sub-organizations is identified. Additionally, a baseline web service version to use for the new version of the web service is automatically identified based on a tracked versioning history of the web service. Furthermore, an existing state of WSDL (Web Services Definition Language) documents and XSD (XML Schema Definition) documents is validated to ensure compliance with a dependency scheme associated with the tracked versioning history of the web service. Moreover, the baseline web service version and dependencies to use for the new version of the web service is recommended to a user, and an impact of introducing the new version of the web service is indicated, such that consistency of the versioning history of the plurality of web services across the plurality of sub-organizations is capable of being maintained. |
| US10277461B1 |
Generating network service models
A system may receive network device configuration information associated with a network service. The system may determine multiple settings associated with the network service based on receiving the network device configuration information. The multiple settings may include a common setting and a device-specific setting. The system may generate a first network service model of the network service based on the multiple settings. The first network service model may include multiple nodes corresponding to the multiple settings. The system may re-configure one or more nodes associated with the first network service model, and may generate a second network service model of the network service. The system may generate a user interface template based on the second network service model and may provide the user interface template to a client device for display. The client device may allow a configuration of the multiple settings based on the user interface template. |
| US10277460B2 |
Updating management instructions for bound services in a distributed network management system
Management instructions for a managed servers are updated according to a set of rules included in management policy. A global manager computer receives information describing a change in a bound service executed by the particular managed server. The global manager generates an updated description of the particular managed server is generated by modifying an initial description of the particular managed server according to the received information describing the change in the bound service. The global manager determines currently relevant rules for the particular managed server. If the currently-relevant rules differ from previously-relevant rules, the global manager determines a rule is that should be added. The global manager generates a function-level instruction including a reference to an authorized actor-set of actors permitted to communicate with the bound service. The global manager configures the particular managed server to enforce the function-level instruction. |
| US10277458B2 |
Gateway apparatus and system
A gateway apparatus including a first inter-device interface configured to communicate with a monitoring apparatus; a second inter-device interface configured to communicate with multiple subordinate base station apparatuses; a memory; and a processor coupled to the memory. The processor is configured to generate first configuration information when second configuration information is received from the monitoring apparatus via the first inter-device interface. The processor generates the first configuration information by performing protocol conversion of converting the second configuration information into a format adapted to the second inter-device interface for the multiple base station apparatuses. The processor is further configured to transmit the generated first configuration information to the multiple base station apparatuses via the second inter-device interface, and divide the multiple base station apparatuses into predetermined groups. The processor transmits the first configuration information to the multiple base station apparatuses at a different timing for each of the groups. |
| US10277456B2 |
Network-enabled devices
Disclosed are methods, systems and computer program products for operating and controlling network-enabled devices. A network-enabled device communicates capability information representative of its set of capabilities. The network-enabled device also communicates a status signal indicative of the status of the device. It may be determined that the first network-enabled device is unable or unavailable to perform a function based on a status signal communicated by the first network-enabled device. A second network-enabled device may be identified to assign a failover function to based on the respective capabilities of the second network-enabled devices. |
| US10277454B2 |
Handling failure of stacking system
This application provides a method for deciding on handling a failure of a stacking system, where the method includes: collecting values of a decision parameter for respective groups after the stacking system is divided; and applying a preset reserve strategy according to the values of the decision parameter for the respective groups to decide on one of the groups to be reserved. |
| US10277451B2 |
Control method and apparatus in a mobile automation system
A control method includes: storing, at a control server, respective identifiers for a plurality of sub-regions in a facility; for each sub-region identifier, a location of the sub-region in the facility and an operational constraint associated with a mobile automation apparatus; at the control server: obtaining a job definition indicating a set of the sub-region identifiers and a task; retrieving the locations and the operational constraints corresponding to the set of sub-region identifiers from the repository; allocating the set of sub-region identifiers to a plurality of subsets of sub-region identifiers, each subset having a shared common operational constraint; for each subset of sub-region identifiers, generating a task fragment containing the subset of sub-region identifiers, and the common operational constraint; and sending the task fragments and an identifier of the task to the mobile automation apparatus for performance of the task at each of the set of sub-region identifiers. |
| US10277449B2 |
Method and device for generating non-gaussian interference channel in wireless communication system
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Provided is an operation method of a base station in a wireless communication system. The method comprises: receiving, from a terminal, at least one piece of information among channel quality information on a resource region allocated to the terminal and non-Gaussian information on a nulling region corresponding to the resource region; and determining a modulation order for the terminal, a code rate, a ratio of the resource region to the nulling region based on the channel quality information and the non-Gaussian information. |
| US10277448B1 |
Method for hierarchical modulation with vector processing
A constellation mapping method, system, and apparatus are provided for mapping a received bit stream of data to a higher order symbol vector by processing a first set of selected bits from the received bit stream with a quadrant selector to identify a first quadrant offset vector corresponding a higher order quadrant in which an intended symbol is to be mapped, processing a second set of selected bits from the received bit stream with a 16-QAM mapper to identify a 16-QAM symbol vector, transforming the 16-QAM symbol vector into a transformed 16 QAM symbol vector based on the identified higher order quadrant, and combining the transformed 16-QAM symbol vector with the first quadrant offset vector to map the bit stream of data to a higher order symbol vector. |
| US10277447B2 |
MCS table adaptation for 256-QAM
The present invention relates to adaptive modulation and coding scheme selection and signaling in a communication system. In particular, a modulation and coding scheme to be used for transmission of a data is selected from a set of predetermined modulation and coding schemes. The predetermination of the set is performed by selecting the set from a plurality of predefined sets. The sets have the same size, so that a modulation and coding selection indicator signaled to select the modulation and coding scheme may be advantageously applied to any of the selected sets. Moreover, a second set includes schemes with a modulation not covered by the schemes of a first set, and which is of a higher order than any modulation in the first set. |
| US10277446B2 |
Method and system for compressed sensing joint channel estimation in a cellular communications network
Methods and systems for performing compressed time domain joint channel estimation in a multi-user MIMO wireless network include receiving training signals from a plurality of users, estimating a maximum delay spread for the received data according to a coherence bandwidth of the received data, limiting the received data in the time domain to the estimated maximum delay spread, selecting and estimating an active tap from the limited data set, and subtracting a contribution of the selected active tap from the reduced data set. These steps can be repeated until the residual signal falls below a specified minimum. The network can be a C-RAN network. The training data can be SRS or DMRS data. Limiting the received data ensures that only a few significant taps are analyzed, so that the system is not under determined and can be analyzed for accurate channel estimation using any of several existing algorithms. |
| US10277442B2 |
Data transmission method and apparatus in wireless communication system
A data transmission method by a station (STA) apparatus of a wireless LAN system is disclosed. A data transmission method by an STA apparatus according to the present invention comprises the steps of: generating a physical protocol data unit (PPDU) including a physical preamble and a data field; determining whether to add a padding symbol to the PPDU; generating and adding the padding symbol to the PPDU if adding the padding symbol is determined; and transmitting the PPDU. |
| US10277441B2 |
Uniformity between levels of a multi-level signal
Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. |
| US10277437B2 |
Telematics 5G and multimode 4G and 3G mobile modulation format selectable (MFS) communications
Telematics, telemetry, including medical telemetry and telematics, one or multiple Remote Control (RC) or Universal Remote Control (URC) devices, Multimode 5G, 4G and 3G Mobile Modulation Format Selectable (MFS) communications wireless and wired communication networks, cellular systems and devices with fingerprint signal authentication. Touchscreen and motion detectors are controlling mobile devices. Processing, modulating and transmitting stored analog or digital information, such as stored music or stored video, or stored images, or stored scanned data information or other stored information. Method and system for processing and displaying and/or transmitting in mobile devices a heart rate sensor and/or pacemaker provided signal. Remote Control (RC) or Universal Remote Control (URC) signals and devices are used to control home security systems and automobiles. Device receiving, demodulating and processing spread spectrum signal into processed Orthogonal Frequency Division Multiplexed (OFDM) signal. Mobile devices modulate and transmit processed OFDM signal. Processing spread spectrum or OFDM signals into Bit Rate Adaptable (BRA), Modulation Format Selectable (MFS) and cross-correlated in-phase and quadrature-phase Time Constrained Signal (TCS) wave form and Long Response (LR) filtered cross-correlated filtered baseband signals. Generation of video signals and processing video signals into cross-correlated signals and modulation and transmission of video cross-correlated signals. Photo camera generated photo signal in mobile device is processed with baseband location finder GPS signal. The photo camera generated photo with baseband location finder signal is modulated and transmitted. |
| US10277436B2 |
Transmission apparatus and method, and reception apparatus and method
Modulated signal A is transmitted from a first antenna, and modulated signal B is transmitted from a second antenna. As modulated signal B, modulated symbols S2(i) and S2(i+1) obtained from different data are transmitted at time i and time i+1 respectively. In contrast, as modulated signal A, modulated symbols S1(i) and S1(i)′ obtained by changing the signal point arrangement of the same data are transmitted at time i and time i+1 respectively. As a result the reception quality can be changed intentionally at time i and time i+1, and therefore using the demodulation result of modulated signal A of a time when the reception quality is good enables both modulated signals A and B to be demodulated with good error rate performances. |
| US10277434B2 |
Method for encoding real number M-ary signal and encoding apparatus using same
Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N1 number of M1-ary signals, a second signal generator which receives the second input code and generates N2 number of M2-ary signals, and a first time division multiplexing module which temporally multiplexes the N1 number of M1-ary signals and the N2 number of M2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A2/A1) used for M1-ary and M2-ary signals to minimize a transmission error rate. |
| US10277429B2 |
Codebook including phase rotation between layers
Various aspects of the disclosure relate to a codebook design that defines phase rotation on one or more layers of a codebook. This codebook may be used, for example, for sparse code multiple access (SCMA) encoding. One feature pertains to a method of communication that includes receiving at least one input signal, and mapping each of the at least one input signal to a corresponding layer of a codebook, where the codebook defines phase rotation between the layers. The method may further include generating a coded signal for each of the at least one input signal on each corresponding layer based on the codebook, and generating an output signal based on each generated coded signal. |
| US10277425B2 |
Protection of ranging sounding signals from physical level attacks
Generally, the described techniques provide for protection mechanisms for sounding training signals transmitted between wireless devices when performing ranging sounding estimation. For example, sounding training signals may be encoded to include a sequence of phase rotations or cyclic shifts to protect the sounding training signal from peer devices. In some cases, encoding information associated with a long training field (LTF) may be transmitted either before or after the LTF is transmitted. Additionally or alternatively, a time delay may be introduced to the sounding training signal, where timing information may be removed from one or more fields of the sounding training signal and the time delay may be appended to an interframe spacing. Alternatively, a frame may be split into multiple frames with the sounding training signal in a first frame, and timing information in a second frame that is offset in time from the first frame. |
| US10277422B2 |
Virtual port support in a logical switch architecture
A tool for assigning virtual port channels to one or more logical switch routers in a distributed system. The tool receives, by one or more computer processors, a request to assign a virtual port channel to a second logical switch router. The tool sends, by one or more computer processors, a request to negotiate a link-down on the channel on a first logical switch router to a universal fiber port on the first logical switch router for processing. The tool sends, by one or more computer processors, a request to create the channel on the second logical switch router to a second interface manager on the second logical switch router for processing. The tool sends, by one or more computer processors, a request to negotiate a link up on the channel on the second logical switch router to the universal fiber port on the first logical switch router for processing. |
| US10277414B2 |
Communication gateway services in a networked message distribution system
Systems for specialized high-performance electronic messaging campaigns using multiple communication partner channels. Electronic messages are sent to a plurality of differing electronic messaging communication systems using a network communication interface component that is configured to interface with individual ones of the plurality of differing electronic messaging communication systems using individualized script files and individualized parameter files. A network communication interface component is initialized with a first set of configuration instructions using a script input port and a parameter input port. The configured network communication interface component sends an electronic message to a first electronic messaging communication system using the first set of configuration instructions. The network communication interface component is initialized using a second set of configuration instructions, after which electronic messages are sent to a second electronic messaging communication system using the second set of configuration instructions. |
| US10277412B2 |
Meeting invitee as proxy
An electronic invitation, including invitation proxy information, for a meeting is communicated to at least a first and a second invitee. A response is received from the first invitee including response proxy information indicating that the response to the invitation includes a request to proxy for the second invitee. Updating, in a memory, using the response proxy information, an attendance register to indicate that the first invitee will attend the meeting and that the first invitee may proxy for the second invitee. Communicating a proxy confirmation request to the second invitee and receiving a proxy confirmation response including proxy confirmation information. The attendance register is updated, in the memory, using the proxy confirmation information, to indicate that the second invitee will not attend the meeting and that the first invitee will proxy for the second invitee. |
| US10277410B2 |
Use of a bus line to transmit alternative signal coding
A vehicle module for a vehicle includes one or more sensors, which are configured to record sensor data in an operating mode of the vehicle module, and are configured to adopt a plurality of discrete states in an energy saving mode in order to provide a basic function of the vehicle module in the energy saving mode of the vehicle module. The vehicle module further has an interface for a data line to transmit the sensor data to a control device of the vehicle. In addition, the vehicle module has an energy saving mode switch which is configured to connect the one or more sensors in the energy saving mode to the interface for the data line in such a way that information regarding a state of the plurality of discrete states can be transmitted to the control device via the data line. |
| US10277409B2 |
Authenticating mobile applications using policy files
Examples of techniques for authenticating mobile applications are described herein. A method includes receiving, via a first server, a key pair and a policy file associated with a mobile service from a second server. Authentication of the mobile application is performed based on the key pair and the policy file. A scope token is generated with an application scope in response to authenticating the mobile application. Authentication of a client device is performed corresponding to the mobile application and a user to generate a doubly-authenticated scope token including a device scope and application authenticity scope. The doubly-authenticated scope token is sent to a security gateway for user authentication. A trebly-authenticated scope token is received with a grant token request and a grant token is sent to the mobile application. The grant token is received from the mobile application. An access token is generated and sent to the mobile application. |
| US10277403B2 |
Digital signature method and apparatus
A method for signing and subsequently verifying a digital message, including the following steps: generating an irreducible monic polynomial f(x) of degree n in a ring Fq[x]; generating an irreducible monic polynomial F(y) of degree n in a ring Fq[y]; producing first and second finite fields as Fq[x]/(f(x)) and Fq[y]/(F(y)), respectively; producing a secret isomorphism from the first finite field to the second finite field; producing and publishing a public key that depends on F(y); producing a private key that depends on the secret isomorphism; producing a message digest by applying a hash function to the digital message and the public key; producing a digital signature using the message digest and the private key; and performing a verification procedure utilizing the digital signature and the public key. |
| US10277402B2 |
Digitally signing a document
For digitally signing a document, an apparatus, method, and computer program product are disclosed. The apparatus includes a processor and a memory that stores code, executable by the processor, including code that: detects a trigger, searches a digital document for a user signature in response to the trigger, and applies a digital signature to the digital document in response to the digital document including a user signature. In some embodiments, the digital signature may be based on the user signature. |
| US10277401B2 |
Systems and methods for authenticating and providing anti-counterfeiting features for important documents
A method for authenticating a document comprises obtaining the contents of a document, obtaining biometric characteristics from an individual, forming a message based on the contents of the document and the biometric characteristics of the individual, generating a digital signature based on the message and a key, and writing the digital signature to an Radio Frequency Identification (RFID) tag affixed to the document. |
| US10277397B2 |
E-mail message authentication extending standards complaint techniques
A system and method for e-mail authentication. The method includes aggregating a plurality of headers associated with an e-mail message and transmitting the aggregated plurality of headers to a validation service. A validation response is then received from the validation service. The e-mail is authenticated based on the validation response. |
| US10277396B2 |
Watermarking for data integrity
Methods, systems, and apparatus for ensuring data integrity are disclosed. A data container structure is obtained, the data container structure containing data and a source identifier of a first hardware component. The data container structure is modified, using a header processing device, to include a component signature and an identifier of a second hardware component. |
| US10277391B2 |
Encryption device, encryption method, decryption device, and decryption method
There is provided an encryption device including a data encryption unit configured to conduct encryption on the basis of a white box model in which at least a part of a plurality of round functions for sequentially conducting encryption processing on an input value is tabulated, and input and output values of the round function are recognizable from an outside. The plurality of round functions each have an encryption function that is tabulated and encrypts an input value in a black box model in which input and output values are recognizable from the outside and an intermediate value is not recognizable from the outside. |
| US10277384B2 |
Intermediate distribution frame for distributed radio heads
Embodiments herein describe using an intermediate distribution frame (IDF) which is connected between a central controller and a plurality radio heads which each include at least one antenna for wireless communication with a user device. Instead of running separate cables to each of the radio heads, a single cable can be used to connect the IDF to the central controller and then separate cables can be used to connect the IDF to the radio heads. If the IDF is disposed near the radio heads, the amount of cables can be reduced. Moreover, the IDF may recover a clock signal used by the central controller and forward that clock to the plurality of radio head in order to synchronize the radio heads to the central controller. |
| US10277383B2 |
Access point (AP), station (STA) and method for allocation of resources for full-duplex (FD) communication in high-efficiency (HE) arrangements
Embodiments of an access point (AP), station (STA) and method for full-duplex (FD) communication are generally described herein. The AP may contend for a transmission opportunity (TXOP) during which the AP is to control access to channel resources. During the TXOP, the AP may request to receive uplink data demands from a first group of STAs; receive the uplink data demands; allocate, based at least partly on the uplink data demands, resource units (RUs) of the channel resources for an OFDMA transmission of uplink data; and schedule a full-duplex (FD) communication in which the AP is to use overlapping portions of the channel resources during overlapping time periods of the TXOP to receive the uplink data and to transmit downlink data to a second group of one or more STAs. |
| US10277382B2 |
Full duplex reconfigurable antenna self-interference cancellation systems
Embodiments of transceivers with one or more reconfigurable antennas are described. In one embodiment, a reconfigurable antenna transceiver includes a transmit chain, a receive chain, and a reconfigurable antenna having a plurality of reconfigurable modes. The transceiver may also include an antenna controller configured to set a mode of the reconfigurable antenna. According to other aspects, the transceiver may also include a signal processor configured to transmit a set of training symbols during a training interval. The antenna controller may be further configured to select a respective mode of the reconfigurable antenna for each training symbol in the set of training symbols. Additionally, the antenna controller may be configured to calculate a received Signal-of-Interest to Interferer Ratio (SIR) for each training symbol of the set of training symbols. In this context, a system utilizing a reconfigurable antenna may achieve significant rate improvement compared to half-duplex systems. |
| US10277381B2 |
Receiver path distortion mitigation using adaptive filter feedback
A duplex communication system includes a duplexer for transmitting and receiving signals, a transmitter part connected to the duplexer, and a receiver part connected to the duplexer, the receiver part comprising an amplifier for amplifying a received signal to provide an amplified received signal and a demodulator for downconverting the amplified received signal, and a second-order intermodulation distortion (IMD2) compensation module for compensating for second-order intermodulation distortion. The system also includes an adaptive filtering module that obtains a transmitter reference signal, generates filter coefficients for the IMD2compensation module and also adjusts a direct current (DC) bias of the demodulator based on the reference signal. |
| US10277379B2 |
UE, network node and methods of assisting measurements in mixed signal configuration
A method in a UE for adapting a radio procedure is provided. The UE obtains information about signal configurations indicating: whether or not a DL RS, transmitted in cells on a first carrier frequency of a first carrier use the same one of a first and a second signal configuration, or whether or not the DL RS transmitted in the cells on the first carrier frequency use the same one of the first and the second signal configuration as that used for DL RS transmitted in a serving cell of the UE on the first carrier frequency. The first signal configuration includes the DL RS not being transmitted in every subframe. The second signal configuration includes the DL RS being transmitted in every subframe and also in every resource block over an entire channel bandwidth of a neighbor cell. The UE adapts a radio procedure based on the information. |
| US10277375B2 |
Method and apparatus for transmitting ack/nack signals using multiple antenna ports
A method for transmitting and receiving a signal by a terminal in a wireless communication system, according to one embodiment of the present invention, comprises the steps of: transmitting uplink data to a base station; and receiving an acknowledgement of reception of the uplink data, wherein a first area, to which the acknowledgement of reception is transmitted, is determined in such a manner that a difference value between the number of REs, to which a first antenna port is allocated, and the number of REs, to which a second antenna port is allocated, is a predetermined value or less. |
| US10277368B2 |
Method for transmitting uplink frame in wireless local area network and wireless device using the same
According to an embodiment of the present specification, a method for transmitting an uplink frame in a wireless local area network (WLAN) system and performed by a user station (STA) includes: receiving from an access point (AP) a trigger frame comprising association identifier information for orthogonal frequency division multiple access (OFDMA)-based random access and allocation information indicating a resource unit, wherein the association identifier information indicates any one of a first value irrelevant to whether being associated with the AP, a second value for a first STA group associated with the AP, and a third value for a second STA group un-associated with the AP; and performing a countdown operation according to the association identifier information based on a backoff value which is set in a backoff counter of the user STA in order to transmit the uplink frame. |
| US10277367B2 |
Method and apparatus for scheduling uplink transmissions with reduced latency
A method and apparatus schedule uplink transmissions with reduced latency. A first resource used for transmitting a scheduling request indication in a subframe can be determined at a device. The first resource can be associated with uplink data transmissions using a first TTI length. The first TTI length can include a first number of symbols. A second resource used for transmitting a scheduling request indication in the subframe can be determined. The second resource can be associated with uplink data transmissions using a second TTI length. The second TTI length can include a second number of symbols. The second number of symbols can be smaller than the first number of symbols. A scheduling request indication resource can be selected from one of the first resource and the second resource. The scheduling request indication can be transmitted in the selected scheduling request indication resource in the subframe. |
| US10277363B2 |
Hybrid automatic repeat request acknowledgement transmission method, user equipment, and base station
The present invention provides a hybrid automatic repeat request acknowledgement transmission method, a user equipment, and a base station. The transmission method includes: receiving, by a user equipment, on a first serving cell and in a downlink subframe n−k, PDSCH transmission or a downlink control channel that indicates downlink SPS release, where a duplex mode of the first serving cell is FDD, or all subframes on the first serving cell are downlink subframes, or one radio frame on the first serving cell includes nine downlink subframes and one special subframe; and transmitting, in an uplink subframe n, an HARQ-ACK response corresponding to the first serving cell and the downlink subframe n−k; where n is an integer, k is a positive integer, k belongs to a set K, and the set K is determined according to first HARQ-ACK timing. |
| US10277362B2 |
Optimistic data fetching and rendering
Embodiments are disclosed for fast data fetching and rendering. In some embodiments, in response to receiving a page display request, a system constructs a static, possibly nested query for retrieving all the data to be rendered for the page and stores the query result in a data store. For a future page display request, the system similarly constructs a query and determines whether the query can be resolved from the data store. If not, the system constructs a “diff query” to fetch only the missing data. In some embodiments, in response to a subsequent page update request, the system retrieves from the server all the data likely to be viewed or updated and renders the data changes corresponding to the requested update. The system then submits the data changes to the server and undoes the rendering of the data changes when the server fails to process the data changes. |
| US10277356B2 |
Multi-platform location deception system
Systems and methods for providing a synthetic track to observation devices are provided. In one embodiment, a method can include determining a location range and a time range for a synthetic track to be created by a plurality of platforms. The method can further include determining an emission location and an emission time for each of the platforms of the plurality of platforms based, at least in part, on the location range and the time range. The method can include sending a set of data to each of the plurality of platforms, each respective set of data indicating the emission location and the emission time at which the respective platform is to generate the emission to create the synthetic track. |
| US10277352B2 |
Noise suppression and amplification systems and methods for colorless optical add/drop devices
A method for noise suppression in a colorless optical add/drop system implemented prior to a colorless optical add/drop device includes, subsequent to receiving an optical signal from an optical modem, filtering the optical signal with a wavelength blocking filter to suppress out of band Amplified Stimulated Emission (ASE) in order to prevent noise funneling in the colorless optical add/drop device; and providing the filtered optical signal with the out of band ASE suppressed therein to a multiplexer port in the colorless optical add/drop device. The method can include, prior to the filtering, amplifying the optical signal with a single channel amplifier, wherein the single channel amplifier can include a pump laser shared with one or more additional single channel amplifiers. |
| US10277345B2 |
Interactive entertainment system
In some examples, an interactive audio system includes a receiver for receiving a broadcasted radio frequency (RF) carrier signal. The system may demodulate a portion of the RF carrier signal to receive a demodulated output signal. For example, the demodulated output signal may include a demodulated audio program having embedded data contained within the demodulated audio signal. The system may extract the embedded data from the demodulated audio program. The system may present information related to the extracted embedded data on a display and/or may send at least a portion of the extracted embedded data to another device. |
| US10277344B2 |
System and method for facilitation of a geographically relevant radio station and transmission of related content
A method for populating a plurality of radio stations on a user device, the method includes receiving the plurality of radio stations, including a radio station signal type, receiving a broadcast area for each of the plurality of radio stations, receiving a request for radio service from the user device, the request for radio service comprising a location of the user device, a user device signal threshold, and a user device antenna capability, wherein the user device antenna capability comprises at least one signal type, calculating a plurality of user device ranges for each of the plurality of radio stations, determining, a plurality of in-range radio stations, filtering, the plurality of in-range radio stations based at least in part on the user device signal threshold, further filtering the plurality of in-range radio stations based at least in part on the user device antenna capability, and transmitting the plurality of in-range radio stations, and related content for the each of the plurality of in-range radio stations. |
| US10277342B2 |
Method and apparatus for enhanced playback of content while switching among channels of broadcast or streamed content while being received
A system and method provide an enhanced listening experience for a user of a radio receiver or other device that receives broadcast or streamed content having a plurality of program channels. The method and system buffer designated channels at the receiver and, when switching among channels, play back the buffered designated channels during reception from a selected point therein depending on the channel or other criteria. When switching to a different channel during reception, a user is able to hear content in a buffered program channel with music from the start of a song, for example, whereas content in a channel with news, talk radio, or live sports is played back from live reception, even though the content segments are transmitted at different start times relative to their selected times for playback following a channel change. User controls allow navigation among buffered designated channels during reception. |
| US10277335B2 |
Through-the-earth emergency radio system
There is provided a Through the Earth Emergency Radio (TER) method and apparatus for creating a communications link that can penetrate the earth or other thick, solid barriers. The communication link is used to connect mobile radios or other conventional wireless devices located below ground and on the surface. The through the earth communication link uses a multi-carrier modulation method that minimizes the impact of AC power line noise by locating each carrier between the harmonic frequencies of the AC power line noise. |
| US10277331B1 |
Conversion of RF signals to optical signals for passage through impairment mediums in a wireless communication network
An apparatus and method of propagating wireless signals through an impairment medium using a penetrator device within a wireless communication network is discussed herein. The apparatus and method includes transmitting a first radio frequency (RF) signal from a first point within the wireless communication network and receiving the first RF signal at a first unit of the penetrator device. The method further includes converting, by the first unit of the penetrator device, the RF signal into an optical signal and transmitting the optical signal from the first unit of the penetrator device to a second unit of the penetrator device through the impairment medium. The method also includes converting, by the second unit of the penetrator device, the optical signal into a second RF signal and transmitting, by the second unit of the penetrator device, the second RF signal to a second point within the wireless communication network. |
| US10277329B2 |
Power insertion device for hybrid fiber and power network
A power insertion device includes: an input interface, configured for receiving a fiber connection from a fiber network; an output interface, comprising one or more hybrid cables for connection to one or more end devices, each of the hybrid cables including fiber for data communication and wire for power transmission; a mains power interface, configured to receive alternating current (AC) mains power; one or more power supplies, configured to convert the AC mains power to direct current (DC) power; and a power insertion board, configured to provide power insertion of the DC power out through the one or more hybrid cables. |
| US10277321B1 |
Acquisition and pointing device, system, and method using quad cell
The Quad Cell permits measurement of four quadrant signal powers simultaneously, metrics which are equal when the laser spot is at the desired zero location, at the center of the cell, the origin of the cells' axes. A control action acts upon the Quad Cell signals to move the laser spot toward the origin of the axes bisecting the four quadrants of the cell, moving the laser spot to the origin to achieve a null in the difference between these four signal levels. |
| US10277318B2 |
Apparatus and method for registering visible light communication device and combining visible light communication signal and wireless communication signal
Disclosed are a method and apparatus for registering visible light communication devices and combining a visible light communication signal and a wireless communication signal. It is an object of the present disclosure to provide a visible light communication device registration method in which a lighting device allows collective registration of the lighting device and a terminal as the terminal transmits data to a light using wireless communication. |
| US10277316B1 |
Free space optical headset
A communications headset system and method of use utilizing first and second headsets with integrated hearing protection for enabling users to wirelessly communicate when the hearing protection is engaged. Each headset is configured for placement onto a user's head and includes hearing protection cups that engage a user's ears and attenuate incoming sound waves external to the headset. The headsets include a first optical receiver that detects a light signal within a first receiving field-of-view and generates an incoming electrical signal corresponding to the light signal. A speaker converts the incoming electrical signal to an incoming audio signal, and then outputs the incoming audio signal as sound waves. A microphone converts outgoing sound waves to an outgoing electrical signal. An optical transmitter converts the outgoing electrical signal to one or more light signals and then broadcasts the one or more light signals within a broadcast field-of-view and a broadcast range. |
| US10277315B2 |
Method and apparatus for monitoring wavelength channel
A method and an apparatus for monitoring a wavelength channel are disclosed. The method includes: performing optical-to-electrical detection on an optical signal on a wavelength channel, to obtain an electrical signal; obtaining a frequency spectrum of the electrical signal; determining a first parameter M according to an equation M=NAC, where NAC represents an alternating current component of the frequency spectrum of the electrical signal; and if M is greater than a preset first threshold, determining that the wavelength channel includes a real service signal. According to the method and apparatus, an erroneous configuration or operation of a network management system can be avoided. |
| US10277312B2 |
Method for adjusting LOS alarm decision threshold and optical module
Embodiments of the present disclosure provide a method for adjusting a LOS alarm decision threshold and an optical module. The method includes: receiving an optical signal; determining a power value of the optical signal and an amplitude of an electrical signal converted from the optical signal; determining a first numeric relation between the power value and a preset threshold, and a second numeric relation between the amplitude value and a preset decision threshold; and adjusting the decision threshold according to the first numeric relation and the second numeric relation. The method for adjusting a LOS alarm decision threshold and the optical module provided in the embodiments of the present invention can improve the efficiency in setting the LOS alarm decision threshold. |
| US10277311B2 |
Dual wavelength optical time domain reflectometer systems and methods embedded in a WDM system
Systems and methods using a bi-directional Optical Time Domain Reflectometer (OTDR) to monitor a fiber optic communication system including a first node and a second node. The systems and methods include performing a first OTDR measurement at a first OTDR wavelength at the first node on a first fiber; performing a second OTDR measurement at a second OTDR wavelength at the second node on the first fiber; and utilizing the first OTDR measurement and the second OTDR measurement for event detection on the first fiber. |
| US10277307B1 |
Network capacity management
An example embodiment may involve flying, by an unmanned aerial vehicle (UAV), to a geographical location, where a wireless router is at the geographical location. The example embodiment may also involve detecting, by the UAV, a wireless coverage area defined by the wireless router. The example embodiment may also involve accessing, by the UAV, the wireless coverage area using a network identifier and a password. The example embodiment may also involve establishing, by the UAV, a backhaul link to a data network. The example embodiment may also involve transmitting, by the UAV, a notification to a client device served by the wireless coverage area, where the notification indicates that the UAV is a default gateway for the wireless coverage area. The example embodiment may also involve exchanging, by the UAV, data transmissions between (i) the client device, and (ii) one or more other devices accessible via the data network. |
| US10277303B2 |
Vehicle-based femtocell with prioritization of data packets on the basis of the required internet service quality
A device for a relay transceiver in a mobile communication system, which includes a base station transceiver and a packet data network interface, includes at least one transceiver module configured to communicate with at least one mobile transceiver and with the base station transceiver. The device further includes a control module configured to determine, on the basis of a data packet received by the at least one mobile transceiver, information about a quality criterion of a service associated with the data packet, and to establish, on the basis of the information about the quality criterion, a data connection to the packet data network interface via the base station transceiver. |
| US10277302B2 |
Signal-repeating device for extending a control area and signal-repeating method thereof
A signal-repeating device for extending a control area and signal-repeating method thereof are provided. The signal-repeating device includes a first connection port, a second connection port, a repeating circuit, a communication-monitoring module and a processing unit. The first connection port is coupled to a first antenna. The first antenna supports a first frequency band and a second frequency band. The second connection port is coupled to a second antenna. The repeating circuit is coupled between the first connection port and the second connection port to repeat signals between a base station and a mobile station via the first antenna and the second antenna through the first frequency band. The communication-monitoring module is connected to a user terminal via the first antenna through the second frequency band. The processing unit is coupled to the repeating circuit and the communication-monitoring module. The first frequency band does not overlap the second frequency band. |
| US10277301B2 |
Information processing system, information processing method and program
An information processing system includes a relay device and first and second information processing devices. The relay device includes a reception unit that receives from a communication terminal a process request indicating first and second processes; and a terminal request transmission unit that sends the process request to the first information processing device in response to a first request, and sends an execution result of the first process and the process request to the second information processing device in response to a second request. The first information processing device includes a first process control unit that controls to execute the first process according to the process request; and a transmission unit that sends the execution result and the process request. The second information processing device includes a second process control unit that controls to execute the second process based on the execution result according to the process request. |
| US10277299B2 |
Method and system for optimizing communication using reflectors in distributed transceiver environments
A communication device may comprise a plurality of distributed transceivers and one or more corresponding antenna arrays. A processor may configure a first distributed transceiver to receive signals comprising one or more first data streams via one or more first communication links. The processor may configure a second distributed transceiver to receive signals comprising one or more second data streams via one or more second communication links. The processor may determine a channel response matrix associated with communication of the one or more first data streams via the one or more first communication links and/or the one or more second data streams via the one or more second communication links. The processor may optimize one or both of link capacity and/or link reliability of the one or more first communication links and/or the one or more second communication links based on the determined channel response matrix. |
| US10277296B2 |
Method and apparatus for channel state information (CSI) reporting in a massive MIMO communications system
Provided is a method of base station (BS) for channel state information (CSI) acquisition in a massive multiple input/multiple output (MIMO) communication system. The method comprises the steps at the BS of sending a set of beamformed reference signals (RSs) to a user equipment (UE) and receiving from said UE an indication of a subset of said set of beamformed RSs and CSI acquired by said UE for only said subset of said set of beamformed RSs. Also provided is a further method and a user equipment (UE) for CSI acquisition. The further method comprises the steps at the UE of receiving from the BS the set of beamformed RSs; estimating a channel of each RS comprising said set of beamformed RSs; selecting a subset of said set of beamformed RSs; acquiring CSI for only said selected subset of said set of beamformed RSs; and communicating to said BS an indication of said selected subset of said set of beamformed RSs and reporting the CSI acquired for said selected subset of said set of beamformed RSs. |
| US10277295B2 |
Simultaneous nulling and beamfocusing from disparate antennas
In an antenna array, signals may be manipulated to increase coherency at certain locations (beamfocusing) and reduce or cancel the signals at other locations (nulling). This is accomplished by multiplying the signals received or transmitted by the set of antennas by a weight vector that is generated by determining a covariance matrix based on a vector representing signals at the set of antennas, vectors representing the desired beamfocusing and nulling locations, and a desired nulling depth. |
| US10277288B1 |
Method and system for a multi-frequency rail car antenna array
The present invention relates to methods and systems utilizing a multiple-frequency antenna array system. The multiple-frequency antenna array system includes a first set of broadband elements that allows the establishment of a first cellular data communication session and a concurrent second cellular data communication session. The system also includes a second set of broadband elements that allow the establishment of a first local area wireless network communication session and a concurrent second local area wireless network communication session. Further, there is a broadband element configured to receive a global positioning signal. In addition, the multiple-frequency antenna array system is coupled to a vehicle. A method for establishing multi-frequency communication sessions using an antenna array is also presented. |
| US10277287B2 |
Antenna system and harmonic suppression element
An antenna system includes an antenna, a first frequency dividing circuit, a second frequency dividing circuit, and a plurality of matching circuits. The first frequency dividing circuit is coupled to the antenna. The matching circuits are coupled to the first frequency dividing circuit. The second frequency dividing circuit is coupled to the matching circuits. The matching circuits are configured to process different frequency signals, respectively. |
| US10277285B2 |
Soft transmit point and user equipment association method for radio access virtualization
Embodiments of the present invention provide a systematic solution to virtual random access (VRA) that dynamically and adaptively forms various metrics. The present invention facilitates dynamic data pipelining between the network-side and the UE-sides without the need to use the same cell-association concept as current wireless networks and provides soft associations between dynamic groups of UEs and TPs based on various UE, TP, and network related metrics. To provide efficient collaborative grouping and association among TPs and UEs, the present invention features a soft TP-UE association map based on several factors, such as individual UE metrics, TP metrics, effects of neighboring or nearby UEs (e.g., interference), and historical network knowledge. |
| US10277282B2 |
Antenna for short-range applications and utilization of such an antenna
An antenna for short-range applications, including an elongate two-pole conductor structure with an internal conductor and a sheath conductor coaxially surrounding the internal conductor, and a terminal structure connected to the conductor structure. The terminal structure includes an electrically insulating carrier plate, an electrically conductive sheath conductor connection surface that extends over a first region of the carrier plate on the upper side of the carrier plate and is connected to the sheath conductor, an electrically conductive internal conductor connection surface that extends over a second region of the carrier plate, which is spaced apart from the first region of the carrier plate, on the upper side of the carrier plate and is connected to the internal conductor, an electrically conductive coupling conductor surface that extends over a third region of the carrier plate on the underside of the carrier plate. The antenna provides reliable transmission of information over short distances. |
| US10277280B2 |
Configuration of data and power transfer in near field communications
Some embodiments disclosed herein provide a method for configuring wireless power and data transfer between consumer electronic (CE) devices. The method comprises identifying a plurality of antenna systems including at least a first antenna system and a second antenna system. At least the first antenna system is cooperated with a first CE device and the second antenna system is cooperated with a separate second CE device. Each of the plurality of antenna systems comprises a power transfer antenna and one or more communications antennas. The system provides a graphical user interface to illustrate each of the identified antenna systems, and receives user instructions corresponding to at least two of the identified antenna systems, to generate configuration instructions in accordance with the user instructions, and to configure selected CE devices in accordance with the configuration instructions. |
| US10277278B2 |
Circuits and systems for multiplexed isolator communication
An embodiment of a communication system for transmitting and receiving data across an isolation barrier may include a communication circuit connected to an isolator at a first side of the isolation barrier, the communication circuit having a transmit circuit to drive a first data signal onto the isolator based on input data received by the communication circuit, a receive circuit to receive a second data signal from the isolator and produce output data based on the received second data signal, and a control circuit to control the transmit and receive circuits to provide time division multiplexing of the first and second data signals. The control circuit may transition to a transmit state in which the transmit circuit drives the first data signal onto the isolator from a receive state in which the receive circuit receives the second data signal from the isolator in response to detecting a condition as a function of receiving a predetermined number of bits of the second data signal and passage of a predetermined time period. |
| US10277277B2 |
ULF/VLF power line communications coupler
A circuit (100) for coupling an amplifier (1) in an electrical power distribution system with the amplifier electrically and physically isolated from a power line of the system. The amplifier generates arbitrary signal waveforms injected into the power line. A transformer (T1) has a primary and a secondary side with the amplifier located on the primary side and the secondary side connected to the power line. A resistor (R1) series connected with the primary side of the transformer is sized to accommodate a minimum load impedance of the amplifier and minimize power dissipation. A resonant circuit interposed between the secondary side of the transformer and the power line has values for a capacitor (C1) and an inductor (L3) forming the resonant circuit chosen to peak the amplitude of the arbitrary signal waveform at the frequency of a waveform propagated through the power line. |
| US10277273B2 |
Method and apparatus for exchanging communication signals
Aspects of the subject disclosure may include, for example, receiving, by each of a plurality of receivers, one of a plurality of electromagnetic waves, each electromagnetic wave of the plurality of electromagnetic waves guided by a different one of a plurality of twin-lead transmission lines, each twin-lead transmission line sharing a wire, and each electromagnetic wave of the plurality of electromagnetic waves including a different one of a plurality of communication signals, and obtaining, by each of the plurality of receivers, one of the plurality of communication signals. Other embodiments are disclosed. |
| US10277270B2 |
Method for transmitting uplink signal in a wireless communication system and apparatus for the same
Provided are a method of transmitting, by a user equipment, a uplink signal in a wireless communication system. The method includes receiving control information related to a codeword cover used for a multiplexing of a multiple of user equipments from a base station, generating a transmission symbol of a specific length by repeating a data symbol in a specific time unit, generating the uplink signal by applying the codeword cover of the specific length to the generated transmission symbol, and transmitting the generated uplink signal to the base station through a single tone. |
| US10277269B2 |
Phased array beam tracking using beam gain coding
A system for phased array signal beam tracking includes a phased array transmitter configurable for transmitting a signal beam at a selected transmit beam angle from a plurality of different transmit beam angles. The system also includes a beam gain angle coding assembly configured for modulation of a gain of the signal beam to produce a resulting gain profile of the signal beam. The resulting gain profile includes offset angle coding that indicates an offset incident angle of the signal beam at a receiving antenna. |
| US10277267B1 |
Antenna tuning device
One example discloses an antenna tuning device, including: a controller configured to be coupled to a transceiver having an antenna tuner; wherein the transceiver is coupled to an antenna; wherein the controller is configured to receive a measured current signal from the transceiver corresponding to a current sent to or received by the antenna; and wherein the controller is configured to change an impedance of the antenna tuner in response to the measured current signal. |
| US10277266B1 |
Mobile device case and methods of making and using same
A case for a mobile device includes a bumper portion and a module portion. The module portion is attached to the bumper portion. The bumper portion has a border configured to receive a mobile device. The module portion includes a base portion, a back plate and battery portion. The base portion is attached to the back plate. The battery portion is positioned between the base portion and the back plate. The battery portion includes a plurality of battery cells, a printed circuit board assembly and a plurality of electromagnetic induction coils all operably connected to one another. |
| US10277264B2 |
Interference averaging and interference resource groups in a wireless communication system
Methods, apparatuses, and systems are described related to interference averaging to generate feedback information and interference averaging to demodulate receives signals. In embodiments, an evolved Node B (eNB) may transmit interference averaging information to a user equipment (UE) including a time domain averaging indicator indicating a time domain averaging window to be used by the UE for averaging interference measurements in a time domain or a frequency domain averaging indicator to indicate a frequency domain averaging window to be used by the UE for averaging interference measurements in a frequency domain. Additionally, or alternatively, the eNB may transmit an interference resource group (IRG) indicator to the UE to indicate an IRG over which the UE is to perform interference averaging to facilitate demodulation of signals received by the UE from the eNB. |
| US10277263B2 |
Radio receiver
A radio receiver, configured to use an impulse UWB, includes: a reception antenna which receives the impulse UWB, a reception unit which amplifies the received impulse UWB and detects an envelope of the impulse UWB, maximum-peak and minimum-peak detection units which detect a maximum value and minimum value of the envelope, respectively, a comparator which acquires signal data from the envelope with an initial threshold value, a baseband unit which measures an error rate of the signal data, an MPU which calculates a correction value based on the error rate, and an arithmetic unit which calculates a corrected threshold value based on the maximum, minimum and correction values. The arithmetic unit transmits the corrected threshold value to the comparator. The comparator acquires the signal data from the envelope based on the corrected threshold value transmitted from the arithmetic unit. |
| US10277261B2 |
Distortion compensation apparatus and distortion compensation method
A distortion compensation apparatus includes: a filtering unit that is provided with a plurality of storing units each of which is capable of storing a signal therein and that filters an input signal by sequentially moving the input signal starting from a storing unit provided on a first stage up to another storing unit provided on a final stage; a calculating unit that calculates a power level of a signal output from a storing unit that is provided on an earlier stage than the storing unit provided on the final stage; an output unit that, on the basis of the power level calculated, outputs a distortion compensation coefficient used for cancelling out non-linear distortion occurring in an amplifier; and a distortion compensation unit that performs a distortion compensation process on a signal output from the storing unit provided on the final stage, by using the distortion compensation coefficient. |
| US10277246B2 |
Program counter compression method and hardware circuit thereof
The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter. |
| US10277245B2 |
Digital to analog converter circuit, display panel and display device
A digital to analog converter circuit, a display panel and a display device are provided. The digital to analog converter circuit includes a voltage dividing unit, a first segmenting unit, a second segmenting unit and a third segmenting unit. |
| US10277244B1 |
Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling
Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements. |
| US10277241B1 |
Continuous-time analog-to-digital converter
A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC. |
| US10277237B2 |
Successive approximation type A/D conversion circuit
A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal. |
| US10277232B2 |
Charge pump circuit and PLL circuit
A charge pump circuit of an embodiment includes a current mirror circuit, a first drive switch, a capacitor and a switch circuit. The current mirror circuit causes a current obtained by mirroring a reference current to flow to a first output terminal and a second output terminal. The first drive switch connects or disconnects the first output terminal and a charge pump output terminal. The switch circuit connects the capacitor either to a discharge path between the second output terminal and a node which provides a predetermined voltage or to a charge path between the charge pump output terminal and a GND. |
| US10277229B2 |
Communication over generator bus
A generator system includes at least one generator, at least one generator controller, and a power bus. The power bus transmits power to a load circuit. Data communications are also transmitted by the power bus. In one example, multiple generator controllers exchange messages over the power bus. In another example, one or more generator controllers exchange messages with a central controller over the power bus. The messages may include a status for the generators, output values for the generators, or commands for the generators. |
| US10277226B1 |
Voltage translator device
In at least one general aspect, an apparatus can include a first voltage domain circuit configured to operate based on a first upper voltage and a first lower voltage, and a second voltage domain circuit configured to operate based on a second upper voltage and a second lower voltage. The apparatus can include a capacitive coupling circuit electrically connected between the first voltage domain circuit and the second voltage domain circuit, and a driver circuit including a switch device and electrically coupled to the second voltage domain circuit. The apparatus can also include an intermediate voltage domain circuit configured to trigger switching of the switch device included in the driver circuit where the intermediate voltage domain is configured to operate based on an intermediate voltage and the second upper voltage or the second lower voltage. |
| US10277222B1 |
Radio frequency switch
A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells includes a field-effect transistor having a drain terminal, a source terminal, a FET gate terminal, and a body terminal and an off-state linearization network. The off-state linearization network includes varactors coupled to the drain terminal and the source terminal of the field-effect transistor. |
| US10277221B2 |
Protection circuit
A protection circuit includes a periodicity determination device, an off circuit and a control device. The periodicity determination device directly or indirectly detects a noise superimposed on a first transistor including a control terminal and determines periodicity of the noise. The off circuit is connected to the control terminal of the first transistor and is configured to perform an off-operation of the first transistor. The control device enables the off-operation of the first transistor, performed by the off circuit, when the periodicity determination device determines that the noise has periodicity. The control device disables the off-operation of the first transistor, performed by the off circuit, when the periodicity determination device determines that the noise does not have periodicity. Accordingly, the protection circuit withdraws an ESD energy while stabilizing a circuit operation. |
| US10277218B2 |
System comprising multi-die power module, method for controlling operation of multi-die power module, device for controlling operation of multi-die power module
The present invention concerns a system comprising a multi-die power module composed of dies and a controller receiving plural consecutive input patterns for activating the dies of the multi-die power module. The dies are grouped into plural clusters of dies and the controller comprises means for outputting one gate to source signals for each cluster of dies, each outputted gate to source signal being different from the other gate to source signals and at least one first outputted gate to source signal reducing the activation of dies during at least one input pattern among the plural input patterns. |
| US10277217B2 |
Controlled bootstrap driver for high side electronic switching device
The subject matter of this specification can be embodied in, among other things, a method that includes providing first power received from a first power bus to a first switching device configured to switch first power to a first output port based on a first input signal received at a first input port, providing second power received from a second power bus to a second switching device configured to switch second power to a first bootstrap capacitor coupled between the second switching device and the first output port based on a second input signal received at a second input port, providing an output voltage to the first output port, providing the second input signal to the second input port, switching the second switching device based on the second input signal, and charging the first bootstrap capacitor with second power received from the second power bus. |
| US10277213B1 |
Glitch detection in input/output bus
A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch. |
| US10277212B2 |
Pulse generator and driving circuit comprising the same
A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change. |
| US10277211B2 |
Integrated switch and self-activating adjustable power limiter
A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches. |
| US10277210B1 |
Clock skew suppression for time-interleaved clocks
A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively. |
| US10277208B2 |
Energy efficient controlled magnetic field generator circuit
A magnetic waveform generator circuit includes a first switch coupled to a first rectifier element at a first node, a first capacitor coupled, at a second node to the first switch, and to a fourth node, a second capacitor coupled, at a third node to the first rectifier element, and to the fourth node, and an inductor coupled between the first and the fourth nodes. The first switch is operable to be in an ON state during a first time period and in an off state during a second time period. The first switch and the first rectifier element are configured to enable the inductor to generate, during the first and the second time periods, a magnetic field having a waveform resembling a positive half-cycle of a triangular waveform. |
| US10277207B1 |
Low voltage, master-slave flip-flop
The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled. |
| US10277205B1 |
SPDT switch with high linearity
A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor. |
| US10277202B2 |
Methods and apparatus for efficient linear combiner
In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output. |
| US10277197B2 |
Piezoelectric vibrating piece and piezoelectric device
A piezoelectric vibrating piece includes a vibrating piece body including a vibrator and at least one pair of excitation electrodes formed on a front surface and a back surface of the vibrator. The vibrating piece body is a twice rotated quartz-crystal vibrating piece. The pair of excitation electrodes are arranged in a Z′″-axis direction determined by an X′″-axis and obliquely disposed with respect to the Y″-axis direction. The X′″-axis is rotated by 260° to 300° counterclockwise about a Y″-axis using a +X″-axis direction as a reference. The pair of excitation electrodes are formed to have respective semicircle shapes including straight line portions extending in the X′″-axis direction and to be disposed in a state where the straight line portions overlapping with one another. The straight line portion of the excitation electrode includes an inclined portion that gradually decreases in thickness toward an end portion of the excitation electrode. |
| US10277196B2 |
Bulk acoustic wave resonator and method for manufacturing the same
In examples, there is provided a bulk acoustic wave resonator including a substrate; a resonating part including a first electrode, a piezoelectric layer, and a second electrode, laminated on an upper surface of the substrate, a cap bonded to the substrate by a bonding agent; and a sealing layer formed on an externally exposed surface of the bonding agent. This structure provides for a bulk acoustic wave resonator with improved reliability. |
| US10277189B2 |
Transmission line reflectionless filters
Reflectionless transmission line filters, as well as a method for designing such filters is disclosed. These filters preferably function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. The insertion of additional transmission line sections that change the phase response of the circuit without altering the amplitude response preferably allows follow-up transmission line identities to be applied in order to arrive at a more easily manufacturable filter topology. This facilitates their application over a higher frequency range the solely lumped-element circuits. |
| US10277187B2 |
Motor vehicle sound enhancement
A method for modifying sound in a motor vehicle that has an audio system. The audio system has at least one electro-acoustic transducer that creates sound from audio signals. An initial audio signal that represents a particular vehicle sound is provided, where the initial audio signal has a plurality of signal properties. A modified audio signal is then provided to the audio system, based on at least one current motor vehicle operating condition. The modified audio signal includes at least one modified signal property that differs from that of the initial audio signal. The at least one signal property is modified by a modification process that relates to a vehicle operating condition. |
| US10277185B2 |
Communication system and robot
A communication system includes a first microphone, a first loudspeaker, a second loudspeaker, a second microphone, a speaker number determination unit, and a control unit. The first microphone acquires a surrounding voice as a voice signal. The first loudspeaker is provided near the first microphone and outputs a voice. The second loudspeaker acquires the voice signal from the first microphone and outputs the voice signal as a voice. The second microphone acquires a surrounding voice as a voice signal and outputs the voice signal to the first loudspeaker. The speaker number determination unit determines the number of speakers around the first microphone based on the voice signal acquired by the first microphone. The control unit controls a volume of the first loudspeaker based on the determination of the speaker number determination unit. |
| US10277174B2 |
Radio-frequency amplification systems, devices and methods
Radio-frequency amplification systems, devices and methods. In some embodiments, an amplification system can include a supply circuit configured to provide a high supply voltage in an average power tracking mode. The amplification system can further include an amplifier configured to operate with the high supply voltage and provide an impedance that substantially matches an impedance of a component coupled to an output of the amplifier. The amplification system can further include a signal path configured to route an amplified signal from the output of the amplifier to the component, with the output path being substantially free of an output matching network. |
| US10277170B1 |
Radio frequency amplifier and integrated circuit using the radio frequency amplifier
A radio frequency amplifier comprises a transistor, a transformer and a variable capacitor. The transistor has an input terminal, an output terminal and a control terminal. The transformer has a first coil conductor and a second coil conductor. The first coil conductor magnetically couples to the second coil conductor. The second coil conductor connects to the control terminal. The first coil conductor connects to the input terminal. The variable capacitor connects in parallel with the second coil conductor. The radio frequency amplifier is configured to be an input or output stage of an integrated circuit. An integrated circuit using the radio frequency amplifier is also introduced. |
| US10277168B2 |
Stacked power amplifier power control
Systems, methods and apparatus for efficient power control and/or compensation with respect to a varying supply voltage of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control and/or compensation is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift/variation in output power of the RF amplifier. |
| US10277166B2 |
Multifunctional solar energy system
Disclosed is a multifunctional solar energy system comprising a converging system and two solar energy utilization devices (P1, P2), wherein the converging system comprises at least one light-focusing refractive surface (s1) and one reflective surface (s2); at least one of the reflective surface (s2) and the two solar energy utilization devices (P1, P2) are movable; if the reflective surface (s2) is movable, the two solar energy utilization devices (P1, P2) are respectively provided on light paths before and after the reflective surface (s2) moves; and if the reflective surface (s2) is fixed, the two solar energy utilization devices (P1, P2) are successively provided in the light path after the reflective surface (s2). The solar energy system is able to place one of the two solar energy utilization devices (P1, P2) in the light path by moving the movable component so as to respectively use the two solar energy utilization devices (P1, P2) at different times, thereby greatly extending the function of the solar energy system and improving the comprehensive utilization rate of the system. |
| US10277165B2 |
Photovoltaic module
The present invention relates to a photovoltaic module. A photovoltaic module according to an embodiment of the present invention comprises a solar cell module, a micro-inverter to convert DC power generated by the solar cell module into AC power, a controller to control the micro-inverter's operation, and an interface unit connected to power grid supplying external electrical power and to provide the AC power to the power grid, the controller to control operation of the micro-inverter such that the AC power is matched to the external electrical power flowing into the power grid. The photovoltaic module according to the present invention can provide electrical power generated at solar cell modules through a simple connection to power grid which supplies electrical power to home, reducing consumption of electrical power flowing into home. |
| US10277156B2 |
Architecture structure of interconnected electronic power modules for hexaphase rotary electrical machine, and hexaphase rotary electrical machine comprising architecture structure of this type
The invention relates to an architecture which is applied to a six-phase rotary electric machine of the type comprising first and second three-phase systems offset angularly at a predetermined offset angle. First and second phase windings of the three-phase systems respectively carry first (U1, V1, W1) and second (U2, V2, W2) phase currents controlled by electronic power modules (15, 16, 17). The electronic modules comprise first and second power terminals (12, 13) each capable of being electrically connected to first and second instances of the first and second phase windings. According to the invention, the electronic power modules are interconnected such as to balance the losses. |
| US10277155B2 |
Smart DC power supply for AC equipment
A system is disclosed comprising a DC power supply for supplying DC power to a device having a universal electric motor configured to operate on AC power. The system is configured to have a first authorization component associated with the device and second authorization component associated with the DC power supply so that DC power is supplied to device, or is continued to be supplied to the device, only when the first and second authorization components operatively engage. |
| US10277152B2 |
Motor control apparatus, sheet conveying apparatus, image forming apparatus
A motor control apparatus operates in a first control mode in which the values of a torque current component and an excitation current component are controlled so that the difference between an instruction phase and a rotation phase is decreased and a second control mode in which constant current is supplied to a winding of a motor. The second control mode is switched to the first control mode if the rotation speed is varied from a value lower than a first threshold value to a value not lower than the first threshold value in the second control mode and the first control mode is kept even if the rotation speed is varied from a value not lower than the first threshold value to a value that is not lower than a second threshold value and that is lower than the first threshold value in the first control mode. |
| US10277150B2 |
Method and circuit for driving single coil BLDC motor
Method of driving a single-coil motor having a stator and a rotor and a coil, comprising the steps of: monitoring a position signal and determining when said signal passes a first threshold; b) providing control signals for energizing the coil; c) a predefined period later, providing control signals for stopping or reducing the energization of the coil; d) monitoring a second signal indicative of the coil current, and determining a third time when said signal passes a second threshold level; and monitoring the first signal, and determining a fourth time when said signal passes a third threshold level; e) updating the prediction period; f) repeating steps b) to e). A driver circuit adapted for performing such method. A system comprising such driver circuit. |
| US10277142B2 |
Electric power devices with automatically established input voltage connection configuration
Electric power devices and control methods are provided which automatically select a line voltage or phase voltage of an AC voltage supply. The electric power device includes a switchable circuit, a sensor and a switch control. The switchable circuit connects to the AC voltage supply, and includes multiple switchable elements. The sensor ascertains a voltage level of the AC voltage supply, and the switch control automatically establishes a configuration of the switchable circuit through control of the multiple switchable elements. The switch control couples the electric power device in a line-line (delta) configuration to the AC voltage supply when the voltage level is in a first voltage range, and a line-neutral (wye) configuration when the voltage level is in a second voltage range. |
| US10277141B2 |
Current protected integrated transformer driver for isolating a DC-DC convertor
An improved electronic oscillator circuit suitable for use in an isolating DC-to-DC converter circuit, and an improved isolating DC-to-DC converter circuit. In one embodiment, an integrated circuit coupled to a transformer includes an oscillator and an output driver. The integrated circuit is preferably fabricated using a silicon-on-insulator technology. The oscillator outputs an alternating pulse signal defined by electrical characteristics of components other than the transformer. The alternating pulse signal is coupled to the output driver, the alternating output of which is coupled to corresponding legs of the primary winding of the transformer. The secondary winding of the transformer provides an electromagnetically coupled isolated output which may be rectified and filtered to produce a DC output voltage. Additional functionality, such as current protection circuitry for the improved circuits, may be readily added to the integrated circuit at little or no increase in cost. |
| US10277139B2 |
Power conversion device which detects power shortage and switches to a power supply that is capable of supplying power
A transformer is composed of three or more windings magnetically coupled. An AC/DC converter (2) for converting AC power of an AC power supply (1), a capacitor (3), and a switching circuit (4) are connected to one winding (6a), and a switching circuit (8) or (30) for power conversion of a DC power supply is connected to at least one of the other windings. Voltage of the capacitor (3) or the AC power supply (1) is detected. On the basis of the detected value thereof, the operation state of each switching circuit (4), (8), (30) is determined by an operation state determination circuit (101). On the basis of a result of the determination, the power supply is switched among the AC power supply (1) and the DC power supplies (11) and (34) by an output switch circuit (103). |
| US10277138B2 |
Active clamp full bridge converter and driving method thereof
Provided is an active clamp full bridge converter, which includes: a transformer having a primary coil and a secondary coil and configured to convert a voltage; a primary circuit connected to an input capacitor for supplying an input power and including a full bridge circuit having first to fourth switches to transmit the input power to the primary coil according to a switching operation of the first to fourth switches; and a secondary circuit connected to the secondary coil and including a rectifying bridge circuit having first to fourth diodes, an active clamp circuit connected to the rectifying bridge circuit and composed of an active clamp switch and a clamping capacitor connected in series, and an output inductor connected to the active clamp circuit, to transmit an energy received from the primary circuit by the transformer to an output capacitor connected to the output inductor and the active clamp circuit. |
| US10277135B2 |
Dual-output flyback voltage conversion circuit and display device
A dual-output flyback voltage conversion circuit and a display device are provided. The dual-output flyback voltage conversion circuit includes an input module, a voltage transformation module, an output module, and a feedback module. The input module is used for rectifying and filtering an input voltage. The voltage transformation module is used for performing a voltage conversion process on the input voltage which is obtained after rectifying and filtering. The output module is used for outputting a first output voltage and a second output voltage according to conversion voltages. The feedback module is used for controlling the voltage transformation module to output the input voltage which is obtained after rectifying and filtering according to the first output voltage and the second output voltage. |
| US10277133B2 |
Isolated DC/DC converter, primary side controller, power adapter, and electronic device
An isolated DC/DC converter includes a transformer having a first winding and a secondary winding, a switching transistor connected to the primary winding of the transformer, a rectifier element connected to the secondary winding of the transformer, a photocoupler, a feedback circuit configured to drive a light emitting element on an input side of the photocoupler by a forward current corresponding to an error between an output voltage of the DC/DC converter and a target voltage of the DC/DC converter, a conversion circuit configured to convert a collector current flowing in a light receiving element on an output side of the photocoupler into a feedback voltage having a negative correlation with the collector current, a pulse signal generator configured to generate a pulse signal corresponding to the feedback voltage, and a driver configured to drive the switching transistor depending on the pulse signal. |
| US10277132B2 |
Systems and methods for constant voltage mode and constant current mode in flyback power converters with primary-side sensing and regulation
System and method for regulating a power converter. The system includes a first signal generator configured to receive a first sensed signal and generate an output signal associated with demagnetization. The first sensed signal is related to a first winding coupled to a secondary winding for a power converter, and the secondary winding is associated with at least an output current for the power converter. Additionally, the system includes a ramping signal generator configured to receive the output signal and generate a ramping signal, and a first comparator configured to receive the ramping signal and a first threshold signal and generate a first comparison signal based on at least information associated with the ramping signal and the first threshold signal. Moreover, the system includes a second comparator configured to receive a second sensed signal and a second threshold signal and generate a second comparison signal. |
| US10277130B2 |
Primary-side start-up method and circuit arrangement for a series-parallel resonant power converter
A series-parallel resonant power converter comprises a primary-side start-up controller and a secondary-side controller, wherein the primary-side start-up controller sends power to the secondary-side controller when power (voltage) is first applied to the series-parallel resonant power converter. The start-up controller starts up the series-parallel resonant power converter using an open-loop start-up technique wherein the secondary-side closed-loop controller takes over control of the series-parallel resonant power converter once it becomes powered and activated. During light-load or no load conditions, the secondary-side controller sends an off resonance higher frequency or a standby code inhibit (disable) command to the start-up controller. When power needs to be sent to the secondary side of the transformer to charge a secondary side capacitor, the secondary-side controller may send an enable code command to the start-up controller where it is detect to allow the start-up controller to operate in a normal fashion with the secondary side controller. |
| US10277127B2 |
Enhanced fault reporting in voltage regulators
An electronic system, voltage regulator, controller and fault reporting method and circuit for a voltage regulator or other type of DC-DC converter are disclosed. For example, a fault reporting circuit is disclosed. The fault reporting circuit includes a first transistor device configured to generate a first signal indicating an occurrence of a fault in an associated circuit, a second transistor device coupled to the first transistor device, the second transistor device configured to generate at least one data signal indicating an identity of the fault in the associated circuit, and an output coupled to the first transistor device and the second transistor device, wherein the output is configured to receive the first signal and the at least one data signal. In some implementations, the fault reporting circuit is in a controller for a voltage regulator circuit formed on one or more semiconductor ICs, wafers, chips or dies. |
| US10277124B2 |
DC-DC converter, boosting unit, electric vehicle and battery backup system
Provided are a boosting unit, a DC-DC converter including the boosting unit, and an electric vehicle. The DC-DC converter includes: a switch connected to an input voltage; a main diode connected to the switch; a regulating capacitor, a first terminal of the regulating capacitor being connected in series with the main diode, a second terminal of the regulating capacitor being connected to the input voltage, and the first terminal and the second terminal of the regulating capacitor serving as output terminals of the DC-DC converter; and a boosting unit, the boosting unit comprising a first inductor, a second inductor, a boosting capacitor, a first unidirectional conducting device, a second unidirectional conducting device, a third unidirectional conducting device and a fourth unidirectional conducting device. According to the embodiments of the present disclosure, voltage gain can be increased by replacing inductors in the ordinary DC-DC converter with the boosting unit. |
| US10277120B1 |
Optimized, multiphase switched-capacitor DC-DC converter with variable gain
A structure and method is provided for DC to DC conversion using switched-capacitors. The DC-DC converter uses an optimized configuration of capacitors and switches that maximize the number of attainable ideal conversion ratios for the given number of capacitors. A method is provided for controlling the converter, wherein the control circuitry generates a multiphase switching sequence which turns the switches on and off in a cyclical manner. Sample switching sequences are provided to generate a set of attainable ideal conversion ratios, for up to three floating capacitors. The converter is programmable, modular and capable of dynamically varying its ideal conversion gain. It can be used to both step-up and step-down the input voltage. |
| US10277117B2 |
Device with a voltage multiplier
A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal. |
| US10277114B2 |
Single stage isolated power converter
Typically, power factor is improved by adding a full power factor correction (PFC) stage between the rectifier and the power converter. This disclosure applies line voltage modulation to the control feedback of an isolated full bridge converter, thereby combining the PFC stage with the isolated power stage and forming a single state isolated power converter. |
| US10277113B2 |
Switching power supply with output power estimation
A switching power supply device includes a control unit alternately turning a first switching device and a second switching device ON/OFF so as to drive a primary side of a transformer, wherein the control unit includes: a peak power limiting circuit that monitors input power to the primary side of the transformer and outputs a forced turn OFF signal every time the input power becomes higher than a prescribed value; and a switching cycle counter circuit that estimates an output voltage on a secondary side of the transformer by counting a number of times the forced turn OFF signal is outputted by the peak power limiting circuit, and outputs a switching stop signal that causes the alternating turning ON/OFF of the first and second switching devices to stop when the estimated output voltage reaches an overvoltage protection detection voltage. |
| US10277112B2 |
Physical topology for a power converter
A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances. |
| US10277106B2 |
Control circuit for switching power supply apparatus
A control circuit 2a for a switching power supply apparatus includes a comparator COMPa for comparing a voltage corresponding to a current flowing through a switching element PT1 with a voltage to be compared therewith, and outputting a comparison signal corresponding to a result of the comparison. To the comparator, a blanking pulse signal is also input. Here, the blanking pulse signal indicates whether or not it is currently in a predetermined period that is set for ensuring that the switching element is not turned off for the predetermined period after the switching element has been turned on. When the blanking pulse signal indicates that it is currently in the predetermined period, the comparison signal is set to low level independently of the voltage corresponding to the current and the voltage to be compared therewith. |
| US10277105B1 |
Method and apparatus for delivering power to semiconductors
A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die. Multi-output POL circuits may be used in conjunction with on-chip rail-selection and regulation circuitry to further improve efficiency. A three-stage power conversion system includes off-package, on-package and on-chip conversion stages. |
| US10277104B2 |
Electromagnetic converter, actuator, and pump
An electromagnetic converter that converts kinetic energy to electric energy, or converts electric energy to kinetic energy, includes a core configured to have a coil disposed; a magnet configured to be magnetically coupled with the core; a yoke configured to have the magnet disposed; a fixing portion configured to have the core and the yoke placed; and an elastic member configured to support the yoke, and to elastically deform so as to displace the magnet with respect to the core. Both ends of the elastic member are fixed to the fixing portion. The magnet and the yoke can rotate around an axis in an extending direction of the elastic member. |
| US10277100B2 |
Rotating electric machine
A stator core and a rotor core are provided. The stator core includes field windings receiving a direct current, and armature windings receiving an alternating current. Permanent magnets, each housed in one of the slots together with ones of the field windings, and in contact with the ones of the field windings, are provided. The field windings are provided on both of inner and outer circumferential sides of the permanent magnets. |
| US10277092B2 |
Linear actuator system
A linear actuator system comprising a linear actuator and at least one box with an openable cover. The box comprises a horizontal hinge pin in each side as well as a track in each side, which the respective hinge pins reach into, and where the track on a first run is horizontal and led out to a free edge such that the cover can be placed on the box in a horizontal movement and that the track has a second run in continuation of the first run, and where the second run has a sloping course, which extends down towards the bottom of the box such that the respective hinge pins when the cover is closed are led into the second sloping course of the track. The cover can thus be removed from the box, in case this would be desired, alternatively the cover can remain on the box and be opened by rotating around the horizontal hinge pins. Due to the design of the tracks, which the hinge pins reach into, the cover can be placed on and removed from the box in a horizontal position. By the sloping course of the track the cover will retract itself to its position when it with the hinge pins is slid into the tracks. |
| US10277091B2 |
Motor cap assembly for reducing internal temperatures
Disclosed is an end cap for a motor housing containing an electric motor, including a tubular structure defining an interior space, including an open first end connectable to the mater casing; a second end, including a first planar surface; a second planar surface offset from the first planar surface and substantially parallel to the first planar surface; and at least one air grate surface substantially perpendicular to the first planar surface and the second planar surface, positioned between and attached to the first planar surface and the second planar surface, and wherein the at least one air grate surface includes at least one air grate configured to permit air flow into and/or out of the interior space. |
| US10277085B2 |
Supercharging apparatus for a combustion engine
A supercharging apparatus (20) for a combustion engine (21) having an electrically drivable compressor (1), which has a compressor housing (2) in which a compressor wheel (3) is arranged, which compressor wheel is fastened on one end (4) of a rotor shaft (5), and which has a compressor housing rear wall (6), which is arranged behind the compressor wheel (3) and closes the compressor housing (2); an electric motor (7); and a stator winding (12), which has a line (21) formed from a multiplicity of litz wires (22, 23, 24). The litz wires (22, 23, 24) of the line (21) have a first degree of twisting in an end winding region (25) of the stator winding (12) and have a second degree of twisting in a magnetically active section (I, II, III, IV). The first degree of twisting is higher than the second degree of twisting. |
| US10277078B2 |
Central controller board enhancements for wireless power battery charging systems
Various embodiments of the present technology generally relate to wireless power transmitter and antenna configurations for transmitting wireless power to one or more clients. In some embodiments, the wireless power transmitter includes boards having multiple antennas (i.e., an Antenna Matrix Board(s) (AMB)). The antennas can be on one side of each AMB board, while the control and power circuitry are on the reverse side. The antennas emit electromagnetic (EM) radiant energy that the client(s) receive, store, and/or use for communication with the charger or for the client device battery charging process. The antenna boards can be arranged in a configuration to increase (e.g., optimize) the amount of power transmitted to client(s). In various embodiments, the boards are arranged in polygonal shape as individual flat panels physically coupled to a support structure and attached to the CCB by plug in multiple pin connectors unique in mechanical design. |
| US10277076B2 |
Power receiving unit, power receiving method, and feed system
A power receiving unit of the disclosure includes a communicator that communicates with a feed unit, a power receiver that has a first rectifier circuit and a second rectifier circuit that each rectify an electric power signal supplied from the feed unit, and a controller that selects and operates one of the first rectifier circuit and the second rectifier circuit. |
| US10277075B2 |
Non-contact power reception apparatus for non-contact charging and electronic settlement performed in a single portable terminal
A non-contact power reception apparatus is provided, in which a power reception coil for a charging system and a loop antenna for an electronic settlement system are mounted on a battery pack and a cover case of a portable terminal such that the power reception coil is arranged in the center thereof and the loop antenna is disposed outside the power reception coil, so that a mode of receiving a wireless power signal and a mode of transmitting and receiving data are selectively performed, thereby preventing interference from harmonic components and enabling non-contact charging and electronic settlement using a single portable terminal. A jig for fabricating a core to be mounted to the non-contact power reception apparatus is provided. |
| US10277073B2 |
Non-contact power transmission apparatus and power transmission and reception apparatus
A non-contact power transmission apparatus for transmitting electric power in a non-contact manner to a power reception apparatus comprises a housing configured to include a support section for placing the power reception apparatus and a circuit section for transmission of the electric power therein; a power transmission antenna arranged at a position corresponding to the support section of the housing and configured to transmit AC power to the power reception apparatus; and a hollow formed in the vicinity of the support section in the housing and capable of housing an end protruding to the support section side of a protrusion included in the power reception apparatus. |
| US10277072B2 |
Wireless power receiver with programmable power path
A wireless power receiver IC in which the power path can be reconfigured as either a low-dropout regulator (LDO), a switched-mode power supply (SMPS) or a power switch (PSW) is provided. All three modes share the same pass device to reduce die area and share the same output terminal to reduce pin. In an inductive wireless receiver, the power path can be reprogrammed on the fly to LDO or PSW mode or can be reprogrammed on the fly to SMPS or PSW mode. In a resonant or multi-mode wireless receiver, the power path can be reprogrammed on the fly to SMPS or PSW mode. Furthermore, to achieve high power transfer efficiency performance, using N-channel MOSFET as its pass device has better efficiency and smaller die area than P-channel MOSFET pass device. |
| US10277069B2 |
Wireless power transmitter
A wireless power transmitter includes a case including a base plate and a structure disposed on the base plate; and a transmitting coil having a three-dimensional spiral shape disposed on a side surface of the structure and configured to generate a magnetic field in a direction perpendicular to the side surface of the structure. |
| US10277066B2 |
Method for balancing power in paralleled converters
A method is provided for balancing power amongst parallel connected power converters in an uninterruptible power supply (UPS). The method includes: applying a control signal to each of the parallel connected power converters, where the control signals applied to the parallel connected power converters are derived from a common control signal output by a centralized controller; receiving measurements of current being supplied by each power converter to the load; and adjusting phase of voltage applied to at least one of the power converters based on the received current measurements, such that the phase adjustment causes same magnitude of current to flow though each filter. Advancing phase angle of the voltage increases current supplied by the at least one power converter while retarding phase angle of the voltage decreases current supplied by the at least one power converter. |
| US10277065B2 |
Power supply control device, image processing apparatus, and power supply control method
A power supply control device includes a moving object detecting unit and a power supply unit. The moving object detecting unit is attached to a processing apparatus body including power supply targets and a controller, and is capable of detecting a moving object moving in the vicinity of the processing apparatus body. The moving object detecting unit has a lower detection range for detecting a part of a moving object that is substantially in contact with the floor, and an upper detection range for detecting a top part of a moving object. The power supply unit is included in the controller and is always supplied with power to monitor approach of a moving object with the moving object detecting unit. The power supply unit supplies, upon the moving object detecting unit detecting a moving object, power to a power supply target that includes a part of the controller. |
| US10277062B2 |
System and method for detecting and characterizing an object for wireless charging
A system for detecting and characterizing an object proximate to a wireless power transmitting unit includes a transmit circuit having a transmit antenna, the transmit circuit configured to transmit at least one signal having a frequency related to a fundamental power transmit frequency, the transmit circuit configured to measure a response of the transmit antenna, and a controller circuit configured to characterize the object based on the response of the transmit antenna. |
| US10277056B2 |
Wireless charging station
A wireless charging system including a transmitter and a receiver. The transmitter is formed of a coil of wire that includes a first loop portion, a second loop portion, and a crossing portion. The crossing portion electrically couples the first loop portion and the second loop portion such that when current is generated in the coil, electrical current flows through the first loop portion in a different rotational direction than in the second loop portion. The receiver is formed of a ferromagnetic core and multiple (e.g., three) coils disposed about the ferromagnetic core. Each coil may be disposed about a different axis of the core such that current may be induced in at least one of the coils by a magnetic field in any direction. |
| US10277055B2 |
Battery wireless charging system
A system for wirelessly charging an electrical energy storage device such as an electrochemical cell or battery pack is described. The system comprises a transmitting base unit having a charging tray that is capable of wirelessly transmitting electrical power received from an external electrical energy source. In addition, the system comprises an electrical energy capture assembly that is electrically incorporatable with an energy storage device. The energy capture assembly comprises a receiving coil that is electrically connected to various sub-circuits that condition and modify the wirelessly received electrical energy so that it re-charges the energy storage device. The system is primarily designed to be used with electrical power that is wirelessly transmitted by near field magnetic induction. The circuitry of the system is designed to accommodate for fluctuations in magnitude of wirelessly transmitted electrical power. In addition, system is designed to optimally utilize wireless near field magnetic induction electrical power. |
| US10277054B2 |
Near-field charging pad for wireless power charging of a receiver device that is temporarily unable to communicate
Disclosed is a system including RF circuitry configured to generate an RF signal; a plurality of unit cells configured to receive the RF signal and to cause an RF energy signal having a center frequency to be present within the unit cells; and receiver circuitry configured to charge an electronic device in response to an antenna of the electronic device receiving the RF energy signal when the antenna is tuned to the center frequency and positioned in a near-field distance from one or more of the unit cells. |
| US10277052B2 |
Controlling power delivery to a battery
A controller for controlling power delivery to a battery includes a first terminal that provides a first signal to enable a bypass path to deliver power from an interface to charge the battery, and includes a second terminal that provides a second signal to enable a conversion circuit to convert input power received at the interface to output power to charge the battery. The controller also includes circuitry that determines whether a first adapter or a second adapter is connected to the interface, generates the second signal if the second adapter is connected to the interface, generates the first signal and a request if the first adapter is connected to the interface, and provides the request to the first adapter through the interface. The request includes information indicative of a target level and an instruction that causes the first adapter to provide power at the target level to the interface. |
| US10277051B2 |
Electronic device, battery module and charging and discharging method
A battery module includes a crystal lattice type battery, a detection circuit, a control circuit and an excitation circuit. The detection circuit is electrically coupled to the battery. The control circuit is electrically coupled to the detection circuit. The excitation circuit is electrically coupled to the control circuit and the battery. When the battery is charged or discharged, the detection circuit is configured to detect an impedance of the battery. The control circuit is configured to compare the impedance and a threshold. And the control circuit is configured to produce a control signal. The excitation circuit is configured to selectively provide an excitation signal to the battery according to the control signal. |
| US10277048B2 |
Half bridge power conversion circuits using GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. |
| US10277045B2 |
Electronic device charger
The present invention discloses an electronic device charger, mainly comprising: a voltage converting module, a microprocessor, a low voltage detecting unit, and an over voltage sensing unit. When a rated output voltage of a vehicle battery of an electric vehicle is detected to be lower than a first threshold voltage by the low voltage detecting unit or found to be higher than a second threshold voltage by the over voltage sensing unit, the microprocessor immediately stops the vehicle battery providing electrical power to at least one portable electronic device owned by the driver of the electric vehicle. Therefore, the electronic device charger can not only save the energy of the vehicle battery while the vehicle battery is at a low voltage state, but also protect the portable electronic devices from being damaged by the electrical power as the rated output voltage of the vehicle battery exceed a normal voltage level. |
| US10277039B2 |
Resonant power transfer systems with protective algorithm
Systems for tuning a wireless power transfer system are provided, which may include any number of features. In one embodiment, a TET system includes a receive resonator is adapted to be implanted in a human patient and is configured to receive wireless power from a transmit resonator. The system can include a controller configured to identify if a foreign object is interfering with the transmission of power or generating an induced voltage in the receiver resonator. The controller can also be configured to control the transmit resonator to phase match with the foreign object. Methods of use are also provided. |
| US10277038B2 |
Power transmission apparatus and wireless power transmission system
A power transmission apparatus includes the following elements. A position detection coil detects a signal from a power reception coil of a power reception apparatus installed on an installation surface. A position detection circuit determines from the detected signal that the power reception apparatus is installed on the installation surface. A reception circuit receives a wireless signal transmitted from the power reception apparatus via the position detection coil. A switch circuit switches electrical connection of the position detection coil between the position detection circuit and the reception circuit. A power transmission control circuit switches electrical connection of the position detection coil from the position detection circuit to the reception circuit if it is determined that a voltage or a current of the detected signal has been smaller than a reference value for a predetermined period, and causes the reception circuit to receive the wireless signal via the position detection coil. |
| US10277033B2 |
Method and device for controlling distributed generator in distribution system
The present disclosure provides a method and a device for controlling a distributed generator in a distribution system. The method includes: extracting a first statistic feature of a load at each bus; extracting a second statistic feature of a distributed generator at each bus; establishing a probability distribution set of each first and second statistic feature; determining security constraints of the distribution system; obtaining a bilinear matrix inequality constraint by using a C-VaR approximation algorithm and a duality algorithm based on the probability distribution set and on the security constraints; determining an objective function to maximize a total installed capacity of the distributed generators; solving the objective function according to the bilinear matrix inequality constraint to obtain an installed capacity of each distributed generator; and controlling an access of each distributed generator according to the installed capacity. The method may take full use of statistic features and has higher practicability. |
| US10277032B2 |
DC voltage droop control method with dead-band for HVDC grids based on DC voltage fiducial node
The present invention discloses a fiducial node DC voltage based DC voltage droop control method with dead-band for HVDC grids. Two levels of DC voltage control e.g. primary and secondary DC voltage regulation are introduced to realize load sharing and DC voltage control in HVDC grids. In the process of primary DC voltage regulation, the power flow regulation ability of the entire HVDC grids can be significantly improved, and the DC voltage and stability of the HVDC grids will be quickly controlled and guaranteed for the benefit of droop characteristic. Secondary DC voltage regulation is achieved by by introducing the load-DC voltage controller. In the process of secondary DC voltage regulation, the burden of accommodating power imbalance by the DC voltage fiducial node will be alleviated, thus improving the ability to resist disturbances of the entire HVDC grids. |
| US10277031B2 |
Systems for provisioning energy generation and storage systems
Techniques for provisioning energy generation and/or storage systems. In one embodiment, a method is provided that can comprise automatically determining, by a site gateway, information pertaining to one or more components of an energy storage system, where the site gateway and the one or more components are located at a customer site. The method can further comprise configuring, by the site gateway, the energy storage system based on the automatically determined information. |
| US10277030B2 |
Load balancing for power distribution
According to one aspect, embodiments of the invention provide a PDU comprising an input configured to receive 3-phase power from a power source, a plurality of phase lines, each phase line configured to carry one phase of the 3-phase power, at least one outlet, at least one switch circuit configured to selectively couple the at least one outlet to the plurality of phase lines, a data connection, and a controller, wherein the controller is configured to monitor current from the plurality of phase lines to the at least one outlet, receive, via the data connection, phase loading information related to 3-phase power of at least one external device coupled to the power source, and operate the at least one switch circuit to selectively couple the at least one outlet to at least one of the plurality of phase lines based on the current and the received phase loading information. |
| US10277029B2 |
Energy storage system with dual-active-bridge converter
An energy storage device includes: a number of cells; and a dual-active-bridge converter connected to the cells, wherein the cells are floating relative to the system and are galvanically isolated therefrom. The energy storage device can be included in an energy storage system that includes: a grid tie unit comprising at least one DC/AC converter; and multiple pods connected to the grid tie unit, each pod including: a number of cells; and a power electronics unit, wherein the cells are floating relative to the system and are galvanically isolated therefrom. |
| US10277027B2 |
Apparatus for isolating a network protector in an electric power distribution network
An apparatus for isolating a malfunctioning network protector from the power distribution network and for allowing the network protector to be safely reset. The apparatus includes: a 3 phase controller coupled by parallel single phase poles in plural contactors to the fuse link and adapted to receive an electric load current flowing in reverse through the network power transformer; a remote controlled switch coupled to the controller for switching the electric load current from the network protector via the controller to the network bus, with the controller then carrying the electric load current in parallel with the network protector fuse link; and visual indicators coupled to the controller for showing when the remote controlled switch has been activated to transfer the load current from the fuse links to the controller and when the electric load current has been transferred from the controller to the network bus. |
| US10277026B2 |
Power converter
A power converter connected between a direct current power supply and a load, the power converter including a switching unit energizing the load based on inputted control signal, a voltage detector detecting a voltage of the direct current power supply, and a protection operation portion detecting a steep elevation of the voltage and performing protection operation to stop a switching operation by the switching unit, wherein the protection operation portion includes an addition circuit adding a predetermined voltage to the voltage detected by the voltage detector and a delay time generator connected to an output of the addition circuit, and wherein the protection operation is performed when a difference between the voltage detected by the voltage detector and an output voltage of the delay time generator reaches a certain value. |
| US10277024B2 |
Telecommunications enclosure with cable seal
A telecommunications enclosure is provided with reliable sealing around cables entering therein. The enclosure includes one or more cable ports with cable seals made from a material that includes an oil-bleed silicone rubber. The cable ports may also have a convoluted or serrated inner surface configured to engage and support the cable seals. |
| US10277019B2 |
Electric circuit apparatus
An electric circuit apparatus capable of enhancing connection workability is provided. An electric circuit apparatus includes: a connector that transmits one or a driving current and a signal to an electric circuit unit; a substrate connected to the connector; a first case member forming an housing space for the substrate and forming an opening portion; and an intermediate member interposed between the connector and the first case member, in which the intermediate member includes a connector-side opening portion through which the connector passes, a seal surface with the connector, and a fix in portion to be fixed on the first case member, and the fixing portion is formed so as to absorb a positional tolerance between the connector and the opening portion of the first case member. |
| US10277018B2 |
Cable clamping apparatus
Embodiments herein discuss a clamping apparatus for a cable gland. The clamping apparatus includes a first body member having a first aperture therethrough for receiving a cable, a plurality of clamping members pivotably mounted relative to the first body member, and a second body member for causing the clamping members to move relative to the first body member into clamping engagement with the cable. |
| US10277016B2 |
Hand-held cable coating device
A hand-held apparatus for repairing a defect in an outer jacket of an elongated wire or cable includes a portable die and a source of a settable material. The die has a first portion connected by a hinge to a second portion. They cooperatively define a channel in a closed configuration. The source is connected to the channel through an opening between the inlet and outlet. A heating element is adapted to heat the settable material into a flowable condition and a control circuit is adapted to vary the supply of heat. The die is juxtaposed around the jacket near the defect. As the settable material is introduced into the channel, the wire or cable is moved along the channel relative to the die in the closed configuration such that a coating is formed over the defect. When the die is removed, the settable material sets into a solid condition. |
| US10277007B1 |
Laser diode firing system
A laser diode firing circuit for a light detection and ranging device is disclosed. The firing circuit includes a laser diode coupled in series to a transistor, such that current through the laser diode is controlled by the transistor. The laser diode is configured to emit a pulse of light in response to current flowing through the laser diode. The firing circuit includes a capacitor that is configured to charge via a charging path that includes an inductor and to discharge via a discharge path that includes the laser diode. The transistor controlling current through the laser diode can be a Gallium nitride field effect transistor. |
| US10277006B2 |
Light-emitting device and distance measurement device
Provided is a technology for suppressing variations in the waveform of a light emission pulse caused by various factors in a light-emitting device. A light-emitting device is provided with: a light source 101 in which relaxation oscillation occurs immediately after energization; a light source drive circuit 104 which includes a differentiation circuit 102 having a resistor and a capacitor connected in parallel, and in which a switching element 103 for voltage application is connected in series with the differentiation circuit; a power supply circuit 105; a light-reception element 107 which detects pulsed light emitted from the light source 101; and a voltage control unit 109 which controls an output voltage from the power supply circuit 105 in correspondence with the waveform of the detected pulsed light. |
| US10277003B2 |
Laser device and laser device manufacturing method
In a laser device 1 in which a laser module 2 is mounted on a heat sink 3, a base plate 20 of the laser module 2 is fixed onto a mounting surface 3s of the heat sink 3 in such a manner that a peripheral part 20b is fixed to the heat sink 3 with screws. The elastic force of the base plate 20 causes stress in the direction toward the mounting surface 3s on the central part 20a of the base plate 20 surrounded by the peripheral part 20b. |
| US10276998B2 |
Solid-state laser device and photoacoustic measurement device
In a solid-state laser device and a photoacoustic measurement device including the solid-state laser device, the distance between a laser rod and a flash lamp is narrowed. A shielding lid shields mirrors and an optical path of laser light from the outside. A first portion of a frame body of a laser chamber is exposed from the shielding lid. A flash lamp stored in the frame body of the laser chamber is able to be removed from and inserted into the first portion of the frame body. A thin film portion having a thickness smaller than the thickness of other portions of the shielding lid is provided in at least a part of a region of the shielding lid covering the optical path of a light beam on the outside in a longitudinal direction from the first portion of the frame body of the laser chamber. |
| US10276996B2 |
Location tracking power cord and method therefore
A location tracking power cord and method therefore is taught in the various embodiments. The power cord includes a location module housing having a location circuit board therein. Within the location module housing, a power supply is positioned and in electrical communication with conductors extending through the cord housing. The location module housing also provides location for a communication module including a location module such as a Global Positioning System (GPS) satellite receiver and at least one cellular transceiver. In some embodiments, the power cord may be hospital grade. |
| US10276990B2 |
Telecommunications assembly with patch cord storage
A telecommunications assembly includes a tray assembly including a tray and a cable spool assembly rotatably mounted to the tray, a connector holder arrangement for temporarily holding connectors, wherein the connector holder arrangement is mounted for rotation with the cable spool assembly, and cable storage arrangements for individually storing cables from the cable spool assembly to the connector holder arrangement. After a main cable is unwound from the cable spool assembly, a connector can be removed from the connector holder assembly, and cable slack stored in the cable storage arrangement can be removed allowing connection of the connector to equipment. |
| US10276989B2 |
Electrical connector with intimate side arms extending from metallic shell and integrally formed within insulative shell
An electrical connector includes a contact module enclosed within a metallic inner shell. The inner shell is formed by stamping and forming, and includes opposite first and second side walls in a vertical direction, and a pair of end walls opposite to each other in the transverse direction and linking the opposite first and second side walls in the vertical direction. Each end wall includes a first arm extending rearwardly from a rear edge and a second arm intimately located beside the first arm either in a unitarily folded manner or a discretely soldered manner. The second arm is located outside of the corresponding first arm in the transverse direction wherein the first arm forms a first mounting leg and the second arm forms a second mounting leg extending through an insulative outer shell which is overmolded upon the inner shell. |
| US10276987B2 |
Shielded connector structure including shielded wire for connecting a device, a shielded connector, and a metal member
A shielded connector structure includes a shielded wire for connecting a device, a shielded connector, and a metal member provided on the device. The shielded connector includes a terminal fitting, a shield terminal, a housing, and a bolt for fixing the housing to the metal member. The metal member includes a circular insertion hole and a female screw portion. The circular insertion hole includes an inner circumferential projected portion and a cutout portion that divides a part of the inner circumferential projected portion. The housing includes a cylindrical housing main body and a fixing flange portion. The housing main body includes a main body insertion portion inserted into the circular insertion hole and a projection portion which protrudes from an outer circumferential surface of the main body insertion portion in conformity with a position of the inner circumferential projected portion. |
| US10276981B2 |
Connector member and connector
Provided are a connector member and a connector that suppress breakage due to butting, pressing in a fitting direction. In the connector, a first connector member having a first housing is fitted with a second connector member having a second housing and a supporting member having a cylindrical shape that supports the second housing. The second housing has a pair of shaft pins formed at positions opposed to each other on the supporting member side. The supporting member has a support claw including a pair of claw pieces that are elastically deformable and hold each of the shaft pins. After the first connector member and the second connector member are fitted together, when a pressure is applied thereto in a fitting direction, the shaft pins are moved to cause the claw pieces of the support claw to elastically deform, causing the shaft pins to detach from the support claw. |
| US10276980B2 |
Connector with a CPA receiving space and connector assembly comprising such a connector
A connector comprises a connector face, a latch, and a CPA receiving space. A plurality of contact receiving spaces of the connector are open to the connector face. The latch engages a mating connector when the connector is inserted into the mating connector along an insertion direction. The CPA receiving space is disposed adjacent an inner side of the latch and receives a position securing member. At least one contact receiving space is disposed between the connector face and the CPA receiving space. |
| US10276979B2 |
Plug retention system
Retention components are provided that are configured to retain a first end of an electrical cord in a plugged configuration with an electrical outlet. The retention components have an interior sized to receive the first end therein and include an wire opening having at least one dimension that is smaller than the corresponding dimension of the first end so that the first end cannot pass therethrough. In one form, a wall plate is provided having retention portion configured to retain a first end of an electrical cord, such that with the wall plate secured to a wall or other substrate, the first end of the electrical cord is retained between the wall and the wall plate. |
| US10276974B2 |
Plug connector with locking and grounding structures
A plug connector includes an insulating body having a mating portion, a ground terminal, and a latch member. A mating slot is disposed in the mating portion. The ground terminal has a first contacting portion protruding and extending into the mating slot, and a first tail portion. The latch member has a connecting portion and two locking arms located on two sides of the connecting portion. The first tail portion is in contact with the connecting portion, or in contact with the locking arms. Plate surfaces of the first tail portions are perpendicular to plate surfaces of the locking arms. The locking arms are located on two sides of the mating portion and respectively have a locking portion protruding and extending into the mating slot. The locking portions are used for engaging with buckling slots of a tongue. |
| US10276971B2 |
Electrical connector having an insulative outer cover and a sealing member secured to the outer cover via a dovetail structure
An electrical connector includes: a contact module including an insulative housing and an upper and lower rows of contacts, the insulative housing having a base and a tongue, the upper and lower rows of contacts being exposed respectively to an upper and lower surfaces of the tongue; a shielding shell enclosing the contact module; an insulative outer cover enclosing the shielding shell, the outer cover having plural peripheral grooves at a front end thereof; and a sealing member having plural protrusions secured to corresponding grooves. |
| US10276970B2 |
Cord and plug cover with one or more pockets and/or support surfaces
A cover suitable for covering a portion of one or more extension cords is disclosed. A cord plug cover includes a plurality of sides that provide a generally covered area. In embodiments, one or more of the plurality of sides include one or more slots and one or more support surfaces. In embodiments, the support surfaces is configured to receive or support one or more extension cords that extend through the cover and the covered area. Embodiments of a cord plug cover include one or more of the following: one or more rib elements, one or more relief portions, one or more pockets, and/or one or more securing formations. |
| US10276967B2 |
Electrical connector including latch assembly
Methods and apparatus are disclosed for supporting first and second electrical connectors on a substrate. For instance, the first electrical connector includes electrical contacts that are configured to be mounted to the substrate. The second electrical connector includes electrical contacts that are configured to be mounted to a complementary electrical component other than the substrate. The second electrical connector is thus configured to be attached to the first electrical connector, such that the second electrical is supported by the substrate without being mounted to the substrate. |
| US10276966B1 |
Electrical connector with alignment plate and seal
An electrical connector assembly having a housing, an alignment plate, a back plate and a sealant. The housing has a bottom wall and a shroud extending therefrom. A recess is provided in the housing proximate the bottom wall, the recess extends in a direction away from the shroud. The alignment plate has housing latching members which extend through latch receiving openings in the bottom wall of the housing. The housing latching members and the alignment plate are movable between a first position and a second position. The back plate is positioned in the recess of the housing. The back plate has latching member receiving projections for receiving the housing latching members when the alignment plate is in the second position. The seal is positioned in the recess of the housing. The sealant positioned in the recess of the housing. |
| US10276964B2 |
Contact carrier
A contact carrier can be inserted into the contact carrier and removed again by a slight elastic deformation of a holding element, a detent engagement action of a detent of the holding element with a further detent of a main body of the contact carrier can be released. A particularly simple mounting and dismounting of a contact element in the contact carrier is realized. The contact carrier is constructed such that the holding element and the contact element can be inserted into the main body from an attachment side which is situated opposite a plug-in side. |
| US10276959B2 |
Contact element and equipping arrangement with said contact element
A contact for an electrical plug connector comprises a plug portion and a contact spring. The plug portion has an opening receiving a pin contact in an insertion direction. The contact spring is connected by at least one spring arm base to the plug portion and extends from the at least one spring arm base toward the opening in a direction opposite the insertion direction. The contact spring exerts a contact force on the pin contact perpendicular to the insertion direction. |
| US10276958B1 |
Electrical contact grid array
An electrical contact grid array includes a board having a top side and an opposite bottom side, a plurality of signal conductors mounted to the board, and a plurality of ground shield structures mounted to the board. Each of the signal conductors includes an upper signal contact extending beyond the top side of the board for electrically connecting with a corresponding mating contact of a mating circuit board. Each of the ground shield structures includes at least one ground contact disposed above the top side of the board that defines an upper annular shield. The upper annular shield circumferentially surrounds at least one of the upper signal contacts. |
| US10276956B2 |
Miniaturized electrical connector for connecting a CPU
An electrical connector for electrically connecting a chip module includes an insulating body, a signal terminal received in the insulating body, and a first and a second shielding sheets retained in the insulating body. The insulating body sustains a chip module, and the signal terminal elastically urges against the chip module. The first shielding sheet is located on one side of the signal terminal and elastically urges the chip module. The second shielding sheet is located on the other side of the signal terminal, and adjacent to the first shielding sheet. The first and second shielding sheets are communicated through an electric conductor. The second shielding sheet does not urge the chip module. |
| US10276955B2 |
Electrical connector
An electrical contact includes a main body and a compliant pin extending from the main body. The compliant pin includes a through-hole. The compliant pin is configured to be compressed. The electrical contact also includes a first leg and a second leg that each extend from the main body. The compliant pin is between the first leg and the second leg. The compliant pin, the first leg, and the second leg extend from the main body in a same direction. The electrical contact further includes a first blade and a second blade that each extend from the main body. A slot is formed between the first blade and the second blade, and a width of the slot is larger at a first position adjacent a distal end of the first and second blades than at a second position adjacent a proximal end of the first and second blades. |
| US10276954B2 |
Board-to-board connectors and mounting structure
A circuit card assembly includes a first printed wiring board with a first receiving feature and a trace attached to the first printed wiring board. The three dimensional trace is formed by layer-by-layer additive manufacturing. The three dimensional trace includes first and second ends. The first end of the three dimensional trace engages with the first receiving feature of the first printed wiring board. The second end of the three dimensional trace is configured to engage with a second printed wiring board. |
| US10276949B2 |
Connector and blind mating connector including the same
Provided are a connector and a blind mating connector including the same. The connector in accordance with the present invention includes a hollow body formed by bending a metal plate that is manufactured by press-processing a raw plate, a dielectric part built in the body, a signal pin passing through the dielectric part, a plurality of contact parts extending from both ends of the body, respectively, with a slit therebetween, a connection part defined in the body and at which both side ends of the metal plate are met and coupled, and an extension contact part bent and extending from one end of the contact part in a direction opposite to an extension direction of the contact part to face the contact part. |
| US10276944B1 |
3D folded compact beam forming network using short wall couplers for automotive radars
A radar system includes a plurality of radiating elements configured to radiate electromagnetic energy and a plurality of feed waveguides defining a common plane and configured to guide electromagnetic energy to the plurality of radiating elements. The radar system also includes a plurality of waveguides arranged as a dividing network, where the dividing network includes one or more coupling apertures located in the common plane. The dividing network is configured to receive electromagnetic energy from a source and split the electromagnetic energy among the plurality of feed waveguides, such that each feed waveguide receives a respective portion of the electromagnetic energy. The splitting and adjusting of the radar system are based in part on the one or more coupling apertures in the dividing network. |
| US10276940B2 |
Multi-band subscriber antenna for portable radios
An antenna is provided with improved ruggedness and flexibility through the use of an embedded substrate with impedance matching circuitry disposed thereon, and a flexible electrical interconnect. The flexible electrical interconnect is coupled between the substrate and an antenna connector. The antenna comprises a first top flexible section having the flexible radiator element, a second stiff section comprising the impedance matching circuit for multi-band operation, and a third lower flexible section comprising the flexible electrical interconnect. Portable radio products incorporating the antenna can now provide multiband capability along with protection against drop. |
| US10276939B1 |
Through-the-lid pit antenna
A pit antenna assembly includes a node, the node including an antenna, the antenna configured to radiate radio waves; an inner tube defining a first inner tube end and a second inner tube end, the first inner tube end disposed opposite from the second inner tube end, the inner tube defining an inner tube bore extending through the inner tube from the first inner tube end to the second inner tube end, the antenna received within the inner tube bore through the first inner tube end, the inner tube configured to electromagnetically couple energy from the antenna; and a top disc, the top disc connected to the second inner tube end of the inner tube, the top disc configured to radiate the energy from the antenna. |
| US10276938B2 |
Mobile terminal device
A mobile terminal device is disclosed. The mobile terminal device includes a metal rear cover; a metal frame forming an accommodation space with the metal rear cover; a printed circuit board assembly; and an antenna module inside the accommodation space and electrically connected with the printed circuit board assembly. The antenna module includes a grounding terminal and a feeding point disposed on the printed circuit board assembly. The metal rear cover includes a first metal part, a second metal part, a third metal part and the two coupled gap. The first metal part and the third metal part are connected to both ends of the second metal part. |
| US10276937B2 |
Jet dispensing electrically conductive inks
A method of forming a conductive trace that includes selecting a substrate, jet dispenser, and conductive ink; measuring the ink's viscosity (Vm); using Vm to select one of criteria (i)-(iv): applying the selected criteria to the dispenser; applying the ink onto the substrate; and drying, curing, or annealing the ink to form the conductive trace having ≥4B adhesion. The criteria (i)-(iv) including: (i) (Vm)>2.0 Pa-s, then (1) add a fluid—repeat D)-E) or (2) repeat C)-E); (ii) 2.0 Pa-s≥Vm>0.35 Pa-s, use needle diameter ≥3.0 mm & nozzle diameter (d)≥0.15 mm with ratio of nozzle length (L) to nozzle diameter (d)≤30; (iii) Vm<0.25 Pa-s, use a needle diameter ≥1.0 mm and <3.0 mm & nozzle diameter ≥0.15 mm with L/d≤30; or (iv) 0.25 Pa-s≤Vm≤0.35 Pa-s, use criteria (ii) or (iii). |
| US10276928B2 |
Sensor device for a motor vehicle
A sensor device for a motor vehicle, including a first transmitting antenna, which is situated on a surface of a substrate, has a narrow lobe-type directional characteristic and includes a defined number of planar antenna elements; a second transmitting antenna situated on the surface of the substrate has a wide lobe-type directional characteristic, including a defined number of planar antenna elements, the directional characteristics of the two transmitting antennas being oriented opposite one another by a defined angle, with respect to a boresight; and at least one receiving antenna situated on the surface of the substrate including a defined number of planar antenna elements. |
| US10276925B2 |
Watch with slot antenna configuration
A wrist-worn electronic device includes a side wall formed of electrically nonconductive material, a printed circuit board, a location determining element, a bezel, and a first antenna. The location determining element is configured to receive a first electronic signal and determine a current geolocation of the electronic device. The bezel is formed of electrically conductive material, positioned above the nonconductive side wall, such that a nonconductive slot is formed between the bezel, a perimeter of the printed circuit board, and electrical connections to two of the electrical ground terminals on the printed circuit board. The first antenna is formed at least partially by an upper portion corresponding to a circumference of the bezel between the two electrical ground terminal and configured to wirelessly receive the first electronic signal and communicate the first electronic signal to the location determining element. |
| US10276916B2 |
Antenna device
An antenna device includes a first plate conductor that is disposed approximately in parallel to the GND conductor plate, of which one end is connected to the GND conductor plate, and the other end that is opposed to the one end is opened, and a second plate conductor that has approximately the same shape as that of the first plate conductor, of which one end is grounded to the GND conductor plate, of which the other end that is opposed to the one end is opened, that is disposed at a position obtained by rotating the first plate conductor approximately 180 degrees about an intersection line passing through an approximately central point of the GND conductor plate as an axis on the same plane as the first plate conductor on the GND conductor plate, and that has a ground portion at which the grounding is performed and an open portion at which the opening is performed at positions obtained by rotating the ground portion and the open portion of the first plate conductor approximately 180 degrees about the axis. |
| US10276914B2 |
Transversely clampable linear adjustment mechanism
In certain embodiments, a linear adjustment mechanism includes an adjustment plate, an adjustment nut, and a holding plate. The adjustment plate has an exterior-threaded section that engages with the adjustment nut, a mounting-bolt opening, and a clamping-bolt slot. The holding plate has a horizontal section having a clamping-bolt opening, a vertical section connected to the horizontal section, and an adjustment-nut opening. With (i) the adjustment nut engaged with the adjustment-nut opening and the exterior-threaded section of the adjustment plate and (ii) the clamping bolt inserted within (a) the clamping-bolt slot of the adjustment plate and (b) the clamping-bolt opening of the holding plate, (1) rotation of the adjustment nut on the exterior-threaded section of the adjustment adjusts the linear position of the adjustment plate relative to the holding plate and (2) rotation of the clamping bolt secures the linear position of the adjustment plate relative to the holding plate. |
| US10276906B1 |
Systems and methods for combining or dividing microwave power
A power combiner/divider includes a main conductor defining an axis; an input connector having a center conductor, adapted to be coupled to a signal source, electrically coupled to the main conductor and having an axis aligned with the main conductor axis, and having a second conductor electrically coupled to a ground conductor; a plurality of satellite conductors radially exterior of and spaced apart from the main conductor, the satellite conductors defining the general shape of a slotted hollow cylinder having a cylinder axis aligned with the main conductor axis; a plurality of output connectors having center conductors electrically coupled to respective satellite conductors and having respective second conductors electrically coupled to a second ground conductor; and a multiconductor transmission line, including the satellite conductors, defined between the input connector and the output connectors. Methods of manufacturing are also disclosed. |
| US10276902B2 |
Secondary battery having improved safety
A pouch type secondary battery includes an electrode assembly and a pouch sheath material including a first pouch portion and a second pouch portion. The pouch-type secondary battery includes dual electrode leads wherein a first electrode lead is attached to the first pouch portion and a second electrode lead is attached to the second pouch portion. In the pouch-type secondary battery, electric current is interrupted by using a volumetric swelling phenomenon caused by swelling or pressure generated upon overcharge so that the battery may be prevented from being further charged. In addition, when pressure is increased by an additional reaction, venting occurs toward the inner lead portion of each of the dual electrode leads. As a result, it is possible to increase the stability of a battery cell, module and a pack received in the pouch, and thus to improve the life of a battery. |
| US10276897B2 |
Apparatus for managing power of a vehicle and a method of controlling the same
An apparatus for managing power of a vehicle and a method of controlling the same, for effectively shutting off dark current are disclosed. The method includes determining a first battery state when a preset first condition is satisfied; cutting off a first portion load or all loads based on the determination of the first battery state; determining a second battery state when a preset second condition is satisfied; and releasing load interruption or cutting off a second portion load except for the first portion load from the all loads based on the determination of the second battery state. |
| US10276896B2 |
Nickel-zinc battery
Provided is a highly reliable nickel-zinc battery, which includes a separator exhibiting hydroxide ion conductivity and water impermeability. The separator is disposed in a hermetic container to separate a positive-electrode chamber from a negative-electrode chamber. The positive-electrode chamber has an extra positive-electrode space having a volume that meets part of a variation in amount of water in association with the positive electrode reaction, and the negative-electrode chamber has an extra negative-electrode space having a volume that meets part of a variation in amount of water in association with the negative electrode reaction. The battery further includes a gas-liquid flow channel that connects the extra positive-electrode space to the extra negative-electrode space, and the gas-liquid flow channel allows the electrolytic solution and gas in the positive-electrode and negative-electrode chambers to pass through the flow channel in response to a variation in amount of water caused by charge and discharge reactions. |
| US10276882B2 |
Fuel cell system and method for controlling fuel cell system
A fuel cell system controls an amount of cooling water supplied to a radiator and an amount of cooling water supplied into a radiator bypass pipe by regulating a temperature of a thermostat valve by controlling a temperature of a heat medium in a housing by an air conditioning apparatus. |
| US10276880B2 |
Method for producing a fuel cell and a fuel cell system
A method is provided for producing a fuel cell, which method includes the arrangement of in each case one gas diffusion layer with in each case one bipolar plate on a respective side of a membrane electrode arrangement which comprises an anode, a cathode and an electrolyte membrane arranged between the anode and the cathode. The gas diffusion layers are set back in relation to the bipolar plates and the membrane electrode arrangement. The gas diffusion layers have in each case at least one reaction fluid supply region and in each case at least one reaction fluid discharge region and in each case at least one reaction fluid sealing region. The method is characterized by injecting a sealing material into at least one reaction fluid sealing region of at least one gas diffusion layer such that the gas diffusion layer is sealed off to the outside. |
| US10276878B2 |
Coated aluminum bipolar plate for fuel cell applications
A fuel cell flow field plate includes an aluminum substrate plate having a first side and a second side wherein the first side of the aluminum substrate plate defines a plurality of channels for transporting a first fuel cell reactant gas. The flow field plate also includes a first metal interlayer deposited on the first side of the aluminum substrate plate, a second metal interlayer deposited on the second side of the aluminum substrate plate, a first amorphous carbon layer deposited on the first metal interlayer, and a second amorphous carbon layer deposited on the second metal interlayer. The first amorphous carbon layer and second amorphous carbon layer each independently have a density greater than or equal to 1.2 g/cc. |
| US10276875B2 |
Anode for molten carbonate fuel cell having improved creep property, method for preparing the same, and molten carbonate fuel cell using the anode
An anode for a molten carbonate fuel cell (MCFC) having improved creep property by adding CeO2 and/or Cr for imparting creep resistance to nickel-aluminum alloy and nickel as materials for an anode is provided. Improved sintering property, creep property and increased mechanical strength of a molten carbonate fuel cell may be obtained accordingly. |
| US10276873B2 |
Current collector for battery comprising metal mesh layer and manufacturing method therefor
Provided are a current collector for a battery, including: a base material; adhesive layers positioned on the base material; and metal mesh layers positioned on the adhesive layers, in which the metal mesh layer includes a plurality of metal mesh patterns, and holes positioned between the metal mesh patterns, and a method of manufacturing the same. An active material is applied onto the metal mesh layer through the holes of the metal mesh layer, and thus a contact area of the metal mesh layer and the active material is increased, so that it is possible to restrict the active material from being deintercalated from the current collector and improve a cycle lifespan property of a battery. |
| US10276872B2 |
Electrolyte for rechargeable electrochemical cell
The present invention provides an aqueous electrolyte for use in rechargeable zinc-halide storage batteries that possesses improved stability and durability and improves zinc-halide battery performance. One aspect of the present invention provides an electrolyte for use in a secondary zinc bromine electrochemical cell comprising from about 30 wt % to about 40 wt % of ZnBr2 by weight of the electrolyte; from about 5 wt % to about 15 wt % of KBr; from about 5 wt % to about 15 wt % of KCl; and one or more quaternary ammonium agents, wherein the electrolyte comprises from about 0.5 wt % to about 10 wt % of the one or more quaternary ammonium agents. |
| US10276871B2 |
Rechargeable lithium battery
A rechargeable lithium battery includes a negative electrode including a negative active material including a silicon-based material and a carbon-based material; and an electrolyte solution, wherein the negative electrode further includes greater than or equal to about 0.01 parts by weight and less than or equal to about 1 part by weight of a compound represented by Chemical Formula 1, based on 100 parts by weight of the negative active material, and at least one, selected from the electrolyte solution and the negative electrode, includes greater than or equal to about 0.1 wt % and less than or equal to about 2 wt % of lithium fluorosulfonate and/or lithium bis(fluorosulfonyl)imide, based on the total weight of the electrolyte solution: |
| US10276869B2 |
Beta-delithiated layered nickel oxide electrochemically active cathode material and a battery including said material
The invention is directed towards an electrochemically active cathode material. The electrochemically active cathode includes beta-delithiated layered nickel oxide. The beta-delithiated layered nickel oxide has an X-ray diffraction pattern. The X-ray diffraction pattern of the beta-delithiated layered nickel oxide includes a first peak from about 14.9°2θ to about 16.0°2θ; a second peak from about 21.3°2θ to about 22.7°2θ; a third peak from about 37.1°2θ to about 37.4°2θ; a fourth peak from about 43.2°2θ to about 44.0°2θ; a fifth peak from about 59.6°2θ to about 60.6°2θ; and a sixth peak from about 65.4°2θ to about 65.9°2θ. |
| US10276868B2 |
Non-aqueous electrolyte rechargeable battery
A non-aqueous rechargeable battery has a non-aqueous electrolyte and positive and negative electrodes capable of intercalating and deintercalating lithium ions. The positive electrode contains a lithium transition metal oxide expressed by Li2-xNiαM1βM2y O4-ε,where 0.50<α<=1.33, 0<=β<0.67, 0<=γ<=1.33, 0<=ε<=1.00, M1 is at least one of Co, Al and Ga, and M2 is at least one of Mn, Ge, Sn and Sb, and x reversibly varies within a range of 0<=x<=2 by intercalating and deintercalating lithium ions. A resistance of the positive electrode when SOC is 0% is not less than twice of that when SOC is not less than a predetermined SOC. A capacity of the negative electrode is not less than 1.1 times of that of the positive electrode. |
| US10276867B2 |
5V-class spinel-type lithium-manganese-containing composite oxide
Provided is a new 5 V-class spinel-type lithium-manganese-containing composite oxide capable of achieving both the expansion of a high potential capacity region and the suppression of gas generation. Proposed is the spinel-type lithium-manganese-containing composite oxide comprising Li, Mn, O and two or more other elements, and having an operating potential of 4.5 V or more at a metal Li reference potential, wherein a peak is present in a range of 14.0 to 16.5° at 2θ, in an X-ray diffraction pattern measured by a powder X-ray diffractometer (XRD) using CuKα1 ray. |
| US10276865B2 |
Negative active material for secondary battery, negative electrode and lithium battery each including negative active material, and method of preparing negative active material
Provided is a negative active material for a secondary battery which provides high capacity, high efficiency charging-discharging characteristics. The negative active material includes: a silicon single phase; and a silicon-metal alloy phase interfaced with the silicon single phase and surrounding the silicon single phase, wherein an X-ray diffraction spectrum of the negative active material has first and second peaks that are originated from the silicon-metal alloy phase, and the first peak is located at 49.1+/−0.5 degrees (°) and the second peak is located at 38.0+/−0.5 degrees (°), and a diffraction intensity of the first peak is 2 or less times that of to the second peak. |
| US10276863B2 |
Non-stoichiometric titanium compound-carbon composite, method for producing same, negative electrode active material and lithium ion secondary battery
A composite material including a carbon-containing material and a non-stoichiometric titanium compound shown by a chemical formula of Li4+xTi5−xO12, where x is in a range of 0 |
| US10276859B2 |
Conductive polymer and Si nanoparticles composite secondary particles and structured current collectors for high loading lithium ion negative electrode application
Embodiments of the present invention disclose a composition of matter comprising a silicon (Si) nanoparticle coated with a conductive polymer. Another embodiment discloses a method for preparing a composition of matter comprising a plurality of silicon (Si) nanoparticles coated with a conductive polymer comprising providing Si nanoparticles, providing a conductive polymer, preparing a Si nanoparticle, conductive polymer, and solvent slurry, spraying the slurry into a liquid medium that is a non-solvent of the conductive polymer, and precipitating the silicon (Si) nanoparticles coated with the conductive polymer. Another embodiment discloses an anode comprising a current collector, and a composition of matter comprising a silicon (Si) nanoparticle coated with a conductive polymer. |
| US10276854B2 |
Rechargeable battery comprising sub-terminal and rivet-terminal structure
A rechargeable battery includes an electrode assembly, a case accommodating the electrode assembly, a cap plate coupled to the case, an electrode terminal within a terminal hole of the cap plate, and a lead tab connecting the electrode assembly to the electrode terminal, wherein the electrode terminal includes a plate terminal located outside of the cap plate and having a through-hole corresponding to the terminal hole, a sub-terminal extending into the through-hole and coupled to the plate terminal, and a rivet terminal penetrating the terminal hole, the rivet terminal being connected to the lead tab and being compression-molded to the sub-terminal. |
| US10276849B2 |
Separator including polyolefin microporous membrane and inorganic porous layer, and nonaqueous electrolyte battery using the same
A separator for nonaqueous electrolyte batteries having multilayer porous membrane, having a polyolefin microporous membrane and a porous layer having an inorganic filler, disposed on at least one side of the polyolefin microporous membrane, wherein, in pores with an area of 0.01 μm2 or more in a cross section of the porous layer, the pores having an angle θ formed between a major axis of each pore and an axis in parallel with an interface between the microporous membrane and the porous layer in a range of 60°≤θ≤120° occupying a proportion of 30% or more therein. |
| US10276847B2 |
Rechargable battery pack
A rechargeable battery pack including unit cells each including a rechargeable battery, barriers coupled to each other at an outer circumference of the unit cells and each located between respective ones of the unit cells, and a pack housing that accommodates the unit cells and the barriers, and that is coupled to the barriers by tight-fitting. |
| US10276845B2 |
Battery case for mobile device
An improved battery case adapted to removably receive, protect and provide power to a mobile device is provided. The case includes a base configured to house a rechargeable battery, a user detachable back face cover capable of providing aesthetic modularity to the consumer and manufacturing advantages, and a bumper that is constructed to include a rigid inner frame or skeleton that includes an outwardly extending rib that is molded on either side with an outer softer and more elastic layer that extends over the face of the mobile device. The bumper can be molded as an integral part of the case or be removably attached to the a component of the case. |
| US10276844B2 |
Battery retention system for a power tool
A battery retention system for a power tool having a motor, a drive mechanism coupled to the motor, an output element coupled to the drive mechanism, and latch-receiving recesses for receiving battery pack latches. The battery retention system includes a battery pack for powering the motor. The battery pack is removably coupled to the power tool and includes latches and elongated rails. The system includes a cavity in the power tool for receiving the battery pack in a direction of insertion. Spring arms extend generally in the direction of insertion and each have a projection extending into the cavity for coupling the battery pack to the power tool. The spring arms are configured to deform in engagement with the respective rails of the battery pack when the battery pack is inserted into the cavity. The rails are elongated generally in the direction of insertion. |
| US10276841B2 |
Module carrier for battery cells and method for producing the module carrier, and battery module, battery pack, battery and battery system
A module carrier (20; 20′; 30; 40; 50; 60; 70; 80; 90; 92; 94) for battery cells (1001, 1002, 1003), characterized by: a first carrier device (2001) and a second carrier device (2002), which is arranged opposite the first carrier device (2001), for carrying the battery cells (1001, 1002, 1003), and a first connecting device (3001) and a second connecting device (3002), which is arranged opposite the first connecting device (3001), in each case for connecting the first carrier device (2001) and the second carrier device (2002). |
| US10276839B2 |
Rechargeable battery
A rechargeable battery includes a battery body and a connector plug. The battery body has a recess, a circuit board and a cell. The circuit board is electrically connected to the battery cell. The connector plug is pivotally connected to the battery body and electrically connected to the circuit board. The connector plug is foldable to be received in the recess. Accordingly, the connector plug is pivotally connected to the battery body and is foldable to be received in the recess, so the battery body can be charged by means of the connector plug connected to an external power supply, thereby improving convenience in using the rechargeable battery. |
| US10276835B2 |
Filling apparatus used in an evaporator system and filling method
A filling apparatus used in an evaporator system and a filling method are provided. The filling apparatus includes: a filling bottle, a magnetic cover plate, an evaporation material trough and a magnetic induction drive unit, wherein the magnetic cover plate is provided at an opening of the filling bottle, in operation the opening of the filling bottle is provided to orientate the evaporation material trough, the magnetic induction drive unit is disposed outside of the opening, and configured to be capable of driving the magnetic cover plate to open and close. |
| US10276834B2 |
Organic light-emitting device
An organic light-emitting device (OLED) which exhibits superior light extraction efficiency due to an extraction structure for dipole light generated from an organic light-emitting layer. The OLED includes a first glass substrate, a first electrode disposed on the first glass substrate, an organic light-emitting layer disposed on the first electrode, a second electrode disposed on the organic light-emitting layer, and a second glass substrate disposed on the second electrode. The second electrode has a composite electrode structure including a first transparent electrode layer and a second transparent electrode layer stacked on each other, the refractive index of the second transparent electrode layer being higher than the refractive index of the first transparent electrode layer. |
| US10276830B2 |
Organic electroluminescent device and method for producing same
Am organic electroluminescent device (100A) in an embodiment includes an element substrate including a plurality of organic electroluminescent elements (3) supported by a substrate; and a thin film encapsulation structure (10E) formed on the plurality of organic electroluminescent elements. The thin film encapsulation structure (10E) includes at least one complex stack body (10S) including a first inorganic barrier layer (12E), an organic barrier layer (14E) in contact with a top surface of the first inorganic barrier layer (12E) and including a plurality of solid portions discretely distributed, and a second inorganic barrier layer (16E) in contact with the top surface of the first inorganic barrier layer and a top surface of each of the plurality of solid portions of the organic barrier layer. The plurality of solid portions include a plurality of solid portions discretely provided and each having a recessed surface. |
| US10276826B2 |
Light-emitting device, electronic device, and lighting device
A lightweight flexible light-emitting device that is less likely to be broken is provided. The light-emitting device includes a first flexible substrate, a second flexible substrate, an element layer, a first bonding layer, and a second bonding layer. The element layer includes a light-emitting element. The element layer is provided between the first flexible substrate and the second flexible substrate. The first bonding layer is provided between the first flexible substrate and the element layer. The second bonding layer is provided between the second flexible substrate and the element layer. The first and second bonding layers are in contact with each other on the outer side of an end portion of the element layer. The first and second flexible substrates are in contact with each other on the outer side of the end portions of the element layer, the first bonding layer, and the second bonding layer. |
| US10276825B2 |
Electroluminescent display and encapsulation method thereof
The present disclosure discloses an electroluminescent display and the encapsulation method thereof. The electroluminescent display comprises: a substrate having encapsulation units provided on a side surface of the substrate; a cover plate covering the substrate, wherein the cover plate together with the encapsulation units defines a first chamber and a second chamber, the second chamber surrounds the first chamber; an electronic device provided on the substrate and located within the first chamber, wherein the first chamber is filled with inert gas and the second chamber is filled with a hydrophobic liquid. The electroluminescent display according to an embodiment of the present disclosure can prevent water vapor and oxygen from entering the electronic device. The entire system has a good sealing performance, such that a service life of the electronic device can be greatly extended. |
| US10276820B2 |
Quantum dots light emitting diode and fabricating method thereof, display panel and display apparatus
The present application discloses a method of fabricating a quantum dots light emitting diode, the method including co-depositing an electron transport material and an inorganic perovskite material on a base substrate to form a composite layer having the electron transport material and the inorganic perovskite material. |
| US10276819B2 |
Organic electroluminescent element, manufacturing method for same, and light emission method including a thermally activated delayed fluorescent material
The organic EL element (10) at least includes, between a first electrode (2) and a second electrode (4), at least one layer of an exciton generating layer (33) which contains at least one type of TADF material as a host material and at least one layer of a fluorescent emission layer (34) which contains at least one type of fluorescent emission material. |
| US10276817B2 |
Stable organic photosensitive devices with exciton-blocking charge carrier filters utilizing high glass transition temperature materials
Disclosed herein are stable organic photosensitive devices including at least one exciton-blocking charge carrier filter. The filters comprise a mixture of at least one wide energy gap material having a sufficiently high glass transition temperature, e.g., higher than the temperature or temperature range at which the device typically operates, higher than a highest operating temperature of the device, higher than a threshold temperature value, etc. and at least one electron or hole conducting material. As described herein, the novel filters simultaneously block excitons and conduct the desired charge carrier (electrons or holes). |
| US10276814B2 |
Display apparatus and electronic apparatus
Disclosed herein is a display apparatus, including: a foldable substrate; a pixel array section including a plurality of pixels disposed on the substrate and each including an electro-optical device; the foldable substrate being folded at a substrate end portion at least on one side thereof around the pixel array section; a peripheral circuit section disposed on the substrate end portion and adapted to drive the pixels of the pixel array section; and a pad section provided on the substrate end portion on which the peripheral circuit section is provided and adapted to electrically connect the peripheral circuit section to the outside of the substrate. |
| US10276811B2 |
Mechanically flexible and durable substrates and method of making
A flexible substrate are disclosed comprising an amorphous inorganic composition, wherein the substrate has a thickness of less than about 250 μm and has at least one of: a) a brittleness ratio less than about 9.5 (μm)−1/2, or b) a fracture toughness of at least about 0.75 MPa·(m)1/2. Electronic devices comprising such flexible devices are also disclosed. Also disclosed is a method for making a flexible substrate comprising selecting an amorphous inorganic material capable of forming a substrate having a thickness of less than about 250 μm and having at least one of: a) a brittleness ratio of less than about 9.5 (μm)−1/2, or b) a fracture toughness of at least about 0.75 MPa·(m)1/2; and then forming a substrate from the selected inorganic material. |
| US10276808B2 |
Organic electroluminescent compound and organic electroluminescent device comprising the same
The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. The organic electroluminescent compound according to the present disclosure is capable of producing an organic electroluminescent device with reasonably improved color purity and efficiency. |
| US10276801B2 |
Triazine-based compound and light emitting device
Provided is a triazine-based compound represented by following formula (I). |
| US10276799B2 |
White-light hyperbranched conjugated polymer, method for preparing the same and it's use
This application discloses a white-light hyperbranched conjugated polymer, a method for preparing the same and its use. The polymer uses a red phosphorescent Ir(III) complex as a core and polyfluorene derivative blue fluorescent materials as a framework which either contains or does not contain carbazole derivatives, and the white light hyperbranched polymers realize white-light emission by adjusting the content of the red phosphorescent Ir(III) complex connected using the complementation of blue and red color. The electroluminescent spectrum of the conjugated polymer in the present application covers the whole visible light emission area and is close to the pure white light emission, by which the conjugated polymer could be used as a material used in light-emitting layer to prepare the organic electroluminescent devices. |
| US10276797B2 |
Vapor deposition device, vapor deposition method, and method for manufacturing organic electroluminescence element
The present invention provides a vapor deposition device including a novel alignment mechanism applicable to a large substrate, a vapor deposition method, and a method for manufacturing an organic electroluminescence element. The vapor deposition device of the present invention is a vapor deposition device for performing vapor deposition while transporting a substrate in a first direction, and includes: a mask; a substrate tray including a substrate-holding portion and a guide portion protruding from the substrate-holding portion to the mask side and disposed along the first direction; at least one distance meter disposed on a first end which is one end of the mask or the guide portion; and at least one driver coupled with a second end which is the other end of the mask. The at least one distance meter is configured to measure a distance between the at least one distance meter and the guide portion or the first end when the guide portion faces the first end. The at least one driver is capable of driving the mask in a second direction perpendicular to the first direction based on the measured value of the at least one distance meter. |
| US10276793B2 |
Variable resistance memory devices and methods of manufacturing the same
A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane. |
| US10276792B2 |
Low power barrier modulated cell for storage class memory
Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array. |
| US10276787B2 |
Integrated anisotropic magnetoresistive device
An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads. |
| US10276783B2 |
Gate voltage controlled perpendicular spin orbit torque MRAM memory cell
A four terminal magnetoresistive memory cell comprises a magnetic tunnel junction stack, a ferroelectric layer and a non-ferromagnetic spin polarization layer between the magnetic tunnel junction stack and the ferroelectric layer. The magnetic tunnel junction includes a first layer with fixed direction of magnetization, a free layer capable of changing direction of magnetization and an insulation layer between the first layer and the free layer. The non-ferromagnetic spin polarization layer is configured to generate perpendicular spin polarization in response to electrical current through the non-ferromagnetic spin polarization layer and a voltage received at the ferroelectric layer. The perpendicular spin polarization applies a torque on the free layer to change direction of magnetization of the free layer. |
| US10276781B2 |
Magnetoresistive structures, semiconductor devices, and related systems
Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region. |
| US10276780B2 |
Semiconductor device, semiconductor device control method and optical switch
Semiconductor devices and semiconductor device control methods are described. A semiconductor device comprises a first electrode; a cell arranged on the first electrode and including a magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; and a heating element to form a thermal gradient in the first electrode. |
| US10276779B2 |
Top electrode cap structure for embedded memory
The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer. |
| US10276778B2 |
Crystal pattern forming method, piezoelectric film producing method, piezoelectric element producing method, and liquid discharging head producing method
A crystal pattern forming method includes: an electromagnetic wave absorbing layer forming process for forming an electromagnetic wave absorbing layer on one of surfaces of a substrate; an amorphous film forming process for forming an amorphous film on the electromagnetic wave absorbing layer; a mask forming process for forming an electromagnetic wave blocking mask for blocking an electromagnetic wave on the other one of the surfaces of the substrate; and a crystallizing process for causing the substrate to be irradiated with the electromagnetic wave from the other one of the surfaces of the substrate through the electromagnetic wave blocking mask to crystallize a given region in the amorphous film. In the mask forming process, a recessed structure is formed on the other one of the surfaces of the substrate, by selectively removing the other one of the surfaces of the substrate to form a recessed portion. |
| US10276773B2 |
Wearable device, system and method for control of the wearable device
The invention concerns an electronic wearable device (1) adapted to form a loop around a body part of a user and comprising an elongated member (10) being a part of the loop and a control unit (20). The elongated member (10) comprises an electroactive polymer (11), whereby the shape of the electroactive polymer is adapted to be changed by regulating a voltage applied to the electroactive polymer. The invention also concerns an electronic wireless communication system comprising the electronic wearable device and a mobile electronic communication device for wireless communication with the electronic wearable device. |
| US10276766B2 |
Light-emitting device
The light-emitting device of the present invention includes: a support; a plurality of light-emitting elements arranged in a row on the support; and a conductor trace portion configured from a plurality of conductor traces which extend on the support from one end portion of the row to the other end portion of the row which are each electrically connected to each of the plurality of light-emitting elements. Each of the plurality of conductor traces is configured such that the trace width in the direction of extension in a region under one light-emitting element to which the conductor trace is electrically connected is greater than the trace width in a region extending in the direction of extension side by side with a conductor trace connected to a light-emitting element disposed closer to the one end portion than the one light-emitting element is. |
| US10276762B2 |
Optoelectronic component
An optoelectronic component includes a carrier, and a light source arranged on a surface of the carrier, said light source including at least one luminous surface formed by at least one light-emitting diode, wherein a transparent converter-free spacer is arranged on the luminous surface such that a distance is formed between the luminous surface and a spacer surface of the spacer facing away from the luminous surface, and wherein the light source is potted by a potting compound such that the spacer surface is formed extending flush with a potting compound surface facing away from the surface of the carrier and a surface formed by a spacer surface and the potting compound surface is plane. |
| US10276761B2 |
Photoelectric device package
A photoelectric device package including a substrate, a first circuit layer, a carrier structure, a second circuit layer, at least one photoelectric device, and a first encapsulation layer is provided. The first circuit layer is disposed on the substrate. The carrier structure is disposed on the substrate and covers the first circuit layer. The carrier structure includes a first dielectric layer, a second dielectric layer, and an elastic layer disposed between the first dielectric layer and the second dielectric layer. The Young's modulus of the elastic layer is less than the Young's modulus of the first dielectric layer and the second dielectric layer. The second circuit layer is disposed on the carrier structure. The photoelectric device is disposed on the carrier structure and is electrically connected to the first and second circuit layers. The first encapsulation layer is disposed on the carrier structure and encapsulates the photoelectric device. |
| US10276758B2 |
Singulaton of light emitting devices before and after application of phosphor
A two-stage singulation process is used in the fabrication of phosphor coated light emitting elements. Prior to the application of the phosphor coating, the individual light emitting elements are singulated using a laser dicing process (130); after application of the phosphor coating (150), the phosphor coated light emitting elements are singulated using a mechanical dicing process (180). Before laser dicing of the light emitting elements, the wafer is positioned on a piece of dicing- or die-attach-tape held by a frame; after laser dicing, the tape is stretched (140) to provide space between the individual light emitting elements that allows for the wider kerf width of the subsequent mechanical dicing (180) after application of the phosphor coating (150). |
| US10276756B2 |
LED display panel
The present disclosure discloses an LED display panel including at least a thin film transistor array layer, a quantum dot light emitting layer, and an LED array layer arranged between the thin film transistor array layer and the quantum dot light emitting layer, when the LED array layer emits excitation light, the excited quantum dot emits light to emit at least two colors of light. The present disclosure can reduce the production cost and greatly improve the production yield, and can effectively reduce the energy consumption of the display panel and improve the service life. |
| US10276755B2 |
Fluidic assembly of emissive displays
Fluidic assembly methods are presented for the fabrication of emissive displays. An emissive substrate is provided with a top surface, and a first plurality of wells formed in the top surface. Each well has a bottom surface with a first electrical interface. Also provided is a liquid suspension of emissive elements. The suspension is flowed across the emissive substrate and the emissive elements are captured in the wells. As a result of annealing the emissive substrate, electrical connections are made between each emissive element to the first electrical interface of a corresponding well. A eutectic solder interface metal on either the substrate or the emissive element is desirable as well as the use of a fluxing agent prior to thermal anneal. The emissive element may be a surface mount light emitting diode (SMLED) with two electrical contacts on its top surface (adjacent to the bottom surfaces of the wells). |
| US10276754B2 |
Method for the fluidic assembly of emissive displays
Fluidic assembly methods are presented for the fabrication of emissive displays. An emissive substrate is provided with a top surface, and a first plurality of wells formed in the top surface. Each well has a bottom surface with a first electrical interface. Also provided is a liquid suspension of emissive elements. The suspension is flowed across the emissive substrate and the emissive elements are captured in the wells. As a result of annealing the emissive substrate, electrical connections are made between each emissive element to the first electrical interface of a corresponding well. A eutectic solder interface metal on either the substrate or the emissive element is desirable as well as the use of a fluxing agent prior to thermal anneal. The emissive element may be a surface mount light emitting diode (SMLED) with two electrical contacts on its top surface (adjacent to the bottom surfaces of the wells). |
| US10276753B2 |
LED flip-chip package substrate and LED package structure
A LED flip-chip package substrate includes a ceramic base (e.g., aluminum nitride base), a conductive wire layer disposed on the ceramic base and having pads in pairs, an insulating protective layer (e.g., low-temperature glass glaze layer) disposed on a same side of the ceramic base as the conductive wire layer and exposing the pads, and a metallic reflective layer (e.g., aluminum layer) disposed on a side of the insulating protective layer facing away from the ceramic base and exposing the pads. Moreover, a LED package structure adopting the LED flip-chip package substrate and other LED package structures with similar material layers such as a chip-level packaged LED package structure are provided. By comprehensively utilizing advantages of various materials, the LED flip-chip package substrate with high heat conductivity, high reflectivity, high stability and superior insulation and the LED package structure with high reliability and even high light extraction efficiency are obtained. |
| US10276751B2 |
Light emitting element
A light emitting element has semiconductor layers and first and second electrodes disposed. In plan view, the first electrode has a first connecting portion, a first extending portion, and two second extending portions, and the second electrode has a second connecting portion and two third extending portions. The first extending portion of the first electrode extends linearly from the first connecting portion toward the second connecting portion, and the two second extending portions extend parallel to the first extending portion on two sides of the first extending portion. The second extending portions each has two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the second extending portion. With respect to an extending direction of the first extending portion, each of the second extending portions extends beyond a position of the second connecting portion. |
| US10276750B2 |
Bonding electrode structure of flip-chip led chip and fabrication method
A bonding electrode structure of a flip-chip LED chip includes: a substrate; a light-emitting epitaxial layer over the substrate; a bonding electrode over the light-emitting epitaxial layer, wherein the bonding electrode structure includes a metal laminated layer having a bottom layer and an upper surface layer from bottom up. The bottom layer structure is oxidable metal and the side wall forms an oxide layer. The upper surface layer is non-oxidable metal. The bonding electrode structure has a main contact portion, and a grid-shape portion surrounding the main contact portion in a horizontal direction. The problems during packaging and soldering of the flip-chip LED chip structure, such as short circuit or electric leakage, can thus be solved. |
| US10276748B2 |
Radiation-emitting semiconductor chip, method for producing a plurality of radiation-emitting semiconductor chips and optoelectronic component having a radiation-emitting semiconductor chip
Disclosed is a radiation-emitting semi-conductor chip (1) comprising an epitaxial semi-conductor layer sequence (3) which emits electromagnetic radiation in operation. The epitaxial semi-conductor layer sequence (3) is applied on a a transparent substrate (4), wherein the substrate (4) has a first main surface (8) facing the semi-conductor layer sequence (3), a second main surface (9) facing away from the semi-conductor layer sequence (3) and a first lateral flank (10) arranged between the first main surface (8) and the second main surface (9), and the lateral flank (10) has a decoupling structure which is formed in a targeted manner from separating tracks. Also disclosed is a method for producing the semi-conductor chip, and a component comprising such a semi-conductor chip. |
| US10276744B2 |
Light-emitting diode epitaxial wafer and method for preparing the same
A light-emitting diode epitaxial wafer, including: a substrate; and a buffer layer, an undoped GaN layer, an n-type GaN contact layer, a multi-quantum well layer, and a p-type GaN contact layer, which are sequentially laminated on the substrate in that order. The multi-quantum well layer includes GaN barrier layers and at least one InxGa1-xN well layer, where 0 |
| US10276742B2 |
Assembly and mounting of solar cells on space vehicles or satellites
Solar cell array assemblies or modules and methods of making and using such solar cell array assemblies or modules, having discrete predefined pressure sensitive adhesive (PSA) regions thereon. In certain embodiments, the solar cell array modules may be conveniently mounted on the surface of a panel of a space vehicle or satellite with the discrete predefined PSA regions. |
| US10276741B2 |
Method for eliminating metal composites from polycrystalline silicon cell piece
A method for eliminating metal composites from a polycrystalline silicon cell piece, comprising the steps of: injecting current into the polycrystalline silicon cell piece under a certain temperature by means of an electric injection method, thereby eliminating the metal composites from the interior of the polycrystalline silicon cell piece; the present invention discloses a simple process, a short processing-time, a low manufacturing cost, and can easily be scaled for manufacture. |
| US10276739B2 |
High voltage photovoltaics integrated with light emitting diode
An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials. |
| US10276738B2 |
Photovoltaic cell, including a crystalline silicon oxide passivation thin film, and method for producing same
A heterojunction photovoltaic cell includes at least one crystalline silicon oxide film directly placed onto one of the front or rear faces of a crystalline silicon substrate, between said substrate and a layer of amorphous or microcrystalline silicon. The thin film is intended to enable the passivation of said face of the substrate. The thin film is more particularly obtained by radically oxidizing a surface portion of the substrate, before depositing the layer of amorphous silicon. Moreover, a thin layer of intrinsic or microdoped amorphous silicon can be placed between said think film and the layer of amorphous or microcrystalline silicon. |
| US10276735B2 |
Semiconductor nanocrystals
A semiconductor nanocrystal include a first I-III-VI semiconductor material and have a luminescence quantum yield of at least 10%, at least 20%, or at least 30%. The nanocrystal can be substantially free of toxic elements. Populations of the nanocrystals can have an emission FWHM of no greater than 0.35 eV. |
| US10276732B2 |
Solar cell element and method of manufacturing solar cell element
A solar cell element includes a semiconductor substrate, a passivation layer and a protective layer. The semiconductor substrate includes a p-type semiconductor region on one surface side thereof. The passivation layer is located on the p-type semiconductor region and contains aluminum oxide. The protective layer is located on the passivation layer and includes polysiloxane layer which contains an alkyl group. |
| US10276730B2 |
Stacked Schottky diode
A stacked Schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack. A second connection contact layer is connected to the top side of the stack, wherein the second connection contact layer forms a Schottky contact. The second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges. The first semiconductor layer, formed as an n+ layer, is placed on the bottom side of the stack and the first semiconductor layer. A second semiconductor layer, formed as an n− layer, is placed on the first semiconductor layer. A third semiconductor layer formed as a p− layer is placed on the second semiconductor layer. |
| US10276728B2 |
Semiconductor device including non-volatile memory cells
A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween. |
| US10276726B2 |
Non-volatile memory cell and non-volatile memory
An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate. |
| US10276724B2 |
Semiconductor device
A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel. |
| US10276721B2 |
Liquid crystal display
A liquid crystal display includes a first gate line, a first data line, and a first pixel. The first pixel includes: a first subpixel including a first thin film transistor connected to the first gate line and data line, and a first liquid crystal capacitor, wherein a first terminal of the first liquid crystal capacitor is electrically connected to the first thin film transistor and a second terminal of the first liquid crystal capacitor is configured to receive a common voltage; and a second subpixel including a second thin film transistor connected to the first gate line and data line, a second liquid crystal capacitor, wherein a first terminal of the second liquid crystal capacitor is configured to receive the common voltage, and a thin film transistor resistor electrically connected between the second thin film transistor and a second terminal of the second liquid crystal capacitor. |
| US10276719B1 |
Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer. |
| US10276717B2 |
Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance. |
| US10276713B2 |
Semiconductor component and method of manufacture
In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench. |
| US10276711B2 |
Semiconductor device and method of manufacturing the same
Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer. |
| US10276710B1 |
High voltage transistor and fabrication method thereof
A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer. |
| US10276708B2 |
Reverse-blocking IGBT having a reverse-blocking edge termination structure
A reverse-blocking IGBT (insulated gate bipolar transistor) includes a plurality of IGBT cells disposed in a device region of a semiconductor substrate, a reverse-blocking edge termination structure disposed in a periphery region of the semiconductor substrate which surrounds the device region, one or more trenches formed in the periphery region between the reverse-blocking edge termination structure and an edge face of the semiconductor substrate, a p-type dopant source at least partly filling the one or more trenches, and a continuous p-type doped region disposed in the periphery region and formed from p-type dopants out-diffused from the p-type dopant source. The continuous p-type doped region extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate. |
| US10276706B2 |
Gated diode in a press-fit housing and an alternator assembly having a gated diode arranged in a load path
A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire. |
| US10276705B2 |
Group III—nitride double-heterojunction field effect transistor
A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer. |
| US10276704B1 |
High electron mobility transistor with negative capacitor gate
A high electron mobility transistor includes a semiconductor structure having a channel layer and a cap layer forming a two dimensional electron gas (2-DEG) channel, and a source, a drain, and a gate electrodes. The gate is arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel is modulated in response to applying voltage to the gate. The cap layer includes III-N material. The gate has a layered structure including a bottom metal layer arranged on cap layer, a ferroelectric oxide (FEO) layer arranged on bottom metal layer, and a top metal layer arranged on the FEO layer. Thickness of FEO layer is less than tcap/(2αεcap), wherein α is a parameter of material of FEO layer, tcap is thickness of cap layer, and εcap is electric permittivity of cap layer. |
| US10276701B2 |
Compound semiconductor device
A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction. |
| US10276695B2 |
Self-aligned inner-spacer replacement process using implantation
A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region. |
| US10276693B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin. |
| US10276687B1 |
Formation of self-aligned bottom spacer for vertical transistors
A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer. |
| US10276685B2 |
Heterojunction tunnel field effect transistor fabrication using limited lithography steps
A structure and method for fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps is disclosed. The fabrication of a second conductivity type source/drain region may utilize a single lithography step to form a first-type source/drain region, and a metal contact thereon, adjacent to a gate stack having a first conductivity type source/drain region on an opposite side. |
| US10276682B2 |
High electron mobility transistor
A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature. |
| US10276681B2 |
Double gate transistor device and method of operating
In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region. |
| US10276678B2 |
Semiconductor device and fabrication method thereof
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer. |
| US10276673B2 |
Semiconductor die having stacking structure of silicon-metallic conductive layer-silicon
The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer. |
| US10276672B2 |
Vertical semiconductor device having a trench gate a base contact region
A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode. |
| US10276671B2 |
Semiconductor device, method for manufacturing semiconductor device, and electronic device
A semiconductor device includes a compound semiconductor layer, a gate electrode, and first and second insulating layers. The first insulating layer covers the gate electrode on the compound semiconductor layer and has a cavity that surrounds the gate electrode. The second insulating layer is provided on the first insulating layer and has an opening at a position corresponding to the cavity. A part of the second insulating layer, which is provided on the first insulating layer that covers the gate electrode, corresponding to the cavity is removed via the opening, so that the generation of parasitic capacitance due to the second insulating layer is suppressed. |
| US10276666B2 |
Semiconductor device
On a front surface of an n+-type SiC substrate becoming a drain region, an n−-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n−-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented. |
| US10276664B2 |
Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current
A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined. |
| US10276661B2 |
Semiconductor device
A semiconductor device includes: a channel-forming region of a first conductivity type; a first main electrode region of a second conductivity type disposed in a portion of an upper part of the channel-forming region; a drift region of the second conductivity type that is disposed in an upper part of the channel-forming region apart from the first main electrode region; a second main electrode region of the second conductivity type that is disposed in a part of an upper part of the drift region; and a stopper region of the second conductivity type that is disposed at an end region of the drift region apart from the first main electrode region and has a higher concentration than the drift region. The stopper region restricts extension of a depletion layer developing at the boundary of the pn junction between the channel-forming region and the drift region. |
| US10276660B2 |
Nanowire field effect transistor having a metal gate surrounding semiconductor nanowire
A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material. |
| US10276659B2 |
Air gap adjacent a bottom source/drain region of vertical transistor device
A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap. |
| US10276658B2 |
FinFET devices
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures. |
| US10276656B2 |
Method of manufacturing semiconductor devices by using epitaxy and semiconductor devices with a lateral structure
Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed. |
| US10276653B2 |
Semiconductor device and method of manufacturing semiconductor device
In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered. |
| US10276649B2 |
Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers
A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion. |
| US10276647B2 |
Display device
A display device according to an embodiment of the present invention includes: a display panel including a display region, a backside region, and a curvature region, wherein the display panel comprises: an insulating base material disposed on the display region, the curvature region, and the backside region; a wiring layer that is disposed on an outer surface side of the insulating base material, and comprises an insulating layer and a wiring; a display element that is provided on an outer surface side of the wiring layer in the display region, and is electrically connected to the wiring; and a first protection sheet that is provided on an inner surface side of the insulating base material in the display region, and includes a plurality of projection parts that protrude toward a side of the curvature region from a side of the display region. |
| US10276640B2 |
Display device
A display device includes a substrate, an encapsulation unit opposite to the substrate, a display unit disposed between the substrate and the encapsulation unit and including a pixel, a camera unit disposed on one side of the substrate and including at least one camera module, and a mirror member disposed on one side of the encapsulation unit. |
| US10276634B2 |
Semiconductor memory structure with magnetic tunnel junction (MTJ) cell
A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion. |
| US10276632B2 |
Display device using semiconductor light-emitting diodes, and manufacturing method therefor
The present invention relates to a display device and, particularly, to a display device using semiconductor light-emitting diodes. In the display device according to the present invention, at least one of the semiconductor light-emitting diodes comprises: a first conductive electrode and a second conductive electrode; a first conductive semiconductor layer having the first conductive electrode arranged thereon; a second conductive semiconductor layer overlapping with the first conductive semiconductor layer in a vertical direction, and having the second conductive electrode arranged thereon; and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein a connecting unit electrically connected to the first conductive electrode is formed on one surface of the first conductive semiconductor layer, and the connecting unit is arranged so as to lean to one side on the basis of the second conductive electrode along the horizontal direction. |
| US10276627B2 |
High-performance radiation detectors and methods of fabricating thereof
A method of fabricating a solid state radiation detector method includes mechanically lapping and polishing the first and the second surfaces of a semiconductor wafer using a plurality of lapping and polishing steps. The method also includes growing passivation oxide layers by use of oxygen plasma on the top of the polished first and second surfaces in order to passivate the semiconductor wafer. Anode contacts are deposited and patterned on top of the first passivation oxide layer, which is on top of the first surface. Cathode contacts, which are either monolithic or patterned, are deposited on top of the second passivation oxide layer, which is on the second surface. Aluminum nitride encapsulation layer can be deposited over the anode contacts and patterned to encapsulate the first passivation oxide layer, while physically exposing a center portion of each anode contact to electrically connect the anode contacts. |
| US10276619B2 |
Semiconductor device structure with a conductive feature passing through a passivation layer
A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die. |
| US10276617B2 |
Protection ring for image sensors
Some embodiments relate to a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the pixel sensor array. The protection ring includes a first ring neighboring the pixel sensor array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another. |
| US10276616B2 |
Image sensor device
An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first light-sensing region and a second light-sensing region adjacent to the first light-sensing region. The image sensor device includes an isolation structure in the semiconductor substrate and surrounding the first light-sensing region and the second light-sensing region. The image sensor device includes a reflective grid over the isolation structure and surrounding the first light-sensing region and the second light-sensing region. The image sensor device includes a first color filter over the first light-sensing region and extending into a first trench of the reflective grid. The image sensor device includes a second color filter over the second light-sensing region and extending into the first trench to be in direct contact with the first color filter in the first trench. |
| US10276615B2 |
Solid-state imaging device, method of manufacturing the same, and electronic apparatus
The present technology relates to a solid-state imaging device that can improve the sensitivity of imaging pixels while maintaining AF properties of a focus detecting pixel. The present technology also relates to a method of manufacturing the solid-state imaging device, and an electronic apparatus.The solid-state imaging device includes: a pixel array unit including pixels; first microlenses formed in the respective pixels; a film formed to cover the first microlenses of the respective pixels; and a second microlens formed on the film of the focus detecting pixel among the pixels. The present technology can be applied to CMOS image sensors, for example. |
| US10276612B2 |
Photoelectric conversion apparatus and image pickup system
A photoelectric conversion apparatus including a light-receiving element, including: a plurality of photoelectric conversion portions; a separating portion located between the plurality of photoelectric conversion portions; and a light guide portion surrounded by an insulation film including at least one insulation layer and provided so as to extend over the plurality of photoelectric conversion portions, and the light guide portion includes: a high refractive index part having a refractive index higher than a refractive index of the insulation layer; and a low refractive index part having a refractive index higher than the refractive index of the insulation layer and lower than the refractive index of the high refractive index part, and the high refractive index part is located on each of the plurality of photoelectric conversion portions and the low refractive index part is located on the separating portion. |
| US10276610B2 |
Semiconductor photomultiplier
The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line. |
| US10276607B2 |
Display panel, manufacturing method thereof and display device
The disclosure discloses a display panel, a manufacturing method thereof and a display device. The display panel includes a backing substrate, a first active layer arranged over the backing substrate, and a second active layer arranged on a side of the first active layer away from the backing substrate. The first active layer and the second active layer each comprise a conductor region, and perpendicular projections of the conductor regions of the first and second active layers on the backing substrate have an overlapping region. A part of the conductor region of the first active layer corresponding to the overlapping region forms as a first electrode, a part of the conductor region of the second active layer corresponding to the overlapping region forms a second electrode, and the first electrode and the second electrode form two electrodes of a capacitor. |
| US10276606B2 |
Array substrate and display device and method for making the array substrate
A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT. |
| US10276599B2 |
Display panel and fan-out circuit structure thereof
A fan-out circuit structure, a display panel, and a display device are provided. The fan-out circuit structure includes: a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer includes a first metal sub-layer and a second metal sub-layer; the third metal layer includes a third metal sub-layer and a fourth metal sub-layer; the first metal sub-layer is connected with a first end of the second metal layer through the third metal sub-layer; and a second end of the second metal layer is connected with the second metal sub-layer through the fourth metal sub-layer. |
| US10276596B2 |
Selective polysilicon doping for gate induced drain leakage improvement
Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed. |
| US10276594B2 |
Display device and electronic device
A novel display device is provided. The display device includes a pixel portion and a driver circuit for driving the pixel portion. The driver circuit includes a first transistor having a dual-gate structure. The pixel portion includes a second transistor having a single-gate structure and a pixel electrode electrically connected to the second transistor. The first transistor and the second transistor each include a first metal oxide film functioning as a channel. The metal oxide films each include a first region and a second region. The first region contains In or Zn, and oxygen. The second region contains In or an element M, and oxygen. The first region and the second region are dispersed or distributed in a mosaic pattern. |
| US10276589B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings. |
| US10276587B2 |
NVM memory HKMG integration technology
The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region. |
| US10276586B2 |
Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween. |
| US10276585B2 |
Semiconductor memory device
A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period. |
| US10276583B2 |
Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof
Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer. |
| US10276580B2 |
Methods, structures and devices for intra-connection structures
Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure. |
| US10276571B2 |
Circuit design system and semiconductor circuit designed by using the system
A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design. |
| US10276565B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness. |
| US10276562B2 |
Semiconductor device with multiple threshold voltage and method of fabricating the same
According to an exemplary embodiment, a chip is provided. The chip includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer. |
| US10276561B2 |
Semiconductor structure with resistor layer and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous. |
| US10276560B2 |
Passive device structure and methods of making thereof
Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer. |
| US10276555B2 |
Method and system for providing a magnetic cell usable in spin transfer torque applications and including a switchable shunting layer
A magnetic cell and method for providing the magnetic cell are described. A magnetic cell resides on a substrate and is usable in a magnetic device. The magnetic cell includes a magnetic junction and an ovonic threshold switch (OTS) layer. The magnetic junction has a plurality of sidewalls. The magnetic junction includes a free layer switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction, a nonmagnetic spacer layer and a pinned layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The OTS layer covers at least a portion of the plurality of sidewalls. |
| US10276553B2 |
Chip package structure and manufacturing method thereof
A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors. |
| US10276551B2 |
Semiconductor device package and method of forming semiconductor device package
A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material. |
| US10276548B2 |
Semiconductor packages having dummy connectors and methods of forming same
An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package. |
| US10276547B2 |
Image display module and method of manufacturing the same, and display device
The present disclosure provides an image display module and a method of manufacturing the same, and a display device. The image display module includes a circuit substrate, a light-emitting group and a light-shading structure. The light-emitting group includes a plurality of light-emitting chips for generating a predetermined image. Each light-emitting chip has a light-emitting region, and the light-emitting region has an exposed portion and a shading portion. The light-shading structure includes a light-shading unit and a plurality of through openings passing through the light-shading unit. The exposed portion of the light-emitting region of each light-emitting chip is exposed by the through opening. The shading portion of the light-emitting region of each light-emitting chip is contacted and covered by the light-shading unit. The exposed portions of the light-emitting regions can be arranged regularly in a predetermined shape due to the through openings that are arranged in a regular arrangement. |
| US10276545B1 |
Semiconductor package and manufacturing method thereof
A semiconductor package including a chip stack, at least one conductive wire, a first insulating encapsulant, a second insulating encapsulant, and a redistribution layer is provided, and a manufacturing method thereof is also provided. The chip stack includes semiconductor chips stacked on top of each other. Each semiconductor chip has an active surface that has at least one bonding region, and each bonding region is exposed by the chip stack. The conductive wire is correspondingly disposed on the bonding region. The first insulating encapsulant encapsulates the bonding region and the conductive wire. At least a portion of each conductive wire is exposed from the first insulating encapsulant. The second insulating encapsulant encapsulates the chip stack and the first insulating encapsulant. The first insulating encapsulant is exposed from the second insulating encapsulant. The redistribution layer is disposed on the first and second insulating encapsulant and electrically coupled to the conductive wire. |
| US10276541B2 |
3D package structure and methods of forming same
An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias. |
| US10276538B2 |
Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device
A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board. |
| US10276537B2 |
Integrated fan-out package and manufacturing method thereof
An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant. |
| US10276536B2 |
Structure and formation method of chip package with fan-out structure
Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer. |
| US10276535B2 |
Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress
An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto. |
| US10276532B2 |
Three-dimensional chip stack and method of forming the same
A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region. |
| US10276531B2 |
Semiconductor device having a boundary structure, a package on package structure, and a method of making
The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure. |
| US10276529B2 |
Semiconductor devices including conductive pillars
A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described. |
| US10276522B2 |
Power module
The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance. |
| US10276515B2 |
Mounting component, wiring substrate, electronic device and manufacturing method thereof
Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer. |
| US10276513B2 |
Integrated circuit with backside structures to reduce substrate warp
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit. |
| US10276509B2 |
Integrated fan-out package
A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts. A plurality of conductive terminals are formed on the surfaces of the conductive posts exposed by the openings. |
| US10276507B2 |
Embedded component package structure and method of manufacturing the same
An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die. |
| US10276506B2 |
Integrated fan-out package
A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided. |
| US10276501B2 |
Formation of liner and metal conductor
An integrated circuit device includes a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench having parallel vertical sidewalls and a horizontal bottom. A liner which is an alloy of a first metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric and is created by an anneal and reflow process. The first metal having a first conductivity in a pure form. A second metal layer fills the set of conductive line trenches, the second metal having a second conductivity higher than the first conductivity. |
| US10276499B2 |
Dual power structure with connection pins
In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch. |
| US10276493B2 |
Semiconductor structure and method for fabricating the same
A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole. |
| US10276491B2 |
Interconnect structure and methods thereof
A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed. |
| US10276487B1 |
Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to system board
A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate. |
| US10276484B2 |
Package with metal-insulator-metal capacitor and method of manufacturing the same
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. |
| US10276483B2 |
Coaxial vias
Embodiments herein may relate to a substrate that includes a coaxial via with a signal portion and a ground shield portion. In embodiments, the via may further include a pad that is coupled with the signal portion. The pad and the ground shield portion may not be coplanar with one another. In embodiments, the substrate may have a plurality of vias that may be formed in a staged and/or skipped manner. Other embodiments may be described and/or claimed. |
| US10276481B2 |
Package structure having a plurality of conductive balls having narrow width for the ball waist
A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls. |
| US10276480B1 |
Semiconductor structure
A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The at least one conductive pillar is tapered toward the second circuit layer and disposed on one of the pads. A portion of the second surface of the dielectric layer is exposed from the second surface layer. |
| US10276477B1 |
Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package. |
| US10276475B2 |
Thermal conductive stress relaxation structure
A thermal conductive stress relaxation structure is interposed between a high-temperature substance and a low-temperature substance to conduct heat in a heat-transfer direction from the high-temperature substance to the low-temperature substance. The structure includes an assembly configured such that a thermal conductive material gathers in a non-bonded state having stress relaxation effect. Such an assembly is a rolled-up body configured such that a carbon-based sheet material and a metal-based sheet material are alternately rolled up, for example. This structure has one or more interfaces at which adjacent parts can slide, thereby dividing a deformable region to relax the thermal stress. It has a low rigidity and can thus deform to release the thermal stress. The structure can suppress the thermal stresses and the shape changes that would be generated in the high-temperature substance and the low-temperature substance, and each physical body located there between. |
| US10276471B2 |
Package and method for integration of heterogeneous integrated circuits
In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer. |
| US10276464B2 |
Semiconductor device
Provided is a technique of reducing detachment of a sealing resin in a semiconductor device, thereby achieving an increased improvement in lifetime of the semiconductor device. The semiconductor device includes the following: an insulating substrate; a metal block disposed on the upper surface of the insulating substrate; a semiconductor element mounted on the upper surface of the metal block; a case enclosing the semiconductor element, the metal block, and the insulating substrate; and a sealing resin sealing the semiconductor element and the metal block. The metal block includes at least one groove on a surface of the metal block, the surface being in contact with the sealing resin. The opening of the at least one groove has a width narrower than a width of the bottom surface of the at least one groove. |
| US10276462B2 |
Lid, and optical device package
A lid constitutes, together with a housing, a package that encloses an optical element. The lid includes a frame plate divided into a first member and a second member; and a window plate that closes an opening of the frame plate. The window plate includes a lower surface whose outer peripheral part is bonded to the first member and an upper surface whose outer peripheral part is bonded to the second member. |
| US10276461B2 |
Split probe pad structure and method
A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material. |
| US10276460B2 |
Endpointing detection for chemical mechanical polishing based on spectrometry
A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during polishing, and for each measured spectrum of the sequence of spectra, finding a best matching library spectrum from the plurality of library spectra to generate a sequence of best matching library spectra. Each library spectrum has a stored associated value representing a degree of progress through a polishing process, and the stored associated value for the best matching library spectrum is determined for each best matching library spectrum to generate a sequence of values representing a progression of polishing of the substrate. The sequence of values is compared to a target value, and a polishing endpoint is triggered when the sequence of values reaches the target value. |
| US10276455B2 |
System and method for measurement of semiconductor device fabrication tool implement
Methods, and corresponding systems, are described that include providing a laser-based measurement tool. An implement of a semiconductor fabrication process tool (e.g., susceptor) is delivered to the laser-based measurement tool where a plurality of measurements is performed of a surface of the implement using a blue wavelength radiation. The measurements are of a distance (e.g., angstroms) from a reference plane and provide an indication of the profile of the surface of the susceptor. As the surface profile of the susceptor can affect layers deposited on target substrates using the susceptor, the measurements provide for a disposition of the susceptor. |
| US10276450B2 |
Fabrication technology for metal gate
One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity. |
| US10276443B2 |
Insulating layer next to fin structure and method of removing fin structure
A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process. |
| US10276441B2 |
Protected chip-scale package (CSP) pad structure
A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge. |
| US10276430B2 |
Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method
Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device. |
| US10276429B2 |
Interconnect structure, interconnect layout structure, and manufacturing method thereof
An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line. |
| US10276424B2 |
Method and apparatus for wafer level packaging
Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer. |
| US10276420B2 |
Electrostatic chuck and semiconductor manufacturing apparatus
An electrostatic chuck includes a first electrode provided in a first plane, a second electrode provided in a second plane parallel to the first plane, and an insulator. The second electrode includes a plurality of portions which intersect with an intersection line between a region in which the first electrode is orthogonally projected to the second plane and a third plane vertical to the second plane. The insulator is provided between the first and second electrodes. |
| US10276419B1 |
Pick and place device with interdigitated electrodes for micro scale device
A compliant electrostatic transfer head and array are described. In an embodiment a compliant electrostatic transfer head includes a base substrate, and a plurality of interdigitated spring electrodes that are deflectable together into a cavity toward the base substrate. Each spring electrode includes mesa structure, and the mesa structures of the plurality of interdigitated spring electrodes are aligned. |
| US10276418B2 |
Silicon wafer pre-alignment device and method therefor
A wafer pre-alignment device is disclosed, including a first unit configured to drive a wafer to rotate or move upward or downward, a second unit configured to drive the wafer to translate, and a position detector including a light source, a lens and an image sensor. A light beam from the light source passes through the wafer and the lens and thereby provides information indicating a position of the wafer to the image sensor. The first unit and the second unit are able to adjust the position of the wafer based on the information obtained by the image sensor. A method for pre-aligning a TSV wafer is also disclosed. |
| US10276416B2 |
Industrial robot
An industrial robot may include a first hand and a second hand, each of which is provided with a first hand portion including a substrate-mounting portion and a second hand portion having multiple substrate-mounting portions; a first arm rotatably joined to the first and second hand portion; a second arm rotatably joined to the first and second hand portion; an arm support portion; a column portion for holding said arm support portion; a first hand portion-rotating mechanism; a second hand portion-rotating mechanism; third hand portion-rotating mechanism; a fourth hand portion-rotating mechanism; a first arm-rotating mechanism structured to rotate said first arm with respect to said arm support portion; and a second arm-rotating mechanism structured to rotate said second arm with respect to said arm support portion. |
| US10276414B2 |
Thin wafer shipper
An improved wafer support mechanism in a wafer container useful for carrying a plurality of axially aligned thin mostly circular wafer substrates. The container includes a cassette that has a plurality of adjacently disposed teeth for receiving the substrates, wherein each rib member is continuous from the cassette open top to the cassette open bottom, a removable top cover portion, a removable bottom cover portion, a cushion assembly removably attached to the container top cover, and another cushion assembly removably located in the container bottom cover and held in place by the weight of the wafer cassette. The top cushions are formed of individual segments having an extended lead-in feature at the end of each segment, spring sections in each segment and each segment has a V-shaped cross section to receive the wafer edge. The top and bottom cushions are installed in the top and bottom container covers, respectively, and extend the wafer support to approximately the entire circumference of each wafer. |
| US10276412B2 |
Heating arrangement and method for heating substrates
The invention relates to a vacuum processing system for processing a substrate (2), with an enclosure (1) for carrying the substrate (2) to be treated in a substrate plane (4), whereby the enclosure (1) comprises a first reflecting means (6) and a heating means (5) having a first plane surface (10) and an opposed second plane surface (11), the heating means (5) is configured for irradiating heating energy only via the first surface (10) and/or via the second surface (11), the first reflecting means (6) is configured for reflecting the heating energy irradiated by the heating means (5) onto the substrate plane (4), and the heating means (5) is arranged such that the first surface (10) faces towards the first reflecting means (6) and the second surface (11) faces towards the substrate plane (4). |
| US10276411B2 |
High pressure and high temperature anneal chamber
Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end. |
| US10276407B2 |
Substrate processing apparatus and substrate processing method
The substrate processing apparatus includes a substrate holding unit that holds a substrate horizontally, a substrate rotating unit that rotates the substrate held by the substrate holding unit around a prescribed rotational axis extending along a vertical direction, a processing liquid supply nozzle that moves in a horizontal direction and supplies a processing liquid onto an upper surface of the substrate held by the substrate holding unit, a shielding member that shields an atmosphere between the shielding member and the upper surface of the substrate held by the substrate holding unit from an ambient atmosphere, an inert gas supply unit that supplies an inert gas between the upper surface of the substrate held by the substrate holding unit and the shielding member, and a shielding member rotating unit that rotates the shielding member around the rotational axis. The shielding member includes an annular portion that surrounds the substrate held by the substrate holding unit, and a passage-allowing portion that is provided in the annular portion and allows the processing liquid supply nozzle to pass through the annular portion. The substrate processing apparatus includes a controller that is programmed so as to control the shielding member rotating unit to adjust a position of the passage-allowing portion in the rotational direction such that the processing liquid supply nozzle is to be passed through the annular portion. |
| US10276401B2 |
3D shielding case and methods for forming the same
A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding material and the die, a second metal mesh underlying the die, and a Through-Assembly Via (TAV) in the molding material and forming a ring encircling the die. The TAV is electrically connected to the first metal mesh and the second metal mesh. |
| US10276397B2 |
CVD metal seed layer
The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off. |
| US10276392B2 |
Loading effect reduction through multiple coat-etch processes
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches. |
| US10276390B2 |
Method and apparatus for reducing threshold voltage mismatch in an integrated circuit
A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero. |
| US10276388B2 |
Laser machining device and laser machining method
A laser processing apparatus 1 is an apparatus for forming a modified region R in an object to be processed S by irradiating the object S with laser light L. The laser processing apparatus 1 comprises a laser light source 2 that emits the laser light L, a mount table 8 that supports the object S, and an optical system 11 that converges a ring part surrounding a center part including an optical axis of the laser light L in the laser light L emitted from the laser light source 2 at a predetermined part of the object S supported by the mount table 8. The optical system 11 adjusts a form of at least one of inner and outer edges of the ring part of the laser light L according to a position of the predetermined part in the object S. |
| US10276387B2 |
Semiconductor device including superjunction structure formed using angled implant process
A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device. |
| US10276381B2 |
Semiconductor methods and devices
In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material. |
| US10276380B2 |
Method of semiconductor device fabrication
A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features. |
| US10276379B2 |
Treatment approach to improve film roughness by improving nucleation/adhesion of silicon oxide
In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer. |
| US10276372B2 |
Method for integrated circuit patterning
A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask. |
| US10276369B2 |
Material deposition for high aspect ratio structures
Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall. |
| US10276368B2 |
Method for producing glass substrate with through glass vias and glass substrate
A method for producing a glass substrate with through glass vias according to the present invention includes: irradiating a glass substrate (10) with a laser beam to form a modified portion; forming a first conductive portion (20a) on a first principal surface of the glass substrate (10), the first conductive portion (20a) being positioned in correspondence with the modified portion (12); and forming a through hole (14) in the glass substrate (10) after formation of the first conductive portion by etching at least the modified portion (12) using an etchant. This method allows easy handling of a glass substrate during formation of a conductive portion such as a circuit on the glass substrate, and is also capable of forming a through hole in the glass substrate relatively quickly while preventing damage to the conductive portion such as a circuit formed on the glass substrate. |
| US10276363B2 |
Mechanisms for forming patterns using multiple lithography processes
The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. |
| US10276358B2 |
Chemically modified ion mobility separation apparatus and method
An ion mobility spectrometry apparatus and method wherein ions are selected using an AC gate, then separated along a drift axis while providing a drift gas flow in a direction that is substantially neither in the direction of the drift axis nor opposite to the drift axis. |
| US10276357B2 |
Methods of ultraviolet photodissociation for mass spectrometry
A method is described that involves simplification of UVPD mass spectra and comprises selecting precursor ions for UVPD fragmentation, performing UVPD fragmentation on selected precursor ions to give UVPD fragment ions. PTR may then be performed on the UVPD fragment ions with optional ion parking to yield charge-state reduced UVPD fragment ions. The UVPD-PTR steps may be repeated above n times where n=1 to 50. Ion parking may enhance the intensity of selected lower fragment ion charge states or to increase the intensity of peaks in selected m/z ranges. After a number of PTR-UVPD iterations, fragment ions are mass analyzed. The method provides a way of simplifying UVPD mass spectral product ions by lowering fragment ion charge states and spreading out resulting product ions in m/z mass spectral space when compared to using UVPD fragmentation alone. |
| US10276348B2 |
Methods and apparatus for a hybrid capacitively-coupled and an inductively-coupled plasma processing system
A capacitively-coupled plasma (CCP) processing system having a plasma processing chamber for processing a substrate is provided. The capacitively-coupled Plasma (CCP) processing system includes an upper electrode and a lower electrode for processing the substrate, which is disposed on the lower electrode during plasma processing. The capacitively-coupled Plasma (CCP) processing system also includes an array of inductor coils arrangement configured to inductively sustain plasma in a gap between the upper electrode and the lower electrode. |
| US10276347B2 |
Apparatus of plural charged-particle beams
A multi-beam apparatus for observing a sample with high resolution and high throughput is proposed. In the apparatus, a source-conversion unit changes a single electron source into a virtual multi-source array, a primary projection imaging system projects the array to form plural probe spots on the sample, and a condenser lens adjusts the currents of the plural probe spots. In the source-conversion unit, the image-forming means is on the upstream of the beamlet-limit means, and thereby generating less scattered electrons. The image-forming means not only forms the virtual multi-source array, but also compensates the off-axis aberrations of the plurality of probe spots. |
| US10276345B2 |
Tunable ampere phase plate for charged particle imaging systems
A phase shifting device for a charged particle imaging system includes means for passing an electric current in a direction that has a nonzero component parallel to at least one section of the imaging beam. Preferably, the electric current is passed parallel along the section of the imaging beam. The amount of phase shift then centrosymmetrically depends on the distance between the electric current axis and the imaging beam axis. The magnetic field produced by the electric current exhibits the same effect on the phase of the beam as a localized charge according to the prior art. |
| US10276343B2 |
Method for acquiring image and ion beam apparatus
A method of acquiring an image of an image acquiring region of a sample comprises a first step of irradiating and scanning an ion beam in a first scan pattern on a first scan region of a sample, the scan region including therein the image acquiring region, and a second step of detecting secondary charged particles generated by irradiating and scanning the ion beam on the first scan region of the sample and generating first image data of the image acquiring region. The first and second steps are repeated a plurality of times using different scan patterns on different scan regions that differ from the first scan and the first scan region and from one another, each of the different scan regions including therein the image acquiring region, to generate a plurality of image data of the image acquiring region. Image data of the image acquiring region are generated by synthesizing all the image data generated by scanning the different scan region, and the synthesized image data of the image acquiring region are displayed on a display unit. |
| US10276342B2 |
Electron microscope
An electron microscope includes a monochromator, an image acquiring portion for obtaining an electron microscope image containing interference fringes of the electron beam formed by an aperture located behind the monochromator, a line profile acquiring portion for obtaining a plurality of line profiles passing through the center of the aperture on the EM image, an energy dispersion direction identifying portion for identifying the direction of energy dispersion of the monochromator on the basis of the line profiles obtained by the line profile acquiring portion, and an optics controller for controlling an optical system on the basis of a line profile in the direction of energy dispersion to bring the focal plane for the electron beam exiting from the monochromator into coincidence with the achromatic plane. |
| US10276338B2 |
Hollow fuse body with trench
Provided herein are protection devices, such as fuses, including a set of trenches or pockets for retention of solder therein. In some embodiments, a fuse includes a body including a center portion extending between a first and second end portions. The first end portion includes a first trench formed in a first end surface, and the second end portion includes a second trench formed in a second end surface. The fuse may further include a first and second endcaps surrounding respective first and second end portions. The fuse may include a fusible element disposed within a central cavity of the body, the fusible element extending between the first end surface and the second end surface. In some embodiments, solder may be disposed within the first trench and the second trench, wherein the solder is in contact with the fusible element, the first endcap, or the second endcap. |
| US10276336B2 |
Circuit breaker assembly including a circuit breaker connector
A circuit breaker assembly includes a circuit breaker cassette having a connector receiving zone, and a housing receptive of the circuit breaker cassette. The housing includes a connector mounting member. A circuit breaker connector member snap-fittingly extends into the connector receiving zone through the connector mounting member joining the circuit breaker cassette and the housing. |
| US10276333B2 |
Method of modifying an aircraft switch
Improvements a modified aircraft switch to protect from Foreign Object Debris (FOD) failure. The aircraft switch is manufactured from the factory as a new OEM switch, but can also be modified from a pre-existing switch. The switch and method to modify a switch to protect a widely used existing switch in military and commercial aircraft that is failing from Foreign Object Debris intrusion and failure from FOD. |
| US10276332B2 |
Actuator alternating indicator light
An exemplary embodiment of a load control device with a light indicator is disclosed. The load control device may include an actuator assembly and a light source. The actuator assembly may include a frame, a light pipe, and an actuator having two surfaces. The light pipe may be arranged within the actuator and include first and second legs. The first leg may extend towards the first surface, and the second leg may extend towards the second surface. When the actuator is in a first position, the light source may be optically aligned with one of the first and second legs; and, when the actuator is in a second position, the light source may be optically aligned with the other of the first and second legs. When the light source is illuminated, the light pipe may direct the light towards the respective surface of the actuator. |
| US10276331B2 |
Blocking members and circuit breakers having quick-make feature
A blocking member for an actuator having a movable arm for effecting a quick-make feature, includes for example, an elongated member having a first end and a second end, and wherein a portion of said elongated member being configured so that said blocking member disposed in a first position engages a portion of the movable arm of the actuator to restrain movement of the movable arm, and so that said blocking member disposed in a second position disengages from the portion of the movable arm of the actuator to permit movement of the movable arm. |
| US10276322B2 |
Laser-cut button veneer for a control device having a backlit keypad
A veneer configured to be secured to a backlit button of a control device may include a plate portion. The plate portion may have one or more laser-cut indicia defined therethrough, may have laser-cut rounded corners, and may have angularly offset outer edges that may be defined during an embossing process. The laser-cut indicia may be representative of a command for controlling an electrical load. The indicia may include an alphanumeric character, an icon, or the like, may define one or more substantially zero-radius corners, and may define respective inner surfaces that are substantially perpendicular to an outer surface of the plate portion. A laser-cut alphanumeric character may have variable (e.g., continuously variable) line width. The plate portion may define a rib that suspends a floating portion of the alphanumeric character relative to an open portion. The rib may define a thickness that does not exceed 0.003 inches. |
| US10276321B2 |
Dynamic coordination of protection devices in electrical distribution systems
A dynamically coordinatable electrical distribution system includes a plurality of intelligently-controlled protection devices (PDs), a communication and control bus (comm/control) bus, and a central computer. The plurality of intelligently-controlled PDs is configured to protect a plurality of associated electrical loads from faults, developing faults, and other undesired electrical anomalies. Each of the PDs further has electrically adjustable time-current characteristics. The intelligently-controlled PDs are communicatively coupled to the comm/control bus and configured to report current data representative of real-time currents flowing through their respective loads to the central computer, via the comm/control bus. The central computer is configured to communicate with the plurality of PDs over the comm/control bus and dynamically coordinate the time-current characteristics of the plurality of PDs based on the current data it receives from the PDs. |
| US10276319B1 |
Switch cover guard
A switch cover guard for guarding at least one electrical device in an electrical plate against access, use and/or damage has a security chamber surrounded by first, second, top and bottom guard walls. The security chamber is open to the rear to allow electrical switches/outlets to be accessed from within the chamber once the rear of the switch cover guard is attached onto the electrical plate. A front security plate can be slid between an open position, which allows access to the switch/outlet, and a closed position. When closed, the security chamber is sealed and the switch/outlet is no longer accessible. An adhesive attachment layer can secure the guard directly to the switch/outlet plate without requiring the plate to be opened. The front security plate can have a transparent or translucent front panel to allow light to pass through while the switch cover guard is closed. |
| US10276318B1 |
Insulated switch
In accordance with certain embodiments, an improved switching mechanism and related components are provided. |
| US10276317B2 |
Snap-action drive and switching device having a snap-action drive
A snap-action drive for a switching device has an energy store, a swinging movable part and a securing device for the movable part. The securing device secures a position of the swinging movable part by a force effect, wherein a reversal of direction of the movable part takes place counter to the force effect. |
| US10276314B2 |
Switching and protection device for high-voltage wiring system
A switching and protection device for high-voltage onboard electrical systems having a DC-voltage switch and a fuse, wherein the DC-voltage switch includes a housing, at least two fixed contacts, and a bridge designed to be movable with respect to the fixed contacts, wherein the bridge is formed from an electric insulator, wherein two contacts are arranged on the bridge such that, during a movement of the bridge in the direction of the fixed contacts, the two contacts make contact with the fixed contacts, wherein the two contacts arranged on the bridge are electrically connected to each other via the fuse. |
| US10276312B2 |
High surface area carbon materials and methods for making same
In a method of making a high surface area carbon material, a precursor organic material is prepared. The precursor organic material is subjected to a first elevated temperature while applying a gaseous purge thereto for a first predetermined time. The precursor organic material is subjected to a second elevated temperature while not applying the gaseous purge thereto for a second predetermined time after the first predetermined time. A high surface area carbon material includes carbon and has a surface area in a range between 3029 m2/g to 3565 m2/g and a pore volume in a range between 1.66 cm3/g and 1.90 cm3/g. The high surface area carbon material may be employed in an electrode for a supercapacitor. |
| US10276311B2 |
Apparatus and method for manufacturing electrodes
Disclosed are an apparatus for manufacturing electrodes and a method of manufacturing electrodes. The method of manufacturing electrodes includes providing a metal substrate having first and second surfaces opposite to each other, performing a patterning process on the first surface of the metal substrate, coating an electrode material on the first surface of the metal substrate, after the patterning process, and irradiating the electrode material, which is coated on the metal substrate, with light. The patterning process includes forming a plurality of holes to penetrate the metal substrate or forming a plurality of grooves to have a shape recessed from the first surface toward the second surface. |
| US10276310B2 |
Carbon fiber electrode, wire-type supercapacitor including the carbon fiber electrode and NO2 sensor and UV sensor including the supercapacitor
A wire shaped carbon fiber electrode is disclosed. The carbon fiber electrode includes braided strings of carbon fiber. The carbon fiber electrode is fabricated in a simple process, facilitating its practical application to clothes. In addition, the carbon fiber electrode possesses high capacitance and structural stability and is easily applicable to various wearable devices. Also disclosed are a wire-type supercapacitor including the carbon fiber electrode, a NO2 sensor including the supercapacitor, and a UV sensor including the supercapacitor. |
| US10276308B2 |
BST capacitor control
A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell. |
| US10276306B2 |
Method of producing a multilayer component
A method of producing a fully active multilayer element including producing a fully active stack, and optionally sintering of the fully active stack or a green precursor thereof; applying outer electrodes onto sides A′ and C′ of the fully active stack and contacting of the uncoated inner electrodes so that the two outer electrodes electrically connect to the uncoated inner electrode layers. |
| US10276304B2 |
Power capacitor unit for high pressure applications
A power capacitor unit for high-pressure applications is provided. The power capacitor unit includes a housing, a plurality of capacitor elements connected to each other and arranged inside the housing, a dielectric liquid (L), a solid electrical insulation system arranged to electrically insulate each capacitor element, a busbar, a plurality of fuse wires, each fuse wire having a first end connected to a respective capacitor element and a second end connected to the busbar (B), wherein the capacitor elements, the solid electrical insulation system, and the fuse wires are immersed in the dielectric liquid (L). Each fuse wire has a plurality of first sections that are in physical contact with the electrical insulation system, and wherein each fuse wire has a plurality of second sections without physical contact with the solid electrical insulation system. |
| US10276302B2 |
Process for treating a magnetic structure
Process for treating a magnetic structure, wherein it comprises the following steps: providing a magnetic structure comprising one first layer of magnetic material comprising a CoFeB alloy; irradiating the magnetic structure with light low-energy ions; and simultaneously holding the magnetic structure with a preset temperature profile and for a preset time. |
| US10276301B2 |
Current transformer and direct current source based on current transformer
A current transformer and a direct current source based on a current transformer are disclosed. In an embodiment, the current transformer includes two output ends; a first winding and a second winding connected in series between the two output ends; a main core; a bypass core, arranged to be magnetically coupled with the main core. The first winding is wound on a part of the main core and a part of the bypass core, and the second winding is wound on apart of the bypass core. In an embodiment, the current transformer also includes a high-frequency bypass, connected in parallel with the first winding, and used to filter a high-frequency signal. The high-frequency bypass provides a low-impedance path for a high-frequency signal in a primary conductor under measurement, such that the bypass core with the second winding presents less obstruction to the main core, thereby reducing heating. |
| US10276297B2 |
Holding device for a rogowski coil
A holding device includes a Rogowski coil, where the Rogowski coil includes a line portion wound into a coil. The holding device further includes a housing part into which the Rogowski coil is connected. A fastening part is configured to be releasebly connected to the housing part and is further configured to be attached to a current-conducting means formed for conducting a current. |
| US10276295B2 |
Compact vertical inductors extending in vertical planes
A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor. |
| US10276285B2 |
Chip resistor
Provided is a chip resistor including: a rectangular parallelepiped insulating substrate which is made of ceramics; a pair of front electrodes which are provided on lengthwise opposite end portions in a front surface of the insulating substrate; a resistive element which is provided between and connected to the two front electrodes; a protective layer which is made of a resin and which entirely covers the front surface of the insulating substrate including the two front electrodes and the resistive element; and a pair of cap-shaped end-surface electrodes which are provided on the lengthwise opposite end portions of the insulating substrate to establish electrical continuity to the front electrodes respectively; wherein: a chip element assembly in which the insulating substrate and the protective layer are laminated on each other but the end-surface electrodes have not been formed yet has an external shape substantially like a square cylinder. |
| US10276284B2 |
Methods and apparatus for preparing power transmission cables
A method for preparing a polymer insulated cable including a semiconductive layer surrounding a polymeric insulation layer includes: cutting the semiconductive layer by grinding a circumferential dividing groove in the semiconductive layer using a rotating grinding surface, wherein the dividing groove defines first and second semiconductive sections of the semiconductive layer on opposed sides of the dividing groove; and thereafter removing the second semiconductive section from the polymeric insulation layer while retaining the first semiconductive section on the polymeric insulation layer. |
| US10276282B2 |
Coaxial transmission line structure
A coaxial transmission line structure having a center conductor section having an input contact and an output contact the output contact being larger than the input contact, the center conductor having a plurality of different geometrically shaped, electrically conductive layers having sizes progressively increasing from the input contact to the larger output contact to conductor transition from the input contact to the larger output contact, the electrically conductive layers being electrically interconnected by staggered microvias passing through dielectric layers to the center, and (B) an outer conductor section disposed about, coaxial with, and electrically isolated from, the center conductor by the dielectric layers. |
| US10276280B1 |
Power over ethernet twisted pair communications cables with a shield used as a return conductor
A communications cable suitable for Power over Ethernet applications may include a plurality of twisted pairs of individually insulated conductors extending in a longitudinal direction. At least one of the plurality of twisted pairs may have a first direct current resistance and may be configured to transmit a power signal. A shield that includes longitudinally continuous electrically conductive material may be formed around at least a portion of the plurality of twisted pairs, and the shield may have a second direct current resistance approximately equal to the first direct current resistance. As a result, the shield may function as a return path or conductor for the at least one twisted pair. A jacket may also formed around the plurality of twisted pairs and the shield. |
| US10276277B2 |
Resin composition, copper paste, and semiconductor device
An object of the present invention is to provide a resin composition suitable for copper pastes, which can be cured in an ambient atmosphere and has a viscosity within an appropriate range and a low specific resistance after curing. This resin composition includes (A) a copper powder, (B) a thermosetting resin, (C) a fatty acid, (D) an amine, and (E) 4-aminosalicylic acid. Preferably, the (B) component is resol-type phenolic resin. More preferably, the (C) component is at least one selected from oleic acid, linoleic acid, linolenic acid, stearic acid, palmitic acid, lauric acid, butyric acid, and propionic acid. |
| US10276268B2 |
Coating of nuclear fuel cladding materials, method for coating nuclear fuel cladding materials
The invention provides a nuclear reactor cladding, wherein at least one layer of coating is deposited on the exterior surface of the cladding. A nuclear reactor cladding, wherein at least one layer of coating is deposited on the interior surface of the cladding. A method of coating a nuclear reactor cladding, with the steps of selecting the cladding and depositing at least one layer of a first coating on the cladding. |
| US10276266B1 |
Systems and methods for wireless prescription compliance monitoring
A medical information system informs prescribers of prescription compliance information in a system for preparing a prescription. The point of prescribing messaging system can assist physicians in understanding prescription compliance when prescribing medication for patients by reviewing pertinent compliance data displayed with the apparatus such as filling dates, dosage and supply information, etc. The system may include a point of prescription application configured to access, either locally or remotely, compliance data typically generated from a pharmacy system. Prescription filling data and supply/dosage information may be compared to generate automated alerts to a physician or prescriber to identify over use, under use, compliance or non-compliance situations based on the accessed and compared data or otherwise identify differences between prescribed medication information and filled medication information. |
| US10276264B2 |
Electronic health record system and method
Provided are a system and method for efficiently creating patient health records with help of expert clinical decision support. The system and method also ensures the doctor's documentation and diagnosis comply with the government healthcare quality measures. |
| US10276263B2 |
Systems and methods for surfacing contextually relevant content into the workflow of a third party system via a cloud-based micro-services architecture
Systems and methods for surfacing contextually relevant data into the workflow of a third party system are discussed herein. The system implements a near-real-time method of detecting activity corresponding to particular electronic health records associated with particular patients in third-party systems using specifically configured software systems. A cloud-based micro-services architecture is communicably coupled to the third-party systems and is operable to transmit contextually relevant data to the third-party system in response to particular detected activities, such as accessing a patient's electronic health record. The contextually-relevant data is identified by comparing electronic health record data from various third-party systems, each third-party system associated with the particular patient, to determine gaps in the records. The contextually relevant data is transmitted to the third-party system and visually integrated into the third-party system's pre-existing clinical workflow. |
| US10276262B1 |
Facilitating access to patient medical information
A method includes displaying a window of a first application which includes text corresponding to a patient identifier for a first patient. The method further includes receiving input corresponding to a preconfigured input sequence associated with an electronic health records (EHR) agent, and initiating, by the EHR agent in response to the preconfigured input sequence, a patient information overlay process. The patient information overlay process includes sending a copy command to copy first text from the window of the first application to the clipboard, accessing the first text, searching the accessed first text for an identification of a patient, determining that the patient identifier represents an identification of a patient, accessing patient information for the first patient based on the patient identifier, and displaying an overlay interface overlaid over the window proximate a cursor, the overlay interface including accessed patient information for the first patient. |
| US10276261B2 |
Patient library interface combining comparison information with feedback
Disclosed and described systems, methods, and apparatus provided facilitate analysis, presentation, and comparison of clinical information. An example system includes a processor configured to provide a patient library interface. The interface displays a plurality of events along a patient timeline and a list of items for comparison to a clinical scenario. The scenario is specified in an interface configuration to trigger collection of the list of comparison items. The processor receives and adds items to the list based on a relevancy analysis of each item to the clinical scenario. The processor facilitates feedback to add, remove, and rate relevance of item(s) in the list. The processor displays item(s) from the list in conjunction with documentation from the clinical scenario and facilitates user interaction with the item(s) and documentation. The processor updates a data source based on the user feedback and user interaction. |
| US10276255B2 |
Sample-and-hold circuit for an electrical signal
Sample-and-hold device for an electrical signal including an input module having two inputs, including a first switching block including two input switches, each input of the input module being connected at the input of one of the input switches, the input module being connected at the input of a first track-and-hold module with two inputs and two outputs, so as to alternately convey the signal from one of the two inputs to one of the two inputs of the first track-and-hold module; the device including a second track-and-hold module connected in parallel with the first track-and-hold module, these track-and-hold modules connected at the output of the first switching block, and an output module including a second switching block including two output switches, the outputs of the first and second track-and-hold modules being connected to the inputs of the output switches, to time interleave the output signals of the track-and-hold modules. |
| US10276250B1 |
Programming NAND flash with improved robustness against dummy WL disturbance
A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level. |
| US10276245B2 |
Semiconductor memory device and method of operating the same
A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to N-th program states divided based on threshold voltages. The peripheral circuit may perform a program operation on the memory cells. The control circuit may control the peripheral circuit so that, during the program operation, a primary program operation is performed, and after the primary program operation, a secondary program operation is performed. The primary program operation may include a plurality of verify steps performed for the first to N-1-th program states and a single primary verify step performed for the N-th program state. The secondary program operation may include a secondary verify step performed for the N-th program state. |
| US10276240B2 |
Nonvolatile semiconductor memory device with a plurality of memory blocks and a shared block decoder
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group. |
| US10276239B2 |
Memory cell and associated array structure
A memory cell includes a latch, two antifuse elements, and two select transistors. The latch is connected with a first node and a second node, and receives a first power voltage and a second power voltage. The latch is selectively enabled or disabled according to an enable line voltage. The first antifuse element is connected with the first node and an antifuse control line. The second antifuse element is connected with the second node and the antifuse control line. The gate terminal, the first drain/source terminal and the second drain/source terminal of the first select transistor are connected with a word line, the first node and a bit line, respectively. The gate terminal, the first drain/source terminal and the second drain/source terminal of the second select transistor are connected with the word line, the second node and an inverted bit line, respectively. |
| US10276238B2 |
Method, system and device for complementary non-volatile memory device operation
Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device. |
| US10276235B2 |
Enhancing nucleation in phase-change memory cells
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described. |
| US10276230B2 |
Memory arrays
Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines. |
| US10276227B2 |
Write algorithm for memory to reduce failure rate of write operations
A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state. |
| US10276226B2 |
Method and system for determining temperature using a magnetic junction
A method for measuring a temperature of magnetic junction switchable using spin transfer. The magnetic junction includes at least one magnetic layer. The method includes measuring a temperature variation of at least one magnetic characteristic for the magnetic layer(s) versus temperature. The method also includes measuring a bias variation in the magnetic characteristic versus an electrical bias for the magnetic junction. This measurement is performed such that spin transfer torque-induced variation(s) in the magnetic characteristic(s) are accounted for. The temperature versus the electrical bias for the magnetic junction is determined based on the temperature variation and the bias variation. |
| US10276225B2 |
Method and system for providing a magnetic junction usable in spin transfer or spin-orbit torque applications and including a magnetic barrier layer
A magnetic device and method for providing the magnetic device are described. The magnetic device includes magnetic junctions and spin-orbit interaction (SO) active layer(s). Each magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than an out-of-plane demagnetization energy. The pinned layer includes a magnetic barrier layer between a magnetic layer and a high PMA layer including at least one nonmagnetic component. The magnetic barrier layer includes Co and at least one of Ta, W and Mo. The magnetic barrier layer is for blocking diffusion of the nonmagnetic component. The SO active layer(s) are adjacent to the free layer. The SO active layer(s) carry a current in-plane and exert a SO torque on the free layer due to the current. The free layer is switchable between stable magnetic states using the SO torque. |
| US10276215B1 |
Data storage device fastener seal system
A data storage device fastener seal system can have at least a base, a cover, and a fastener seal. The base may have at least one fastener aperture and a first contact surface while the cover can have a second contact and a fastener hole. The second contact surface may physically contact the first contact surface to enclose a data storage region. The fastener seal can be positioned between the base and cover proximal the fastener aperture with the fastener seal extending less than an inch from the fastener aperture in every direction along a plane parallel to the first and second contact surfaces. |
| US10276213B2 |
Automatic and intelligent video sorting
Systems and methods disclosed herein provide automatic and intelligent video sorting in the context of creating video compositions. A computing device sorts a media bin of videos in the user's work area based on similarity to the videos included in the video composition being created. When a user selects or includes a particular video on the composition's timeline, the video is compared against the entire video collection to change the display of videos in the media bin. In one example, videos that have similar tags to a selected video are prioritized at the top. Only a subset of frames of each of the videos are used to use to identify video tags. Intelligently selecting tags using a subset of frames from each video rather than using all frames enables more efficient and accurate tagging of videos, which facilitates quicker and more accurate comparison of video similarities. |
| US10276210B2 |
Video enhancement
Methods, systems, and computer program products for generating revised videos. The method includes, for example, receiving, by one or more processor, first video data of an environment having at least one projection on a screen from a first point of view, and generating, by the one or more processor, revised video data of the environment having the at least one projection on the screen from the first point of view based on the first video data, the revised video data comprising a plurality of frames with the at least one projection on the screen disposed in the first area relative to the environment in a plurality of frames being revised based on data for projecting the at least one projection on the screen in the first video data. |
| US10276205B2 |
Library control device and library control method for removing malfunctioning media from magazine by rewriting its slot position
A library control device moves a desired record medium from a magazine, which is configured to load a plurality of record media into a plurality of slots, to a drive so as to read or write data. The library control device stores identifications of record media in correlation with slots loading recording media. Upon detecting a malfunction in reading or writing data with a record medium, an operator needs to extract the record medium from the magazine. At this time, the library control device rewrites the identification of a slot, which is stored in correlation with the record medium subjected to extraction, with the identification of a predetermined slot so as to move the record medium to the predetermined slot. Thus, it is possible for an operator to extract the record medium detecting a malfunction from the predetermined slot without making any mistake. |
| US10276202B1 |
Heat-assisted magnetic recording (HAMR) medium with rhodium or rhodium-based alloy heat-sink layer
A heat-assisted magnetic recording (HAMR) medium has a rhodium (Rh) or Rh-based alloy heat-sink layer. The Rh or Rh-based alloy does not roughen when annealed and thus does not require an intermediate layer between it and the MgO seed layer for the recording layer, so the MgO seed layer can be formed directly on and in contact with the Rh or Rh-based alloy heat-sink layer. The Rh or Rh-based alloy heat-sink layer is formed on a seed layer or multilayer that allows the Rh or Rh-based alloy to grow with the desired face-centered-cubic (fcc) crystalline structure. |
| US10276201B1 |
Dual phase MgO-X seed layers for heat assisted magnetic recording media
Magnetic media having dual phase MgO-X seed layers with both MgO grains and segregants are provided. One such magnetic medium includes a substrate, a heatsink layer on the substrate, a dual phase seed layer on the heatsink layer, where the dual phase seed layer comprises MgO and a segregant, where a concentration of the MgO is greater than 50 percent by volume in the dual phase seed layer, and a magnetic recording layer including FePt on the dual phase seed layer. |
| US10276196B2 |
Thin-film piezoelectric material substrate, thin-film piezoelectric material element, head gimbal assembly, ink jet head and method of manufacturing the thin-film piezoelectric material element
A thin-film piezoelectric material substrate includes an insulator on Si substrate and a thin-film laminated part. The insulator on Si substrate has a substrate for deposition made of silicon and an insulating layer formed on a surface of the substrate for deposition. The thin-film laminated part is formed on a top surface of the insulating layer. The thin-film laminated part has a YZ seed layer including yttrium and zirconium, and formed on the top surface; a lower electrode film laminated on the YZ seed layer; a piezoelectric material film made of lead zirconate titanate, shown by general formula Pb(ZrxTi(1-x))O3, and formed on the lower electrode film; and an upper electrode film laminated on the piezoelectric material film. |
| US10276194B2 |
Split-shaft pivot with interface spacer for a dual-actuator hard disk drive
A split-shaft pivot assembly for a dual-actuator data storage device may include a first pivot shaft around which a first bearing assembly is affixed, a second pivot shaft around which a second bearing assembly is affixed, and whereby the two pivot shafts are coupled together by way of an interface spacer between the shafts. The interface spacer may include a receiving structure at each end of a housing, for receiving an end of a respective shaft, and an annular slot circumscribing the housing between the receiving structures, where an elastomeric damper is positioned within the slot. The interface spacer housing may be composed of a material having a lower elastic modulus than the material of which the shafts are composed, thereby making the interface spacer relatively compliant. Such features may serve to inhibit and/or damp transmission of vibrational energy among the actuators through the shared split-shaft. |
| US10276193B2 |
Magnetic head having magnetic pole and shield, and magnetic recording and reproducing device
According to one embodiment, a magnetic head includes a magnetic pole having a first surface, a first shield separated from the magnetic pole along the first surface, and a stacked body provided between the magnetic pole and the first shield. The stacked body includes a magnetic layer, and first and second conductive layers. The magnetic layer includes at least one selected from the group consisting of Fe, Co, and Ni. The first conductive layer contacts the magnetic pole and the magnetic layer, and is provided between the magnetic pole and the magnetic layer. The second conductive layer contacts the magnetic layer and the first shield, is provided between the magnetic layer and the first shield. The first shield has a first shield surface contacting the second conductive layer. A ratio of a length of the magnetic layer to a length of the first shield surface is 0.1 or more. |
| US10276192B2 |
Perpendicular magnetic recording medium
A magnetic recording medium includes an amorphous buffer layer, a hybrid layer including a barrier layer, and a texture control layer. The magnetic recording medium also includes a heat sink layer, an under layer, and a perpendicular recording layer. |
| US10276190B2 |
Sentiment analysis of mental health disorder symptoms
Monitoring and analysis of a user's speech to detect symptoms of a mental health disorder by continuously monitoring a user's speech in real-time to generate audio data based, transcribing the audio data to text and analyzing the text of the audio data to determine a sentiment of the audio data is disclosed. A trained machine learning model may be applied to correlate the text and the determined sentiment to clinical information associated with symptoms of a mental health disorder to determine whether the symptoms are a symptom event. The initial determination may be transmitted to a second device to determine (and/or verify) whether or not the symptom event was falsely recognized. The trained machine learning model may be updated based on a response from the second device. |
| US10276188B2 |
Systems and methods for identifying human emotions and/or mental health states based on analyses of audio inputs and/or behavioral data collected from computing devices
Systems and methods are provided for analyzing voice-based audio inputs. A voice-based audio input associated with a user (e.g., wherein the voice-based audio input is a prompt or a command) is received and measures of one or more features are extracted. One or more parameters are calculated based on the measures of the one or more features. The occurrence of one or more mistriggers is identified by inputting the one or more parameters into a predictive model. Further, systems and methods are provided for identifying human mental health states using mobile device data. Mobile device data (including sensor data) associated with a mobile device corresponding to a user is received. Measurements are derived from the mobile device data and input into a predictive model. The predictive model is executed and outputs probability values of one or more symptoms associated with the user. |
| US10276185B1 |
Adjusting speed of human speech playback
A system configured to vary a speech speed of speech represented in input audio data without changing a pitch of the speech. The system may vary the speech speed based on a number of different inputs, including non-audio data, data associated with a command, or data associated with the voice message itself. The non-audio data may correspond to information about an account, device or user, such as user preferences, calendar entries, location information, etc. The system may analyze audio data associated with the command to determine command speech speed, identity of person listening, etc. The system may analyze the input audio data to determine a message speech speed, background noise level, identity of the person speaking, etc. Using all of these inputs, the system may dynamically determine a target speech speed and may generate output audio data having the target speech speed. |
| US10276173B2 |
Encoded audio extended metadata-based dynamic range control
An audio encoder encodes a digital audio recording having a number of audio channels or audio objects. A Dynamic Range Control (DRC) processor produces a sequence of encoder DRC gain values, by applying a selected one of a number of DRC characteristics to a group of one or more of the audio channels or audio objects. The encoder DRC gain values are to be applied to adjust the group of audio channels or audio objects, upon decoding them from the encoded digital audio recording. A bitstream multiplexer combines a) the encoded digital audio recording with b) the sequence of encoder DRC gain values, an indication of the selected DRC characteristic, and an indication of an alternate DRC characteristic, the latter as metadata associated with the encoded digital audio recording. Other embodiments are also described including a system for decoding the encoded audio recording and performing DRC adjustment upon it. |
| US10276168B2 |
Voiceprint verification method and device
Embodiments of the present invention provide a voiceprint verification method and device. The voiceprint verification method comprises receiving verification voice data relating to a verification phrase; generating a verification voiceprint on the basis of said verification voice data; determining whether a similarity value between the verification voiceprint and a reference voiceprint conforms to a preset similarity value; and, if the similarity value between the verification voiceprint and a reference voiceprint conforms to a preset similarity value, then determining there is a match between the verification voiceprint and the reference voiceprint. |
| US10276167B2 |
Method, apparatus and system for speaker verification
The present disclosure relates to a method, apparatus, and system for speaker verification. The method includes: acquiring an audio recording; extracting speech signals from the audio recording; extracting features of the extracted speech signals; and determining whether the extracted speech signals represent speech by a predetermined speaker based on the extracted features and a speaker model trained with reference voice data of the predetermined speaker. |
| US10276166B2 |
Method and apparatus for detecting splicing attacks on a speaker verification system
A method of detecting an occurrence of splicing in a speech signal includes comparing one or more discontinuities in the test speech signal to one or more reference speech signals corresponding to the test speech signal. The method may further include calculating a frame-based spectral-like representation ST of the speech signal, and calculating a frame-based spectral-like representation SE of a reference speech signal corresponding to the speech signal. The method further includes aligning ST and SE in time and frequency, calculating a distance function associated with aligned ST and SE, and evaluating the distance function to determine a score. The method also includes comparing the score to a threshold to detect if splicing occurs in the speech signal. |
| US10276165B2 |
Always-on audio control for mobile device
In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples. |
| US10276163B1 |
Speech recognition parameter adjustment
Audio data that encodes an utterance of a user is received. It is determined that the user has been classified as a novice user of a speech recognizer. A speech recognizer setting is selected that is used by the speech recognizer in generating a transcription of the utterance. The selected speech recognizer setting is different than a default speech recognizer setting that is used by the speech recognizer in generating transcriptions of utterances of users that are not classified as novice users. The selected speech recognizer setting results in increased speech recognition accuracy in comparison with the default setting. A transcription of the utterance is obtained that is generated by the speech recognizer using the selected setting. |
| US10276161B2 |
Contextual hotwords
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for contextual hotwords are disclosed. In one aspect, a method, during a boot process of a computing device, includes the actions of determining, by a computing device, a context associated with the computing device. The actions further include, based on the context associated with the computing device, determining a hotword. The actions further include, after determining the hotword, receiving audio data that corresponds to an utterance. The actions further include determining that the audio data includes the hotword. The actions further include, in response to determining that the audio data includes the hotword, performing an operation associated with the hotword. |
| US10276154B2 |
Processing natural language user inputs using context data
An embodiment provides a method, including: receiving, at a device, user input; identifying, using a processor, elements included in the user input; determining, using a processor, that at least one of the identified elements renders the user input ambiguous; identifying, using a processor, a source of context data; accessing, using a processor, context data associated with the user input from the source of context data; disambiguating, using a processor, the user input based on the context data associated with the user input; and forming, using a processor, an altered input based on the disambiguating. Other embodiments are described and claimed. |
| US10276143B2 |
Predictive soundscape adaptation
Methods and apparatuses for addressing open space noise are disclosed. In one example, a method for masking open space noise includes receiving a sensor data from a sensor arranged to monitor an open space over a time period. The method includes generating a predicted future noise parameter in the open space at a predicted future time from the sensor data. The method further includes adjusting a sound masking noise output from a loudspeaker prior to the predicted future time responsive to the predicted future noise parameter. |
| US10276139B1 |
Musical instrument having diminished chords interlaced with other chords
A musical instrument with two or more classes of pitches where at least one class is a diminished chord extended over an arbitrary number of octaves, and another class is another chord extended over the same span of octaves. The pitches of the second class of pitches are interlaced with the pitches of the diminished chord of the first class of pitches. Additional classes are chords similarly interlaced with other classes, with one class of any interlaced pair of classes being a diminished chord. |
| US10276138B2 |
Customizable wearable electronic musical instruments having user-installable controller modules and synthesis modules
A customizable electronic musical instrument includes a mounting frame for securing a plurality of user-installable electronic musical modules of various types including a type for generating at least one control signal responsive to user operation, a type for generating audio signals, responsive to a control signal. The instrument can transmit outgoing audio electrical signals to an external system and can include internal sound amplification. The instrument includes one or more types of controller elements such as a keyboard, touchpad, strumpad, impact sensor, slider control, expression wheel, joystick, ribbon controller, button, switch, pressure sensor, multiple-position selector, knob potentiometer, and further comprises at least one music synthesizer element. Control and audio signals may be routed among modules by a switch or bus. Audio signals can be mixed by a multichannel audio mixer and/or processed responsive to at least one control signal. Outgoing control signals responsive to controller electronic musical modules. |
| US10276134B2 |
Decision-based data compression by means of deep learning technologies
Data may be handled based on compressibility (i.e., whether the data may be further compressed or is not further compressible). A supervised learning model may be trained using a set of known further compressible data and a set of known non-compressible data. Using these data sets, the model may generate weighting factors and bias for the particular data sets. The trained model may then be used to evaluate a set of unclassified data. |
| US10276133B2 |
Projector and display control method for displaying split images
A projector includes: a projecting section that projects an image onto a projection surface; an imaging section that captures the image projected on the projection surface and a person located between the projecting section and the projection surface, and obtain a captured image; a specifying section that specifies a split position of the projection surface based on a position of the person in the captured image; and a display control section that splits the projection surface into a plurality of areas at the split position specified by the specifying section and controls the projecting section so as to project different images in the plurality of areas. |
| US10276128B2 |
Display control method, display control device and display system
A display control device and a display system are provided. The display control method includes: detecting if a glare is presented on the surface of the semi-translucent polarizing film layer on the emergent light side of the display device; generating a driving signal for driving the display device to display a non-black image in a glare compensation region if a glare is detected to be presented on the surface of the semi-translucent polarizing film layer; in which the glare compensation region corresponds to a glare region in the semi-translucent polarizing film layer and the glare region is an region in which a glare is presented. The display control method of the present disclosure may reduce glare intensity when a glare is created on a mirror surface such as a rearview mirror. |
| US10276127B2 |
Identifying users from screen touch events
Examples are disclosed that relate to attributing touch events on a touch-sensitive computing device to a user who performed the touch event. One example provides a computing system, comprising a touch sensor, a communication subsystem comprising a first communication mechanism integrated with the touch sensor, the first communication mechanism configured to communicate with a portable device over a first communication channel via a body-transmissible signal upon detection of a touch input, and also comprising a second communication mechanism configured to communicate with the portable device via a second communication channel. The computing device further comprises instructions executable to detect a touch input via the touch sensor, communicate information to the portable device via the body-transmissible signal using the first communication mechanism, and connect with the portable device via the second communication mechanism based upon the information communicated to the portable device via the body-transmissible signal. |
| US10276126B2 |
Information processing method and electronic device
The present disclosure provides an information processing method and an electronic device. The electronic device has a display unit, and is capable of generating a deformation in response to a stress. The display unit of the electronic device is capable of presenting M window interfaces, each of the M window interfaces being used for displaying a separate display content. The method comprises: determining a first display sub-region of the display unit which is in a presentation state, when it is judged that the electronic device has generated a predetermined deformation; obtaining a first attribute parameter of a first window interface among the M window interfaces; and displaying the first window interface in the first display sub-region if the first attribute parameter satisfies a preset condition. |
| US10276123B2 |
Display apparatus and driving method thereof
A display apparatus includes: a display panel including pixels respectively connected to gate lines and data lines; a data driving circuit to output a data output signal in response to a data signal; a demultiplexer circuit to provide first and second data lines from among the data lines with the data output signal, in response to control signals; and a driving controller to provide the data signal and the control signals. The demultiplexer circuit includes: a switching transistor including a first electrode to receive the data output signal, a second electrode connected to the first data line, and a gate electrode connected to a first node; and a switching control circuit to charge the first node to turn on the switching transistor during a first interval of a first horizontal period, and to discharge the first node during a second interval of the first horizontal period. |
| US10276121B2 |
Gate driver with reduced number of thin film transistors and display device including the same
In a gate driver, a Q node is shared by two channels to output a scan signal at high level, and a QB node is shared by four channels to output a scan signal at low level. Accordingly, the number of thin-film transistors required to configure four channels of a gate-in-panel (GIP) is reduced, such that the bezel size can be reduced. Further, the gate driver includes a compensation capacitor or a discharge transistor disposed in some of the channels sharing the Q node, such that deviation in output characteristics among the channels sharing the Q node can be reduced. |
| US10276115B2 |
Display circuit and LCD having the display circuit
The invention provides a display circuit and a LCD having the display circuit. The display circuit includes a display unit, a level shifter, a timer controller, and scanning circuits. Each scanning circuit includes a first voltage stabilizing circuit including first and second field effect transistors. Source electrodes of the two transistors are connected to the level shifter. The scanning circuits send a first group of scanning signals to the display unit in sequence in a first period of time, and send a second group of scanning signals to the display unit in sequence in a second period of time. The timer controller sends a control signal to the level shifter in a time difference between the two groups of signals. The level shifter converts the control signal to a high level signal and sends it to the two transistors to enable the two transistors to be under reverse bias. |
| US10276110B2 |
Liquid crystal panel driver and method for driving the same
A liquid crystal panel driver includes a signal controller to generate pixel clock signals and adjust duty cycle of the pixel clock signals, and a gate driver to receive the pixel clock signal of an adjusted duty cycle and a preset gate turn-on voltage provided by an external signal source, and calculate the actual gate turn-on voltage provided to the gate lines based on the pixel clock signal of the adjusted duty cycle and the preset gate turn-on voltage. The present disclosure also proposes a method for driving drivers of a liquid crystal display, the drivers comprising a signal controller and gate drivers. The liquid crystal panel driver and the method to ensure that each gate driver outputs an identical gate turn-on voltage VGH, therefore areas driven by each gate drivers have the same actual charging time, which elevates the display quality of an LCD. |
| US10276109B2 |
Method for driving electro-optic displays
A method for driving an electro-optic display having a front electrode, a backplane and a display medium positioned between the front electrode and the backplane, the method comprising of applying a first driving phase to the display medium, the first driving phase having a first signal and a second signal, the first signal having a first polarity, a first amplitude as a function of time, and a first duration, the second signal succeeding the first signal and having a second polarity opposite to the first polarity, a second amplitude as a function of time, and a second duration, such that the sum of the first amplitude as a function of time integrated over the first duration and the second amplitude as a function of time integrated over the second duration produces a first impulse offset. The method further comprising applying a second driving phase to the display medium, the second driving phase produces a second impulse offset, wherein the sum of the first and second impulse offset is substantially zero. |
| US10276099B2 |
Organic light emitting diode display and method for driving the same
Disclosed is an organic light emitting diode (OLED) display that includes a display panel including a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of pixels, each pixel including a driving transistor, a switching transistor, an OLED and a storage capacitor; a timing controller that receives pixel data of an input image and timing signals and time-divides a period of one frame into at least a driving sub-frame and a compensation sub-frame based on one or more of the timing signals; and a display panel driver that converts the pixel data into data voltages and supplies the data voltages to the plurality of data lines during the driving sub-frame, and that adjusts compensation gray levels of the plurality of pixels or compensation duties of the plurality of pixels based on a luminance map, which contains information on a luminance deviation for each pixel with respect to a same gray level, during the compensation sub-frame. |
| US10276097B2 |
Pixel circuit, driving circuit, array substrate and display device
The present disclosure relates to the OLED display technology. There are provided a pixel circuit, a driving circuit, an array substrate and a display device, which are supplied with the voltage by the light emitting operation voltage when the pixel circuit enters the light emitting stage, by inputting an inverse signal synchronized with the pre-charging control voltage at the input terminal of the light emitting operation voltage to ensure a stable output of the current by the circuit at the light emitting stage. Also, it does not require an arrangement of an external voltage input terminal which will affect the aperture ratio, thereby increasing the aperture ratio of the OLED employing the current-driven pixel circuit while ensuring the stable output of the current by the current-driven circuit, and thus increasing the lifetime of the OLED employing the current-driven pixel circuit. |
| US10276094B2 |
Pixel driving circuit and driving method therefor, and organic light-emitting display panel
A pixel driving circuit, a driving method and an organic light-emitting display panel are provided. The pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistors, and a capacitor. A first node is present between the fourth transistor and the fifth transistor. The seventh transistor is coupled between a reference voltage line and the first node, and the eighth transistor is coupled between the reference voltage line and an anode of the light-emitting element. |
| US10276093B2 |
Organic light emitting diode display device using vertical synchronization signals with different phase
An organic light emitting diode (OLED) display device is discussed. The OLED display device includes a display module including a display panel and a panel driver for driving the display panel, and a host system externally separated from the display module. The OLED display device further includes an interface device including a transmission module configured to transmit sensing data via a plurality of vertical synchronization signals for communication between the host system and the display module. The transmission module generates first and second vertical synchronization signals having blank periods that are not overlapping with each other. The interface device transmits the sensing data in a sensing period of one vertical synchronization signal that overlaps with the blank period of another vertical synchronization signal. |
| US10276089B2 |
Electronic device and method for driving the same
An electronic device includes a display portion, an imaging portion, a control portion, an input portion, and a sensor portion. The display portion has a first display element that reflects visible light and a second display element that emits visible light. The display portion has a function of displaying an image using one of or both first light reflected by the first display element and second light emitted from the second display element. The imaging portion takes an image of an object, the control portion controls the display portion and the imaging portion, the input portion inputs a signal for controlling the display portion and the imaging portion to the control portion, and the sensor portion outputs sensing data to the control portion, in consideration of illuminance of external light. Such a display device increases the display quality, or keeps high-quality display regardless of environmental conditions and reduces power consumption. |
| US10276088B2 |
Pixel array structure
A pixel array structure includes a plurality of scanning lines and a plurality of pixel blocks. Each pixel block includes a plurality of data lines, a plurality of pixel units, a wireless receiving unit, and a position selection unit. The plurality of pixel units is arranged in an array form, and each pixel unit is coupled to one of the plurality of scanning lines and one of the plurality of data lines. The wireless receiving unit receives a data signal in a wireless manner. The position selection unit transmits the data signal to one of the plurality of data lines according to a position selection signal. |
| US10276085B2 |
Pixel signal compensation for a display panel
This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel. |
| US10276084B2 |
Circuit having a variable output and a converter controller including same
A circuit has a variable output that changes an output of a fixed input inversion amplification circuit, which includes a first operation amplifier with one input terminal that is applied with a fixed input value. The circuit includes an intermediate inversion amplification circuit having a second operation amplifier with an output terminal that is connected to another input terminal of the operation amplifier included in the fixed input inversion amplification circuit. One input terminal of the second operation amplifier is applied with the same input value as the fixed input value applied to the one input terminal of the first operation amplifier. Another input terminal of the second operation amplifier is applied with a variable input corresponding to an output of the first operation amplifier. |
| US10276081B2 |
Display device with color and luminance characterization and compensation methods
Improved display devices, information handling systems and related methods are provided for color and luminance characterization and compensation. According to one embodiment, a characterization method is provided for correlating the color/luminance measured from light emitted by a light source disposed within the display device to the color/luminance measured from light output from the display device at the time of manufacture. After the display device is characterized and a set of characterization values are stored, a compensation method is used during operation of the display device to perform color/luminance compensation for the light output from the display device by measuring the color/luminance of the light source illumination, and adjusting color gain values to maintain the color/luminance of the output light at a reference set point. |
| US10276080B2 |
RGBW pixel rendering device and method
The disclosure provides a RGBW pixel rendering device, including a collecting module obtaining a RGB grayscale value, converters converting the RGB grayscale value to a RGB brightness value and converting a second RGBW brightness value to a RGBW grayscale value to be output, a sampler, converting the RGB brightness value to a first RGBW brightness value, a judging element obtaining saturation values and brightness values, and calculating the saturation values and the brightness values respectively to obtain a saturation value difference and a brightness value difference for judging, a rendering element rendering the first RGBW brightness value according to an outcome to obtain the second RGBW brightness values. The disclosure further provides a rendering method. Compared with the prior art, the display has relatively high resolution without losing details. |
| US10276077B2 |
Driving circuit
A driving circuit includes an amplifier circuit, a control path, and a control circuit. The control path is coupled to the amplifier circuit. The control circuit is coupled to the control path. The control circuit receives a control signal and outputs a modulation signal to the control path according to the control signal. |