最新美国发明专利第2019-04-23期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US10270782B2	Virtual desktopaccess control A virtual desktop access control is disclosed. A gateway apparatus receives a virtual desktop access request from a client, obtains a virtual desktop access policy according to a source address of the virtual desktop access request, and determines a virtual switch according to a destination address of the virtual desktop access request, wherein the destination address is an address of a virtual desktop that is connected to the virtual switch. The gateway apparatus sends the virtual desktop access policy to the virtual switch, such that the virtual switch is allowed to control a level of access which the virtual desktop has to access network resources. The gateway apparatus forwards the virtual desktop access request to the virtual desktop, receives a response to the virtual desktop access request from the virtual desktop, and forwards the response to the client.
US10270780B2	Access management using electronic images Techniques are described for an access management system to manage access to a service (e.g., a message management service). A client can receive a message including an electronic image from a messaging service. The electronic image can include access information for obtaining access to a message management service. Input is received that indicates interaction with the electronic image in an interface. The client can send, to the access management system, the electronic image to request access to the message management service based on the access information. Authorization is received from the access management system indicating that the account can access the message management service. The client displays an interface to provide access to the message management service. The access to the message management service can be based on the authorization.
US10270765B2	Enabling application functions responsive to biometric input from more than one person A method includes running an application on a mobile computing device, the mobile computing device accepting biometric input, and the mobile computing device enabling one or more function of the application only in response to the biometric input indicating that more than one person is present in the same location. Examples of suitable biometric input include a fingerprint, heartbeat, iris scan, facial recognition, and voice recognition. The biometric input may be provided directly to the mobile computing device from the more than one person present, or the biometric input may be provided by a first person to a first mobile computing device and by a second person to a second mobile computing device.
US10270763B2	Virtual SIM authentication According to a first aspect of the present disclosed subject matter, a mobile terminal comprises a single cellular modem having concurrent protocol stack that is capable of simultaneous communicating over two channels with at least one mobile network, a logic selector configured to pass authentication information of a SIM to the modem, wherein the SIM can be a physical SIM accommodated in a first slot (native SIM) or a virtual SIM. The terminal further comprises firmware retained in a non-transitory memory operative to cause the mobile terminal to obtain and authenticate the virtual SIM for communicating with the at least one mobile networks, wherein the virtual SIM is obtained from a SIM server connected to a SIM bank that comprises a plurality of SIM profiles.
US10270762B2	User authentication method for enhancing integrity and security Disclosed is a user authentication method including at least: (1) performing a primary conversion to generate a first common authentication key and performing a secondary conversion to provide an encrypted first common authentication key, and registering the encrypted first common authentication key; (2) generating a first server authentication key, and performing an OTP operation on the first server authentication key to generate first server authentication information; (3) performing a primary conversion to generate a second common authentication key, performing a secondary conversion to generate an encrypted second common authentication key, generating a first user authentication key, and performing an OTP operation on the first user authentication key to generate first user authentication information; and (4) performing a user authentication or an authentication of the authentication server for determining a genuineness of the authentication server, based on coincidence of the first server authentication information and the first user authentication information.
US10270760B2	Domain joined virtual names on domainless servers Services from domainless machines are made available in a security domain under a virtual name. Each machine is not joined to the domain but can reach a security domain controller. The controller controls at least one security domain using an authentication protocol, such as a modified Kerberos protocol. One obtains a set of security domain credentials, generates a cluster name secret, gives the cluster a virtual name, and authenticates the machines to the domain controller using these items. In some cases, authentication uses a ticket-based protocol which accepts the cluster name secret in place of a proof of valid security domain membership. In some, the domain controller uses a directory service which is compatible with an active directory service; the cluster virtual name is provisioned as an account in the directory service. The cluster virtual name may concurrently serve clients on different security domains of the directory service.
US10270759B1	Fine grained container security A system for a containerized application includes an interface and a processor. The interface is configured to receive an indication from a user to create a containerized application. The indication comprises a first user authentication information (e.g., an authentication token issued by an authentication server) and an application permission information. The processor is configured to determine whether the first user authentication information indicates that the user has permission to create a definition for the containerized application with the application permission information, and, if so, create the definition for the containerized application with the application permission information. The processor is configured to determine whether a second user authentication information indicates that the user has permission to execute the containerized application using the definition for the containerized application, and, if so, indicate to process a job using the containerized application.
US10270757B2	Managing exchanges of sensitive data A method, system or computer usable program product for managing exchanges of sensitive data including utilizing a processor to request a service across a network from an application, the service requiring a disclosure of a first set of sensitive data by the application; providing a set of certified policy commitments regarding the first set of sensitive data to the application for a determination of acceptability; and upon a positive determination, receiving the service including the disclosure of the first set of sensitive data.
US10270756B2	Service providing method, and service providing device A service providing method, the method comprises transmitting, by a first information processing device, a certification token including a first role information on a service provided by the first information processing device to a terminal device when a certification is successful in response to a certification demand from the terminal device, receiving, by the first information processing device, the certification token and a first address information, that identifies a service providing device and indicates the first information processing device, from the terminal device, and transmitting, by the first information processing device, a first token including the first role information indicated by the certification token which is received and a second address information, that identifies the service providing device and indicates a second information processing device, to the second information processing device which is either one of the service providing device or a way device to the service providing device.
US10270749B2	Apparatus and method for managing files An apparatus includes a file managing application and a device management policy data. The apparatus receives deadline data from a remote administration system. The deadline data including at least one time limit for use of at least one user file stored in the apparatus. The apparatus stores the received deadline data in the device management policy data. The file managing application makes the at least one user file inoperable in the apparatus at and after the time limit defined by the deadline data.
US10270748B2	Advanced authentication techniques and applications A system, apparatus, method, and machine readable medium are described for performing advanced authentication techniques and associated applications. For example, one embodiment of a method comprises: receiving a policy identifying a set of acceptable authentication capabilities; determining a set of client authentication capabilities; and filtering the set of acceptable authentication capabilities based on the determined set of client authentication capabilities to arrive at a filtered set of one or more authentication capabilities for authenticating a user of the client.
US10270746B2	People-based user synchronization within an online system Embodiments include one or more client devices accessible by users, an online system, and one or more partner systems such that the online system is able to identify a user of the online system across different devices and browsers based on the user activity that occurs external to the online system. A user performs user actions (e.g. purchase a product) on a web page of a partner system and may provide personally identifiable information (PII) to the partner system. The partner system provides the hashed PII and user actions performed by the user to the online system. The online system identifies a user profile on the online system by matching personal information in the user profile to the hashed PII. The online system generates a confidence score indicating a likelihood that the identified user of the online system is the individual that performed the external user action.
US10270745B2	Securely transporting data across a data diode for secured process control communications Securely transporting data across a unidirectional data diode interconnecting a process plant to a remote system includes provisioning, using join key material, a sending device at the plant end of the diode with a receiving device at the remote end. The join key material is used to securely share network key material that is used to encrypt/decrypt messages or packets that are transported across the diode and whose payload includes plant—updated or re-set generated data. The shared network key material is recurrently using the join key material, and the recurrence interval may be based on a tolerance for lost data or other characteristic of an application, service, or consumer of plant data at the remote system.
US10270744B2	Behavior analysis based DNS tunneling detection and classification framework for network security New and improved techniques for a behavior analysis based DNS tunneling detection and classification framework for network security are disclosed. In some embodiments, a platform implementing an analytics framework for DNS security is provided for facilitating DNS tunneling detection. For example, an online platform can implement an analytics framework for DNS security based on passive DNS traffic analysis.
US10270742B2	Cryptographic service with output redirection A method is provided for redirecting signed code images. The method includes the steps of receiving a code image from an origin device at a proxy machine, invoking a code signing client at the proxy machine, receiving signing request information indicating a requested cryptographic operation, sending a code signing request to a code signing server, receiving a signed code image at the code signing client from the code signing server, storing the signed code image in a restricted memory, invoking a software repository client at the proxy machine, and sending the signed code image from the restricted memory location to a software repository.
US10270741B2	Personal authentication and access A user of a system defines a limited use access token for an external user for that external user to access defined resources of the system based on the user's account with the system. An access control system validates the access token when the external user attempts to access the defined resources and grants the external principal access to the defined resources.
US10270740B2	Systems and methods for configuration driven rewrite of SSL VPN clientless sessions The present disclosure provides solutions for an enterprise providing services to a variety of clients to enable the client to use the resources provided by the enterprise by modifying URLs received and the URLs from the responses from the servers to the client's requests before forwarding the requests and the responses to the intended destinations. An intermediary may identify an access profile for a clients' request to access a server via a clientless SSL VPN session. The intermediary may detect one or more URLs in content served by the server in response to the request using one or more regular expressions of the access profile. The intermediary may rewrite or modify, responsive to detecting, the one or more detected URLs in accordance with a URL transformation specified by one or more rewrite policies of the access profile. The response with modified URLs may be forwarded to the client.
US10270735B2	Distributed components in computing clusters The subject disclosure is directed towards components in different server clusters, e.g., comprising software components such as components of a distributed computing system. Components are available for use by distributed computing system applications, yet managed by the distributed computing system runtime such that only a single instance can be activated and exist within communicating (non-partitioned) clusters. Also described is recovery from a situation in which no longer partitioned clusters each have created the same component.
US10270731B2	Systems and methods for providing shared content-based minutiae post recommendations Systems, methods, and non-transitory computer-readable media can receive shared content information associated with a content item selected by a user for sharing on a social networking system. A minutiae post recommendation is determined based on the shared content information. The minutiae post recommendation is presented on a user device.
US10270728B1	Managing notifications across services A system and method identify first notification data and second notification that notify a user of a message about an activity that is of interest to the user. The system and method send the first notification data to a first client service and the second notification data to a second client service. The system and method receive a read notification indicating that the first notification data sent to the first client service has been interacted with by the user. The system and method update a first read status associated with the first notification data and a second read status associated with the second notification data. The system and method send a modify instruction to the second client service that instructs the second client service to modify the second notification data that has not been interacted to reflect that the first notification data has been interacted with by the user.
US10270727B2	Short message communication within a mobile graphical map In one embodiment, a computer-implemented process is programmed or configured to allow a first mobile device to generate and send enriched pin data to a geographical messaging system. Enriched pin data may include latitude and longitude data, a timestamp, and a media element. Media elements may include image data, video data, text data, drawing data that defines a geographic location, route data that defines a geographic travel path, and/or pin expiration data. The geographical messaging system may then broadcast the enriched pin data to a second mobile device belonging to a team member in the same geographical region as the first mobile device. The second mobile device may then use the enriched pin data to display, on a geographical map, a map pin that corresponds to the enriched pin data. In one embodiment, the second mobile device may also use the enriched pin data to display, in a message chain, a message related to the enriched pin data.
US10270723B2	Systems and methods for providing unread content items from specified entities Systems, methods, and non-transitory computer-readable media can acquire a specified set of one or more entities associated with a user of a social networking system. A collection of content items provided by the specified set of one or more entities can be detected. One or more content items that are unread by the user can be identified out of the collection of content items. The one or more content items unread by the user can be sorted, in a chronological order, to produce a sorted set of one or more unread content items. An interface can be provided to the user for accessing the sorted set of one or more unread content items.
US10270718B2	Operational safety mode The present disclosure generally relates to implementing an operational safety mode that manages the output of notifications at an electronic device when a user of the device is operating a vehicle.
US10270716B2	Switching device based on reordering algorithm A switching device includes a processor, an input buffer, an output buffer, and a Banyan switching architecture, where the processor is configured to convert an initial switching table to a non-congestion switching table and an order-adjustment table using a preset reordering algorithm; the input buffer is configured to save first period data that is from an input port; the processor is further configured to perform, using the non-congestion switching table, data switching on data in the first full-period data saved in the input buffer, to obtain second full-period data; the Banyan switching architecture is configured to perform synchronous data switching on the second full-period data; the output buffer is configured to save the second full-period data on which the synchronous data switching has been performed; the processor is further configured to adjust, using the order-adjustment table, a data order of the second period data.
US10270715B2	High performance network I/O in a virtualized environment From received data packets intended for a target virtual machine of a virtualization system, a destination network address of the target virtual machine is determined, and a current write buffer pointer is identified that points to a buffer associated with the identified target virtual machine corresponding to the destination network address. If the identified write buffer pointer indicates that the buffer has sufficient available space to accept the data packets, and if the associated buffer has sufficient available space, the data packets are placed in the associated buffer in buffer data locations according to a calculated new write buffer pointer value, and a wakeup byte data message is sent to a designated socket of the target virtual machine. Generally, the target virtual machine detects the wakeup byte data message at the designated socket and, in response, retrieves the data packets from the associated buffer in accordance with the new write buffer pointer value.
US10270712B1	Virtual storage network connectivity service Described are techniques for processing a network connectivity request received by a virtual network connectivity service. First processing is performed by the virtual network connectivity service to service the network connectivity request. The first processing includes determining a first of a plurality of network control planes to which the network connectivity request is directed, selecting, in accordance with the first network control plane, one of a plurality of modules, and invoking the one module in connection with performing processing to service the network connectivity request.
US10270708B2	Aggregated adaptive bit rate streaming Systems, methods and devices provide efficient bandwidth allocation on a satellite, mobile telephone or other data connection by allowing nodes to share bandwidth for commonly-requested data. A transmission center, uplink or other gateway suitably recognizes when content requests from multiple different nodes are simultaneously requesting delivery of the same content. When the same content is recognized, the gateway device allocates shared bandwidth on the data transmission link for the requested content that is accessible to both the first and second nodes.
US10270702B2	Kind of transmission method based on the network learnable power model A kind of transmission method based on the learnable power model, which conducts periodic record for the historical change trend of the network. This method conducts weighting smooth processing on the round trip time and judges the changing trend of congestion control window. Then, it establishes model for the relationship between network power and the congestion control widow. When a new ACK is received, it immediately updates the window of power model. Finally, it forecasts the size of the congestion control window of the next time period by combining the congestion window and the network power changing trend. For the network packet loss or time-out events, the retransmission mechanism of traditional TCP is used, and when the packet loss ends, the power model process is used again. This invention reduces the influence of the network random events of the estimation error of traditional algorithm.
US10270699B2	Automated flow devolvement in an aggregate flow environment Mechanisms for devolving microflows from aggregate flows are disclosed. An ingress node receives a packet that matches an aggregate flow entry in a flow table. A determination that a devolve action is associated with the aggregate flow entry is made. Based on the determination that the devolve action is associated with the aggregate flow entry, a microflow flow entry is generated in the flow table to define a microflow. The microflow flow entry includes header information extracted from the packet. Microflow generation information that identifies the microflow is sent to a controller node. It is determined that the microflow has timed out based on an idle timeout period of time. In response to determining that the microflow has timed out, microflow termination information that includes path measurement metric information associated with the microflow is sent to the controller node.
US10270697B2	E-TREE service with optimal forwarding in EVPN In one embodiment, when an ingress provider edge (PE) device of a computer network domain receives a frame at the ingress PE device destined to a destination media access control (MAC) address, it can determine whether the frame was received on a root or leaf Ethernet ingress segment, and also whether the destination MAC address is located via a root or leaf Ethernet segment. Accordingly, the ingress PE device may either drop or forward the frame based on the ingress Ethernet segment and destination MAC address Ethernet segment being either a root or a leaf, respectively.
US10270689B2	Multi-nonce enabled interest packet design for named-data networking A router, and a method of routing an interest packet having multiple nonces in NDN to eliminate stale PIT entries. The method includes a consumer device initially sending an interest packet having a first nonce within a protocol data unit (PDU), the interest packet having a second nonce. A router receives the interest packet and creates a pending interest table (PIT) entry. The consumer device resends the interest packet, the router keeping a single PIT entry per consumer device and using the second nonce to clear PIT entries corresponding to the initial transmission of the consumer device. The first nonce is indicative of requested content from the producer device, and the second nonce is indicative of the consumer device.
US10270685B2	Communication apparatus, control method therefor, and computer-readable storage medium The following processing is executed by a communication apparatus capable of performing wireless communication in a first communication mode in which communication is performed via an access point and a second communication mode in which communication is performed with a communication partner apparatus in a peer-to-peer mode. If communicating with the communication partner apparatus in the second communication mode, it is determined whether to concurrently execute operations in the first communication mode and the second communication mode. If it is determined to concurrently execute the operations in the first communication mode and the second communication mode, it is controlled to operate as a service providing source which provides a service in the second communication mode.
US10270681B2	Method for scalable computer network partitioning Various techniques for partitioning a computer network is disclosed herein. In certain embodiments, control plane functions (e.g., computation of network routes) and/or forwarding plane functions (e.g., routing, forwarding, switching) may be partitioned and performed individually on per domain basis based on (1) a network configuration of a particular domain (e.g., end points and/or lower-level domains in the particular domain); and (2) one or more higher-level domains connected to the particular domain in the hierarchy. Thus, a particular domain can manage various network operations of the domain without concerns regarding end points or network nodes in other domains of the hierarchy. Thus, network configuration and operation may be partitioned to reduce hardware costs and operational complexity even as the size of the overall computer networks increases.
US10270679B2	Determining connections between nodes in a network According to one embodiment of the present invention, a system determines groups of nodes within a network, each group forming a bi-connected component. The system identifies articulation nodes within the network, where each articulation node resides within each connection between a pair of nodes in the network. The system removes from the determined group each node that includes an articulation node between that node and both the source and target nodes to produce a resulting set of nodes. The system determines connections between the source and target nodes based on the resulting set of nodes. Embodiments of the present invention further include a method and computer program product for determining connections between network nodes in substantially the same manners described above.
US10270678B2	System including master device and slave device, and operation method of the system A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. The master device determines a temperature of the slave device in response to the temperature information, and controls the slave device based on the determined temperature of the slave device.
US10270676B2	Signal detecting device A signal detecting device provided in a connector at an end of a communication cable or in a communication device to which the connector is connected. The signal detecting device includes a detection circuit that branches and extracts a portion of a signal transmitted through the communication cable and indicates existence of a data communication based on the extracted signal, and a self-diagnostic circuit that inputs a diagnostic signal into the detection circuit upon diagnosis of the detection circuit.
US10270664B2	Segment routing over label distribution protocol An apparatus and method is disclosed for segment routing (SR) over label distribution protocol (LDP). In one embodiment, the method includes a node receiving a packet with an attached segment ID. In response, the node may attach a label to the packet. Thereafter, the node may forward the packet with the attached label and segment ID to another node via a label switched path (LSP).
US10270661B2	Passive SAN discovery A method, system, and computer program product for managing a storage area network (SAN) comprising determining a plurality of resources within a SAN, the SAN comprising at least one or more host, a fabric and at least one or more arrays, wherein the at least one or more arrays further comprises a storage, determining a passive resource in the SAN, the passive resource identified from the plurality of resources comprising active resources and passive resources in the SAN, and displaying to a user virtual information of the SAN, wherein the virtual information includes the passive resource and attributes associated with the passive resource.
US10270660B2	Function virtualization for multimedia network topology adaptation A network architecture includes a gateway that terminates broadband service at a particular location, e.g., at the entry to a house or business. The gateway may execute a MoCA network controller (NC) that manages a network of MoCA nodes connected by cable connections. The gateway distributes content to the MoCA nodes on the network, using a logical star topology over the physical tree topology connections. The NC allocates greater downlink (gateway to MoCA node) bandwidth compared to uplink (node to gateway) bandwidth. Because the gateway terminates the broadband service, the network architecture frees very significant spectrum over the cable connections, permitting, for instance, the transmission of hundreds of Mbps of broadband content streams to the MoCA nodes.
US10270658B2	Zero touch configuration and synchronization of a service appliance in a network environment An example method for zero touch configuration and synchronization of a service appliance in a network environment includes receiving, at an appliance port on a service appliance, an indication that a switch port on a switch changed from an inactive status to an active status, the appliance port being connected over a network to the switch port, starting a bootstrap protocol, including by receiving at the service appliance from the switch, a bootstrap message from a service executing in the switch, creating, by the service appliance, an empty port channel at the service appliance, adding, by the service appliance, the appliance port to the port channel, and associating, by the service appliance, the service to the port channel in a cache.
US10270652B2	Network management A system and method for network management are described herein. The system includes a number of servers and a first network coupling the servers to each other and configured to connect the servers to one or more client computing devices. The system also includes a second network coupling the servers to each other, wherein data transferred between the servers is transferred though the second network. Network management requests for configuring the second network are communicated to the servers through the first network.
US10270650B2	Data defined infrastructure A system for managing the operation of different components within a cloud system to accomplish various tasks, including the implementation of build features within the cloud system to achieve specific operational goals. The system may include a data defined infrastructure (DDI) tool installed within a data defined infrastructure (DDI) to manage certain features or tasks within the cloud system. The DDI may include an environment configuration database (ECDB), an orchestration engine, an automation engine, and/or other hardware and software components within the cloud system, such that the DDI tool installed on the DDI infrastructure may control operation of the ECDB, the orchestration engine, the automation engine, or other hardware and software components within the cloud system based on a set of data that fully describes the operational goal.
US10270648B2	Configuration information management method, device, network element management system and storage medium A method for managing configuration information is disclosed including: an operation support system (OSS)/network management system/(NMS) receiving a lifecycle operation completion message of a virtualized network function (VNF); and sending a management information object instance operation request message corresponding to a lifecycle operation of the VNF to an element management system (EMS) according to the received lifecycle operation completion message of the VNF. A method and device for managing configuration information, an element management system (EMS) and a storage medium are also disclosed.
US10270644B1	Framework for intelligent automated operations for network, service and customer experience management A device may receive an alarm from a network and determine whether to process the alarm using a robotic process automation (RPA) engine or a machine learning automation (MLA) engine. Based on the determination, the device may selectively cause the alarm to be processed by the RPA engine or the MLA engine. The device may receive data associated with a network performance indicator and may provide the data to the MLA engine. The MLA engine may use a machine learning model to assign a score to the data and may determine whether to generate a trouble ticket based on the score.
US10270638B2	Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals A method and an apparatus for transmitting broadcast signals thereof are disclosed. The method for transmitting broadcast signals, the method comprises encoding service data, encoding signaling data, MIMO (Multiple-Input and Multiple-Output) precoding the encoded service data, building at least one signal frame including the MIMO precoded service data and the encoded signaling data, modulating data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and transmitting the broadcast signals having the modulated data.
US10270637B2	Communication system with PAPR management using noise-bearing subcarriers A communication system (20) includes a base station (22) and a number of peak-managed user equipment apparatuses (26) that simultaneously transmit peak-reduced FDMA communication signals (128) to the base station (22). The communication system (20) exclusively assigns payload subcarriers (44) to the apparatuses (26) and assigns a few noise-bearing subcarriers (48) for common simultaneous use by all apparatuses (26). Each user equipment apparatus (26) includes a peak reduction section (92) that distorts an otherwise undistorted modulated communication signal (86) into a distorted, peak-reduced communication signal (128) by generating and adding peak-reduction noise (131) to the undistorted signal (86). The peak-reduction noise (131) is primarily mapped onto the noise-bearing subcarriers (48) without conforming to an in-band noise constraint and may be mapped onto the assigned payload subcarriers (44) to the extent permitted by an in-band noise constraint. The peak-reduction noise (131) is blocked in unassigned payload subcarriers (46).
US10270636B2	Wireless communication apparatus, integrated circuit, transmission method, reception method, and communication method In some embodiments, a wireless communication apparatus may include, but is not limited to, a pilot inserter, a segment divider, a phase rotator, and a first adder. The pilot inserter inserts first and second pilot symbols into a symbol stream. The segment divider divides into a plurality of segments a plurality of subcarriers. Each of the subcarriers is allocated with a respective one of the symbols included in the symbol stream into which the first and second pilot symbols have been inserted. The phase rotator performs, for each segment, a phase rotation to all of the symbols, except for a predetermined one of the first and second pilot symbols, included in the symbol stream. The first adder adds together signals corresponding to the subcarriers included in the plurality of segments to which the phase rotation has been performed by the phase rotator to generate a transmission signal.
US10270634B2	Signal transmission apparatus and multicarrier communication system A signal transmission apparatus includes: a first receiving unit to receive a probe signal transmitted by transmitting end; wherein, the signal is generated based on a recommended signal configuration from previous signal to noise ratio (SNR) probings; a first processing unit to probe a channel SNR according to the signal; a first determining unit to determine transmission signal configuration and signal transmission performance of a final channel SNR obtained by multiple SNR probings; and a first transmitting unit to transmit the configuration and the performance to the transmitting end, where the transmitting end transmits an actual transmission signal according to the configuration and the performance.
US10270633B2	Phase measuring device and apparatuses using the phase measuring device The inventive phase measuring device includes a first A/D converter 2 that digitizes a first periodical input signal X at each predetermined sampling timing and outputs the resultant signal as a digital signal Xd, a first zero-crossing identification means operable to detect a sign of Xd, a counting processing unit 4 that counts a difference in the number of times of zero-crossing detection by the first zero-crossing identification means and calculates the difference at each sampling timing, and a fraction processing unit 5 that computes a fraction of the number of times of zero-crossing detection on the basis of Xd at sampling timings immediately before and immediately after determination of zero-crossing by the first zero-crossing identification means. An averaging processing unit 6 performs averaging by adding up and totalizing the outputs from the counting processing unit 4 and the fraction processing unit 5, thereby computing a phase. The inventive device thus implements a digital phase measuring device and a digital phase difference measuring device that allow input of periodical signals in a wide frequency range and that are capable of accurate and real-time measurement.
US10270631B2	Transmission apparatus, reception apparatus and digital radio communication method A transmission apparatus and method include modulating a transmission signal using a first modulation scheme selected from a plurality of modulation schemes to generate a first symbol sequence. A second symbol, generated using a phase shift keying (PSK) modulation scheme, is inserted in the first symbol sequence to generate a first modulation signal for transmission. A second modulation signal is received that includes a third symbol generated using a PSK modulation scheme and inserted in a second symbol sequence generated using a second modulation scheme selected from the plurality of modulation schemes. The third symbol is extracted from the received modulation signal. A transmission path associated with the received modulation signal is estimated using the third symbol. A received data signal from the second symbol sequence included in the received modulation signal is output using the estimated transmission path.
US10270629B2	Wireless relay device, processing apparatus, wireless communication system, and wireless communication method A wireless relay device for relaying packets via a wireless network includes an aggregator and a transfer controller. The aggregator is configured to aggregate a plurality of sets of data respectively included in a plurality of first packets transmitted from a plurality of wireless devices in the wireless network and under the wireless relay device to generate a second packet. The plurality of first packets is addressed to the wireless relay device. The transfer controller is configured to transfer the second packet to a transfer destination.
US10270625B2	Hardware virtualization for mean and variance estimations of QAM symbols Receivers including estimation unit (EU) circuits and related processing techniques for wireless systems are provided. Efficient expressions for quadrature amplitude modulation (QAM) symbol mean and variance calculations are utilized with efficient expressions and implementations that are adaptive to different orders of QAM formats. An EU circuit includes a mean estimation unit (MEU) circuit and/or second moment estimation unit (SEU) circuit. Each estimation unit circuit is configured to receive a variable QAM normalization factor so that the circuit can be adapted to different QAM orders. Each MEU or SEU circuit can be configured for sequential and/or parallel processing. A pool including multiple MEU circuits and/or a pool including multiple SEU circuits is provided in one embodiment, with a control unit for configuring and reconfiguring the pools of circuits for mean and variance estimation for data streams of QAM symbols.
US10270624B2	Channel estimation method and apparatus for use in wireless communication system A channel estimation method includes receiving signals at Resource Elements (REs) designated for reference signals, converting the received signals to time-domain entries using a matched filter, organizing the entries output from the matched filter into groups by delay, determining whether an energy sum of the entries of each group is greater than a predetermined threshold, and selecting the entries belonging to the group of which the energy sum is greater than the threshold value into a candidate group for channel estimation.
US10270614B2	Method and device for controlling timed task A method and a device for controlling a timed task are provided. The method applied in a first apparatus includes: receiving the timed task, wherein the timed task carries an execution time of the timed task; and sending the timed task to a second apparatus before the execution time of the timed task. The method applied in a second apparatus includes: receiving a timed task sent by a first apparatus; and executing the timed task in response to the execution time.
US10270613B2	Layout creation method and light position registration system Provided is a layout creation method for creating a layout of apparatuses disposed in a space (such as lighting devices, air conditioners, and switches). The layout creation method includes: obtaining reference coordinates through a portable terminal having a position sensing function; and for each of the apparatuses, obtaining position coordinates corresponding to the apparatus as coordinates relative to the reference coordinates through the portable terminal, and storing the position coordinates on the portable terminal in association with a type of the apparatus.
US10270608B2	Method for managing alerts relating to the detection of a local phenomenon A method for managing alerts relating to the detection of a local phenomenon in a communications network. The communications network includes at least one first residential gateway capable of transmitting alert messages in the network. The local phenomenon is likely to degrade the hardware and/or software resources of the residential gateway. The method includes: detection, by the first residential gateway, of a degradation linked to the local phenomenon; transmission of an alert message in the network by the first residential home gateway, in order for at least one second residential gateway able to receive the alert message, adjacent to the first residential gateway in the wide area network, to respond to the local phenomenon.
US10270607B2	Method and system for roamed client device handling A non-transitory computer readable medium that includes instructions which, when executed by one or more hardware processors, causes performance of operations. The operations include receiving, at a first network device in a first network, a multicast message comprising data to be transmitted at least to two or more client devices that have roamed from the first network to a same second network, determining that at least one client device has roamed from the first network to the second network, and responsive at least to the determining operation, forwarding, by the first network device to a second network device in the second network, a single copy of the data for distribution to each of the two or more client devices.
US10270601B2	Providing forward secrecy in a terminating SSL/TLS connection proxy using ephemeral Diffie-Hellman key exchange An infrastructure delivery platform provides a proxy service as an enhancement to the TLS/SSL protocol to off-load to an external server the generation of a digital signature, the digital signature being generated using a private key that would otherwise have to be maintained on a terminating server. Using this service, instead of digitally signing (using the private key) “locally,” the terminating server proxies given public portions of ephemeral key exchange material to the external server and receives, in response, a signature validating the terminating server is authorized to continue with the key exchange. In this manner, a private key used to generate the digital signature (or, more generally, to facilitate the key exchange) does not need to be stored in association with the terminating server. Rather, that private key is stored only at the external server, and there is no requirement for the pre-master secret to travel (on the wire).
US10270598B2	Secure elliptic curve cryptography instructions A processor of an aspect includes a decode unit to decode an elliptic curve cryptography (ECC) point-multiplication with obfuscated input information instruction. The ECC point-multiplication with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for an ECC point-multiplication operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the ECC point-multiplication with obfuscated input information instruction, is to store an ECC point-multiplication result in a destination storage location that is to be indicated by the ECC point-multiplication with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.
US10270593B2	Managing security in a computing environment In response to at least one message received by a processor of a gateway server from a user device wherein each message requests that an encryption key be downloaded to the user device, the processor generates at least one unique encryption key for each message and sends the at least one generated encryption key to the user device, but does not store any of the generated encryption keys in the cloud. For each encryption key having been sent to the user device, the processor receives each encryption key returned from the user device. For each encryption key received from the user device, the processor stores each received encryption key in the cloud.
US10270592B1	Systems and methods for encryption and provision of information security using platform services Systems and methods for securing or encrypting data or other information arising from a user's interaction with software and/or hardware, resulting in transformation of original data into ciphertext. Generally, the ciphertext is generated using context-based keys that depend on the environment in which the original data originated and/or was accessed. The ciphertext can be stored in a user's storage device or in an enterprise database (e.g., at-rest encryption) or shared with other users (e.g., cryptographic communication). The system generally allows for secure federation across organizations, including mechanisms to ensure that the system itself and any other actor with pervasive access to the network cannot compromise the confidentially of the protected data.
US10270591B2	Remotely managed trusted execution environment for digital-rights management in a distributed network with thin clients A method is performed at a client device distinct from an application server. In the method, a first key is stored in a secure store of the client device. A wrapped second key is received from the application server. The first key is retrieved from the secure store and used to unwrap the second key. Encrypted media content is received from the application server, decrypted using the unwrapped second key, and decoded for playback.
US10270590B2	Process efficient preprocessing for any encryption standard A pre-encryption process for symmetric encryption processes that inputs a bit stream into any existing or future encryption standard to increase encryption complexity with a disproportionate increase in processing time. The first encoding step is the two-stage generation of two strong keys based on a seed strong crypto key and known information from the Source Data bit stream. The second step is to split and encode the bit stream based on entropy levels. After entropy coding, the aligned bit streams are multiplexed in a cyclic fashion to generate one resulting bit stream. The third step is to slice the resulting bit stream into blocks, encrypting each block and adding each block to a coded output bit stream. Each new strong crypto key is derived from the previous crypto key and the previous pre-processed bit stream data. The decoding process is provided that is a simplified inverse of the encoding process.
US10270589B2	Flexible architecture and instruction for advanced encryption standard (AES) A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
US10270582B2	Duplexer having improved reflectivity A duplexer and a quadplexer are disclosed. In an embodiment, the duplexer includes an antenna terminal and two sub-paths including a transmit path and a receive path, the two sub-paths being connected to the antenna terminal, wherein the transmit path includes serially interconnected series resonators and, in parallel therewith, n parallel paths connected to ground, wherein each parallel path includes one parallel resonator or a cascade of serially interconnected parallel resonators, wherein n is an integral number with 0
US10270578B2	Search space for non-interleaved R-PDDCH The present invention relates to providing control information within a search space for blind decoding in a multi-carrier communication system. In particular, the control information is carried within a sub-frame of the communication system, the sub-frame including a plurality of control channel elements. The control channel elements may be aggregated into candidates for blind decoding. The number of control channel elements in a candidate is called aggregation level. In accordance with the present invention, the candidates of lower aggregation levels are localized, meaning that the control channel elements of one candidate are located adjacently to each other in the frequency domain. Some candidates of the higher aggregation level(s) are distributed in the frequency.
US10270576B2	Information transmission method, user equipment, and base station The present invention discloses an information transmission method, user equipment, and a base station. The method includes: receiving indication information sent by a base station, where the indication information is used to indicate a first downlink subframe in which a cell-specific reference signal (CRS) is transmitted; determining the first downlink subframe according to the indication information; and performing information transmission according to the first downlink subframe. According to the information transmission method, the user equipment, and the base station of embodiments of the present invention, indication information is used to indicate a downlink subframe in which a cell-specific reference signal is transmitted.
US10270575B2	Method and apparatus for supporting network listening in wireless communication system A method and apparatus for supporting a network listening in a wireless communication system is provided. A user equipment (UE) receives a subframe configuration used for the network listening, and monitors subframes indicated as subframes used for radio interface based synchronization (RIBS) by the received subframe configuration.
US10270573B2	Techniques and apparatuses for reusing remaining minimum system information configuration bits to signal a synchronization signal block location Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a first synchronization signal (SS) block that does not include remaining minimum system information (RMSI). The first SS block may indicate an offset for obtaining a second SS block that includes RMSI. The UE may determine a location of the second SS block based at least in part on the offset. Numerous other aspects are provided.
US10270572B2	Apparatus and methods for wireless channel sounding A technique of operating a wireless communication device includes receiving an assigned starting point index and an assigned reference signal bandwidth for a reference signal. The reference signal is then transmitted multiple times, beginning at an initial resource block that is associated with the assigned starting point index and in accordance with the assigned reference signal bandwidth, across a shared channel.
US10270570B2	System and method for SRS switching, transmission, and enhancements User Equipments (UEs) may be assigned a set of aggregated component carriers for downlink carrier aggregation and/or carrier selection. Some UEs may be incapable of transmitting uplink signals over all component carriers in their assigned set of aggregated component carriers. In such scenarios, a UE may need to perform SRS switching in order to transmit SRS symbols over all of the component carriers. Embodiments of this disclosure provide various techniques for facilitating SRS switching. For example, a radio resource control (RRC) message may be used to signal a periodic SRS configuration parameter. As another example, a downlink control indication (DCI) message may be used to signal an aperiodic SRS configuration parameter. Many other examples are also provided.
US10270568B2	Transmitter and method for transmitting data block in wireless communication system Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.
US10270564B2	System and method for multi-layer protocol selection A system and method for transmitting data is provided. An embodiment comprises a dynamic determination of ARQ and HARQ protocols in order to achieve a wider range of Quality of Service guarantees. The ARQ and HARQ protocols can be selected base on Quality of Service requirements of packets and the capabilities of the piece of user equipment.
US10270563B2	Method and network node for allocating resources of an uplink subframe It is presented a method of allocating resources of a first uplink subframe being part of a radio frame, each resource being a combination of a frequency range, and a time slot and a code. The method is performed in a network node and comprises: determining a first set of resources allocated for Hybrid Automatic Repeat Request, HARQ, feedback in the first uplink subframe; determining a second set of resources allocated for HARQ feedback in a second uplink subframe being part of the radio frame; identifying free resources in the first uplink subframe by identifying resources of the second set of resources which have no correspondence in the first set of resources; and allocating when a free resource is found, at least part of the free resources to a use other than HARQ feedback. A corresponding network node is also presented.
US10270560B2	Communication device and retransmission control method An object of the present invention is to increase speed of retransmission. A communication device has a transmission unit, a reception unit, a comparison unit, and a retransmission control unit. The transmission unit transmits first data toward a communication party. The reception unit receives second data as the first data received and returned by the communication party. The comparison unit is a process unit in a data link layer and compares the transmitted first data with the received second data. The retransmission control unit is a process unit in the data link layer and, when the transmission first data and the received second data do not match as a result of the comparison by the comparison unit, controls retransmission of the first data.
US10270559B2	Single encoder and decoder for forward error correction coding Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.
US10270555B2	Optical beamforming A beamforming device for a phased array antenna, comprising: a laser light source (2) arranged to provide an optical spectrum comprising a plurality of spaced wavelengths, and a distribution unit (4) configured to distribute one or more of the plurality of spaced wavelengths onto a plurality of optical paths (6). A wavelength selection device (8) configured to receive the plurality of spaced wavelengths on each of the plurality of optical paths. One or more phase shift unit (12) connected to a said wavelength selection device, wherein the phase shift unit is configured to introduce a phase shift to a received wavelength. The wavelength selection device on each optical path is configured to selectively transmit a wavelength to the phase shift unit. The wavelength selection device is configured to receive the said phase shifted wavelength from the phase shift unit (12). The beamforming device further comprising a heterodyning device (16) configured to generate a signal for transmission by an element of the phased array antenna, wherein the heterodyning device is configured to heterodyne a plurality of selected spectral components of the spaced wavelengths of the laser light source.
US10270554B2	Optical power measurement in a passive optical network A device and method for optical power measurement in an optical network supporting upstream and downstream signal propagation along an optical transmission path. The device includes an upstream wavelength analyzer receiving upstream light extracted from the optical transmission path and configured to determine an upstream spectral characteristic of the extracted upstream light. The device also includes a downstream filter assembly receiving downstream light extracted from the optical transmission path and configured to spectrally split the extracted downstream light into a plurality of downstream signals, one of which corresponding to a downstream signal of interest. The device further includes a processing unit configured to identify, based on the upstream spectral characteristic, the downstream signal of interest among the downstream filtered signals, and a downstream optical power meter assembly coupled to the downstream filter assembly and configured to measure an optical power parameter of the downstream signal of interest.
US10270552B1	Sports information gathering and broadcasting system Systems and methods of gathering, processing, and distributing information of a sporting event over a wireless network covering the sporting event, including a first portable device carried by a spotter of the sporting event to acquire global positioning system (GPS) data corresponding to the first portable device, to receive input data regarding status of the sporting event from the spotter, and to transmit the GPS and input data over the network, and a second portable device carried by a patron of the sporting event to receive the transmitted data, and to selectively display graphical representations of the transmitted data according to an input from the patron.
US10270547B2	Method and apparatus for sinusoid detection A system and method for detection of complex sinusoidal signals. The method can include obtaining a set of complex-valued samples of one or more signals, in the presence of unknown noise, using a plurality of sensors. The presence of κ candidate complex sinusoids can be assumed. Then, κ candidate complex sinusoids in the set of complex-valued samples can be estimated. The method can include comparing a measurement of the energy of the κ estimated candidate complex sinusoids with a threshold value. Based on the comparison, a determination can be made whether to assume a different number of candidate complex sinusoids and repeat the estimation and the comparison steps, or to specify the estimated κ candidate complex sinusoids as detected complex sinusoids. The threshold value can be determined using a penalty value which reduces the probability of overestimating the number of complex sinusoids.
US10270542B2	Sending known data to support fast convergence Methods and systems for fast convergence. One embodiment includes the following steps: extracting a digital representation of a common mode signal of a received differential signal sent by a transceiver, and generating, by a fast-adaptive mode-conversion canceller (FA-MCC), a compensation signal to mitigate differential interference; feeding the received differential signal to at least one of the following: a digital equalizer, and a digital canceller (DEDC); wherein the FA-MCC and the DEDC feed a slicer; responsive to receiving an indication that a serious differential interference has occurred, indicating the transceiver to transmit known data; and utilizing the received known data for improving the accuracy of the slicer's errors, which enables rapid adaptation of the FA-MCC to a level that mitigates the serious differential interference and enables requesting retransmission of erred packets fast enough to maintain a fixed rate of data transmission over a 2-millisecond window.
US10270541B2	Optical link management The present disclosure provides optical link management in a marine seismic environment. A first device can transmit, to a second device, a first optical transmission at a first output level. The first optical transmission can include a first packet corresponding to a network protocol. The first device can determine that the second device failed to receive the first packet via the first optical transmission. The first device can transmit, responsive to failure of the first optical transmission, a second optical transmission at a second output level different than the first output level. The second optical transmission can include a second packet corresponding to the network protocol. The first device can identify that the second packet was successfully received by the second link manager agent. The first device can establish, responsive to the identification that the second packet was successfully received, the second output level as a transmission output level for the first device.
US10270540B2	Communications system An underwater communications system is provided that transmits electromagnetic and/or magnetic signals to a remote receiver. The transmitter includes a data input. A digital data compressor compresses data to be transmitted. A modulator modulates compressed data onto a carrier signal. An electrically insulated, magnetic coupled antenna transmits the compressed, modulated signals. The receiver that has an electrically insulated, magnetic coupled antenna for receiving a compressed, modulated signal. A demodulator is provided for demodulating the signal to reveal compressed data. A de-compressor de-compresses the data. An appropriate human interface is provided to present transmitted data into text/audio/visible form. Similarly, the transmit system comprises appropriate audio/visual/text entry mechanisms.
US10270536B2	Phase-sensitive regeneration without a phase-locked loop using brillouin amplification Methods, systems, and apparatus for phase-sensitive regeneration of a signal without a phase-locked loop and using Brillouin amplification. The system for phase-sensitive regeneration includes a data channel, one or more pumps and a mixing stage. The one or more pumps are coupled with the data channel. The mixing stage is coupled with the data channel and is for processing a data signal that is combined with an output of the one or more pumps and idler or higher harmonic. The mixing stage is configured to amplify the idler or higher harmonic using Brillouin amplification in a Brillouin gain medium to keep the one or more pumps and the data channel phase-locked.
US10270534B2	Method and transmitter device for creating an optical transmit signal A method for creating an optical transmit signal includes creating an electrical discrete multi-tone signal according to digital input data carrying the information to be transmitted, the discrete multi-tone signal having a plurality of electrical partial signals, each electrical partial signal defining a sub-channel. Each electrical partial signal includes a sub-carrier at a predetermined sub-carrier frequency which is modulated according to a dedicated modulation scheme, so that a dedicated portion of the digital input data is included in each sub-channel. The method includes creating an optical signal by using the electrical discrete multi-tone signal as modulating signal for amplitude-modulating the intensity of an optical carrier signal. The method further includes bandpass-filtering the optical signal in order to create an optical single sideband or vestigial sideband transmit signal. An optical transmitter device for creating such an optical transmit signal and to an optical transmitter and receiver device includes a respective optical transmitter device.
US10270530B2	Wireless communications system and wireless radio frequency apparatus A wireless communications system includes a BBU, an optical multiplexer, M (greater than or equal to 2) first optical transceivers, and a wireless radio frequency apparatus, where the M first optical transceivers are provided between the BBU and the optical multiplexer, operating wavelengths of the M first optical transceivers are different from each other. The wireless radio frequency apparatus includes M RRUs, M second optical transceivers separately corresponding to the M first optical transceivers, and at least one optical splitter, where the M second optical transceivers are separately connected to the M RRUs, and an operating wavelength of a first optical transceiver matches an operating wavelength of a corresponding second optical transceiver. The M second optical transceivers are connected to a same optical fiber by the at least one optical splitter, and the optical fiber is connected to the optical multiplexer and one of the at least one optical splitter.
US10270524B2	Broadband satellite payload architecture A spacecraft includes a payload subsystem, the payload subsystem including a phased array of feed elements configured to illuminate an antenna reflector, a beam forming network (BFN) disposed proximate to the array of feed elements, and a plurality of power amplifiers disposed between the BFN and the array of feed elements. The BFN includes a plurality of variable amplitude and phase adjusting arrangements disposed between (i) m:1 power combiners that are communicatively coupled with the power amplifiers and (ii) at least one 1:n power splitter, where m is greater than 1, and n is greater than 2.
US10270523B2	Satellite terminal system with wireless link A satellite system may have a constellation of communications satellites. Satellite terminal equipment may be used to communicate with the satellite constellation. The satellite terminal equipment may have indoor and outdoor equipment that can communicate wirelessly. Power may be conveyed wirelessly between the indoor equipment and the outdoor equipment. The indoor equipment may include communications circuitry for supporting communications with electronic devices. The outdoor equipment may include satellite communications circuitry. The satellite communications circuitry may include antennas, satellite transceiver circuitry, and modems. Wireless communications between the indoor and outdoor equipment may be supported using radio-frequency wireless communications circuits or optical communications circuits.
US10270520B2	Joint transmitter signal processing in multi-beam satellite systems A, method and apparatus for wirelessly transmitting data to a plurality of terminals in each of a plurality of beams through a plurality of transmit feeds includes selecting, for each beam, two or more terminals among the plurality of terminals in the beam as a subgroup of terminals, on the basis of channel state information of the plurality of terminals; determining, for each beam, equivalent channel state information representing the subgroup of terminals in the beam on the basis of the channel state information of the terminals of at least one of the plural subgroups of terminals; and determining a set of weight coefficients that relate the plurality of transmit feeds to a plurality of signals that are intended for transmission in the plurality of beams on the basis of the equivalent channel state information representing the plural subgroups of terminals. Also disclosed is a method and apparatus for receiving data transmitted via wireless transmission to a plurality of beams through a plurality of transmit feeds and estimating a channel on the basis of the received data. The present disclosure is advantageously applicable to satellite communication systems.
US10270519B2	Air-to-ground co-channel interference avoidance system Techniques to reduce scheduling grants to minimize or eliminate the use of control channels, at the expense of flexibility, allow protection of the system from unnecessary retransmissions in case of interference from the primary system. Use of a single grant to allocate a set of resources across all carriers, or communication channels simplifies the system at the cost of retransmission of a grant for all carriers in the case if interference corrupts the transmission of a subset of the carriers. Thus, complementing a single grant embodiment with detection of the affected frequency carriers or victim carriers and remove such carriers from the carrier aggregation configuration allows more efficient use of the allocated spectrum.
US10270518B2	Method and apparatus for cooperative wireless communications Methods and wireless devices are described. A method includes a wireless device transmitting to wireless transmit/receive units (WTRUs) by being scheduled by the base station or using a pool of radio resources, which is for any of a plurality of wireless devices to use for transmission to WTRUs. On a condition that the wireless device is to be scheduled by the base station, the wireless device receives scheduling information for transmission to a WTRU having a group radio network terminal identifier (RNTI) and transmits to the WTRU in response to the received scheduling information. The scheduling information for transmission to the base station uses a different RNTI. On a condition that the wireless device is to use the pool of radio resources for transmission to a WTRU, the wireless device transmits to the WTRU without being scheduled by the base station using the pool of radio resources.
US10270516B2	Timing a random access UE to relay AP The embodiments disclose a method in a relay AP for timing a random access of a UE to the relay AP in a TDD radio communication network. The relay AP performs a self-backhaul over a backhaul link to a donor AP. The backhaul link and the random access link between the relay AP and the UE share a same frequency resource. The method comprises obtaining a first propagation delay information from the donor AP to the relay AP over the backhaul link; determining a timing advance offset for the UE to perform the random access at least based on the first propagation delay information; and transmitting the timing advance offset to the UE.
US10270506B2	System and method for widely-spaced coherent transmit arraying using a remote receiver A system and method for operating a communications or radar system wherein the system is a closed-loop coherent transmit array consisting of a plurality of antenna elements that may be widely-spaced, many wavelengths apart, an array control system, and a remote receiver that can feedback a measure of the transmit performance, and is a cooperative receiver, a bent-pipe, or a reflector. The method involves generation of weights which are applied to the array transmit signals based on feed-back data from a remote receiver compensating for at least one: circuit, propagation, and polarization phase errors. The method correlates feedback performance changes with transmit weight perturbations, enabling maximization of transmitted power delivered to the remote receiver. The method further involves an optimization control process that can be coordinated, with systematic weight perturbations and adjustment, or which can be operated asynchronously and autonomously, nevertheless achieving maximization of the received signal power.
US10270502B2	Precoding method, transmitting device, and receiving device A transmission scheme for transmitting a first modulated signal and a second modulated signal in the same frequency at the same time. According to the transmission scheme, a precoding weight multiplying unit multiplies a precoding weight by a baseband signal after a first mapping and a baseband signal after a second mapping and outputs the first modulated signal and the second modulated signal. In the precoding weight multiplying unit, precoding weights are regularly hopped.
US10270494B2	Parasitic circuit for device protection Exemplary embodiments are directed to a device include a parasitic coil for protection of the device. A device may include a first circuit configured to receive a first transmitted signal at an operational frequency. The device may also include a second circuit a second circuit configured to generate a field that opposes at least one of an undesirable portion of a wireless power field of the first transmitted signal and a portion of another wireless power field proximate the first circuit, the another wireless power field generated by a second transmitted signal at a non-operational frequency of the first circuit.
US10270493B2	Portable rechargeable transmitter In accordance with one aspect of the present disclosure, a method is provided for charging a movable barrier operator transmitter in a vehicle. The method includes connecting a transmitter and a component of the vehicle, transmitting an initiation signal from the transmitter to the component, and transmitting an inquiry signal from the component to the transmitter. The inquiry signal may include charging information. The method includes transmitting an answer signal from the transmitter to the component that includes information responsive to the charging information. The method further includes energizing a charging coil of the component to create an electromagnetic field and charge a battery of the transmitter.
US10270491B2	Power-line communication systems AMD methods having location-extendable collector for end-point data Power-line communication (PLC) systems collect information over power lines from end-point devices respectively associated with customer sites, for assessment by a central processing circuit operated on behalf of a power utility company. In the PLC system, each of a number of PLC data-collector circuits includes a plurality of data interface units and PLC end-point device data computation circuit. Typically, one data interface circuit is located proximate, and another is distal, the location of the computation circuit. Each data interface unit includes a transformer circuit for selectively receiving data from a subset of the end-point devices via the power lines, a transformer-coupling circuit for selectively sending data to the subset of the end-point devices via the power lines, and a high-throughput data driver circuit for outputting data in accordance with a data-transfer protocol which is common to the other high throughput driver circuits which operate in accordance with the data-transfer protocol.
US10270486B2	Ultra-low power receiver An ultra-low-power receiver includes a low-noise amplifier configured to receive an input analog signal and generate an amplified signal and a mixer electrically coupled to the low-noise amplifier. The mixer is configured to convert said amplified signal into an intermediate frequency signal. A progressively reduced intermediate frequency filter is configured to process the intermediate frequency signal from the mixer in discrete time.
US10270484B2	Sterilizable enclosure for securing a portable electronic device A sterilizable enclosure for securing a portable electronic device having a touchscreen and for preventing ingress and egress of contaminants to and from the secured device, comprising a frame with a frame periphery edge, the frame defining a window with a transparent panel adjacent the window arranged to abut the touchscreen. A base coupled to the frame comprises a base periphery edge and cooperates with the frame to define a closed position in which the device is secured between the base and the frame. A seal comprising a seal periphery edge is attached to at least one of the base and the frame and is arranged to be engaged between the base and the frame when the enclosure is closed to prevent ingress and egress of contaminants to and from the secured device with the seal periphery edge adjacent to the frame periphery edge and base periphery edge.
US10270480B1	Signal-tracking RF bandstop filter Systems and methods are provided for implementing bandstop filters (e.g., RF/microwave bandstop filters) that can automatically tune to a frequency of an interfering signal. Embodiments of the present disclosure provide automatically tunable signal-tracking bandstop filters with a significant reduction in response time, complexity, size, weight, and cost when compared to conventional devices.
US10270479B2	Signal processing device A signal processing device capable of performing a process of reducing peak power without interfering with a transmission signal at a high speed is provided. A signal processing device includes a peak-reduced signal generating device and a band pass filter. The peak-reduced signal generating device divides an input signal having an information component into signal streams for every predetermined number of signals, and generates peak-reduced signal with peak canceling signals on the basis of the signal streams. The peak-reduced signal generating device combines the signal streams which the peak-reduced signals on the basis of an order in which the division into the signal streams has been performed. The band pass filter passes a frequency component corresponding to the information component and rejects a frequency component corresponding to the peak canceling signal with respect to a signal based on a signal from the peak-reduced signal generating device.
US10270474B1	Partial concatenated coding system using algebraic code and LDPC code A partial concatenated coding system using an algebraic code and LDPC code is disclosed. The partial concatenated coding system includes an ECC encoder, a received codeword monitoring module and an ECC decoder. The ECC encoder has a LDPC code encoding module and an algebraic code encoding module. The ECC decoder has a LDPC code decoding module and an algebraic code decoding module. Comparing with conventional concatenating coding systems, the present invention has advantages of less spare spaces, better error-correcting performance, lower hardware complexity, better decoding throughput and fixable code length.
US10270471B2	Memory system having ECC self-checking function and associated method A memory system having an error correction codes (ECC) self-checking function is disclosed. The memory system includes: an ECC encoder, used to convert input information bits into a codeword; a memory, coupled to the ECC encoder, the memory being used to store the codeword; and an ECC decoder, coupled to the memory and the ECC encoder, the ECC decoder being used to generate a syndrome of the codeword; wherein when the memory system is operated in an on-line self-checking mode and the codeword is fed into the memory from the ECC encoder, the codeword is as well fed into the ECC decoder from the ECC encoder to generate the syndrome.
US10270468B2	Method for file updating and version control for linear erasure coded and network coded storage A method for use in a distributed storage system having a plurality of nodes, the method including receiving, at a source node, original data, encoding the original data into plurality of coded fragments using a linear code, transmitting at least a first one of the coded fragments from the source node to a first sink node. The method further includes receiving, at the source node, modified data, calculating, at the source node, a coded difference between the original data and the modified data, transmitting the coded difference from the source node to the first sink node; and recovering, at the first sink node, at least a first portion of the modified data using the coded difference and the at least a first one of the coded fragments.
US10270467B2	Transmitting apparatus and interleaving method thereof Provided is a signal interleaving method which includes: interleaving parity bits by encoding input bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups according to a specific permutation order to provide an interleaved codeword; de-multiplexing bits of the interleaved codeword to generate data cells; mapping the data cells onto constellation points for 1024-quadrature amplitude modulation (QAM); and transmitting a signal based on the constellation points.
US10270465B2	Data compression in storage clients Embodiments include method, systems and computer program products for data compression in storage clients. In some embodiments, a storage client for accessing a storage service from a computer program is provided. A compression method is provided in the storage client to reduce a size of data objects. A frequency of compressing data from the computer program or modifying a compression algorithm based on assessing costs and benefits of compressing the data is varied.
US10270462B2	Digital analog conversion circuit, data driver, display device, electronic apparatus and driving method of digital analog conversion circuit, driving method of data driver, and driving method of display device A digital to analog conversion circuit is disclosed. In one example, the conversion circuit includes a selector unit and a differential amplifier. The selector unit includes a selector unit that selects nodes from a voltage dividing circuit based upon bit information of a higher order side of an input digital signal and outputs voltages of the selected nodes. The differential amplifier includes differential pairs to which the output voltages of the selector unit are input. When a voltage corresponding to the digital signal is output, after a correspondence relationship between the output voltages of the selector unit and the inputs of the respective differential pairs of the differential amplifier is allowed to have a short settling time, and is then controlled in accordance with the bit information of the lower order side of the input digital signal.
US10270461B1	Non-uniform sampling implementation This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.
US10270459B2	DAC capacitor array, SAR analog-to-digital converter and method for reducing power consumption thereof The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.
US10270454B2	Method and system for clock and data recovery (CDR) A clock and data recovery (CDR) device is disclosed. The CDR device comprises a sensing unit and an interpolator. The sensing unit is configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge. Each of the thresholds is related to a different level among data levels of the data. The interpolator is configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.
US10270451B2	Low leakage ReRAM FPGA configuration cell A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
US10270445B2	Half-frequency command path A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.
US10270442B2	Memory component with on-die termination A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
US10270441B2	Calibration methods and circuits to calibrate drive current and termination impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
US10270438B2	Switch device with switch circuits that provide high voltage surge protection A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its bulk.
US10270432B2	Flip-flop with delineated layout for reduced footprint In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.
US10270426B2	Duplexer At least one of a transmission filter and a reception filter of a duplexer includes a piezoelectric substrate, an elastic wave filter electrode portion on the piezoelectric substrate and including ground terminals to be connected to a ground potential, a support layer provided on the piezoelectric substrate, a cover provided on the support layer to seal a cavity in the support layer, and via hole electrodes penetrating the support layer and the cover and including first and second ends. The ground terminals are commonly connected on the piezoelectric substrate, and the ground terminals are electrically connected to the respective first ends of the plurality of via hole electrodes. The second ends of the via hole electrodes are connected to the ground potential outside of the at least one of the transmission filter and the reception filter.
US10270421B2	Elastic wave device and method for manufacturing the same An elastic wave device includes a piezoelectric substrate, first to third IDT electrodes provided on the piezoelectric substrate, a dielectric film provided on the piezoelectric substrate and covering the first to third IDT electrodes, the thickness of the dielectric film in a first region in which the dielectric film covers the first IDT electrodes is different from the thickness of the dielectric film in a second region in which the dielectric film covers the second IDT electrodes and the thickness of the dielectric film in a third region in which the dielectric film covers the third IDT electrodes. The density equivalent thickness of each of the first IDT electrodes and the second IDT electrodes are equal to each other, and the density equivalent thickness of each of the third IDT electrodes is different from the density equivalent thickness of each of the first IDT electrodes and the second IDT electrodes.
US10270420B2	Surface elastic wave device comprising a single-crystal piezoelectric film and a crystalline substrate with low visoelastic coefficients A surface elastic wave device comprises a stack including: a thin film made of a piezoelectric first material; a substrate made from a second material; and exciting means for generating at least one surface acoustic wave propagation mode in the piezoelectric film; wherein: the first material is a single-crystal material and the second material is a crystalline material, the thickness of the thin film of piezoelectric first material being smaller than or equal to 20 μm, and the first material and the second material having viscoelastic coefficients lower than or equal to those of quartz for the propagation mode induced by the exciting means.
US10270418B2	Impedance matching method and impedance matching system An impedance matching device and an impedance matching method. A variable reactance impedance matching network is disposed between a variable frequency RF power source varying a driving frequency and a load. An impedance matching method of the variable reactance impedance matching network includes controlling variation amount of capacitance or reactance of a variable reactive component of the impedance matching network as a function of a difference between a target driving frequency ft and the driving frequency.
US10270416B2	Electronic filter circuit Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analog or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.
US10270414B2	Acoustic wave device An acoustic wave device includes: a support substrate; a piezoelectric substrate that is jointed on the support substrate; a plurality of acoustic wave elements that are provided on the piezoelectric substrate; and an interconnection line that is provided on the piezoelectric substrate and couples the plurality of acoustic wave elements, wherein: the piezoelectric substrate of a first area, on which the plurality of acoustic wave elements are provided, is remained; the piezoelectric substrate of a second area, on which the interconnection line is provided, is remained; the piezoelectric substrate of a third area is for cutting the support substrate; and the piezoelectric substrates of a fourth area is other than the first area, the second area and the third area, the fourth area having a fifth area in which at least a part of the piezoelectric substrate is removed.
US10270413B2	Advanced thermally compensated surface acoustic wave device and fabrication This disclosure relates to a method of fabrication of a surface acoustic wave device comprising the step (a) of providing a piezoelectric structure, the step (b) of providing a dielectric structure, wherein the step (b) comprises a step (b1) of metalizing the dielectric structure, and the method further comprising the step (c) of bonding the metalized dielectric structure to the piezoelectric structure.
US10270406B2	Power amplifier, semiconductor integrated circuit, and method of controlling the power amplifier A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.
US10270398B2	Low noise amplifier A low noise amplifier includes an amplifier transistor having a source, a gate, and a drain. An input node is coupled to the gate. An output node is coupled to the drain. An inductor is coupled between the gate and the drain.
US10270394B2	Automated envelope tracking system Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.
US10270389B2	Semiconductor device and method A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew.
US10270386B2	Photovolatic powered cathodic protection probe A remotely operated vehicle (ROV) compatible photovoltaic powered cathodic protection (CP) probe can measure voltage potential of subsea structures. In an embodiment, the CP's meter is integrated and able to send CP data topside. The CP meter's compact display module also houses the telemetry board to send CP readings, via an ROV serial, topside. The CP probe does not require a battery and can be used standalone or connected through an ROV to topside logging and display. Further, the CP probe can monitor a plurality of CP voltages and other conditions such as an electrical field gradient.
US10270384B2	Systems and methods for dual tilt, ballasted photovoltaic module racking Systems and methods for dual tilt, ballasted photovoltaic module racking are provided herein. Under one aspect, a system for supporting first and second photovoltaic modules can include first and second elongated stiffeners respectively configured to be coupled to and support the first and second photovoltaic modules. The system also can include first and second feet respectively configured to be coupled to first and second grooves respectively provided within first and second ballasts. The system also can include a first stiffener hinge rotatably coupling the first and second stiffeners to one another, a first foot hinge rotatably coupling the first foot to the first stiffener, and a second foot hinge rotatably coupling the second foot to the second stiffener. At least one of the first stiffener hinge and the first and second foot hinges can include a respective mechanical stop inhibiting rotation of that hinge beyond a respective predetermined angle.
US10270379B2	Method and apparatus for quasi-sensorless adaptive control of switched reluctance motor drives A method and apparatus for quasi-sensorless adaptive control of a high rotor pole switched-reluctance motor (HRSRM). The method comprises the steps of: applying a voltage pulse to an inactive phase winding and measuring current response in each inactive winding. Motor index pulses are used for speed calculation and to establish a time base. Slope of the current is continuously monitored which allows the shaft speed to be updated multiple times and to track any change in speed and fix the dwell angle based on the shaft speed. The apparatus for quasi-sensorless control of a high rotor pole switched-reluctance motor (HRSRM) comprises a switched-reluctance motor having a stator and a rotor, a three-phase inverter controlled by a processor connected to the switched-reluctance motor, a load and a converter.
US10270376B2	Fan driving circuit A fan driving circuit includes a processing module providing a fan phase signal and a speed signal providing module electrically connected to the processing module and including a first switch having a first terminal, a second terminal receiving the fan phase signal and a third terminal electrically connected to a ground voltage, a second switch having a first terminal electrically connected to a speed signal providing terminal of the fan driving circuit and a first terminal of a first impedance, a second terminal electrically connected to a second terminal of the first impedance and a terminal of a diode, and a third terminal electrically connected to the first terminal of the first switch, and a third switch having a terminal electrically connected to a bias voltage.
US10270374B2	Motor driving circuit, motor driving method, and motor utilizing the same A motor driving circuit, the motor itself, and a motor driving method are disclosed. The circuit includes a controllable bidirectional alternating current (AC) switch and a processing unit, a voltage polarity of the AC power source and zero voltage crossing point of an AC power source being detected, together with a magnetic pole position of a permanent-magnet rotor, to govern the operation of the AC switch. When the controllable bidirectional AC switch is to be switched on, a trigger pulse is output after a delay time after the zero voltage crossing point, such that a phase difference between a back electromotive force and current flowing through the stator winding is decreased.
US10270371B2	Vibrating-element driving circuit, vibration-type actuator, image pickup apparatus, image generation apparatus, and dust removal apparatus In a vibrating-element driving circuit including a transformer and a coil as elements for stepping up a voltage, an improvement in a circuit efficiency of the driving circuit is achieved. The vibrating-element driving circuit includes a transformer, and an inductor connected to a primary side of the transformer, wherein an alternating voltage is applied to a primary winding coil of the transformer, an electro-mechanical energy conversion element of the vibration-type actuator is connected in parallel to a secondary winding coil of the transformer, the inductor is connected in series to the primary winding coil of the transformer, and wherein when the inductance of the inductor is Le1, the inductance of the primary winding coil of the transformer is L1, and Ka=L1/Le1, then the following is satisfied: 1≤Ka≤10.
US10270368B2	Bi-directional, transformerless voltage system A multi-stage electric voltage converter is disclosed. The converter comprises a voltage source and multiple stages. Each stage of the multiple stages comprises a first and a second and a third switch, and a capacitor, wherein the capacitor is coupled to the voltage source by the first and the second switches and each stage is coupled to a different stage or to an output of the multi-stage electric voltage converter by the third switch so as to allow the capacitor to be charged by the voltage source when the first and the second switches are closed and the third switch is open, and to allow the capacitor to be connected to the output of the multi-stage electric voltage converter when the first and the second switches are open and the third switch is closed.
US10270367B2	Frequency converter with LCL line and common mode filter A filtering method and arrangement for a system comprising a regenerative frequency converter and a motor, which regenerative frequency converter has an intermediate DC circuit comprising positive and negative pole and which regenerative frequency converter is connected to a supplying 3-phase mains network via a line filter unit comprising in serial connection a first 3-phase inductor unit with mains side terminals and motor side terminals and a second 3-phase inductor unit, and a 3-phase capacitor unit which comprises phase-specific capacitors which are connected in star connection between the motor side terminals of the first 3-phase inductor unit and a star point, which star point is connected to ground via a fourth capacitor. The filtering arrangement further comprises a common mode inductor unit and a filtering capacitor unit. Filtering capacitor unit comprises two capacitors in serial connection between the poles of the intermediate DC circuit such that the common point of the capacitors is connected to the star point of the capacitor unit in the line filter unit. The filter arrangement is configured to determine the control pattern of the controllable power switches by using a 60° bus clamp modulation or a softened 60° bus clamp modulation.
US10270361B2	High speed synchronous rectifier A control circuit and method for a synchronous rectifier having a plurality of switches and receiving an AC input signal. The control method includes switching between controlling a first switch of the plurality of switches in response to a control signal for a second switch of the plurality of switches, controlling the first switch in response to a comparison between the AC input signal and a second signal.
US10270359B2	Multi-use driver circuits In some implementations, a device that powers a load includes a first terminal to couple with an alternating current (AC) power source, a second terminal to couple with the AC power source, and a full bridge rectifier arranged to receive power from the AC power source and provide direct current (DC) power between a positive node and a negative node. The device includes a first capacitor coupled in series between the full bridge rectifier and the first terminal or the second terminal, a load coupled between the positive node and negative node of the rectifier, and a second capacitor coupled between the positive node and negative node of the rectifier, in parallel with the load.
US10270358B2	Power electronics submodule having DC and AC voltage terminal elements, and assembly hereof A submodule and an assembly include a switching device having a substrate, and printed conductors arranged thereupon. The submodule incorporates a first and a second DC voltage printed conductor, to which a first and a second DC voltage terminal element are connected in an electrically conductive manner, and an AC voltage printed conductor, to which an AC voltage terminal element is connected in an electrically conductive manner. The submodule further comprises an insulating moulding, which encloses the switching device in a frame-type arrangement. The first DC voltage terminal element, by means of a first contact section, engages with a first supporting body of the insulating moulding, and the AC voltage terminal element, by means of a second contact section, engages with a second supporting body of the insulating moulding. To this end, a first clamping device is configured to project through a first recess in the first supporting body, in an electrically insulating manner, and to form an electrically-conductive clamping connection between the first DC voltage terminal element and an associated first DC voltage connecting element, and a second clamping device is configured to project through a second recess in the second supporting body, in an electrically insulating manner, and to form an electrically-conductive clamping connection between the AC voltage terminal element and an associated AC voltage connecting element.
US10270345B1	Method and apparatus for wide bandwidth, efficient power supply An efficient power supply with fast, wideband response has been disclosed. In one implementation, two switching regulators with different frequency responses are combined to provide wideband, efficient power.
US10270342B2	Error correction for average current sensing in a switching regulator Certain aspects of the present disclosure provide methods and apparatus for current sensing and error correction, or at least adjustment, for a switching regulator. One example current-sensing circuit generally includes a first amplifier, a buffer, a low-pass filter, a first switch coupled between an output of the first amplifier and an input of the buffer, a second switch coupled between the output of the first amplifier and an input of the low-pass filter, a third switch coupled between an output of the buffer and the input of the low-pass filter, and a fourth switch coupled between the input of the low-pass filter and a reference node for the circuit.
US10270336B2	Feedforward loop to stabilize current-mode switching converters A circuit includes a current sensor to sense a switching current flowing at input side of a switching DC-DC converter. An output capacitor filters an output voltage at an output side of the switching DC-DC converter. A feed-forward circuit passes a portion of the sensed switching current to a feedback path on the output side of the switching DC-DC converter simulating a changing effective series resistance (ESR) of the output capacitor to facilitate operating stability in the switching DC-DC converter.
US10270335B2	Switching converter and method for converting an input voltage into an output voltage A switching converter having an input for receiving an input voltage, an output for supplying an output voltage, and a converter device which includes an inductance, a capacitance, a diode and a switching device developed as a current source, for converting the input voltage into the output voltage.
US10270331B2	Power supply apparatus A power supply apparatus includes a boosting converter, an inrush current limiting element, a detection circuit, a switch element, and a control circuit. The inrush current limiting element is configured to limit an inrush current to the boosting converter. The detection circuit is configured to detect whether an output voltage of the boosting converter has reached a set voltage. The switch element is configured to short-circuit the inrush current limiting element. The control circuit is configured to operate the switch element according to the detection to short-circuit the inrush current limiting element.
US10270330B2	Predictive ripple-cancelling signal into error amplifier of switch mode power supply A predicted ripple in the feedback voltage of a switching converter is generated, based on the ripple over a certain number of recent switching cycles. The DC portion of the feedback voltage is filtered out. This predicted feedback voltage ripple is then added to a fixed reference voltage to create a compensated reference voltage. The compensated reference voltage is applied to the non-inverting input of an error amplifier, and the feedback voltage (having a DC component and ripple) is applied to the inverting input of the error amplifier. Thus, substantially the same ripple component is applied to both inputs and cancels out. Therefore, the output of the error amplifier is not affected by the ripple in the feedback voltage, and a non-rippling control voltage is generated by the error amplifier. As a result, the gain-bandwidth product of the converter can be increased for faster response to transients.
US10270327B1	Voltage sensor-less position detection in an active front end A controller may include a memory having computer-readable instructions stored therein; and a processor configured to execute the computer-readable instructions to generate Pulse Width Modulation (PWM) signals to control power switches of an Active Front End (AFE) inverter based on at least a synthesized grid voltage vector angle at a terminal of an alternating current (AC) grid without using physical voltage sensors at the terminal of the AC grid, and control the AFE inverter to supply power to a load based on the PWM signals.
US10270323B2	Low resistance generator A low resistance generator includes a series of stator plates and rotors. Stator plates include the coils wrapped around coil spools. The stator plates and coil spools are made from non-conductive and non-ferromagnetic material. The coils are exposed to the surrounding air and cooled convectively by airflow caused by a rotation of the rotors in the gaps. Rotors house magnets and are disposed within gaps between the stator plates. The rotors are also made of non-conductive and non-ferromagnetic materials. The magnets may be disposed on the rotors to form columns. Two columns of magnets are joined together to form one or more closed magnetic loops, each column being joined by a gauss bridge disposed at first and second end rotors.
US10270320B1	Motor grounding seal A shaft seal assembly is disclosed having a stator including a main body and axial and radial projections therefrom. The rotor may be radially extended to encompass the axial and radial projections from said stator. A passageway formed between the radial projection of stator and rotor results in an axial passageway having its opening facing rearwardly from the rotor and away from the source of impinging coolant and/or contaminant. A concentric circumferential receptor groove in the stator facing the housing allows insertion of a conductive insert for transmission of electrostatic charge away from the shaft through the shaft seal assembly to the housing and ground. The receptor groove is opposite the axial passageway and provides for both a substantially lower contaminant environment and improved engagement with the conductive insert.
US10270319B2	Dynamoelectric machine assemblies having memory for use by external devices A method is provided for storing data from an external device in a dynamoelectric machine assembly (i.e., an electric motor or generator). The dynamoelectric machine assembly includes a memory device and a processor for controlling operation of the dynamoelectric machine assembly in response to commands from an external device. The method includes receiving a command from the external device to store data in the memory device of the dynamoelectric machine assembly, and storing the data in the memory device in response to the command. Dynamoelectric machine assemblies, external devices and systems suitable for use in the provided method are also disclosed.
US10270318B2	Electric motor with rotor, circuit board and improved lead wire connection An electric motor includes: a rotating shaft; a rotor securely attached to the rotating shaft and including a cylindrical magnet portion; a stator formed in an annular shape on an outer peripheral side of the rotor; a board installed above the rotor and the stator with a predetermined air gap therefrom; and a lead wire connected to the board. A connecting portion of the board and the lead wire is formed at a position on an inner side of an axial projection plane of the magnet portion of the rotor above the board. In this electric motor, even when the rotor is increased in diameter, the connecting portion of the lead wire connected to the board can be prevented from being located proximate to an upper part of the magnet portion of the rotor.
US10270311B2	Superconducting electrical machine with two part rotor with center shaft capable of handling bending loads A superconducting electrical machine includes a rotor and a stator. The stator defines a cavity. The rotor is configured to rotate about a longitudinal axis. The rotor is disposed at least partially within the cavity. The rotor includes a shaft configured to rotate with the rotor, a rotor active section including at least a rotor torque tube and a superconductor, and a first re-entrant end attaching the shaft to the rotor active section. At most a threshold fraction of a bending force applied to the shaft is communicated to the rotor active section.
US10270306B2	Motor and rotor A motor includes a stator, a rotor, and a case. The stator includes a stator core and windings. The rotor is provided inside the stator. The rotor includes first and second rotor cores and a field magnet. The first and second rotor cores each includes a core base and claw-shaped magnetic poles. The core bases are opposed to each other and the claw-shaped magnetic poles of the first and second rotor cores are alternately disposed in a circumferential direction. The field magnet is disposed between the core bases in the axial direction. The field magnet is magnetized in the axial direction so as to cause the claw-shaped magnetic poles of the first rotor core and the second rotor core to function respectively as first magnetic poles and second magnetic poles. At least part of an end part of the case in the axial direction is made of a non-magnetic body.
US10270305B2	Motor-generator with multiple stator windings A motor-generator includes a stator disposed along a centerline including a stator pole, a first stator winding and a second stator winding, wherein the first stator winding is wound on the stator pole and the second stator winding is wound on the stator pole, and at least one rotor axially disposed from the stator along the centerline.
US10270304B2	Linear vibration motor A linear vibration motor is disclosed. The linear vibration motor includes a housing; a vibrating unit in the housing, the vibrating unit including a magnet; a plurality of elastic members suspending the vibrating unit elastically in the housing; a drive coil positioned opposed to the magnet for driving the vibrating unit to vibrate along a first direction; a Hall sensor fixed on the housing and facing the magnet for detecting displacement of the vibrating unit along a direction vertical to the first direction; and a braking coil arranged on the housing and surrounding the Hall sensor for reacting upon the vibrating unit in accordance with the displacement detected by the Hall sensor in order to adjust the displacement of the vibrating unit vertical to the first direction.
US10270302B2	Electric motor rotor and electric motor associated An electric motor rotor includes a substantially cylindrical body, which conducts a magnetic field, and defines at least one housing receiving a group of magnets that includes at least two permanent magnets. Two circumferentially adjacent magnets of the housing are separated from one another by an air knife.
US10270293B2	Wireless charger with resonator A wireless charger is disclosed that comprises a transmitter and a resonator connected to the transmitter and comprising a conductive path substantially located within a plane, wherein the conductive path is arranged to form at least two loops, said loops being arranged such that a current that flows in the conductive path flows around a first one of said loops in a first direction and around a second one of said loops in a second direction opposite the first direction.
US10270291B2	Wireless power receiver and method of manufacturing the same A wireless power receiver can include a magnetic substrate and a coil configured to wirelessly receive power. The coil can be formed as a conductive layer on the magnetic substrate. A connecting unit can be disposed in a receiving space of the magnetic substrate and can be connected to the coil unit.
US10270289B2	Polyphase inductive power transfer system with individual control of phases The present invention provides a polyphase inductive power transfer (IPT) system comprising a primary power supply comprising a plurality of primary conductors, the primary conductors being individually selectively operable to provide or receive a magnetic field for inductive power transfer; and at least one pick-up comprising one or more pick-up conductors, the one or more pick-up conductors each being individually selectively operable to magnetically couple with a primary conductor to control power transfer between the primary power supply and a load coupled or coupleable with the respective pick-up. The polyphase primary power supply may be used to power a plurality of single-phase pick-ups, one or more polyphase pick-ups, or a combination thereof. Also disclosed are polyphase primary and secondary converters for use in such a system.
US10270288B2	Hand tool case holding device A hand tool case holding device includes at least one charging coil, a case accommodating area and a holding device housing, which includes a first outer side facing toward the case accommodating area. The holding device housing includes at least one second outer side, (a) which, in at least one operating state, faces toward the case accommodating area, (b) which is aligned essentially perpendicularly to the first outer side, and (c) on which the charging coil is situated.
US10270286B2	LED smart control circuit and LED lighting device containing the same A light-emitting diode (LED) smart control circuit and the related LED lighting device are provided. The LED smart control circuit includes a microprocessor, a bridge rectifier, a transformer circuit, a power grid detection unit, a voltage detection unit, a battery charging controller, a first sampling circuit, a second sampling circuit, a constant current controller, and an external rechargeable battery. The LED smart control circuit is configured for controlling LED light source components to emit light. An LED lighting device includes the LED light source components, a smart control circuit board, a rechargeable battery, a shell, and a lamp head. The smart control circuit board is integrated with the disclosed LED smart control circuit.
US10270284B2	Semiconductor chip and solar system A semiconductor chip having four sides and being substantially formed in a rectangle, and including a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.
US10270282B2	Solar charger comprising a charging unit for charging a power battery to a high voltage, a photo-sensitive unit for detecting light intensity, a switch unit for regulating connection between the charging unit and the power battery, and a control unit for regulating the charging of the power battery based on a saturation level and the light intensity A solar charger for charging a power battery is provided, comprising: a photo-sensitive unit configured to detect light intensity; a charging unit configured to receive a voltage transformed from solar energy and to boost the voltage for charging the power battery; a switch unit coupled between the charging unit and the power battery and configured to disconnect the charging unit from the power battery or connect the charging unit with the power battery; and a control unit coupled to each of the photo-sensitive unit, the switch unit, and the charging unit, and configured to switch on the charging unit and the switch unit when the light intensity is higher than a first predetermined value to charge the power battery.
US10270281B1	In line manually actuated battery charger for tactical radio According to aspect, the subject matter described herein includes an in line manually actuated charging device for a tactical radio. The charging device includes a housing enclosing the charger for charging a battery of the tactical radio. A manual actuator is coupled to the housing for actuating the charger to charge the battery. A first mechanical connector is located on a first surface of the housing for detachably connecting to a battery connector of the tactical radio. The second mechanical connector is located on a second surface of the housing opposite a first surface for detachably connecting to the battery of the tactical radio. The first and second mechanical connectors are configured such that the housing fits in line between the tactical radio and the battery during use of the tactical radio.
US10270276B2	Wireless charging method and apparatus thereof An electronic device is provided. The electronic device includes a housing, a wireless charging coil disposed inside the housing, a fan disposed inside the housing and in proximity to the coil, a temperature sensor disposed inside the housing and in proximity to the coil, a wireless charging circuit having the coil and configured to transmit power wirelessly to an external device via the coil, and a control circuit electrically connected to the fan, the temperature sensor, and the wireless charging circuit. The control circuit may be configured to receive a signal from the external device, receive data related to a temperature of the coil from the temperature sensor, and control the fan at least partially on the basis of at least one of the signal and the data.
US10270275B2	Systems and methods for controlling energy storage systems having multiple battery types Systems and methods for controlling an energy storage system are provided. In particular data indicative of a load profile can be received. The load profile can specify one or more amounts of power to be delivered by an energy storage system over a duration. The energy storage system can include one or more energy storage elements of a first type and one or more energy storage elements of a second type. One or more time windows associated with high power events and one or more time windows associated with high energy events can then be determined based on the load profile. Power delivery by the energy storage elements of the first type and the energy storage elements of the second type can then be controlled based at least in part on the determined time windows.
US10270274B1	Active power management A method for security and/or automation systems is described. In one embodiment, the method may include receiving, at a power adapter, power from a power supply, routing a first portion of the power received from the power supply to the doorbell unit, and routing a second portion of the power received from the power supply to both the device of the doorbell unit and the doorbell chime when the doorbell button is being actuated. In some cases, the power adapter is wired, via doorbell wiring, to at least one of a doorbell chime, a doorbell unit, and the power supply. In one example, the first portion of power is routed to power a device of the doorbell unit when a doorbell button of the doorbell unit is not being actuated.
US10270265B2	Controlling batteries for electric bus An onboard charging system for an electric vehicle is configured to communicate with a power supply through exchange of control signals on a power supply line by modulating a charging current being supplied to the charging system. The charging system is capable of communicating fault and battery parameter data to the power supply, as well as a requested charging current used to regulate the power supply output. The power supply may convert high voltage AC power into a controllable DC output supplied directly to the electric vehicle, thereby providing a convenient means for the vehicle to initiate charging during operations. Connection between the electric vehicle and the power supply may be effected using an extendible and retractable electrical connection, such as a mechanical pantograph.
US10270264B2	Battery pack management apparatus selectively controlling battery cells Provided is a battery pack management apparatus that effectively improves the life of a battery pack. The battery pack management apparatus is an apparatus for managing a battery pack, in which a plurality of battery cells are electrically connected to each other, and includes: a measurement unit configured to measure the number of charging and discharging cycles of each of the plurality of battery cells; a selection unit configured to select at least some battery cells from among battery cells whose number of charging and discharging cycles measured by the measurement unit reached a reference number; and a blocking unit configured to stop operations of the at least some battery cells selected by the selection unit for a first reference time.
US10270263B2	System and method for charging a battery pack System and method for charging a battery pack. One system includes a battery pack with at least one battery cell, a memory, and a charging circuit configured to control a charging current from a charger to the battery pack. The battery pack also includes an electronic processor configured to control the charging circuit and to determine a type of charger to which the battery pack is connected. The electronic processor is further configured to determine, based on the type of charger, a disconnect time and to control the charging circuit to allow the charging current to charge the battery pack. The electronic processor is further configured to control the charging circuit to electrically disconnect the battery pack from the charger after the disconnect time elapses and to control the charging circuit to electrically reconnect the battery pack and the charger after disconnecting the battery pack from the charger.
US10270260B2	Cross-connection resolution in wireless power transfer systems Power transmitting unit (PTU) usable with a wireless power transfer system to supply power and maintain a control signaling link to a local power receiving unit (PRU). A cross-connection circumstance between the PTU and a remote PRU is determined, where a control signaling link between the PTU and the remote PRU is established in an absence of power transmission to the remote PRU from the PTU. In response to the cross-connection circumstance, the control signaling link with the remote PRU is terminated while the supply of power and the control signaling link with the local PRU is maintained. In a related embodiment, a wrong-placement characteristic where power is transferred to a rogue local PRU in an absence of a control signaling link with that PRU, is detected. In response, the supply of power is maintained for at least a waiting period.
US10270258B2	Direct integration of photovoltaic device into circuit board Aspects relate to a system and a method of manufacturing an integrated device. The method includes providing a circuit board, configuring an upper surface of the circuit board as a substrate, integrally depositing photovoltaic device layers that include at least a semi-conductor absorber layer, a buffer layer, and a top electrode layer on the upper surface of the circuit board to form a photovoltaic device using the upper surface of the circuit board as a photovoltaic device substrate, wherein the buffer layer is integrally deposited between the semi-conductor absorber layer and the top electrode, and electrically connecting the photovoltaic device to one or more on-board electronic components.
US10270252B2	System and method for scalable modular electric devices with hot-swap capability Systems, apparatuses, and methods for receiving a first magnitude of AC-sourced current at an inverter/charger from an AC bus and receiving a second magnitude of DC-sourced current at the inverter/charger from a DC bus. Then, a third magnitude of current is delivered to a load coupled to the AC bus. Given the dual originating sources of possible current to supply power to the load, the method may determine if the third magnitude of current being delivered to the load is less than the second magnitude of DC-sourced current and then, in response, converting a portion of the first magnitude of AC-sourced current into DC current to charge a DC source. Similarly, the method may determine if the third magnitude of current being delivered to the load is greater than the second magnitude DC-sourced current, and then, in response, inverting the DC-sourced current into an AC current.
US10270246B2	Start-up of HVDC networks A method and apparatus for controlling a voltage source converter to energize a DC link. A voltage order generating module generates a voltage order for controlling the voltage source converter to generate a DC voltage on the DC link. An oscillation damping module monitors the DC current flow to determine an indication of current oscillation and the voltage order is based on a voltage reference signal which is modulated by the indication of current oscillation to provide oscillation damping.
US10270245B2	Integrated circuit device and a device for protection of a circuit An integrated circuit device comprises at least one non-linear circuit. Further the integrated circuit device comprises a plurality of terminal circuits coupled to the non-linear circuit. Each terminal circuit comprises an associated terminal and an inductor coupled to the associated terminal and to the at least one non-linear circuit. A protective device for protection of a circuit, comprises an electro-static discharge protection element configured to be coupled to a circuit terminal and an inductor coupled to the electro-static discharge protection element and configured to be coupled to the circuit. The inductor has a low quality factor.
US10270241B2	Fault current limiter having fault checking system for power electronics and bypass circuit A fault current limiter may include a current limiting leg to transmit a first current and a control leg in parallel with the current limiting leg, the control leg to transmit a second current. The control leg may include a plurality of power electronic modules arranged in electrical series with one another, and a bypass power electronic module arranged in electrical series with the plurality of power electronic modules. The control leg may further include a plurality of current monitors arranged electrically in series with the plurality of power electronic modules and the bypass power electronic module, and at least one triggering circuit, wherein the plurality of current monitors is electrically coupled to the at least one triggering circuit, and wherein the at least one triggering circuit is coupled to at least one of: the plurality of power electronic modules, and the bypass power electronic module.
US10270238B2	Sealing boot for electrical interconnection A sealing boot for protecting an electrical interconnection includes: a main body having a cavity configured to house an interconnection of two electrical connectors; and a neck merging with one end of the main body and having a cylindrical inner surface that defines a bore that is continuous with the cavity of the main body, the inner surface having an inner diameter that is less than an inner diameter of the cavity of the main body. The inner surface of the neck includes a helical projection comprising a main artery and two tributaries, the tributaries each intersecting a section of the main artery at one end and merging with an end of the main artery at an opposite end.
US10270236B2	Recessed equipment boxes and related assemblies and methods An equipment box assembly includes a housing including a back wall, a bottom wall, a top wall, and first and second sidewalls defining a cavity. At least one mounting feature is on each of the first and second sidewalls. The housing is sized to fit between first and second adjacent studs with the first sidewall mounted to the first stud using the at least one mounting feature on the first sidewall and with the second sidewall mounted to the second stud using the at least one mounting feature on the second sidewall.
US10270231B2	Integrated contactor mounting post A contactor assembly post is provided. The contactor assembly post includes a first portion electrically connected to an external bus bar at an exterior of an electrical contactor housing, a second portion electrically connected to an internal bus bar at the exterior of the electrical contactor housing, a third portion and fins. The internal bus bar is configured to extend into an interior of the electrical contactor housing to be electrically coupled to another internal bus bar. The third portion extends transversely between the first and second portions. The fins extend transversely from multiple points defined along a longitudinal axis of the third portion.
US10270230B2	Power distribution system A power distribution system includes an electrical contactor arrangement. The electrical contactor arrangement includes a first contactor post, a first contactor lead, and a second contactor lead. The first contactor post extends from a first bus bar. The first contactor lead extends from the first contactor post. The first contactor lead is at least partially received within a contactor housing. The second contactor lead is spaced apart from the first contactor lead and extends from the first contactor post. The second contactor lead is at least partially received within the contactor housing.
US10270228B2	Spark plug A spark plug having a connection portion disposed in the axial hole and between a metal terminal and a center electrode. The connection portion includes: a magnetic substance formed from a Fe-containing oxide; a conductor helically disposed on an outer periphery of the magnetic substance and electrically connected to the metal terminal and the center electrode; and an intermediate member disposed between the magnetic substance and the conductor, and an inner peripheral surface of the insulator and having lower electrical conductivity than the conductor. The conductor includes a base and a conductive layer disposed on an outer periphery of the base and having higher electrical conductivity than the base, and the conductive layer has a thickness of larger than 0.1 μm and equal to or smaller than 25 μm.
US10270227B2	Ignition plug An ignition plug includes a ground electrode tip disposed in through hole through a ground electrode base material, a discharge surface of the ground electrode tip being exposed to the center electrode side from the through hole; and a fixing member disposed in the through hole at a part on a second direction side with respect to the large diameter surface.
US10270222B2	Semiconductor laser source A semiconductor laser source wherein a waveguide in which a filter is produced is made of a material that is less sensitive to temperature. The laser source also includes a tuning device able to shift the possible resonant wavelengths ΔλRj of a Fabry-Pérot optical cavity in response to an electrical controlling signal, a sensor able to measure a physical quantity representative of the difference between a central wavelength λCf of the filter and one of the possible wavelengths λRj, and an electronic circuit able to generate, depending on the physical quantity measured by the sensor, the electrical signal controlling the tuning device in order to keep one wavelength λRj at the center of each passband of the filter that selects an emission wavelength λLi of the laser source.
US10270221B1	Optical device and system having an array of addressable apertures Optical devices and systems are depicted and described herein. One example of the optical system is disclosed to include a semiconductor layer, a first metal strip positioned adjacent to a first surface of the semiconductor layer, a second metal strip positioned adjacent to a second surface of the semiconductor layer that opposes the first surface of the semiconductor layer, and a third metal strip positioned adjacent to the second surface of the semiconductor layer. In one example, the first metal strip includes a first aperture positioned adjacent to a first active region in the semiconductor layer and second aperture positioned adjacent to a second active region in the semiconductor layer. The second metal strip overlaps the first metal strip in proximity with the first active region and not the second active region and the third metal strip is oriented substantially parallel with the second metal strip.
US10270220B1	Methods and systems for heat flux heat removal Methods and systems for increased heat removal from devices in which the component design allows for thinner heat removal components.
US10270219B1	Packaging structure of laser diode A packaging structure of a laser diode is provided. The packaging structure of the laser diode includes a laser chip, a first substrate and a second substrate. The first substrate having a first electrode and a second electrode on a first surface of the first substrate, and the laser chip is disposed on the first surface of the first substrate; and a second substrate having a third electrode and a fourth electrode on a second surface of the second substrate, wherein the first electrode and the second electrode are electrically connected to the third electrode and the fourth electrode by a wireless-bonding process, respectively.
US10270217B2	De-emphasis with separate edge control A driver system with emphasis or de-emphasis control of optic signal generator comprising an input configured to receive an input signal that is to be transmitted as an optic signal. Also part of this system is a rising edge delay creating a first delay signal relative to the input signal and a falling edge delay creating a second delay signal relative to the input signal. A multiplexer receives the first delay signal and the second delay signal and selectively outputs either the first delay signal and the second delay signal to an amplifier. A first amplifier amplifies the input signal to create an amplified input and a second amplifier amplifies the multiplexer output signal to create a de-emphasis signal. A summing junction subtracts the de-emphasis signal from the amplified input to create a driver output signal. The rising and falling edge delays may each comprise two more delays.
US10270216B2	Brush holder assemblies and methods for mounting and replacing brushes An assembly has a handle, a brush holder, and a support that connect and disconnect to each other using a locking mechanism. The handle reversibly connects and disconnects from the brush holder. The locking mechanism includes a connecting member on the brush holder that attaches to the handle by interaction of a locking flange on the connecting member with a pair of teeth inside of the handle. Insertion of the support within the brush holder extends a post on the support through the connecting member to interact with the handle and enable disconnection of the handle from the brush holder when the support is fully engaged by the brush holder. The locking mechanism prevents the handle from releasing from the brush holder before the brush holder is completely seated on the support.
US10270210B2	Communications connectors including transmission lines having impedance discontinuities that improve return loss and/or insertion loss performance and related methods Communications connectors are provided that include a printed circuit board having a plurality of input terminals, a plurality of output terminals, and a plurality of conductive paths that connect each input terminal to a respective output terminal. The conductive paths are arranged as a plurality of differential transmission lines, and a solenoid inductor is implemented along at least one of the conductive paths.
US10270202B2	Power electronic arrangement comprising a communication device The invention presents a power electronic arrangement comprising a power electronic switching device, a printed circuit board for carrying control signals for driving the power electronic switching device, a housing which covers the printed circuit board, a communication device which is arranged on the printed circuit board and is accessible through a recess in the housing, and comprising a sealing device, wherein the sealing device has a sealing section which rests in a sealing manner on a first sealing face of the communication device, and wherein the sealing device has a first and second sealing lip which are each arranged circumferentially around and at a distance from the communication device, wherein the two sealing lips are connected to one another by a web and both rest on a second sealing face of the printed circuit board, and wherein the housing has a wall-like pressure device which presses on the web and in this way the first sealing lip bears against that side of the pressure device which faces the communication device, and the second sealing lip bears against that side of the pressure device which is averted from the communication device.
US10270201B2	Housing for a plug-in connection The invention relates to a housing for a plug-in connection, comprising a lower shell element (100) and an upper shell element (200) that is identical to the lower shell element (100), each shell element (100, 200) containing a retaining element (2), by means of which a plug-in connector (1) can be secured to the housing. Each shell element (100, 200) contains a receptacle (3), in which a cable mount (9) can be received and each shell element (100, 200) has at least one detent element (11, 12, 13, 14) that cooperates with a mating detent element (21, 22, 23, 24) of the other shell element (200, 100). The detent elements (11, 12, 13, 14) and the mating detent elements (21, 22, 23, 24) have a multi-step design and the entire border regions between the shell elements (100, 200) forming the housing, with the exception of openings for the plug-in connector (1) and the cable mount (9), have a multi-step design.
US10270199B2	Power connector A power connector includes an insulative housing, a plurality of power contact pairs retained in the insulative housing abreast along a transverse direction and a plurality of parallel fasteners. The insulative housing has a plurality of receiving slots arranged side by side along the transverse direction. Each power contact pair defines a pair of power contacts opposite to each other, and each parallel fastener is connecting the pair of power contacts of each power contact pair mechanically and electrically together. The insulative housing defines a plurality of accommodating grooves, and each accommodating groove is located behind and communicated with the corresponding receiving slot, each parallel fastener is locked in the corresponding accommodating groove and fixing the corresponding power contact pair in the accommodating groove.
US10270198B2	Canted coil springs, connectors and related methods Connector assemblies formed by attaching two stamped housing sections to form a connector housing having a housing groove with a groove bottom and two side walls are disclosed. Using stamped housing sections can reduce manufacturing costs and simplifies assembly, among other things. The connector housings with a canted coil spring can be used as a mechanical connector and/or as an electrical connector for numerous applications and across numerous industries. The canted coil springs can have complex shapes, with optional dimples.
US10270197B2	Female terminal having a resiliently displaceable contact piece folded rearward from a front end of a step A female terminal disclosed by this specification is a female terminal (10) to which a male terminal (50) is connected from front, and includes a bottom plate (15) long in a front-rear direction, a ceiling plate (16) disposed to face the bottom plate (15), a pair of side plates (17) linking both side edges of the bottom plate (15) and both side edges of the ceiling plate (16), a step portion (25) provided on a front end edge of the bottom plate (15) in a stepwise manner to be slightly higher than the bottom plate (15) and extending forward to be disposed between the pair of side plates (17), and a resilient contact piece (30) resiliently displaceably provided by being folded rearwardly from a front end edge of the step portion (25), the male terminal (50) being capable of resiliently contacting the resilient contact piece (30) from front.
US10270196B2	High current connector and socket connector thereof A high current connector and a socket connector of the high current connector are provided. The high current connector includes a first connector, a resilient electrical conductor and a second connector. The first connector includes an insertion slot. The resilient electrical conductor is received in the insertion slot and includes a resilient body, an insertion space formed inside the resilient body, and gaps arranged annularly on the resilient body. The second connector includes a conductive element inserted in the insertion space, the conductive element is electrically connected to the first connector through the resilient electrical conductor and is fixed in the insertion slot by means of stretchable configuration of the gaps. Accordingly, the resilient electrical conductor tightly fixes the conductive element to achieve reliable and safe connection and also improve contact quality.
US10270195B2	Connector A connector is provided with a female contact and a housing. A protection portion of the female contact has a guide portion intersecting with a front-rear direction to guide a male contact to a receiving portion. An insertion opening of the housing is located forward of a contact accommodation portion in the front-rear direction. The insertion opening opens in a predetermined direction perpendicular to the front-rear direction and thereby communicates with an aperture portion. When a front of the connector is viewed along the front-rear direction, the guide portion is visible through the insertion opening at least in part.
US10270194B2	Electrical connector assembly having a latch secured to both connector housing and internal substrate An electrical connector assembly includes: a connector housing receiving a plurality of contacts mounted to an internal substrate; a shielding shell enclosing the connector housing; and a pair of latches secured to the connector housing in a cantilevered fashion; wherein the latch has an arm secured to the substrate.
US10270192B2	Cable connector assembly A cable connector assembly includes: an insulative housing; a printed circuit board (PCB) received in the insulative housing, the PCB having an upper surface; an electrical connector electrically connected with the PCB; a cable; a light member mounted on the PCB; a light guide member mounted on the PCB; and a shading member covered on the light guide member; wherein the electrical connector includes plural conductive terminals and plural fixing fingers fixed on the PCB, the PCB includes plural conductive pads exposed on the upper surface of the PCB and fixed with the conductive terminals and plural mounting holes on the upper surface of the PCB and matched with the fixing fingers.
US10270191B1	Plug and connector assembly Provided is a plug and a connector assembly, which belong the technical field of connectors. The plug includes an insulating body, a cable and a circuit board. The insulating body includes a body part and a mating part which extends forwardly from the body part. The cable and the circuit board are electrically connected. The circuit board has an inserting part which protrudes forwardly out of the mating part. An outer side of the mating part is provided with a limiting groove and a guiding wall disposed within the limiting groove, and the guiding wall is adjacent to the inserting part and is capable of guiding insertion of the plug into a socket and preventing the plug from shaking in an up-down direction and/or in a left-right direction when the plug is inserted into the socket. The connector assembly includes the plug and the socket.
US10270186B2	Antenna module and electronic device According to one embodiment, an antenna module includes a substrate, a first antenna, an array antenna, and a radio frequency (RF) module. The first antenna includes a first radiation element arranged on the substrate and a first ground plane arranged on the substrate. The array antenna includes a plurality of second radiation elements arranged on the substrate. The substrate includes a first surface and a second surface. The first ground plane is arranged on at least the first surface of the substrate. The plurality of second radiation elements are arranged on the second surface of the substrate and opposed to the first ground plane via the substrate.
US10270184B2	Control module and multiple-antenna device having the same A control module is installed in a multi-antenna device having a wireless chip, and comprises a multi-antenna system, an antenna control unit, an application unit and a microprocessor. The multi-antenna system comprises antenna units. Each antenna unit comprises a main antenna and a reflecting unit, with the main antenna generating a radiation pattern in a single polarization direction, and the reflecting unit parallel to the single polarization direction and partially surrounding the main antenna. When a diode is conducted, the reflecting unit forms a rectangular closed slot structure as a reflector of the main antenna; conversely, the reflecting unit does not serve as the reflector. According to the signal strength or data receiving rates of the antenna units, the application unit controls the microprocessor to associate with an algorithm processing procedure to determine whether to conduct the diode for changing a radiation pattern of the multi-antenna system.
US10270183B1	Graphene-based rotman lens Embodiments of the present invention relate to a graphene-based Rotman lenses and associated methods of formation. In some embodiments, a lens is positioned proximate to a surface of a dielectric plate. In other embodiments, the lens comprises a first lens contour positioned opposite a second lens contour. In certain embodiments, a plurality of first transmission lines extends from the first lens contour and each terminating at a particular first port. In yet still other embodiments, a plurality of second transmission lines extends from the second lens contour and each terminating at a particular second port. In some embodiments, the lens includes a composition having a polymer(s) and a three-dimensional network of individual sheets of graphene positioned within the composition. In certain embodiments, the first port and/or the second port has a width of λ/2 or less.
US10270180B2	Antenna apparatus A plurality of unit structures, each including a first planar conductor, a second planar conductor arranged so as to be opposed to the first planar conductor, a first conductor connection part that connects the first planar conductor and the second planar conductor, a second conductor connection part that connects the first planar conductor and the second planar conductor in a position different from the position of the first conductor connection part, and an opening part that is held between the first conductor connection part and the second conductor connection part and is provided on the first planar conductor, are arranged in a direction perpendicular to a line segment that connects the first conductor connection part and the second conductor connection part and include unit structures including at least two or more types of opening parts, the shapes of which are different from one another.
US10270177B2	Broadband antenna, multiband antenna unit and antenna array A broadband antenna of an antenna system comprises a conductive plate comprising four slots. The slots are arranged in a rotation symmetrical manner in the plate. Each slot extends from a circumference of the plate towards a center of the plate. Each slot has an associated feed point located at its associated slot. The feed points associated with a pair of oppositely arranged slots are arranged to be fed with radio frequency signals, such that that a main radiation propagation direction of the antenna is along the rotational symmetry axis of the plate. The antenna design enables the achievement of flexibility in terms of isolation between the two polarizations. The antenna design may further enable a reduced size and weight. The antenna design also enables an antenna unit and an antenna array.
US10270175B2	Battery provided with three electrical connection tongues Disclosed is a battery having a positive terminal and a negative terminal and two electrical connection tongues, each tongue secured to one of the terminals thereof. The battery also includes at least one additional connection tongue secured to one of the terminals thereof, forming a radiating element with the electrical connection tongue secured to the same terminal of the battery.
US10270173B2	Patch antenna A patch antenna includes a grounding portion and a radiating portion. The radiating portion includes a first feeding point, a first grounding point, a second feeding point, and a second grounding point. The first feeding point is electrically connected to a first signal source. The first grounding point is electrically connected to the grounding portion. The second feeding point is electrically connected to a second signal source. The second grounding point electrically connected to the grounding portion. The line formed by connecting the first feeding point and the first grounding point is substantially perpendicular to the line formed by connecting the second feeding point and the second grounding point.
US10270165B2	Antenna device The antenna device in one embodiment of the present invention includes a conductor ground plate, a first antenna portion, a switch, and a plurality of second antenna portions. The above described switch is connected between the above described conductor ground plate and the above described first antenna portion. The above described plurality of second antenna portions are arranged at positions at which the second antenna portions can be capacitively coupled to the above described first antenna portion.
US10270164B2	Systems and methods for beam direction by switching sources Various embodiments of a millimeter-wave wireless point-to-point or point-to-multipoint communication system which enables determining preferred directions of transmissions, and transmitting in such preferred directions without routing radio-frequency signals. The system comprises a millimeter-wave focusing element, multiple millimeter-wave antennas, and multiple radio-frequency-integrated circuits (“RFICs”). In various embodiments, preferred directions are determined, and millimeter-wave beams are transmitted in the preferred directions.
US10270163B2	Communication module and communication device including same One embodiment of a communication module can comprise: a first antenna printed on a substrate and provided in a plate shape; a second antenna spaced from the first antenna, printed on the substrate, and provided in a plate shape; a third antenna coupled to the substrate, provided in a three-dimensional shape, and transmitting or receiving a radio wave of a frequency band which is the same as or similar to that of the first antenna; a fourth antenna coupled to the substrate, provided in a three-dimensional shape, and transmitting or receiving a radio wave of a frequency band which is the same as or similar to that of the second antenna; and an integrated circuit electrically connected to the first to fourth antennas, mounted on the substrate, applying currents to the first to fourth antennas, and processing a transmitted or received signal.
US10270162B2	Omnidirectional antennas, antenna systems, and methods of making omnidirectional antennas Exemplary embodiments are disclosed of antennas, antenna systems, and methods of making antennas. In an exemplary embodiment, an antenna generally includes a ground plane and first and second antennas each including a first feed. The antenna system further comprises a neutral line having first and second end portions coupled to the first feed of the respective first and second antennas, and/or one or more decoupling stubs integrally formed from and extending outwardly relative to the ground plane. In another exemplary embodiment, a method of improving isolation between first and second antennas of an antenna system generally includes coupling first and second end portions of a neutral line to a first feed of the respective first and second antennas, and/or integrally forming one or more decoupling stubs from a ground plane.
US10270161B2	Antenna device and wireless apparatus including same An antenna device includes a feeding element connected to a feed point, and a radiating element disposed at a distance from the feeding element. The feeding element is coupled with the radiating element by electromagnetic field coupling to feed the radiating element so that the radiating element functions as a radiating conductor.
US10270158B2	Wearable electronic device A wearable electronic device is disclosed. Wearable electronic device includes a metal casing, a dielectric support part, a frame-shaped metal part, a dielectric sidewall and a first antenna wired circuit. The metal casing is electrically connected to the system ground. The dielectric support part is disposed on the metal casing. The frame-shaped metal part is disposed on the dielectric support part. One side of the frame-shaped metal part is electrically connected to the metal casing and another side of the frame-shaped metal part has a slot. The dielectric sidewall is surrounding within the metal casing. The first antenna wired circuit is disposed on the inner surface of the dielectric sidewall and insulated from the metal casing. The first antenna wired circuit is near the slot. The first antenna wired circuit and the frame-shaped metal part resonate a first resonant frequency band.
US10270157B2	Antenna device of mobile terminal Various mobile communication terminals, apparatuses, and methods having antenna improvements are discussed. An apparatus is described which includes an outer front side having a display disposed therein; an outer rear side a conductive part and a non-conductive part; a battery disposed between the outer front side and the outer rear side; and an antenna including a radiation unit capable of receiving a signal, at least a portion of the radiation unit being disposed between the outer front side and the non-conductive part of the outer rear side, a feeding unit which electrically connects the radiation unit to a circuit board, and a ground part which electrically connects the radiation unit to the conductive part of the outer rear side.
US10270155B2	Antenna device and electronic apparatus Coil conductors each including a coil opening, and a planar conductor are included in an antenna device. The coil conductors are disposed at edge portions of the planar conductor such that winding axes of the coil conductors extend in a normal direction of the planar conductor. The coil conductors are connected such that magnetic fluxes generated at the respective coil conductors are in phase with each other. In a plan view, portions of the plurality of coil conductors overlap the planar conductor and portions of the coil openings do not overlap the planar conductor.
US10270149B2	Circulator device with two magnet-free circulators There is provided a circulator device. The circulator device comprises two magnet-free circulators. Each magnet-free circulator has a forced time variance. The circulator device comprises ports. The two circulators are in the circulator device arranged to have mutually anti-phase time variance. Each of the two circulators is coupled to all of the ports. There is also presented an isolator device comprising such a circulator device. There is also presented a radio transceiver device comprising such a circulator device or isolator device.
US10270142B2	Copper alloy metal strip for zinc air anode cans The present disclosure generally relates to a zinc air cell having an anode can made of a copper alloy. The anode can material reduces internal gassing within the electrochemical cell while being compatible with the internal chemistry of the anode and the alkaline electrolyte of the cell itself.
US10270141B2	Thermoelectric-based thermal management system Disclosed embodiments include thermoelectric-based thermal management systems and methods configured to heat and/or cool an electrical device. Thermal management systems can include at least one electrical conductor in electrical and thermal communication with a temperature-sensitive region of the electrical device and at least one thermoelectric device in thermal communication with the at least one electrical conductor. Electric power can be directed to the thermoelectric device by the same electrical conductor or an external power supply, causing the thermoelectric device to provide controlled heating and/or cooling to the electrical device via the at least one electrical conductor. The thermoelectric management system can be integrated with the management system of the electrical device on a printed circuit substrate.
US10270138B2	Battery module with a fixture for a temperature sensitive element A battery module includes: a battery cell; a protective circuit module electrically coupled to the battery cell; a temperature sensitive element at the battery cell; a flexible printed circuit board having first and second end portions and an inner portion extending between the first and second end portions; and a spring. The protective circuit module includes a rigid printed circuit board. The flexible printed circuit board is fixed to a surface of the rigid printed circuit board facing the battery cell by the first and second end portions such that the inner portion forms a loop, is electrically connected to the protective circuit module and to the temperature sensitive element, and is centrally positioned on the inner portion of the flexible printed circuit board. The spring is arranged within the loop of the flexible printed circuit board such that the temperature sensitive element is pushed towards the battery cell.
US10270137B1	Battery status and failure detector The present invention extends to methods, systems, devices, apparatus, and computer program products for detecting battery status and failure. In general, detecting mechanical swelling of a battery cell along with optional measurement of temperature increases can be used to identify a battery cell as failing or failed. Force strain sensors or similar extension/compression sensors can be mounted in a (e.g., fire resistant) sleeve surround a battery pack and/or between cells in a battery pack. In some embodiments, extension/compression sensors are used along with temperature probes to detect battery cell failure.
US10270133B2	Method of increasing secondary power source capacity A method of increasing secondary power source capacity includes doping a compound into an electrolyte as an additive which binding energy is higher than binding energy of combinations that are formed at a secondary power source discharge, the compound being ZnKr or CdAr. The method can be used in manufacturing secondary power sources such as batteries for electrical machines, transport vehicles, and cars, and for power sources for portable and mobile electronic devices.
US10270132B2	Electrolyte for non-aqueous electrolyte battery and non-aqueous electrolyte lithium battery An electrolyte for a non-aqueous electrolyte battery includes a non-aqueous organic solvent and at least lithium hexafluorophosphate as a solute, characterized by further including 10 to 1000 mass ppm of a phosphorus-containing acidic compound and 0.01 to 10.0 mass % of a difluorophosphate. The phosphorus-containing acidic compound is preferably at least one selected from the group consisting of HPF6, HPO2F2, H2PO3F and H3PO4. By the use of such an electrolyte, it is possible to provide the non-aqueous electrolyte lithium battery capable of maintaining high discharge capacity even after repeated charge/discharge cycles under a high temperature environment.
US10270128B2	Battery, electrolyte, battery pack, electronic device, electric vehicle, power storage device, and power system A particle size D50 of the particle is not less than 50 nm and not more than 450 nm, or not less than 750 nm and not more than 10,000 nm. A refractive index of the particle is not less than 1.3 and less than 2.4. One of a mass ratio between the particles and the matrix polymer compound (particles/matrix polymer compound) and a mass ratio between the particles and the electrolyte salt (particles/electrolyte salt) is not less than 15/85 and not more than 90/10.
US10270127B2	Nonaqueous electrolyte secondary battery A nonaqueous electrolyte secondary battery includes a positive electrode, a negative electrode having a negative electrode active material, and a separator containing an electrolyte. The electrolyte includes an electrolyte salt, a nonaqueous solvent into which the electrolyte salt can be dissolved, a first additive selected from predetermined oxalate compounds and disulfonic acid ester compounds, and a second additive that has a reduction potential less than the reduction potential of the first additive. The second additive is selected from a group having vinylene carbonate, fluoroethylene carbonate, vinyl ethylene carbonate, 1, 3-propane sultone, 1, 4-butane sultone, 1, 3-propene sultone, succinonitrile, and adiponitrile.
US10270124B2	Lithium secondary battery A lithium secondary battery including a cathode, an anode and a non-aqueous electrolyte. The cathode includes a cathode active material containing lithium-metal oxide of which at least one of metals has a concentration gradient region between a core part and a surface part thereof. The lithium-metal oxide includes elements M1, M2, and M3. M3 has a concentration gradient region with increased concentration between the core part and the surface part, M1 has a concentration gradient region with decreased concentration between the core part and the surface part, and M2 has a constant concentration from the core part and the surface part. The anode includes graphite having an average lattice distance d002 of 3.356 to 3.365 Å.
US10270123B2	Prevention of cell-to-cell thermal propagation within a battery system using passive cooling Disclosed herein are liquid-cooled battery systems configured to prevent cell-to-cell thermal propagation. In one embodiment, a system includes a section configured to generate and store electrical energy through heat-producing electro-chemical reactions. A cooling system may be configured to generate a flow of a liquid coolant through the battery system to remove heat produced by the battery. Cooling fins may be configured to receive the flow of the liquid coolant through a primary coolant channel and to transfer heat from the battery to the liquid coolant. The cooling fins may also include a secondary coolant channel configured to be at least partially filled with a melting material configured to obstruct the liquid coolant from exiting through the aperture at temperatures below a temperature threshold. When the melting material melts, it permits some of the liquid coolant to exit the cooling fin and wet and cool the adjacent battery section.
US10270122B2	Liquid electrolyte for fluoride ion battery and fluoride ion battery A problem of the present invention is to provide a liquid electrolyte for a fluoride ion battery, in which fluoride anion conductivity is imparted to an ionic liquid containing fluoride complex anions. The present invention solves the problem by providing a liquid electrolyte for a fluoride ion battery, which comprises an ionic liquid containing specific fluoride complex anions and an anion acceptor having a specific acceptor number.
US10270119B2	Fuel cell stack arrangement The present invention is concerned with improved fuel cell stack assembly arrangements.
US10270116B2	High-temperature polymer electrolyte membrane fuel cell stack having independent cooling plate and method of producing the same A high-temperature polymer electrolyte membrane fuel cell stack may include a plurality of cell units; a cooling assembly including a plurality of first independent cooling plates disposed on top surfaces of the plurality of cell units, respectively, and a plurality of second independent cooling plates disposed on bottom surfaces of the plurality of cell units, respectively; and a support assembly configured to support the plurality of cell units and the cooling assembly.
US10270111B2	Method for accelerating activation of fuel cell stack A method for accelerating activation of a fuel cell stack may shorten an activation time of the fuel cell stack and reduce the amount of hydrogen used. The method includes a process of applying a high current to the fuel cell stack for a prescribed amount of time and a shutdown maintenance process of pumping hydrogen to an air electrode reaction surface for a prescribed amount of time.
US10270105B2	Insulator and fuel cell In order to improve a power density of a fuel cell and prevent a generation of a poor insulation, an insulator is provided, which is disposed between a current collector disposed in contact with one end of a stacked body having a plurality of stacked unit cells in stacking directions, and an end member disposed outside from the current collector in the stacking directions, and includes a plurality of insulator members, each having a sheet-like planar portion. The plurality of insulator members which are stacked onto each other by the planar portions thereof are disposed oppose to the current collector.
US10270102B2	Electrode for electrochemical device with low resistance, method for manufacturing the same, and electrochemical device comprising the electrode The present disclosure relates to an electrode that may minimize an electrical resistance increase caused by a binder polymer or a conductive material used in the electrode and provide a high capacity, a method for manufacturing the same, and an electrochemical device comprising the electrode, and an electrode mix slurry is prepared using a high shearing mixing process for each step such that fine grained conductive material and a binder polymer are uniformly dispersed in an electrode mix, and a high capacity electrode active material is used in the electrode mix, to manufacture a high capacity electrochemical device.
US10270099B2	Positive electrode for lithium-ion secondary battery, production process for the same, and lithium-ion secondary battery A positive electrode for lithium-ion secondary battery includes: a lithium metallic oxide with a lamellar rock-salt structure including nickel, cobalt, and manganese; and a phosphate/carbon composite including an olivine-type phosphate compound at least some of which is coated with carbon partially. A rate of a volume resistivity of the phosphate/carbon composite to a volume resistivity of the lithium metallic oxide is 0.034 or less. The olivine-type phosphate compound is expressed by a general formula: LiMhPO4 (where “M” is at least one element selected from the group consisting of Mn, Fe, Co, Ni, Cu, Mg, Zn, V, Ca, Sr, Ba, Ti, Al, Si, B, Te and Mo, and 0<“h”<2). A content of the phosphate/carbon composite is from 15% by mass or more to 35% by mass or less when a summed mass of the lithium metallic oxide and the phosphate/carbon composite is taken as 100% by mass.
US10270098B2	Positive electrode active material for lithium ion battery, containing lithium vanadium zirconium phosphate, and lithium ion battery comprising same The present invention relates to a positive electrode active material for a lithium ion battery and, more specifically, to a positive electrode active material for a lithium ion battery, having improved initial capacitance and charging and discharging efficiency due to increased electrical conductivity or ion conductivity. The positive electrode active material for a lithium ion battery of the present invention contains lithium vanadium phosphate (Li3V2(PO4)3) and lithium zirconium phosphate (Li3Zr2(PO4)3) formed on an external surface of the lithium vanadium phosphate. The positive electrode active material for a lithium ion battery comprising lithium vanadium zirconium phosphate (Li3V2-xZrx(PO4)3) particles, which is prepared by a preparation method of the present invention, has excellent structural stability and ion conductivity as well as high capacitance.
US10270096B2	Positive active material for rechargeable lithium battery, method of preparing same and rechargeable lithium battery including same A positive active material for a rechargeable lithium battery includes a LiCoO2 particle. An interior of the particle has a layered structure and a surface of the particle has a spinel structure.
US10270094B2	Porous sintered superstructure with interstitial silicon for use in anodes for lithium batteries Anodes for the lithium secondary batteries include a strong, electrically conductive, porous superstructure filled with a milled or melted interstitial material, such as nano-scaled silicon; the milled or melted interstitial material provides high lithiation capacity, and the superstructure provides durability and controls the anode's electromechanical expansion and contraction during the lithiation and de-lithiation cycle. Embodiments include porous superstructures comprised of silicon carbide, tungsten, and other materials, many of which offer capability of lithiating.
US10270090B2	Production method for cathode material of lithium sulfur battery, cathode material of lithium sulfur battery, and lithium sulfur battery A production method for a cathode material of a lithium sulfur battery includes, in sequence: a step of preparing a first dispersed solution in which a carbon particle is dispersed in a lithium sulfate solution; a step of adding a solvent in the first dispersed solution, the solvent being a solvent in which lithium sulfate is insoluble; a step of separating a precursor particle from the first dispersed solution in which the solvent is added; and a step of changing the precursor particle into a cathode active material particle by heating the precursor particle under an inert atmosphere.
US10270088B2	Positive active material composition, and lithium secondary battery including the positive electrode including the positive active material composition, and lithium battery including the positive electrode A positive active material composition for a lithium secondary battery includes a positive active material that allows intercalation and deintercalation of lithium ions, a binder, and a conductive agent. The conductive agent includes a first conductive agent having an average particle diameter (D50) ranging from about 20 nanometers (nm) to about 40 nm and a second conductive agent having a D50 ranging from about 1 micrometer (μm) to about 5 μm.
US10270084B2	Lithium ion battery, negative electrode for lithium ion battery, battery module automobile, and power storage device An object is to provide a lithium ion battery excellent in input/output characteristics, cycle life characteristics, and safety. The lithium ion battery is a lithium ion battery including, in a battery container, an electrolyte solution and an electrode group in which a positive electrode and a negative electrode are disposed through a separator. A lithium-nickel-manganese-cobalt composite oxide having a layered crystal structure is contained as a positive electrode active material, an easily graphitizable carbon is contained as a negative electrode active material, a weight of the easily graphitizable carbon heated at 550° C. in dry air flow in thermogravimetric analysis is equal to more than 75% of a weight of the easily graphitizable carbon heated at 25° C. therein, and a weight of the easily graphitizable carbon heated at 650° C. therein is equal to or less than 20% of the weight of the easily graphitizable carbon heated at 25° C. therein.
US10270083B2	Negative electrode for lithium secondary battery, method of manufacturing the same and lithium secondary battery using the same The present invention relates to a negative electrode for a lithium secondary battery that can ensure a high energy density, a long-life characteristic, and stability by forming a film on a negative electrode for a lithium secondary battery and thus suppressing dendrites during electrodeposition, a method of manufacturing the same, and a lithium secondary battery using the same. The method of manufacturing the negative electrode for a lithium secondary battery according to the present invention includes preparing a sulfur dioxide-based sodium molten salt and forming a protective layer on the surface of a current collector by immersing the current collector in the sulfur dioxide-based sodium molten salt.
US10270076B2	Spacer A spacer in a square shape and includes an upper groove section provided on an upper surface, and a lower groove section provided on a lower surface. The upper groove section includes a first upper groove fittable with a first lower end edge of a first frame of a battery module located on the upper side, and a second upper groove fittable with a second lower end edge of a second frame of the battery module located on the upper side. The lower groove section includes a first lower groove fittable with a first upper end edge of the first frame of the battery module located on the lower side, and a second lower groove fittable with a second upper end edge of the second frame of the battery module located on the lower side.
US10270075B2	Separator having adhesive layer, manufacturing method of the same, and electrochemical device having the same A heat-resistant separator contains a porous film, a polymeric fibrous layer adhesively bonded to the surface of the porous film, and an adhesive binder layer located between the porous film and the fibrous layer and covering at least a portion of the surface of the porous film. The fibrous layer contains fibers manufactured of a polyimide wherein the fibers of a form of polyimide comprise fibers with a majority of fibers having diameters in the range of 1-3000 nm. In one of the embodiment the binder layer contains sodium carboxymethylcellulose, and the amount of adhesive present between the porous film and the fibrous web in the final product is within the range of 0.30 grams per square meter of covered surface of porous film to 0.90 grams per square meter of covered surface of porous film.
US10270074B2	Battery separators comprising chemical additives and/or other components Non-woven webs that can be used as battery separators for batteries, such as lead acid batteries, are generally provided. In some embodiments, battery separators comprising a non-woven web including one or more chemical additives are provided. The chemical additives may impart beneficial properties, such as enhanced separator stability and/or battery performance. In some embodiments, the chemical additive(s) may confer resistance to oxidation, heavy metal deposition, and/or formation of short circuits during cycling of a battery including the battery separator. The respective characteristics and/or amounts of the chemical additive(s) may be selected to impart desirable properties while having relatively minimal or no adverse effects on another property of the battery separator and/or the battery.
US10270073B2	Organic/inorganic composite coating porous separator and secondary battery element using same There is provided an organic/inorganic complex coating porous separator including a porous substrate, and an organic/inorganic complex coating layer formed in a single layer or multiple layers on a single surface or both surfaces of the porous substrate or at least a part of a pore portion of the porous substrate using a coating solution comprising a binder dispersed or suspended in a certain size and selectively comprising inorganic particles, and a secondary battery including the same. According to the present invention, since the coating solution comprising the binder dispersed in a certain size or less in a solvent is coated/dried on the porous substrate, a organic/inorganic complex coating porous separator having excellent air permeability and adhesive strength and a secondary battery including the organic/inorganic complex coating porous separator are provided.
US10270071B2	Systems and methods for voltage regulated battery backup management Systems and methods are provided that employ voltage regulated management of battery backup for information handling systems, such as blade server systems. The disclosed systems and methods may be implemented for an information handling system using multiple battery subsystems in a single battery backup unit (BBU) or using multiple battery backup units, and the multiple battery subsystems or BBUs may be individually controlled and managed using defined protocols and architectures.
US10270067B2	AMOLED display panel manufacturing method, apparatus and system The present disclosure discloses an AMOLED display panel manufacturing method, apparatus and system. The method comprises: collecting size parameters of a substrate, constructing an AMOLED display panel model based on the size parameters, and determining spray data of respective organic vapor materials; controlling corresponding spraying devices to spray the respective organic vapor materials on the substrate successively according to the determined spray data of the respective organic vapor materials, to form an AMOLED display panel.
US10270057B2	Light-emitting device, module, electronic device, and method for manufacturing light-emitting device A light-emitting element, a bonding layer, and a frame-like partition are formed over a substrate. The partition is provided to surround the bonding layer and the light-emitting element, with a gap left between the partition and the bonding layer. A pair of substrates overlap with each other under a reduced-pressure atmosphere and then exposed to an air atmosphere or a pressurized atmosphere, whereby the reduced-pressure state of a space surrounded by the pair of substrates and the partition is maintained and atmospheric pressure is applied to the pair of substrates. Alternatively, a light-emitting element and a bonding layer are formed over a substrate. A pair of substrates overlap with each other, and then, pressure is applied to the bonding layer with the use of a member having a projection before or at the same time as curing of the bonding layer.
US10270056B2	Display device and method of manufacturing thereof A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided. According to the present invention, a display device and a method of manufacturing the same comprising: a display portion formed by aligning a light-emitting element using an organic light-emitting material between a pair of substrate, wherein the display portion is formed on an insulating layer formed on any one of the substrates, the pair of substrates is bonded to each other with a sealing material formed over the insulating layer while surrounding a periphery of the display portion, at least one layer of the insulating layer is made of an organic resin material, the periphery has a first region and a second region, the insulating layer in the first region has an opening covered with a protective film, the sealing material is formed in contact with the opening and the protective film, an outer edge portion of the insulating layer in the second region is covered with the protective film or the sealing material.
US10270055B2	Flexible display device and method of manufacturing the same The present disclosure relates to a technical field of a display, especially a flexible display device including a substrate, an anode layer disposed on the substrate, and a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, a cathode layer and a package layer disposed on the anode layer from bottom to top, wherein the anode layer includes a third metal layer disposed the substrate, and a first metal layer and a second metal layer disposed on the third metal layer by stacking up and down, the first metal layer and the third metal layer have work functions greater than that of the second metal layer, and the work functions of the first metal layer and/or the third metal layer are not less than 4.5 eV.
US10270050B2	Photoelectric conversion layer composition and photoelectric conversion element A composition that can form a photoelectric conversion layer having an electricity storage function is provided. The composition comprises at least a semiconductor (e.g., a titanium oxide particle) and an ionic polymer (e.g., a fluorine-series resin having a sulfo group), and the ratio of the ionic polymer relative to 1 part by weight of the semiconductor is not less than 0.05 parts by weight. The composition may further contain a dye (a sensitizing dye). An electrode provided with a photoelectric conversion layer formed from the composition can be used in combination with, in particular, an electrode having a porous layer to give a photoelectric conversion element having an excellent electricity storage function.
US10270048B2	Organic EL panel translucent substrate, control method for refractive index anisotrophy of organic EL panel translucent substrate, manufacturing method for organic EL panel translucent substrate, organic EL panel, and organic EL device Disclosed is an organic EL panel translucent substrate that can prevent or reduce the color gap/coloring of an organic EL panel. In order to achieve the above object, organic EL panel translucent substrate 201 is formed of resins 203 and 204 and is substantially optically isotropic in its in-plane direction and thickness direction.
US10270045B2	Semiconductor light-emitting element A semiconductor light-emitting element including a first semiconductor layer of a first conductivity type; a first light-emitting layer; a second light-emitting layer; and a second semiconductor layer of a conductivity type opposite to the conductivity type of the first semiconductor layer. The first light-emitting layer has a base layer with composition subject to stress strain from the first semiconductor layer and has a plurality of base segments partitioned into a random net shape; and a first quantum well structure layer composed of at least one quantum well layer and at least one barrier layer. The second light-emitting layer has a second quantum well structure layer composed of a plurality of barrier layers that have different compositions from that of the at least one barrier layer of the first quantum well structure layer, and at least one quantum well layer.
US10270039B2	Light-emitting element, display device, electronic device, and lighting device A light-emitting element with a lower voltage and higher emission efficiency is provided. The light-emitting element includes a first organic compound, a second organic compound, and a guest material. The LUMO level of the first organic compound is lower than the LUMO level of the second organic compound, and a difference between them is larger than 0 eV and smaller than or equal to 0.5 eV. Furthermore, the HOMO level of the first organic compound is lower than the HOMO level of the second organic compound. The guest material has a function of converting triplet excitation energy into light emission. The first organic compound and the second organic compound form an exciplex.
US10270038B2	Fullerene derivative, organic solar cell using same, and preparation method therefor The present disclosure relates to a fullerene derivative, an organic solar cell including the same, and a fabrication method thereof.
US10270035B2	Polymer, composition for organic electroluminescent element, organic electroluminescent element, organic EL display device, and organic EL lighting device The object of the present invention is to provide a polymer capable of being insolubilized at a low temperature in a short time, having a high hole injecting and transporting ability and a high durability, and a composition for organic electroluminescent element comprising the polymer. The polymer of the present invention comprises a specific crosslinkable group.
US10270032B2	Light source and a manufacturing method therewith A method of forming a device includes emitting a coherent light beam and providing a mask including a region transparent to the light beam. The method further includes projecting the light beam on a photosensitive layer through the transparent region of the mask. The method further includes forming a recess in the photosensitive layer, wherein the recess corresponds to a position of the transparent region of the mask. The method further includes filling an organic light emitting material in the recess.
US10270029B2	Resistive switching memory stack for three-dimensional structure A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.
US10270028B1	Memory device and method for manufacturing the same A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.
US10270026B2	Multilayered spacer structure for a magnetic tunneling junction and method of manufacturing A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a magnetic tunneling junction (MTJ) over the bottom electrode; a top electrode over the MTJ; a spacer, including: a first spacer layer including SiN with a first atom density, the first spacer layer laterally encompassing the MTJ; and a second spacer layer including SiN with a second atom density different from the first atom density, the second spacer layer laterally encompassing at least a portion of the first spacer layer; and an (N+1)th metal layer over the top electrode. A method for manufacturing a semiconductor structure is also disclosed.
US10270025B2	Semiconductor structure having magnetic tunneling junction (MTJ) layer The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
US10270023B2	Thermoelectric material, thermoelectric module, optical sensor, and method for manufacturing thermoelectric material A thermoelectric material includes a plurality of first semiconductor members having first band gap energy and a second semiconductor member having second band gap energy higher than the first band gap energy. The first semiconductor member and the second semiconductor member are alternately arranged in a direction of carrier transport. The first semiconductor member has a width in the direction of carrier transport not greater than 5 nm and a distance between two adjacent first semiconductor members in the direction of carrier transport is not greater than 3 nm.
US10270022B2	LED (light-emitting diode) module and a light apparatus An LED chip module includes a first electrode plate and a second electrode plate. A first set of LED chip and a second set of LED chip are respectively set on the first electrode plate and the second electrode plate. The second set of LED chip is electrically connected to the first set of LED chip. A plastic shell is fixedly connected to the first electrode plate and the second electrode plate by injection molding to make the first electrode plate and the second electrode plate keep a predetermined space between each other and make a lower surface of the first electrode plate and a lower surface of the second electrode plate be respectively connected to two different polarity terminals of the power supply to drive the first set of LED chip and the second set of LED chip to emit light.
US10270020B2	LED package structure An LED package structure includes a first metal plate, a second metal plate, and a mold. The first metal plate has at least one first protrusion portion. The second metal plate has at least one second protrusion portion. The mold is disposed on the first metal plate and the second metal plate, in which the mold has a first side surface, a second side surface opposite to the first side surface, a third side surface, and a fourth side surface opposite to the third side surface. The first and second protrusion portion protrude respectively from the first side surface and the second side surface, and the first metal plate and the second metal plate are covered by the third side surface and the fourth side surface, in which a portion of the first side surface between the first edge and the first protrusion portion is a fracture surface.
US10270012B2	Light-emitting dies incorporating wavelength-conversion materials and related methods In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., a light-emitting or a light-detecting element) suspended in the binder and within the aperture of the frame.
US10270010B2	Substrate with transparent electrode and method for producing same Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization during a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.
US10270009B2	Light-emitting device and light-emitting device package having same Disclosed in an embodiment is a light emitting device comprising: a light-emitting structure having a first semiconductor layer, an active layer under the first semiconductor layer, and a second semiconductor layer under the active layer; a first contact layer disposed under the light-emitting structure; a reflective layer disposed under the first contact layer; a first electrode layer including a capping layer disposed under the reflective layer; a second electrode layer electrically connected with the first semiconductor layer; a protective layer disposed at the outer peripheral portion between the capping layer and the light-emitting structure; a barrier layer at an outer side of the reflective layer and made of a metal different from that of the reflective layer; and a support member disposed under the capping layer.
US10270007B2	Light emitting diode, method for manufacturing the same, and light emitting device module having the same A light emitting diode having improved light efficiency and enhanced reflectivity of a device by forming an insulating reflective part on a reflective electrode formed on the upper surface of a mesa. A mesa exposing part is formed on the outer periphery and/or in the interior region of the reflective electrode to expose a predetermined area of the upper surface of the mesa such that reflection at the mesa exposing part is performed by the insulating reflective part.
US10270005B2	Graphene light emitting display and method of manufacturing the same A graphene light emitting display and a method of manufacturing the same are disclosed. The method comprises: manufacturing a graphene oxide (GO) thin film on a surface of a substrate with a thin film transistor formed thereon; providing a photomask corresponding to the GO thin film to form a source electrode, a drain electrode and a graphene quantum dot layer of a graphene light emitting transistor; and wherein the photomask includes: a complete transparent part corresponding to the region in which the source electrode and the drain electrode are located; a light blocking part corresponding to the region in which the thin film transistor is located; and a semitransparent part corresponding to the region in which the graphene quantum dot layer is located; wherein an insulating layer and a water and oxygen isolating layer are formed sequentially on a surface of the substrate with the graphene light emitting transistor formed thereon.
US10269994B2	Liftoff process for exfoliation of thin film photovoltaic devices and back contact formation A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including Cu—Zn—Sn—S(Se)(CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer.
US10269992B2	Solar cell A solar cell has multiple busbar electrodes formed at intervals and multiple finger electrodes formed between the busbar electrodes. The finger electrodes comprise multiple finger parts connected only to one busbar electrode and multiple finger parts connected to only another busbar electrode. The adjacent multiple finger parts are connected to one another, and the adjacent multiple finger parts are connected to one another.
US10269991B2	Method of patterning a layer The present disclosure provides a method of patterning a polymeric layer based on the chemical reaction of two chemical compounds. One chemical compound is provided in the polymeric layer and another chemical compound is deposited on the polymeric layer by, for example, ink-jet printing. The method allows for fabrication of, for example, metallization patterns for solar cells electronic components, integrated devices and formation of selective doped areas in solar cells amongst others.
US10269988B2	Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
US10269987B2	Bidirectional Zener diode A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
US10269984B2	Thin film transistor, array substrate, and display apparatus, and fabrication methods thereof The present application discloses A thin film transistor (TFT), including: a substrate; a source-drain layer comprising a source electrode and a drain electrode over the substrate; and an active layer comprising a poly-Si pattern and an amorphous-Si pattern having contact with the poly-Si pattern over the substrate. The amorphous-Si pattern is between the poly-Si pattern and the source-drain layer; the source electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in a direction substantially perpendicular to a surface of the substrate; and the drain electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in the direction substantially perpendicular to the surface of the substrate.
US10269983B2	Stacked nanosheet field-effect transistor with air gap spacers Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.
US10269969B2	Semiconductor structures and methods with high mobility and high energy bandgap materials An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
US10269968B2	Semiconductor device including fin structures and manufacturing method thereof A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.
US10269962B2	Semiconductor device and method for manufacturing the same A semiconductor device has a fin-type structure which extends in a first direction and includes a laminate of oxide and semiconductor patterns disposed one on another on a first region of a substrate, and a first gate electrode that extends longitudinally in a second direction different from the first direction on the fin-type structure. Each oxide pattern is an oxidized compound containing a first element.
US10269960B2	Power MOSFETs manufacturing method Present application provides a method of manufacturing a semiconductor structure, including forming a well, forming a gate electrode over the well, implanting a lightly doped region in a first side of the well, implanting a first drain in the lightly doped region by a first depth, implanting a second drain in the lightly doped region by a second depth, implanting a source in a second side of the well, the second side being opposite to the first side. The second depth is greater than the first depth. The gate electrode is formed to cover a part of the lightly doped region and a part of the first drain.
US10269958B2	Semiconductor device and method of fabricating the same A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.
US10269956B2	Asymmetric vertical device A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.
US10269953B2	Semiconductor device having a trench gate A semiconductor device includes a gate structure extending from a first surface into a semiconductor portion and having a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion. An interlayer dielectric separates a first load electrode from the semiconductor portion, and includes a screen oxide layer thinner than the gate dielectric. A body zone and a source zone are formed in the semiconductor portion and directly adjoin the gate structure.
US10269949B2	Semiconductor structure, HEMT structure and method of forming the same A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
US10269946B2	Semiconductor device and method of manufacturing the same A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.
US10269941B2	Method for manufacturing semiconductor device It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
US10269938B2	Semiconductor device structure having a doped passivation layer A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin structure has sidewalls. The semiconductor device structure includes a passivation layer over the sidewalls. The passivation layer includes dopants. The dopants include at least one element selected from group 4A elements, and the dopants and the substrate are made of different materials. The semiconductor device structure includes an isolation layer over the base and surrounding the fin structure and the passivation layer. A first upper portion of the fin structure and a second upper portion of the passivation layer protrude from the isolation layer. The semiconductor device structure includes a gate electrode over the first upper portion of the fin structure and the second upper portion of the passivation layer.
US10269935B2	Semiconductor device including Fin-PET and manufacturing method thereof A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.
US10269931B2	Vertical transport field effect transistor with precise gate length definition Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
US10269930B2	Method for producing a semiconductor device with self-aligned internal spacers Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
US10269928B2	Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.
US10269927B2	Semiconductor structures and fabrication methods thereof A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a core region of a substrate and a plurality of second fin structures in a peripheral region of the substrate, forming a first dummy gate structure including a first dummy gate oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second gate oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate electrode layer, performing an ion implantation process to tune the threshold voltages of the first fin structures, and removing each first dummy gate oxide layer. The method also includes removing each second dummy gate electrode layer, and forming a gate dielectric layer and a metal layer on each first fin structure and each second fin structure.
US10269924B2	High selectivity nitride removal process based on selective polymer deposition A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
US10269923B2	HEMTs with an AlxGa1-xN barrier layer grown by plasma enhanced atomic layer deposition In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
US10269920B2	Nanosheet transistors having thin and thick gate dielectric material Provided is a method for forming a semiconductor structure. In embodiments, the method includes forming multiple channel nanosheets in multiple first stacks over a substrate. The channel nanosheets in the first stack define first stack cavities such that each pair of adjacent stacked channel nanosheets in the first stack is separated by one of the first stack cavities. The method further includes forming multiple channel nanosheets in a second stack over a substrate. The channel nanosheets in the second stack defining second stack cavities such that each pair of adjacent stacked channel nanosheets in the first second is separated by one of the second stack cavities. The method further includes filling the first stack cavities with a first gate dielectric material and filling the second stack cavities with a work function metal and a second gate dielectric material. The first gate dielectric material differs from the second gate dielectric material.
US10269915B2	Vertical MOS transistor and fabricating method thereof A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.
US10269905B2	Structure for reduced source and drain contact to gate stack capacitance A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer.
US10269902B2	Semiconductor device and method of formation A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
US10269901B2	Semiconductor liner of semiconductor device The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant.
US10269895B2	Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
US10269893B2	Method and system for MOM capacitance value control A method for MOM capacitance value control is disclosed. The method comprises: S01: setting a target thicknesses for each metal layers; S02: after forming a current metal layer, measuring a thickness of the current metal layer; when the thickness of the current metal layer is equal to or less than a threshold value, then turning to step S03; S03: calculating multiple capacitance variations related to the current metal layer according to the thickness of the current metal layer; wherein each of the capacitance variation related to the current metal layer is between an actual capacitance value of a MOM capacitor combination associated with the current metal layer and a target capacitance value of the same MOM capacitor combination; S04: calculating updated target thicknesses for all subsequent metal layers according to the capacitance variations related to the current metal layer.
US10269892B2	Organic light-emitting display apparatus and manufacturing method thereof An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display unit arranged on the substrate, a dam unit arranged at a periphery of the display unit and on the substrate and an encapsulating layer to encapsulate the display unit, wherein the encapsulating layer includes an organic film covering the display unit, and an inorganic film covering the organic film and the dam unit, and wherein a hardness of the dam unit is lower than that of the inorganic film. According to this, lateral moisture-proof characteristics of the organic light-emitting display apparatus are improved.
US10269891B2	Display device and method of manufacturing the same A display device includes a substrate including a bending area, a display area. A plurality of first wires is disposed above the substrate. A second wire is disposed above the plurality of first wires. A third wire is disposed above the second wire. At least a portion of the second wire and at least a portion of the third wire are disposed in the bending area.
US10269890B2	Display device having notched connection wiring A display device includes a substrate including a display region, a pad region spaced apart from the display region, and a bending region between the display region and the pad region. A plurality of pixel structures is positioned in the display region of the substrate. A plurality of pad wirings is positioned in the pad region of the substrate. A plurality of connection wirings electrically connect the pad wirings to the pixel structures. The connection wirings include a plurality of notches in the bending region.
US10269886B2	Organic electroluminescent display device and manufacturing method thereof An organic electroluminescent display device and a manufacturing method thereof are disclosed. The organic electroluminescent display device includes a substrate, a first thin film transistor disposed on the substrate, a second thin film transistor disposed on the first thin film transistor, a first light emitting element electrically connected with a drain of the first thin film transistor, wherein the first light emitting element comprises a first electrode, a first light emitting layer and a second electrode which are stacked, a second light emitting element electrically connected with a drain of the second thin film transistor, wherein the second light emitting element is disposed on the second thin film transistor and comprises a third electrode, a second light emitting layer and a fourth electrode, wherein the second light emitting element is configured to emit white light. By forming the second light emitting element on the second thin film transistor, an original non-display region of the organic electroluminescent display device becomes a display region, as a result, an aperture ratio of the organic electroluminescent display device is increased, and the display effect of the organic electroluminescent display device is improved.
US10269884B2	Organic light emitting display having an insulating layer and a metal layer forming a capacitor Organic light-emitting display is disclosed. The organic light-emitting display includes a first substrate, a semiconductor layer positioned on the first substrate, a first insulating layer positioned on the semiconductor layer, a gate metal layer positioned on the first insulating layer, a second insulating layer with a contact hole exposing part of the gate metal layer, a source-drain metal layer positioned on the second insulating layer and electrically connected to the gate metal layer via the contact hole, a third insulating layer positioned on the source-drain metal layer, a fourth insulating layer positioned on the third insulating layer, and a pixel electrode positioned on the fourth insulating layer, wherein the fourth insulating layer fully covers the contact hole, and a stepped portion of the pixel electrode caused by the fourth insulating layer is spaced apart from the contact hole.
US10269878B2	Organic EL display panel and organic EL display device An organic EL display panel includes plural streaks of first partition walls 16 on the upper side of an underlying layer 13 in such a manner that each of the plural streaks of the first partition walls 16 extends along a first direction, plural streaks of second partition walls 14 that are on the upper side of the underlying layer 13 in such a manner that each of the plural streaks of the second partition walls 14 extends along a second direction intersecting the first direction, and each have an upper surface 14a at a position lower than upper surfaces 16a of the first partition walls 16, and a light emitting layer 17 formed along the first direction on the upper side of the underlying layer 13 and in gaps 20 between the first partition walls 16 adjacent to each other in such a manner as to get over the plural streaks of the second partition walls 14. An organic EL display panel in which luminance unevenness is suppressed is thereby obtained.
US10269877B2	Display device A display device is disclosed. In one aspect, a plurality of pixels are formed in a display area, and the pixels include a first pixel including a thin film transistor (TFT). The display device includes a test unit formed in a peripheral area surrounding the display area, and the test unit includes a test transistor configured to measure a characteristic of the TFT included in the first pixel. The display device also includes a first insulating layer formed over the test transistor and the display area, and a plurality of dummy contact holes are formed in the first insulating layer and the test unit.
US10269870B2	Organic light-emitting device, production method thereof, and display apparatus This disclosure discloses an organic light-emitting device, a production method thereof, and a display apparatus, and belongs to the technical field of display. The organic light-emitting device comprises: a first electrode; a second electrode; a first light-emitting layer provided between the first electrode and the second electrode; a spacing layer provided between the first light-emitting layer and the second electrode; and a light intensity compensation layer provided between the spacing layer and the second electrode, wherein the color of light emitted from the light intensity compensation layer is the same as that of the first light-emitting layer, and when a recombination area of electrons and holes in the first light-emitting layer moves, the light intensity compensation layer limits the recombination area in the light intensity compensation layer and compensates the light intensity of the first light-emitting layer.
US10269866B2	Magnetoresistive element and magnetic memory A magnetoresistive element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a first nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer, the first ferromagnetic layer including (MnxGay)100-zPtz, the (MnxGay)100-zPtz having a tetragonal crystal structure, where 45 atm %≤x≤75 atm %, 25 atm %≤y≤55 atm %, x+y=100 atm %, and 0 atm %
US10269865B2	Light emitting device and manufacturing method of the light emitting device A light-emitting device includes: a substrate; a unit light-emitting area disposed on the substrate; first and second electrodes disposed in the unit light-emitting area to be separated from each other; a plurality of rod-shaped LEDs disposed between the first and second electrodes; a reflective contact electrode disposed on opposite ends of the rod-shaped LEDs to electrically connect the rod-shaped LEDs to the first and second electrodes; and a light-transmitting structure disposed between the first and second electrodes and extending to cross the rod-shaped LEDs.
US10269863B2	Methods and apparatus for via last through-vias Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
US10269862B2	High efficiency wide spectrum sensor An optical sensor including a first material layer comprising at least a first material; a second material layer comprising at least a second material that is different from the first material, where a material bandgap of the first material is larger than a material bandgap of the second material; and a graded material layer arranged between the first material layer and the second material layer, the graded material layer comprising an alloy of at least the first material and the second material having compositions of the second material that vary along a direction that is from the first material to the second material.
US10269860B2	Sensor element, image sensor, methods of forming and operating the same A sensor element for sensing optical light may be provided. The sensor element may include a first electrode for electrically coupling to a first supply voltage, a second electrode for electrically coupling to a second supply voltage, and an oxide dielectric element between the first electrode and the second electrode. The oxide dielectric element may be configured to form a conductive filament upon a potential difference between the first supply voltage and the second supply voltage exceeding a threshold level, thereby decreasing a resistance of the oxide dielectric element. The sensor element may also include a detector. The first electrode may be configured to allow the optical light to pass through the first electrode to the oxide dielectric element. The detector may be configured to detect an increase in the resistance of the oxide dielectric element upon the oxide dielectric element receiving the optical light.
US10269857B2	Image sensor comprising reflective guide layer and method of forming the same Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.
US10269856B2	Semiconductor integrated circuit, electronic device, solid-state imaging apparatus, and imaging apparatus A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.
US10269851B2	Methods and apparatus for sensor module Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.
US10269848B2	Image sensor having enhanced backside illumination quantum efficiency A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
US10269841B1	Sensor package and method of manufacturing the same A sensor package includes a sensor, an encapsulation layer, a redistribution layer, a photo-imageable dielectric (PID) layer and via plugs. The encapsulation layer exposes the active surface of the sensor, and the top surface of the encapsulation layer is coplanar with the active surface of the sensor. The redistribution layer covers the top surface of the encapsulation layer and the active surface of the sensor. The PID layer covers the redistribution layer, the encapsulation layer and the active surface of the sensor. The via plugs are disposed around the sensor and through the encapsulation layer. The via plugs are electrically connected to the redistribution layer and the active surface of the sensor. The cross section of the via plug at the top surface of the encapsulation layer has a first hole diameter, and the cross section of the via plug at the bottom surface of the encapsulation layer has a second hole diameter. The first hole diameter is less than the second hole diameter.
US10269840B2	Image sensing device and manufacturing method thereof The image sensing device includes a pixel region in a pixel array area and a dummy pixel region in a periphery area. The pixel region includes a radiation region, a floating diffusion region, a transfer transistor, a source-follower transistor, a reset transistor and a select transistor. The dummy pixel region includes a radiation region and a floating diffusion region. A gate of one of the transfer transistor, the reset transistor and the select transistor in the pixel region is electrically connected to the radiation region or the floating diffusion region in the dummy pixel region.
US10269837B2	Sensor, manufacturing method thereof and electronic device A sensor, a manufacturing method thereof and an electronic device. The sensor includes: a base substrate; a thin-film transistor (TFT) disposed on the base substrate and including a source electrode; a first insulation layer disposed on the TFT and provided with a first through hole running through the first insulation layer; a conductive layer disposed in the first through hole and on part of the first insulation layer and electrically connected with the source electrode via the first through hole; a bias electrode disposed on the first insulation layer and separate from the conductive layer; a sensing active layer respectively connected with the conductive layer and the bias electrode; and an auxiliary conductive layer disposed on the conductive layer. The sensor and the manufacturing method thereof improve the conductivity and ensure normal transmission of signals by arranging the auxiliary conductive layer on the conductive layer without addition of processes.
US10269836B2	Display apparatus and method of manufacturing the same A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.
US10269833B2	Semiconductor device and display device A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.
US10269827B2	Electronic device having stacked structures A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
US10269825B2	Semiconductor device and method for manufacturing same According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
US10269823B2	Flash memory semiconductor device The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.
US10269818B2	Semiconductor device and manufacturing method thereof A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
US10269814B2	Method of fabricating semiconductor structure The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.
US10269813B2	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.
US10269799B2	Field effect transistor contact with reduced contact resistance The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
US10269795B2	Semiconductor structure and manufacturing method thereof A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
US10269792B2	Structure and method for FINFET device A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.
US10269789B2	Protection circuit for integrated circuit die-let after scribe cut A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.
US10269781B1	Elastomeric layer fabrication for light emitting diodes An elastomeric interface layer (elayer) is formed over multiple light emitting diode (LED) dies by depositing photoresist materials across multiple LED dies, and using the LED dies as a photolithography mask to facilitate formation of the elayer on each LED die. The elayer facilitates adhesive attachment of each LED die with a pick and place head (PPH), allowing the LED dies to be picked up and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (μLED) dies.
US10269779B2	Micro light-emitting-diode display panel and manufacturing method thereof A micro light emitting-diode display panel and a manufacturing method thereof are provided. The first electrode contact and the second electrode contact are alternatively disposed on the base substrate of the micro light-emitting-diode display panel, and the first electrode contact and the second electrode contact are respectively connected with the bottom electrode and the connection electrode of the micro light-emitting-diode. The connection electrode is also connected with the top electrode of the micro light-emitting-diode, and the micro light-emitting-diodes can be immediately inspected after the micro-light-emitting-diode is transferred, to reduce the difficulty of detection and product repair, and to improve the product yield.
US10269775B2	Semiconductor device and method for manufacturing semiconductor device A semiconductor device has a first board (10); and an intermediate layer (20) being provided on the first board (10) and having a plurality of connectors (31), (41). The first board (10) has a positioning section (5) that positions the intermediate layer (20). The intermediate layer (10) is provided with a positioning insertion section (37), (47), into which the positioning section (5) is inserted.
US10269772B2	Input output for an integrated circuit A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers of the three-dimensional integrated circuit. The input output circuit has first and second input output circuitry, wherein the first input output circuitry operates faster than the second input output circuitry.
US10269771B2	Semiconductor device package and a method of manufacturing the same A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
US10269770B2	Hybrid bond pad structure In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.
US10269764B2	Discrete polymer in fan-out packages A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
US10269754B2	Semiconductor device A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.
US10269753B2	Semiconductor device and manufacturing method of semiconductor device The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate including a recess in a surface of the electrode plate, the specified area being adjacent to the recess. The manufacturing method of a semiconductor device includes placing a semiconductor chip on the conductive paste so that an outer peripheral edge of the semiconductor chip is located above the recess. The manufacturing method of a semiconductor device includes hardening the conductive paste by heating the conductive paste while applying pressure to the semiconductor chip in a direction toward the electrode plate.
US10269752B2	Package with UBM and methods of forming Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.
US10269748B2	Semiconductor device and manufacturing method of semiconductor device A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.
US10269746B2	Methods and apparatus for transmission lines in packages Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
US10269744B2	Semiconductor device with thin redistribution layers A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.
US10269737B2	Method for manufacturing semiconductor structure A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.
US10269727B2	Composite magnetic sealing material and electronic circuit package using the same as mold material Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blend ratio of 50 vol. % or more and 85 vol. % or less. The filler includes a first magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material composed mainly of Ni, the first magnetic filler having a first grain size distribution, and a second magnetic filler having a second grain size distribution different from the first grain size distribution.
US10269721B2	Fan-out semiconductor package A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.
US10269720B2	Integrated fan-out packaging The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
US10269719B2	Multilevel light emitting LED substrate, package and bulb A multilevel light emitting LED substrate and package, and bulb, comprising multiple annular substrates disposed at intervals, wherein every two adjacent annular substrates among the multiple annular substrates are connected by using at least one connection part, and the the connection part is stretched and shaped such that the multiple annular substrates are located in different planes to form a three-dimensional structure, By means of the multilevel light emitting LED substrate and package, and the bulb, a planar LED substrate and package can be processed to be a three-dimensional structure; the process is convenient, the structure is simple, and it is easy to set and control LED chips; moreover, the process efficiency is high, so that the LED package is not easily damaged in the process, and the production efficiency and yield are improved.
US10269718B2	Rectangular semiconductor package and a method of manufacturing the same A rectangular semiconductor package and a method manufacturing the same described in the present disclosure features no carrier installed on a die cut from a wafer. In an embodiment, a first die on a top surface of a conductive routing layer is electrically connected to the conductive routing layer through a plurality of first metal wires, a plurality of conductive balls is installed on a bottom surface of the conductive routing layer, and a molding compound is used to encase the first die on the conductive routing layer. In another embodiment, a second die is added in the above rectangular semiconductor package and encased in the molding compound, as is the first die. Alternatively, the molding compound is processed such that the second die encapsulated in a package is stacked on the molding compound and electrically connected to the conductive routing layer.
US10269716B2	Device, system and method to interconnect circuit components on a transparent substrate Techniques and mechanisms for interconnecting circuitry disposed on a transparent substrate. In an embodiment, a multilayer circuit is bonded to the transparent substrate, the multilayer circuit including conductive traces that are variously offset at different respective levels from a side of the transparent substrate. Circuit components, such as packaged or unpackaged integrated circuit devices, are coupled each to respective input and/or output (IO) contacts of the multilayer circuit, where the conductive traces and the IO contacts interconnect the circuit components with each other. In another embodiment, the multilayer circuit is a flexible circuit that is bent to interconnect circuit components which are disposed on opposite respective sides of the transparent substrate.
US10269708B2	Increased contact alignment tolerance for direct bonding A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
US10269705B2	Semiconductor structure and manufacturing method thereof A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
US10269704B2	Semiconductor device and method A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
US10269702B2	Info coil structure and methods of manufacturing same A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil.
US10269701B2	Semiconductor structure with ultra thick metal and manufacturing method thereof The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.
US10269699B2	Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
US10269695B2	Method for forming an electrical device and electrical devices A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
US10269675B2	Conductive line system and process A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.
US10269674B2	Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
US10269672B2	Semiconductor package device and method of manufacturing the same A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.
US10269670B2	Curable silicone resin composition, silicone resin composite, photosemiconductor light emitting device, luminaire and liquid crystal imaging device A curable silicone resin composition is provided, including (A) a curable silicone resin-forming component of which a viscosity is 0.02 Pa·s or greater and 100 Pa·s or less, (B) surface-modified metal oxide particles which are surface-modified by a surface-modifying material having a reactive functional group and have an average primary particle diameter of 3 nm or more and 10 nm or less, and (C) a silicone compound having a reactive functional group of which a viscosity is less than the viscosity of the (A) component and is 0.01 Pa·s or greater and 1.0 Pa·s or less and having a content of 0.1% by mass or more and 15% by mass or less based on a total amount of the composition, in which a viscosity is 1.0 Pa·s or greater and 100 Pa·s or less.
US10269665B2	Semiconductor device for sensor application using contacts located on top surface and bottom surface and method for fabricating thereof A semiconductor device and a method of fabricating the same are disclosed. A semiconductor device according to an embodiment of the present invention includes: a first type doped semiconductor substrate; a second type doped deep well configured such that one or more semiconductor device elements are formed therein; a first type doped first well formed inside a region surrounded by the deep well of the one surface of the semiconductor substrate, and separated from the semiconductor substrate by the deep well; a first electrical contact formed on a part of the one surface of the semiconductor substrate, and electrically connected to the first well; and a second electrical contact formed on another surface of the semiconductor substrate.
US10269664B2	Semiconductor structure and method for forming the same A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
US10269661B2	Manufacturing system for semiconductor device, method of manufacturing semiconductor device, and control device According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device.
US10269660B2	Metrology sampling method with sampling rate decision scheme and computer program product thereof In a metrology sampling method with a sampling rate decision scheme, a mean absolute percentage error (MAPE) and a maximum absolute percentage error (MaxErr) of visual metrology values of all workpieces in a set of determinative samples (DS), and various index values that can detect various status changes of a process tool (such as maintenance operation, parts changing, parameter adjustment, etc.), and/or information abnormalities of the process tool (such as abnormal process data, parameter drift/shift, abnormal metrology data, etc.) appearing in a manufacturing process are applied to develop an automated sampling decision (ASD) scheme for reducing a workpiece sampling rate while VM accuracy is still sustained.
US10269655B1	Semiconductor device and method An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
US10269652B2	Vertical transistor top epitaxy source/drain and contact structure An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
US10269651B2	Fin field effect transistor (FinFET) device structure and method for forming the same A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.
US10269650B2	Structure and formation method of semiconductor device structure Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
US10269648B1	Method of fabricating a semiconductor device structure Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.
US10269643B2	Method and device for the production of wafers with a pre-defined break initiation point The present invention relates to a method for the production of layers of solid material, in particular for use as wafers. The method may include the following steps: providing a workpiece for the separation of the layers of solid material with the workpiece optionally having at least one exposed surface, producing and/or providing a carrier unit for receiving at least one layer of solid material having the carrier unit optionally having a receiving layer for holding the layer of solid material, attaching the receiving layer to the exposed surface of the workpiece forming a composite structure, producing a break initiation point by means of pre-defined local stress induction in the peripheral region, including at the edge, of the workpiece, and separating the layer of solid material from the workpiece starting from the break initiation point.
US10269641B2	Method and apparatus for plasma dicing a semi-conductor wafer The present invention provides a method for plasma dicing a substrate. The substrate is provided with a top surface and a bottom surface, the top surface of the substrate having a plurality of street areas and at least one device structure. The substrate is placed onto a support film on a frame to form a work piece. A process chamber having a plasma source is provided. A work piece support is provided within the plasma process chamber. The work piece is placed onto the work piece support. A plasma is generated from the plasma source in the plasma process chamber. The work piece is processed using the generated plasma and a byproduct generated from the support film while the support film is exposed to the generated plasma.
US10269639B2	Method of manufacturing packaged wafer Disclosed herein is a method of manufacturing a packaged wafer including a step of forming grooves in a face side of a wafer along projected dicing lines to a depth larger than a finished thickness of the wafer, a step of forming a ring-shaped groove in and along a boundary between a device area and an outer peripheral excess area of the wafer to a depth larger than the depth of the grooves, and a step of placing a recess mold of a molding apparatus in engagement with the wafer so that a side wall of the recess mold is placed on a bottom of the ring-shaped groove and filling a space between the recess mold and the wafer with a molding resin.
US10269635B2	Integrated circuit substrate and method for manufacturing the same A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.
US10269632B2	Semiconductor device and method A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.
US10269631B2	Manufacturing method of semiconductor device As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process. Next, the back surface of a semiconductor substrate is cleaned by spraying a cleaning chemical liquid toward the back surface thereof, and a portion of the barrier metal film located in the outer peripheral portion is removed by causing the cleaning chemical liquid to wrap around toward the surface side of the outer peripheral portion from the back surface side. Next, a tungsten film is formed to cover the barrier metal film by a CVD process.
US10269628B2	FinFET low resistivity contact formation method A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
US10269627B2	Interconnect structure and method A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
US10269626B2	Stair step formation using at least two masks Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
US10269625B1	Methods of forming semiconductor structures having stair step structures A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.
US10269623B2	Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.
US10269622B2	Materials and deposition schemes using photoactive materials for interface chemical control and patterning of predefined structures Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.
US10269619B2	Wafer level chip scale packaging intermediate structure apparatus and method Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
US10269618B2	FETS and methods of forming FETS An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.
US10269611B1	Method and apparatus for bonding semiconductor devices A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
US10269609B2	Wafer level flat no-lead semiconductor packages and methods of manufacture Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
US10269606B2	Two-link arm trajectory Providing a first movement including rotating a first arm about a rotational axis of a robot drive; rotating a second arm on the first arm, where the first and second arms form a robot arm, where the first and second arms are the only arms of the robot arm, where the robot arm has an end effector rotationally fixed to the second arm, and where the end effector is configured to support a substrate thereon for transporting the substrate by the robot arm; and controlling the rotating to provide a path of the end effector such that the end effector does not contact the substrate during the rotating. Providing a second movement including rotating the arms to provide an at least partially straight linear path of a center of the substrate relative to the rotational axis of the drive robot when the substrate is on the end effector.
US10269604B2	Substrate transport vacuum platform An apparatus including a first device configured to support at least one substrate thereon; and a first transport having the device connected thereto. The transport is configured to carry the device. The transport includes a plurality of supports which are movable relative to one another along a linear path; at least one magnetic bearing which at least partially couples the supports to one another. A first one of the magnetic bearings includes a first permanent magnet and a second magnet. The first permanent magnet is connected to a first one of the supports. A magnetic field adjuster is connected to the first support which is configured to move the first permanent magnet and/or vary influence of a magnetic field of the first permanent magnet relative to the second magnet.
US10269603B2	Substrate processing apparatus, gas-purging method, method for manufacturing semiconductor device, and recording medium containing abnormality-processing program A substrate processing apparatus includes a process chamber configured to process a substrate, a carrier mounting part configured to mount a carrier which accommodates the substrate, the substrate capable of being brought into and out of the carrier when a door of the carrier mounted on the carrier mounting part is opened, a carrier opener configured to open and close the door of the carrier mounted on the carrier mounting part, a purge gas supply part configured to supply an inert gas into the carrier with the door kept opened, and a control part configured to perform control so as to carry out at least one inert gas purge among a load purge, an unload purge and a standby purge.
US10269602B1	Wafer warpage inspection system and method using the same The present disclosure provides a system for wafer warpage inspection including a heatable susceptor configured to heat a wafer according to a predetermined temperature profile. The system for wafer warpage inspection further includes a confocal imager array over the heatable susceptor configured to capture one or more warpage parameters of the wafer. Each confocal imager of the confocal imager array covers a predetermined field of view (FOV). The system for wafer warpage inspection further includes a first actuator permitting the confocal imager array to move in a plurality of directions. The system for wafer warpage inspection further includes a processing unit connected to the confocal imager array. The processing unit is configured to dynamically process the one or more warpage parameters captured during the heating of the wafer according to the predetermined temperature profile. Present disclosure also provides a method for wafer warpage inspection described herein.
US10269597B2	Manufacturing apparatus of light-emitting element Disclosed is a manufacturing apparatus of a light-emitting element. The manufacturing apparatus includes: a main transporting route including a first transfer device and a second transfer device connected to each other through a first transporting chamber; a sub-transporting route extending in a direction intersecting the main transporting route, the sub-transporting route including: a second transporting chamber connected to the first transfer device or the second transfer device; and a delivery chamber connected to the second transporting chamber; and a plurality of treatment chambers connected to the delivery chamber. A region to which the first transfer device, the second transfer device, the first transporting chamber, and the second transporting chamber are connected is under a continuous vacuum environment.
US10269595B2	Seal for wafer processing assembly A seal having a cross-sectional profile that includes a first lobe, a second lobe, and a corner having an angle between 45 and 90 degrees, inclusive, a first side extending from the first lobe to the corner and a second side extending from the second lobe to the corner, where the first side and the second side define the corner angle. The seal can be seated in a groove so that the first lobe and the corner are in the groove and the second lobe extends from the groove. In use, the second lobe folds into the groove to form a fluid-tight seal.
US10269587B2	Integrated circuit packages and methods of forming same An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.
US10269584B2	3D packages and methods for forming the same Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
US10269583B2	Semiconductor die attachment with embedded stud bumps in attachment material The embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a die attachment pad; a stud bump located on the die attachment pad and in direct contact with the die attachment pad; a first die located on the stud bump and electrically coupled to the stud bump; and a conductive attachment material located between the die attachment pad and the first die.
US10269576B1	Etching and structures formed thereby Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.
US10269575B2	Semiconductor device with non-linear surface A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.
US10269572B2	Semiconductor device and manufacturing method thereof A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.
US10269562B2	Use of at least one binary group 15 element compound, a 13/15 semiconductor layer and binary group 15 element compounds The invention provides the use of at least one binary group 15 element compound of the general formula R1R2E-E′R3R4 (I) or R5E(E′R6R7)2 (II) as the educt in a vapor deposition process. In this case, R1, R2, R3 and R4 are independently selected from the group consisting of H, an alkyl radical (C1-C10) and an aryl group, and E and E′ are independently selected from the group consisting of N, P, As, Sb and Bi. This use excludes hydrazine and its derivatives. The binary group 15 element compounds according to the invention allow the realization of a reproducible production and/or deposition of multinary, homogeneous and ultrapure 13/15 semiconductors of a defined combination at relatively low process temperatures. This makes it possible to completely waive the use of an organically substituted nitrogen compound such as 1.1 dimethyl hydrazine as the nitrogen source, which drastically reduces nitrogen contaminations—compared to the 13/15 semiconductors and/or 13/15 semiconductor layers produced with the known production methods.
US10269552B2	Gas discharge lamp and a device for controlling the temperature thereof The present invention relates to a device for the regulated temperature control of a gas discharge lamp, and a gas discharge lamp. The device according to the invention includes a transformer core of a transformer, the transformer core being designed for accommodating at least one discharge current-conducting connecting line of the gas discharge lamp as a primary winding. The transformer forms an energy source for heating a functional area of the gas discharge lamp that determines a function of the gas discharge lamp, and that is formed by an amalgam reservoir. The device also includes a secondary winding on the transformer core, and a means for temperature control that is used to regulate the energy that heats the amalgam reservoir. The means for temperature control is electrically connected to the secondary winding.
US10269551B2	High-pressure discharge lamp having an ignition aid The invention relates to a high-pressure discharge lamp having an ignition aid and comprising a discharge vessel, which is accommodated in an outer bulb. The ignition aid is a UV enhancer having a can-like container (12), which has an inner electrode (18). At least part of the end-face edge of the inner electrode at least comes close to the end face (24) of the container (12). An external electrode is attached to the outside of the container.
US10269544B2	Gas ring for plasma system and method of manufacturing the same A gas ring for a plasma system includes a gas ring body having a surface and an insulating protective layer covering the surface. Methods of manufacturing the gas ring are also provided.
US10269543B2	Lower electrode and plasma processing apparatus A lower electrode 2 includes a conductive base member 2a to which a high frequency power is applied; an electrostatic chuck 6, having an insulating layer 6b formed on a top surface of the base member 2a to cover an electrode 6a, configured to electrostatically attract a semiconductor wafer W as a target of a plasma process onto the insulating layer 6b; a focus ring 5 provided on a top surface of the insulating layer 6b of the electrostatic chuck 6 to surround the semiconductor wafer W; and a thermally sprayed film 100, which is conductive and formed on a portion of the insulating layer 6b of the electrostatic chuck 6 positioned between the focus ring 5 and the base member 2a by using a composite material in which titania is added to an insulating material for the insulating layer at a preset weight ratio.
US10269540B1	Impedance matching system and method of operating the same An impedance matching system includes an impedance matching network coupled between an alternating current (AC) generator and electrodes of a plasma chamber. The AC generator is configured to generate a multi-level pulse signal of cyclically recurring pulse intervals with differing amplitude levels. A controller or other device identifies each recurring pulse interval, and for each pulse interval, determines an impedance mis-match level between the AC generator and the electrodes, adjusts a configuration of the impedance matching network according to the determined impedance mis-match level, and stores information associated with the adjusted configuration. When an ensuing pulse interval occurs, the controller obtains the stored information from memory, adjusts the configuration of the impedance matching network according to the stored information, determines another impedance mis-match level between the AC generator and the electrodes, and adjusts the configuration of the impedance matching network to iteratively reduce the impedance mismatch level.
US10269537B2	Vacuum assembly for an ion implanter system In one embodiment a vacuum assembly for an ion implanter system includes a first turbomolecular pump operatively coupled to a source chamber of the ion implanter system and a first backing line having a first end and a second end, the first end coupled to an exhaust port of the first turbomolecular pump, wherein the first turbomolecular pump and first end of the first backing line are configured to operate at a voltage potential of the source chamber. The vacuum assembly further includes a voltage insulator that is insulatively coupled to the first backing line, and a second turbomolecular pump operatively coupled to the first backing line, wherein the second turbomolecular pump is configured to operate at ground voltage potential.
US10269533B2	Anti-contamination trap, and vacuum application device In conventional structures, a space between a dual cooling tank is vacuum insulated, and a cooling part is cooled via a highly thermally conductive material connected to an inner container. Such structures are affected by heat infiltrating into the highly thermally conductive material and the cooling part. For instance, in cases when liquid nitrogen is used as a coolant, it takes approximately 30 minutes for the temperature to reach −120° C. Even in cases when a significant amount of time has been spent, the temperature only reaches approximately −150° C., and thus falls significantly short of the temperature of liquid nitrogen, namely −196° C. Accordingly, an anti-contamination trap and a vacuum application device according to the present invention are provided with a structure in which a device-internal cooling part in the vacuum application device is cooled, and are characterized by being provided with: a cooling tank filled with a coolant for cooling a cooling part; and a cooling pipe extending from the cooling tank to the vicinity of the cooling part. The anti-contamination trap and the vacuum application device are further characterized in that: the coolant is supplied to an end of the cooling part; and a tube for releasing air bubbles inside the cooling pipe is inserted so as to extend to the cooling part.
US10269527B2	Electron emitting construct configured with ion bombardment resistant An electron emitting construct design of an x-ray emitter device is disclosed configured to facilitate radiation in the X-ray spectrum and further relates to preventing a cold cathode from being damaged by ion bombardment in high-voltage applications. The electron beam emitted by the emitting construct is focused and accelerated by an electrical field towards an electron anode target operable to attract electron beam to an associated focal spot, wherein the generated ions are accelerated along a trajectory perpendicular to the electric field in parallel to the surface of the electron anode target. More specifically, the present invention relates to realizing a robust cold cathode to avoid ion bombardments damages in high-voltage applications, by means of setting non-emitter zone surrounded by or set between the emitter areas. The system is further configured to provide an angled target anode or a stepped target anode to further reduce the ion bombardment damage.
US10269524B2	Multiple fuse device The present invention provides a multiple fuse device that is compatible with various ratings and reduces an increase in manufacturing cost. A multiple fuse device includes an input terminal, an external terminal, a bus bar that includes a circuit portion disposed between the input terminal and the external terminal, and a housing that covers the bus bar. The external terminal includes an integral external terminal integrated with the circuit portion with a fusible portion interposed between the integral external terminal and the circuit portion, and a fuse-side external terminal that pairs up with a fuse connection terminal connected to the circuit portion. The fuse connection terminal and the fuse-side external terminal provided in a pair hold a fuse exteriorly in a removable manner, the fuse having a fusible portion connected between the fuse connection terminal and the fuse-side external terminal.
US10269523B2	Protection element The present invention aims to achieve a Pb-free protection element by using a layered body including a high melting point metal layer and a low melting point metal layer. A protection element includes an insulating substrate, a heating body, an insulating member, two electrodes, a heating body extraction electrode, and a fusible conductor. Furthermore, the fusible conductor includes a layered body including at least a high melting point metal layer and a low melting point metal layer, and the low melting point metal layer is melted by a heat generated by the heating body, whereby, while eroding the high melting point metal layer, the low melting point metal layer is drawn close to the side of the two electrodes and the heating body extraction electrode, and fused, the two electrodes and the heating body extraction electrode each having high wettability for the low melting point metal layer.
US10269521B2	Mounting structure for energy storage assembly of circuit breaker A mounting structure for an energy storage assembly of a circuit breaker comprises an energy storage lever and an energy storage spring, wherein one end of the energy storage lever is an energy storage end which is connected with the energy storage spring, and the other end of the energy storage lever is a driving end. An external force can be applied to the driving end, such that the energy storage lever rotates around a lever fulcrum in the middle of the energy storage lever, thereby extruding the energy storage spring at the energy storage end to finish energy storage. One end of the energy storage spring is connected and mounted with the energy storage lever, and the other end of the energy storage spring is mounted in a base support. An energy storage mounting shaft which can be considered as a rotating fulcrum is also arranged in the middle of the energy storage lever. The driving end is stressed, such that the energy storage lever rotates around the energy storage mounting shaft. The mounting structure for the energy storage assembly of the circuit breaker, which is provided by the present invention, is simple in mounting process, stable in connection structure and high in assembly accuracy.
US10269517B2	Contact device, electromagnetic relay using the same, and method for manufacturing contact device A contact device of present invention includes a first contact portion, a first fixed terminal electrically connected to the first contact portion, a second contact portion, and a second fixed terminal electrically connected to the second contact portion. The contact device further includes a housing being box-like in shape and disposed so as to surround the first and second contact portions, the housing including a bottom plate having a first opening hole through which the first fixed terminal passes and a second opening hole through which the second fixed terminal passes. The contact device further includes a first insulating member being electrically insulating, annular, and directly or indirectly joined to the bottom plate around the first opening hole, and a second insulating member being electrically insulating, annular, and directly or indirectly joined to the bottom plate around the second opening hole.
US10269512B2	Method and device for cutting off an electric current with dynamic magnetic blow-out The invention relates to a method and a device for cutting off electric current. The device comprises at least one fixed contact and at least one moving contact that can move between a closed position and an open position, and at least one permanent magnet mounted together with the moving contact, such that the permanent magnet and the moving contact are able to move at the same time. The magnetic field of the magnet interferes with the area where the arc occurs and moves with the moving contact along its path, so with a small number of magnets, arc quenching capacity increases. The method of the invention comprises moving a permanent magnet through the area where an electrical arc occurs between a moving contact and a fixed contact, such that the generated magnetic field runs through at least part of the area where the arc occurs.
US10269510B2	Combined discharging and grounding device for a high voltage power converter Combined high voltage discharging and grounding device with a discharging unit with a first electric contact and a first counter-contact as well as a grounding unit with a second electric contact and a second counter contact. The first electric contact and the second electric contact are provided on a movable member which is movable by way of a drive along a path of movement from an open position to a close position. An electric contact between the first electric contact and the first counter-contact is established in an intermediate position between the open position and the closed position of the movable member when closing the discharging and grounding device in an operating state of the discharging and grounding device while the second electric contact is electrically still disconnected from the second counter contact.
US10269498B2	Multi-layer ceramic capacitor and method of producing the same A multi-layer ceramic capacitor includes a body. The body includes a capacitance forming unit, a cover, and a side margin. The capacitance forming unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers. The cover covers the capacitance forming unit from the first direction. The side margin covers the capacitance forming unit from a second direction orthogonal to the first direction. The capacitance forming unit includes a surface layer portion adjacent to the cover. Ends of the internal electrodes in the second direction in the surface layer portion are curved toward the cover.
US10269497B2	Electronic component An electronic component includes a laminated body including dielectric layers and internal electrode layers, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The internal electrode layers include first and second internal electrode layers, the second internal electrode layers each include first and second extended electrode portions. A relationship of L1/L2>1.0 is satisfied when a length of a first contact portion with one second external electrode in contact with the first extended electrode portion in the length direction is L1, and a length of a second contact portion with the other second external electrode in contact with the second extended electrode portion in the length direction is L2.
US10269493B2	Modular dense energy ultra cell and process for fabrication A hybrid ultra-capacitor and Dense Energy Ultra Cell (DEUC) energy storage device and methods of production are described. An example method uses spray deposition processes to deposit energy storage layers that are interleaved in between electrodes to enable rapid charge and dense energy storage in a scalable Element with efficient fabrication methods to support a wide variety of applications.
US10269491B2	Ceramic electronic component A ceramic electronic component includes an electronic component body, an inner electrode, and an outer electrode. The outer electrode includes a fired electrode layer and first and second plated layers. The fired electrode layer is disposed on the electronic component body. The first plated layer is disposed on the fired electrode layer. The thickness of the first plated layer is about 3 μm to about 8 μm, for example. The first plated layer contains nickel. The second plated layer is disposed on the first plated layer. The thickness of the second plated layer is about 0.025 μm to about 1 μm, for example. The second plated layer contains lead.
US10269488B2	Preparation of permanent magnet material The present invention provides a method for preparing a permanent magnet material, the method comprising coating step and infiltrating step, wherein, coating a rare earth element-containing substance on the surface of a permanent magnet, the magnet having a thickness of 10 mm or less at least in one direction, then placing the magnet into a container, vacuuming to an atmospheric pressure of below 10 Pa, closing the passageway, and then heat treating the closed container. Using the method of the present invention enables the rare earth element to infiltrate homogeneously with a high permeability. In addition, the present invention may have a lower production cost, significantly increase coercive force of the permanent magnet material, but decrease the remanence very little.
US10269481B2	Stacked coil for wireless charging structure on InFO package A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.
US10269477B2	Soft magnetic resin composition and soft magnetic film A soft magnetic resin composition contains flat soft magnetic particles, a resin component, and a rheology control agent.
US10269473B1	Electrical insider fitting for internal connection to an electrical box An electrical fitting adapted for insertion from the interior of an electrical box in order to provide a secure means for attaching an electrical cable to the box. The electrical insider fitting includes a connector body having a leading end, a trailing end, and a base flange on the trailing end. A leading face is included on the base flange and a seat on the connector body adjacent the leading face of the base flange. An external snap ring resides in the seat and includes one or more outward extending locking tangs. The leading end of the connector body includes an internal bore with an internal snap ring secured therein. The internal snap ring includes one or more cable retaining tangs for engaging and securing an electrical cable to the leading end of the connector body.
US10269463B2	Nuclear thermionic avalanche cells with thermoelectric (NTAC-TE) generator in tandem mode Systems, methods, and devices of the various embodiments described herein enable an energy conversion system comprising a radioactive element for generating conduction-band electrons in an avalanche cell and generating heat, wherein the conduction-band electrons are provided to an anode to generate avalanche cell power, and the heat is provided to a thermoelectric generator to generate thermoelectric power. In an embodiment, the avalanche cell is irradiated with gamma rays, which excite electrons within the avalanche cell, generating a current. In an additional embodiment, the thermoelectric power and avalanche cell power can comprise a dual power system.
US10269461B2	Device and method for cleaning surfaces A device for submersibly cleaning surfaces inside a nuclear reactor includes a pump and a nozzle connected to said pump. The nozzle is arranged to face surfaces to be cleaned. The device includes cleaning means capable of removing debris on surfaces to be cleaned. The device includes adjustable flotation means, capable of adjusting the flotation capability of the device depending on a type of cleaning application.
US10269460B2	Control rod position indicator A rod position indication system includes a drive rod operably coupled to a control rod that is configured to be both withdrawn from and inserted into a reactor core. A number of sensing devices are arranged along a path of the drive rod, and an end of the drive rod passes by or through one or more of the sensing devices in response to movement of the control rod relative to the reactor core. The sensing devices are arranged into a plurality of groups, and each group includes two or more of the sensing devices electrically coupled together. The rod position indication system further includes a control rod monitoring device electrically coupled to each group of sensing devices by a routing wire.
US10269450B2	Probabilistic event classification systems and methods Probabilistic event classifications systems and method are provided herein. In one embodiment, a method includes receiving an event narrative, the event narrative comprising textual content describing a safety event, parsing the textual content to identify key terms, searching a safety event database for classifications associated with the key terms, selecting a set of classifications based on the key terms using statistical analysis, the set of classifications comprising potential event types for the event narrative, and displaying the set of classifications for the event narrative via a graphical user interface.
US10269447B2	Algorithm, data pipeline, and method to detect inaccuracies in comorbidity documentation Systems and methods for detecting inaccuracies in comorbidity documentation are provided. An example method can include retrieving patient data from a hospital records database, generating a first data structure representing a list of patient identifiers, retrieving patient symptom data for each patient identifier listed in the first data structure, generating, a second data structure by assigning the retrieved patient symptom data to the eligible patients represented in the first data structure, retrieving, a plurality of lookup tables, generating a third data structure by applying the lookup tables to the second data structure to assign a CC or a MCC value to at least one unique patient identifier of the second data structure, and storing the third data structure to the memory. In some implementations, the method can include updating the hospital records database with the CC or the MCC value assigned to the at least one unique patient.
US10269446B2	System and method for real time display of diagnostic laboratory data A system and method for real time updating and displaying medical diagnostics data, wherein the information stored in databases comprising large amounts of sensitive data that is being updated frequently are provided herein. By using a batch table for data filtering and a snapshot table for data retrieval, the system's performance remains substantially predictable and stable regardless of the base tables' size.
US10269445B1	Memory device and operating method thereof A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.
US10269437B2	Non-volatile memory device and operation method of the same A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.
US10269435B1	Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.
US10269433B2	Memory device A memory device according to an embodiment includes word lines stacked in a third direction perpendicular to a first direction and a second direction; main bit lines including a first main bit line and extending in the second direction; transistors including first and second transistors of which the channel width is greater than the width of the main bit lines; sub-bit lines extending in the third direction and including a first sub-bit line electrically connected to the first main bit line, with the first transistor interposed therebetween, and a second sub-bit line electrically connected to the first main bit line, with the second transistor interposed therebetween, and being adjacent to the first sub-bit line, a line segment virtually connecting the first sub-bit line and the second sub-bit line intersecting the second direction; and a resistance-change layer provided between the word lines and the sub-bit lines.
US10269432B2	Method and apparatus for configuring array columns and rows for accessing flash memory cells In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
US10269430B2	Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
US10269426B2	Integrated circuits with complementary non-volatile resistive memory elements Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.
US10269425B2	Circuit methodology for highly linear and symmetric resistive processing unit A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.
US10269424B2	Semiconductor memory apparatus A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a memory element. The semiconductor memory apparatus may include a first switching driving circuit coupled to the memory element. The semiconductor memory apparatus may include a second switching driving circuit coupled to the memory element.
US10269422B2	Storage system with data reliability mechanism and method of operation thereof A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.
US10269415B2	Dual port SRAM cell with dummy transistors A semiconductor device includes a semiconductor substrate having an upper surface region and a lower surface region. The lower surface region is recessed relative to the upper surface region so a sidewall region of the semiconductor substrate extends from the lower surface region to the upper surface region. A gate electrode overlies the upper surface region of the semiconductor substrate and is spaced laterally apart from the sidewall region. An epitaxial source/drain region is disposed in the semiconductor substrate between the gate electrode and the sidewall region. A dummy gate electrode is spaced apart from the gate electrode by the epitaxial source/drain region and is disposed over the sidewall region. The dummy gate electrode has a non-planar lower surface having a first peripheral portion extending over the upper surface region, an intermediate portion extending downward along the sidewall region, and a second peripheral portion extending over the lower surface region.
US10269413B1	Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
US10269406B2	Adaptive refreshing and read voltage control scheme for a memory device such as an FeDRAM A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g., FeFETs). The memory device further includes a plurality of refresh trigger circuits, each refresh trigger circuit being associated with a respective one of the rows. Each refresh trigger circuit is structured to produce an output signal indicative of an estimated degradation of a memory window of one or more of the storage elements of the associated one of the rows. The memory device also further includes control circuitry coupled to each of the refresh trigger circuits, wherein the control circuitry is structured and configured to determine whether to initiate a refresh of the storage elements of a particular one of the rows based on the output signal produced by the refresh trigger circuit associated with the particular one of the rows.
US10269403B2	Semiconductor storage device According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.
US10269400B2	Tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits Embodiments disclosed herein generally relate to a multilayer magnetic device, and specifically to a spin-torque transfer magnetoresistive random access memory (STT-MRAM) device which provides for a reduction in the amount of current required for switching individual bits. As such, a polarizing reference layer consisting of a synthetic antiferromagnet (SAF) structure with an in-plane magnetized ferromagnet film indirectly exchange coupled to a magnetic film with perpendicular magnetic anisotropy (PMA) is disclosed. By tuning the exchange coupling strength and the PMA, the layers of the SAF may both be canted such that either may be used as a tilted polarizer for either an in-plane free layer or a free layer with PMA.
US10269394B2	Memory package, memory module including the same, and operation method of memory package Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.
US10269387B2	Audio authoring and compositing Some embodiments provide an audio authoring method that provide a set authoring tools for specifying rules for combining sections of a first song to generate a second song. The set of authoring tools allow an array of cells to be arranged in first and second directions, and allow each body section to be associated with one set of cells that are arranged in the first direction and another set of cells that are arranged in the second direction. At each cell that belongs to one set of cells arranged in the first direction for a first body section and another set of cells arranged in the second direction for a second body section, the set of tools also allow the user to specify whether the second body section is allowed to follow the first body section. Some embodiments provide a method for compositing audio. The method receives (1) several song sections, and (2) for each particular song section, a priority value and a set of succession rules that identify a set of song sections that cannot follow the particular song section. Based on the priority values, the method adds the song sections to the first song until a desired first-song duration is reached without exceeding the duration or until all song sections have been examined for adding to the first song. The method then analyzes a sequence of song sections in the first song to remove any song section that violates a succession rule.
US10269385B1	Data storage device switching disk surfaces to perform seek using spiral track A data storage device is disclosed comprising a first head actuated over a first disk surface comprising a first spiral track written from an outer diameter (OD) of the first disk surface to an inner diameter (ID) of the first disk surface, and a second head actuated over a second disk surface comprising a second spiral track written from an ID of the second disk surface to an OD of the second disk surface. A seek operation of the first head over the first disk surface is performed in order to access the first disk surface by reading the second spiral track from the second disk surface, seeking the second head over the second disk surface based on reading the second spiral track, and after seeking the second head over the second disk surface, accessing the first disk surface using the first head.
US10269382B1	Si-based overcoat for heat assisted magnetic recording media A stack includes a heatsink layer, a magnetic recording layer disposed over the heatsink layer, and a Si-based overcoat layer disposed over the magnetic recording layer. The Si-based overcoat layer is substantially devoid of carbon.
US10269375B2	Methods and systems for classifying audio segments of an audio signal The disclosed embodiments illustrate a method for classifying one or more audio segments of an audio signal. The method includes determining one or more first features of a first audio segment of the one or more audio segments. The method further includes determining one or more second features based on the one or more first features. The method includes determining one or more third features of the first audio segment, wherein each of the one or more third features is determined based on a second feature of the one or more second features of the first audio segment and at least one second feature associated with a second audio segment. Additionally, the method includes classifying the first audio segment either in an interrogative category or a non-interrogative category based on one or more of the one or more second features and the one or more third features.
US10269367B2	Encoding apparatus, decoding apparatus, and methods A coding apparatus, including a processor that performs operations, including encoding a first band of an input audio signal to be a first spectrum and dividing the first spectrum into a plurality of subbands at equal intervals, each interval including a predetermined number of samples. The operations also include searching a largest amplitude value of the divided first spectrum in each of the subbands, and normalizing the divided first spectrum with the largest amplitude values searched in each of the subbands to obtain a flattened first spectrum. The operations further include searching a best band which has a largest correlation value between each divided band of a second band spectrum and the flattened first spectrum, the second spectrum being higher than a predetermined frequency, and encoding the second spectrum using lag information identifying the best bands for transmitting the lag information to a decoder side.
US10269363B2	Coding method, decoding method, apparatus, program, and recording medium A normalization value calculator 12 calculates a normalization value that is representative of a predetermined number of input samples. A normalization value quantizer 13 quantizes the normalization value to obtain a quantized normalization value and a normalization-value quantization index corresponding to the quantized normalization value. An quantization-candidate calculator 14 subtracts a value corresponding to the quantized normalization value from a value corresponding to the magnitude of each of the samples to obtain a difference value and, when the difference value is positive and the value of each of the samples is positive, sets the difference value as an quantization candidate corresponding to the sample. When the difference value is positive and the value of each of the samples is negative, the quantization-candidate calculator 14 reverses the sign of the difference value and setting the sign-reversed value as an quantization candidate corresponding to the sample. When the difference value is not positive, the quantization-candidate calculator 14 sets 0 as an quantization candidate corresponding to the sample. A vector quantizer 15 jointly vector-quantizes a plurality of quantization candidates corresponding to a plurality of samples to obtain a vector quantization index.
US10269360B2	Efficient format conversion in audio coding The present disclosure relates to a method of downmixing a plurality of input audio channels. The method include obtaining, for each of the input audio channels, a plurality of frequency coefficients in a plurality of corresponding frequency bins, and applying, for at least one frequency bin, a downmix matrix to a first array formed by the frequency coefficients of the plurality of input audio channels for the respective frequency bin to obtain a second array formed by the frequency coefficients of a plurality of intermediate audio channels for the respective frequency bin. The method further involves determining a third array including only the non-zero entries of the downmix matrix, and determining a fourth array including, for each entry of the third array, an entry indicative of a position of the respective entry of the third array within the downmix matrix. Applying the downmix matrix to the first array involves multiplying, for the at least one frequency bin, the entries of the third array with corresponding entries of the first array for the respective frequency bin, the corresponding entries of said first array being determined on the basis of the fourth array. The present disclosure further relates to a corresponding apparatus for downmixing a plurality of input audio channels and to a corresponding program storage device configured for downmixing a plurality of input audio channels.
US10269359B2	Audio decoder and method for providing a decoded audio information using an error concealment based on a time domain excitation signal An audio decoder and method for providing a decoded audio information on the basis of an encoded audio information are disclosed. In one example, the audio decoder includes an error concealment configured to provide an error concealment audio information for concealing a loss of an audio frame following an audio frame encoded in a frequency domain representation using a time domain excitation signal.
US10269357B2	Speech/audio bitstream decoding method and apparatus The present invention disclose a speech/audio bitstream decoding method including: acquiring a speech/audio decoding parameter of a current speech/audio frame, where the foregoing current speech/audio frame is a redundant decoded frame or a speech/audio frame previous to the foregoing current speech/audio frame is a redundant decoded frame; performing post processing on the acquired speech/audio decoding parameter according to speech/audio parameters of X speech/audio frames, where the foregoing X speech/audio frames include M speech/audio frames previous to the foregoing current speech/audio frame and/or N speech/audio frames next to the foregoing current speech/audio frame; and recovering a speech/audio signal by using the post-processed speech/audio decoding parameter of the foregoing current speech/audio frame. The technical solutions of the present invention help improve quality of an output speech/audio signal.
US10269356B2	Systems and methods for estimating age of a speaker based on speech There is provided a system comprising a microphone, configured to receive an input speech from an individual, an analog-to-digital (A/D) converter to convert the input speech to digital form and generate a digitized speech, a memory storing an executable code and an age estimation database, a hardware processor executing the executable code to receive the digitized speech, identify a plurality of boundaries in the digitized speech delineating a plurality of phonemes in the digitized speech, extract a plurality of formant-based feature vectors from each phoneme in the digitized speech based on at least one of a formant position, a formant bandwidth, and a formant dispersion, compare the plurality of formant-based feature vectors with age determinant formant-based feature vectors of the age estimation database, determine the age of the individual when the comparison finds a match in the age estimation database, and communicate an age-appropriate response to the individual.
US10269354B2	Voice recognition system Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for voice recognition. In one aspect, a method includes the actions of receiving a voice input; determining a transcription for the voice input, wherein determining the transcription for the voice input includes, for a plurality of segments of the voice input: obtaining a first candidate transcription for a first segment of the voice input; determining one or more contexts associated with the first candidate transcription; adjusting a respective weight for each of the one or more contexts; and determining a second candidate transcription for a second segment of the voice input based in part on the adjusted weights; and providing the transcription of the plurality of segments of the voice input for output.
US10269351B2	Systems, methods, and apparatuses for resuming dialog sessions via automated assistant Methods, apparatus, systems, and computer-readable media are provided for storing incomplete dialog sessions between a user and an automated assistant in order that the dialog sessions can be completed in furtherance of certain actions. While interacting with an automated assistant, a user can become distracted and not complete the interaction to the point of the automated assistant performing some action. In response, the automated assistant can store the interaction as a dialog session. Subsequently, the user may express interest, directly or indirectly, in completing the dialog session, and the automated assistant can provide the user with a selectable element that, when selected, causes the dialog session to be reopened. The user can then continue the dialog session with the automated assistant in order that the originally intended action can be performed by the automated assistant.
US10269349B2	Voice interactive device and voice interaction method A voice interactive device that interacts with a user by voice, the device comprises a voice input unit that acquires and recognizes voice uttered by a user; a degree-of-intimacy calculating unit that calculates a degree of intimacy with the user; a response generating unit that generates a response to the recognized voice, based on the degree of intimacy; and a voice output unit that outputs the response by voice, wherein the degree-of-intimacy calculating unit calculates a degree of intimacy with the user based on a sum of a first intimacy value calculated based on a content of an utterance made by the user and a second intimacy value calculated, based on the number of previous interactions with the user.
US10269348B2	Communication system and method between an on-vehicle voice recognition system and an off-vehicle voice recognition system A vehicle based system and method for receiving voice inputs and determining whether to perform a voice recognition analysis using in-vehicle resources or resources external to the vehicle.
US10269347B2	Method for detecting voice and electronic device using the same An electronic device is provided, which includes a housing; a microphone located on or within a predetermined distance of a first portion of the housing; a speaker located on or within a predetermined distance of a second portion of the housing; a communication circuit; a processor electrically connected to the microphone, the speaker, and the communication circuit; and a memory electrically connected to the processor configured to store a message to be provided as a voice through the speaker, wherein the memory stores instructions, wherein the processor is configured to execute the instructions to perform operations comprising: determining time information corresponding to a first part of the message if providing of the message is necessary, outputting the message through the speaker, receiving an input sound through the microphone while at least a part of the message is output, and processing the input sound using the time information to detect at least one word or sentence from the input sound, and the processing the input sound includes processing the input sound by ignoring at least a part of the input sound using the time information.
US10269346B2	Multiple speech locale-specific hotword classifiers for selection of a speech locale Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for recognizing speech in an utterance. The methods, systems, and apparatus include actions of receiving an utterance and obtaining acoustic features from the utterance. Further actions include providing the acoustic features from the utterance to multiple speech locale-specific hotword classifiers. Each speech locale-specific hotword classifier (i) may be associated with a respective speech locale, and (ii) may be configured to classify audio features as corresponding to, or as not corresponding to, a respective predefined term. Additional actions may include selecting a speech locale for use in transcribing the utterance based on one or more results from the multiple speech locale-specific hotword classifiers in response to providing the acoustic features from the utterance to the multiple speech locale-specific hotword classifiers. Further actions may include selecting parameters for automated speech recognition based on the selected speech locale.
US10269345B2	Intelligent task discovery This relates to systems and processes for operating an automated assistant to process messages. In one example process, an electronic device receives a communication including a text string and determines whether a portion of the text string is associated with a data type of a plurality of data types. The data type is associated with at least one task. In accordance with a determination that the portion of the text string is associated with the data type, the electronic device receives a user input indicative of a task of the at least one task, and in response, causes the task to be performed based on the portion of the text string. In accordance with a determination that the portion of the text string is not associated with the data type, the electronic device foregoes causing the task to be performed based on the portion of the text string.
US10269341B2	Speech endpointing Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for speech endpointing are described. In one aspect, a method includes the action of accessing voice query log data that includes voice queries spoken by a particular user. The actions further include based on the voice query log data that includes voice queries spoken by a particular user, determining a pause threshold from the voice query log data that includes voice queries spoken by the particular user. The actions further include receiving, from the particular user, an utterance. The actions further include determining that the particular user has stopped speaking for at least a period of time equal to the pause threshold. The actions further include based on determining that the particular user has stopped speaking for at least a period of time equal to the pause threshold, processing the utterance as a voice query.
US10269340B2	Ultrasound beamformer with individual array element multiplexers An ultrasound beamformer may include an array of ultrasound transducer elements. Multiple signal transmitters may each generate an ultrasound signal that is different from the ultrasound signal generated by each of the others. The number of ultrasound transmitters may be no more than half the number of ultrasound transducer elements. Each multiplexer may have multiple signal inputs, each connected to a different one of the ultrasound signals; an output that drives the ultrasound transducer element; and a control input that controls which of the ultrasound signals at the signal inputs to the multiplexer is delivered to the output of the multiplexer based on a control signal. The controller may generate the control signals with a collective configuration that causes the array of ultrasound transducer elements to steer an/or focus a beam of ultrasound energy in one or more different ways at one or more different times.
US10269338B2	Wall and floor structure for reducing inter-floor noise A hard panel of wall and floor structures for reducing floor impact sound according to example embodiments includes patterned layer having different density and elastic modulus form a base layer. A transmission path of an acoustic wave may be changed in a lateral direction by passing the patterned layer and the sound energy is dissipated by the refection, refraction, and cancellation of the acoustic wave. Thus, a noise is reduced.The hard panel of the wall and floor structures according to example embodiments is effectively reduces the light and heavy impact sounds. In addition, the hard panel is formed by at least one patterned layer to refract and reflect the acoustic wave such that the floor noise may be effectively dissipated. The hard panel is further includes the sound absorbing material to absorb the noise passing through the hard panel such that the floor noise can be effectively reduced.
US10269336B2	Arrangement and field device of process measurements technology An arrangement comprising an ultrasonic transducer and a damping element with a longitudinal axis, which damping element connects the ultrasonic transducer with a housing- or measuring tube wall. The transducer has an end piece with a medium-contacting surface, from which ultrasonic signals are transferred into a gaseous or liquid medium. The damping element has at least two annular grooves and an annular mass segment arranged therebetween, characterized in that the damping element has a first eigenfrequency, in which the annular mass segment executes an axial movement parallel to the longitudinal direction of the damping element. This first eigenfrequency is the highest eigenfrequency, in the case that a plurality of eigenfrequencies are present, in the case of which the annular mass segment executes an axial movement parallel to the longitudinal direction of the damping element, and the damping element has a second eigenfrequency, in which the annular mass segment executes a rotary movement. This second eigenfrequency is the lowest eigenfrequency, in the case that a plurality of eigenfrequencies are present, in the case of which the annular mass segment executes a rotary movement, will and wherein the ratio of the first eigenfrequency to the second eigenfrequency is less than 0.75; and a field device of process measurements technology.
US10269334B2	One touch drum tuning system A cam operated drum tuning system which is rotatable clockwise and counterclockwise to tunes a musical drum. A cam ring mechanism employs multiple helical tracks. A removable radius plate and tool facilitates rotation. The timing system may be attached directly to drum lugs, to a retrofit ring attached to the lugs, or to a full floating I or II framework which use edge or full floater rings, and/or adjustable pull rods to connect the top and/or bottom tuning systems so that nothing need contact the drum shell. Eccentric micro tuners adjust the rim rollers which ride on the inner hoop, which has a lip on the underside to add overlap. Elevators are fused to raise and/or lower the cam ring to align it perpendicular to the bearing edge of the drum shell.
US10269332B1	Gear tuner device for stringed instruments A tuner for a stringed instrument, comprising: a housing mounted to the stringed instrument; a knob coupled to one end of the housing; a post coupled to the other end of the housing, the knob and the post positioned on a rotation axis, the post for receiving a string and the knob for causing rotation of the post; a gear assembly mounted in the housing between the knob and the post, the gear assembly having a first gear for rotating about the rotation axis and a second gear mounted on a gear body, the second gear having a center axis offset from the rotation axis, the first gear being meshed with the second gear, the gear body including a plurality of pins, being opposed to the second gear, for positioning in a respective plurality of cavities in the housing; wherein the second gear being coupled to the knob and the first gear being coupled to the post.
US10269327B2	Display control A method for controlling a display includes segmenting the display; assigning an importance level to at least one of the segments; and selectively setting the luminance of said segment in dependence on its importance level.
US10269322B2	Power conservation techniques for foldable displays Power conservation techniques for foldable displays are described. In one embodiment, for example, an apparatus may comprise at least one memory and logic, at least a portion of which is implemented in circuitry coupled to the memory, the logic to identify a use state of a display segment of a flexible display, determine whether to alter a power state of the display segment based on the use state of the display segment, and in response to a determination to alter the power state of the display segment, send a power control command to cause the display segment to initiate a power state transition. Other embodiments are described and claimed.
US10269320B1	GOA circuit and embedded touch display panel In a GOA circuit and an embedded touch display panel of the present disclosure, by providing a suppression module in each of multiple levels of GOA units, when the embedded touch display panel enters a stage in which signal interruption occurs and touch scanning is performed, a second node control signal on a second node is pulled down to a constant-voltage low level. This relieves the insufficiency in retaining capability of the GOA circuit in the case of TP interruption and further decreases the risk of stage-shift failure so that this GOA circuit becomes more stable.
US10269319B2	Display device and driving method thereof A display device and a driving method thereof are provided. The driving method includes supplying a first voltage Vp1 to a sub-pixel of the display device through data lines in a first stage of a control period for displaying an image. A time for displaying the image includes a plurality of control periods, and the control period includes the first stage and at least a second stage following the first stage. The driving method also includes supplying a second voltage Vp2 to the sub-pixel through the data lines in the second stage. A gate scanning frequency of the first stage is F1 and a gate scanning frequency of the second stage is F2. When the first stage ends, the sub-pixel has a pixel voltage Vp3, F1\|Vp3\|.
US10269314B2	Display device To reduce the area of a portion where a plurality of transistors are provided in a region around a display region and to reduce the area of the region around the display region, a display device includes a first transistor and a second transistor each as a transistor, and the transistor includes a connection wiring that electrically connects a semiconductor film and a source-drain electrode to each other via an opening portion provided in an insulating film. The first transistor and the second transistor are adjacent to each other, and there is a clearance between an end portion, on the side of the second transistor, of the connection wiring in the first transistor and an end portion, on the side of the second transistor, of the opening portion in the first transistor.
US10269313B2	Display device and display device drive method In a display device, pixels each including first to fourth subpixels that respectively display first to third primary colors and fourth color are arranged on an image display panel. A lighting unit emits light to the panel from the rear thereof. A control unit calculates a required luminance value for each block of the display surface of the panel based on an input image signal, determines a light source lighting amount of the lighting unit based on luminance distribution information on the lighting unit so as to satisfy the required luminance value, generates luminance information on each pixel based on the luminance distribution information and light source lighting amount, generates an output image signal that drives the subpixels based on the luminance information and input image signal, controls the lighting unit by the light source lighting amount, and controls the panel by the output image signal.
US10269312B2	Display panel driving apparatus, method of driving display panel using the same, and display apparatus having the same A display panel driving apparatus includes a data driving part and a gate driving part. The data driving part is configured to convert image data into a data signal and output the data signal to a data line of a display panel. The gate driving part is configured to output, to a gate line of the display panel, a gate signal having different gate on voltages during a first sub-frame period of a frame period and a second sub-frame period subsequent to the first sub-frame period. Thus, display quality of a display apparatus may be improved.
US10269309B2	Persistent display device with power harvesting A display device which includes an electronic paper display additionally comprises power harvesting hardware and display update hardware which is configured to control the updating of the electronic paper display based on a sensed power harvesting level which may, in various embodiments, be a current incoming power level as generated by the power harvesting hardware or a stored power level in a power storage device within the display device.
US10269305B2	Mirror display The present invention provides a mirror display that has improved design aesthetics and makes it possible to sufficiently improve visibility in mirror mode in dark environments. The mirror display according to the present invention includes a half mirror plate having a half mirror layer, a display device, a case, and an auxiliary illumination unit that includes an auxiliary light source. The case supports at least the half mirror plate and the display device and includes an outer frame that covers an edge of a front surface of the half mirror plate when viewed in a plan view from a viewing side. The display device is arranged on a rear side of the half mirror plate. The auxiliary light source is arranged on the rear side of the half mirror plate, the display device, or the outer frame. The auxiliary illumination unit is controlled separately from the display device and emits light towards the viewing side when the mirror display is in mirror mode. As measured on the viewing side, a brightness of the light emitted from the auxiliary illumination unit is greater than a brightness of the display device when the display device is in a white display state.
US10269299B2	Display device and method for obtaining a data voltage to be output to rows of pixel circuits A display driving method and device, and a display device are provided. The method comprises: obtaining a data voltage to be output to each of successive k rows of pixel circuits by a source driving integrated circuit, where k is an integer and not less than 1; determining a maximum voltage of the data voltage to be output to each of the successive k rows of pixel circuits; determining a magnitude of a power supply voltage required for the source driving integrated circuit to output the data voltages to the successive k rows of pixel circuits in accordance with the maximum voltage; and supplying the required power supply voltage to the source driving integrated circuit in accordance with the determined magnitude of the required power supply voltage when the source driving integrated circuit outputs the data voltages to the successive k rows of pixel circuits. According to an embodiment of the disclosure, when a power supply voltage required for an actual operation of the source driving integrated circuit is relatively small, the power supply voltage supplied to the source driving integrated circuit is also relatively small, such that power consumption of the source driving integrated circuit can be reduced.
US10269292B2	Display driver integrated circuits, devices including display driver integrated circuits, and methods of operating display driver integrated circuits Methods of operating a display driver integrated circuit (IC) are provided. A method of operating a display driver IC may include generating a first clock signal, and calculating a frequency of the first clock signal using a second clock signal. Moreover, the method may include generating an adjustment signal using the frequency of the first clock signal and a target frequency, and adjusting the frequency of the first clock signal using the adjustment signal. Related display driver ICs and portable electronic devices are also provided.
US10269291B2	LED driver circuit with reduced external resistances An apparatus is described that includes an LED driver circuit having a series of frequency dividers to divide a clock signal's frequency to produce a frequency divided clock signal. The series of frequency dividers are coupled to a frequency multiplier circuit. The frequency multiplier circuit is to multiply the frequency divided clock signal's frequency by an amount proportional to a desired LED intensity.
US10269290B2	Shift register units and driving methods thereof, gate driving circuits and display devices with transistors having extended lifetime Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.
US10269289B2	Shift register and control method thereof A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.
US10269286B2	Gamma correction method and gamma correction device for display module Embodiments of the present disclosure provide gamma correction method and device for a display module. The gamma correction method includes: determining, for each sub-pixel of a display module to be corrected, the highest data voltage and the lowest data voltage after gamma correction of the highest gray scale and the lowest gray scale of the display module; determining at least one set of alternative gamma register values that are capable of performing gamma correction of the display module; determining at least one set of gamma register values to be corrected for respective gray scales before the gamma correction of the display module; and performing gamma correction of the display module by adjusting the gamma register value corresponding to the gray scale to be corrected which needs to perform gamma correction.
US10269285B2	Display device and method of driving the same A display device includes: a display unit; a plurality of pixels disposed in the display unit, each pixel including first and second blue sub-pixels; and a driving mode controller configured to set a driving mode to one of a first driving mode in which both of the first and second blue sub-pixels emit light, and a second driving mode in which one of the first and second blue sub-pixels emits light, wherein the first blue sub-pixel emits light of a first frequency, and the second blue sub-pixel emits light of a second frequency different from the first frequency.
US10269284B2	Timing controller and display driving circuit including the same A display driving circuit includes a timing controller including an encoder that compresses image data based on a reference having a number of image pixels of the image data as a compression unit and that outputs the compressed image data. The timing controller further includes at least one source driver including a decoder that decompresses compressed image data and transmits decompressed image data to a display panel through a plurality of channels. Compression by the encoder based on a first reference is performed independently of compression based on a second reference.
US10269283B2	Display panel and method of adjusting brightness thereof, and display device The present disclosure provides a display panel and a method of adjusting brightness thereof, and a display device. The display panel comprises a slide detection unit including at least two electrodes independent of each other, a sensor and a processor. The slide detection unit is configured to sense a sliding touch action made by a user within a preset touch region of the display panel, the sensor is configured to sense values of currents passing through the electrodes of the slide detection unit when the sliding touch action is made by the user and to send the values of currents to the processor. The currents are generated due to the sliding touch action. The processor is configured to determine a sliding direction of the sliding touch action based on the values of the currents, and to adjust screen brightness of the display panel based on the sliding direction.
US10269282B2	Shift register, gate driving circuit, display panel and driving method A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.
US10269280B2	Display device and method of manufacturing the same A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a flexible substrate having a display area and a peripheral area outside the display area, and a second surface opposite to the first surface, and a display unit located on the display area. The display device also includes an adhesive layer located on the second surface of the flexible substrate, wherein a first groove is formed in a first portion of the adhesive layer and wherein the first portion corresponds to the peripheral area. The display device further includes a lower protective film located on the adhesive layer and having a first opening passing therethrough and overlapping the first groove in the depth dimension of the display device, and a first planarization layer at least partially filling the first groove.
US10269277B2	Organic light emitting display panel, organic light emitting display device and the method for driving the same An organic light emitting display device can include data lines; scan lines; subpixels; a data driver; and a scan driver, in which each of the subpixels includes: an organic light emitting diode; a driving transistor connected to the organic light emitting diode; a first transistor controlled by a first scan signal applied to a first gate node and connected between the driving transistor and a data line; a second transistor controlled by a second scan signal applied to a second gate node and connected between the driving transistor and a reference voltage line; a third transistor controlled by a data voltage applied to a third gate node and connected between the second gate node of the second transistor and the second scan line; and a storage capacitor connected between the first node and the second node of the driving transistor.
US10269272B1	Remote controlled optical coupler with charger, GPS, and audio I/O An input device, an optical coupler having a receiver, a processor, and one or more light emitting diodes, a light conductive material such as a bundle of optical fibers, and a connector connecting the optical coupler to the light conductive material such as a bundle of fiber optic fibers is provided. The receiver receives data from the input device that relates to lighting effects having predetermined routine or graphic patterns. The processor converts the data into instructions for the light emitting diodes to form the predetermined graphic patterns, color routines and intensities. The light emitting diodes produce light for transmission through the connector to the light conductive material such as a bundle of fiber optic fibers so that the bundle of fiber optic fibers can produce the predetermined light patterns, routines, intensities or graphic patterns.
US10269269B2	Three-dimensional advertising/promotional display A fold-flat advertising/promotional display system which incorporates tabs and slits on pre-printed panels to form a unique three dimensional structure. The advertising/promotional display system incorporates nine cooperating members: a top and bottom panel, an interior panel and six side panels. This advertising/promotional display can be used for a wide variety of promotions, have many designs and be constructed of flexible and non-flexible materials. The advertising/promotional display system provides an exciting and surprising result which is not anticipated by the user. Additionally, this advertising/promotional display can incorporate LED lights and cut outs on top and side panels of object silhouettes.
US10269268B2	Folding display tower A display unit for conveying information to a desired audience includes an outer shell having one or more areas for displaying information, and an inner support assembly coupled to the outer shell and configured to support the outer shell during use of the display unit. The display unit has at least one folded position and a use position, wherein the display unit is self-deployable such that the display unity automatically transitions from a folded position to the use position. In accordance with an aspect of the invention, the display unit may automatically transition from a folded position to the use position under a force generated from the display unit itself. A method of using the display unit is also disclosed.
US10269266B2	Syringe dose and position measuring apparatus An injection system can have a Syringe Dose and Position Apparatus (SDPA) mounted to a syringe. The SDPA can have one or more circuit boards. The SDPA can include one or more sensors for determining information about an injection procedure, such as the dose measurement, injection location, and the like. The SDPA can also include a power management board, which can be a separate board than a board mounted with the sensors. The syringe can also include a light source in the needle. Light emitted from the light source can be detected by light detectors inside a training apparatus configured to receive the injection. The syringe can have a power source for powering the sensors and the light source. The SDPA and the power source can be mounted to the syringe flange.
US10269264B2	Device and methods for continuosly refreshing a tactile display A tactile display apparatus renders information to a user, and comprises multiple braille cells attached adjacent to each other along a predefined path, a set of pins housed within the braille cells, and a set of pin holders inserted on the braille cells. The braille cells are moved periodically at a predefined speed via a driving assembly. The pins are selectively actuated by actuators, where the linear motion of the braille cells allow the user to contact the pins to read the information represented by the arrangement of the pins. The pin holders are moved along a defined path to contact the pins, and each pin holder comprises a rigid body and multiple elastic rings attached along the rigid body. The number of elastic rings is equal to the number of pins to allow the pin holder to selectively hold or release a pin.
US10269262B2	System and method for teaching pre-keyboarding and keyboarding The present invention is directed to systems and related methods of teaching pre-keyboarding and keyboarding on a QWERTY-style keyboard wherein a color-coded row-based metaphorical and visual cuing system is used in a curriculum to make foundational keyboarding skills easy-to-teach and easy-to-learn, including: unilateral hand/finger skills, Home Row hand/finger positions, relational position of symbol location, and the essential keystroke spectrum of Home Row positioning-based finger movements of the left and right hand. The invention provides a dynamic virtual keyboard with colored rows which hexfurcates the QWERTY layout into left- and right-handed row sections, independently toggling the visibility of each in a developmental order to teach keyboarding skills in incremental steps rather than all at once. The invention further provides a dynamic cursor that uses visual indicators that mirror the visual cuing system to reinforce instruction with the dynamic virtual keyboard and aid keyboarding accuracy.
US10269261B2	Flight simulation device Disclosed is a flight simulation apparatus. According to the flight simulation apparatus of the present disclosure, first left and right rails and second left and right rails slide along a pair of first front and rear rails and a pair of second front and rear rails so that first and second seats can freely move forward and rearward, first and second auxiliary rails are formed to position the first and second seats at various locations in the front-rear direction, and the first and second seats can be stably supported by first and second sliders.
US10269253B2	System and method of refining trajectories for aircraft Systems and methods of refining trajectories for aircraft include a trajectory prediction module for predicting a set of four-dimensional trajectories for aircraft; and a constraint selector module for determining a set of constraints based on the set of four-dimensional trajectories. The trajectory can be refined by mapping values for a goal associated with the set of four-dimensional trajectories based on the determined set of constraints and estimating additional values for the goal based on the mapped values.
US10269250B2	Method for coordinating the traffic of motor vehicles in a parking environment The present disclosure discloses a method for coordinating the traffic of motor vehicles in a parking environment. The method evaluates sensor data and determines current traffic situation data of a parking environment based on the evaluating. The method determines a target corridor for a destination of a motor vehicle based on current traffic situation data, a map data set, and target corridors determined for other motor vehicles. The method transmits the target corridor to the motor vehicle, and a recommendation to wait to another motor vehicle during a planned departure of the other motor vehicle from the parking environment. The method outputs a confirmation of a request for an automatic departure of the other motor vehicle to a mobile device when a time to reach an exit according to an optimal target corridor exceeds a threshold value.
US10269244B2	Method and apparatus for enhancing driver situational awareness Aspects of the subject disclosure may include, for example, determining, by a system comprising a processor, a driver profile according to a driver identity for a driver of a vehicle, selecting a driver-specific enforcement scenario for the vehicle according to the driver profile and traffic enforcement information that is associated with a vehicle location, and presenting an in-vehicle alert to convey the driver-specific enforcement scenario to the driver. Other embodiments are disclosed.
US10269243B1	System and method of use for safety of drivers and pedestrians in traffic circles The invention disclosed comprises a system and method for managing pedestrian and vehicle action while traversing a traffic-circle intersection so as to optimize pedestrian and driver safety.
US10269242B2	Autonomous police vehicle Techniques pertaining to an autonomous police vehicle are described. A method may involve a processor associated with an autonomous vehicle obtaining an indication of violation of one or more traffic laws by a first vehicle. The method may also involve the processor maneuvering the autonomous vehicle to pursue the first vehicle. The method may further involve the processor remotely executing one or more actions with respect to the first vehicle.
US10269240B2	Automatically identifying associations between vehicle operating data and non-vehicle operating data Automatically identifying associations between vehicle operating data and non-vehicle operating data may include identifying vehicle transportation network data representing a vehicle transportation network, identifying vehicle operating data reported for a plurality of vehicles, wherein the vehicle operating data includes vehicle operation records, identifying non-vehicle operating data reported for a plurality of users, wherein the non-vehicle operating data includes non-vehicle operation records, automatically identifying an association between the vehicle operating data and the non-vehicle operating data, and generating updated vehicle transportation network data based on the vehicle transportation network data.
US10269236B2	Systems and methods for generating a graphical representation of a fire system network and identifying network information for predicting network faults Systems and methods for generating a graphical representation of a fire system network and identifying network information for predicting network faults are provided. Some methods can include extracting at least one network parameter from a network board of at least one a plurality of nodes in a fire system network and using the extracted at least one network parameter to generate a topology map that graphically represents a physical connectivity structure of the plurality of nodes.

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