| Document | Document Title |
|---|---|
| US10264019B2 |
Logging encrypted data communications for QoE analysis
A device such as a smartphone may communicate with a server or other network entity using encrypted communications, making it difficult to examine such communications for purposes of identifying communication issues that may affect user QoE (quality of experience). In certain embodiments, an application may be modified to log communication data before encryption and after decryption. For example, the application program may be decompiled and logging instructions may be inserted before portion that result in data encryption and after portions where received data is decrypted. The modified application program may then be recompiled and executed on a device to produce an unencrypted log of data. In other embodiments, elements of the device operating system may be modified to log data before encryption and after decryption. |
| US10264018B1 |
Systems and methods for artificial model building techniques
Embodiments disclosed describe a security awareness system may adaptively learn the best design of a simulated phishing campaign to get a user to perform the requested actions, such as clicking a hyperlink or opening a file. In some implementations, the system may adapt an ongoing campaign based on user's responses to messages in the campaign, along with the system's learned awareness. The learning process implemented by the security awareness system can be trained by observing the behavior of other users in the same company, other users in the same industry, other users that share similar attributes, all other users of the system, or users that have user attributes that match criteria set by the system, or that match attributes of a subset of other users in the system. |
| US10264016B2 |
Methods, systems and application programmable interface for verifying the security level of universal resource identifiers embedded within a mobile application
The present disclosure discloses a method of allowing Web View to verify the security level of a web content and inform the user with regards to the security and blocks web contents that are determined harmful or inappropriate. In one embodiment of the present disclosure, the Web View checks a trusted data source to see if the visited web content has been labeled or flagged as safe or unsafe by initiating a connection to a trusted third-party database using a to determine whether or not the URL is associated with a domain that has been classified or labeled as safe or unsafe. The Web View then informs the user about the security level of the web content through a visual indicator or it can redirect the user to a warning page explaining why access to the site is prohibited, or it can block access without warning. |
| US10264015B2 |
Real-time asynchronous event aggregation systems
A real-time asynchronous event aggregation system, method, and network device are configured to capture real-time asynchronous events, and to pass them as input to one or more aggregation engines to determine a reputation for a target. The aggregation engine(s) may then send out notifications where a reputation category changes for a target, indicating that an action may be taken to inhibit spam messages from the target, highlight a display of content from the target, or the like. As such, the event-driven aggregation engines may be designed to capture real-time asynchronous events, such as reputation reports for a wide variety of activities, including, but not limited to spam and/or not-spam messages, determining a reputation on a posting of comments to a movie, a blog posting, a play list posting, or the like. In one embodiment, a reputation of the sender of the reputation event may also be determined. |
| US10264013B2 |
Preventing a memory attack to a wireless access point
Systems, methods, and machine-readable and executable instructions are provided for preventing a memory attack to a wireless access point (AP). Preventing a memory attack to a wireless access point can include receiving, with a wireless AP, a generic advertisement service (GAS) initial request from a querying station and transmitting, with the wireless AP, a GAS initial response to the querying station without querying an advertisement server based on the GAS initial request. |
| US10264011B2 |
Persistent cross-site scripting vulnerability detection
Various techniques for detecting a persistent cross-site scripting vulnerability are described herein. In one example, a method includes detecting, via the processor, a read operation executed on a resource using an instrumentation mechanism and returning, via the processor, a malicious script in response to the read operation. The method also includes detecting, via the processor, a write operation executed on the resource using the instrumentation mechanism and detecting, via the processor, a script operation executed by the malicious script that results in resource data being sent to an external computing device from a client device. Furthermore, the method includes receiving, via the processor, metadata indicating the execution of the read operation, the write operation, and the script operation. |
| US10264008B2 |
Vulnerability exposing application characteristic variation identification engine
Embodiments of the invention are directed to a system, method, or computer program product for an engine for exposing vulnerability within applications based on application characteristic identification. In this way, the engine identifies existing data sets that aid in understanding the possible privacy vulnerabilities associated with technologies such as applications, operated by an entity. The engine comprises dials and levers that allow for prioritization visualization of vulnerabilities critical to a particular portion of the entity. In this way, a user can drive the application engine allowing them to narrow the focus on any number of variations of application characteristics including, but not limited to types of vulnerabilities, status of the vulnerabilities, critical applications, regulated applications, vulnerabilities, business continuity and/or accessibility to the applications. |
| US10264004B2 |
System and method for connection fingerprint generation and stepping-stone traceback based on netflow
The method for tracking a cyber hacking is provided. The method of connection fingerprint generation and stepping-stone traceback based on NetFlow includes receiving a traceback request including IP packet attribute information of a victim and an attacker which corresponds to a target connection that is the last connection on a connection chain, generating a fingerprint for an associated connection based on the IP packet attribute information and requesting a NetFlow collector for relevant information, detecting a stepping-stone connection to the target connection which is generated at the time of generation of the fingerprint and instructing to check whether sorted candidate connections are present on the same connection chain as the target connection, and determining an order of the candidate connections based on an attacker host when the candidate connections are determined to be present on the same connection chain as the target connection. |
| US10264003B1 |
Adaptive network monitoring with tuneable elastic granularity
Embodiments are directed to monitoring network traffic using network computers. Monitoring triggers associated with one or more conditions and one or more actions may be provided. A monitoring engine may monitor information that is associated with network traffic associated with networks based on an inspection detail level. The monitoring engine may compare the monitored information to the conditions associated with the monitoring triggers. The monitoring engine may activate one or more monitoring triggers based on a result of the comparison. The monitoring engine may modify the inspection detail level based on the actions associated with the activated monitoring triggers to increase the amount of the information monitored by the monitoring engine. An analysis engine may provide analysis of the network traffic based on the monitored information. |
| US10264001B2 |
Method and system for network resource attack detection using a client identifier
Methods, systems, and techniques for network resource attack detection using a client identifier. A server receives from a device the client identifier and user credentials. The client identifier and user credentials are assessed to determine their authenticity. If one or both of the credentials and identifier are inauthentic, the device does not learn from the server which of the identifier and credentials have been found to be inauthentic. When at least one of the identifier and credentials are inauthentic, the device that sent them is assessed to determine whether it is an attacker of the network resource. If the device is determined to be an attacker, one or both of prophylactic and remedial action is taken in response. |
| US10263999B2 |
System for securely accessing network address, and device and method therein
Disclosed are a system for securely accessing a network address, and a device and a method therein. The system for securely accessing a network address comprises a terminal device and a security control server. The security control server stores security attributes of known network addresses. The terminal device comprises: a scanner, used for scanning a two-dimensional code; a decoder, used for decoding the two-dimensional code scanned by the scanner to obtain a network address corresponding to the two-dimensional code; a transmission interface, used for transmitting the network address to a security control server for check, and receiving a security attribute of the network address from the security control server; and a monitor, used for forbidding or allowing the connection of the network address according to the security attribute of the network address. |
| US10263996B1 |
Detecting fraudulent user access to online web services via user flow
Techniques to detect unauthorized access and/or use of a user's account provided by an online web service are provided. A user's activity on the online web service can be monitored to determine a model of the user flow through the online web service. The model of user flow can be unique to the user or can be a model assigned to a cluster of users having similar behaviors or mannerisms when navigating the online web service. The model can vary based on the type of device used by the user to access the online web service. Once a model is determined, subsequent activity on the online web service by the user can be monitored and compared to the model of user flow. Unauthorized access and/or use of the user's online account can be detected if the subsequent activity fails to fit the model of the user flow. |
| US10263995B1 |
Provisional computing resource policy evaluation
A policy management service receives a request to evaluate a provisional policy to determine the impact of implementation of the provisional policy. The policy management service evaluates an active policy against a request to access a computing resource to determine an authorization decision. The policy management service then evaluates the provisional policy against the request to access the computing resource to generate an evaluation of the provisional policy. The policy management service provides the evaluation and the authorization decision in response to the request to evaluate the provisional policy. |
| US10263986B1 |
Privilege elevation system and method for desktop administration
In one embodiment, a method is executed by an information handling system comprising computer hardware. The method includes monitoring a desktop environment of a user for a desktop-administration event. The method further includes, responsive to a detected occurrence of the desktop-administration event, identifying at least one script-execution process to invoke. The at least one script-execution process executes at least one privilege-agnostic desktop-administration script. The method also includes determining whether the at least one script-execution process is designated for privilege elevation. Moreover, the method includes, responsive to a determination that the at least one script-execution process is designated for privilege elevation, injecting a security token of the at least one script-execution process with elevated privileges to yield a privilege-injected script-execution process. Also, the method includes invoking the privilege-injected script-execution process in the desktop environment so that the desktop-administration script executes as the user with the elevated privileges. |
| US10263985B2 |
Work method for smart key device
A work method for a smart key device. A host machine acquires data from a trusted server via a browser and then transmits the data to a smart key device; the smart key device performs a signing operation when the data transmitted by the host machine is received and when a user confirmed by pressing a key and then returns a signing result to the host machine; and the host machine transmits data returned by the smart key device to the trusted server to verify the validity of the smart key device. This implements rapid authentication of user identity, thus allowing highly efficient, secure, and expedited online transactions. |
| US10263984B2 |
Authentication failure handling for access to services through untrusted wireless networks
Apparatus and methods to support authentication failure handling by network elements and by a wireless communication device when attempting access to services through non-cellular wireless networks by the wireless communication device are disclosed. Error messages received from evolved packet core (EPC) network elements, such as an authentication, authorization, and accounting (AAA) server, are mapped to failure messages provided to wireless communication devices by internetworking equipment, such as an evolved packet data gateway (ePDG). The wireless communication device determines a failures cause based on the failure messages and disallows retry attempts until select criteria are satisfied. |
| US10263982B2 |
Foldable device and method of controlling the same
A foldable device includes: a display; a touch panel configured to detect a touch input; a sensing interface configured to detect an angle of the foldable device; and a controller configured to activate the display unit when the angle detected by the sensing unit as the foldable device is unfolded is equal to or greater than a first angle, and activate the touch panel when the angle detected by the sensing unit is equal to or greater than a second angle. |
| US10263978B1 |
Multifactor authentication for programmatic interfaces
Systems and methods provide logic that validates a code generated by a user, and that executes a function of a programmatic interface after the user code is validated. In one implementation, a computer-implemented method performs a multifactor authentication of a user prior to executing a function of a programmatic interface. The method includes receiving, at a server, a user code through a programmatic interface. The server computes a server code in response to the user code, and compares the user code to the server code to determine that the user code corresponds to the server code. The server validates the user code and executes a function of the programmatic interface, after the user code is validated. |
| US10263973B2 |
Method for accessing a service, corresponding first device, second device and system
A first device generates a first signature by using complete transaction data received from a second device, a first algorithm and a first key, modifies at least one character from the complete transaction data and gets partial transaction data, and sends to the second device the partial transaction data. The second device requests a user to modify the partial transaction data by providing at least one character, as complementary data to the partial transaction data, gets, as request response from a user, at least one character to modify the partial transaction data, a corresponding result being proposed modified transaction data, generates a second signature by using the proposed modified transaction data, the first algorithm and the first key, and sends to the first device the second signature. Only if the second signature does match the first signature, then the first device authorizes to carry out a corresponding transaction. |
| US10263971B2 |
Preventing unauthorized access to secured information systems by injecting device data collectors
Aspects of the disclosure relate to providing information security and preventing unauthorized access to resources of an information system by injecting device data collectors into pages and/or other interfaces provided by and/or otherwise associated with an information system. A computing platform may intercept a request corresponding to a selection of an interface element included in a modified version of a first page associated with a uniform resource locator. Based on intercepting the request, the computing platform may validate a security state of a client device based on device data collected by a device data collector. In response to failing to validate the security state of the client device, the computing platform may generate and send a step-up authentication prompt to the client device. The step-up authentication prompt may prompt a user of the client device to provide authentication input to access a second page associated with the selection. |
| US10263967B2 |
Apparatuses, systems and methods for constructing unique identifiers
An apparatus for producing unique user specific identifiers including capturing user specific biometric data, kinetic data, biokinetic data, kinetic data and biometric data, biokinetic data and biometric data, and kinetic data, biokinetic data and biometric data and generating unique user specific identifiers. |
| US10263966B2 |
Perimeter enforcement of encryption rules
Rules are applied at a network perimeter to outbound network communications that contain file attachments. The rules may, in a variety of circumstances, require wrapping of an outbound file from the endpoint in a portable encrypted container. The network perimeter may be enforced locally at the endpoint, or at any network device between the endpoint and a recipient. |
| US10263965B2 |
Encrypted CCNx
One embodiment provides a system that facilitates selective encryption of bit groups of a message. During operation, the system determines, by a content requesting device or content producing device, a message that includes a plurality of bit groups, each corresponding to a type, a length, and a set of values, wherein one or more bit groups are marked for encryption, and wherein the message indicates a name that is a hierarchically structured variable-length identifier comprising contiguous name components ordered from a most general level to a most specific level. The system computes a plurality of cipher blocks for the message based on an authenticated encryption protocol. The system encrypts the one or more bit groups marked for encryption based on one or more symmetric keys, wherein the marked bit groups include one or more name components. Subsequently, the system indicates the encrypted bit groups as encrypted. |
| US10263962B2 |
User authentication over networks
Methods are provided for authenticating user authentication data, associated with a user ID, at an authentication system. The authentication system comprises an authentication server connected to a network, and a secure cryptoprocessor operatively coupled to the authentication server. A first token for the user ID is provided in data storage operatively coupled to the authentication server. The first token is produced by the secure cryptoprocessor by encoding the user authentication data associated with the user ID via an encoding process dependent on a secret key of the secure cryptoprocessor. The authentication server receives an authentication request for the user ID from a remote computer via the network. The authentication request comprises a ciphertext encrypting user authentication data under a public key of a first public-private key pair, the private key of which is secret to the secure cryptoprocessor. The authentication server supplies the ciphertext to the secure cryptoprocessor which decrypts the ciphertext using this private key to obtain plaintext user authentication data. The authentication server retrieves the first token for the user ID from the data storage. The authentication system checks for equality of the plaintext user authentication data and the user authentication data encoded in the first token via a cryptographic processing operation in which the authentication data is not exposed outside the secure cryptoprocessor. In response to such equality, the authentication server sends an authentication confirmation message to the remote computer via the network. |
| US10263961B2 |
Security chip and application processor
A security chip and an application processor may be included in a device configured to engage in encrypted communications with an external client, including public key infrastructure communications, in an environment where a certificate authority is absent. The security chip may provide the application processor with a device public key from among a pair of device keys related to public key infrastructure communications, receive a request from the application processor to generate a digital signature on a certificate form including the device public key, provide the application processor with a digital signature generated based on an encryption operation using a certificate authority private key, and receive and store a certificate including the digital signature from the application processor. |
| US10263960B2 |
Wireless communication system and wireless communication method
A wireless communication device 1 encrypts a passphrase which corresponds to a communication mode after change and which is a character string for authentication by using an encryption key PTK corresponding to a communication mode before change, and transmits the encrypted passphrase to a wireless communication device 2, and also creates an encryption key PTK corresponding to the communication mode after change from the passphrase corresponding to the communication mode after change. The wireless communication device 2 receives the encrypted passphrase transmitted from the wireless communication device 1 and decrypts the encrypted passphrase by using an encryption key PTK corresponding to the communication mode before change, and also creates an encryption key PTK corresponding to the communication mode after change from the decrypted passphrase. |
| US10263959B2 |
Method for communicating medical data
A method for communicating medical data includes forming a secure channel between a first medical device and a second medical device connected to each other through a network on the basis of first authentication information of the first medical device and second authentication information of the second medical device; encrypting medical data that is obtained by the first medical device using a secure circuit that is provided in the first medical device; and transmitting the encrypted medical data to the second medical device through the secure channel. |
| US10263955B2 |
Multi-tiered protection platform
A multi-tier platform provides security at a perimeter of a computer system, where an intermediate layer interacts between a web layer and an application layer. A data request that is associated with a data set is received at the web layer and passed to the intermediate layer. The intermediate layer determines the authoritative source for the data set and whether the data set has a static or dynamic value. If the value is static, the intermediate layer accesses the value stored at the intermediate layer. However, if the value is dynamic, the intermediate layer queries the source registered to the data set, obtains the value from the authoritative source, and returns the dynamic value via the web layer, where the registered source may be internal or external to the computer system. Consequently, the intermediate layer may function as an aggregate layer that supports both database and messaging services. |
| US10263952B2 |
Providing origin insight for web applications via session traversal utilities for network address translation (STUN) messages, and related methods, systems, and computer-readable media
Providing origin insight via Session Traversal Utilities for Network Address Translation (STUN) messages for web applications, and related methods, systems, and computer-readable media are disclosed herein. In one embodiment, a method for providing origin insight for web applications via STUN messages comprises determining an origin identifier for a web application attempting to send a STUN message to a STUN server; generating the STUN message incorporating the origin identifier for the web application; and transmitting the STUN message to the STUN server. In another embodiment, a method for providing STUN services to web applications comprises receiving a STUN message from a web client, and extracting an origin identifier for a web application. Provision of a STUN service to the web application is determined based on the origin identifier. If the STUN service should not be provided, the STUN message is rejected or disregarded; otherwise the STUN message is processed. |
| US10263951B2 |
Network address family translation method and system
The present invention, generally, is directed towards sending and receiving communication sessions across more than one network using an address family translation or network address translation (NAT) system and method. Such application is directed towards providing the ability to send and receive communications sessions between communication nodes, network edge devices, and the like, using more than one Internet protocol. This application is especially advantageous where communication sessions need to be transferred from one location to a second using the public Internet, i.e., Internet access provided by third-party Internet service providers (ISPs). The present invention, also, provides a translation system and method which may allow a communication node or a network edge device to recognize and interpret communication sessions received over a third-party Internet connection from a device hidden by a third party ISP-provided NAT implementation. |
| US10263950B2 |
Directing clients based on communication format
Methods and systems for redirecting client requests are provided. According to one embodiment, a system includes a processor and a memory coupled to the processor and configured to provide the processor with instructions. A request is received from a client capable of communicating via multiple supported communication formats. The request is capable of being serviced by multiple servers each of which are configured to communicate via a different communication format. A server is selected from the multiple servers based on a traffic management policy. The traffic management policy is based on (i) different communication formats available via the multiple servers and (ii) performance expected to be provided to the client as a result of using each of the different communication formats. The client is then redirected to the selected server. |
| US10263948B2 |
Method and apparatus for provisioning a scalable communications network
A method that incorporates teachings of the subject disclosure may include, for example, determining at a first directory server of a first regional call processing system whether a new name authority pointer associated with a telephone number is within a first geographic region of the first regional call processing system, transmitting the new name authority pointer to a first name server of the first regional call processing system for provisioning the name authority pointer to the first name server responsive to determining that the telephone number is located within the first geographic region, and transmitting the new name authority pointer to a second directory server for provisioning the new name authority pointer to a second name server of a second regional call processing system responsive to determining that the telephone number is not located within the first geographic region. Other embodiments are disclosed. |
| US10263945B1 |
Transaction lifecycle management
A transaction management platform is provided that is configured to perform end-to-end tracking of transactions including messages. Message tracking information is used to identify anomalies at certain nodes in a network. For example, if too many or too few messages are passing through a node as compared to historical values, an anomaly event may be logged as anomaly and a graphical diagram may be updated. |
| US10263941B2 |
Managing multiple messages
This disclosure relates to systems and methods for managing multiple messages. In one example, a method includes determining a message transmission frequency threshold for a member of an online social networking service using responses from the member; receiving a message that is to be transmitted to the member; storing the message, without transmitting the message to the member, in a digest of messages for the member; and transmitting the digest to the member in response to a send score for the digest exceeding a send score threshold, the send score calculated using the number of messages in the digest. |
| US10263937B2 |
Automated message recall from a sender's device
A system, apparatus, and methods are provided for supporting automated recall of a message (e.g., a chat message) from an originator's device, or at least media that accompanied the message. An original message may convey one or more media files that are temporarily stored on a system or apparatus that hosts the communication application used to create, send, and receive messages. The media files may be lost in transit because of failure of a system component, failure of a storage device, purging of the files before they are retrieved by a recipient, or for some other reason. When the recipient's device receives an error in response to an attempt to retrieve the media file(s), it automatically initiates a recall request that is returned to the originating device. If the message and media are still available on the device, an abbreviated version of the message is re-sent, with the media. |
| US10263935B2 |
Message categorization
One or more techniques and/or systems are provided for defining a message behavior profile for a sender, which may be used to categorize messages from the sender. A message behavior profile may be defined based upon, for example, message distribution behavior of the sender (e.g., volume, frequency, variance in content amongst messages sent to recipients, etc.); recipient interactions with messages from the sender (e.g., message read rates, message response rates, etc.); unsubscription options comprised within messages from the sender; and/or other factors. In this way, the message behavior profile and/or features extracted from a message may be used to categorize a message from the sender (e.g., newsletter, commercial advertisements, alert, social network etc.). Categorized messages may be organized into folders, displayed or hidden within views, and/or processed based upon their respective categorizations. |
| US10263930B2 |
System and method for blocking notification messages during screen sharing
Systems and methods are disclosed for suspending notification messages at a presenter's computer during a presentation. For example, a method comprises: receiving, by an operating system of a computer, a first instruction from a screensharing application to suspend displaying notification messages by the operating system of the computer. The method further comprises sending visual media of a display screen of the computer by the operating system to the screensharing application during a screen sharing communication session. The method further comprises disregarding the request during the screen sharing communication session in accordance with the first instruction, in response to receiving a request from a first application to display a notification message on the display screen. |
| US10263929B2 |
Cloud based chat governance system based on behavioral patterns and situational-awareness
A computer-implemented method for intelligent chat governance, is provided. The computer-implemented method includes analyzing an incoming message based on relationship between a plurality of users, content of the incoming message, and metadata of the incoming message. The computer-implemented method further includes calculating a plurality of prioritization metrics of the incoming message based on a comparison of the analyzed message to a knowledge base, wherein the knowledge base includes behavioral tendencies of users of the incoming message, patterns of interaction of the users, and situational awareness of the users. The computer-implemented method further includes the transmitting the incoming message to a client interface of, in response to a determination that at least one of the plurality of prioritization metrics are greater than a threshold level. |
| US10263922B2 |
Forming a group of users for a conversation
Forming a group of users for a conversation includes determining when users are accessing information associated with each other, maintaining a group of the users, the group of the users representing a transitive closure over a viewing relationship of the information, displaying, via a display of a user device, digital representations of the users in the group accessing the information, and initiating, based on an action of at least one of the users in the group of users, a conversation. |
| US10263920B2 |
Enhanced acknowledgement handling in communication packet transfer
Described herein are methods, systems, and software for handling packet buffering between end users and content servers, such as content delivery nodes. In one example, a method of operating a content server includes generating first and second data packets for first and second content requests. Once generated, the method provides storing the first packets in a packet buffer and transferring the first packets to a first user device. Upon transfer, the first packets are deleted from the packet buffer and replaced with the second packets. Theses second packets are then transferred to a second user device and deleted from the packet buffer. Further, once the packets are transferred to the user devices, the method further includes monitoring for an acknowledgment from the user devices to ensure the packets are received. |
| US10263903B2 |
Method and apparatus for managing communication flow in an inter-network system
According to at least one example embodiment, a method and corresponding apparatus for managing a data packet flow at an inter-network system include obtaining, by an inter-network device, an identification of the data packet flow, the identification of the data packet flow being determined based on one or more transport protocol fields extracted from control-plane data associated with the data packet flow. Using the obtained identification of the data packet flow, the inter-network device identifies data packets associated with the data packet flow by checking transport layer data of intercepted user-plane data packets for potential match with the one or more transport protocol fields extracted from the control-plane data. If a match is found, the corresponding data packet is then managed by the inter-network device based on one or more management actions associated with the data packet flow. |
| US10263902B2 |
Device and system for selective forwarding
A system and method of operating equipment and services to allow enhanced global transport of IP packets is presented. A global virtual network with guaranteed capacity is used to transport said IP packets. A number of application-specific forwarding devices are deployed to detect and forward selected traffic types to the virtual network. The application-specific selective forwarding devices can be implemented based on the IP packets analysis, or by deploying enhanced control protocols like SIP/H.323. |
| US10263901B2 |
Service packet processing method, apparatus, and system
The present invention discloses a service packet processing method, apparatus, and system. The method includes a first service atom receiving a second packet sent by a central switching device, where a first service packet is encapsulated in the second packet and the second packet further includes a first service path identifier. The first service atom performs first service processing according to information in the first service packet, to obtain a first processing result. The first service atom queries a first path switching entry according to the first processing result and the first service path identifier. The first service atom sends a third packet to the central switching device, where a source device identifier of the third packet is a device identifier of the first service atom, a second service packet is encapsulated in the third packet, and the third packet includes the second service path identifier. |
| US10263895B2 |
Data transmission method, central processing node, gateway, and base station
The present disclosure provide a data transmission method, including: receiving, by a central processing node, downlink user data from a first gateway GW; sending, by the central processing node, the downlink user data to a corresponding base station; and when it is determined that an interface between the central processing node and the first GW is congested, sending, by the central processing node, a first bearer switching request message to the first GW, where the first bearer switching request message is used to instruct the first GW to bypass the central processing node when transmitting data. In the embodiments of the present invention, when determining that an interface between a central processing node and a first GW is congested, the central processing node sends a first bearer switching request message to the first GW, so that the first GW transmits downlink user data with the central processing node bypassed. |
| US10263893B2 |
Application-level dynamic scheduling of network communication for efficient re-partitioning of skewed data
Techniques are provided for using decentralized lock synchronization to increase network throughput. In an embodiment, a first computer sends, to a second computer comprising a lock, a request to acquire the lock. In response to receiving the lock acquisition request, the second computer detects whether the lock is available. If the lock is unavailable, then the second computer replies by sending a denial to the first computer. Otherwise, the second computer sends an exclusive grant of the lock to the first computer. While the first computer has acquired the lock, the first computer sends data to the second computer. Afterwards, the first computer sends a request to release the lock to the second computer. This completes one duty cycle of the lock, and the lock is again available for acquisition. |
| US10263891B2 |
Switching device, computer system, method, and program
Provided is a switching apparatus including a processor that allows the switching apparatus to function as: an analysis unit that is configured to extract a header of a received packet and to acquire information of the header; a determination unit that is configured to determine an operation for the packet according to information of a type, request source, and destination of a request included in the header; and an execution unit including a means that is configured to execute, in accordance with the determined operation, at least one of processing for responding to the request included in the packet, processing for rewriting the packet, and processing for transmitting the packet. |
| US10263885B2 |
Wireless home network routing protocol
A hierarchical wireless network is provided with a mesh backbone network portion and a switching tree network portion. The mesh backbone network portion includes first tier nodes each having at least one wireless link to another first tier node. The first tier nodes execute a link-state protocol for routing packets. The switching tree network portion includes second tier nodes each having a single wireless link to one first tier node and at least one wireless link to one third tier node, and third tier nodes each having a single wireless link to one second tier node. The second tier and the third tier nodes execute switching rules for switching packets. |
| US10263880B1 |
Method apparatus, and computer program product for dynamic security based grid routing
A method of routing data that is part of a grid job including steps of: receiving a data packet at a routing device; determining whether the data packet is identified as part of a grid job; and routing the data packet that is identified as part of a grid job through the Internet to an external node. |
| US10263877B1 |
Generating collections of sets based on user provided annotations
Described are systems and methods for establishing and generating collections of sets that contain object identifiers based on user provided annotations for the object identifiers. A set may include one or more object identifiers and each object identifier may include one or more user provided annotations. Annotations from all object identifiers within a set are processed to form a set profile signature representative of the set. The set profile signatures are then compared between different sets to identify similar sets. Similar sets are included in a collection. Utilizing set profile signatures for a set formed based on user provided annotations provides useful relationships between sets that might otherwise not exist. |
| US10263866B2 |
DSL neighborhood diagnostics
A Device Abstraction Proxy (DAP) interface receives a request for operational data relating to Digital Subscriber Line (DSL) services provided to a plurality of DSL terminals in a DSL network by two or more providers. The DAP interface receives, in response to the request, the operational data, including operational data for a plurality of DSL lines coupled to the plurality of DSL terminals. The DAP then identifies at least two of the plurality of DSL lines as belonging to a common neighborhood of DSL lines, each of the at least two of the plurality of DSL lines respectively associated with at least two of the plurality of DSL terminals being provided the DSL services by different providers. Embodiments correlate a condition and/or a performance of one of the at least two DSL lines identified as belonging to the common neighborhood with a condition and/or performance of another one of the at least two DSL lines identified as belonging to the common neighborhood. |
| US10263865B2 |
Network availability measurement aggregation and correlation
Methods, systems, and apparatus for correlating communications measurements are disclosed. In one aspect, a communications measurement of a maintenance entity (ME) is received. The communications measurement is stored and correlated with a maintenance entity group (MEG) identifier and an ME identifier received with the communications measurement. The stored communications measurement is registered with one or more previously received communications measurements. Each previously received communications measurement is associated with an availability indicator corresponding to an availability of the ME at a time the particular communications measurement was obtained. An availability of the ME during a given time interval is determined based on availability indicators of consecutive communications measurements for the ME. Availability indicators of at least one of the one or more previously received communications measurements are changed after the ME has been determined to be unavailable during the given time interval. |
| US10263862B1 |
Utilizing machine learning with self-support actions to determine support queue positions for support calls
A device receives a communication associated with a support issue encountered by a user, and receives information identifying one or more self-support actions performed by the user in relation to the support issue. The device assigns the communication to a position in a support queue. The support queue includes information identifying positions of other communications received from other users, when the other communications are received, and self-support actions performed by the other users. The device associates the information identifying the one or more self-support actions with information identifying the position of the communication, and applies respective weights to the one or more self-support actions. The device generates a score for the communication based on applying the respective weights, and modifies the position of the communication based on the score. The device performs one or more actions based on modifying the position of the communication. |
| US10263861B2 |
Multi-path aware tracing and probing functionality at service topology layer
In one embodiment, a system and method are disclosed for sending a request and receiving a reply. The request contains a network service header including a flow label field and a target index field. The flow label field contains a set of available flow labels. The target index field includes a value indicating a target node. The reply contains information indicating which of the flow labels can be used to route a packet to each of the next hop nodes downstream from the device that sent the reply. This process can be repeated for other nodes on a path, and other paths in a service topology layer. The information determined by this process can be used to perform other necessary functionalities at the service topology layer. |
| US10263859B2 |
Delaying new session initiation in response to increased data traffic latency
A system includes at least one server that is configured to provide a multi-client network service to a plurality of existing users. When the server receives requests to join the multi-client network service from new users, the server may issue timestamps to each new user and obtain load metric based on the requests or timestamps. The server can repeatedly compare the load metric to a threshold load value. When it is determined that the load metric does not meet or is below the threshold load value, the server enables joining the multi-client network service by the plurality of new users. Otherwise, when it is determined that the load metric meets or is above the threshold load value, the server causes delivery of a wait message to the new users and keeps them in a wait mode for a predetermined period or until the load metric changes. |
| US10263857B2 |
Instrumentation and monitoring of service level agreement (SLA) and service policy enforcement
Source policy identification information of a registry service policy is captured. The source policy identification information includes a source policy identifier (ID), a source policy name, and a source policy uniform resource locator (URL). The captured source policy identification information is correlated with configured policy enforcement processing rules and processing actions using a source policy reference key. Per-transaction service policy enforcement information that documents policy enforcement activities performed by a policy enforcement point (PEP) is captured. The captured per-transaction service policy enforcement information is correlated with the captured source policy identification information using the source policy reference key. |
| US10263855B2 |
Authenticating connections and program identity in a messaging system
A messaging system enables client applications to send and receive messages. The messaging system includes independent component programs performing different functions of the messaging system, such as connection managers that maintain network connections with the client applications, a message router that sends received messages to recipient applications through network connections, and a dispatcher that authenticates other component programs. A messaging server may authenticate client applications using certificate-based authentication (e.g., private and public keys), authentication transfer from another trusted messaging server, or other methods (e.g., user name and password). To authenticate a component program, the dispatcher compares instantiation information (e.g., user identity, process identifier, creation time) of the component program provided by the operating system with instantiation information saved in a shared memory at the time of the component program's instantiation. In response to a match, the dispatcher provides the component program with secure information through an inter-process communication socket. |
| US10263854B2 |
System and method for supporting version based routing in a transactional middleware machine environment
A system and method can support service management in a transactional middleware machine environment. A transactional service provider can dispatch at least one service using a plurality of service entries with different service versions, and determine whether a service version associated with a service entry matches a requested service version associated with a service request received from a service requester. Then, transactional service provider can allow the service requester to access the service entry that matches the requested service version associated with the service request. |
| US10263851B1 |
Device differentiation for electronic workspaces
An electronic workspace may be created from multiple viewer devices. The viewer devices are coordinated so that each exhibits a different visual identification characteristic such as a distinct or unique color. Content can be assigned by way of a user interface in which individual viewer devices are represented by visual icons that exhibit the same visual identification characteristics as the respective viewer devices, so that a user may easily distinguish between the available viewer devices. |
| US10263850B2 |
Network testing device for automated topology validation
A network testing device is provided in order to validate network topology information and test various other attributes of a network. The network testing device may, in response to a command, obtain connection information from a network indicated in the command. The connection information may be compared to network topology information corresponding to the network. The network topology information may indicate which interfaces of a network device should be to be connected to which interfaces of other network devices. The network testing device may then return, in response to the command, a result of the comparison. Furthermore, the network testing device may return result of other network test performed by the network testing device on the network device. |
| US10263848B2 |
Compiler for and method for software defined networks
Method of and a compiler for controlling a network based on a logical network model. The network has physical nodes and virtual nodes. The physical nodes are interconnected by physical links in accordance with a physical network layout. The logical network model has logical nodes indicated with a logical node name which refers to at least one physical or at least one virtual node in the network. The method uses a physical forwarding point-of-attachment relation defining physical paths of the physical network in dependence on a physical forwarding policy, a first mapping relation defining how the virtual nodes and the physical nodes are mapped to one another, and a second mapping relation defining how the logical nodes are mapped to the physical nodes and the virtual nodes. The method also includes transforming paths in the physical network to paths between the physical nodes and the virtual nodes. |
| US10263842B2 |
Dynamic configuration in cloud computing environments
Virtual machines, virtualization servers, and other physical resources in a cloud computing environment may be dynamically configured based on the resource usage data for the virtual machines and resource capacity data for the physical resources in the cloud system. Based on an analysis of the virtual machine resource usage data and the resource capacity data of the virtualization servers and other physical resources in the cloud computing environment, each virtual machine may be matched to one of a plurality of virtualization servers, and the resources of the virtualization servers and other physical resources in the cloud may be reallocated and reconfigured to provide additional usage capacity to the virtual machines. |
| US10263839B2 |
Remote management system for configuring and/or controlling a computer network switch
Methods and systems for remotely managing a switching device are provided. According to one embodiment the existence of a firewall security device within a network is automatically determined by a discovery module of a switching device. Upon determining the existence of the firewall security device, a command channel is established with the firewall security device by a communication module of the switching device. The switching device may then receive commands issued by the firewall security device through the command channel relating to configuration of one or more Virtual Local Area Networks (VLANs). |
| US10263836B2 |
Identifying troubleshooting options for resolving network failures
Described herein are various technologies pertaining to providing assistance to an operator in a data center with respect to failures in the data center. An alarm is received, and a failing device is identified based upon content of the alarm. Failure conditions of the alarm are mapped to a failure symptom that may be exhibited by the failing device, and troubleshooting options previously employed to mitigate the failure symptom are retrieved from historical data. Labels are respectively assigned to the troubleshooting options, where a label is indicative of a probability that a troubleshooting option to which the label has been assigned will mitigate the failure symptom. |
| US10263834B2 |
Communication apparatus, control method, and storage medium for transmitting data in different antenna directions
A communication apparatus sets a first antenna direction to be used in a first time slot among a plurality of time slots, and a second antenna direction to be used in a second time slot among the plurality of time slots, transmits first data in the first time slot by using a first communication path using the first antenna direction, retransmits the first data in the second time slot by using a second communication path using the second antenna direction if transmission of the first data has failed, and transmits second data different in type from the first data in the second time slot by using the second communication path using the second antenna direction if transmission of the first data has succeeded. |
| US10263833B2 |
Root cause investigation of site speed performance anomalies
The disclosed embodiments provide a system for processing data. During operation, the system obtains a set of components of a time-series performance metric associated with an anomaly in a performance of one or more monitored systems. For each component in the set of components, the system performs a statistical hypothesis test on the component to assess a deviation of the component from a baseline value of the component. When the statistical hypothesis test identifies a statistically significant deviation of the component from the baseline value, the system outputs an alert comprising a root cause of the anomaly that is represented by the statistically significant deviation of the component from the baseline value. |
| US10263829B2 |
Network element reachability
Embodiments of the present invention include systems and methods for detecting status of network elements, such as, applications, information handling systems, links, and the like, in a network. In embodiments, a system for detecting status of network elements in a network includes an agent that monitors status of one or more network elements related to a first information handling systems and sends a status notice to a status controller. In embodiments, the status controller receives status information from a number of status agents operating on other information handling systems in the network and uses that information to generate one or more reachability graphs. In embodiments, the status controller sends at least part of a reachability graph to one or more of the status agents in the network. In embodiments, an application on an information handling systems may query the local status agent to obtain status information regarding a network element. |
| US10263828B2 |
Preventing concurrent distribution of network data to a hardware switch by multiple controllers
Some embodiments provide, for a first controller application, a method for configuring a managed hardware forwarding element (MHFE) to implement one or more logical networks. The method of some embodiments receives logical network data that defines at least one logical forwarding element of a logical network to be implemented by the MHFE. The method then identifies a set of tables of a database instance that is instantiated on the MHFE in order to distribute the logical network data to the MHFE. In some embodiments, the method monitors the identified set of tables in order to determine whether a second controller application updates any one of the set of tables. The method distributes the logical network data to the MHFE so long as none of the tables in the set of tables is updated by the second controller application. |
| US10263823B2 |
Communicating synchronization signals in wireless communications
Aspects of the present disclosure describe receiving synchronization signals in wireless communications. A block of synchronization signals can be received from a base station in a first time interval. A beam identifier and a redundancy version associated with the block of synchronization signals can be determined. A broadcast channel can be received based at least in part on a timing associated with the beam identifier. The broadcast channel can be descrambled based at least in part on a scrambling code associated with the redundancy version. |
| US10263820B2 |
Channel sounding using multiple sounding configurations
More than one set of sounding signal configuration parameters are determined for the same mobile terminal. The mobile terminal uses the sets of configuration parameters to generate different sounding reference signals which can be used for different purposes such as estimating timing and channel quality. In one embodiment, a method of configuring uplink sounding transmissions by mobile terminals in a wireless communication network is characterized by determining different sets of configuration parameters for sounding signal transmissions for a given mobile terminal (200). The different sets of configuration parameters are transmitted to the mobile terminal, allowing the mobile terminal to generate different sounding signals for different uses by the wireless communication network (202). |
| US10263816B2 |
Method and system for split voltage domain receiver circuits
Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit. |
| US10263814B2 |
Method and system for providing scrambled coded multiple access (SCMA)
A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme. |
| US10263813B1 |
Signal receiving apparatus and signal processing method thereof
A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance. |
| US10263811B2 |
Equalizing device, equalizing method, and signal transmitting device
An equalizing device has: a low-frequency zero-point circuit having a zero point in a low-frequency band of a before-equalization frequency characteristic of a communication medium; a high-frequency zero-point circuit having a zero point in a high-frequency band of the before-equalization frequency characteristic of the communication medium; and an intermediate-frequency zero-point circuit having a zero point in an intermediate-frequency band present between the low-frequency band and the high-frequency band, wherein an inclination of a waveform of the before-equalization frequency characteristic of the communication medium changes in the intermediate-frequency band; wherein the equalizing device equalizes the signal transmitted through the communication medium so as to restrain an amount of change in an inclination of a waveform of the after-equalization frequency characteristic. |
| US10263810B2 |
Estimating signals in sub-sampled systems
Embodiments are disclosed for improving precoder-matrix computations in a MIMO base station. Particularly, various embodiments implement methods for interpolating pilot signal results from multiple calibration transmissions. A subchannel of a resource block is selected as an anchor subchannel and the channel matrices for each subchannel are then determined using weights associated with each subchannel that are determined from the subchannel's distance away from the anchor subchannel. Selecting variable subchannels allows the accuracy of the channels matrices for the subchannels to be tailored where more accuracy is desired. |
| US10263801B2 |
Method and system for a high capacity cable network
A cable modem termination system (CMTS) may communicate with a plurality of cable modems using a plurality of orthogonal frequency division multiplexed (OFDM) subcarriers. The CMTS may determine a performance metric of each of the cable modems. For each of the OFDM subcarriers and each of the cable modems, the CMTS may select physical layer parameters to be used for communication with that cable modem on that OFDM subcarrier based on a performance metric of that cable modem. The parameters may be selected for each individual modem and/or each individual subcarrier, or may be selected for groups of modems and/or groups of subcarriers. The parameters may include, for example, one or more of: transmit power, receive sensitivity, timeslot duration, modulation type, modulation order, forward error correction (FEC) type, and FEC code rate. |
| US10263799B1 |
Managing meeting data
A device may receive meeting data associated with a first meeting, the first meeting having previously occurred. The device may obtain, based on the meeting data, data identifying at least one individual associated with the first meeting and data identifying at least one topic associated with the first meeting. In addition, the device may identify a second meeting based on the at least one individual or the at least one topic, the second meeting having not yet occurred. The device may provide, to a user device associated with the second meeting and based on identifying the second meeting, at least a portion of the meeting data associated with the first meeting. |
| US10263797B2 |
Packet-switched core network architecture for voice services on second- and third-generation wireless access networks
Communications systems and methods with an evolved packet-switched core network architecture to enable voice services on second- and third-generation wireless access networks. The systems and methods permit unmodified 2G and 3G mobile devices to conduct voice calls using conventional circuit-switched user-plane and control-plane protocols at the air interface while the voice calls are switched at the back-end using a packet-switched core network. The system may include a translation module at a controller component that is configured to provide both user-plane and control-plane translation functions between an unmodified 2G/3G mobile device that utilizes circuit-switched protocols for a voice call and the packet-switched core network that utilizes packet-switched protocols to switch the voice call. |
| US10263793B2 |
Devices with modifiable physically unclonable functions
A device may include a physically unclonable function (PUF) source that has at least one fuse embedded in the device. The PUF source may be responsive to an input for transmitting a signal through the fuse and providing a PUF value based on a measurement of such signal. The device also has circuitry that is configured to modify the fuse by transmitting a signal of sufficiently high current or voltage through the fuse to change its resistance, thereby changing a response of the PUF source to the input. |
| US10263792B2 |
Cryptographic key escrow
An escrow platform is described that can be used to enable access to devices. The escrow platform can be used to sign cryptographic network protocol challenges on behalf of clients so that the secrets used to sign cryptographic network protocol challenges do not have to be exposed to the clients. The escrow platform can store or control access to private keys, and the corresponding public keys can be stored on respective target platforms. A client can attempt to access a target platform and in response the target platform can issue a challenge. The client platform can send the challenge to the escrow platform, which can use the corresponding private key to sign the challenge. The signed challenge can be sent back to the client, which can forward it to the target platform. The target platform can verify the expected private key and grant access. |
| US10263786B2 |
Intelligent sensor and controller framework for the power grid
Disclosed below are representative embodiments of methods, apparatus, and systems for monitoring and using data in an electric power grid. For example, one disclosed embodiment comprises a sensor for measuring an electrical characteristic of a power line, electrical generator, or electrical device; a network interface; a processor; and one or more computer-readable storage media storing computer-executable instructions. In this embodiment, the computer-executable instructions include instructions for implementing an authorization and authentication module for validating a software agent received at the network interface; instructions for implementing one or more agent execution environments for executing agent code that is included with the software agent and that causes data from the sensor to be collected; and instructions for implementing an agent packaging and instantiation module for storing the collected data in a data container of the software agent and for transmitting the software agent, along with the stored data, to a next destination. |
| US10263783B2 |
Method and system for authenticating a data stream
A method for authenticating a data stream includes selecting a number of data fragments of the data stream, defining at least two granularity levels for the selected data fragments, dividing each of the selected data fragments according to the granularity levels, generating a hierarchical authentication structure including elements representing hash values of the divided selected data fragments on the different granularity levels, selecting at least a portion of the hash values of the hierarchical authentication structure for transmission to a receiver, reconstructing the granularity value on the top level of the hierarchical authentication structure based on the transmitted hash values, and performing authentication of the data fragments of the data stream based on comparing the reconstructed value on the top granularity level of the hierarchical authentication structure with the signed value on the top granularity level of the generated hierarchical authentication structure. |
| US10263781B2 |
IC chip and authentication method for user authentication
An IC chip for preventing an authentication key from leaking, and an authentication key setting and authentication key verifying method are provided. A part performing connection or disconnection between an external terminal and a smartcard chip may be configured by a separate chip or may be incorporated into the smartcard chip to configure a single chip. When the part is configured by the separate chip, the disconnection between the external terminal and the smart card chip can be performed according to whether an authentication key is verified. When the part is configured by the one chip, the disconnection between the external terminal and the smart card chip can be performed under a control of the smartcard chip according to whether the authentication key is verified. |
| US10263777B2 |
Systems and methods for secure communications using organically derived synchronized encryption processes
Organically Derived Synchronized Processes provide encryption parameter management in a certificate-less system. A first node generates a parameter data set containing multiple values; uses a seed value stored at the first node to select values from a random parameter data set to form a parameter subset; generates encryption parameters using the subset; encrypts user data using the encryption parameters; generates a signature based at least on the parameter data set; and transmits a start frame including the parameter data set, the encrypted user data, and the signature. A second node receives the start frame; uses a seed value stored at the second node to select values from the received parameter data set to form a parameter subset; generates decryption parameters using the subset; decrypts the user data using the decryption parameters; and verifies the received signature. The encryption and decryption parameters are then applied to further payload data. |
| US10263775B2 |
Policy-based key recovery
A device establishes a key recovery policy and generates a key that is protected based on the key recovery policy. The key recovery policy indicates which combinations of other entities can recover the protected key. The device generates different shares of the protected key, each share being a value that, in combination with the other share(s), allows the protected key to be recovered. Each share is associated with a particular leaf agent, the device encrypts each share with the public key of the leaf agent associated with the share and provides the encrypted share to a service. When recovery of the protected key is desired, a recovering authority can generate the protected key only if the recovering authority receives decrypted shares from a sufficient one or combination of leaf agents as indicated by the recovery policy. |
| US10263774B2 |
Ensuring authenticity in a closed content distribution system
A technique for maintaining encrypted content received over a network in a secure processor without exposing a key used to decrypt the content in the clear is disclosed. |
| US10263772B2 |
Smart card chip for generating private key and public key pair, and generation method therefor
The smart card chip for generating a private key and public key pair in accordance with an embodiment of the present invention comprises: a communication unit for performing at least one of a contact communication with an external device and a near-field wireless communication therewith; a control unit for communicating with the external device through the communication unit and generating a private key and public key pair; and a memory unit for storing the generated private key and public key pair, wherein if receiving a command to generate a private key and public key pair from the external device, the control unit checks if a pre-generated private key and public key pair is stored in the memory unit, and if the pre-generated private key and public key pair is stored in the memory unit, the control unit reads the pre-generated private key and public key pair. |
| US10263769B2 |
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. |
| US10263767B1 |
System and method for power analysis resistant clock
A system and method to mitigate or complicate the use of differential power analysis (DPA) and simple power analysis (SPA) in the attack of a targeted integrated circuit, or device containing an integrated circuit, that is processing sensitive information. The system and method modifies the regularity of a clock that initiates the power events within the circuit such that subsequent processing of information does not always occur at the same time. |
| US10263766B1 |
Independent pair 3-phase eye sampling circuit
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol. |
| US10263765B2 |
Systems and methods for low-power single-wire communication
Systems and methods for low-power single-wire communication are provided. In some embodiments, a method of operation of a transmitter to transmit a data word to a receiver using low-power single-wire communication includes receiving the data word to be transmitted to the receiver. The method also includes encoding the data word to be transmitted in a Pulsed Index Communication (PIC) format to produce a PIC data word and transmitting the PIC data word to the receiver. In this way, the transmitter may be able to transmit an increased amount of data while maintaining a simple communication protocol that uses low power and does not require a Clock-Data Recovery circuit. |
| US10263760B2 |
Method for time synchronization
Embodiments relate to a method for time synchronization and, more particularly, to a method for time synchronization between devices and the devices using the same. The method for time synchronization includes: receiving data from a first device; checking time information of the first device, which is included in the received data; and correcting a time error based on the checked time information, wherein the time error is corrected using a correction constant according to a time error relative to the first device. |
| US10263758B2 |
Half duplex FDD WTRU with single oscillator
Half duplex (HD) frequency division duplexing (FDD) in a wireless transmit-receive unit (WTRU) using a single oscillator (SO) for uplink (UL) and downlink (DL), which may contribute to reduced costs of implementation. Approaches to the resolution of scheduling issues which may result from increased switching time versus implementations using separate oscillators are discussed, including indication of SO-HD-FDD capability, scheduling for collision avoidance, enhanced node-b (eNB) receiver implementations, link adaptation for missed detected physical downlink control and shared channels, collision handling, DL measurement, and burst based transmissions. |
| US10263755B2 |
Method and apparatus for sending response information and computer storage medium
A method and an apparatus for sending response information and a computer storage medium are disclosed. The method comprises: determining a Hybrid Automatic Repeat reQuest (HARQ) timing corresponding to a downlink subframe, wherein the downlink subframe is a downlink subframe, for which a feedback of HARQ-ACK response information is needed, and is located in a Frequency Division Duplexing (FDD) downlink or uplink frequency spectrum; and sending the HARQ-ACK response information corresponding to the downlink subframe according to the determined HARQ timing. |
| US10263752B2 |
Communication method and electronic device for performing the same
An electronic device includes a first communication module, a second communication module, a memory, a processor configured to be electrically connected with the first communication module and the second communication module, and a memory. The processor is configured to verify a first data packet to be transmitted via the first communication module. The processor is also configured to obtain scheduling information of a second data packet received via the second communication module. The processor is also configured to adjust a time when transmission of the first data packet is started, based on the scheduling information. |
| US10263750B2 |
Cross indication of queue size in a reverse direction protocol
This disclosure describes systems, methods, and computer-readable media related to cross indication of queue size in a reverse direction protocol. In some embodiments, a reverse direction (RD) grantor may transmit a frame to an RD responder. The RD responder may identify data to be transmitted to the RD grantor based on the received frame. The RD responder may generate a frame that may comprise a plurality of sub-frames. The RD responder may set a sub-field in each of the sub-frames indicating whether there is data to transmit. The RD responder may also set a second sub-field that may indicate a priority or traffic stream associated with the data to be transmitted. The RD responder may transmit the frame (and associated sub-frames) to the RD grantor. |
| US10263742B2 |
Coordinated communication method and system and apparatus
Embodiments of the present disclosure provide a coordinated communication method which can reduce a transmission delay in inter-base-station coordinated communication when reliability of the inter-base-station coordinated communication is ensured. The method may include: sending first instruction information and second instruction information to each of n first base stations, so that each of the n first base stations establishes a first interface and a second interface according to the first instruction information and the second instruction information; receiving, by using the second interface, measurement information reported by each of the n first base stations, where the measurement information is a measurement results of m cells; determining resource configuration information of the m cells according to the measurement information; and sending the resource configuration information of the m cells to each of the n first base stations by using the first interface. |
| US10263741B2 |
Coordinated multipoint (CoMP) and network assisted interference suppression/cancellation
A method of wireless communications identifies a first virtual cell identity. The method also includes determining one or more virtual cells based on the identified first virtual cell identity. The method further includes processing one channel based on the determination. |
| US10263740B2 |
Transmission method, reception method, transmitter, and receiver
When transmitting signals from a plurality of base stations (broadcasting stations), the base stations include at least a first base station having a first antenna with a first polarization and a second base station having a second antenna with a second polarization that is different from the first polarization. Then, when the first base station transmits a signal from the first antenna having the first polarization, the second base station transmits the same signal as the first antenna of the first base station from a second antenna having the second polarization, at the same time. |
| US10263737B2 |
Techniques for managing transmissions of uplink data over an unlicensed radio frequency spectrum band
Techniques are described for wireless communication. A first method may include performing a clear channel assessment (CCA) on an unlicensed radio frequency spectrum band; transmitting an indication of a time division duplexing (TDD) configuration over the unlicensed radio frequency spectrum band when the CCA is successful; and transmitting downlink data over the unlicensed radio frequency spectrum band in accordance with the TDD configuration when the CCA is successful. A second method may include performing a CCA on an unlicensed radio frequency spectrum band; dynamically determining, based at least in part on at least one grant to a user equipment (UE), and for a period following the CCA, a number of uplink subframes for communication over the unlicensed radio frequency spectrum band; and transmitting downlink data over the unlicensed radio frequency spectrum band in accordance with the timing of the number of uplink subframes when the CCA is successful. |
| US10263735B2 |
Tone block allocation for orthogonal frequency division multiple access data unit
For a first group of devices having a first group size, a set of block allocations is selected from a codebook. A block allocation for the first group of devices is selected from the selected set of block allocations. A corresponding integer number of different orthogonal frequency division multiplexing (OFDM) tone blocks is assigned to each device of the first group of devices according to the allocation. An orthogonal frequency division multiple access (OFDMA) data unit to be transmitted to the first group of devices via the WLAN communication channel is generated using the assigned set of OFDM tone blocks. The OFDMA data unit includes a preamble portion and a data portion, the preamble portion having an index to the codebook that indicates i) the first group size, and ii) the selected block allocation. |
| US10263725B2 |
Transmission device with mode division multiplexing and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes at least one transceiver configured to modulate data to generate a plurality of first electromagnetic waves. A plurality of couplers are configured to couple at least a portion of the plurality of first electromagnetic waves to a transmission medium, wherein the plurality of couplers generate a plurality of mode division multiplexed second electromagnetic waves that propagate along the outer surface of the transmission medium. Other embodiments are disclosed. |
| US10263722B2 |
Multi-wavelength balanced optical transmission networks
A method for transmitting data over an optical communication system is performed by sequentially tuning a laser beam among a plurality of optical wavelengths. At least one data signal is modulated onto the plurality of optical wavelengths by sequentially switching the modulation of the data signal among the plurality of optical wavelengths such that at any given time the data signal is only modulated onto a single one of the optical wavelengths. The sequential switching is performed at a rate equal to or greater than a response time of one or more optical amplifiers used for amplifying the optical wavelengths. |
| US10263719B2 |
Method and system for interference avoidance in a multi-protocol communication system
Methods and systems for interference avoidance in a multi-protocol communication system may comprise receiving signals in a first communications protocol in a first frequency range and preventing interference signals from being generated in said first frequency range by configuring channel usage in a second communications protocol in a second frequency range based on said received signals. The configuring channel usage may include avoiding communicating in taboo channels and the received signals in said first communications protocol and signals in said configured channels in said second communications protocol may be communicated over one or more coaxial cables based on the configured channel usage. The taboo channels may be selected based on said received signals such that interference signals from said second frequency range do not occur in said first frequency range. The first frequency range comprises a cable or satellite television frequency range, or data over cable service interface standard (DOCSIS). |
| US10263715B1 |
Transmitter and a post-cursor compensation system thereof
A post-cursor compensation system includes a state detector that receives a signal on a data line to detect a predefined state, and accordingly generates a clear control signal; a synchronization detector that receives the signal on the data line and the clear control signal to detect at least one synchronization state, and accordingly generates a trigger signal; and a compensation generator that receives the trigger signal and accordingly generates a compensation signal. |
| US10263708B2 |
Dual parallel Mach-Zehnder-modulator device with pre-distorted driving voltages
Disclosed herein is a dual parallel Mach-Zehnder-modulator (DPMZM) device comprising a DPMZM 10 having first and second inner MZMs arranged parallel to each other. The first inner MZM generates an in-phase component EI of an optical signal in response to a first driving voltage VI, and the second inner MZM generates a quadrature component EQ of said optical signal in response to a second driving voltage VQ. Further disclosed is a calculation unit 52 configured for receiving an in-phase component yI and a quadrature component yQ_ of a desired base-band signal, and for calculating pre-distorted first and second driving voltages VI, VQ. The calculation of the pre-distorted first and second driving voltages VI, VQ is based on a model of said DPMZM 10 accounting for I-Q cross-talk, and using an algorithm that determines said first and second driving voltages VI, VQ each as a function of both of said in-phase and quadrature components yI, yQ of said base-band signal. |
| US10263706B2 |
Single-fiber bidirectional controller area network bus
A controller area network (CAN) comprising a plurality of CAN nodes that communicate via a CAN bus that comprises a fiber optical network. The fiber optical network uses a single fiber and a single wavelength for transmit and receive, and comprises a passive reflective optical star. The reflective optical star comprises an optical mixing rod having a mirror at one end. The other end of the reflective optical star is optically coupled to the transmitters and receivers of a plurality of optical-electrical media converters by way of respective high-isolation optical Y-couplers. Each CAN node produces electrical signals (in accordance with the CAN message-based protocol) which are converted into optical pulses that are broadcast to the fiber optical network. Those optical pulses are then reflected back to all CAN nodes by the reflective optical star. |
| US10263701B2 |
Display method, non-transitory recording medium, and display device
A display method capable of displaying an image valuable to a user is disclosed. The display method according to an embodiment of the present disclosure includes: Step S41 of capturing, by an imaging sensor, a still image lit up by a transmitter that transmits a signal by luminance change of light as a subject to obtain a captured image; Step S42 of decoding the signal from the captured image; and Step S43 of reading video corresponding to the decoded signal from a memory and superimposing the video on a target region corresponding to the subject in the captured image for display on a display. In Step S43, out of a plurality of images included in the video, the plurality of images is sequentially displayed from a leading image identical to the still image. |
| US10263698B2 |
Monitoring apparatus for optical signal to noise ratio, signal transmission apparatus and receiver
Embodiments of the present disclosure provide a monitoring apparatus for an optical signal to noise ratio, a signal transmission apparatus and a receiver. White noise power of received signals is calculated according to noise power and power of pilot signals of the received signals in different polarization states, and influence of a nonlinear noise is excluded, thereby accurately estimating an optical signal to noise ratio, for example, with a calculation process being simple and an application range being relatively wide. |
| US10263694B2 |
Satellite provisioning of cell service
Satellite provisioning of cell service for an in-vehicle telematics control unit (“TCU”) is presented. Thus, a truly carrier independent TCU is facilitated. A TCU may be provided with a cellular modem and two or more SIM cards, each associated with a cellular carrier that has approved the modem and their SIM card. The TCU may also be provided with connectivity to a satellite, such as, for example, via an SDARS antenna and processing module, that can receive and process SDARS audio and data signals. When a user desires to change from one of the cellular carriers to another, provisioning data for the new carrier's SIM, now already in the telematics system, may be (i) sent over the satellite, (ii) received at the satellite antenna, and (iii) passed to a telematics processor. The telematics processor, in turn, may (iv) deliver the provisioning data to the cell modem, which may then (v) program the appropriate SIM with the provisioning data, thus allowing cellular communications on the new carrier's network. The inventive functionality facilitates easily switching carriers as one crosses a border, or when a new vehicle is imported to a given country, and cellular service then or there available on one of the approved carriers is easily chosen by a user and turned on. The TCU may also include a Wi-Fi module, configured to receive provisioning instructions or data over a Wi-Fi network. |
| US10263691B2 |
Dynamic reverse link retransmission timelines in satellite communication systems
A method and apparatus for operating a satellite access network (SAN) of a satellite communication system to schedule communications with a user terminal. In some aspects, the SAN may provision a communication frame, for the user terminal, into a number of forward-link (FL) subframes and a different number of reverse-link (RL) subframes. The SAN then transmits the FL subframes to the user terminal via a forward link of the satellite communication system, and subsequently receives the RL subframes from the user terminal via a reverse link of the satellite communication system. |
| US10263690B2 |
Handover based on predicted network conditions
Methods and systems are described for providing satellite beam handover based on predicted network conditions. In embodiments, a satellite communications system retrieves flight plan data for a plurality of aircraft being provided a network access service, identifies, for each aircraft respective candidate satellite beams of the plurality of satellite beams for providing the network access service, each candidate satellite beam having an associated service timeframe for providing the network access service, obtains, for each of the respective candidate satellite beams, a beam utilization score indicative of predicted beam utilization by the plurality of aircraft over the associated service timeframe, selects satellite beams for providing the network access service of each aircraft of the plurality of aircraft based at least in part on the beam utilization scores, and schedules handover of the network access service for the plurality of aircraft to the selected satellite beams. |
| US10263688B2 |
Method to detect when vehicle is out of LOS datalink network area so messages from vehicle can be proactively directed to different available network
A method for vehicle communications is disclosed. The method comprises monitoring, in a vehicle during travel, line of sight (LOS) datalink messages sent to one or more other vehicles from one or more ground stations in a LOS datalink network coverage area, and calculating a rate in which the LOS datalink messages are sent to the other vehicles. The method detects that the vehicle is substantially out of the LOS datalink network coverage area, when the LOS datalink messages rate drops below a threshold value. Messages are transmitted from the vehicle over a different available network when the vehicle is substantially out of the LOS datalink network coverage area. |
| US10263687B2 |
Phase-diversity radio-frequency receiver
A phase-diversity radio-frequency receiver, including two tuners tuned to the same frequency in order to produce two intermediate frequency signals, a combiner capable of implementing a constant modulus algorithm, CMA, in order to combine the two intermediate frequency signals into a single signal, a controller capable of transforming the single signal into a final signal having a constant envelope, the controller being parametrized by a control coefficient defining the control convergence speed, the control coefficient being recalculated permanently in accordance with at least one multi-path level. |
| US10263686B2 |
Communication system, transmission device, and communication method
A reception device includes receivers and controller. Receivers receive a plurality of modulation signals modulated by a transmission device. Controller selects a communication scheme on the basis of phase difference between reception signals, which are the modulation signals received by the receivers, and of polarization plane deviation of the reception signals from transmission signals, which are the modulation signals transmitted from the transmission device, and sets, for the transmission device, a modulation scheme corresponding to the communication scheme. |
| US10263682B2 |
Channel state prediction based on prediction of channel state factors
The present disclosure generally discloses a channel state prediction capability. In a communication system including a transmitter and a receiver communicating via a communication channel, the channel state prediction capability may enable the transmitter to transmit to the receiver via the communication channel based on a predicted channel state of the communication channel. The predicted channel state may be a prediction of the channel state at a future time at which data transmitted by the transmitter is expected to be received by the receiver, which may be based on a total round trip latency of the communication channel. The predicted channel state may include one or more parameters (e.g., a predicted channel quality indicator, a predicted rank indicator, or the like). The predicted channel state may be predicted based on predictions of channel state factors which may impact the channel state of the communication channel (e.g., path loss, shadow fading, fast fading, or the like). |
| US10263680B2 |
Method and apparatus for generating feedback in a communication system
Methods and apparatuses are provided for reporting channel status by a user equipment (UE) in a communication system. Information on at least one channel status information reference signal is received from an evolved node B. A first channel status based on a first period and a first set of the at least one channel status information reference signal, is reported to the evolved node B. A second channel status based on a second period and a second set of the at least one channel status information reference signal, is reported to the evolved node B. The first channel status includes at least one of a precoding matrix indicator (PMI), a channel quality indicator (CQI), and a ranking indication (RI), and the second channel status includes at least one of a CQI, a PMI and a RI. The RI of the second channel status is same as the RI of the first channel status. |
| US10263679B2 |
Method for supporting beamforming in communication network
Disclosed are a method and an apparatus for performing communications based on multiple antennas in a communication network. An operation method performed in a multi-antenna performing beamforming in a communication network according to the present disclosure may comprise selecting a beamformer generating a transmission beam for transmitting data to a plurality of communication nodes included in the communication network among a plurality of beamformers included in the multi-antenna; selecting at least one antenna panel corresponding to each of the plurality of communication nodes among a plurality of antenna panels included in the selected beamformer; configuring parameters for respectively allocating independent transmission beams to the plurality of communication nodes based on the selected at least one antenna panel; and transmitting data to the plurality of communication nodes using transmission beams through the plurality of antenna panels based on the configured parameter. |
| US10263678B2 |
Preamble design within wireless communications
A wireless communication device (alternatively, device) includes a processor configured to support communications with other wireless communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other wireless communication device(s) and to generate and process signals for such communications. The device is configured to generate OFDM/A packets having certain characteristics based on different packet formats. For example, a first OFDM/A packet has first characteristic(s) based on a first packet format, a second OFDM/A packet has second characteristic(s) based on a second packet format, and so on. A receiver device is configured to process such OFDM/A packets to determine characteristic(s) thereof to determine, identify, classify, etc. their respective packet formats so that the OFDM/A packets can be properly and appropriately processed based on their particular packet formats. |
| US10263676B2 |
Layer mapping method and data transmission method for MIMO system
A method for indicating a combination between a codeword and a layer in a MIMO communication, system, a layer mapping method, and a data transmission method using the same are disclosed. A minimum number of codeword-layer mapping combinations from among all available combinations based on the’ numbers of all codewords and all layers are pre-defined in consideration of a ratio of a codeword to a layer, a reception performance of a receiver, and reduction of combinations, so that a data transmission method using the predefined combinations is implemented. If a specific one codeword is mapped to at least two layers, a diversity gain can be acquired. |
| US10263675B2 |
Method and device for efficient precoder search
The disclosure relates to a method performed in a wireless device for establishing a feedback metric. The wireless device is configured with a grouping of available precoding matrix indicators, PMIs, of a codebook, the grouping comprising two or more groups each of which comprises an exclusive subset of the available precoding matrix indicators, PMIs. The method comprises: identifying for one or more rank indicator, RI, hypotheses a respective parent PMI providing the highest link quality metric, LQM; establishing for one or more of the identified parent PMIs, a respective set of child PMIs; determining a link quality metric, LQM for each child PMIs of the established one or more sets of child PMIs; and establishing the feedback metric to be the child PMI having the highest link quality metric, LQM. The disclosure also relates to a wireless device, method in a network node, network node, computer programs and computer program products. |
| US10263674B2 |
Method for determining precoding matrix indicator, user equipment, and base station
A method for determining a precoding matrix indicator, user equipment, and a base station are disclosed in embodiments of the present invention. The method includes: receiving a first reference signal set sent by a base station, where the first reference signal set is associated with a user equipment-specific matrix or matrix set; selecting a precoding matrix based on the first reference signal set, where the precoding matrix is a function of the user equipment-specific matrix or matrix set; and sending a precoding matrix indicator to the base station, where the precoding matrix indicator corresponds to the selected precoding matrix. In the embodiments of the present invention, CSI feedback precision can be improved without excessively increasing feedback overhead, thereby improving system performance. |
| US10263673B2 |
Signal transmission method and device
Embodiments of the present invention provide a signal transmission method and device. The method includes: determining, by a sending device, a target precoding matrix V, where V=(H)−1·{tilde over (H)}, H indicates a channel matrix between the sending device and a receiving device, {tilde over (H)} indicates an equivalent channel matrix between the sending device and the receiving device, ({tilde over (H)}H·{tilde over (H)}) or ({tilde over (H)}·{tilde over (H)}H) is a diagonal matrix, and {tilde over (H)} is related to a transmission distance D between the sending device and the receiving device and an element spacing of an antenna of the receiving device; and sending, by the sending device, a signal to the receiving device according to the target precoding matrix V. Because {tilde over (H)} meets a characteristic that ({tilde over (H)}H·{tilde over (H)}) or ({tilde over (H)}·{tilde over (H)}H) is a diagonal matrix, a channel corresponding to {tilde over (H)} can support multiple data stream transmission. Therefore, the signal transmission method and device provided in the embodiments of the present invention can support multiple data stream transmission. |
| US10263669B2 |
Tiered control of iterative MIMO receivers
In order to balance the power requirements of a MIMO receiver with the gains that may be achieved through its use, an apparatus determines whether a current configuration of the UE supports iterative MIMO reception. When it is determined that the current configuration of the UE supports iterative MIMO reception, the apparatus determines whether at least one parameter of the received signal is within a corresponding target condition, respectively, for each of the at least one parameters, e.g., including determining whether a scheduling percentage meets a scheduling threshold and whether an error rate is within an error rate range. When both the configuration supports iterative MIMO reception and the signal parameter(s) meet the corresponding target condition(s), the apparatus uses the iterative MIMO receiver. If not, the apparatus uses a serial receiver. |
| US10263667B2 |
Mesh network device with power line communications (PLC) and wireless connections
Network hardware devices organized in a wireless mesh network (WMN) in which one network hardware devices includes a first wireless radio and a power line communications (PLC) radio coupled to a processing device. The processing device communicates, using the first wireless radio, first data with a second mesh network device over a wireless link between the first wireless radio and a first wireless radio of the second mesh network device. The processing device also communicates, via the power distribution network via the PLC radio, second data with the second mesh network device over a PLC link between the first PLC radio and a first PLC radio of the second mesh network device. The first data and the second data may be redundant data. The first data may be content data and second data may be control data. The first and second data may be subsets of the same digital content. |
| US10263664B2 |
Signal transmission method, apparatus, and signal transmission system
Embodiments of the present invention provide a signal transmission method. The method includes: sequentially rotating phases of to-be-sent signals on a line set 1 by different angles and in relative to phases of to-be-sent signals on a line set 2, and sequentially sending, to a user side, the to-be-sent signals whose phases are rotated. The method also includes receiving a rotation factor that is of a high-quality received signal on the line set 1 and that is fed back by the user side, where the high-quality received signal includes a received signal with a high signal-to-noise ratio or high power. The method also includes using the rotation factor fed back by the user side as a fixed rotation factor, and rotating, according to the fixed rotation factor, a phase of a signal to be subsequently sent on the line set 1. |
| US10263662B2 |
Cyclic-frequency shift orthogonal frequency division multiplex device
The invention discloses a cyclic-Frequency shift orthogonal frequency division multiplex spread spectrum device, comprising: at least one communication device for performing the conversion between a series of bits and a frequency domain symbol out of a plurality of frequency combination patterns; wherein different patterns correspond to different bit values; and the device forms a cyclic frequency shift value utilizing a frequency reordering, each of the cyclic frequency shift values corresponding to a frequency combination pattern. |
| US10263660B2 |
Methods and apparatus for construction of SCMA codebooks
Disclosed are methods and apparatus used in wireless communications. The methods and apparatus establish a codebook for use in sparse code multiple access (SCMA) encoded communications, in particular. The SCMA codebook is configured to set the codebook for at least one layer (i.e., a user) to include a constellation of points having a first grouping of constellation points located at first radial distance from an origin in a complex plane and a second grouping of constellation points located at a second radial distance from the origin. This codebook arrangement provides increased gains at receivers by optimizing the constellation shape to improve the distance between constellation points (i.e., SCMA codebook performance), and in particular more robust performance when encountering amplitude and phase misalignment in uplink (UL) multiple access. |
| US10263658B2 |
Protective cover and electronic device having it
A protective cover and an electronic device having it are provided. The protective cover for receiving and protecting at least part of an electronic device includes a first case frame comprising a mounting surface for mounting the electronic device, a second case frame for forming an exterior of the protective cover by combining with the first case frame, and at least one electronic component interposed between the first case frame and the second case frame and electrically connected to the electronic device. Thus, the electronic device can be protected from an external impact or a foreign substance, and various additional functions can be performed in aid of the electronic device. |
| US10263651B1 |
Spatial power-combining devices with amplifier connectors
Spatial power-combining devices having amplifier connectors are disclosed. A spatial power-combining device structure includes a plate including a first face, a second face that opposes the first face, an exterior surface between the first face and the second face, and a plurality of amplifier connectors accessible at the exterior surface. A waveguide assembly is coupled to the plate at the first face, the waveguide assembly including an inner housing including a plurality of antenna signal conductors and an outer housing including a plurality of antenna ground conductors. A coaxial waveguide section is coupled to the waveguide assembly. The plurality of amplifier connectors may be radially arranged in the plate. A plurality of amplifier modules are on the exterior surface and coupled to corresponding ones of the plurality of amplifier connectors. |
| US10263647B2 |
Multiplexing architectures for wireless applications
Multiplexing architectures for wireless applications. In some embodiments, a front-end architecture can include a first power amplifier having an output coupled to a transmit filter through a path that is substantially free of a switch. The transmit filter can be configured for a first transmit band or a second transmit band, with the first and second transmit bands at least partially overlapping with each other. The front-end architecture can further include a receive filter configured for at least a first receive band corresponding to the first transmit band, and a second power amplifier having an output capable of being coupled to a first duplexer or a second duplexer through a selector switch. The first duplexer can include a receive portion configured for a second receive band corresponding to the second transmit band. |
| US10263646B2 |
Analog processing system for massive-MIMO
An analog processing subsystem is disclosed. Said subsystem comprising at least one antenna (202,302), a duplexer (202a,302a), at least one power amplifier (203a,203b), at least one mixer (204a,204b, 304a, 304b) and an interface connectable to a baseband processing subsystem. The at least one mixer (204a,204b,304a,304b) is adapted to down-convert and inphase/quadrature—IQ—demodulate a received analog radio frequency signal, received by the at least one antenna (202,302), to provide a received analog baseband signal and to IQ-modulate and up-convert a transmit analog baseband signal, to be transmitted by the at least one antenna (202, 302), to provide a transmit analog radio frequency signal. The analog processing subsystem is comprised on a single analog radio frequency processing chip (201,301) comprising a metallization on at least one side of the chip for integration of the at least one antenna (202,302). |
| US10263645B2 |
Error correction and decoding
In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder. |
| US10263641B2 |
Reception apparatus and associated method of receiving encoded data
A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix. |
| US10263633B2 |
Modulators
This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN). |
| US10263628B2 |
Apparatuses and methods for converting fluctuations in periodicity of an input signal into fluctuations in amplitude of an output signal
An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element. |
| US10263627B1 |
Delay-locked loop having initialization circuit
A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency. |
| US10263623B1 |
Circuit for and method of storing data in an integrated circuit device
A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described. |
| US10263622B2 |
Semiconductor apparatus and method of controlling MOS transistor
[Object] To provide a semiconductor apparatus and a method of controlling a MOS transistor, with which a leak current of the MOS transistor can be suppressed. [Solving Means] A semiconductor apparatus includes a MOS transistor and a voltage application unit that applies, when the MOS transistor is off, a voltage for controlling a threshold value of the MOS transistor in a shallower direction onto a substrate of the MOS transistor. |
| US10263620B2 |
Continuously charged isolated supply network
A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply. |
| US10263608B2 |
Filtered sampling circuit and a method of controlling a filtered sampling circuit
A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal. |
| US10263607B1 |
Pulse filtering circuit
The present disclosure provides a pulse filtering circuit with two input ports and two output ports, including: a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit; each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port; the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port. The new pulse filtering circuit of the present disclosure may eliminate the common-mode noise signal, especially the dV/dt common-mode noise generated by the power supply, and therefore the circuit has a strong anti-dV/dt noise capability and a small transmission delay, and at the same time reduces the chip area and production costs due to its simple circuit structure. |
| US10263598B2 |
Acoustic resonator and method of manufacturing the same
An acoustic resonator and a method of manufacturing the same are provided. The acoustic resonator includes a resonance part including a first electrode, a second electrode, and a piezoelectric layer disposed between the first and second electrodes; and a substrate disposed below the resonance part. The piezoelectric layer is disposed on a flat surface of the first electrode. |
| US10263595B2 |
Method and apparatus for adapting a variable impedance network
The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed. |
| US10263594B2 |
Impedance matching circuit for radio-frequency amplifier
Impedance matching circuit for radio-frequency amplifier. In some embodiments, an impedance matching circuit can include a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier. The impedance matching circuit can further include a secondary metal trace having first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node. The impedance matching circuit can further include a capacitance implemented between the first and second ends of the secondary metal trace, and be configured to trap a harmonic associated with an amplified signal at the output of the power amplifier. |
| US10263592B2 |
Optimal response reflectionless filters
Reflectionless low-pass, high-pass, band-pass, band-stop, all-pass, all-stop, and multi-band filters, as well as a method for designing such filters is disclosed, along with a method of enhancing the performance of such filters through the use of unmatched sub-networks to realize an optimal frequency response, such as the Chebyshev equal-ripple response. These filters preferably function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. The unmatched sub-networks preferably offer additional degrees of freedom by which element values can be assigned to realize improved cutoff sharpness, stop-band rejection, or other measures of performance. |
| US10263588B2 |
Method of manufacturing piezoelectric vibrator element, piezoelectric vibrator element, and piezoelectric vibrator
A method of manufacturing a piezoelectric vibrator element, a piezoelectric vibrator element, and a piezoelectric vibrator, superior in vibration characteristics, high in quality, and capable of suppressing a variation in frequency after a frequency adjustment, are provided. The method includes a first frequency adjustment step of performing ion milling on a weight metal film for a frequency adjustment formed on a surface of a tip part in each of a pair of vibrating arm parts, and a second frequency adjustment step of performing ion milling on the weight metal film at a lower etch rate than in the first frequency adjustment step after the first frequency adjustment step. |
| US10263587B2 |
Packaged resonator with polymeric air cavity package
A packaged resonator includes a substrate, an acoustic stack, a first polymer layer and a second polymer layer. The acoustic stack is disposed over the substrate. The first polymer layer is disposed over the substrate surrounding the acoustic stack. The first polymer layer also provides a first air gap above the acoustic stack. The second polymer layer is disposed over the acoustic stack and above the first air gap. |
| US10263585B2 |
Amplifier system and method for controlling amplifier
An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier. |
| US10263581B2 |
Amplifier calibration
An amplifier circuit can include an amplifier and a resistor network coupled to the amplifier. The resistor network can include a range resistor coupled in parallel to a resistor string, and one or more switches coupled to the resistor string. The resistor network can be used to calibrate gain and common mode rejection ratio (CMRR) of the amplifier circuit. |
| US10263578B2 |
Power amplifier, a radio frequency electronic device and a method for operating a power amplifier
A power amplifier with adjustable voltage standing wave ratio is described which comprises an amplifier unit, a coupler configured to obtain an incident power and a coupled reflected power, and a power control unit. The power control unit is configured to control the amplifier unit. The power control unit has two power detectors configured to provide actuating variables which correspond to the incident power and the reflected power, respectively. The power control unit comprises two digital potentiometers which are configured to variably weight the actuating variables wherein the power control unit is configured to determine a control variable for the amplifier unit based on the actuating variables such that a predetermined power level related to a set value of the voltage standing wave ratio is not exceeded by the incident power and/or the reflected power. Further, a radio frequency electronic device and a method are described. |
| US10263576B2 |
Semiconductor integrated circuit, communication module, and smart meter
A semiconductor integrated circuit includes a transformer that includes a first winding and a second winding, a low-noise amplifier circuit that includes an input terminal in which at least one end of the second winding of the transformer is connected to the input terminal; and a switch that is provided between the one end and another end of the second winding of the transformer. The switch is opened and the transformer functions as an input impedance matching circuit for the low-noise amplifier circuit in a period in which a reception signal is supplied to the first winding of the transformer. On the other hand, the switch is closed and the transformer is caused to become an element including a predetermined capacitance in a period in which another circuit connected to the predetermined node operates. |
| US10263573B2 |
Driver with distributed architecture
A distributed driver for an optic signal generator has a first amplifier cell with one or more amplifiers configured to receive and amplify an input signal to create a first amplified signal. A second amplifier cell has one or more amplifiers configured to receive and amplify the input signal to create a second amplified signal. A first conductive path and second conductive path connects to the first amplifier cell and the second amplifier cell such that the inductance associated with the first and second conductive path counteracts a capacitance associated with the first amplifier cell and the second amplifier cell. A variable capacitor may be part of the first amplifier cell and/or the second amplifier cell to selectively tune the capacitance of the distributed driver. A distributed bias circuit may be part of the first amplifier cell and/or the second amplifier cell to bias an optic signal transmitter. |
| US10263571B2 |
Protection circuit for an RF power amplifier
An RF PA and an RF PA protection circuit are disclosed according to one embodiment of the present disclosure. The RF PA includes an RF PA bias circuit and an RF PA transistor element. The RF PA transistor element has a first current terminal and a control terminal. The RF PA protection circuit is coupled between the RF PA bias circuit and the first current terminal. The RF PA protection circuit reduces a current through the first current terminal using the RF PA bias circuit when a magnitude of a voltage at the first current terminal exceeds a protection threshold. |
| US10263570B2 |
Amplifier arrangement and method
The present invention provides an amplifier arrangement for amplifying a broadband signal, the amplifier arrangement comprising a signal splitter configured to receive the broadband signal and output a first split signal and a second split signal, and a balanced amplifier that is coupled to the signal splitter and is configured to amplify the first split signal and the second split signal and is configured to output a single amplified broadband signal based on the amplified first split signal and the amplified second split signal. The present invention further provides a respective method. |
| US10263564B2 |
Voltage-controlled oscillator
A voltage-controlled oscillator includes a first transistor, a second transistor, a first center-tapped inductor, two first varactors, a second center-tapped inductor and two second varactors. The first and second transistors cooperatively forma cross-connected pair. The first center-tapped inductor and the first varactors cooperatively form a first LC tank. The second center-tapped inductor and the second varactors cooperatively forma second LC tank. The cross-connected pair is connected between the first and second LC tanks. The first and second center-tapped inductors are mutual-inductively coupled to each other. An oscillation signal pair is provided between the first LC tank and the cross-connected pair. |
| US10263554B2 |
Power supply device for internal combustion engine
A power supply device for an internal combustion engine, using a generator driven by an internal combustion engine as a power source and supplying power to a first load that needs to be constantly driven to cause the internal combustion engine to operate and a second load that is permitted not to drive during startup of the engine, wherein a first generation coil for driving the first load and a second generation coil for driving the second load are provided to be magnetically-coupled tightly in the generator, and voltage supplied to a load is boosted to a higher voltage value than conventionally achieved by performing chopper control of an energizing current of the first generation coil and an energizing current of the second generation coil while preventing energization from the second generation coil to a load. |
| US10263550B2 |
Gas turbine power generation system and control system used in the same
A gas turbine power generation system having an improved function to stabilize the power system is disclosed. The gas turbine power generation system has a dual-shaft gas turbine, an electric generator mechanically connected to a low pressure turbine of the dual-shaft gas turbine and electrically connected to an electric power system, a rotary electric machine mechanically connected to a high pressure turbine through a compressor of the dual-shaft gas turbine and electrically connected to the electric power system, wherein a power oscillation is suppressed by operation of the rotary electric machine as a motor or as a generator. |
| US10263545B2 |
Motor velocity control within an aircraft hydraulic system
A system comprises an aircraft hydraulic system motor, a position sensor, and a programmable controller. The aircraft hydraulic system motor includes a rotor whose position is detected by the position sensor. The position sensor produces an output representative of that position. The programmable controller is configured to receive the output of the position sensor and calculate an estimated velocity of the aircraft hydraulic system motor based on the output of the position sensor. The calculation of the estimated velocity comprises determining both a high bandwidth velocity estimation and a low bandwidth velocity estimation. The programmable controller is additionally configured to compare the estimated velocity to a desired velocity and direct the aircraft hydraulic system motor to increase or decrease velocity based on the comparison. |
| US10263541B2 |
Robust single-phase DC/AC inverter for highly varying DC voltages
A single-phase DC/AC inverter has a single-phase inverter bridge with binary switches connected to an RLC low-pass filter. Digital control logic in a control circuit (or in a microcontroller) determines and controls a logic state q determining the position of the switches in the inverter bridge from sensed iL, vC values from the RLC filter. The control logic selects one of multiple possible logic states q based on whether the sensed iL, vC values belongs one of multiple boundary regions of a tracking band in an iL, vC state space. |
| US10263538B2 |
Semiconductor device and power conversion device
A semiconductor device according to an embodiment includes a transistor including a first electrode, a second electrode, and a gate electrode, an electric resistance being electrically connected to the gate electrode, a diode including an anode being electrically connected to the first electrode and a cathode being electrically connected between the electric resistance and the gate electrode, and a capacitor being connected in parallel with the electric resistance. |
| US10263534B2 |
Power conversion device
A power conversion device includes a reactor, a single-phase inverter, and a single-phase converter which are connected in series to each other between an AC power supply and a smoothing capacitor, and performs power conversion between AC voltage of the AC power supply and DC voltage of the smoothing capacitor. The power conversion device includes a control unit which controls switch elements of the single-phase inverter and switch elements of the single-phase converter so that charging operation and discharging operation of the DC capacitor are performed in one switching cycle of the single-phase inverter and the charging amount and the discharging amount thereof are equal to each other. |
| US10263531B2 |
Method for manufacturing rectifier and rectifier
A heat dissipation heat sink having a press-fit hole whose inner peripheral surface is a cast skin surface is included; the heat dissipation heat sink is sandwiched by the press-fit head and the insertion guide by aligning the axis of a rectifying element in an insertion guide with the axis of the press-fit hole and making the press-fit head face the heat dissipation heat sink; a protrusion portion of a load receiving jig is made to face the rectifying element in the insertion guide; and the rectifying element is press-fitted into the press-fit hole of the heat dissipation heat sink by pressing the periphery of the press-fit hole of the heat dissipation heat sink (22,23) by the press-fit head and receiving a load applied to the rectifying element by the protrusion portion of the load receiving jig. |
| US10263529B2 |
Electrical circuit for delivering power to electronic devices
One or more embodiments of the present disclosure may include a method of power regulation. The method may include determining a peak voltage level on a primary winding of a transformer. The method may also include selecting a particular coarse current level window based on the determined current level. Wherein the particular coarse current level window is one of a plurality of coarse current level windows. The method may additionally include determining a low window value based on the particular coarse current level window. The method may include generating a reference voltage based on the low window value. The method may also include generating a control signal based on the reference voltage. The method may additionally include transmitting the control signal to a switch circuit coupled to the primary winding of the transformer to adjust the current level on the primary winding of the transformer. |
| US10263526B2 |
Electrical circuit for isolated voltage conversion
A system includes a boost circuit, a capacitive circuit, and a converter circuit. The boost circuit receives a DC signal at a first DC voltage and generates an intermediate AC signal at a first AC voltage based on the DC signal. The capacitive circuit receives the intermediate AC signal at the first AC voltage and generates an isolated AC signal at the first AC voltage based on the intermediate AC signal at the first AC voltage. The converter circuit receives the isolated AC signal at the first AC voltage; generates a first isolated DC signal at a second DC voltage based on the isolated AC signal at the first AC voltage; and generates a second isolated DC signal at a third DC voltage based on the first isolated DC signal at the second DC voltage. The third DC voltage may be less than the second DC voltage. |
| US10263522B2 |
Semiconductor integrated circuit device and power supply system
A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET. |
| US10263520B2 |
DC-DC power converters with step-up and/or step-down mode(s)
A DC/DC power converter connected to a DC power source having first and second DC terminals. The DC/DC power converter operates in voltage step-up and step-down modes. The converter includes first and second DC buses connected to the first and second DC terminals and third and fourth DC buses defining a DC link. Energy storage devices are connected between the third and fourth buses. A first converter leg includes a first branch with switches and a second branch. Each switch includes a controllable semiconductor switch and an anti-parallel connected freewheeling diode. A controller switches the controllable semiconductor switches between a conducting and non-conducting state, in the step-up and step-down modes, switching to supply power from the DC power source to the DC link in the step-up mode and to supply power from the DC link to the DC power source in the step-down mode. |
| US10263515B2 |
Quasi-analog digital pulse-width modulation control
A power supply for a smooth power output level transitioning includes an energy storage circuit for temporarily storing electric energy for driving a load, a semiconductor switch for pulse-width modulation (PWM) switching, and a digital PWM controller. The digital PWM controller generates a driving waveform to regulate on and off status of the semiconductor switch. The driving waveform toggles between PWM periods of a first type and PWM periods of a second type, and gradually adjusts a ratio of numbers of the PWM periods of the two types over time. The toggling driving waveform achieves one or more intermediate finer power output level that cannot be realized by a single type of PWM period with an intermediate duty cycle, due to the minimum item unit of the driving waveform limited by a clock rate of the digital PWM controller. |
| US10263513B2 |
Switched capacitor power converter
A switched capacitor power converter comprising: an input terminal; an output terminal; a plurality of capacitors; a plurality of switches for selectively connecting the plurality of capacitors to each other, and/or to the input terminal, and/or to the output terminal; and a controller configured to operate the plurality of switches based on an output voltage, such that one or more of the plurality capacitors are connected between the input terminal and the output terminal as either: a first-topology, to provide a first conversion ratio; or a second-topology, to provide a second conversion ratio, wherein the second conversion ratio is different to the first conversion ratio. |
| US10263510B2 |
DC/DC resonant converters and power factor correction using resonant converters, and corresponding control methods
Various improvements are provided to resonant DC/DC and AC/DC converter circuit. The improvements are of particular interest for LLC circuits. Some examples relate to self-oscillating circuit and others relate to converter circuits with frequency control, for example for power factor correction, driven by an oscillator. |
| US10263505B2 |
Filtering of alternating voltage components in the intermediate circuit of a rectifier device of a motor vehicle
A rectifier device which is used for a motor vehicle. Such a device includes a switching unit, which is connected to an intermediate circuit and can be operated with a predetermined switching frequency and provided with a plurality of filter elements connected in an intermediate circuit. Each is equipped with an inter intermediate circuit capacitance. A minimum of the magnitude frequency response of a respective filter element is within a different frequency interval, which has a harmonic of the switching frequency as a middle frequency and an interval length corresponding to the switching frequency as a respective minimum of the magnitude frequency response. |
| US10263502B2 |
Voice coil motor
The VCM according to an exemplary embodiment of the present disclosure includes a base unit, a mover including a bobbin arranged at an upper surface of the base unit and formed with a plurality of rotation prevention units along a periphery and a first driving unit arranged at a periphery of the bobbin, a stator including a yoke configured to the base unit to surround the mover and inner yoke units each extended to between the rotation prevention units, and a second driving unit oppositely arranged to the first driving unit, and an elastic member elastically supporting the mover, wherein an object occurrence preventing portion is formed between the rotation prevention unit and the inner yoke units to decrease a contact area between the rotation prevention unit and the inner yoke units. |
| US10263497B2 |
System and method for active cooling of on-machine devices
A system and method for cooling an enclosed position feedback device mounted to a motor is disclosed. An active cooling device is mounted between the position feedback device and the housing enclosing the position feedback device. A compliant mount is provided to accommodate vibration in the position feedback device. The compliant mount may be a compliant thermal pad positioned between the feedback device and the active cooling device. Optionally, the compliant mount may be provided between the motor and the position feedback device. |
| US10263496B2 |
Cooling apparatus for an electric machine
Provided is a cooling apparatus for an electric machine that is integrally combined with the cover of the electric machine and includes a body portion around the circumference of an external surface of the cover that has a first part which is formed at a first angle in a direction away from the cover, and a second part which is formed in a second angle in a downward direction which is opposite the direction of the first part, wherein the first part and the second part form an opening therebetween. The body portion is formed above a plurality of fins attached to a frame of the electric machine, wherein the fresh air is introduced into the fins and mixes with air from an air inlet end and exits through an air outlet end at the opposite end of each fin of the plurality of fins. |
| US10263495B2 |
Rotary electric machine
In a rotary electric machine, a power supply unit includes a metal casing, a power circuit unit mounted in the metal casing, and a control board for controlling an operation of the power circuit unit, and supplies power to a motor main body. The power circuit unit includes a plurality of power semiconductor components and a capacitor unit. The plurality of power semiconductor components and the capacitor unit are disposed alternately on a plane perpendicular to a rotary shaft of the motor main body. |
| US10263492B2 |
Wheel having electricity generation-combined electromechanical means having plurality of auxiliary power structures
The present invention relates to a wheel including a means for power generation and transfer having a plurality of auxiliary power units in which compartments are formed inside one wheel, and a plurality of auxiliary power units capable of generating auxiliary power separately from a main power source are installed in the compartments, such that it is possible to secure increased driving force and rotational force while minimizing costs required for securing compartments required to facilitate a separate auxiliary power source, as well as decrease a used power due to driving an apparatus using the auxiliary power, and by reasonably solving the problems entailed in the wheel including a means for power generation and transfer, efficiency thereof is significantly improved. |
| US10263491B2 |
Electromechanical actuator damping
The invention provides a stator for an electric motor comprising a plurality of teeth separated by slots, and comprising conductive material provided in the slots between two or more of the teeth. |
| US10263488B2 |
Stator with insulating bobbin in a brushless motor
A brushless motor includes a stator core having a plurality of tooth portions; a lower insulating bobbin connected to a lower face of the stator core, the lower insulating bobbin having a plurality of lower slot insulation portions each corresponding to a respective tooth portion; and an upper insulating bobbin connected to an upper face of the stator core, the upper insulating bobbin having a plurality of upper slot insulation portions each corresponding to a respective tooth portions such that the upper slot insulation portions, the tooth portions, and the lower slot insulation portions define a plurality of coil wound portions. The plurality of coil wound portions includes at least one group of coil wound portions with each group having first to sixth coil wound portions. All of the coil wound portions of all groups are wound by a single lead wire. |
| US10263487B2 |
Household appliance electric motor terminal direct socket connection structure
The present invention relates to an electrical household appliance comprising an electric motor with a stator having a core around which a coil is wrapped to be connected to a motor power socket by an electrical connection terminal. An electric motor is disclosed, the electric motor comprising a stator which contains a core wrapped with a coil therearound, an electrical connection terminal into which a mag mate terminal having at least one slit is inserted to be electrically connected to the coil through insertion of the coil into the slit. |
| US10263486B2 |
Rotary electric machine stator
A plurality of coil groups are each configured by connecting a tip portion of a first conductor terminal and a tip portion of a second conductor terminal that is subject to connection therewith using a connecting conductor, and the connecting conductors include: a pair of connecting portions that are respectively disposed so as to contact the tip portion of the first conductor terminal and the tip portion of the second conductor terminal that is subject to connection therewith in a circumferential direction of the tip portions so as to be parallel to the tip portions, and that are joined together with the tip portions; and a linking portion that links the pair of connecting portions. |
| US10263479B2 |
Electrical rotating machine
Provided is a stator for an electrical rotating machine. The stator includes a stator core having a magnetic material. The stator core includes a cylindrical yoke extending in an axial direction of the stator. The yoke includes a plurality of yoke pieces having fracture surfaces disposed relative to each other along a circumferential direction of the yoke. The fracture surfaces of mutually adjacent yoke pieces of the plurality of yoke pieces have the fracture surfaces thereof in direct contact with each other. The stator core further includes a plurality of teeth extending in a radial direction from the yoke. Each of the teeth is provided on at least one of the plurality of yoke pieces. The stator further includes a stator coil wound around the teeth. |
| US10263477B2 |
Power transmitting apparatus, power receiving apparatus, control methods therefor, and non-transitory computer-readable storage medium
A power transmitting apparatus supporting a plurality of wireless power transmission methods, acquires information about at least one wireless power transmission method supported by a power receiving apparatus from the power receiving apparatus, decides, based on the acquired information, a wireless power transmission method to be used for power transmission to the power receiving apparatus, and transmits power to the power receiving apparatus by the decided wireless power transmission method. |
| US10263475B2 |
Method and system for a complementary metal oxide semiconductor wireless power receiver
Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier. |
| US10263469B2 |
Wireless inductive power transfer
A power transmitter (101) is arranged to transfer power to a power receiver (105) via a wireless inductive power transfer signal transmitted from a transmit coil (103) to a power receiver (105). A first communication unit (305) communicates a message to the power receiver (105) on a first communication link A second communication unit (307) receives data from the power receiver (105) on a separate second communication link having a longer range. The power receiver (105) comprises a third communication unit (405) which receives the first message. A response generator (407) generates a response message to the message and a fourth communication unit (409) transmits the response message to the power transmitter (103) over the second communication link. The power transmitter (103) determines an expected response message to the message and a power controller (303) controls the power level of the power transfer signal dependent on whether a message is received on the second communication link corresponding to the expected response message. |
| US10263464B2 |
System and method for communicating bidirectionally and simultaneously
Method and system for communicating between a first piece of equipment and a second piece of equipment connected to the first piece of equipment via a single-conductor transmission line, wherein data (DATA1, DATA2) are transmitted from the first piece of equipment to the second piece of equipment by pulse width modulation of a transmission signal emitted on the transmission line, and wherein data are transmitted from the second piece of equipment to the first piece of equipment by amplitude modulation of said transmission signal. |
| US10263460B2 |
Uninterruptible power supply systems and methods for communication systems
An uninterruptible power supply adapted to be connected between an AC line and a load a battery system for storing battery power, an inverter, a transformer, and a controller. The inverter is operatively connected to the battery system. The transformer comprises a primary winding adapted to be operatively connected to the AC line, a load winding adapted to be operatively connected to the load, and an inverter winding operatively connected to the inverter. The controller controls the inverter to operate in a first mode in which the inverter supplies power to the battery system, a second mode in which the inverter supplies power to the load winding using battery power stored in the battery system, and, based on a cost value indicative of reduction of life of the battery system, a third mode in which the inverter supplies power to the primary winding using battery power stored in the battery system. |
| US10263459B2 |
Power supply system
A power supply system includes a plurality of uninterruptible power supplies provided for a load in parallel. The uninterruptible power supplies each include a power supply unit configured to supply the load with power and being larger in capacitance than the load, and a switch provided between the power supply unit and the load. The power supply system further includes a control unit selecting a first uninterruptible power supply of the plurality of uninterruptible power supplies, and setting the switch of the first uninterruptible power supply to the on state. |
| US10263455B2 |
Automated programmable battery balancing system and method of use
The present disclosure provides a programmable controller for monitoring battery performance and usage at a remote pump jack location. The disclosure provides an energy efficient controller and display system which allows the operator to quickly and accurately test batteries in an installation. It uses programmable logic to switch between system modes and decide which battery supplies power to the output. Further it will sense any high voltages at and disable the input from the faulty source. Further, the programmable logic is designed such that the mode selection process is automatic when the system is in operation. The purpose is to elongate battery and connected equipment life by preventing battery failure. The present disclosure also provides an easy and economical method of communicating potential battery failure and status to an operator via cell phone communication. |
| US10263454B2 |
Charger and power delivery control chip and charging method thereof
A charger and a power delivery control chip and a charging method thereof are provided. Resistance values of equivalent resistances corresponding to a power supply bus are calculated according to a charging current and voltage sensing signals respectively provided by chips of a first connector and a second connector. A charging voltage supplied to the power supply bus is adjusted according to a target charging voltage, a current charging current, and variations of the resistance values of the equivalent resistances corresponding to the power supply bus. |
| US10263450B2 |
Power regulation in wireless charging
Techniques for power regulation in a system, method, and apparatus are described herein. An apparatus for voltage regulation in a wireless power receiver may include a power switch to selectively supply a regulated voltage to a battery at a regulated current. The apparatus may also include load modulation logic to generate load modulation signaling by toggling the power switch. |
| US10263447B2 |
Secondary battery management system
A method and system for managing a battery system. The method including receiving at least one measured characteristic of the battery over a pre-defined time horizon from the at least one sensor, receiving at least one estimated characteristic of the battery from a electrochemical-based battery model based on differential algebraic equations, determining a cost function of a Moving Horizon Estimation based on the at least one measured characteristic and the at least one estimated characteristic, updating the electrochemical-based battery model based on the cost function, estimating at least one state of the at least one battery cell by applying the electrochemical-based battery model, and regulating at least one of charging or discharging of the battery based on the estimation of the at least one state of the at least one battery cell. |
| US10263442B2 |
Apparatus and system to manage charging operation of electronic device
Embodiments herein provide an apparatus to manage a charging operation of an electronic device. The apparatus includes a first connector adapted to fit into a charging receptacle of the electronic device. A second connector is adapted to connect to the first connector. The second connector includes a switch member configured to detect a status of the second connector. The status of the second connector is in one of a data synchronization mode and an optimal charging mode. A charging member is configured to perform the charging operation based on the status of the second connector. |
| US10263436B2 |
Electrical energy storage unit and control system and applications thereof
An electrical energy storage unit and control system, and applications thereof. In an embodiment, the electrical energy storage unit includes a battery system controller and battery packs. Each battery pack has battery cells, a battery pack controller that monitors the cells, a battery pack cell balancer that adjusts the amount of energy stored in the cells, and a battery pack charger. The battery pack controller operates the battery pack cell balancer and the battery pack charger to control the state-of-charge of the cells. In an embodiment, the cells are lithium ion battery cells. |
| US10263434B2 |
Charge and discharge device, charge and discharge control method, and program
A charge and discharge device (10) includes: a battery unit (110) in which m (m is an integer of 3 or more) battery cells (112) that are connected in series are grouped into plural groups (114) including n (n is an integer equal to or larger than 2 and smaller than m) battery cells (112) that are continuously arranged and a part of the battery cells (112) that belong to a certain group is shared by a different group; a cell balance unit (120) that is provided for each group (114) and uniformizes voltages of the battery cells (112) that belong to the group (114); and a control unit (130) that stops the operation of the cell balance unit (120), when a voltage difference of the battery cells (112) that belong to an arbitrary one of the groups (114) is within a predetermined value, and when a total average voltage in all the battery cells (112) and a partial average voltage which is an average voltage of the battery cells (112) that belong to the arbitrary group (114) satisfy a specific condition, the cell balance unit (120) corresponding to the arbitrary group (114). |
| US10263433B2 |
Power supply device, power supply system, and sensor system
According to one embodiment, a power supply device includes a voltage conversion circuit configured to convert a voltage of power generated by a power generation element; a plurality of power storage elements connected in parallel with respective load circuits; a switch circuit configured to switch an electrical connection between the voltage conversion circuit and each of the plurality of power storage elements; and a control circuit configured to measure voltages of the plurality of power storage elements and to control the switch circuit based on the measured voltages. |
| US10263432B1 |
Multi-mode transmitter with an antenna array for delivering wireless power and providing Wi-Fi access
A method for wireless power transmission is provided. The method comprising emitting, by a first antenna element of a transmitter, a first signal comprising a plurality of wireless power waves establishing a pocket of energy. The method further comprising emitting, by a second antenna element of the transmitter, a second signal different from the first signal. The second signal provides Wi-Fi access. |
| US10263428B2 |
Power conversion apparatus, method for controlling power conversion apparatus, and power conversion system
In a power conversion apparatus that has adopted a DC-linkage system, the connection to a load is switched depending on the output characteristics of the power-supply device, to thereby flexibly operate power supply from each power source. The disclosed power conversion apparatus includes: a plurality of connection terminals for connecting the DC power-supply devices; a plurality of voltage transducers connected in series to the plurality of connection terminals; a plurality of DC power output lines electrically independent from one another; a switch for selectively connecting the plurality of voltage transducers and the plurality of DC power output lines with each other; and a controller for controlling the switch, according to the operating state of at least either the plurality of DC power-supply devices or loads connected to the plurality of DC power output lines. |
| US10263421B2 |
Load allocation for multi-battery devices
This document describes techniques and apparatuses of load allocation for multi-battery devices. In some embodiments, these techniques and apparatuses determine an amount of load power that a multi-battery device consumes to operate. Respective efficiencies at which the device's multiple batteries are capable of providing power are also determined. A respective portion of load power is then drawn from each of the batteries based on their respective efficiencies. |
| US10263418B2 |
Method to protect sensitive devices from electrostatic discharge damage
ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain. |
| US10263414B2 |
Adaptive in-rush current control for minimizing MOSFET peak temperature upon voltage step
In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2ICL=2IL during the bypass capacitor 12 charging time, where ICL is the capacitive current and IL is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage. |
| US10263413B2 |
Charging station
A single-phase or multi-phase feed line is connected to a charging connection of the charging station, via which feed line the charge current flows to the charging connection of the charging station regardless of the load capacity identifier of the charge cable. An overload protection device is connected to and monitors the feed line. The overload protection device is an automatically switching overload protection device in which at least one identifier-specific trigger criterion is stored for each of at least two load capacity identifiers of the charging cable. The overload protection device is capable of automatically selecting the identifier-specific trigger criterion assigned to the load capacity identifier depending on the load capacity identifier of the charging cable, and of shutting off a switching device of the overload protection device arranged in the feed line depending on the selected trigger criterion. |
| US10263412B2 |
System and method for desaturation detection
In accordance with an embodiment, a method of operating a control circuit includes generating a threshold value based on a drive signal of an external power transistor, and determining an overpower state of the external power transistor based on a voltage at a drain or a collector of the external power transistor and the threshold value. |
| US10263410B2 |
Heat-recoverable component, electrical wire bundle, and insulated electrical wire-covering method
A heat-recoverable component includes a tube-shaped or cap-shaped base material layer having heat shrinkability, and an adhesive layer formed on an inner circumferential surface of the base material layer. The adhesive layer includes a low-viscosity adhesive portion and a high-viscosity adhesive portion disposed between the low-viscosity adhesive portion and an opening of the base material layer. The low-viscosity adhesive portion has a shear viscosity of 10 Pa·s or less at a shear rate of 1 s−1 at a heat shrinkage temperature of the base material layer. The high-viscosity adhesive portion has a shear viscosity of 100 Pa·s or more at a shear rate of 1 s−1 at the heat shrinkage temperature of the base material layer. At the heat shrinkage temperature, a ratio of the shear viscosity of the high-viscosity adhesive portion to the shear viscosity of the low-viscosity adhesive portion is 15,000 or less. |
| US10263408B2 |
Movement-tolerant wiring arrangement for a stand device
A movement-tolerant wiring arrangement for, among other things, a stand device configured for arrangement in an operating room incorporates a mounting apparatus for movement-tolerant mounting of at least one line, for example a cable, about an axis of rotation between two connection components that are displaceable, such as being twistable, relative to one another; and a fastening apparatus for arranging the at least one line relative to one of the connection components, for example at a socket of the stand device; wherein the mounting apparatus is fixable to the fastening apparatus and configured for movement-tolerant, such as, rotation-tolerant guidance of the at least one line about the axis of rotation and/or in the direction at least approximately parallel to the axis of rotation. Furthermore, a rotary joint, a socket or a stand device, respectively, can incorporate such a wiring arrangement, and can use of such a wiring arrangement at a stand device, for example, in the operating room. |
| US10263403B2 |
Adjustable mud ring assembly
A mud ring assembly includes a base member, a movable member, and at least one actuator. The base member is configured to be coupled to a junction box and includes a flange, an opening extending through the flange, and at least one threaded hole extending through the flange. Each threaded hole is spaced apart from the opening. The movable member is positioned in the opening and is configured to support an electrical device. The movable member includes a first edge and a second edge. The first edge is positioned adjacent the first side of the flange and the second edge is positioned adjacent the second side of the flange. The movable member further includes at least one slot positioned proximate the first edge. Each slot is aligned with one threaded hole. The actuator includes a threaded portion, a head, and a bearing flange. Each actuator is secured in one slot by the head and the bearing flange. Each actuator is rotatable relative to the slot. The threaded portion engages one threaded hole such that rotation of the actuator changes the depth of insertion of the movable member within the opening of the base member. |
| US10263395B2 |
Airport runway approach lighting apparatus
An airport runway approach lighting apparatus is disclosed. According to one embodiment, the airport runway approach light includes a visible light source configured to emit a visible light beam and an infrared light source configured to emit an infrared beam. A first lens is attached to the visible light source to change the visible light beam emitted from the visible light source to a desired visible light beam pattern. The infrared light source includes a plurality of semiconductor laser diodes distributed on a surface of a laser diode chip in an array. |
| US10263394B2 |
Widely tunable swept source
A high-speed, single-mode, high power, reliable and manufacturable wavelength-tunable light source operative to emit wavelength tunable radiation over a wavelength range contained in a wavelength span between about 950 nm and about 1150 nm, including a vertical cavity laser (VCL), the VCL having a gain region with at least one compressively strained quantum well containing Indium, Gallium, and Arsenic. |
| US10263392B2 |
Optical waveguide, and optical component and variable wavelength laser which use the same
Provided are: an optical waveguide that relatively easily expands a spot size and that can suppress an increase in optical coupling loss with another optical waveguide element; and an optical component and variable-wavelength laser that use the optical waveguide. The optical waveguide is provided with: a cladding member; and a core layer that is disposed within the cladding member and that is formed as an elongated body having a rectangular cross-sectional shape from a material having a higher refractive index than the material configuring the cladding member. Here, the cross-sectional shape of the core layer is characterized in having a rectangular shape in which the length in the lateral direction is at least 10 times the length in the vertical direction. |
| US10263388B2 |
LD module cooling device and laser apparatus
An LD module cooling device includes, in a cooling plate, common flow paths that supply/drain a cooling medium in parallel to/from a plurality of cooling portion flow paths that correspond to a plurality of LD modules, in which the cooling portion flow path is a thin layer flow path having a flow path height and a flow path width that are constant in at least a majority of a flow path length, a rectangular shape of the cooling portion flow path defined by the dimensions flow path length×flow path width overlaps with at least the majority of a main contact surface between the cooling plate and the LD modules as viewed from a front surface of the cooling plate, the flow path height of the cooling portion flow path satisfies at least either one of a condition that flow path height is 1/20 or less of the flow path length and the flow path width, and a condition that the flow path height is 0.5 mm or less, and pressure loss of a cooling medium in the cooling portion flow path is greater than pressure loss of a cooling medium in the common flow paths. |
| US10263387B2 |
Light emitting device
A light-emitting device includes: a base having a depressed portion upwardly opening, the depressed portion having a bottom surface, surrounding surfaces and at least one placement surface disposed at a position higher than the bottom surface; at least one semiconductor laser element mounted on or above the bottom surface; and a wavelength conversion member enclosed in the depressed portion to convert a wavelength of light from the at least one semiconductor laser element, the wavelength conversion member having a lower surface disposed on the at least one placement surface and a circumferential edge partly surrounded by the surrounding surfaces. |
| US10263386B1 |
Four-wave mixing reduction due to raman pumps in optical communication systems
A Raman pump system for a Raman amplifier includes a plurality of primary Raman pumps each at a corresponding wavelength; and at least one pair of redundant Raman pumps including a primary redundant Raman pump at a primary wavelength and a secondary redundant Raman pump at a secondary wavelength, wherein only one of the primary redundant Raman pump and the secondary redundant Raman pump is employed based on a zero dispersion wavelength location of a fiber over which the Raman pump system operates. The secondary wavelength can be separated from the primary wavelength by at least 2 nm or 3 nm and no more than 10 nm. The Raman pump system can provide amplification across both the C Band and the L Band. |
| US10263384B2 |
Laser system having a dual pulse-length regime
A single loop hardware-based system for producing laser pulses in a microsecond scale operational mode includes a GUI to enable a user to select the operational mode of the system; a laser source for producing one or more laser beam pulses, the laser source being a diode laser pump source module; a DSP which enables and disables a hardware-based FPGA. The FPGA controls the diode pump source module. When a user selects one or more microsecond scale laser sub-pulses on the GUI, the DSP transmits to the FPGA the sub-pulse energy level and the sub-pulse on-time selected by the user on the GUI. A photodetector operatively connected to the hardware-based system measures the power of the laser pulse beam that was transmitted to the photodetector and, in a feedback mode, transmits a feedback signal of that power measurement to the FPGA. The FPGA compares the power of the laser beam measured by the photodetector to the power of the laser beam selected by the user on the GUI. If the power level read by the FPGA is higher than the selected power level, the FGPA decreases the power level to the pumping source module for any subsequent laser pulses; and if the power level read by the FPGA is less than the selected power level, the FGPA increases the power level to the pumping source module for subsequent laser pulses. |
| US10263382B1 |
Device, system and method with burst mode laser source system forming laser-induced radio frequency (LIRF) energy
A device comprising a master clock configured to produce a pulse sequence having a wideband light signal of approximately 800 nanometers or red visible wavelength of a predetermined amplitude. The device comprises X laser amplifiers along a common optical path each amplifier being triggered by a burst of X pulses with high-peak power and high-average power. The X laser amplifiers receive the pulse sequence of the master clock and sequentially amplifying the pulse sequence wherein a last laser amplifier of the X laser amplifiers produces an amplified pulse sequence. A compressor is configured to compress the amplified pulse sequence to produce a laser signal having a sequence of directed energy (DE) pulses each DE pulse having a pulse width in a femtosecond range to induce when striking a solid surface of a target object transient electric fields in a microwave frequency range. A system and method are also provided. |
| US10263380B2 |
Crosstalk reduction in electrical interconnects
Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk. |
| US10263379B2 |
Large deflection canted coil springs, connectors, and related methods
A connector assembly having a housing and pin and a spring contact located therebetween to take up a set gap between the pin and the housing. The spring contact can be a canted coil spring and the spring contact can be made to have a large range of deflection to take up the gap with a large range of variation, such as when the pin diameter varies for a given groove bore diameter or when the groove bore diameter varies for a given pin diameter. |
| US10263378B2 |
Method for manufacturing terminal member, method for connecting terminal member and conductive member, terminal member, and wiring member
A method is provided for manufacturing a terminal member that is electrical conductive with a conductive member. The terminal member is formed by working a workpiece having a plate shape with a first surface and a second surface extending from one end toward the other end, by cutting out a recessed portion at the one end from the first surface to the second surface. In this method, the recessed portion is supported by being abutted against a supporting member, and a portion spaced from the recessed portion toward the other end side is fixed, and both side portions along the one end from the recessed portion are bent while being pressed from the first surface toward the second surface side, thereby forming, as a pair of conductive surfaces for conduction with the conductive member, second surface portions facing each other with the supporting member interposed therebetween. |
| US10263375B1 |
Busbar connector
An apparatus includes first and second struts, each of which defines a channel and has an open side. The struts together define a juncture at which one of the struts crosses the other. First and second electrical contacts engage busbars in the channels. Wires interconnect the first electrical contacts with the second electrical contacts. A housing contains the wires. The housing has a first elongated portion reaching along the open side of the first strut in a direction from the first electrical contacts toward the juncture, a second elongated portion reaching along the open side of the second strut in a direction from the juncture toward the second electrical contacts, and a corner at which the first and second elongated portions meet in vertical alignment with the juncture. |
| US10263374B2 |
Modular socket box
A modular electronic apparatus includes an electric box, an insert, and optionally one or more electric modules. The insert is configured to be inserted at least partially into an internal space of the electric box and connect to electric wires of a building. The insert is further configured to receive the electric modules such that they can be powered from the electric wires without directly connecting to them. The electric modules can engage with the insert and be easily replaceable without the need to reconnect the electric wires. Each of the electric modules can be one of the following: a programmable electric socket (“smart” socket), traditional electric socket, programmable electric switch (“smart” switch), traditional electric switch, dimmer, touch screen panel, speaker, personal computer, television device, lighting device, audio player, multimedia device, network hub, a router, and the like. |
| US10263373B2 |
Portable tower with electrical outlets
A portable tower with electrical capability includes a housing with base, central, and upper housing portions, and with electrical power and/or data outlets including at least one outlet at either or both of the upper and lower housing portions. The central housing portion projects upwardly from the base housing portion and supports the upper housing portion at an elevated position spaced above the base housing portion. The electrical power and/or data outlets are in electrical communication with a power or data source, such as a remote source or an onboard source as in a rechargeable battery or capacitor. Where an onboard source is provided, the portable tower is positionable in substantially any desired location and is capable of providing electrical power to other devices when there is sufficient energy stored in the onboard source. |
| US10263366B2 |
Lever fitting-type connector
A lever fitting-type connector includes a first housing, a lever that has a pair of arm sections each having a cam groove, and a second housing having a pair of cam pins. Each of the cam grooves includes an inlet section, a curved section, and a guide rail section provided on an inner peripheral face of the cam groove. The inlet section has a running-on preventing portion which is formed so that the cam pin enters the inlet section without allowing the guide rail section to run on the cam pin. |
| US10263364B1 |
Pull-type tripping device for electrical connector
A pull-type tripping device for an electrical connector has a housing unit and a connector body unit. The connector body unit is disposed inside the housing unit, the connector body unit has a board body and a frame body vertically coupled to each other, a plurality of contact terminals are formed inside the frame body, and each upper portion of two sides of the frame body is formed a hook opening thereon. The pull-type tripping device includes a snap hook unit and a pull belt. The snap hook unit includes a fix arm, a flexible arm, and two snap hook arms. Each of the snap hook arms is disposed inside the frame body, and each of the two snap hook arms is removably buckled at the hook opening. |
| US10263363B2 |
Connector
In a connector (4) including: a first connector housing (5) including a hood portion (52) having a substantially cylinder shape to be fitted to an outer circumference of a cylindrical portion (82) of a second connector housing (8), and a lock arm (53) formed integrally with a terminal storing portion (51) such that a free end side of the lock arm (53) is deflected and deformed in a direction perpendicular to a surface of the cylindrical portion (82); and the second connector housing (8) including the cylindrical portion (82), and a lock protrusion (83) which is provided to protrude from an outer surface of the cylindrical portion (82) and which engages the lock arm (53) when a fitting length between the cylindrical portion (82) and the hood portion (52) reaches a predetermined value, the first connector housing (5) is formed of a hydrolysis-resistant material. |
| US10263360B2 |
Waterproof connector
A waterproof connector has a cable in which metal terminals are connected to the tip end, a housing that houses the metal terminals and a part of the cable, a packing in which a cable through hole that is passed to the front and rear sides is disposed, which is incorporated in the housing in a state where the packing is passed over the cable, and which ensures a watertightness between the cable and the housing, and a stopper in which a cable through hole that is passed to the front and rear sides is disposed, which is incorporated in the housing on a side of the packing opposite to the side of the metal terminals, in a state where the stopper is passed over the cable, and which holds the packing to the housing in a slipping-off preventing state. |
| US10263359B2 |
Power conversion apparatus
Provided is a power conversion apparatus that can enhance the strength of the vicinity of an opening through which a connector is exposed, and can prevent water from entering a casing through the opening or reduce such water intrusion. The power conversion apparatus includes a circuit board, a connector mounted on the circuit board, and a lid having an opening to allow the connector to be exposed therethrough and placed over the circuit board and the connector. The lid includes a bead that protrudes from a top plate to enclose an exposed portion of the connector. |
| US10263356B2 |
Secondary lock and receptacle
The present disclosure discloses a secondary lock and a receptacle. The secondary lock may be mounted to a receptacle housing. The secondary lock has a lock body, a locking portion and a terminal retaining portion. The lock body has a longitudinal insertion direction. The locking portion is protrudingly arranged on the lock body to be configured for being longitudinally block-fittable with the receptacle housing. The terminal retaining portion is arranged on the lock body to be configured for being block-fittable with a connecting terminal along an axial direction of the connecting terminal. The secondary lock according to the present disclosure may be pre-assembled on the receptacle housing to be integrally retained and conveniently transported. |
| US10263353B2 |
Precious-metal-alloy contacts
Contacts that may be highly corrosion resistant, may be readily manufactured, and may conserve precious materials. One example may provide contacts having a layer of a precious-metal alloy to improve corrosion resistance. The precious-metal-alloy layer may be plated with a hard, durable, wear and corrosion resistant plating stack for further corrosion resistance and wear improvement. The resources consumed by a contact may be reduced by forming a bulk or substrate region of the contact using a more readily available material, such as copper or a material that is primarily copper based. |
| US10263350B2 |
Electrical connector
An electrical connector comprises an insulative body and at least two fitting nails. The insulative body is provided with at least two receiving grooves. An upper edge contour of each fitting nail comprises at least one stepped contour which cooperates with an inner upper wall surface of the receiving groove so as to limit a position of the fitting nail moving toward the upper and a position of the fitting nail moving toward the front, so as to allow the fitting nail to be firmly fixed in the receiving groove of the insulative body. |
| US10263348B2 |
Grounding apparatus and methods for grounding
A method for electrically grounding structures or equipment includes providing an open-topped enclosure having peripheral sidewalls defining an interior cavity, positioning the enclosure over an in situ soil mass, placing a selected soil material in the cavity, and installing a grounding device in the soil contained in the cavity, so as to establish electrically-conductive continuity between the grounding device and the soil material in the cavity, and between the soil material in the cavity and the underlying in situ soil mass. Electrical cables can then be run between the grounding device and a structure or equipment to effect electrical grounding thereof. The effectiveness of the resultant electrical grounding may be enhanced by moistening the soil material in the enclosure and/or the in situ soil mass. The enclosure may have an open bottom, or may have a floor element with apertures allowing passage of moisture. |
| US10263345B2 |
Multiport multiband vehicular antenna assemblies including multiple radiators
Exemplary embodiments are disclosed of multiport multiband vehicular antenna assemblies. In exemplary embodiments, a multiport multiband antenna assembly may include multiple ports (e.g., three, four, or five ports, etc.) with different combinations of antennas or radiators operable over various frequencies, such as one or more cellular frequencies (e.g., Long Term Evolution (LTE), etc.), internet frequencies (e.g., Wi-Fi, Wi-Fi ISM, etc.), satellite navigation frequencies (e.g., Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), etc.), and/or other frequencies. For example, a multiport multiband antenna assembly may include radiators or antennas operable with LTE, WI-FI, GPS (and/or with other cellular, internet, and/or satellite navigation frequencies) where the radiators or antennas are located and/or part of a single antenna system, e.g., positioned on and/or supported by the same or common base assembly and within the same interior enclosure cooperatively defined by the base assembly and radome of a single roof-mount antenna system, etc. |
| US10263344B2 |
High-frequency antenna module and array antenna device
A high-frequency antenna module includes: a substrate; an input port to which an RF signal is inputted; a distribution circuit configured to distribute the RF signal inputted to the input port; a plurality of amplification units which each have a plurality of cascade-connected amplifiers configured to amplify the RF signal distributed by the distribution circuit, and which are arranged on a side of the substrate provided with the distribution circuit to be rotationally symmetric about the distribution circuit; a plurality of antennas provided on a side of the substrate opposite to the side provided with the amplification units, and each configured to emit the RF signal amplified by the amplification unit corresponding thereto to a space; and a plurality of RF signal supplying portions each configured to supply the RF signal amplified by the amplification unit to the antenna corresponding thereto. |
| US10263343B2 |
Reflector antenna arrangement
The present disclosure relates to a reflector antenna arrangement comprising at least a first reflective metal surface and a signal feeding arrangement transition that is adapted to receive a signal feeding arrangement that in turn is adapted to transmit and/or receive electromagnetic radiation via the first reflective metal surface. The reflector antenna arrangement further comprises a common dielectric body comprising at least one dielectric material, to which common dielectric body the first reflective metal surface is attached in a fixed relation to the signal feeding arrangement transition with a certain distance between them such that said transmitted and/or received electromagnetic radiation at least partly is arranged to propagate through at least a part of the common dielectric body. |
| US10263342B2 |
Reflectarray antenna system
One embodiment describes a reflectarray antenna system. The system includes an antenna feed configured to at least one of transmit and receive a wireless signal occupying a frequency band. The system also includes a reflector comprising a reflectarray. The reflectarray includes a plurality of reflectarray elements, where each of the reflectarray elements includes a dipole element. The dipole element of at least a portion of the plurality of reflectarray elements comprises a crossed-dipole portion and a looped-dipole portion. The plurality of reflectarray elements can be configured to selectively phase-delay the wireless signal to provide the wireless signal as a coherent beam. |
| US10263341B2 |
Low profile antenna system
An antenna system is described where uniform radiation pattern coverage is provided in the plane of a low profile antenna element. A polarization that is orthogonal to the plane of the low profile antenna element can be achieved for the radiated field. Tuning mechanisms are described to provide a method for dynamically altering the radiation pattern and for adjusting the frequency response of the antenna during the manufacturing process as well as at field installation. The antenna system is capable of being implemented in applications such as local area network (LAN), cellular communication network, and machine to machine (M2M). |
| US10263340B2 |
Wireless charging and communications systems with dual-frequency patch antennas
An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more dual-frequency dual-polarization patch antennas. Each patch antenna may have a patch antenna resonating element that lies in a plane and a ground that lies in a different parallel plane. The patch antenna resonating element may have a first feed located along a first central axis and a second feed located along a second central axis that is perpendicular to the first central axis. The patch antenna resonating element may be rectangular, may be oval, or may have other shapes. A shorting pin may be located at an intersecting point between the first and second axes. The patch antennas may be used in beam steering arrays. The patch antennas may be used for wireless power transfer at microwave frequencies or other frequencies and may be used to support millimeter wave communications. |
| US10263339B2 |
X-ray detector and X-ray imaging apparatus having the same
The X-ray detector includes a side frame; a cover coupled to an outside of the side frame; a first antenna radiator supplied with a power by being coupled to the side frame; and a second antenna radiator provided in the cover while being spaced apart from the first antenna radiator, and configured to resonate with the first antenna radiator. |
| US10263337B1 |
Method for multiple-input multiple-output communication using single port radiation pattern reconfigurable antennas
An aspect of the present invention is drawn to a communication system that includes an electrically steerable parasitic array transmitter antenna, a transmitter driver, an electrically steerable parasitic array receiver antenna, and a receiver driver. The transmitter driver is arranged such that it is operable to enable the electrically steerable parasitic array transmitter antenna to transmit a beam having a first directional vector at a first time, a second directional vector at a second time, and an nth directional vector at an nth time. The receiver driver is arranged such that it is operable to enable the electrically steerable parasitic array receiver antenna to receive a beam having a third directional vector at a third time, a fourth directional vector at a fourth time, and an mth directional vector at an mth time. |
| US10263336B1 |
Multi-band multi-antenna array
A multi-band multi-antenna array includes a ground conductor plane and a dual antenna array. The ground conductor plane includes a first edge and separates a first side space and a second side space. The dual antenna array has a maximum array length extending along the first edge and includes a first antenna and a second antenna. The first antenna includes a first resonant loop and a first radiating conductor line exciting the first antenna generating a first resonant mode and a second resonant mode, respectively, wherein frequencies of the first resonant mode are lower than frequencies of the second resonant mode. The second antenna includes a second resonant loop and a second radiating conductor line exciting the first antenna generating a third resonant mode and a fourth resonant mode, respectively, wherein frequencies of the third resonant mode are lower than frequencies of the fourth resonant mode. |
| US10263328B2 |
Device for wireless access
The present disclosure provides a device for wireless access, which pertains to the technical field of wireless network. The device for wireless access includes a device body; a radio frequency circuit disposed inside the device body; and a plurality of antenna units disposed on an external surface of the device body, each of the plurality of antenna units being connected to the radio frequency circuit; wherein each of the plurality of antenna units comprises an antenna oscillator, and the antenna oscillators on each two adjacent antenna units of the plurality of antenna units are misaligned with each other. By disposing antenna oscillators of adjacent antenna units on the misaligned regions of the respective antenna unit, the interference of co-frequency signals between adjacent antenna units may be reduced, and the isolation of adjacent antenna units may be enhanced. Thus, adjacent antenna units may be disposed at a reduced distance therebetween. Therefore, it is achievable to have a plurality of co-frequency antennas arranged side by side on a small-sized device for wireless access, thereby reducing the production cost. |
| US10263326B2 |
Repeater with multimode antenna
The disclosure concerns an antenna subsystem that can be used in various repeater systems to optimize gain of the repeater by increasing isolation between donor and server antennas, wherein at least one of the donor and server antennas is an active multi-mode antenna. |
| US10263320B2 |
Methods of making stretchable and flexible electronics
A method of making a stretchable and flexible electronic device includes the steps of creating a computer aided design using a computer modeling software system of the electronic device; digitizing the computer aided design and importing the design into a computer memory of a sewing machine capable of performing embroidery; using the sewing machine and a conductive thread to embroider the design on to a fabric substrate to create the electronic device, whereby the electronic device comprises at least a portion of conductive threads; removing the fabric substrate from the electronic device using heat; coating the electronic device with a polymer. |
| US10263315B2 |
Directional coupler and communication module
A directional coupler includes a first signal transmission line disposed between a signal input terminal and a signal output terminal, a coupled line disposed between a coupled output terminal and a resistance connection terminal and electromagnetically coupled to the first signal transmission line, switching terminals connected to a switching element of an IC chip, and a second signal transmission line in which a connection state with respect to the first signal transmission line is switched in accordance with a connection switching operation between the switching terminals by the switching element. The second signal transmission line is connected in parallel to the first signal transmission line in accordance with the connection switching operation between the switching terminals by the switching element when an electric signal in a first frequency band at low frequency is input to the signal input terminal. |
| US10263311B2 |
Transmission line and signal processing device
A transmission line according to an embodiment, includes a first conductor layer, a second conductor layer spaced apart from the first conductor layer, a first conductor line including a first region facing the first conductor layer and a second region facing the second conductor layer, the first conductor line being spaced apart from the first conductor layer and the second conductor layer, the first conductor line extending in a first direction, and a second conductor line spaced apart from the first conductor layer, the second conductor layer, and the first conductor line, the second conductor line extending in the first direction, the second conductor line being shorter than the first conductor line in the first direction in length. |
| US10263309B1 |
Devices and methods for a dielectric rotary joint
A device is provided that includes a first waveguide configured to guide propagation of RF waves inside the first waveguide. A first side of the first waveguide is configured to emit an evanescent field associated with the propagation of the RF waves inside the first waveguide. The device also includes a second waveguide having a second side positioned within a predetermined distance to the first side of the first waveguide. The second waveguide is configured to guide propagation, inside the second waveguide, of induced RF waves associated with the evanescent field from the first waveguide. The device also includes a first probe coupled to the first waveguide and configured to emit the RF waves for propagation inside the first waveguide. The device also includes a second probe coupled to the second waveguide and configured to receive induced RF waves propagating inside the second waveguide. |
| US10263302B1 |
Baffle structure for heat dissipation
A baffle structure for heat dissipation, mounted on an electric vehicle on top of which a battery pack is mounted, includes a base, a plurality of baffle fins and a mask. The base is connected to the battery pack. The baffle fins are disposed on the base. The baffle fins each have a first end and a second end. The mask covers the baffle fins. The mask includes at least an air inlet and at least an air outlet which correspond in position to the first and second ends, respectively. The baffle structure guides hot air out, takes up no space inside the electric vehicle, dispenses with a need to be connected to any external cooling system, and saves electrical power supplied by the battery pack. |
| US10263296B2 |
Semiconductor device and manufacturing method of semiconductor device
A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area. |
| US10263294B2 |
Lithium ion secondary battery
Provided is a lithium ion secondary battery which has a low internal resistance in a low-SOC region and a sufficiently large amount of gas generated during overcharge. The lithium ion secondary battery disclosed herein includes an electrode body having a positive electrode and a negative electrode, and a nonaqueous electrolytic solution. The lithium ion secondary battery further includes a pressure-type safety mechanism. The nonaqueous electrolytic solution includes a gas generating agent. The positive electrode has a positive electrode active material layer including a positive electrode active material. The positive electrode active material includes a lithium transition metal composite oxide represented by LiNiaCobMncO2 wherein a, b and c satisfy the following conditions: 0.35≤a≤0.45, 0.15≤b≤0.25, 0.35≤c≤0.45, and a+b+c=1, and a lithium transition metal composite oxide represented by LiNixCoyMnzO2 wherein x, y and z satisfy the following conditions: 0.35≤x≤0.45, 0.45≤y≤0.55, 0.05≤z≤0.15, and x+y+z=1, and the mass ratio of the oxides is 60:40 to 85:15. |
| US10263290B2 |
Nonaqueous electrolyte secondary battery
It is an object of the present invention to provide a nonaqueous electrolyte secondary battery in which swelling due to charge-discharge cycling is inhibited. The nonaqueous electrolyte secondary battery including a flat electrode assembly in which a first electrode plate and a second electrode plate having a different polarity from the first electrode plate are wound with a separator provided therebetween. |
| US10263287B2 |
Non-aqueous electrolyte solution and electricity storage device in which same is used
Provided are a nonaqueous electrolytic solution having an electrolyte salt dissolved in a nonaqueous solvent, the electrolyte salt including at least one first lithium salt selected from LiPF6, LiBF4, LiN(SO2F)2, LiN(SO2CF3)2, and LiN(SO2C2F5)2, and at least one second lithium salt selected from a lithium salt having an oxalate structure, a lithium salt having a phosphate structure, and a lithium salt having an S═O group, with a sum total of the first lithium salt and the second lithium salt being four or more, and an energy storage device using the same.This nonaqueous electrolytic solution is not only able to improve electrochemical characteristics at a high temperature and much more improve a discharge capacity retention rate and low-temperature output characteristics after a high-temperature storage test but also able to improve low-temperature input characteristics even for high-density electrodes. |
| US10263285B2 |
Nonaqueous electrolyte, capacitor device using same, and carboxylic acid ester compound used in same
The present invention provides a nonaqueous electrolytic solution capable of improving electrochemical characteristics in the case of using an energy storage device at a high temperature and at a high voltage and further capable of inhibiting the gas generation while maintaining a capacity retention rate after storage at a high temperature and at a high voltage and also provides an energy storage device using the same. Disclosed is a nonaqueous electrolytic solution having an electrolyte salt dissolved in a nonaqueous solvent, the nonaqueous electrolytic solution containing a carboxylic acid ester compound represented by the following general formula (I). In the formula, each of R1 and R2 independently represents a hydrogen atom, a —C(═O)—OR4 group, or the like, and R1 and R2 may be bonded to each other to form a ring structure. R3 represents a hydrogen atom or the like, and n represents an integer of 1 to 3. When n is 1, then L and R4 represent an alkyl group having 1 to 6 carbon atoms or the like; and when n is 2 or 3, then L represents an n-valent connecting group, X represents a —C(═O)— group, an —S(═O)— group, an —S(═O)2— group, an —S(═O)2—R5—S(═O)2— group or a CR6R7 group, R5 represents an alkylene group having 1 to 4 carbon atoms, and each of R6 and R7 represents a hydrogen atom or an alkyl group having 1 to 6 carbon atoms. |
| US10263284B2 |
Non-aqueous liquid electrolyte and lithium secondary battery comprising the same
The present disclosure provides a lithium secondary battery comprising a non-aqueous liquid electrolyte comprising lithium bis(fluorosulfonyl)imide (LiFSI) and a trimethylsilyl phosphate (TMSPa) additive, a positive electrode comprising a lithium-nickel-manganese-cobalt-based oxide as a positive electrode active material, a negative electrode and a separator.The non-aqueous liquid electrolyte for a lithium secondary battery of the present disclosure is capable of forming a solid SEI membrane in the negative electrode when initially charging a lithium secondary battery comprising the same, is capable of improving an output property of the lithium secondary battery, and is also capable of enhancing an output property and a capacity property after high temperature storage. |
| US10263283B2 |
Electrolyte formulations
An electrolyte formulation including additive compounds, additive salts, or combinations thereof to improve both low temperature and high temperature performance of lithium ion batteries as compared to conventional electrolytes. Some of these embodiments further include solvents in the electrolyte solution. |
| US10263282B2 |
Extensible provider connection systems, methods and architecture
A system is disclosed for delivering dynamically-rendered web experiences via implementing a provider interface in a provider framework where the interface defines supported behaviors for interfacing with external content in an external content repository, and where the interface defines at least one external object and specifies at least one method for implementing the supported behaviors for the object. The provider framework discovers supported behaviors upon instantiation of a provider implementation class embodied in implementation of the provider interface. A connection is engaged to the external repository with the supported behaviors using the interface to connect to and expose the external content. During web content delivery, the system accesses the provider connection and dynamically integrates external content with system-managed content in a delivered web page. |
| US10263276B2 |
Producing method of assembled battery
A producing method of an assembled battery includes: preparing plural battery cells each of which includes an electrode body having a positive electrode and a negative electrode, and a container for housing the electrode body; classifying the plural battery cells into plural thickness ranks depending on a thickness in an arrangement direction of the electrode body housed inside each battery cell; and arranging the plural battery cells in the arrangement direction, and fastening the plural battery cells such that a load is applied to the plural battery cells in the arrangement direction, the plural battery cells being selected from the plural thickness ranks in a manner as to conform a length in the arrangement direction of the battery cells is adapted to a predetermined length when the plural battery cells are arranged in the arrangement direction. |
| US10263275B2 |
All-solid rechargeable battery, method for manufacturing same, and electronic apparatus
The present invention relates to an all-solid rechargeable battery, a method for manufacturing the same, and an electronic apparatus, makes the annealing step for crystallization unnecessary in the all-solid rechargeable battery. The present invention includes a substrate, a negative electrode, a solid electrolyte, and a positive electrode, wherein LiFePO4 in an amorphous state is used as the positive electrode. |
| US10263273B2 |
In-vehicle fuel cell stack
A cell voltage control unit is provided on a lower surface of a stack body of a fuel cell stack. The cell voltage control unit is connected to cell voltage terminals for monitoring cell voltage. A protection member is provided on a second end plate where the cell voltage control unit is provided. The protection member has protrusions protruding from both sides of the protection member in a horizontal direction, and a body portion having a vertically elongated shape so as to extend to a front face of the cell voltage control unit. |
| US10263272B2 |
Gas flow path forming bodies of fuel cell, and fuel cell
A gas passage forming body for a fuel battery includes gas passages and water guide passages. A communication passage is arranged between one of the water guide passages and a gas passage that is adjacent to the water guide passage and is in communication with the adjacent gas passage and water guide passage to permit water to move therethrough. An aid portion is arranged at water drainage ends of two adjacent ones of the water guide passages and aids bonding of water drained from the water drainage ends of the two adjacent ones of the water guide passages. Thus, water drainage from the water guide passages of the gas passage forming body is improved, and water in the gas passages is reduced. As a result, the battery performance of the fuel battery is improved due to an improvement in gas diffusion. |
| US10263270B2 |
Redox flow battery system and method for operating redox flow battery system
A redox flow battery system includes a plurality of branch circuits electrically connecting a plurality of battery cell parts in parallel; a switching unit configured to switch conduction states of a closed loop in which the branch circuits are connected together; a circulation mechanism; a detection unit; a determination unit configured to determine whether or not a voltage difference between the open circuit voltages of the battery cell parts is more than a predetermined value; and a control unit configured to control a switching operation of the switching unit such that, when the determination unit determines the voltage difference to be more than the predetermined value, the closed loop is brought into a non-conducting state and, when the determination unit determines the voltage difference to be equal to or less than the predetermined value, the closed loop is brought into a conducting state. |
| US10263264B2 |
Method for high-temperature electrolysis or co-electrolysis, method for producing electricity by means of an SOFC fuel cell, and associated interconnectors, reactors and operating methods
A heat exchanger can be integrated into an interconnector that can be used in both a SOFC fuel cell and an EHT electrolyser, which allows a heat-transfer fluid different from that in the reactive and drainage gas circuits to be circulated from the inlet of the reactor, thereby allowing the best possible management of the exothermic operating modes of the SOFC cell and the exothermic or endothermic operating modes of the EHT electrolyser and the SOFC cell, especially in the absence of current for the latter. |
| US10263261B2 |
Electrically conductive ink
Provided is electrically conductive ink that shows favorable flowability and that can also suppress deformation, such as flattening, upon application of surface pressure.The electrically conductive ink is applied onto a substrate 21 of a separator 11 that constitutes a cell 13 of a fuel cell stack by way of screen printing so as to form ribs 22 on the substrate 21, wherein the electrically conductive ink has viscoelasticity, as measured by a rotary rheometer, that exhibits a loss tangent of 1 with a strain of 10 to 100%. |
| US10263257B2 |
Electrode assemblies
Provided herein is electrode assembly for a nonaqueous electrolyte secondary battery, comprising at least one anode, at least one cathode and at least one separator interposed between the at least one anode and at least one cathode, wherein the at least one anode comprises an anode current collector and an anode electrode layer, and the at least one cathode comprises a cathode current collector and a cathode electrode layer, wherein each of the cathode and anode electrode layers independently has a void volume of less than 35%, and wherein each of the at least one cathode and anode independently has a peeling strength of 0.15 N/cm or more. |
| US10263255B2 |
Lithium secondary battery
A lithium secondary battery includes a cathode electrode, an anode electrode, and a separation film installed between the cathode electrode and the anode electrode, wherein the cathode electrode includes a cathode active material containing lithium-metal oxide of which at least one of metals has a concentration gradient region between a core part and a surface part thereof, and the separation film includes a base film and a ceramic coating layer formed on at least one surface of the base film, such that it is possible to achieve a significantly improved effect in both of the lifespan property and penetration durability. |
| US10263245B2 |
Complex for anode active material, anode including the complex, lithium secondary battery including the anode, and method of preparing the complex
A complex for anode active material, the complex including: a conductive framework having a spherical skein shape; and metal particles dispersed in the conductive framework. Also an anode including the complex, a lithium secondary battery including the anode, and a method of preparing the complex. |
| US10263241B2 |
Electroless process for depositing refractory metals
The invention provides an inexpensive, scalable process for coating materials with a film of a refractory metal. As an example, the immersion process can comprise the deposition of a sacrificial zinc coating which is galvanically displaced by the ether-mediated reduction of oxophilic WCl6 to form a complex WOxCly film, and subsequently annealed to crystalline, metallic tungsten. The efficacy of this process was demonstrated on a carbon foam electrode, showing a 50% decrease in electrode resistance and significant gains in electrochemical performance. This process enables voltage efficiency gains for electrodes in batteries, redox flow batteries, and industrial processes where high conductivity and chemical stability are paramount. |
| US10263239B2 |
Method for manufacturing electrode sheet
A method for manufacturing an electrode sheet includes the steps of forming a granulated material by mixing an electrode active material, a cellulose derivative, a binder, and an aqueous solvent, and placing the granulated material in the form of a sheet on electrode current collector foil. The cellulose derivative is at least one selected from the group consisting of hydroxyethyl cellulose, hydroxypropyl cellulose, hydroxyethyl methylcellulose, and hydroxypropyl methylcellulose, and has 3.0 or more moles of substitution, which is an average number of hydroxy groups substituted per glucose unit. |
| US10263238B2 |
Battery protection circuit module package, battery pack and electronic device including same
Provided are a battery protection circuit module package capable of achieving high integration and size reduction, and a battery pack and an electronic device including the same. The battery protection circuit module package includes a lead frame including a plurality of leads space apart from each other, and capable of being coupled and electrically connected to electrode tabs of a battery cell, battery protection circuit devices mounted on the lead frame and including a positive temperature coefficient (PTC) structure, and an encapsulant for encapsulating the battery protection circuit devices to expose a part of the lead frame. |
| US10263231B2 |
Battery cover assembly
A vent cap gang includes a plurality of vent caps to be received in respective vent ports formed in a battery cover. Each of the vent caps includes a cylindrical body having first pin located at an axial center thereof and a second pin offset from the axial center. A plurality of elongate members is operably coupled to each of the vent caps by the first and second pins. An actuator is operably coupled to the elongate members and at least one of the vent caps to cause simultaneous rotational movement of the vent caps. |
| US10263226B2 |
Battery cell having asymmetric and indented structure
A battery cell configured to have a structure in which an electrode assembly, including a positive electrode, a negative electrode, and a separator interposed therebetween, is mounted in a battery case, the electrode assembly including two or more unit cells having different planar sizes, the unit cells being stacked in the height direction on the basis of a plane, at least one first unit cell selected from among the unit cells has an asymmetric structure formed on at least one side of the outer edge thereof on the basis of a middle axis crossing a main body of the first unit cell when viewed from above, and at least one second unit cell selected from among the unit cells has an indented portion indented from at least one side of the second unit cell toward the middle of the second unit cell. |
| US10263224B2 |
Power storage device and electronic device
To improve the flexibility of a power storage device, or provide a high-capacity power storage device. The power storage device includes a positive electrode, a negative electrode, an exterior body, and an electrolyte. The outer periphery of each of the positive electrode active material layer and the negative electrode active material layer is a closed curve. The exterior body includes a film and a thermocompression-bonded region. The inner periphery of the thermocompression-bonded region is a closed curve. The electrolyte, the positive electrode active material layer, and the negative electrode active material layer are in a region surrounded by the thermocompression-bonded region. |
| US10263223B2 |
Secondary battery
A secondary battery with an exterior body having a novel sealing structure, and a structure of a sealing portion that relaxes a stress of deformation are provided. The secondary battery includes a positive electrode, a negative electrode, an electrolyte solution, and an exterior body enclosing at least part of the positive electrode, at least part of the negative electrode, and the electrolyte solution. The exterior body includes a first region having a shape with a curve, a shape with a wavy line, a shape with an arc, or a shape with a plurality of inflection points, and a second region having the same shape as the first region. The first region is in contact with the second region. Alternatively, the first region has a shape without a straight line. The secondary battery may be flexible, and the exterior body in a region having flexibility may include the first region. |
| US10263222B2 |
Tubular lithium battery
The invention discloses a tubular lithium battery. The tubular lithium battery comprises at least a tubular body and a hollow channel. The body has at least one power supply unit, at least one packaging unit and at least two terminals. The power supply unit is packed via the packaging unit and is electrically connected to the terminals. The power supply unit and the packaging unit are wound as a whole. The hollow channel, which is positioned inside the body, is formed by winding the power supply unit and the packaging unit. The orientations and the positions of the terminals may be various due to locating in different positions of the power supply unit as well as winding the power supply unit and the packaging unit toward different directions, so that the electronic device exerting the tubular lithium battery disclosed in the present invention can be designed in various ways. |
| US10263220B2 |
Manufacturing method for QLED display
The manufacturing method for QLED display of the present invention uses the white QD layer to replace the organic light-emitting layer of the WOLED structure in the WOLED process, and adds the UV photoinitiator to the white QD layer. The QDs between the sub-pixels are irreversibly quenched by UV irradiation with mask to form fine QD pattern so as to eliminate the mutual influence between adjacent sub-pixels and effectively reduce the distance between two sub-pixels, increase the aperture ratio, and improve the color gamut and contrast of the display to enhance the color expression capability of the display. The manufacturing method is simple, and saves cost and process. Compared with the conventional TFT-LCD display, the QLED display of the present invention is not required to fabricate a liquid crystal cell separately, thinner and lighter, and has a longer lifetime and higher luminous efficiency than a conventional WOLED display. |
| US10263219B2 |
Radiation-emitting component with organic layer stack
A radiation-emitting component is disclosed. Embodiments of the invention relate to a radiation-emitting component with an organic layer stack which is arranged on a substrate. An outcoupling structure is arranged on a substrate face facing the organic layer stack, an additional optical layer is arranged between the substrate and the outcoupling structure, and the additional optical structure has a refractive index which is lower than the refractive index of the substrate, or the additional optical layer forms a mirror which has a selective angle and which only allows light that can be coupled out of the substrate at a substrate boundary surface facing away from the organic layer sequence to pass, the light being generated in the organic layer stack during operation. |
| US10263218B2 |
Electro-optical device with a luminance adjustment layer
An organic EL device as an the electro-optical device includes a reflective layer; an opposite electrode as a semitransparent reflective layer; and a first luminescence pixel and a second luminescence pixel as first pixels, and a third luminescence pixel as a second pixel respectively having an optical path length adjustment layer and a functional layer provided between the reflective layer and the opposite electrode; in which the optical path length adjustment layer of the first luminescence pixel includes a fourth insulation layer as a luminance adjustment layer and the optical path length adjustment layer of the third luminescence pixel does not include a third insulation layer. |
| US10263216B2 |
Rollable display apparatus
A rollable display apparatus includes a rolling drum; and a flexible display panel comprising an end bonded to the rolling drum, the flexible display panel being windable around an outer circumferential surface of the rolling drum, the flexible display panel including a flexible substrate including a first surface on which a display device is arranged; and a first protection film over the first surface of the flexible substrate, the first protection film including a first layer including an elastic polymer, and a second layer on the first layer and having a smaller surface frictional force than the first layer, and the second layer includes a plurality of first grooves each indented in a depth direction of the second layer from a surface of the second layer. |
| US10263212B2 |
OLED device with auxiliary electrode connected to cathode
Provided is an organic light emitting display device in which a plurality of pixel areas each including an emitting area and a non-emitting area is defined in a display area. The organic light emitting display device includes: an auxiliary electrode in a part of a non-emitting area of at least one pixel area; an auxiliary electrode contact portion formed as a part of the auxiliary electrode; a first electrode in the emitting areas of the plurality of pixel areas; an organic layer on the first electrode and the auxiliary electrode; and a second electrode on the organic layer. The auxiliary electrode contact portion electrically connects the auxiliary electrode and the second electrode. A distance from a center of the auxiliary electrode contact portion to a terminal end of the first electrode in the emitting area may be 3 μm or more. |
| US10263211B2 |
Organic light emitting display device and method of manufacturing the same
Disclosed is an organic light emitting display device that may include a substrate having an active area and a pad area, a passivation layer provided on the active area of the substrate, an anode electrode provided on the passivation layer, a bank layer for defining a pixel region on the anode electrode, an organic emitting layer provided on the bank layer and connected with the anode electrode, a cathode electrode provided on the organic emitting layer, and an auxiliary electrode electrically connected with the cathode electrode and provided under the passivation layer, wherein a contact hole for exposing the auxiliary electrode is provided in the passivation layer, the auxiliary electrode includes a lower auxiliary electrode and an upper auxiliary electrode, and the cathode electrode is in contact with an upper surface of the lower auxiliary electrode via the contact hole. |
| US10263210B2 |
Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes: a first pixel electrode and a second pixel electrode disposed on a substrate; a pixel-defining film disposed on the first pixel electrode and the second pixel electrode and having openings through which the first pixel electrode and the second pixel electrode are exposed; a first intermediate layer and a second intermediate layer respectively disposed on the first pixel electrode and the second pixel electrode, the first intermediate layer and the second intermediate layer respectively comprising a first emission layer and a second emission layer; a first counter electrode and a second counter electrode respectively disposed on the first intermediate layer and the second intermediate layer; a first layer and a second layer respectively disposed on the first counter electrode and the second counter electrode and comprising fluorine; and a connection layer disposed on the first layer and the second layer and electrically connected to the first counter electrode and the second counter electrode. |
| US10263206B2 |
Organic semiconductor crystalline film, method for preparing the same, organic transistor, and organic phototransistor
An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an oriented relationship with the ordered substrate. The organic semiconductor crystalline film prepared by the present invention is useful for organic transistor and organic phototransistor devices. The method of the present invention can control the high carrier mobility direction of organic semiconductor crystals to have ordered orientation in the film, enhance contacts between crystals, improve mechanical strength and micro-machining property of the film, and give a high carrier mobility. The carrier mobility of weak oriented epitaxially grown film of the present invention is 0.32 cm2/Vs, which is 5 times as large as that of a vapor phase deposited film, and is similar to that of single crystal. The present invention is adapted to glass substrates and plastic substrates. |
| US10263205B2 |
Organic solar cell and manufacturing method thereof
A solar cell includes an active layer between a first electrode and a second electrode, and a transport layer between the active layer and one of the first or second electrodes. A plurality of nanoparticles are included in at least one of the active layer or the transport layer. The nanoparticles may have the same or different shapes or sizes and may be spaced differently based on location. The nanoparticles may be made of metal or a different material and the active layer may be made from an organic photovoltaic material. |
| US10263203B2 |
Display device
A display device for preventing a curling phenomenon of an edge of a substrate and solving a problem caused by separation of the substrate is disclosed. The display device includes a flexible substrate including a first substrate region overlapping a display unit and a second substrate region except the first substrate region, and a thin film transistor and an organic light emitting diode disposed on the display unit of the first substrate region. The first substrate region is formed of transparent polyimide, and the second substrate region is formed of colored polyimide. |
| US10263200B2 |
Display module including a display area and an outer picture-frame area
A display module includes an insulating substrate and a plurality of pixels each located on the insulating substrate and including a light-emitting element layer. The insulating substrate includes a display area where the plurality of pixels are disposed, a picture-frame area outside the display area, an outer area that is in contact with an opposite side of the picture-frame area from the display area, and a plurality of terminals located on the outer area and arranged in a direction. The outer area includes a narrowed portion whose length in the direction is shorter than a length of the display area in the direction. |
| US10263199B2 |
Display device including a bending region and non-bending regions
A display device, including a substrate having a first region and second regions; transistors on the substrate in the first region and the second regions; first electrodes each connected to the transistors; an organic emission layer on the first electrodes; and second electrodes on the organic emission layer, molecular weights of organic materials of the organic emission layer in the first region and the organic emission layer in the second regions being different from each other. |
| US10263196B2 |
Organic molecules for use in optoelectronic devices
The invention relates to an organic molecule having precisely two units of formula I linked to one another via a single bond or a bridge Y where Y=a divalent group; X=at each occurrence identically or differently CN and CF3; D=chemical unit having a structure of the formula I-1: where #=attachment point of the unit of formula I-1 to the structure of formula I; A and B=independently of one another are selected from the group consisting of CRR1, CR, NR, N, there being a single or double bond between A and B and a single or double bond between B and Z; Z=a direct bond or a divalent organic bridge which is a substituted or unsubstituted C1-C9-alkylene, C2-C8-alkenylene, C2-C8-alkynylene or arylene group or a combination thereof, —CRR1, —C═CRR1, —C═NR, —NR—, —O—, —SiRR1—, —S—, —S(O)—, —S(O)2—, O-interrupted substituted or unsubstituted C1-C9-alkylene, C2-C8-alkenylene, C2-C8-alkynylene or arylene group, phenyl units or substituted phenyl units. |
| US10263195B2 |
Organic compound, light-emitting element, light-emitting device, electronic device, and lighting device
A novel substance with which an increase in life and emission efficiency of a light-emitting element can be achieved is provided. A carbazole compound having a structure represented by General Formula (G1) is provided. Note that a substituent which makes the HOMO level and the LUMO level of a compound in which a bond of the substituent is substituted with hydrogen deep and shallow, respectively is used as each of substituents in General Formula (G1) (R1, R2, Ar3, and α3). Further, a substituent which makes the band gap (Bg) and the T1 level of a compound in which a bond of the substituent is substituted with hydrogen wide and high is used as each of the substituents in General Formula (G1) (R1, R2, Ar3, and α3). |
| US10263194B2 |
Light-emitting element, light-emitting device, electronic device, and lighting device
Provided is a novel light-emitting element, a light-emitting element with a long lifetime, or a light-emitting element with high emission efficiency. The light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer containing a fluorescent substance and a host material, a first electron-transport layer containing a first electron-transport material, and a second electron-transport layer containing a second electron-transport material, which are in contact with each other and in this order. The LUMO level of each of the host material and the second electron-transport material is higher than the LUMO level of the first electron-transport material. |
| US10263192B2 |
Organic electroluminescent device using aryl amine derivative containing heterocycle
An organic electroluminescent device including: an anode, a cathode, an emitting layer formed of an organic compound and interposed between the cathode and the anode, and two or more layers provided in a hole-injecting/hole-transporting region between the anode and the emitting layer; of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is in contact with the emitting layer containing a compound represented by the formula (1); and of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is interposed between the anode and the layer which is in contact with the emitting layer containing an amine derivative represented by the formula (2). |
| US10263189B2 |
Organic electroluminescent device and manufacturing method thereof, and display apparatus
The invention provides an organic electroluminescent device and a manufacturing method thereof, and a display apparatus. The method for manufacturing the organic electroluminescent device of the invention includes using the following to form at least one function layer: preparing a solution of a material of the function layer, and forming a liquid material layer for the function layer using the solution of the material of the function layer; performing a vacuum drying on the liquid material layer for the function layer to form function layer. In the invention, a relatively dense film is formed by performing a vacuum drying on the function layer, and the residual organic solvent is effectively removed to avoid the formation of defects, so that the film becomes smooth and dense, which increases the carrier mobility in the film and is advantageous to the transport and recombination of electrons and holes. |
| US10263188B2 |
RF-transistors with self-aligned point contacts
A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode. |
| US10263183B2 |
Methods of forming an array of cross point memory cells
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture. |
| US10263179B2 |
Method of forming tunnel magnetoresistance (TMR) elements and TMR sensor element
A method includes performing an ion beam etching process on a tunnel magnetoresistance (TMR) stack to remove material portions of a first magnetic layer and a tunnel barrier layer of the TMR stack. The ion beam etching process stops at a top surface of a second magnetic layer of the TMR stack. A protective layer is deposited over the TMR stack. Another etch process is performed to remove the protective layer such that a portion of the second magnetic layer is exposed from the protective layer and a spacer is formed from a remaining portion of the protective layer. The spacer surrounds sidewalls of the first magnetic layer and the tunnel barrier layer. The portion of the second magnetic layer exposed from the protective layer is removed so that a TMR sensor element remains, where the TMR sensor element includes a bottom magnet, a top magnet, and a tunnel junction. |
| US10263178B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers. The second magnetic layer includes a first main surface on the nonmagnetic layer side and a second main surface opposite to the first main surface, and includes a first region on the first main surface side and a second region on the second main surface side, and an intermediate region between the first and second regions and containing a predetermined nonmagnetic element. A concentration of the predetermined nonmagnetic element in the intermediate region is higher than that in the first and second regions. The second magnetic layer contains a magnetic element from the first to second main surfaces. |
| US10263174B2 |
Composite material used as a strain gauge
In one general aspect, an apparatus comprises a material including a non-layered mixture of an elastomeric polymer with a plurality of voids; and a plurality of conductive fillers disposed in the elastomeric polymer. The apparatus may produce an electrical response to deformation and, thus, function as a strain gauge. The conductive fillers may include conductive nanoparticles and/or conductive stabilizers. In another general aspect, a method of measuring compression strain includes detecting, along a first axis, an electrical response generated in response to an impact to a uniform composite material that includes conductive fillers and voids disposed throughout an elastomeric polymer, and determining a deformation of the impact based on the electrical response. The impact may be along a second axis different from the first axis. |
| US10263170B1 |
Bumped resonator structure
A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface. |
| US10263167B2 |
Method of manufacturing semiconductor device
A method of manufacturing at least one semiconductor device includes: providing a substrate having a flat lower surface, and an upper surface that allows mounting of at least one semiconductor element or an upper surface having at least one semiconductor mounted thereon; providing a work table having a support plate with a flat support surface for placing the substrate, and having a plurality of support pins arranged at a support surface side and configured to move along an up-and-down direction; abutting the lower surface of the substrate upon tip portions of the plurality of support pins to press down so that the lower surface of the substrate abuts upon the support surface of the support plate; and fixing the substrate on the support plate and performing one or more operations on the substrate. |
| US10263165B2 |
Optoelectronic component with optical elements for beam shaping and beam deflection
In an embodiment the optical component includes an optoelectronic semiconductor chip including a radiation emission face, a deflection element configured to deflect electromagnetic radiation emitted by the optoelectronic semiconductor chip in a main emission direction which forms an angle deviating from 90° with the radiation emission face, wherein the deflection element is configured as a prism structure and an optical lens having an optical axis, wherein the optical axis forms an angle deviating from 90° with the radiation emission face. |
| US10263157B2 |
Light-emitting diode with transparent conductive electrodes for improvement in light extraction efficiency
A light-emitting diode device may include a conductive substrate, a metal reflection layer provided on the conductive substrate, a transparent insulating layer provided on the metal reflection layer, an n ohmic contact plug provided in a lower portion of each of through holes formed in the transparent insulating layer, an n-type gallium arsenide (GaAs) plug provided in an upper portion of the through hole, an n cladding layer provided on the transparent insulating layer, an active layer provided on the n cladding layer, a p cladding layer provided on the active layer, a p-type GaP window layer provided on the p cladding layer, a p ohmic contact pattern provided on the p-type GaP window layer, a transparent conductive metal oxide pattern provided on the p ohmic contact layer, and a p electrode pad provided on the transparent conductive metal oxide. |
| US10263155B2 |
Method for producing an optoelectronic component
A method for producing an optoelectronic component is disclosed. In an embodiment the method includes a metallization with first mask structures is deposited directionally, and then a first passivation material is deposited non-directionally onto the metallization. Further, cutouts are introduced into the semiconductor body, such that the cutouts extend right into an n-type semiconductor region, and a second passivation material is applied on side faces of the cutouts. Furthermore, an n-type contact material is applied, structured and passivated. Moreover, contact structures are arranged on the semiconductor body and electrically connected to the n-type contact material and the metallization, wherein the contact structures and the semiconductor body are covered with a potting. |
| US10263150B2 |
Semiconductor light emitting device capable of increasing luminous efficiency under a low applied current
A semiconductor light emitting device includes a substrate having a first major surface and a second major surface, a semiconductor layer that includes a first semiconductor layer of a first conductive type formed on the first major surface of the substrate, a light emitting layer formed on the first semiconductor layer and a second semiconductor layer of a second conductive type formed on the light emitting layer, and a mesa structure formed in the semiconductor layer by selectively notching the first semiconductor layer, the light emitting layer and the second semiconductor layer so as to expose the first semiconductor layer, and a ratio of a luminescent area of the light emitting Layer with respect to an area of the first major surface of the substrate being set to equal to or smaller than 0.25. |
| US10263149B2 |
Nanostructured LED array with collimating reflectors
The present invention relates to nanostructured light emitting diodes, LEDs. The nanostructure LED device according to the invention comprises an array of a plurality of individual nanostructured LEDs. Each of the nanostructured LEDs has an active region wherein light is produced. The nanostructured device further comprise a plurality of reflectors, each associated to one individual nanostructured LED (or a group of nanostructured LEDs. The individual reflectors has a concave surface facing the active region of the respective individual nanostructured LED or active regions of group of nanostructured LEDs. |
| US10263148B1 |
Light emitting diode structure
A light emitting diode structure includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is divided into a base area and a structural supporting area. The base area includes a bottom portion and a top portion. The bottom portion is wider than the top portion. The top portion protrudes from a surface of the bottom portion along a single direction. The structural supporting area protrudes from the surface of the bottom portion beside the top portion along the same single direction. A top of the structural supporting area is aligned with a top of the top portion. The first electrode is arranged on the top of the top portion. The second electrode is at least arranged on the top of the structural supporting area. The second electrode arranged on the structural supporting area is aligned with the first electrode. |
| US10263145B2 |
Ultraviolet light emitting device
A light emitting device, according to one embodiment, may comprise: a substrate; a first conductive semiconductor layer disposed on the substrate; an active layer disposed on the first conductive semiconductor layer and generating an ultraviolet light; a second conductive semiconductor layer disposed on the active layer; and a hole injection layer disposed between the active layer and the second conductive semiconductor layer and comprising a first layer comprising AlxGa1-xN (0 |
| US10263144B2 |
System and method for light-emitting devices on lattice-matched metal substrates
Light-emitting devices and methods, wherein, in some embodiments, the devices each include a first mirror having a first face, wherein the first mirror includes a metal and, in some embodiments, is a grown-epitaxial metal mirror (GEMM); and an epitaxial structure, wherein the epitaxial structure is lattice matched with and in contact with at least a first portion of the first face of the first mirror, wherein the epitaxial structure includes an active region configured to emit light at a wavelength λ, and wherein the active region is located a first non-zero distance away from the first face of the first mirror such that there is plasmonic coupling between the active region and the first mirror. |
| US10263136B1 |
Direct band gap group IV semiconductors and methods of preparing the same
A semiconductor film includes a two-dimensional (2D) material layer having a hexagonal in-plane lattice structure, and a substantially planar Group IV semiconductor layer having a direct band gap on the 2D material layer. A method of fabricating a semiconductor material includes growing a Group IV semiconductor material on a two-dimensional material having a hexagonal in-plane lattice structure. This growth process results in the Group IV semiconductor material having a direct band gap. The semiconductor films may be used in any optoelectronic device, including flexible devices. |
| US10263135B2 |
Method for producing a solar cell involving doping by ion implantation and depositing an outdiffusion barrier
The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (S2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (S3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (S4) is subsequently carried out. |
| US10263133B2 |
Photovoltaic plant
Described herein is a photovoltaic plant (1; 1′; 1″; 1′″) including a plurality of photovoltaic modules (PV) arranged in arrays (2) spaced with respect to each other, and wherein the photovoltaic modules (PV) of each array (2) have a first assigned inclination (α-1) with respect to a reference direction. Each array (2) of photovoltaic modules (PV) is associated to an array (4; 4′; 4′″) of mobile reflection devices (RF) set adjacent thereto, and at least one array (4; 4′; 4′″) of mobile reflection devices (RF) is located in a space between successive arrays (2) of photovoltaic modules. The mobile reflection devices (RF) of each array have a second assigned inclination (a2) with respect to a reference direction. The arrays (2) of photovoltaic modules (PV) and the arrays (4; 4′; 4′″) of mobile reflection devices (RF) associated to one another includes respective front surfaces (12, 14; 14′″) set facing one another, and the mobile reflection devices (RF) of each array are orientable by variation of said second inclination (a2) in order to intercept the incident solar radiation (ISR) and reflect the latter (RSR) towards the photovoltaic modules (PV) of the associated array (2). |
| US10263131B2 |
Parallel interconnection of neighboring solar cells with dual common back planes
A solar assembly or module comprising a plurality of solar cells and a support, the support comprising a conductive layer or back plane on each planar side. Each one of the plurality of solar cells is placed on the first conductive portion with the first contact electrically connected to the first conductive portion so that the solar cells are connected in parallel through the first conductive portion. A second contact of each solar cell can be connected to the second conductive portion so that the first and second conductive portions form terminals of opposite conductivity type. The modules can be interconnected to form a string or an electrical series connection of discrete modules by overlapping and bonding the first terminal of a first module with the second terminal of a second module. |
| US10263129B2 |
Multijunction photovoltaic device having SiGe(Sn) and (In)GaAsNBi cells
A multijunction tandem photovoltaic device is disclosed having a bottom subcell of silicon germanium or silicon germanium tin material and above that a subcell of gallium nitride arsenide bismide, or indium gallium nitride arsenide bismide, material. The materials are lattice matched to gallium arsenide, which preferably forms the substrate. Preferably, further lattice matched subcells of gallium arsenide, indium gallium phosphide and aluminum gallium arsenide or aluminum indium gallium phosphide are provided. |
| US10263128B2 |
Photodetector converting ultraviolet light into visible light
A photodetector includes a structure that converts ultraviolet light into visible light; and a photodetection element that detects the visible light converted by the structure, wherein the structure is provided on the photodetection element and protrudes in a predetermined shape on a side opposite to the photodetection element. |
| US10263127B2 |
Solar cell and method for manufacturing the same
A method for manufacturing a solar cell includes forming a conductive type region on one surface of a semiconductor substrate, and forming an electrode on the conductive type region, wherein the forming of the electrode includes forming a metal layer on an entire area of the conductive type region, forming a printed electrode layer having a pattern on the electrode layer, and forming an electrode layer between the conductive type region and the printed electrode layer, wherein the forming of the electrode layer includes patterning the metal layer by using the printed electrode layer as a mask. |
| US10263126B2 |
Cavitation apparatus and method of using same
Provided in one embodiment is a method of making, comprising: exposing a raw material having a first viscosity to a first pressure and a first temperature such that the raw material after the exposure has a second viscosity, wherein the raw material comprises particles comprising at least one electrically conductive material, and wherein the second viscosity is sufficiently low for the raw material to be adapted for a hydrodynamic cavitation process; and subjecting the raw material having the second viscosity to the hydrodynamic cavitation process to make a product material having a third viscosity. Apparatus employed to apply the method and the exemplary compositions made in accordance with the method are also provided. |
| US10263122B1 |
Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate. |
| US10263121B2 |
Thin film transistor and method of manufacturing thin film transistor
Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask. |
| US10263114B2 |
Semiconductor device, method for manufacturing the same, or display device including the same
A gate electrode, a first insulating film thereover, an oxide semiconductor film thereover, a source electrode and a drain electrode thereover, and a second insulating film thereover are included. The source and the drain electrodes each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film includes copper. The first and the third conductive films each include an oxide conductive film. An end portion of the first conductive film includes a region located outward from an end portion of the second conductive film. The third conductive film covers a top surface and a side surface of the second conductive film and includes a region in contact with the first conductive film. |
| US10263111B2 |
FinFET and method for manufacturing the same
A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack. |
| US10263108B2 |
Metal-insensitive epitaxy formation
The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer. |
| US10263107B2 |
Strain gated transistors and method
A strain gated transistor and associated methods are shown. In one example, a transistor channel region includes a metal dichalcogen layer that is stressed to improve electrical properties of the transistor. |
| US10263106B2 |
Power mesh-on-die trace bumping
A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace. |
| US10263098B2 |
Threshold voltage modulation through channel length adjustment
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin. |
| US10263096B1 |
FinFET device and method of forming the same
A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%. |
| US10263095B2 |
Method of forming semiconductor fin structure
A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region. |
| US10263094B2 |
Nitride semiconductor device and process of forming the same
A process of forming a HEMT that makes the contact resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050° C. and growing an AlN spacer layer with a flow rate of NH3 at most 10% smaller than a summed flow rate of NH3 and H2. The grown GaN channel layer includes a substantial density of threading dislocations and the grown AlN layer includes a substantial density of pits. |
| US10263093B2 |
Optoelectronic semiconductor device and fabrication method thereof
An optoelectronic semiconductor includes a carrier, a semiconductor main body having a first semiconductor layer, a second semiconductor layer, and a radiation emitting layer for generating electromagnetic radiation, the semiconductor main body having at least one recess extending through the radiation emitting layer; a first electrode and a second electrode; a first electrical connection layer electrically connected between the first semiconductor layer and the first electrode; a second electrical connection layer electrically connected between the second semiconductor layer and the second electrode and extending through the recess from the carrier to the second semiconductor layer; and a zener diode structure disposed between the first electrical connection layer and the second electrical connection layer so that the first electrical connection layer and the second electrical connection layer are electrically dependent, wherein at least a portion of the zener diode structure is located in a current path between the first electrode and the second electrode. |
| US10263090B2 |
Semiconductor device and manufacturing method thereof
A method for fabricating a semiconductor device is provided including an opening in a gate electrode layer to form two spaced apart gate electrode layers. An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers. A first insulating layer is formed in the opening between the two spaced apart gate electrode layers. |
| US10263089B2 |
Transistor including active layer having through holes and manufacturing method thereof
A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided. |
| US10263084B2 |
Semiconductor device having buried gate structure and method of fabricating the same
A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure. |
| US10263076B2 |
Semiconductor device having a gate electrode embedded in a trench
To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench. The second region includes a base contact region having a depth from the front surface of the semiconductor device to the second height higher than the first height and a second front surface semiconductor electrode layer of the first conductivity type from the first height to the second height. |
| US10263075B2 |
Nanosheet CMOS transistors
Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region. |
| US10263073B2 |
III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface. |
| US10263069B2 |
III-nitride based semiconductor device with low vulnerability to dispersion and backgating effects
The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure. |
| US10263066B2 |
Memory and logic device and method for manufacturing the same
The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area. |
| US10263064B2 |
Semiconductor devices and methods of forming the same
Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor device includes an inductor structure, and the inductor structure is on a substrate and includes a first metal layer, a magnetic stack, a polymer layer and a second metal layer. The first metal layer is over the substrate. The magnetic stack is over the first metal layer and has a substantially zigzag shaped sidewall. The polymer layer is over the first metal layer and encapsulates the magnetic stack. The second metal layer is over the polymer layer. |
| US10263063B2 |
Display device
One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge. |
| US10263061B2 |
Display unit and electronic apparatus
There are provided a display unit and an electronic apparatus that are capable of preventing color mixture in adjacent color pixels, and improving color reproducibility and chromaticity viewing angle. The display unit includes: a drive substrate having a plurality of pixels with a partition therebetween; and a first light shielding film provided on the partition. |
| US10263055B2 |
Pixel definition structure, organic light-emitting device, encapsulation method thereof, and display apparatus
A pixel definition structure, an organic light-emitting device and the encapsulation method thereof, and a display apparatus are provided, in the field of display technology. The pixel definition structure includes a plurality of barriers, wherein the plurality of barriers includes a first barrier and a second barrier. The height of the first barrier is smaller than that of the second barrier, and a barrier at a first edge area of the pixel definition structure is the first barrier. The present disclosure can solve the problem of the poor encapsulation effect and improve the encapsulation effect. The present disclosure is applied to an organic light-emitting device. |
| US10263050B2 |
Hybrid display
A hybrid pixel arrangement for a full-color display is provided, which includes an inorganic LED in at least one sub-pixel, and an organic emissive stack in at least one other sub-pixel. In an embodiment, a first sub-pixel is configured to emit a first color, and includes an inorganic LED, a second sub-pixel is configured to emit a second color, and includes a first organic emissive stack configured to emit an initial color different from the first color. A third sub-pixel is configured to emit a third color different from the initial color. |
| US10263049B2 |
Color filter substrate and method of manufacturing the same, organic light emitting display panel and display device
The present disclosure provides a color filter substrate, comprising a base substrate, and a color filter matrix, a black matrix and spacers formed in order on the base substrate, the color filter matrix being consisted of a plurality of red, green and blue photoresists. The red, green and blue photoresists are respectively and separately formed within corresponding pixel regions, and are overlapped with one another to form three-layer stacked structures within gap regions between adjacent pixel regions, and, the black matrix and the spacers are sequentially formed on the stacked structures within the pixel regions. The present disclosure further provides a method of manufacturing a color filter substrate, an organic light emitting display panel and a display device. With the solutions of the present disclosure, the red, green and blue photoresists are arranged to overlap with one another to form the stacked structures within the gap regions between adjacent pixel regions, so that the height of the color filter substrate can be increased, the manufacturing height of the spacers is decreased and the process implementation difficulty is reduced, thereby improving the production yield of the color filter. Moreover, the barrier layer can also greatly reduce residues of the material of the black matrix, further improving the production yield of the color filter substrate. |
| US10263048B2 |
Pixel arrangement structure
The present invention provides a pixel arrangement structure, comprising a plurality of pixel units, and each pixel unit comprising a first sub pixel, a second sub pixel, a third sub pixel and a fourth sub pixel, and the fourth sub pixel being a triangle, and the first sub pixel, the second sub pixel and the third sub pixel being respectively arranged around the fourth sub pixel, and respectively sharing three sides with the fourth sub pixel. The pixel arrangement structure of the present invention adds the white sub pixel to promote the transmission rate of the panel, and to reduce the energy consumption of the display, and meanwhile to be beneficial for implementation of the sub pixel rendering algorithm to promote the virtual resolution. |
| US10263044B2 |
Tandem organic light-emitting diode, array substrate and display device
A tandem organic light-emitting diode, an array substrate and a display device are provided. The tandem organic light-emitting diode includes an anode, a hole transport layer, a first light-emitting layer, a first charge generation layer, a second charge generation layer, a third charge generation layer, a fourth charge generation layer, a second light-emitting layer, an electron transport layer and a cathode which are sequentially laminated, wherein the first charge generation layer is an N-type bulk heterojunction, the second charge generation layer and the third charge generation layer are both PN junction type bulk heterojunctions, a proportion of the P-type organic material in the second charge generation layer is greater than that of the N-type organic material, a proportion of the P-type organic material in the third charge generation layer is less than that of the N-type organic material, and the fourth charge generation layer is a P-type bulk heterojunction. |
| US10263041B2 |
Quantum dot optical devices with enhanced gain and sensitivity and methods of making same
Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described. |
| US10263036B2 |
Strain assisted spin torque switching spin transfer torque memory
Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer. |
| US10263034B2 |
Member for solid-state image pickup device and method for manufacturing solid-state image pickup device
A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion. |
| US10263031B2 |
Feedback capacitor and method for readout of hybrid bonded image sensors
A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier. |
| US10263028B2 |
Solid-state image pickup apparatus and method of manufacturing the same
Provided are a solid-state image pickup apparatus which includes: a semiconductor substrate having a plurality of photoelectric converters; a first and a second insulating layers formed on the semiconductor substrate; an optical waveguide formed above each of the plurality of photoelectric converters and in an opening portion of the first and the second insulating layers, and has a refractive index higher than a refractive index of the first insulating layer; and a light reflecting layer formed at a boundary between the optical waveguide and the second insulating layer, and has a refractive index lower than a refractive index of the optical waveguide, where the following expression is satisfied: α<90°, where a represents an angle formed by a boundary surface between the light reflecting layer and the second insulating layer with respect to a boundary surface between the first insulating layer and the second insulating layer. |
| US10263025B2 |
Solid-state imaging sensor
The present technology relates to a solid state imaging sensor that is possible to suppress the reflection of incident light with a wide wavelength band. A reflectance adjusting layer is provided on the substrate in an incident direction of the incident light with respect to the substrate such as Si and configured to adjust reflection of the incident light on the substrate. The reflectance adjusting layer includes a first layer formed on the substrate and a second layer formed on the first layer. The first layer includes a concavo-convex structure provided on the substrate and a material which is filled into a concave portion of the concavo-convex structure and has a refractive index lower than that of the substrate, and the second layer includes a material having a refractive index lower than that of the first layer. It is possible to reduce the reflection on the substrate such as Si by using the principle of the interference of the thin film. Such a technology can be applied to solid state imaging sensors. |
| US10263018B2 |
Signal line structure, array substrate, and display device
Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire. |
| US10263015B2 |
Semiconductor device
A semiconductor device includes a first electrode, a first insulating layer on the first electrode, a second electrode on the first insulating layer, a second insulating layer on the second electrode, a first opening in the first insulating layer, the second electrode and the second insulating layer, the first opening reaching the first electrode, a first oxide semiconductor layer in the first opening, the first oxide semiconductor layer being connected with the first electrode and the second electrode, a first gate electrode facing the first oxide semiconductor layer, and a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode. |
| US10263012B2 |
Semiconductor integrated circuit device comprising MISFETs in SOI and bulk substrate regions
The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane. |
| US10263008B2 |
Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer. |
| US10263005B2 |
Method of manufacturing a semiconductor device
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode. |
| US10263003B2 |
Semiconductor device and method of manufacturing the same
Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view. |
| US10263002B2 |
Anti-fuse memory and semiconductor storage device
In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly. |
| US10262999B2 |
High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing. |
| US10262998B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure. |
| US10262993B2 |
Semiconductor devices and a method for forming a semiconductor device
A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure. The semiconductor device includes a second transistor structure including a second transistor body region of a second conductivity type located within the semiconductor substrate. At least part of the second transistor body region is located between a first source/drain region of the second transistor structure and a second source/drain region of the second transistor structure. At least part of the second source/drain region of the second transistor structure is located between a doping region comprising the second source/drain region of the first transistor structure and the second transistor body region. |
| US10262992B2 |
Three dimensional LVDMOS transistor structures
A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts. |
| US10262990B2 |
Electrostatic discharge protection device for differential signal devices
A robust electrostatic (ESD) protection device is provided. In one example, the ESD protection device is configured to accommodate three nodes. When used with a differential signal device, the first and second nodes may be coupled with the differential signal device's BP and BM signal lines, respectively, and the third node may be coupled to a voltage source. This allows for a single ESD protection device to be used to protect the signal lines of the differential signal device, thus providing significant substrate area savings as compared to the conventional means of using three dual-node ESD protection devices to accomplish substantially the same protection mechanism. Moreover, the ESD protection device may be structurally designed to handle high voltage ESD events, as required by the FlexRay standard. |
| US10262989B2 |
ESD protection for 2.5D/3D integrated circuit systems
An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices. |
| US10262984B1 |
Optical integrated circuit systems, devices, and methods of fabrication
An optical integrated circuit device includes an electrically insulating substrate, an optical connection disposed at a boundary of the optical integrated circuit, and a first electrostatic discharge (ESD) protection structure in direct contact with and electrically coupled to the first waveguide. The optical connection includes a first waveguide. The first waveguide is disposed on the electrically insulating substrate and configured to transmit an optical signal. The first ESD protection structure is both electrically non-insulating and substantially optically transparent to the optical signal. An ESD diode including an anode and a cathode is electrically coupled to the first ESD protection structure. A ground connection is electrically coupled to the anode of the ESD diode. |
| US10262983B2 |
Integrated photo detector, method of making the same
An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V. |
| US10262979B2 |
Light emitting device
A light emitting device includes: a first light emitting element configured to emit light of a first peak wavelength; a second light emitting element configured to emit light of a second peak wavelength that is different from the first peak wavelength; a first light reflecting member disposed in contact with at least one lateral surface of the first light emitting element, the first light reflecting member having an upper surface from which an upper surface of the first light emitting element is exposed; a wavelength conversion member covering the upper surface of the first light emitting element; and a second light reflecting member disposed on the upper surface of the first light reflecting member, the second light reflecting member being located between the second light emitting element and the wavelength conversion member in a plan view. |
| US10262977B2 |
Colour inorganic LED display for display devices with a high number of pixel
An image generator for use in a display device, the image generator comprising: a plurality of ILED array chips each comprising a plurality of ILED emitters and arranged in an array such that each of a plurality of pixels of the image generator comprises an ILED emitter from each of a plurality of adjacent ILED array chips. The total area of ILED emitter material may be less than 50% of the area of each pixel. The image generator may comprise secondary optics in optical communication with an output of the plurality of ILED emitters of an ILED array chip and configured to direct light from the ILED emitters towards an emission region of the associated pixel. |
| US10262976B1 |
Package including a plurality of stacked semiconductor devices, an interposer and interface connections
A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon. |
| US10262975B1 |
Package including a plurality of stacked semiconductor devices, an interposer and interface connections
A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor. |
| US10262973B1 |
Modular chip with redundant interfaces
Aspects of the disclosure provide a chip package that includes a first die and a second die. The first die has a processing circuit and a first interface circuit. The second die is disposed in a proximity to the first die and coupled to the first die. The second die includes internal functional circuits, two or more second interface circuits with an identical configuration, and a switch circuit. A specific second interface circuit is electrically connected to the first interface circuit via wires. The switch circuit is configured to select the specific second interface circuit from the two or more second interface circuits, and couple the specific second interface circuit to the internal functional circuits on the second die. |
| US10262971B2 |
Stacked image sensor package and stacked image sensor module including the same
Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween. |
| US10262970B2 |
Selective area heating for 3D chip stack
A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. |
| US10262969B2 |
Bonding device
[Problem]To provide a bonding device capable of adequately controlling a leading end of a capillary when a ball formed at a leading end of a wire is pressed and bonded to an electrode of a semiconductor chip with scrub vibration.[Solution]The bonding device is provided with a vibration driving portion (7), the vibration driving portion (7) including a plurality of piezoelectric elements (10) that are expanded and contracted along an axial direction of a bonding arm (3) respectively with one end thereof fixed to a leading end of the bonding arm (3), a plurality of capillary holding portions (15) that are in contact respectively with a circumferential face of a capillary (20) at a base end side thereof as being fixed correspondingly to the other end of the piezoelectric elements (10), and a pressing-holding portion (21) that sandwiches the capillary (20) as pressing the capillary (20) to the capillary holding portions (15) with at least one end side fixed to the bonding arm (3) and the other end side being in contact with the circumferential face of the capillary (20) at the base end side thereof on a side opposite to the capillary holding portions (15). Here, functional operation of amplitude, phase, frequency, or waveform is performed on drive voltage waveform to the respective piezoelectric elements. |
| US10262968B2 |
Wire bonding apparatus and wire bonding method
In order to easily and accurately measure an offset for wire bonding and improve precision of wire bonding, a wiring bonding apparatus includes a first imaging unit, a bonding tool, a moving mechanism, a reference member, a second imaging unit arranged on the opposite side to the bonding tool and the first imaging unit with respect to a reference surface, and a control unit. The first imaging unit detects a position of an optical axis of the first image capture unit with respect to a position of the reference member, the second imaging unit detects the position of the reference member when moving the bonding tool above the reference member according to pre-stored offset values, and detects a position of a ball-shaped tip section of a wire, and the control unit measures a change in offset between the bonding tool and the first imaging unit based on each detection result. |
| US10262967B2 |
Semiconductor packages
A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer. |
| US10262962B2 |
Semiconductor device
A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad. |
| US10262959B2 |
Semiconductor devices and methods of forming thereof
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced. |
| US10262958B2 |
Package with solder regions aligned to recesses
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. |
| US10262956B2 |
Timing based camouflage circuit
In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior. |
| US10262955B2 |
Activating reactions in integrated circuits through electrical discharge
Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit. |
| US10262949B2 |
Fan-out semiconductor package and method of manufacturing the same
The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member. |
| US10262944B2 |
Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions. |
| US10262942B2 |
Method of forming cobalt contact module and cobalt contact module formed thereby
The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method. |
| US10262941B2 |
Devices and methods for forming cross coupled contacts
Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed. |
| US10262940B2 |
Electric connector
An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied. |
| US10262931B2 |
Lateral vias for connections to buried microconductors and methods thereof
The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein. |
| US10262930B2 |
Interposer and method for manufacturing interposer
An interposer includes an insulating layer, conductor circuits formed in grooves formed on a first surface of the insulating layer respectively, and metal posts formed in openings extending from the grooves to a second surface of the insulating layer on the opposite side with respect to the first surface such that the metal posts are connected to the conductor circuits respectively. The insulating layer has an opening portion which accommodates an electronic component and is extending from the first surface to the second surface of the insulating layer, and each of the metal posts has an upper surface and a bottom surface on the opposite side of the upper surface such that the upper surface is connected to a respective one of the conductor circuits and that the bottom surface is exposed from the second surface of the insulating layer. |
| US10262928B2 |
Semiconductor device
A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b. |
| US10262927B2 |
Semiconductor device and manufacturing method thereof
Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA). |
| US10262926B2 |
Reversible semiconductor die
A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires. |
| US10262920B1 |
Stacked silicon package having a thermal capacitance element
Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die. |
| US10262908B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed. |
| US10262907B1 |
Dye and pry process for removing quad flat no-lead packages and bottom termination components
Embodiments of the invention include a dye and pry process for removing quad flat no-lead (QFN) packages and bottom termination components (BTC) from card assemblies. Aspects of the invention include immersing a semiconductor package assembly in a solution comprising dye and placing the immersed semiconductor package assembly under vacuum pressure. Vacuum conditions ensure that the dye solution is pulled into any cracks in the solder formed between the semiconductor package assembly and the QFN package or BTC. The package assembly is dried and a hole is drilled to expose a bottom surface of the QFN package or BTC. The QFN package or BTC is then removed by applying a force to the exposed bottom surface. The semiconductor package assembly can then be inspected for the dye to locate cracks. |
| US10262904B2 |
Vertical transistor top epitaxy source/drain and contact structure
An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process. |
| US10262902B2 |
Multiplexer and integrated circuit using the same
The multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source. One of gates of the P-type gate field effect transistor is connected to a second threshold voltage control node, and a second resistor is connected between the second threshold voltage control node and a second threshold voltage control voltage source. |
| US10262899B2 |
Method of processing wafer
A wafer has a plurality of projected dicing lines on a face side thereof, a plurality of devices formed in respective areas demarcated on the face side of the wafer by the projected dicing lines, a plurality of grooves defined in the projected dicing lines, and a molding resin laid on the devices and embedded in the grooves. An outer circumferential portion of the molding resin is removed, exposing the molding resin embedded in the grooves. The molding resin embedded in the grooves exposed on an outer circumferential portion of the wafer is detected, and a laser beam is focused at a transversely central point on the molding resin embedded in the grooves. The laser beam is applied to the molding resin along the grooves, thereby forming dividing grooves in the wafer to allow the wafer to be divided into individual devices. |
| US10262898B2 |
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening. |
| US10262897B2 |
Bond pad protection for harsh media applications
A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part. |
| US10262896B2 |
Formation of a transition metal nitride
A use of an amine-containing silane for forming a transition metal nitride is provided. In this use, the amine of the amine-containing silane is the source of at least some, preferably most and most preferably all of the nitrogen present in the transition metal nitride. |
| US10262894B2 |
FinFET device and method for forming the same
Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween. |
| US10262888B2 |
Apparatus and methods for wafer rotation in carousel susceptor
Apparatus and method for processing a plurality of substrates in a batch processing chamber are described. The apparatus comprises a susceptor assembly, a lift assembly and a rotation assembly. The susceptor assembly has a top surface and a bottom surface with a plurality of recesses in the top surface. Each of the recesses has a lift pocket in the recess bottom. The lift assembly including a lift plate having a top surface to contact the substrate. The lift plate is connected to a lift shaft that extends through the susceptor assembly and connects to a lift friction pad. The rotation assembly has a rotation friction pad that contacts the lift friction pad. The rotation friction pad is connected to a rotation shaft and can be vertically aligned with the lift friction pad. |
| US10262885B2 |
Multifunction wafer and film frame handling system
A multifunction wafer and film frame handling system includes a wafer table assembly having a wafer table providing an ultra-planar wafer table surface configured for carrying a wafer or a film frame, and at least one of: a flattening apparatus configured for automatically applying a downward force to portions of a warped or non-planar wafer in a direction normal to the wafer table surface; a displacement limitation apparatus configured for automatically constraining or preventing uncontrolled lateral motion of a wafer relative to the wafer table surface after cessation of an applied negative pressure and application of a positive pressure to the underside of the wafer via the wafer table; and a rotational misalignment compensation apparatus configured for automatically compensating for a rotational misalignment of a wafer mounted on a film frame. |
| US10262881B2 |
Environmentally controlled coating systems
Embodiments of an enclosed coating system according to the present teachings can be useful for patterned area coating of substrates in the manufacture of a variety of apparatuses and devices in a wide range of technology areas, for example, but not limited by, OLED displays, OLED lighting, organic photovoltaics, Perovskite solar cells, and organic semiconductor circuits. Enclosed and environmentally controlled coating systems of the present teachings can provide several advantages, such as: 1) Elimination of a range of vacuum processing operations such coating-based fabrication can be performed at atmospheric pressure. 2) Controlled patterned coating eliminates material waste, as well as eliminating additional processing typically required to achieve patterning of an organic layer. 3) Various formulations used for patterned coating with various embodiments of an enclosed coating apparatus of the present teachings can have a wide range of physical properties, such as viscosity and surface tension. Various embodiments of an enclosed coating system can be integrated with various components that provide a gas circulation and filtration system, a particle control system, a gas purification system, and a thermal regulation system and the like to form various embodiments of an enclosed coating system that can sustain an inert gas environment that is substantially low-particle for various coating processes of the present teachings that require such an environment. |
| US10262876B2 |
Substrate processing apparatus
A substrate holding unit which holds the substrate, a nozzle which includes a first cylindrical member within which a first flow path along which the first fluid is passed is formed and in which a tip end edge of the first cylindrical member defines, between the tip end edge and a main surface of the substrate, an annular first discharge port that discharges the fluid flowing through the first flow path along the main surface of the substrate radially and a first fluid supply unit which is a fluid supply unit supplying the first fluid to the first flow path of the nozzle and which applies, to the nozzle, a force in a direction apart from the main surface of the substrate, by the discharge of the first fluid from the first discharge port. |
| US10262874B2 |
Semiconductor module radiator plate fabrication method, radiator plate, and semiconductor module using the same
A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering. |
| US10262873B2 |
Pre-heat processes for millisecond anneal system
Preheat processes for a millisecond anneal system are provided. In one example implementation, a heat treatment process can include receiving a substrate on a wafer support in a processing chamber of a millisecond anneal system; heating the substrate to an intermediate temperature; and heating the substrate using a millisecond heating flash. Prior to heating the substrate to the intermediate temperature, the process can include heating the substrate to a pre-bake temperature for a soak period. |
| US10262872B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a method of manufacturing a semiconductor device. The method includes: forming a first amorphous silicon film on a substrate in a process chamber; and etching a portion of the first amorphous silicon film using a hydrogen chloride gas under a temperature at which an amorphous state of the first amorphous silicon film is maintained, in the process chamber. |
| US10262871B1 |
Formation of field-tunable silicon carbide defect qubits with optically transparent electrodes and silicon oxide surface passivation
A method includes depositing a layer of silicon oxide onto a layer of silicon carbide; ion implanting the layer of silicon carbide, annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide, performing photolithography using a mask layer on regions of the layer of silicon carbide to define regions for electrode deposition, removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition, forming one or more electrodes by depositing indium tin oxide (ITO) in each of the regions for electrode deposition, performing a first lift-off operation to remove the mask layer surrounding the electrodes, depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes, and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes. |
| US10262870B2 |
Fin field effect transistor (FinFET) device structure and method for forming the same
A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width. |
| US10262869B2 |
Planarization method
A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed. |
| US10262866B2 |
Indium phosphide smoothing and chemical mechanical planarization processes
A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas. |
| US10262865B2 |
Methods for manufacturing semiconductor devices
An example method for manufacturing a semiconductor device includes forming a nitride, carbide, or metal film on a substrate in a chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, purging an interior of the chamber, forming an oxide film on the substrate in the chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, and supplying a reducing gas into the chamber to create a reduction atmosphere and purging the interior of the chamber. The forming of the nitride film, carbide, or metal, purging, forming an oxide film, and supplying the reducing gas may be repeated a plurality of times. |
| US10262858B2 |
Surface functionalization and passivation with a control layer
Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiNx monolayer at temperatures below about 300° C. |
| US10262857B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a method of manufacturing a semiconductor device, comprising forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times. The cycle includes alternately performing supplying a halogen-based first process gas to the substrate in the process chamber, and supplying a non-halogen-based second process gas to the substrate in the process chamber. Further, an internal pressure of the process chamber in the act of supplying the first process gas is set to be higher than an internal pressure of the process chamber in the act of supplying the second process gas. |
| US10262850B2 |
Inorganic and organic mass spectrometry systems and methods of using them
Certain configurations of systems and methods that can detect inorganic ions and organic ions in a sample are described. In some configurations, the system may comprise one, two, three or more mass spectrometer cores. In some instances, the mass spectrometer cores can utilize common components such as gas controllers, processors, power supplies and vacuum pumps. In certain configurations, the systems can be designed to detect both inorganic and organic analytes comprising a mass from about three atomic mass units, four atomic mass units or five atomic mass units up to a mass of about two thousand atomic mass units. |
| US10262845B2 |
System and method for enhanced ion pump lifespan
Within an ion pump, accelerated ions leave the center portion of an anode tube due to the anode tube symmetry and the generally symmetrical electric fields present. The apparent symmetry within the anode tube may be altered by making the anode tube longitudinally segmented and applying independent voltages to each segment. The voltages on two adjacent segments may be time varying at different rates to achieve a rasterizing process. In various embodiments, one or more wire internal to the anode structure and having a time-varying electric potential may alter the trajectory of the ions leaving the anode tube, as may the shape of the anode near the ends of the anode tube. |
| US10262843B2 |
Cooling water jet pack for high power rotary cathodes
A sputtering target assembly, including a cylindrical backing tube, a magnet assembly disposed within the backing tube, and a conduit disposed within the backing tube and adapted for transporting coolant. The conduit includes at least one first opening positioned for providing the coolant in a substantially circumferential direction from the conduit toward an inner surface of the backing tube into a gap volume between a front side of the magnet assembly and the inner surface of the backing tube. |
| US10262839B2 |
Aluminum apparatus with aluminum oxide layer and method for forming the same
In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75° C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm. |
| US10262830B2 |
Scanning electron microscope and electron trajectory adjustment method therefor
To provide a scanning electron microscope having an electron spectroscopy system to attain high spatial resolution and a high secondary electron detection rate under the condition that energy of primary electrons is low, the scanning electron microscope includes: an objective lens 105; primary electron acceleration means 104 that accelerates primary electrons 102; primary electron deceleration means 109 that decelerates the primary electrons and irradiates them to a sample 106; a secondary electron deflector 103 that deflects secondary electrons 110 from the sample to the outside of an optical axis of the primary electrons; a spectroscope 111 that disperses secondary electrons; and a controller that controls application voltage to the objective lens, the primary electron acceleration means and the primary electron deceleration means so as to converge the secondary electrons to an entrance of the spectroscope. |
| US10262826B2 |
Snap fit circuit breaker and load center system
A circuit breaker and panel system includes a panel including a base pan having a plurality of base pan electrical connections. A circuit breaker including a housing having a plurality of circuit breaker electrical connections arranged to contact the base pan electrical connections when the circuit breaker is coupled to the base pan. The circuit breaker is rotatably coupleable with the base pan via a pivot joint for engaging the plurality of base pan electrical connections with the plurality of circuit breaker electrical connections per a predetermined electrical connection coupling sequence. One of the housing and the base pan includes a protrusion and the other of the housing and the base pan includes a corresponding recess which, when engaged with each other, retain the housing to the base pan to prevent reverse rotational movement of the breaker with respect to the base pan. |
| US10262824B2 |
Operation coil drive device of electromagnetic contactor
Operation coil drive device of electromagnetic contactor includes current detector and drive controller. The detector, when switching control is performed on operation coils of the contactor, detects coil current flowing through the coils. The controller controls an on/off time ratio of a semiconductor switching element wherein the on/off time ratio during close circuit control becomes larger than the on/off time ratio during holding control. Power supply voltage is switchingly applied to the coils at the on/off time ratio. The controller includes a determination locus setter and a close circuit state determiner. The setter sets a determination locus that continuously increases along a change locus of detected coil current during close circuit control. The determiner determines a contact point close circuit state by contact of a movable contact to a fixed contact based on deviation between the determination locus by the setter and the detected coil current detected. |
| US10262822B2 |
Load drive apparatus
A load drive apparatus includes: a first drive element that drives a first load; a second drive element that drives a second load; a control circuit that controls the first drive element and the second drive element; a power supply circuit that supplies electric power; and a failsafe circuit that includes an abnormality detection portion detecting whether an abnormality occurs in at least one of the control circuit and the power supply circuit, the failsafe circuit controlling the first drive element and the second drive element to drive the first load and the second load when the abnormality detection portion has detected that an abnormality occurs in at least one of the control circuit and the power supply circuit and also when the load drive apparatus receives at least one of a command directing a drive of the first load and a command directing a drive of the second load. |
| US10262821B2 |
Environmentally protected switch for activating an electronic device when submersed in a conducting fluid
An environmentally protected switch and water activated device using the switch is disclosed. The switch comprises an elongate housing having an open end and divided into a pair of chambers and into which a probe is inserted. When water infiltrates the housing an electrical circuit is completed between the two probes. There is also disclosed a lens/selector assembly comprising a selector ring encircling a lens and a wave spring which biases the selector ring into one of a number of predetermined positions around the lens. Illustratively, a magnet is placed within the selector ring a position of which can be detected by electronics within the lens. |
| US10262816B2 |
Key input apparatus sensing touch and pressure and electronic apparatus having the same
According to one embodiment, there is provided an input apparatus comprising a key that is displaceable along a direction; a first detecting circuit that comprises an electrostatic capacitance sensor that detects a variation of an electrostatic capacitance caused by a contact or a proximity of a pressing body with the key; and a second detecting circuit that comprises a first electrode, the second detecting circuit detecting an electric connection of the first electrode to a second electrode that is displaced along the direction as the key is displaced, wherein the input apparatus switches a detecting status thereof exclusively between a first detecting status and a second detecting status to each other in accordance with a displacement variation of the key. |
| US10262813B2 |
Circuit breaker containing a gas escape hood with sealable opening
A medium-, high-, or very high-voltage circuit breaker (10), comprising at least one arc-control chamber (12) and an outer casing (14) in which the arc-control chamber (12) is arranged. In the invention, the circuit breaker includes sealing ring (52) for sealing an opening (50) in a discharge cap (40) of the arc-control chamber (12), the ring (52) being movable between a sealing position and a retracted position in which they allow the gas to pass, the circuit breaker being configured in such a manner that in the closed position, the sealing ring (52) are in their retracted position, and in such a manner that passage from the retracted position to the sealing position takes place during an operation of opening the circuit breaker. |
| US10262812B2 |
Lockout device and method for its use
A lockout device for preventing an electrical switch from being turned either ON or OFF while the lockout device is attached to the switch. The present lockout device can be capable of quick and easy attachment to the switch and can be secured to the switch with a padlock or similar locking device. The present lockout device can also have a peg for attaching a lockout tag, which prevents the tag from being removed while the lockout device is connected to a switch. |
| US10262811B2 |
Control system for an electrical switching apparatus and related electrical switching apparatus
A control system for an electrical switching apparatus adapted to be installed in a medium voltage or high voltage electrical circuit. The control system includes at least a first module with first control means which are adapted to execute a first control logic, and a second module with second control means which are adapted to execute a second control logic; and at least one communication bus. The first control means and the second control means are adapted to be operatively connected to the at least one communication bus, and to share values of variables associated to the first control logic and to the second control logic through the at least one communication bus. |
| US10262805B2 |
Variable capacitance element
A variable capacitance element includes variable capacitance layers made of a dielectric material, paired electrodes located on both main surfaces of the variable capacitance layers opposite to each other across the variable capacitance layers, insulating elements; and at least one pair of lead-out elements. The variable capacitance layers and the insulating elements are alternately laminated to provide a laminated body. The variable capacitance layers and the paired electrodes define capacitor structures, and the lead-out elements are electrically connected at one end thereof to an electrode defining the capacitor structures, penetrate the insulating elements, and are electrically connected at the other end to external electrodes or other electrical elements. |
| US10262802B2 |
Capacitor and method for manufacturing same
A capacitor includes a capacitor element having internal electrodes and dielectric layers, the internal electrodes and the dielectric layers being alternately laminated; a first electrode layer formed on an edge surface of the capacitor element and connected to an internal electrode of the internal electrodes; and a second electrode layer formed into a mesh shape or a dot shape on the first electrode layer. |
| US10262801B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes an electronic component body including a laminate and an external electrode, and a pair of metal terminals that are joined by a joining material. The pair of metal terminals includes a terminal joint portion, an extended portion and a mounting portion. The external electrode is provided only on both end surfaces of the laminate, and includes first and second external electrodes. The first external electrode and the second external electrode each include a saddle portion with a thickness larger than the thickness of a center portion of each end surface in the periphery of the first end surface and the second end surface of the laminate, respectively. |
| US10262800B2 |
Multilayer ceramic capacitor
In an embodiment, one length-direction end of each first internal electrode layer 111a of the capacitor body 110 is connected, via the conductive part 114a of the first relay layer 114 connected over a connection width equivalent to the width of each first internal electrode layer 111a, to the first external electrode 120 provided on one height-direction face of the capacitor body 110; also, the other length-direction end of each second internal electrode layer 111b is connected, via the conductive part 115a of the second relay layer 115 connected over a connection width equivalent to the width of each second internal electrode layer 111b, to the second external electrode 130 provided on one height-direction face of the capacitor body 110. |
| US10262798B2 |
Multilayer electronic component
In an embodiment of a multilayer electronic component, one main electrode part 12a of the first external electrode 12 present on one height-direction face of the capacitor body 11 of the multilayer capacitor is partially opposed to the other main electrode part 13a of the second external electrode 13 present on the other height-direction face, while one main electrode part 13a of the second external electrode 13 present on one height-direction face of the capacitor body 11 is partially opposed to the other main electrode part 12a of the first external electrode 12 present on the other height-direction face of the capacitor body 11, and margin areas MR1 to MR4 of roughly belt shape exist between each of the opposing areas OR and each of the edges on both height-direction faces of the capacitor body 11. |
| US10262794B2 |
Winding method
A method includes bending back a wire fed to a first end side of a magnetic pole in a winding position by guiding the wire from a first end side to a second end side of a multi-pole armature, so that a first extending portion, a second extending portion, and an arc portion are formed. The first extending portion and the second extending portion are continuous via the arc portion. The first extending portion and the second extending portion are parallel to each other. The first extending portion and second extending portion are simultaneously inserted into slots on both sides of one or more of the magnetic poles in the winding position by moving the wire in a radial direction of the multi-pole armature. The slots are parallel to each other. The bending back the wire step and the simultaneous insertion step are performed repeatedly. |
| US10262791B2 |
Arrangement of single phase transformers
A configuration for replacing a multi-phase transformer includes a plurality of single phase transformers each having a housing which is filled with an insulating fluid and in which a core with a high-voltage winding and a low-voltage winding is disposed. The configuration can be set up flexibly and also connected easily and conveniently to a supply network or consumer network by providing each housing with at least one cable connection and connecting each cable connection through a cable line to an outdoor connection which is air insulated, constructed for outdoor use and set up separately from the housing. |
| US10262789B2 |
Transformer and switched-mode power supply apparatus
A transformer is capable of suppressing the output voltage difference, and a switched-mode power supply apparatus uses the transformer. A transformer has a core; a primary winding provided in the core; a gap provided in the core at a location where the primary winding is provided; and at least two secondary windings, provided in the core and spaced apart from both sides of the primary winding as well as the gap at an equal distance in a winding axis direction of the primary winding. A switched-mode power supply apparatus has the transformer; a switching element connected to the primary winding of the transformer; and a control circuit configured to control the switching element. |
| US10262788B2 |
Method to enable standard alternating current (AC)/direct current (DC) power adapters to operate in high magnetic fields
A power supply (10) and corresponding method (200) supply power in high external magnetic fields. A power converter system (12) converts input power to output power using one or more electromagnetic components (18). One or more ferrous bands (16) encircle the electromagnetic components (18) and shield the electromagnetic components (18) from the high external magnetic fields. |
| US10262787B2 |
Coil component
A coil component includes a conducting wire and a terminal electrode. The terminal electrode includes a first terminal piece and a second terminal piece that face and overlap each other with the conducting wire interposed therebetween. The first terminal piece and the second terminal piece are coupled to one another with a coupling portion and are integrated in a welded ball at a position different from a position of the coupling portion. An end portion of the conducting wire is in the welded ball. |
| US10262784B2 |
Ceramic insulated transformer
A transformer includes a ceramic housing, a primary winding disposed within the housing, a secondary winding disposed outside the winding, and a core extending through a first aperture in the housing. The housing includes a first portion and a second portion. Each of the first and second portions include a planar structure having a first housing aperture, and a plurality of sidewalls extending perpendicular to the planar structure along a plurality of edges of the planar structure. The first and second portions interface with one another when the ceramic housing is assembled such that the sidewalls of the first and second portions overlap with one another. |
| US10262782B1 |
Integrated inductor structure
An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit. |
| US10262781B2 |
Superconducting wire and method for manufacturing the same
Included are: a first superconducting wire rod having a first front surface, and a first back surface, and also having a first superconducting layer, and first reinforcing layers; a second superconducting wire rod having a second front surface, and a second back surface, and also having a second superconducting layer, and second reinforcing layers; and a connection member joining the first superconducting wire rod to the second superconducting wire rod. The first superconducting wire rod has a first edge portion, and the second superconducting wire rod has a second edge portion. The first front surface located at the first edge portion is joined by the connection member to the second front surface located at other than the second edge portion, and the second front surface located at the second edge portion is joined by the connection member to the first front surface located at other than the first edge portion. |
| US10262778B2 |
Multilayer component and process for producing a multilayer component
A multilayer component and a mathod for producing a multilayer component are disclosed. In an embodiment the multilayer component includes a ceramic main element being a varistor ceramic and at least one metal structure, wherein the metal structure is cosintered, and wherein the main element is doped with a material of the metal structure in such a way that a diffusion of the material from the metal structure into the main element during a sintering operation is reduced. |
| US10262774B2 |
Insulated electric cable
An insulated electric cable 10 has a core member 1 formed by stranding a plurality of core wires 4, each of the core wires 4 including a conductor 5 and an insulating layer 6 covering the conductor 5, an inner sheath 7 covering the core member 1, an outer sheath 8 covering the inner sheath 7, and a paper tape 2 disposed between the core member 1 and the inner sheath 7 in a state that it is wrapped around the core member 1, in which the outer sheath 8 is formed by a flame-retardant polyurethane resin, and a cross-sectional area of each of conductors 5 is within 0.18-3.0 mm2. |
| US10262773B2 |
Corrosion protection of buried metallic conductors
A method for protecting a conductive metal from corrosion, including coating the conductive metal with a water impermeable carbonaceous conductive material to protect the conductive metal from corrosion. |
| US10262768B2 |
Power cable for cable deployed electric submersible pumping system
A technique facilitates construction and operation of a power cable which may be used to deploy an electric submersible pumping system downhole into a wellbore. The power cable is constructed to provide structural support of the electric submersible pumping system while also providing electric power to the electric submersible pumping system when located downhole in the wellbore. The power cable has at least one conductor and a plurality of layers selected and arranged to ensure long-term support and delivery of electrical power in the relatively harsh downhole environment. |
| US10262765B2 |
Method and facility for incinerating, melting and vitrifying organic and metal waste
The method according to the invention enables a facility having a rather reduced dimension, for incinerating to be used, melting and vitrifying mixed waste (30) introduced into a reactor (10), by means of a basket (18) in turn passing through an air lock (12). Plasma torches (14) burn all waste (30) contained in the basket (18). The waste is then lowered in a melting bath of a furnace (20) with an inductor (24) including a crucible-forming container (23). A combustion gas treatment train completes the facility.The furnace (20) can be dismantled, after a series of treatments of several baskets (18) of waste (30) for disassembling the crucible-forming container (23) from the furnace (20).Application in treating different radiologically contaminated and/or toxic mixed waste. |
| US10262764B2 |
Advanced non-toxic Red Mud based Nano gel type functional radiation shielding materials and the process thereof
The conventional radiation shielding materials are made using lead, barite and hematite ore which are either toxic, costly and are non-replinshable possessing limited functionality. In view of above, we develop a novel process for making advanced non-toxic Red Mud based functional radiation shielding materials utilizing appropriate novel matrixes like Advanced geopolymer, geopolymeric-polymeric matrix, putty, cement and phosphatic based matrix and are also compatible with conventional matrixes. The appropriate physico-chemical consolidation and or densification of red mud using advanced or conventional matrix helps in obtaining functional radiation shielding material by simultaneous and synergistic chemical reactions among various mineralogical and chemical compounds of red mud with complementary various chemical compounds present in citrus fruit peel waste especially citric acid to form nano gel material to obtain the fine “tailored shielding powder”. The developed material has broad application spectrum from diagnostic radiation installations like diagnostic X-ray to CT scanner room. |
| US10262763B2 |
Systems, devices, and/or methods for managing radiation shielding
Certain exemplary embodiments can provide a system comprising a substantially transparent radiation shield, which comprises transparent ammonium metatungstate. The transparent ammonium metatungstate can have a density of greater than 1.5 gram/(cubic centimeter). The substantially transparent radiation shield can be installed on tanks and/or pressure vessels, used as a transparent radiation shield in medical shielding/devices, used as windows in glove boxes, and any application where effective radiation shielding is needed with transparency. The substantially transparent radiation shield can be used in one or more articles worn by a human. |
| US10262762B2 |
Apparatus for generating first vascular data having a tree structure based on anatomical data and generating second vascular data without relying on the anatomical data
In a vascular data generation apparatus, a processor generates first vascular data based on anatomical statistics data about vessels of an organ. This first vascular data has a tree structure representing a vascular network in the organ. The processor further generates second vascular data representing a plurality of vessels that connect a plurality of nodes in a geometric model of the organ with the vascular network represented by the first vascular data. |
| US10262760B2 |
System and method of interactive navigation of subject's treatment
System and method for monitoring a subject's condition. The system comprises a data input utility for receiving medical data indicative of a first condition of a subject; a communication utility for obtaining reference data comprising at least two predefined multi-dimensional functions and a multi-parameter space within said functions corresponding to a normal condition of a subject; a processing utility for processing said medical data of a subject by identifying a plurality of individual medical parameters describing said at least two predefined multi-dimensional functions, analyzing the identified plurality of individual parameters and determining a relation between the parameters and said multi-parameter space, for determining a treatment plan for navigating the subject from said first condition to a second subject condition in which values of said plurality of medical parameters define a parametric space matching the multi-parameter space of the normal condition; and an output utility for outputting said treatment plan. |
| US10262759B2 |
Personal health operating system
A method for facilitating a personal health operating system (PHOS) is provided in one example embodiment and includes extracting data into a mobile device that includes a portable health virtual machine executing the PHOS using a processor couples to a memory element, generating an N-gram dataset comprising data indicative and predictive of fitness of an individual, generating, in the PHOS, an N-gram from the N-gram dataset from the data according to a data structure indicative and predictive of fitness of an individual, the fitness including a numerical index representing a composite effect of various health conditions of the individual including interdependencies of the health conditions, generating an N-gram based on the N-gram dataset and calculating the individual's fitness using the N-gram. |
| US10262749B2 |
Shift register unit and driving method, shift register, gate driving circuit and display device
A shift register unit comprises a pull-up module, a clock signal input terminal, a storage module, a signal output terminal, a control voltage signal input terminal and a current leakage suppression module. An output terminal of the current leakage suppression module is connected to a control terminal of the pull-up module A first input terminal of the current leakage suppression module is connected to the control voltage signal input terminal A second input terminal of the current leakage suppression module is connected to the other end of the storage module. A driving method uses a shift register unit, a shift register, a gate driving circuit, and a display device. |
| US10262747B2 |
Method to reduce program disturbs in non-volatile memory cells
A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array. |
| US10262745B2 |
Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string. |
| US10262744B2 |
Layer-based memory controller optimizations for three dimensional memory constructs
Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell. |
| US10262742B2 |
Memory protection circuit and liquid crystal display including same
Provided is a liquid crystal display device, including: a liquid crystal display panel; a memory for storing driving information and image data modulation information, and supplying the stored driving information and image data modulation information to a timing controller; a memory protection circuit for enhancing a write protection function of the memory, the memory protection circuit including a pull-up resistor for pulling up a write protection terminal of the memory to a power voltage, and a pad connected to the write protecting terminal and applying a low voltage to the write protection terminal; and a timing controller for reading the data stored in the memory to output various control signals for driving the liquid crystal display panel. |
| US10262740B2 |
Semiconductor memory device
A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops. |
| US10262734B2 |
Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. |
| US10262731B2 |
Device and method for forming resistive random access memory cell
A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed. |
| US10262730B1 |
Multi-state and confined phase change memory with vertical cross-point structure
A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation. |
| US10262724B2 |
Memory cell of static random access memory based on DICE structure
A memory cell of a static random access memory based on DICE structure, which includes a redundant information latch circuit and a redundant bit selection circuit. The redundant information latch circuit is formed by four MOS transistors and includes four data storage nodes, the redundant bit selection circuit is formed by four MOS transistors M0, M1, M2 and M3, with their drains connected to the four data storage nodes X0, X1, X2 and X3. Sources of M0 and M2 are connected to each other and are connected to a bit line BL, sources of M1 and M3 are connected to each other and are connected to a bit line BLB; and gates of the four MOS transistors are connected to each other and are connected to a word line WL. |
| US10262717B2 |
DRAM adjacent row disturb mitigation
The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate. |
| US10262712B2 |
Memory device with a control circuit to control data reads
According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line. |
| US10262703B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, a first word line electrically coupled to the first memory cell, a second word line electrically coupled to the second memory cell, and a control circuit configured to supply voltages to the first word line and the second word line. In a read, the control circuit applies a first voltage to the first word line and a second voltage to the second word line, applies, after applying the first voltage to the first word line and the second voltage to the second word line, a third voltage lower than the first voltage and the second voltage to the second word line, and applies, after applying the third voltage to the second word line, the third voltage to the first word line. |
| US10262702B2 |
System for implementation of a hash table
The system contains at least one basic block formed by a first multiplexer having an output is connected to a flag register memory, implemented as a LUT table. An output of a circuit for write permit to the memory is connected to the input of the write signal to the memory, which is further equipped with the clock signal input and the data input. The data output from the memory of each basic block is connected to a masking block relevant for the given basic block. The outputs of these masking blocks are connected to the inputs of the second multiplexer, while its output is the output of the system of flags. The input of the control signal for writing to the memory of each basic block is connected to the output of the demultiplexer and to the second input of the masking block for the given basic block. |
| US10262701B2 |
Data transfer between subarrays in memory
The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array. |
| US10262699B2 |
Memory device for performing internal process and operating method thereof
A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed. |
| US10262698B2 |
Intermittent operation of compartmented pneumatics for sealed data storage system
A data storage system includes multiple hermetically-sealed enclosures containing a lighter-than air gas, multiple data storage devices housed in each enclosure and containing the lighter-than-air gas, a tray pneumatic control system each corresponding to and pneumatically coupled to a corresponding hermetically-sealed enclosure, and a rack pneumatic control system pneumatically coupled to each tray pneumatic control system. The tray pneumatic control system may include a tray valve operable in a first way to provide a vacuum in a space between first and second sealing members of the enclosure, and operable in a second way to provide the lighter-than-air gas to the enclosure. The rack pneumatic control system may include a vacuum source operable to provide a vacuum to each tray valve and a lighter-than-air gas source operable to provide the lighter-than-air gas to each tray valve. |
| US10262687B1 |
Disc grabbing device for grabbing a plurality of discs and sequentially unloading the plurality of discs
A disc grabbing device including a support body, a drive shaft, multiple first planetary gears, a center gear, multiple second planetary gears and a driver is provided. The support body includes a plate and a center column. When the disc grabbing device grabs the discs, the center column is located in the center holes of the discs. The drive shaft is rotatably disposed on the plate. The first planetary gears are respectively engaged with the drive shaft and connected to multiple first levers for driving the first levers to rotate. The second planetary gears are respectively engaged with the center gear and connected to multiple second levers for driving the second levers to rotate. The driver concurrently drives the drive shaft and the center gear to rotate the first planetary gears and the second planetary gears synchronically and make the first levers and the second levers rotate synchronically. |
| US10262686B2 |
System and method for write protecting portions of magnetic tape storage media
A non-transitory computer readable storage medium includes a tape having a plurality of partitions configured for storing data, and a plurality of read-only partition identifiers, each read-only partition identifier associated with one of the plurality of partitions and readable by a tape drive having a processor and memory for writing and reading tape data. Each read-only partition identifier selectively designates a corresponding one of the partitions as read-only to prevent data from being written to the designated read-only partition by the tape drive. |
| US10262684B2 |
Tape head formed with high accuracy tape bearing surface length definition process
In one general embodiment, an apparatus includes a substrate, a thin film layer on the substrate having transducers therein, and a portion of a slot extending along the substrate, the portion of the slot defining a skiving edge. A length of a tape bearing surface between the thin film layer and the skiving edge is in a range of about 7 to about 30 microns. In another general embodiment, an apparatus includes a substrate, a thin film layer on the substrate having transducers therein, and a slot extending along the substrate, the slot defining a skiving edge. A length of a tape bearing surface between the thin film layer and the skiving edge is in a range of about 7 to about 30 microns. |
| US10262683B2 |
Self-aligned hybrid Au—Rh near field transducer for enhanced reliability
A near field transducer (NFT) is formed between a waveguide and main pole layer at an air bearing surface (ABS). The NFT includes a resonator body layer made of Au, for example, with a front side at a first plane that is recessed a first distance from the ABS and a back side that is at a second plane formed parallel to the ABS and first plane. The NFT also has a peg layer with a rectangular peg portion between the ABS and first plane, and a larger back portion between the first and second planes that overlays directly above the resonator body layer. The peg layer is preferably made of Rh to improve mechanical stability of the NFT without significantly degrading overall optical efficiency of the NFT. A blocker may be formed between the ABS and waveguide to prevent light not coupled to the NFT from reaching the ABS. |
| US10262679B2 |
Method and system for a headset with profanity filter
A gaming headset receives a plurality of audio channels comprising game audio channels and a chat audio channel during play of a particular game. The gaming headset monitors the received audio channels for predefined words that are associated with particular sounds in a data structure, and in response to detecting predefined words, filters out at least a portion of the detected predefined words from the received plurality of audio channels. The monitoring compares sounds on the received audio channels with the particular sounds in the data structure and also performs signal analysis on the audio channels during game play to detect the occurrence of the predefined words. The filtering mutes one or more of the plurality of audio channels so that the detected occurrence of the one of the predefined words is not output via speakers of the gaming headset. |
| US10262670B2 |
Method for decoding a higher order ambisonics (HOA) representation of a sound or soundfield
When compressing an HOA data frame representation, a gain control (15, 151) is applied for each channel signal before it is perceptually encoded (16). The gain values are transferred in a differential manner as side information. However, for starting decoding of such streamed compressed HOA data frame representation absolute gain values are required, which should be coded with a minimum number of bits. For determining such lowest integer number (βe) of bits the HOA data frame representation (c(k)) is rendered in spatial domain to virtual loudspeaker signals lying on a unit sphere, followed by normalisation of the HOA data frame representation (c(k)). Then the lowest integer number of bits is set to βe=┌log2(┌log2(√{square root over (KMAX)}·O)┐+1)┐. |
| US10262668B2 |
Decoding audio bitstreams with enhanced spectral band replication metadata in at least one fill element
Embodiments relate to an audio processing unit that includes a buffer, bitstream payload deformatter, and a decoding subsystem. The buffer stores at least one block of an encoded audio bitstream. The block includes a fill element that begins with an identifier followed by fill data. The fill data includes at least one flag identifying whether enhanced spectral band replication (eSBR) processing is to be performed on audio content of the block. A corresponding method for decoding an encoded audio bitstream is also provided. |
| US10262664B2 |
Method and apparatus for encoding and decoding digital data sets with reduced amount of data to be stored for error approximation
When combining digital data sets in the time domain into a combined digital data set a subset of samples of each digital data set is adjusted to enable unraveling the data when decoding. To enable correction during decoding of an error introduced by the adjustment, an error approximation is stored for each adjusted sample. A set of error approximations is created which is indexed allowing substantial reduction in size of the error approximations to be stored for the adjusted samples. Instead of creating a set of error approximations for each combined digital data set one set of error approximations is created based on the errors introduced when creating multiple combined digital data sets. |
| US10262663B2 |
Method and apparatus for low bit rate compression of a higher order ambisonics HOA signal representation of a sound field
The invention is suited for improving a low bit rate compressed and decompressed Higher Order Ambisonics HOA signal representation of a sound field, wherein the decompression provides a spatially sparse decoded HOA representation and a set of indices of coefficient sequences of this representation. From reconstructed signals of the original HOA representation a number of modified phase spectra signals are created using de-correlation filters, which modified phase spectra signals are uncorrelated with the signals of said original representation. The modified phase spectra signals are mixed with each other using predetermined mixing parameters, in order to provide a replicated ambient HOA component. Finally the spatially sparse decoded HOA representation is enhanced with the replicated time domain HOA representation. |
| US10262662B2 |
Audio decoder and method for providing a decoded audio information using an error concealment based on a time domain excitation signal
An audio decoder for providing a decoded audio information on the basis of an encoded audio information includes an error concealment configured to provide an error concealment audio information for concealing a loss of an audio frame following an audio frame encoded in a frequency domain representation using a time domain excitation signal. |
| US10262657B1 |
Processing spoken commands to control distributed audio outputs
A system that is capable of controlling multiple entertainment systems and/or speakers using voice commands. The system receives voice commands and may determine audio sources and speakers indicated by the voice commands. The system may generate audio data from the audio sources and may send the audio data to the speakers using multiple interfaces. For example, the system may send the audio data directly to the speakers using a network address, may send the audio data to the speakers via a voice-enabled device or may send the audio data to the speakers via a speaker controller. The system may generate output zones including multiple speakers and may associate input devices with speakers within the output zones. For example, the system may receive a voice command from an input device in an output zone and may reduce output audio generated by speakers in the output zone. |
| US10262649B1 |
Noise cancellation device and noise cancellation method
A noise cancellation device includes a voice receiving module, a distance measuring module, a noise cancellation module and a speaker module. The voice receiving module is configured to receive a noise. The distance measuring module is configured to send a distance measuring signal to an object, and calculate distance information of the object according to a reflected distance measuring signal reflected by the object. The noise cancellation module is connected to the voice receiving module and the distance measuring module, and is configured to generate a reverse phase signal of the noise according to the noise. The speaker module is connected to the noise cancellation module, and is configured to generate an anti-noise according the reverse phase signal, and sound the anti-noise according to the distance information. |
| US10262637B1 |
Electronic keyboard alignment tool and method of use
A musical instrument keyboard alignment tool comprises a central member having defined therein a slot dimensioned to receive a key stop member of an electronic musical instrument keyboard, at least one handle extending from the central member, and an elongate foot extending from the central member. A distance between the bottom of the slot to the bottom surface of the foot corresponds to a calibration distance from the bottom of a key stop to a reference portion of the key bed of a keyboard. The described tool and methods of use significantly reduces the time required to perform a complete key stop alignment of an electronic musical instrument keyboard. |
| US10262636B2 |
Techniques for magnetically mounting a percussion instrument to a cymbal and related systems and methods
According to some aspects, a cymbal system is provided comprising a cymbal, and a percussion instrument magnetically coupled to the cymbal, said magnetic coupling between the percussion instrument and the cymbal provided at least in part by at least one first magnetic component disposed on a lower side of the cymbal, and at least one second magnetic component disposed on an upper side of the cymbal and attached to the percussion instrument, the at least one first magnetic component and at least one second magnetic component being coupled to the cymbal, at least in part, by a magnetic force of attraction between the at least one first magnetic component and the at least one second magnetic component that acts through the cymbal. |
| US10262633B2 |
String instrument having unitary neck support and fingerboard brace
Embodiments of the present disclosure relates to a string instrument, such as a guitar, having a neck support-fingerboard brace unit. The neck support-fingerboard brace unit is formed as a unitary unit or formed by fixedly attaching a neck support to a fingerboard brace before attaching the fingerboard brace to a guitar top. The solid connection between the neck support and the fingerboard brace allows the fingerboard brace, which rests on a guitar side, to provide support to the guitar neck, thus, reducing deformation in the guitar neck and the fret board. |
| US10262632B2 |
Providing output surfaces for display in data processing systems
A data processing system 1 comprises a display controller operable to provide to a display a compressed version of an output surface to be displayed that has been compressed using a lossy compression scheme, and one or more processing stages operable to provide a surface or surfaces that are to be used when forming an output surface to be displayed. At least one of the one or more processing stages is operable to output one or more regions of the surface or surfaces that it provides to be used when forming an output surface to be displayed in a compressed form using a lossy compression scheme. |
| US10262631B1 |
Large scale highly detailed model review using augmented reality
In an example embodiment, a technique is provided for model review using augmented reality. An augmented reality device obtains tiles from a remote computing device for an overview resolution, and augments the model at the overview resolution and an overview view size into a physical environment at a data location. The augmented reality device displays the model augmented into the physical environment to a user disposed at a view location. In response to input requesting a change to the new resolution, the augmented reality device obtains additional tiles from the remote computing device for the new resolution, augments the model at the new resolution and a new view size into the physical environment, and displays the model augmented into the physical environment to the user disposed at the view location. In response to input that requests navigation of the model, the augmented reality device changes at least one of the data location or the view location. The display of the model may be synchronized with a second user of a second augmented reality device disposed at a second view location. |
| US10262630B2 |
Information processing apparatus and control method
Provided is an information processing apparatus, including: a line-of-sight detection unit configured to detect lines of sight of a plurality of users with respect to presentation information; and an area determination unit configured to determine, on the basis of the detected lines of sight of the plurality of users, a shared area that is visually recognized by the plurality of users to share information and a confidential area that is not visually recognized by another user to keep information of each user confidential. |
| US10262626B2 |
Electronic interactive system and setting method thereof
An electronic interactive system and a setting method thereof. The electronic interactive system includes a wireless transmission unit respectively connected with an electronic terminal device and an electronic whiteboard, where the wireless transmission unit is configured to transmit data signals from the electronic terminal device to the electronic whiteboard in a wireless form and transmit touch signals from the electronic whiteboard to the electronic terminal device in the wireless form. |
| US10262624B2 |
Separating a compressed stream into multiple streams
Embodiments of the invention generally provide a display device that includes a controller that is communicatively coupled between a display source and source drivers. The controller and source drivers include respective decompression engines that can decompress the compressed data received from the display source. Instead of sending all of the compressed data to the source drivers, the controller evaluates the uncompressed data and identifies what portion of the compressed data corresponds to each of the source drivers. Moreover, the controller may determine a decompression engine state that corresponds to each portion of the compressed data. The saved engine state is transmitted to the source drivers which then initialize their decompression engines using the engine states. |
| US10262617B2 |
Gate driving circuit and driving method thereof, display substrate, and display device
The present invention is related to a gate driving circuit for a display device. The gate driving circuit may comprise x stages of driving shift register units connected in series. Each of the driving shift register units may comprise an input terminal, an output terminal, and a reset terminal. The input terminal may comprise a first input port and a second input port. A row of pixel units driven by the driving shift register unit of the m-th stage may have the same polarity distribution as a row of pixel units driven by the driving shift register unit of the (m−N)-th stage. N is an integer greater than 1. m is an integer and N+1 |
| US10262616B2 |
Display device and drive method therefor
A still row discrimination unit 15 discriminates whether data of one row included in a video signal D1 is a still row. A scanning line drive circuit 13 applies a non-selection voltage to scanning lines GL1 to GLm corresponding to the still row. A data line drive circuit 14 does not apply data voltages to data lines SL1 to SLn when discriminated as the still row. A similar structure may be applied to a display device in which pixel circuits are divided into a plurality of blocks in a row direction and the pixel circuits in a same block among the pixel circuits in each row are connected to each scanning line. With this, it is possible to provide a display device which can reduce power consumption even when a part of a display image changes. |
| US10262614B2 |
Scan driving circuit, driving circuit and display device
The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally. |
| US10262613B2 |
Gate driver on array circuit and LCD panel
The present disclosure provides a gate driver on array (GOA) circuit. A low level signal source is used to output a low level signal, a first high level signal source is used to output a first high level signal, and the second high level signal source is used to output the second high level signal. A cascade signal latch module is used to latch a cascade signal of a current grade. A gate driving signal generating module generates a preparation gate driving signal of the current grade. A gate driving signal outputting module is used to output a gate driving signal of the current grade. |
| US10262612B2 |
Scan compensation method and scan compensation circuit of gate driver
The present disclosure provides a scan compensation method and a scan compensation circuit of a gate driver. The scan compensation method comprises: when the gate driver switching from first scanning mode to second scanning mode or from second scanning mode to first scanning mode, performing a first operation to a clock signal and a first compensation signal of the gate driver, and performing a second operation to the obtained signals and a second compensation signal, wherein the first scanning mode is a sequential scan mode, the second scanning mode is non-sequential scan mode. |
| US10262609B2 |
Scanning driving circuit with pull-down maintain module and liquid crystal display apparatus with the scanning driving circuit
The disclosure discloses a scanning driving circuit and a liquid crystal display apparatus, the scanning driving circuit including a first driving circuit and a second driving circuit, each of the first driving circuit and the second driving circuit including a number of driving units in cascade connections, and each of the driving units including: a forward and reverse scanning module to output a forward scanning signal, a reverse scanning signal and an optional signal; a pull-down maintain module connected to the forward and reverse scanning module and to receive the optional signal from the forward and reverse scanning module and output a pull down signal according to the optional signal; a control module connected to the forward and reverse scanning module and the pull-down maintain module; a reset module connected to the pull-down maintain module and the control module to reset the electrical potential of the scanning line. |
| US10262606B2 |
Display device
According to one embodiment, a display device includes a pair of substrates including a display area in which pixels are arranged, pixel electrodes and memories provided in the pixels, signal lines supplied with digital signals, switching elements connecting the memories and the signal lines, scanning lines supplied with scanning signals, a first driver unit, and a second driver unit. The first driver unit is provided in a peripheral area around the display area, and supplies the digital signal to the signal line. The second driver unit is provided in the peripheral area, and supplies the scanning signal to the scanning line. In the display device, at least a part of the first driver unit is provided between the display area and the second driver unit. |
| US10262604B2 |
Control device, display device, and control method for display device
A host control section (30) is a control device for a display device (1). The host control section (30) includes an image determining section (35) for calculating a density of pixels, which have intermediate grayscale levels (i.e., grayscale levels of a first range), among a plurality of pixels in an image; and a driving changing section (36) for changing a refresh rate of the display device (1) in accordance with the density which has been calculated. |
| US10262602B2 |
Array substrate having shift register unit and display device
An array substrate and a display device are disclosed. The array substrate (01) comprises a gate electrode driving circuit (10), the gate electrode driving circuit (10) includes at least two stages of shift register units (SR1-SRn), and each stage of the shift register units (SR1-SRn) is connected with a row of gate lines (Gate1-Gaten). The shift register units (SR1-SRn) include driving modules (D1-Dn) and logical modules (L1-Ln); the driving modules (D1-Dn) include a portion located in a display region (100) of the array substrate. The array substrate can solve a problem that a larger size of a driving TFT in a gate driver on array (GOA) circuit is not conducive to a narrow frame design trend of a display panel. |
| US10262593B2 |
Light emitting drive circuit and organic light emitting display
The present disclosure provides a light emitting drive circuit and an organic light emitting display. The circuit includes: the reset memory module for resetting the driving module and for generating and storing a threshold offset voltage corresponding to the driving module; the driving module is used for generating a light emission drive voltage in a light emission phase in accordance with a power supply positive voltage, a stored threshold compensation voltage, and a light emission control signal; the light emitting module is configured to emit light, and the light emission driving voltage is a difference between the power supply positive voltage and the data voltage. The driving voltage (or drive current) of the light emission is independent of the threshold voltage for driving the thin film transistor. This eliminates the problem that the threshold voltage drift of the driving thin film transistor causes the screen display to be poor. |
| US10262591B2 |
Circuit for driving amole pixel
A circuit for driving an AMOLED pixel is disclosed. The circuit includes: a first transistor, a second transistor, and a grayscale storage capacitor, wherein a connecting path is arranged between an input end of a data line and an input end of a scanning line, by which an afterimage is eliminated when an AMOLED display device is turned off in a predetermined turned-off sequence of external control signals and voltages on each portion of the circuit. |
| US10262590B2 |
Active matrix substrate and display panel
An array substrate includes pixels PX, source wires, a first column circuit portion connected to the source wires, first column connection wires connected to the first column circuit portion, a second column circuit portion, panel-side input terminal portions, second column connection wires, and diagonally arrayed circuit portions. The second column circuit portion includes unit circuits connected to the first column connection wires. Some of the panel-side input terminal portions are displaced in the row direction with respect to the corresponding unit circuits. The second column connection wires include second diagonally extending portions extending from the unit circuits to the panel-side input terminal portions. The diagonally arrayed circuit portions include the unit circuits disposed such that the closer to the middle of the second circuit portion with respect to the row direction, the closer to the first column circuit portion with respect to the column direction. |
| US10262588B2 |
Pixel, display device including the same, and driving method thereof
Provided are a pixel, a display device including the same, and a driving method thereof. A pixel includes: an organic light-emitting diode including an anode and a cathode, a first transistor configured to provide a driving current flowing through the organic light emission diode, a second transistor configured to provide data to a gate of the first transistor in response to a scan signal, a capacitor configured to maintain a difference between a voltage level of the data and a threshold voltage of the first transistor, and a third transistor configured to: sense a change of the threshold voltage of the first transistor in response to a sensing signal, and transfer a reference voltage to a node coupled to the anode when the sensing signal is enabled, wherein a level of the reference voltage is lower than a threshold voltage of the organic light-emitting diode. |
| US10262587B2 |
Method and system for driving an active matrix display circuit
A method and system for driving an active matrix display is provided. The system includes a drive circuit for a pixel having a light emitting device. The drive circuit includes a drive transistor for driving the light emitting device. The system includes a mechanism for adjusting the gate voltage of the drive transistor. |
| US10262584B2 |
Pixel circuit, method for driving the same, array substrate and display device
The pixel circuit comprises a driving sub-circuit, a controlling sub-circuit and a light-emitting sub-circuit. The light-emitting sub-circuit includes a first organic light-emitting element and a second organic light-emitting element. The first and second organic light-emitting elements are coupled to the driving sub-circuit respectively. The controlling sub-circuit is coupled to the driving sub-circuit so as to control the driving sub-circuit to drive the first and second organic light-emitting elements, so that at an identical display stage, one of the first and second organic light-emitting elements emits light in a forward bias state and the other does not emit light in a backward bias state, and at an adjacent display stage, the bias states are switched. |
| US10262583B2 |
Organic light-emitting diode display
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a data line disposed on a substrate and extended in a first direction, a power line disposed on the substrate and extended in the first direction, a scan signal line disposed on the substrate across the data line, an active layer formed over the substrate, wherein the active layer includes first to fourth regions, wherein the first and fourth regions are connected to each other through a connecting region, a first transistor including the active layer formed between the first region and the second region, a second transistor including the active layer formed between the third region and the fourth region, and wherein the active layer is extended from the first region, the organic light emitting diode is electrically coupled to the first transistor, and a storage capacitor including a first electrode and a second electrode formed over the first electrode, wherein the second electrode overlaps with at least of an area of the first electrode. The second electrode is extended to the connecting region and disposed between the active layer and a line extended in the first direction in the connecting area. |
| US10262579B2 |
Drive system and drive method of liquid crystal display
There provides a drive system for a liquid crystal display, which includes: a timing controller for generating a scanning start signal; a level shifter for boosting the generated scanning start signal and generating at least one clock signal according to the boosted scanning start signal; and a gate driver for scanning and driving gate lines according to the boosted scanning start signal and the generated clock signal. There also provides a drive method of a liquid crystal display. With the drive system and drive method of a liquid crystal display provided in the present invention, it can reduce the pins required by the timing controller and the level shifter, thus the packages of the timing controller and the level shifter get smaller, thereby reducing the package cost. |
| US10262578B2 |
Power supply circuit, circuit device, display device, and electronic apparatus
A power supply circuit includes: a regulator configured to receive a first power supply voltage and a third power supply voltage higher than the first power supply voltage and output a regulated voltage between the first power supply voltage and the third power supply voltage based on the third power supply voltage; and an output control circuit configured to select the first power supply voltage or the regulated voltage to output as a second power supply voltage. The output control circuit outputs the first power supply voltage as the second power supply voltage when the third power supply voltage is lower than a threshold voltage, whereas the output control circuit outputs the regulated voltage as the second power supply voltage when the third power supply voltage is higher than or equal to the threshold voltage. |
| US10262577B2 |
Scanning driver circuit and display device with the same
A scanning driver circuit includes N stage-connected GOA units. An Nth-stage GOA unit includes a pull-up part, a pull-up control part, a pull-down holding part, and a key pull-down part. The pull-up part is connected to an output terminal of an Nth stage gate signal. The pull-up control part is connected to the output terminal of the Nth stage gate signal. The pull-down holding part receives a first direct current voltage and a second direct current voltage. The key pull-down part connected to the Nth stage gate signal receives the first direct current voltage. The pull-down holding part is formed by a first pull-down holding circuit and a second pull-down holding circuit. The first pull-down holding circuit and the second pull-down holding circuit operate alternatively so that the output terminal of the Nth stage gate signal and the node can hold at a negative voltage level. |
| US10262576B2 |
Display device, control circuit and associated control method
A display device, a control circuit and associated control method are provided. The display device includes the control circuit and a display panel. The control circuit receives a plurality of source frames with a source frame rate. The control circuit generates a plurality of data signals and a plurality of gate signals based on the plurality of source frames. The display panel is electrically connected to the control circuit. The display panel displays the plurality of output frames according to the plurality of data signals and the plurality of gate signal. The plurality of output frames are displayed with one of a first refresh frame rate and a second refresh frame rate. The source frame rate is equivalent to the first refresh frame rate, and the source frame rate is greater than the second refresh frame rate. |