最新美国发明专利第2018-11-13期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US10128987B2	Scalable receive window auto-tuning Examples of the disclosure dynamically scale receive window auto-tuning. Tuning data is obtained, including the number of bytes in a receive buffer and the distribution of receive packets over time. Aspects of the disclosure use this tuning data to determine rates at which one or more applications on the receiving computer are consuming data and adjust or maintain the receive buffer accordingly in a dynamic manner to scale a receive window to current conditions.
US10128986B2	Method and apparatus for controlling soft buffer for TDD-FDD carrier aggregation Provided is a method and apparatus for controlling soft buffer for TDD-FDD carrier aggregation. The method includes: establishing a Radio Resource Control (RRC) connection with a base station through a first serving cell, the first serving cell supporting a Time Division Duplex (TDD) mode; receiving an RRC message from the base station through the first serving cell, the RRC message comprising carrier aggregation (CA) configuration information, the CA configuration information comprising information of a second serving cell supporting a Frequency Division Duplex (FDD) mode; determining a maximum number of DL HARQ processes for the second serving cell, the maximum number of DL HARQ processes for the second serving cell being differently determined according to a DL reference timing; and storing soft channel bits for a received transport block (TB) based on the determined maximum number of DL HARQ processes for the second serving cell.
US10128978B2	Receiver, method for cancelling interference thereof and transmitter for the same Provided is a method for eliminating an interference operating on a receiver of a transmitter in a communications system, which includes transmitting at least one user signal; changing user phase information to be separated from interference phase information by a preset difference, when receiving the user phase information of the user signal and the interference phase information of an interference signal from at least one receiver; and transmitting at least one other user signal according to the changed user phase information.
US10128977B2	Transmitting a first and a second channel quality information between two network elements It is described a method for transmitting channel quality information between a second network element and a first network element. The method comprises includes (a) dividing a range of possible radio channel qualities between the two network elements into a fixed number of quality classes, (b) measuring the quality of a radio channel between the two network elements, (c) selecting one quality class out of the fixed number of quality classes based on the measured quality of the radio channel, (d) transmitting from the second network element to the first network element a first channel quality information being indicative for the selected quality class, and (e) transmitting from the second network element to the first network element a second channel quality information being indicative for the measured quality within the limits of the selected quality class. It is further described the first and the second network element, which in conjugation with each other are adapted to carry out the described method.
US10128976B2	Radio wave jamming system, radio wave jamming apparatus, and radio wave jamming method A radio wave jamming system (1) comprises a plurality of radio transmitters (10) that are adapted to transmit respective jamming signals (11) including substantially the same frequency. The plurality of radio transmitters (10) are further adapted to temporally change at least one of the transmission phases of the jamming signals (11), which are to be transmitted from the plurality of radio transmitters (10), so as to temporally change the phase differences among the jamming signals (11) when the jamming signals (11) transmitted from the plurality of radio transmitters (10) arrive at a particular site (50). Thus, for example, a radio wave jamming system that can be constituted by small-output radio devices can be provided.
US10128972B2	Method for converting wavelength of optical signal in passive optical network According to the present disclosure, a controlling unit arbitrarily determines a current set temperature of a temperature setting unit to cause a light generating unit connected to the temperature setting unit to generate an optical signal having a wavelength according to the current set temperature, thereby making it possible to effectively reduce a wavelength overlap phenomenon that may occur when a plurality of R-ONUs in a passive optical network simultaneously transmit the optical signals.
US10128971B2	Multi wavelength routing plane optical architecture Example embodiments of the present invention relate to a multi wavelength-routing-plane optical architecture. Example embodiments include a Reconfigurable Optical Add Drop Multiplexer (ROADM) supporting a multi wavelength-routing-plane optical architecture, and optical networks supporting a multi wavelength-routing-plane optical architecture.
US10128968B2	Satellite downlink signal performance monitoring at identified antennas A satellite monitoring system is disclosed. The system may monitor various downlink signals of various satellites. In response to user queries, the system may provide diagnostic and other data related to the characteristics of the downlink signals. In this manner, an independent verification and validation of downlink signal characteristics may be performed. Moreover, the system may take various actions in response to detected anomalies related to the characteristics of the downlink signals, such as automatically generating alerts for users and/or activating an uplink facility, such as a backup uplink facility and/or providing control signals to user devices, such as antenna controllers, to reorient user antennas in response to the characteristics of the downlink signals.
US10128961B2	Angular electrode An electrode having a first metallic plate; and a second metallic plate arranged at an angle of greater than 0° and less than 180° with respect to the first metallic plate.
US10128960B2	Estimation method for optical receiver and light source device A method for estimating characteristics of an optical receiver includes: a generating process, a monitoring process, a suppressing process, a guiding process and an estimating process. The generating process generates a modulated optical signal based on an oscillation signal. The monitoring process monitors an optical spectrum of the modulated optical signal or a spectrum of an electric signal obtained by performing optical-to-electrical conversion on the modulated optical signal. The suppressing process suppresses a modulation component of an upper sideband or a lower sideband of the modulated optical signal based on the optical spectrum of the modulated optical signal or the spectrum of the electric signal. The guiding process guides the modulated optical signal in which the modulation component is suppressed to the optical receiver. The estimating process estimates the characteristics of the optical receiver based on an output signal of the optical receiver.
US10128959B1	Tap centerer method and structure for coherent optical receiver A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.
US10128956B2	Calibration of pluggable optical module An optical communications apparatus comprising a host (100) and an optical module (200) comprising a Mach-Zehnder modulator (202), MZM, wherein the optical module is removably connected to the host via a connection path, the optical communications apparatus comprising: a signal generator (101) at the host, configured to generate a plurality of calibration signals at a plurality of frequencies; a host interface (102) configured to transmit the calibration signals to the optical module via the connection path; a module interface (201) configured to receive the transmitted calibration signals; wherein the MZM is configured to use the calibration signals to modulate a laser light source (206) and biased to a point at which average output power is proportional to the output modulated signal; an optical detector configured to measure an average magnitude of an output of the MZM when each of the calibration signals is used to modulate the laser light source; one of a host calibration unit (103) and a module calibration unit (203), configured to determine a magnitude response of the connection path based on the measured average magnitudes and magnitudes of the respective calibration signals, and further configured to determine a pre-emphasis characteristic based on the magnitude response, the pre-emphasis characteristic for application to signals transmitted by the optical transmitter in use.
US10128953B2	High-speed pluggable optical transceivers with advanced functionality An optical transceiver configured to operate in a host device includes an electrical interface communicatively coupled to the host device to interface electrically with the host device, wherein the optical transceiver is compliant with a Multi-Source Agreement (MSA) which is supported by the host device; optical transceiver components communicatively coupled to the electrical interface, wherein the optical transceiver components are configured to optically interface signals with a second optical transceiver to form an optical link; and electronic dispersion compensation circuitry communicatively coupled to the optical transceiver components and configured to electronically compensate for optical fiber chromatic and/or polarization mode dispersion associated with the optical link, separate and independent from the host device.
US10128945B2	MIMO visible light communication system receiving device A receiving device for a multi-input multi-output (MIMO) visible light communication system includes a collimation unit, a metal thin film, a transparent substrate and a receiving unit. The receiving device performs receiving by using optical components, and uses the metal thin film as a main receiving component, which plays a role of filtering and enhanced transmission, and equals to implementing a function of filtering and signal amplification by using electronic components, but overcomes the nonlinear effect of the electronic components, thereby solving the problem of waveform distortion in receiving.
US10128942B2	Method of transmitting an optical data signal via a fiber optical medium in opposite directions at the same carrier wavelength The described method relates to fiber optic communication engineering and can be used in fiber optic communication systems for creating several independent communication channels. One object of the method is to increase the utilization efficiency of the optic fibers by using optical signals transmitted in opposite directions at one wavelength.
US10128941B2	Dimming control for orthogonal frequency division multiplexing-based visible light communication A method of dimming control for orthogonal frequency division multiplexing (OFDM)-based visible light communication (VLC). The method includes transmitting, by an optical communication device, an optical signal using OFDM with all active sub-carriers when a first dimming level is observed, transmitting, by the optical communication device, the optical signal using OFDM with a first subset of active sub-carriers and without sub-carrier index modulation (SIM) when a second dimming level is observed, wherein the second dimming level is less than the first dimming level; and transmitting, by the optical communication device, the optical signal using OFDM with a second subset of active sub-carriers and with SIM when a third dimming level is observed, wherein the second subset of the active sub-carriers is smaller than the first subset of the active sub-carriers, and wherein the third dimming level is less than the second dimming level.
US10128937B2	Data management method and data management system A management device is connected with a plurality of relay devices, and the relay devices store data collected by a device. The management device registers, when a connection notification is received from one of the relay devices, relay device identification information, which identifies the relay device, of the relay device serving as the request destination when the data is acquired, sends a data acquisition request to the specified relay device, and sends, to one of the relay devices, relay device identification information of the target relay device targeted for deletion. The plurality of the relay devices associates, when the identification information targeted for the deletion is received, inquiry destination information specifying the target relay device with the data, and performs, when the data acquisition request is received, response control of the data on the basis of the determination of whether the inquiry destination information is associated with the data.
US10128935B2	Partial downlink repeater apparatus and methods useful in conjunction therewith For use with a cellular communication network having a base station transmitting downlink signals received by mobile device/s: a downlink signal reception enhancement system including partial repeater apparatus enhancing quality of reception of at least a portion of downlink signal/s by mobile device/s, the partial repeater apparatus including a downlink receiver receiving at least a portion of downlink signal/s arriving from the base station; a controller including a critical region selector, selecting only a portion of at least one individual downlink signal; and a partial transmitter generating signal/s by regenerating, according to characteristic/s of at least one of a downlink signal and the mobile device, at least the portion selected by the critical region selector, and to transmit a signal including at least the regenerated portion plus less than all of the individual downlink signal.
US10128934B2	Method and repeater for broadband distribution Aspects of the subject disclosure may include, for example, a method that includes extracting first channel signals from first guided electromagnetic waves bound to an outer surface of a transmission medium of a guided wave communication system; amplifying the first channel signals to generate amplified first channel signals in accordance with a phase correction; selecting one or more of the amplified first channel signals to wirelessly transmit to at least one client device via an antenna; and guiding the amplified first channel signals to the transmission medium of the guided wave communication system to propagate as second guided electromagnetic waves, wherein the phase correction aligns a phase of the second guided electromagnetic waves to add in-phase with a residual portion of the first guided electromagnetic waves that continues propagation along the transmission medium.
US10128923B2	Method and device for configuring waveform at transmitter Method and device for configuring a waveform at a transmitter are provided. The method includes: receiving at least one input signal, each input signal corresponding to a subcarrier spacing setting; performing IDFT pre-processing to each input signal, the IDFT pre-processing including DFT pre-coding or offset modulation; performing IDFT to each input signal which is subjected to the IDFT pre-processing, the IDFT including an IDFT with parameters including resource mapping and a corresponding IDFT size; performing IDFT post-processing to each input signal which is subjected to the IDFT to obtain at least one output signal, the IDFT post-processing including cyclic extension and time-domain windowing; adding the at least one output signal in time domain; and transmitting the added signal through a corresponding antenna port. Waveforms are configured flexibly according to practical scenarios at the transmitter to determine a most suitable waveform for current scenario, which meets practical requirements of 5G technology.
US10128921B2	Multi-user multiple-input multiple-output (MU-MIMO) operation and user selection System and method of Multi-User Multiple-Input Multiple-Output (MU-MIMO) Beamforming communication. An MU-MIMO BF training session is used to train all the responders in a user group in relation to an initiator having multiple antenna arrays. Accordingly, suitable TX-RX sector pairs are selected based on the training results, and the user group is arranged into subsets such that the initiator can transmit data to the responders in one subset simultaneously by using mutually orthogonal BF waveforms. Prior to the MU-MIMO BF training session, the initiator can select TX sectors of the TX antennas and responders for the training session based on results from a prior or preliminary SISO BF training.
US10128913B2	Method and circuit of an actively transmitting tag A circuit of an actively transmitting tag includes an antenna, a digitizer, a voltage-controlled oscillator (VCO), an output amplifier, a phase-displacement detector, and a regulator. The input of the digitizer connects to the antenna. The outputs of the digitizer and the output amplifier are connected to the input terminals of the phase-displacement detector. The output amplifier connects the output of the VCO to the antenna and the regulator connects the output of the phase-displacement detector to the VCO.
US10128906B2	Power line signal coupler A main power line (+ and − lines) is coupled to a power supply, for example a car battery, grounded to a vehicle chassis. Positive and negative main power lines are coupled to a power line gateway module, and spliced to carry power for a segment, until receiving, by splices, RF power line communcations. The main power lines, now carrying power and RF power line communications are then coupled to remote modules. RF power line communication carries signal from the power line gateway module to a impedance matching network or a transformer are used to match impedances.
US10128905B2	Method and system for impulsive noise classification and mitigation A system for classifying impulsive noise on a communications signal comprises an impulse signal generator, an integrator, a first comparator, and an impulse peak detector. The impulse signal generator receives a communications signal that includes impulsive noise and is configured to provide an impulse signal that includes just the impulsive noise. The integrator receives the impulse signal and integrates the impulse signal to determine the power of the impulse signal. The first comparator receives the impulse signal and is configured to compare the impulse signal to a first reference signal and indicate the time during which the value of the impulse signal is greater than the value of the first reference signal. The impulse peak detector receives the impulse signal and is configured to process the impulse signal, compare the processed signal to a second reference signal, and detect the peak value of the impulse signal.
US10128904B2	Low-latency bi-directional repeater A repeater circuit is disclosed. The repeater circuit is coupled to a transmission line driven by a first transmitter circuit and configured to detect a signal transition from a first voltage level to a second voltage level at a first position on the transmission line. The repeater circuit then reinforces the signal transition from the second voltage level to a third voltage level at the first position on the transmission line without interrupting a current through the transmission line.
US10128893B2	Method and system for planar, multi-function, multi-power sourced, long battery life radio communication appliance A multifunction electronic key is provided with at least one wireless communication interface that can function as an access control key to unlock an electronic lock when the key is placed in proximity of an electronic lock that has been previously configured to allow temporal access to the said electronic key, and at least one of the following functions: a) Measure the electric field experienced by the device, process it and optionally send it to a second wireless device; b) A physical button to communicate a distress signal to a second wireless device, in response to which the second wireless device estimates the position of the electronic key and generates a system alarm indicating the identity of the electronic key that generated the alarm and its position estimate; c) Measures the device's motion, process it and optionally send it to a second wireless device; d) One or two way audio communication via the wireless link; e) Measures ionizing radiation.
US10128892B1	Generic SerDes tuning module Systems and methods of tuning SerDes links between transmitter SerDes channels and receiver SerDes channels are described. Generally, the SerDes links may be tuned using a generic SerDes tuner implementation and a tuning algorithm. The tuning algorithm may have a first tuner interface specific to the transmitter SerDes device and a second tuner interface specific to the receiver SerDes device. The tuning algorithm may define a sequence of operations from the first tuner interface and the second tuner interface that when executed result in calibration of the SerDes link.
US10128891B2	Mobile phone / tablet shell with finger grasping ring A mobile phone/tablet case with finger grasping ring comprises a box for receiving a body of the mobile phone or tablet, a finger grasping ring is provided on the box bottom; the finger grasping ring is provided a multiple of finger holes which are enterable by fingers. Another embodiment the finger grasping ring has an elastic valve and an elastic belt; the elastic valve has one side connected with the elastic bottom together and other sides are separated from the bottom; the elastic belt has two opposite ends connected with the elastic valve together and other two opposite sides separated from the elastic valve, the elastic belt is parallel to long sides of the box. When the middle finger of user enter the gap between the belt and valve, the case with a mobile phone/tablet is grasped without thumb.
US10128888B2	Tablet computer case A device case for a portable electronic device includes a device stand attached to a hack surface of the case housing. The device stand is formed by an inner stand and outer stand connected by releasable hinged connections to the back surface of the case housing. A track is formed on a surface of the outer stand that the inner stand slides along. A locking portion such as a cavity or channel on the outer stand locks the inner stand into an open position with respect to the outer stand. At least a portion of the outer stand is flexible such that applying a threshold pressure to the device case causes the portion of the outer stand to flex such that the locking portion releases the inner and outer stand from the open position without damaging the stand.
US10128886B1	Radio frequency (RF) receivers and methods to spread spectral energy of spurious outputs Radio frequency (RF) receivers and methods to spread spectral energy of spurious responses of mixers over a frequency band are disclosed. For example, a receiver includes first and second mixers, and first and second variable frequency oscillators (VFOs). The first mixer is configured to receive an RF signal and provide an intermediate frequency (IF) signal. The second mixer is coupled with the first mixer and configured to receive the IF signal and provide a baseband signal. The first VFO is coupled with the first mixer and configured to provide a first angle modulated LO signal. The second VFO is coupled with the second mixer and configured to provide a second angle modulated LO signal. The first and second mixers provide a stable frequency downconversion.
US10128884B2	Antenna interface circuit, data card, and antenna connection control method and apparatus A circuit includes a main connector and a single-pole double-throw switch. A common contact of the main connector is used as a port of a main receiver, and a normally-closed contact of the main connector is used as a port of a main antenna. Furthermore, a normally-open contact of the main connector is used as a port of an external antenna, and a common contact of the single-pole double-throw switch is used as a port of a diversity receiver. Additionally, a normally-closed contact of the single-pole double-throw switch is used as port of a diversity antenna, and a normally-open contact of the single-pole double-throw switch is connected to the normally-closed contact of the main connector.
US10128881B2	Time to digital converter, radio communication device, and radio communication method A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.
US10128879B2	Enhanced receive sensitivity for concurrent communications A system using multiple communication technologies for concurrent communication is disclosed. The system includes a loopback receiver, a receiver, and a noise remover component. The loopback receiver is configured to obtain a coupled signal and generate a noise signal from the coupled signal. The noise signal includes direct transmission noise. The receiver is configured to receive a chain receive signal and to provide a receive signal therefrom. The noise remover component is configured to generate a wanted receive signal from the noise signal and the receive signal.
US10128877B2	Network assisted interference cancellation and suppression, methods and devices for controlling the same The disclosure discloses Network Assisted Interference Cancellation and Suppression (NAICS), methods and devices for controlling the same, which are configured to reduce processing complexity of User Equipment (UE) in NAICS under the condition of no excessive high-layer signalling overhead and no waste of a Carrier Aggregation (CA) capability of the UE in a CA scenario. The method for NAICS includes that: the UE receives an Interference Cancellation (IC) indication message sent by a Node B, and the IC indication message includes an Identifier (ID) of a Component Carrier (CC) which is targeted when the UE performs NAICS. The CC is a CC which performs CA transmission on the UE; and the UE performs NAICS on the CC according to the IC indication message.
US10128876B2	Efficient output power combining digital microwave radio system A digital microwave radio system includes a splitter that splits a common baseband input into two baseband outputs, first and second transmitters, each transmitter electrically connected to a baseband output of the splitter via a mixer, a common local oscillator electrically connected to the mixer of the first transmitter and the mixer of the second transmitter via an adjustable phase shifter, respectively, and a combiner. The common local oscillator is configured to up-convert each baseband output into a radio-frequency signal using a corresponding mixer. The combiner combines the two radio-frequency signals into a 0-degree phase-shift output and a 180-degree phase-shift output, respectively. A phase error control loop adjusts the phase shifter to minimize the 180-degree phase-shift radio-frequency output. A combiner gain control loop adjusts the output power level of the two transmitters in accordance with an actual power detector reading at the 0-degree phase-shift radio-frequency output.
US10128875B1	Methods and system of a digital transmitter with reduced quantization noise A digital transmitter includes baseband interfaces to generate digital baseband signals with baseband frequencies, digital-upconverting stages to upconvert the baseband frequencies to first radio frequencies having a predetermined frequency range, a M-Band ΔΣM modulator to modulate the up-stage signals based on noise shaping and noise quantization processes, delay registers to align phases of the modulated up-stage signals, a noise canceler to generate noise canceling signals with a converted polarity, a Switch Mode Power Amplifier to amplify the phase aligned modulated up-stage signals up to a predetermined power level, a linear power amplifier to amplify the noise canceling signals up to the predetermined power level, a power combiner to combine to generate transmitting signals by combining the amplified phase aligned modulated up-stage signals and the amplified noise canceling signals, and an antenna to transmit the transmitting signals.
US10128872B2	Enabling radio frequency multiplexing in a wireless system A communication device comprises a set of filters that are selectively coupled to different groups of front end ports and an antenna port to form a diplexer, a single filter or a no filter connection for transmission and reception of different data signals. A processor operates to selectively determine or combine filters and couple them to the front end ports and the antenna port based on an operational mode and a frequency separation of signals operating in different frequency ranges of different operating bands. The operational mode can alter between a carrier aggregation mode, in which more than one operating band is aggregated during transmission or reception, and a non-carrier aggregation mode, in which only one filter, no filters or the diplexer is bypassed. The insertion loss of the transmissions and receptions can also be actively decreased.
US10128868B1	Efficient dictionary for lossless compression Various systems and methods for lossless data compression are described herein. A process for lossless data compression includes hashing an input byte stream to produce a hash key; identifying a set of dictionary entries in a hash table using the hash key, the hash key associated with a word from a compact dictionary; identifying a set of candidate words from the compact dictionary based on the identified set of dictionary entries, the compact dictionary being a subset of a standard dictionary; determining a best match of the set of candidate words with the input byte stream; and encoding the best match of the set of candidate words as a compressed output of the input byte stream, the encoding including an operation to determine an index into the standard dictionary of the best match and using the index in the encoding operation.
US10128864B2	Non-linear converter to linearize the non-linear output of measurement devices A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.
US10128863B2	Resistor-based configuration system A configuration circuit for obtaining a digital code includes a controller circuit that generates a plurality of multibit control words. A digitally controlled current source circuit receives a multibit control word generated by the controller circuit. The digitally controlled current source circuit generates an output current that corresponds to the multibit control word in accordance with a predetermined output curve. A test voltage node receives the output current, and a test voltage develops in response to the output current. A reference voltage node develops a reference voltage, the level of which is independent of the multibit control word. A voltage comparison circuit (i) receives the test voltage and the reference voltage, (ii) compares the two voltages to produce a comparison result and (iii) sends the comparison result to the controller circuit. The digital code is obtained by the configuration circuit using the comparison result and the multibit control word.
US10128854B2	Oscillation circuit, electronic apparatus, and moving object An oscillation circuit includes an oscillating circuit adapted to oscillate a resonator element having a frequency-temperature characteristic, and a frequency adjustment circuit having a capacitance circuit connected to the oscillating circuit and adapted to adjust an oscillation frequency of the oscillating circuit, and a logic circuit, to which a signal having been output from the oscillating circuit is input, and which adjusts a frequency of the signal, and the frequency adjustment circuit compensates the frequency-temperature characteristic using at least the capacitance circuit in a predetermined temperature range, and compensates the frequency-temperature characteristic using the logic circuit alone outside the predetermined temperature range.
US10128848B2	Level shifter A level shifter that includes: a power supply system current source; a second transistor having a third main electrode that is connected to an input voltage signal terminal, a fourth main electrode that is connected to an output voltage signal terminal, and a second control electrode that is connected to a third power supply voltage having a voltage that is lower than a first power supply voltage and higher than a second power supply voltage; a second resistor; and a third transistor having a fifth main electrode that is connected to the second end of the second resistor, a sixth main electrode that is connected to the second power supply voltage, and a third control electrode that is connected to a first control electrode of a first transistor of the power supply system current source.
US10128846B2	Apparatus and method for data level shifting with boost assisted inputs for high speed and low voltage applications The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.
US10128842B1	Output impedance calibration for signaling Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.
US10128833B2	Millivolt power harvesting FET controller Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives an voltage existing across the second and third terminals of the transistor, generates an isolated voltage and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.
US10128832B2	Converter system, driving circuit and method for semiconductor switch The present application discloses a converter system, a driving circuit and a driving method for a semiconductor switch. The driving circuit includes a driving unit, a sampling unit and a selection unit. A plurality of turn-off driving units with different turn-off parameters is provided in the driving unit, and a turn-off driving unit having a turn-off parameter adaptive to the working state of the semiconductor switch is selected according to the working state of the semiconductor switch so as to turn off the semiconductor switch.
US10128830B2	Track and hold circuit A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.
US10128829B2	Composite semiconductor device Provided is a composite semiconductor device that has a low on-resistance and a high load-short-circuit resistance. In a composite semiconductor device (10) including a normally-on first FET (Q1) and a normally-off second FET (Q2) that are cascode-connected to each other. In a case where a voltage applied to a drain of the first FET (Q1) is 400 V, a relation of the following expression is satisfied: [ Math . ⁢ 1 ] RonQ ⁢ ⁢ 2  VTHQ ⁢ ⁢ 1  + 1 Id ⁢ ⁢ max ⁢ ⁢ 1 ≥ 1 Id ⁢ ⁢ max , where a time elapsed after short circuit T represents a time elapsed after a time at which a load connected to the composite semiconductor device (10) starts to be short-circuited, RonQ2 represents a value of an on-resistance of the second FET, VTHQ1 represents a threshold voltage of the first FET, Idmax1 represents a drain current of the first FET in a saturated state of the first FET when a gate voltage of the first FET is 0 V, and Idmax represents a drain current limited to an extent that breakdown of the first FET is prevented for the time elapsed after short circuit T of at least 2 μsec.
US10128828B2	Synchronous, internal clock edge alignment for integrated circuit testing A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.
US10128822B2	Integrated circuits for controlling slew rates of signals An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal. The integrated circuit further includes a first capacitor unit connected to the first output terminal and controlling a slew rate of the first output signal based on a first capacitance, a second capacitor unit connected to the second output terminal and controlling a slew rate of the second output signal based on a second capacitance, and a phase selection unit that receives the first signal and provides the first signal to the second capacitor unit, and that receives the second signal and provides the second signal to the first capacitor unit, so as to control the slew rates of the first and second output signals.
US10128819B2	High rejection wideband bandpass N-path filter Certain aspects of the present disclosure provide an N-path filter implemented using a generalized impedance converter (GIC) circuit. The GIC circuit is configured such that the N-path filter has a desired frequency response, which may include a wide passband with steeper rejection than a conventional N-path filter with only a single pole in each filter path. Certain aspects of the present disclosure provide an N-path filter having a frequency response with multiple concurrent passbands. In certain aspects, the N-path filter with multiple passbands is implemented using the GIC circuit. In other aspects, the N-path filter may include a bandpass response circuit where an inductance of the bandpass response circuit may be implemented using gyrators.
US10128816B2	High-frequency module In a high frequency module, in addition to a main transmission path in which a high-frequency signal propagates in first filter elements, a sub transmission path is defined by inductive coupling or capacitive coupling between a first inductor and a matching element or by inductive coupling between the first inductor and a second inductor. The sub transmission path has different amplitude characteristics and phase characteristics from those of the main transmission path depending on a degree of the inductive coupling or capacitive coupling, and transmission characteristics as a high-frequency module are adjustable by adjusting the amplitude characteristics and the phase characteristics of the sub transmission path.
US10128814B2	Guided surface acoustic wave device providing spurious mode rejection Embodiments of a Surface Acoustic Wave (SAW) device having a guided SAW structure that provides spurious mode suppression and methods of fabrication thereof are disclosed. In some embodiments, a SAW device includes a non-semiconductor support substrate, a piezoelectric layer on a surface of the non-semiconductor support substrate, and at least one interdigitated transducer on a surface of the piezoelectric layer opposite the non-semiconductor support substrate. A thickness of the piezoelectric layer, a SAW velocity of the piezoelectric layer, and an acoustic velocity of the non-semiconductor support substrate are such that a frequency of spurious modes above a resonance frequency of the SAW device is above a bulk wave cut-off frequency of the SAW device. In this manner, the spurious modes above the resonance frequency of the SAW device are suppressed.
US10128813B2	Bulk acoustic wave (BAW) resonator structure A bulk acoustic wave (BAW) resonator comprises: a first electrode; a second electrode comprising a plurality of sides, wherein at least one of the sides is a connection side; a piezoelectric layer disposed between the first and second electrodes, and an acoustic reflective element disposed beneath the first electrode, the second electrode and the piezoelectric layer, wherein an overlap of the reflective element, the first electrode, the second electrode, and the piezoelectric layer defines an active area of the acoustic resonator; a bridge adjacent to a termination of the active area of the BAW resonator; and a discontinuity disposed in the bridge.
US10128812B2	Electrical resonator An acoustic resonator comprises a substrate comprising a cavity. The electrical resonator comprises a resonator stack suspended over the cavity. The resonator stack comprises a first electrode; a second electrode; a piezoelectric layer; and a temperature compensating layer comprising borosilicate glass (BSG).
US10128810B2	Impedance matching structure of transmission line An impedance matching structure is disposed on a circuit board for matching an impedance of a transmission line for transmitting an electronic signal. The structure includes: at least two redundant conducting sections coupled to different points between an input terminal and an output terminal of the transmission line, wherein the redundant conducting sections are apart from one another, and a first terminal of each of the redundant conducting sections is coupled to the transmission line, while a second terminal of each of the redundant conducting sections is apart from the transmission line; and at least one grounded conducting section, each of which corresponds to one of the redundant conducting sections, and surrounds in separation from the corresponding redundant conducting section, wherein each of the at least two redundant conducting sections is disposed in a corresponding plating hole.
US10128809B2	Intelligent method and apparatus for spectral expansion of an input signal A method, and a corresponding apparatus, for processing an input signal comprise filtering the input signal to separate a passband frequency component of the input signal from a stopband frequency component of the input signal, and adjusting relative signal power values of the passband frequency component and the stopband frequency component of the input signal based at least in part on signal values of a number of samples associated with the input signal. In the case of audio signals, for example, such processing is used for spectral expansion of the input signal by enhancing the power of the stopband, or low and high frequencies, component with respect to the power of the passband component of the input signal. As a result, a better audio quality is achieved.
US10128796B2	Power amplification module and front end circuit A PA module (10) includes multiple amplifying elements (11a, 11b) and a variable filter circuit (12). The amplifying elements (11a, 11b) amplify a transmission signal in a frequency range including multiple communication bands and are cascade-connected to each other. The variable filter circuit (12) is connected between the amplifying elements (11a, 11b). The variable filter circuit (12) uses a transmission band corresponding to a used communication band selected from the multiple communication bands as a pass band and a reception band corresponding to the used communication band as an attenuation band.
US10128794B2	Feedback compensated oscillator An oscillator produces an oscillator output signal usable as a clock signal, otherwise as a frequency reference on an integrated circuit. The oscillator includes an RC network with a voltage-controlled element, such as a voltage-controlled resistor, voltage-controlled capacitor or a combination including a voltage-controlled resistor and voltage-controlled capacitor. Also, a tunable element having an adjustable resistance determined by a first static parameter is included in the RC network. The oscillator also includes a feedback circuit which can include a frequency-to-voltage converter. The feedback circuit generates a control signal for the voltage-controlled element. The feedback circuit includes a feedback reference circuit having a reference output determined by a second static parameter, and a loop amplifier responsive to the reference output and the oscillator output signal.
US10128789B2	Phantom electric motor system with parallel coils A method and apparatus for operating an electric motor is presented. A transmit magnetic field is received at a group of receive coils having a group of axes oriented substantially parallel to magnetic field lines from a transmit coil and having a group of resonant frequencies. A resonant frequency in the group of resonant frequencies is different from other receive coils in the group of receive coils. A receive magnetic field is generated at a receive coil in the group of receive coils having the resonant frequency when the transmit magnetic field has a selected frequency matching the resonant frequency. The receive magnetic field attracts a rotor in the electric motor.
US10128786B2	Electric vehicle electric drive system A vehicle may include an inverter, a motor coupled to the inverter, and a traction battery coupled to the inverter and having a terminal voltage equal to a rail voltage between rails of the inverter such that the rail voltage is unregulated. The vehicle may also include a voltage converter configured to reduce the terminal voltage below an intermediate bus voltage threshold on an intermediate bus, and an auxiliary converter configured to draw power from the intermediate bus to supply auxiliary loads.
US10128782B2	Variable frequency drive motor control Various embodiments include a variable frequency drive motor control apparatus. The apparatus includes a main controller having a first interface. A motor controller is coupled to and controls an electric motor, the motor controller further coupled to the main controller. A network switch is coupled to the main controller, the motor controller, and a remote controller over respective digital connections. The remote controller has a second interface. The network switches data between the first interface, the second interface, and the motor controller. A network coupler is coupled between a variable frequency drive controller and the motor controller.
US10128781B2	Variable electric motor system and electrically powered device This variable electric motor system comprises an electrically powered device and a planet gear transmission device. One of a sun gear shaft, a planet gear carrier shaft, and an internal gear carrier shaft of the planet gear transmission device constitutes an output shaft, another shaft constitutes a constant-speed input shaft, and the other shaft constitutes a variable-speed input shaft. The electrically powered device includes: a constant-speed electric motor including a constant-speed rotor that rotates about the axis, and that is connected to the constant-speed input shaft; and a variable-speed electric motor including a variable-speed rotor that rotates about the axis, and that is connected to the variable-speed input shaft. The variable-speed rotor has a shaft insertion hole formed therethrough in the axial direction, the shaft insertion hole having a cylindrical shape centered on the axis. The constant-speed rotor is inserted through the shaft insertion hole.
US10128780B2	Method and system for controlling the regenerative braking of a vehicle A method of and a system for controlling the regenerative braking of a vehicle includes initiating a regenerative braking mode in response to an initiating control input to an accelerator of the vehicle, the initiating control input comprising a reduction in the degree of actuation of the accelerator of the vehicle, modifying a level of regenerative braking in the regenerative braking mode in response to at least one of a further reduction in the degree of actuation of the accelerator, application of a brake of the vehicle, application of a clutch of the vehicle, and a change of gear of the vehicle, and maintaining a modified level of regenerative braking after the additional control input has been terminated.
US10128779B2	Induction motor long start protection Method and system for protecting induction motors from stalled start conditions provide a motor overload protection device that includes a stalled start detector capable of differentiating long start from stalled start conditions. This helps the motor overload protection device identify a stalled start condition right away and trip immediately rather than allowing the motor to continue drawing locked rotor current for the duration of the startup interval. Such a motor overload protection device may be used with any suitable multiphase induction motors, including two-phase motors, three phase motors, and the like. And because only the motor phase currents are used to detect the stalled start condition, the motor overload protection device disclosed herein does not require voltage phase shift information and/or motor speed measurements, thereby simplifying overall management of the motor.
US10128778B2	Energy harvester An energy harvester is provided. The energy harvester includes a housing, a permanent magnet that is disposed within the housing, and a mass body that has a relative position to the permanent magnet changed by a translational motion within the housing by vibration energy from the exterior and that is formed of a magnetic substance. Further, a piezoelectric body generates electricity while elastically supporting vibration with respect to the housing of the permanent magnet by the translational motion of the mass body and an induction coil is disposed within the housing to generate induction electricity based on the vibration of the permanent magnet.
US10128774B2	Inverter inrush current limiting A method and circuit arrangement is described for start-up and shut-down of high power DC to AC inverters which limits inrush current for capacitor charging, reduces input and output relay contact stress and discharges internal capacitors upon shut down. A preferred inrush limiting component has a higher resistance when hot than when cold, such as an incandescent filament lamp.
US10128773B2	Electric power conversion device and electric power system An electric power conversion device includes a first arm and a second arm each including converter cells. The converter cell of the first arm is a first converter cell having a full-bridge configuration including an energy storing element and semiconductor switching elements. The converter cell of the second arm is a second converter cell having a half-bridge configuration including an energy storing element and semiconductor switching elements. Thus, short-circuit current between DC terminals is suppressed.
US10128772B2	Load control device for high-efficiency loads A load control device for controlling power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting current through a gate terminal of the thyristor, a controllable switching circuit coupled between first and second main terminals of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct a pulse of current through the gate terminal to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct at least one other pulse of current through the gate terminal after the firing time until a transition time before an end of the half-cycle. The control circuit is configured to render the controllable switching circuit conductive to conduct current through the electrical load between approximately the transition time until approximately the end of the half-cycle.
US10128770B2	Converter and electric power conversion apparatus An adverse effect on a smoothing capacitor device caused by heat is suppressed. A flow path forming body 240 provided with protruding portions 411, 412 for attaching a capacitor board, a smoothing inductor device 130 mounted on the flow path forming body 240, and a capacitor board 170A on which a smoothing capacitor device 170 is implemented are provided, and the capacitor board 170A is fixed to the protruding portions 411, 412 for attaching the capacitor board, in such a manner that the smoothing capacitor device 170 is away from the flow path forming body 240.
US10128769B2	Remotely controllable modular power control device for power generation A power adjusting circuit includes a sensor configured to measure a voltage and a current of the first AC output by an inverter, an AC/DC/AC converter configured to receive the first AC output from the inverter, and a controller configured to convert the first AC output to a second AC output having a desired power factor.
US10128768B2	Meter/voltage regulator with volt-ampere reactive control positioned at customer site A method and system are provided for sourcing and sinking reactive power to an electric grid. The control system includes a terminal electrically coupled to a power source that originates from an electric utility grid. The terminal receives a grid alternating current having a real power component and a reactive power component. A power converter is electrically coupled to the terminal, the power converter includes an active rectifier that converts substantially all of the grid alternating current to a direct current and an energy storage device that stores energy supplied by the direct current. The active rectifier sources the reactive power component and the stored energy through the terminal to the electric utility grid. The power converter further includes an inverter that converts the direct current to a load alternating current having at least one of a load real power component and a load reactive power component.
US10128766B1	Method and apparatus for bi-directional switched mode power supply with fixed frequency operation Various embodiments relate to a method and circuit for maintaining zero voltage switching while having a fixed switching frequency, the method including switching on a first switch, on a primary side, at a beginning of a primary stroke of a time period at zero voltage and switching off the first switch at an end of the primary stroke, switching on a second switch, on a secondary side, at a beginning of a secondary stroke of a time period and switching off the second switch at an end of the secondary stoke of a time period and switching on a second switch at a beginning of a ringing period of the time period and switching off the second switch at an end of a bi-directional flyback action.
US10128765B2	Multi-stage power converter using pulse width modulator to convert sampled second-stage power parameters into digital pulse width modulation signals and control method thereof A multi-stage power converter includes a first-stage power conversion circuit, a second-stage power conversion circuit, a second-stage analogic sampler, a pulse width modulator, a first isolator, a pulse width analyzer and a control unit. The second-stage analogic sampler samples power parameter from the second-stage power conversion circuit. The pulse width modulator converts the power parameter into a pulse width modulation signal. The pulse width analyzer receives the pulse width modulation signal through the first isolator in an isolation manner, calculates a duty ratio of the pulse width modulation signal according to a rising edge and a falling edge of the pulse width modulation signal, and calculates the power parameter according to the duty ratio. The control unit controls operations of the second-stage power conversion circuit according to the power parameter that is obtained by the pulse width analyzer.
US10128763B2	Output-side controller with switching request at relaxation ring extremum A method for regulating a power converter includes initiating a transition of a switch coupled to an input side of the power converter from an OFF to an ON state to regulate a transfer of energy from the input to an output side of the power converter after a switch control signal generator receives an enable signal and if a feedback signal representative of an output of the power converter indicates a change in an output of the power converter. The enable signal is generated to communicate a control signal from the output to the input side in response to a first signal representative of a voltage on an output terminal that oscillates in response to an ending of the transfer of energy. The transition of the switch from the OFF to the ON state occurs substantially at a time that the first signal reaches an extremum.
US10128762B2	Semiconductor device for controlling power source A semiconductor device for power supply control includes an over-current detection circuit which detects an over-current state on a secondary side of a transformer by comparing a voltage in proportion to current flowing in a primary-side winding wire with an over-current detection voltage; a control signal generation circuit which generates a control signal to turn off a switching element when the over-current detection circuit has detected the over-current state; and an over-current detection level generation circuit which generates the over-current detection voltage in accordance with an on-duty of a driving pulse of the switching element. The over-current detection level generation circuit is configured to generate the over-current detection voltage in accordance with: Vocp=Vint+a·ON Duty, where Vocp represents the over-current detection voltage, ON Duty represents the on-duty, Vint represents the over-current detection voltage to be a reference, and “a” represents a correction coefficient.
US10128761B2	Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter The present disclosure is directed to a primary-controlled high power factor quasi resonant converter. The converter converts an AC power line input to a DC output to power a load, generally a string of LEDs, and may be compatible with phase-cut dimmers. The power input is fed into a transformer being controlled by a power switch. The power switch is driven by a controller having a shaping circuit. The shaping circuit uses a current generator, switched resistor and capacitor to produce a reference voltage signal. The controller drives the power switch based on the voltage reference signal, resulting in a sinusoidal input current in a primary winding of the transformer, resulting in high power factor and low total harmonic distortion for the converter.
US10128760B2	PCB planar transformer and converter using the same A PCB planar transformer, comprising: at least one primary winding layer, each formed with a primary winding therein, wherein wire traces constituting the primary winding have a first horizontal width; at least one secondary winding layer, each formed with a secondary winding therein, wherein wire traces constituting the secondary winding have a second horizontal width; and at least one shielding layer, each located between the primary winding layer and the adjacent secondary winding layer, wherein the shielding layer is formed with a conductor therein, and the conductor in the shielding layer has a third horizontal width, wherein at least one of the first horizontal and the second horizontal width is smaller than the third horizontal width of the conductor in the shielding layer.
US10128759B2	Power supplying apparatus with piezoelectric transformers A power supplying apparatus includes a first piezoelectric transformer operated at a first operating frequency, a second piezoelectric transformer operated alternately with the first piezoelectric transformer and operated at a second operating frequency, wherein the second operating frequency is a multiple of the first operating frequency.
US10128755B2	Slew mode control of transient phase based on output voltage slope of multiphase DC-DC power converter A multi-phase switch mode, voltage regulator has a transient mode portion in which a phase control output is coupled to one or more control inputs of one or more switch circuits that conduct inductor current through one or more transient phase inductors, from amongst a number of phase inductors. A slew mode control circuit detects a high slope and then a low slope in the feedback voltage and, in between detection of the high slope and the low slope, pulses the phase control output of the transient mode portion so that the switch circuit that conducts transient phase inductor current adds power to, or sinks power from, the power supply output. Other embodiments are also described.
US10128751B1	Control system for controlling a DC-DC voltage converter circuit A control system for controlling a DC-DC voltage converter circuit is provided. An output voltage controller outputs a DC-DC voltage converter control voltage to an input control terminal to increase a switching duty cycle within the DC-DC voltage converter circuit when the low voltage is less than an output reference voltage. An input voltage controller reduces the DC-DC voltage converter control voltage at the input control terminal of the DC-DC voltage converter circuit when a high voltage is less than an input reference voltage to reduce the switching duty cycle within the DC-DC voltage converter circuit.
US10128750B2	Switched-mode power converter with an inductive storage element and a cascode circuit A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.
US10128747B2	Frequency-controlled voltage source Voltage source circuits, asynchronous processing systems and methods are disclosed. A voltage source circuit includes a capacitor storing an operating voltage for an asynchronous processor. A frequency comparator compares a frequency reference and a feedback signal indicative of an operating frequency of the asynchronous processor to determine whether or not the operating frequency is less than a target frequency. When operating frequency is less than the target frequency, a charge pump adds charge to the capacitor.
US10128746B2	Switched capacitor DC-DC power converter The present disclosure relates to a switched capacitor DC-DC converter configured for converting a DC input voltage into a higher or lower DC output voltage. The switched capacitor DC-DC converter comprises an output voltage regulator utilizing a feedback loop with a multi-level quantizer configured to convert a lowpass filtered control signal into a corresponding digital control signal.
US10128742B2	Reference signal for a current regulator A PFC circuit according to the invention is connected to a grid, includes an input filter and a rectifier connected to a converter. A control circuit generates the reference current for the current regulator of the converter that controls its input current. Thereby, the reference current is generated by adding an offset current (I0) to a standard reference current and adapting the magnitude of the standard reference current to compensate for a change of the input power resulting from the addition of the offset current (I0). However, due to the addition of the offset current (I0) the magnitudes of some lower harmonic components of the input current of the power supply unit are increased and the magnitudes of some higher harmonic components of the input current are decreased such that the power supply may draw more current from the grid.
US10128741B2	Power conversion device Each phase arm of a power conversion device includes at least one converter cell connected in series. For each converter cell, an element driving unit is provided which turns on one switching element in the converter cell as a startup element. The element driving unit is supplied with power from a DC capacitor, and when voltage of the DC capacitor exceeds startup voltage Vsh, turns on the startup element. Thus, at the time of startup of the power conversion device, the DC capacitor in each converter cell is initially charged to desired voltage.
US10128739B2	Power conversion device A first offset voltage which is added to voltage commands in a first three-phase voltage command calculated on the basis of a control command for an AC rotary machine, and a second offset voltage which is added to voltage commands in a second three-phase voltage command calculated on the basis of a control command for the AC rotary machine, are set in such a manner that a period during which one of a first power converter and a second power converter outputs an effective vector and the other thereof outputs a zero vector occurs during a carrier period of a first carrier wave signal and a second carrier wave signal.
US10128738B2	Determination of entering and exiting safe mode The disclosure describes examples of integrate circuit (IC) chips. An IC chip includes a first detector configured to generate information indicative of whether an input supply voltage or power is greater than or equal to a first threshold, a second detector configured to receive a circuit voltage or current level and generate information used to indicate a status of the IC chip based on the received circuit voltage or current level, and a controller configured to cause the IC chip to enter a safe mode in response to both the first detector indicating that the input supply voltage or power is greater than the first threshold and the circuit voltage or current level being greater than a second threshold.
US10128737B1	Constant on-time switching converter and clock synchronization circuit A constant on-time switching converter and a clock synchronization circuit are provided, which generate a synchronization signal according to a clock signal, an input voltage, and an output voltage. The synchronization signal will be synchronized with a period length of the clock signal, thereby acquiring the duty cycle of the constant on-time switching converter. People in the business can accordingly avoid the interference with the synchronization signal and other major clock signals, to prevent electromagnetic interference (BMI) generation.
US10128733B2	Position-detection system A position-detection system for a drive having a rotor, which can move along a path, comprises an encoder unit, a signal-detection unit and a signal-processing device. The encoder unit or the signal-detection unit is arranged on the rotor, and the respective other unit is arranged along the path. Furthermore, the signal-processing device is designed to generate a first position signal and a second position signal on the basis of a relative position of the encoder unit and signal-detection unit. The signal-processing device is designed to determine a longitudinal position of the rotor along the path on the basis of phase values of the first and second position signals. Furthermore, the signal-processing device is designed to determine a distance, directed transversely with respect to the path, between the encoder unit and the signal-detection unit, on the basis of amplitude values of the first and second position signals, and to detect an operating state of the drive on the basis of the distance.
US10128728B2	Manufacturing method for segment coil A manufacturing method for a segment coil according to the invention includes forming an assembled wire by bundling a plurality of element wires, forming a stranded wire by twisting the assembled wire, forming a rectangular conductor by rolling the stranded wire, and forming a segment coil by cutting the rectangular conductor into a given length and bending the cut rectangular conductor. Before the rectangular conductor is bent, the plurality of element wires is fastened at a position where the coil end portion of the segment coil is formed.
US10128726B2	Method for manufacturing a laminate and method for manufacturing a rotor A method for manufacturing a laminate used for manufacturing a rotor is provided. The method includes: (a) stamping out a plurality of workpieces from a metal sheet wherein each of the workpieces has a temporarily-interlocking portion; and (b) obtaining a laminate including the workpieces integrated together by the temporarily-interlocking portion, wherein each of the workpieces further has a shaft hole, a magnet insertion hole, and a weight-reducing hole formed between the shaft hole and the magnet insertion hole, and the temporarily-interlocking portion is provided to the weight-reducing hole.
US10128725B2	Contact brush holder A contact brush holder is disclosed. According to an aspect, a brush holder is provided for receiving at least two contact brushes and holding the brushes in contact with a slip ring in an electrical power device. The brush holder comprises a holder body adapted for receiving said brushes. The brushes are arranged on opposite sides of a plane in which a central axis of the brush holder is located and in which an axis of rotation of the electric apparatus is situated. A biasing device is provided for biasing the holder body towards the slip ring, thus biasing the at least two contact brushes towards the slip ring.
US10128721B2	Motor A motor may include a motor body portion; a connector portion disposed to the motor body portion; and a wiring member electrically connected to the motor body portion. The connector portion has a surface exposed to an outside of the motor body portion. The wiring member includes a plurality of external connection terminals which are connected to the external power supply to protrude from the exposed surface of the connector part. The connector portion is provided with a through hole which extends from the exposed surface toward the accommodating space and connects the outside of the motor body portion and the accommodating space. When viewed in the normal direction of the exposed surface, at least a portion of the through hole is positioned inside an edge of an external connection terminal group which consists of the plurality of external connection terminals.
US10128717B2	Ring for an electric machine The present disclosure relates to a ring for a rotor of an electric machine as a support for a retaining ring and for cooling coils of the rotor. It is an object of the invention to provide measures for cooling coils of a rotor of an electric machine. Disclosed is a ring for an electric machine, the ring is connected between a retaining ring and coils wound around a rotor, whereas the ring is fabricated from a non-conductive material.
US10128708B2	Armature and motor There is provided an armature including a shaft; a core attached to the shaft; a commutator that is attached to the shaft, and includes a plurality of commutator segments; windings that are wound onto the core, and are connected to the respective commutator segments; and a short-circuit member that connects together a pair out of the plurality of commutator segments, and is disposed further to the commutator radial direction outside than an outer peripheral portion of the commutator.
US10128707B2	Winding for an electric machine having transposed bars comprised of stacks of strands The winding for an electric machine comprises transposed bars having at least four stacks of strands. Couples of stacks of strands define elementary transposed bars. The winding comprises at least two stacks of cooling pipes in each transposed bar, each stack of cooling pipes being arranged between two stacks of strands, and at least one crossover transposed bar in which the sides of the elementary transposed bars are exchanged.
US10128705B2	Electric motor heating/cooling system An electric motor includes a case, a stator that includes a stator laminaiton and end-windings, a rotor coupled to the case via at least one rotor bearing. The rotor includes a hollow cylindrical body, a first shaft portion, and a second shaft portion. The hollow cylindrical body includes an inner wall, an outer wall, a first distal end, and a second distal end. The first shaft portions couples to the first distal end and the second shaft portion couples to the second distal end. The second shaft portion includes a fluid feed tube formed therewith having a fluid receive end and a fluid feed end, the fluid feed end extending to a central inner portion of the hollow cylindrical body. A plurality of fluid exit ports adjacent the first distal end and the second distal end of the hollow cylindrical body spray fluid onto components of the stator.
US10128702B2	Rotor of rotary electric machine and method of producing the same A rotor of a rotary electric machine includes a rotor core. The rotor core has magnet insertion holes which are arranged at first circumferential intervals and in which permanent magnets are disposed. The rotor core includes steel plates, a first core block, and a second core block. The steel plates are stacked in an axial direction of the rotor. The first core block includes first steel plates among the steel plates stacked with rotational stacking at a rotational stacking angle corresponding to a common multiple of a first circumferential interval among the first circumferential intervals and a second circumferential interval among second circumferential intervals. The second core block includes second steel plates among the steel plates stacked with the rotational stacking at the rotational stacking angle from a position shifted by an angle corresponding to the first circumferential interval relative to the first core block.
US10128695B2	Hybrid Wi-Fi and power router transmitter The present disclosure provides a method of wireless transmission of power and Wi-Fi signals to electronic devices. The method includes identifying a first receiver that is associated with a first electronic device that requires power and a second receiver that is associated with a second electronic device that requires Wi-Fi signals, generating RF signals at least in part by converting power provided by a power source, where the transmitter includes a first set of antennas for transmitting RF signals and a second set of antennas for transmitting Wi-Fi signals, and transmitting, to the first receiver, the RF signals using at least two antennas of the first set of antennas connected to the transmitter. The method further includes, while transmitting the RF signals using the at least two antennas of the first set of antennas, simultaneously transmitting, to the second receiver, Wi-Fi signals using the second set of antennas.
US10128694B2	Power storage apparatus A storage apparatus includes a plurality of storage cells connected in series. Each storage cell comprises a storage element that stores a charge, a container that houses the storage element, a reception antenna capable of receiving power transmitted from a transmission antenna of a feeding facility provided in a wireless power transfer system, and a charging control circuit that charges the storage element using the power received by the reception antenna. The plurality of storage cells are charged concurrently and wirelessly, and therefore charging can be performed on all of the storage cells without overcharging or undercharging.
US10128691B2	Bidirectional power converter A bidirectional power converter circuit is controlled via a hysteresis loop such that the bidirectional power converter circuit can compensate in near real time for variations and even changes in transmit and receive coil locations without damaging components of the system. Because the bidirectional power converter is capable of both transmitting and receiving power (at different times), one circuit and board may be used as the main component in multiple wireless power converter designs.
US10128687B2	Power transmission apparatus, and power transmitting device and power receiving device for the power transmission apparatus There is provided a non-contact power transmission apparatus which can supply stable power from a power transmitting side to a power receiving side even if a load is changed. The power transmission apparatus transmits power from a power transmitting device to a power receiving device in a non-contact manner. The power transmitting device includes a series circuit which is connected to a direct-current power source, and includes a parallel resonance circuit including a first capacitor and a first inductor, and a switch element, a drive source to drive on or off the switch element, and a first series resonance circuit connected to a connection point between the parallel resonance circuit and the switch element and including a second inductor, a second capacitor and a power transmission coil. The power receiving device includes a second series resonance circuit including a power receiving coil paired with the power transmission coil and a third capacitor connected in series to the power receiving coil, and a rectifying circuit to rectify a voltage generated in the second series resonance circuit and to supply the voltage to a load circuit.
US10128686B1	Systems and methods for identifying receiver locations using sensor technologies An example method disclosed herein includes: acquiring, by at least one sensor in communication with a transmitter, data indicating a location of an electrical apparatus within a transmission field of the transmitter. The transmitter is in communication with a mapping memory that stores information that identifies a set of receivers that has each been designated to receive power waves from the transmitter. The method also includes: determining, by the transmitter, using the mapping memory and the data indicating the location of the electrical apparatus, whether the electrical apparatus is a respective receiver of the set of receivers. The method further includes: transmitting, by the transmitter, power waves to the electrical apparatus upon determining that the electrical apparatus is the respective receiver, wherein the power waves are transmitted to converge in a three dimensional space to form one or more pockets of energy at the location associated with the electrical apparatus.
US10128679B2	Adaptive charger with input current limitation and controlling method for the same An adaptive charger can include: a power converter configured to receive an input current from an external power supply, and to generate an output current as a charging current to a load; a current feedback loop configured to compare a first detection signal that represents the input current against a first current reference signal, and to generate a first error signal, where the power converter is configured to regulate the input current according to the first error signal; and the current feedback loop being configured to determine an overload state of the external power supply according to an input voltage of the power converter, where the charger is configured to enter a current limit state when the external power supply is determined to be in the overload state, and where the first current reference signal is gradually reduced until the external power supply recovers to a non-overloaded state.
US10128673B2	Portable device for aiding low temperature high power output of battery pack Disclosed is a portable device for aiding low temperature high power output of a battery pack, the device including a primary loop and a control unit, in which: the primary loop is configured as a working loop of the battery pack and comprises a power resistor, herein two ends of the power resistor are electrically connected with the positive/negative terminal of the battery pack respectively, and the battery pack discharges at low temperatures through the power resistor so that an internal temperature of the battery pack rises; and the control unit is configured to control on/off of the primary loop.
US10128671B2	Cupholder (3 in 1) The present invention discloses a charging cup holder with slot having a cup sleeve, a fixing base and a cup carrier, the cup sleeve used for a cup passing through is hinged to the upper end of the fixing base, and the cup carrier for supporting the cup is hinged to the lower end of the fixing base, wherein a USB interface used to electrically connect with a mobile terminal is provided on the fixing base and the cup sleeve is provided with two opposite slots for placing the mobile terminal. The charging cup holder may not only hold the cup, but also the mobile terminals can be placed in the slot of the cup sleeve conveniently, such as cell phones and other mobile electronic devices, to realize charging easily by electrically connecting to the USB interface on the fixing base.
US10128669B2	Method of transmitting and receiving power and electronic device using the same An electronic device comprising: a battery having a plurality of cells that are connected in series; a circuit electrically connected to the battery; and a conductive pattern electrically connected to the circuit, wherein the circuit is configured to: receive a first signal wirelessly from a first external device by using the conductive pattern, charge at least some of the plurality of cells in the battery by using a power of the first signal, generate a second signal by changing a first voltage, that is produced by at least two of the plurality of cells in the battery, into a second voltage that is lower than the first voltage, and wirelessly transmit the second signal to a second external device, the second signal being transmitted by using the conductive pattern.
US10128667B2	DC/DC converter with capacitor voltage balancing A method for voltage balancing of series connected capacitors, wherein a voltage in an intermediate circuit of an electric circuit can be easily and safely balanced between a plurality of series connected capacitors and thus these components are operated safely in terms of their voltage strength. This problem is solved in that the voltage balancing is accomplished in that, in a first step of the method, an at least partial discharging of a first or a second capacitor occurs across a first or second winding of a transformer, while thanks to the action of the transformer a current is induced in a second step of the method in the second or first winding which charges the second or first capacitor as a charging current.
US10128663B2	Wireless power transfer using stacked resonators A wireless power transfer system may include a primary resonator and one or more secondary resonators. At least one of the secondary resonators lie in overlapping relation to the primary resonator. An electromagnetic (EM) field generated by the primary resonator can couple to the secondary resonators, thus inducing current flow in the secondary resonators. EM fields generated by the secondary resonators interact with the EM field from the primary resonator to produce a resultant EM field.
US10128662B2	Power system for an aircraft with dual hybrid energy sources A power system for an aircraft having a plurality of power-consuming components, some of which have transient power requirements, which is greater than the average power requirement, the power system includes at least one generator, a power distribution buss, a non-battery power source, a battery power source, and a power controller selectively coupling the non-battery power source and the battery power source to the power distribution buss to satisfy the transient power requirements.
US10128661B2	Status indicator for power generation systems An indicator device includes a housing configured to be coupled to positive and negative DC wire lines that supply power from an energy generation source to an inverter. The indicator device further includes a current sensor for measuring a current level on the positive and negative DC wire lines, and voltage sensors for measuring a first voltage across the positive and negative DC wire lines, a second voltage across the positive DC wire line and a ground terminal, and a third voltage across the negative DC wireline and the ground terminal. A circuit block compares the measured current level to one or more threshold current levels, and further compares the measured first, second and third voltages to one or more threshold voltage levels, and in response provides an output signal. A visual indicator receives the output signal from the circuit block, and in response provides a visual indication of whether voltage and current levels on the positive and negative DC wire lines are at levels that may harm humans.
US10128659B2	Energy generation interactions bypassing the grid Methods, devices, and systems for controlling energy generation interactions that bypass the grid may be provided. Flow control devices may be directly connected with one another independent of electrical connections to the utility grid. In some examples, the direct connections between the devices may enable sharing of power, controlling power flow over the direct connections, and/or recording relative power flows between the devices.
US10128658B2	Autonomous methods, systems, and software for self-adjusting generation, demand, and/or line flows/reactances to ensure feasible AC power flow Autonomous, self-adjusting, and distributed line flow processing for a network having nodes with branches coupling adjacent ones of the nodes and components coupled to the nodes. Systems, methods, and software made in accordance with this disclosure can be used to identify where power flows can exceed the maximum transfer limit in each line and to enable automated adjustments in order to avoid such conditions. These can be useful tools for both system operators of large electrical networks and for implementing automated schemes to ensure network feasibility in micro-grids or other networks with many smart components embedded with communications and/or computation capabilities.
US10128656B2	Power assist unit and power assist system A power assist apparatus includes a branch power lines, a first power storage device, a power assist converter, and a second power storage device. The branch power line is connected to a main line of a natural energy power generation system, which is connected to a system. The first power storage device connected to the branch power line. The power assist converter connected to the branch power line. The second power storage device connected to a downstream side of the power assist converter.
US10128654B2	Method and apparatus for correcting for power harmonics A light-emitting diode (“LED”) lighting unit includes an operational, a sense resistor electrically connected to the input of the operational amplifier, a first field effect transistor (“FET”) whose gate is electrically connected to the output such that the input voltage at the gate of the first FET rises and falls with the output voltage, a second FET whose gate is electrically connected to the output such that the input voltage at the gate of the second FET rises and falls with the output voltage, and a string of LED lights connected such that when the voltage across the string drops below a level to operate, the voltage across a sense resistor drops, causing the operational amplifier to increase its output until the input voltage at the gate of the second FET increases allowing one bank of LED lights to operate.
US10128652B2	Stabilizing a DC electricity network A method of stabilizing a DC electricity network, the network including a DC voltage source powering electrical loads that are connected in parallel to terminals of the voltage source and each of which is to receive a current or voltage setpoint. The method stabilizes the network by regulating setpoints applied to the loads by a virtual stabilization impedance generated at terminals of each load, the virtual impedances being dimensioned to stabilize the network in desired operating points and in given configurations of the network including a state in which at least one load is inactive or has failed and a state in which the stabilization of a load is inactive. Each virtual impedance is generated by a non-linear regulation loop acting on the setpoint for the corresponding load.
US10128650B2	Relay protection method and apparatus against LC parallel circuit detuning faults A relay protection method against LC parallel circuit detuning faults comprises the steps of: a relay protection device samples a current of a parallel LC, that is, a reactor and a capacitor, and samples a total current flowing through the whole LC; convert the current of the reactor into a current of an equivalent capacitor; calculate amplitudes of the current of the equivalent capacitor and a current of a realistic capacitor and calculate an amplitude of the total current flowing through the LC; calculate a current amplitude ratio of the equivalent capacitor to the realistic capacitor; and when the amplitude of the total current flowing through the LC is large enough, send an alarm signal or a trip after a setting time delay if the current ratio exceeds a preset upper and lower limit range. Also provided is a corresponding relay protection device.
US10128649B2	Power supply device A power supply device includes a resistor that limits an electric current supplied from an AC power supply, a switching unit that is connected in parallel with the resistor, a rectifier circuit unit that is connected to a subsequent stage of the resistor and the switching unit and rectifies an AC voltage of the AC power supply, a booster circuit unit, a DC-voltage detection unit that detects a DC voltage output from the booster circuit unit, an AC voltage detection unit, a protection setting unit that compares a first protection voltage calculated on the basis of the boosting level by the booster circuit unit with a second protection voltage calculated based on the AC voltage detected by the AC-voltage detection unit and sets either one as a protection voltage, and a control unit that opens the switching unit when the DC voltage falls below the protection voltage and stops boosting.
US10128648B2	Diagnostic system for a DC-DC voltage converter A diagnostic system for a DC-DC voltage converter having a low voltage bi-directional MOSFET switch is provided. The low voltage bi-directional MOSFET switch has first and second nodes. The microcontroller samples a first voltage at the first node at a first sampling rate utilizing a first common channel in a first bank of channels to obtain a first predetermined number of voltage samples. The microcontroller determines a first number of voltage samples in the first predetermined number of voltage samples in which the first voltage is less than a first threshold voltage. The microcontroller sets a first voltage diagnostic flag equal to a first fault value if the first number of voltage samples is greater than a first threshold number of voltage samples indicating a voltage out of range low fault condition for the analog-to-digital converter.
US10128642B2	Foldable cable tray The present invention relates to a foldable cable tray configured for ease of transportation and for storage. The foldable cable tray includes a first side rail, a second side rail, a plurality of rungs movably connected to the first and second side rails to transit the foldable cable tray between unfolded and folded positions, and a locking device configured to lock each of the plurality of rungs to the first and second side rails when the foldable cable tray is in the unfolded position.
US10128634B2	Integrated wavelength locker Described are various configurations of integrated wavelength lockers including asymmetric Mach-Zehnder interferometers (AMZIs) and associated detectors. Various embodiments provide improved wavelength-locking accuracy by using an active tuning element in the AMZI to achieve an operational position with high locking sensitivity, a coherent receiver to reduce the frequency-dependence of the locking sensitivity, and/or a temperature sensor and/or strain gauge to computationally correct for the effect of temperature or strain changes.
US10128631B2	Generation of VUV, EUV, and X-ray light using VUV-UV-VIS lasers A method for extending and enhancing bright coherent high-order harmonic generation into the VUV-EUV-X-ray regions of the spectrum involves a way of accomplishing phase matching or effective phase matching of extreme upconversion of laser light at high conversion efficiency, approaching 10−3 in some spectral regions, and at significantly higher photon energies in a waveguide geometry, in a self-guiding geometry, a gas cell, or a loosely focusing geometry, containing nonlinear medium. The extension and enhancement of the coherent VUV, EUV, X-ray emission to high photon energies relies on using VUV-UV-VIS lasers of shorter wavelength. This leads to enhancement of macroscopic phase matching parameters due to stronger contribution of linear and nonlinear dispersion of both atoms and ions, combined with a strong microscopic single-atom yield.
US10128630B2	Solar-pumped laser device A solar-pumped laser device includes: a light-guiding plate configured such that a fluorescence substance absorbing solar light and emitting fluorescence including a predetermined wavelength is dispersed in the light-guiding plate so as to bring the fluorescence to exit a predetermined surface; and an optical fiber disposed close to the predetermined surface, the optical fiber including: a core part in which a medium excitable by the fluorescence so as to emit a laser is dispersed; and a clad part that is formed by a material through which the fluorescence passes, is disposed around the core part, and has a smaller refractive index than a refractive index of the core part, wherein a light emitted by the medium is totally reflected by one end surface of the optical fiber, and is brought to pass through the other end surface of the optical fiber.
US10128629B2	Laser oscillator provided with discharge tube and laser processing machine A laser oscillator which can effectively remove scattered light by a simpler configuration. The laser oscillator comprises an output mirror and a rear mirror which are arranged facing each other and a discharge tube which is arranged between the output mirror and the rear mirror. The discharge tube has a first part which gets larger in inner diameter from a first end part in an axial direction facing the output mirror toward the rear mirror.
US10128626B2	Composite cable and composite harness A composite cable is provided that improves terminal machinability while maintaining bending resistance. The composite cable is provided with: a pair of first electric wires; a twisted-pair wire obtained by twisting together a pair of second electric wires having an outer diameter that is smaller than that of the first electric wires; and a tape member spirally wrapped around an aggregate obtained by twisting the pair of first electric wires together with the twisted-pair wire. The twisting direction of the twisted-pair wire, the twisting direction of the aggregate, and the wrapping direction of the tape member are all the same direction.
US10128625B2	Bus bar and power electronic device with current shaping terminal connector and method of making a terminal connector A current shaping phase leg bus bar for power electronics systems includes a first terminal connector, a second terminal connector, insulated from the first terminal connector, and a third terminal connector, insulated from the first and second terminal connectors. At least one of the terminal connectors is a current shaping terminal connector that includes one or more layers having a plurality of pre-defined locations for electrical connections, said plurality of pre-defined locations including one or more first locations and a plurality of second locations, and includes one or more gaps within or among its one or more layers, to provide substantially balanced conductive pathways among its one or more first locations and its plurality of second locations.
US10128624B2	Power connector system A power connector system includes a header connector having a header housing mounted to a chassis. The header housing holds a header terminal comprising a plurality of contact members arranged side-by-side in a stacked arrangement. Each contact member has a pair of spring beams defining sockets at a mating end of the contact member. The sockets of the contact members are aligned to define a tab socket of the header terminal. The power connector system includes a plug connector having a plug housing holding a tab terminal. The tab terminal has a mating end and a cable end. The mating end is received in a mating direction into the tab socket of the header terminal during mating to electrically connect the tab terminal with the header terminal.
US10128622B1	Electrical system, and power inlet apparatus and electrical receptacle assembly therefor An electrical receptacle assembly is for a power inlet apparatus of an electrical system. The power inlet apparatus includes a housing. The electrical system has a power source and a transfer switch. The electrical receptacle assembly includes an electrical receptacle structured to be mechanically coupled to the housing and electrically connected with the power source and the transfer switch, and an indication assembly mechanically coupled to and electrically connected with the electrical receptacle. The indication assembly has a status indicator adapted to provide an indication of circuit status within the electrical system.
US10128621B2	Cable connector The present disclosure discloses a cable connector, which comprises: at least one cable, the at least one cable comprises an insulating sheath, a shielding layer inside the insulating sheath and at least one conductive wire; a connector, the connector comprises a metal shell, the metal shell is provided with a cable receiving portion mounting the at least one cable, the at least one cable is inserted into the connector to allow the connector and the at least one conductive wire to be electrically connected. The shielding layer is exposed out of the insulating sheath at an end of the at least one cable, a conductive elastomer is sheathed on the exposed shielding layer, when the cable receiving portion squeezes the at least one cable, the conductive elastomer is deformed and fills most of a gap between the cable receiving portion and the at least one cable.
US10128617B2	Angle connector for differential transmission of data signals An angle connector for differential transmission of data signals, having first and second conductor pair ends in a first and second flat angle connector end surface, respectively, wherein the connector end surfaces are tilted spatially relative to one another, wherein, between the angle connector end surfaces, the angle connector has at least one first curved section in which all conductors of the conductor pair(s) are arranged with the respective longitudinal axes parallel to one another and all longitudinal axes follow a curved line, wherein in the first curved section, the longitudinal axes of at least one conductor pair follow differently curved lines, which are curved to varying degrees in such a way that, in the first curved section, two conductors have different geometric lengths relative to one another, wherein the angle connector has at least one second section in which all conductors of the conductor pair(s) are twisted for a predetermined fraction of a lay length in such a way that all conductors of the conductor pair(s) have an identical geometric length.
US10128613B2	Pin connector assembly A pin connector assembly has male connector and a female connector. The male connector has a first alignment slot formed on a first housing of the male connector and a mounting hole. The female connector has a second alignment slot formed on a second housing of the male connector and a mounting hole. The first and second alignment slots allows the male connector and the female to be coupled with each other without damaging metal contacts on the male connector. Moreover, the installation efficiency of the male connector and the female connectors are improved. The mounting holes of the male and female connectors are used for detachably mounting the male and female connectors on tubes of a trunk of an artificial Christmas tree.
US10128612B1	Dual purpose latch An electronics module includes a housing having four sides and defining an axis extending from a front to rear of the housing. Each side defines a mating feature that engages a mating feature of another electronics module. One side defines a pin-receiving receptacle, another defines a recess extending partially through a width or a thickness of the housing; and another includes a catch mechanism. A latch is mounted within the recess and includes a body having top, bottom, front, rear, inner side, and outer side surfaces. The bottom or top surface defines an opening to a vertical channel formed in the body. A hook extends from the rear surface and secures a catch on the other module. A spring-biased pin is received within the channel and mounted within the recess such that an end of the pin extends through the opening beyond a surface of the electronics housing.
US10128611B2	Ferrule assembly for an electrical connector A ferrule assembly for terminating an electrical connector to a cable includes an inner ferrule, an outer ferrule and an inner ferrule sleeve. The inner ferrule has an inner surface and an outer surface. The inner ferrule is conductive and provides electrical shielding. The outer ferrule is positioned radially outside of the inner ferrule such that a cable shield of the cable is received between the inner ferrule and the outer ferrule. The outer ferrule secures the cable shield between the inner ferrule and the outer ferrule. The inner ferrule sleeve is positioned radially inside of the inner ferrule. The inner ferrule sleeve substantially fills the space between the inner ferrule and an inner jacket of the cable. The inner ferrule sleeve is dielectric and electrically isolating the inner ferrule from an inner conductor of the cable.
US10128606B2	Connector having a potting material covered by a protective plate with holes for contact terminals and for filling of the potting material In a relay connector, a male terminal is formed in a rod-like shape, inserted into a through hole penetrating a male terminal housing chamber, extends inside a cylinder part, and has a first contact part. A protective plate includes a body part that partitions an internal space defined by the cylinder part and the male terminal housing chamber into a first space portion located on the first contact part side of the male terminal and a second space portion located on the male terminal housing chamber side of the male terminal, a terminal hole that is formed in the body part, and configured to receive the male terminal thereinto, and a filling port that is formed in the body part, and communicably connects the first space portion and the second space portion to each other. The second space portion is filled with a potting filling part.
US10128597B2	Electrical contact pad for electrically contacting a connector An electrical contact pad for electrically contacting a connector includes first, second and third regions. The first region is connected to a trace. The second region is adjacent to the first region and has a width less than the first region. The third region is adjacent to the second region and has a width that is greater than the second region. The third region is sized to make contact with a connector. Having the width of the second region be smaller than the width of the first and third regions increases an impedance of the electrical contact pad.
US10128594B2	Connectors having three-dimensional surfaces Apparatus and methods are described, including apparatus that includes a connector. The connector includes a connector body including at least one mating surface having a first longitudinal end, and a second longitudinal end that is narrower than the first longitudinal end. A plurality of electrically-conductive terminals are coupled to the mating surface of the connector body. Other embodiments are also described.
US10128593B1	Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.
US10128587B2	Power connection apparatus assembly and power connection apparatus A power connection apparatus assembly has first and second power connection apparatuses. The first apparatus includes a connecting unit and a first circuit board. The connecting unit has a conductive member and a positioning member, the conductive member has a mounting plate portion and an inserting plate portion bending from the mounting plate portion and extending. The mounting plate portion has a positioning hole, the positioning member has a flat plate portion cooperating with the mounting plate portion and a protruding post protruding from the flat plate portion to correspondingly pass through the positioning hole. The first circuit board has an insertion hole corresponding to the positioning hole in position to allow the protruding post to insert therein, the protruding post of the positioning member passes through the positioning hole of the mounting plate portion of the conductive member and inserts into the insertion hole so that the mounting plate portion and the first circuit board are positioned relative to each other. The second apparatus has a second circuit board and an electrical connector corresponding to the connecting unit. The inserting plate portion of the conductive member may insert into an insertion slot of the electrical connector, and after the conductive member and the electrical connector has mated with each other, the first circuit board and the second circuit board are parallel to each other.
US10128586B2	Plug connector for making solder-free contact with a coaxial cable A plug connector has an outer conductor socket to receive a coaxial cable. An inner conductor receiving element receives an inner conductor of the coaxial cable and is arranged in a centered manner within the outer conductor socket. The outer conductor socket has at least one contact-making area which makes electrical contact with an outer conductor of the coaxial cable. At least one separating element is arranged within the outer conductor socket in such a way that making electrical contact with the end of the outer conductor of a coaxial cable that can be or is inserted into the outer conductor socket and the outer conductor socket is prevented or suppressed. In the plugged-in state, the contact-making area is arranged in the outer conductor socket in such a way that electrical contact can be or is made radially with the circumferential wall adjoining the end.
US10128582B2	Splice with tap clamp A wire connection system for providing electrical communication between a first conductor and a second conductor includes a housing having a sidewall, a housing surface, and a housing channel. The sidewall extends between a first end and a second end and at least partially encloses a housing chamber. The connection system further includes at least one jaw supported for movement within the housing chamber and configured to engage the first conductor. The connection system further includes a clamp member at least partially disposed within the housing channel, the clamp member including a clamp surface proximate the housing surface in a facing relationship. The connection system further includes a linear actuator coupled to the housing and movable along a longitudinal axis, the linear actuator coupling the housing and the clamp member and movably coupled to the at least one jaw.
US10128581B2	Crimp terminal A crimp terminal (1) includes a barrel (13) on which a recessed serration (14) is formed, the barrel is to be bent and crimped to a conductor portion (21) of a wire (2), and the shape of an outer edge of the serration (14) is formed so that arcs (A1 to A4) each of which is convex outward continue to each other.
US10128574B2	Antenna tuning assembly and mobile communication apparatus using same An antenna tuning assembly is disclosed, including: a substrate; an input path on the substrate, for receiving control signals; a tuning network on the substrate, including an impedance circuit with a tunable impedance and at least one tuner connecting with the impedance circuit and the input path for generating an corresponding impedance in response to the control signals; an output path connecting with the tuning network on the substrate, for coupling to an external antenna according to the corresponding impedance.
US10128569B2	Antenna assembly and electronic device An antenna assembly and an electronic device are provided. The antenna assembly includes: an antenna body having a feed point, a first grounding point, a second grounding point, and a third grounding point; a feed circuit connected with the antenna body via the feed point; a first grounding circuit configured to provide at least two low frequency states and connected with the antenna body via the first grounding point; a second grounding circuit connected with the antenna body via the second grounding point; and a third grounding circuit connected with the antenna body via the third grounding point.
US10128562B2	LTE/Wi-Fi wireless router The invention relates to a wireless router, comprising at least one first antenna suitable to operate within a Wi-Fi frequency band, said first antenna comprising a ground plane and a first probing structure. The invention also relates to a second antenna comprising a second probing structure, wherein said second antenna is configured to be mounted as add-on to said Wi-Fi router. The invention further relates to an assembly of multiple second antennas.
US10128558B2	Directional couplers and devices including same Directional couplers having a chain configuration and devices incorporating same. In some implementations, a chain coupler assembly can include a plurality of couplers each having a driver arm configured to route a respective RF signal and a coupled arm disposed physically proximate to the driver arm to detect a portion of power of the respective RF signal. Portions of the driver arm and the coupler arm can form an overlapping region. At least one of the driver arm and the coupled arm can have a non-straight arm shape, and the coupled arms of the plurality of couplers can be connected together in series.
US10128557B2	Chip-to-chip interface comprising a microstrip circuit to waveguide transition having an emitting patch The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.
US10128549B2	Electrical energy store An electrical energy store for a motor vehicle has multiple battery cells oriented in the same direction. Each battery cell has two parallel sides and a cell terminal with one plus pole and one minus pole. The battery cells are in the form of pouch cells between which there is arranged a cooling foil that comprises graphite particles and a cooling duct connected in heat-transmitting fashion to the cell terminal and to the foil.
US10128548B2	Battery device, and protection method thereof A battery device in one aspect of the present disclosure comprises a battery, a cell voltage monitoring part, a power supply line, a plurality of monitor lines, and an interrupter. The interrupter interrupts the power supply line and all of the plurality of monitor lines when the battery enters an overdischarge state.
US10128544B2	Cooling for battery units in energy storage system Systems and methods for controlling the temperature of an energy storage system are provided. More specifically, a time period of increased battery temperature attributable to, for instance, charging or discharging of the battery can be identified. A control system can be used to reduce the ambient temperature of a space associated with the battery energy storage devices in the time period prior to or immediately before the period of increased battery temperature. The ambient temperature can be maintained at a nominal ambient temperature at other times.
US10128543B2	Molten metal rechargeable electrochemical cell The present invention provides rechargeable electrochemical cells comprising a molten anode, a cathode, and a non-aqueous electrolyte salt, wherein the electrolyte salt is situated between the molten anode and the cathode during the operation of the electrochemical cell, and the molten anode comprises an aluminum material; also provided are batteries comprising a plurality of such rechargeable electrochemical cells and processes for manufacturing such rechargeable electrochemical cells.
US10128540B2	Lithium secondary battery Disclosed is a lithium secondary battery including: (i) a cathode active material including a lithium metal phosphate according to Formula 1 below; (ii) an anode active material including amorphous carbon; and (iii) an electrolyte for lithium secondary batteries including a lithium salt and an ether based solvent, wherein propylene carbonate (PC) is included in an amount of 1 wt % to 60 wt % in the electrolyte for lithium secondary batteries, based on the total weight of the electrolyte, Li1+aM(PO4-b)Xb (1) wherein M is at least one selected from metals of Groups II to XII; X is at least one selected from F, S and N, −0.5≤a≤+0.5, and 0≤b≤0.1.
US10128538B2	Non-aqueous electrolytic solution and lithium ion secondary battery The present invention provides a non-aqueous electrolytic solution comprising a phosphinoamine-based compound represented by formula (1) below and a lithium ion secondary battery comprising the non-aqueous electrolytic solution. By adding the phosphinoamine-based compound to the non-aqueous electrolytic solution, oxidative degradation in the non-aqueous electrolytic solution is suppressed, and thus gas generation is suppressed.
US10128537B2	Electrolyte formulations for electrochemical cells containing a silicon electrode Additives to electrolytes that enable the formation of comparatively more robust SEI films on silicon anodes. The SEI films in these embodiments are seen to be more robust in part because the batteries containing these materials have higher coulombic efficiency and longer cycle life than comparable batteries without such additives. The additives preferably contain a nitrate group.
US10128535B2	Secondary battery including electrolytic solution having an unsaturated cyclic ester carbonate, battery pack, electric vehicle, electric power storage system, electric power tool, and electronic apparatus including the same A secondary battery includes: a cathode; an anode; and an electrolytic solution. The anode includes a carbon material and styrene-butadiene rubber. The electrolytic solution includes an unsaturated cyclic ester carbonate represented by the following Formula (1). (X is a divalent group in which m-number of >C═CR1R2 and n-number of >CR3R4 are bonded in any order. Each of R1 to R4 is one of a hydrogen group, a halogen group, a monovalent hydrocarbon group, a monovalent halogenated hydrocarbon group, a monovalent oxygen-containing hydrocarbon group, and a monovalent halogenated oxygen-containing hydrocarbon group. Any two or more of the R1 to the R4 are allowed to be bonded to one another. m and n satisfy m≥1 and n≥0.)
US10128530B2	Multi-functional electrolyte for thermal management of lithium-ion batteries The high thermal conduction resistances of a lithium-ion battery (LIB) severely limit the effectiveness of a conventional external thermal management system (TMS). A method for a new thermal management system for lithium-ion batteries that utilizes a multi-functional electrolyte (MFE) to remove heat locally inside the cell by evaporating a volatile component of the MFE is disclosed. These new electrolyte mixtures comprise a high vapor pressure co-solvent. The characteristics of a previously unstudied high vapor pressure co-solvent HFE-7000 (65 kPa at 25° C.) in an MFE (1 M LiTFSI in 1:1 HFE-7000/EMC), and other possible MFE compositions that can be utilized in a custom electrolyte boiling facility, are disclosed.
US10128528B2	Combinatorial chemistries for matching multiple batteries A micro-hybrid battery system includes a lithium ion battery module configured to be coupled to an electrical load. The lithium ion battery module includes a housing. The lithium ion battery module also includes a first lithium ion battery cell disposed in the housing and having a first active material chemistry including a first cathode active material and a first anode active material. The lithium ion battery module also includes a second lithium ion battery cell electrically connected to the first lithium ion battery cell and disposed in the housing. The second lithium ion battery cell has a second active material chemistry including a second cathode active material and a second anode active material. The first and second active material chemistries are different such that the first and second lithium ion battery cells have different open circuit voltages.
US10128526B2	Electrode assembly having step, secondary battery, battery pack and device including electrode assembly, and method of manufacturing electrode assembly There is provided an electrode assembly including a first electrode laminate having at least one or more electrode units having a first area, stacked therein, a second electrode laminate having at least one or more electrode units having a second area smaller than the first area, stacked therein, and a step portion provided by stacking the first electrode laminate and the second electrode laminate in a direction perpendicular to a plane and having a step formed due to a difference in areas of the first and second electrode laminates, the electrode assembly being characterized in that, the electrode unit is wound by a rectangular-shaped separation film such that at least a portion of the rectangular-shaped separation film covers the step portion of the electrode assembly, and a step having a shape identical to the step portion is formed.
US10128523B2	Fuel cell system and control method for the same A fuel cell system is equipped with a fuel cell and a secondary battery. This fuel cell system is equipped with a recordation unit that records a charge-discharge history of the secondary battery, a prediction unit that predicts restriction on an output of the secondary battery based on the charge-discharge history recorded by the recordation unit, and an output control unit that starts power generation by the fuel cell prior to a timing of restriction on the output of the secondary battery, when the prediction unit predicts restriction on the output of the secondary battery and the fuel cell is in an intermittent operation state.
US10128522B2	Complete oxidation of sugars to electricity by using cell-free synthetic enzymatic pathways The present invention is in the field of bioelectricity. The present invention provides energy generating systems, methods, and devices that are capable of converting chemical energy stored in sugars into useful electricity.
US10128520B2	Fuel cell A fuel cell includes an electrolyte membrane electrode assembly and a resin frame member. The electrolyte membrane electrode assembly includes an electrolyte membrane, a first electrode and a second electrode. The resin frame member has a recess in which the first electrode, the electrolyte membrane, and a portion of a second electrode catalyst layer protruding from a second gas diffusion layer are disposed, and an insertion hole which is in communication with the recess and in which the second gas diffusion layer is inserted. A filling layer covering an outer edge portion of the second electrode catalyst layer and having an oxygen permeability of 2×105 ml/m2·24 hr·atm or less is formed at least in a space between an inner wall of the insertion hole and the second gas diffusion layer.
US10128519B2	Aqueous all-copper redox flow battery The present disclosure relates to aqueous all-copper redox flow batteries. This battery comprises at least one first and second half-cell compartments including the first and second aqueous electrolyte solutions comprising a copper compound and supporting electrolytes and a first and second electrodes. The battery further comprises external storage tanks for the electrolytes residing outside of the half-cell compartments, and means for circulating the electrolytes to and from the half-cells. There is a separator between the first and the second half-cell, and the half-cells of this battery are configured to conduct oxidation and reduction reactions for charging and discharging the battery.
US10128516B2	Fuel cell system A control device for fuel cell includes, comprising a compressor configured to supply cathode gas to a fuel cell, a driving device including at least two compressor driving sources including a drive motor and a driving body using a power source other than the drive motor, the driving device configured to drive the compressor by the driving sources; and a control unit. The control unit configured to control a state of the power source on the basis of an operating state of the fuel cell, and the control unit selects the driving source to be used out of the compressor driving sources on the basis of the state of the power source.
US10128510B2	Advanced electrocatalysts for oxygen reduction reaction Provided are nanocomposites including an iron-based core and a nitrogen-doped graphitic carbon shell, and methods of making and using the same. Included in the nanocomposites is an Fe3C-based interlayer between the core and the shell. The nanocomposites can show a catalytic activity toward reducing oxygen comparable to commercial Pt/C catalysts.
US10128509B2	Gas vent for electrochemical cell An electrochemical cell system is configured to utilize an ionically conductive medium flowing through a plurality of electrochemical cells. One or more gas vents are provided along a flow path for the ionically conductive medium, so as to permit gasses that evolve in the ionically conductive medium during charging or discharging to vent outside the cell system, while constraining the ionically conductive medium within the flow path of the electrochemical cell system.
US10128504B2	Negative active material for rechargeable lithium battery, and rechargeable lithium battery including same A negative active material for a rechargeable lithium battery, including crystalline carbon-based material particles, for which a maximum volume % in a graph of a particle size distribution on a volume basis is about 20 volume % or more.
US10128503B2	Conductive fibrous materials There is provided a conductive fibrous material comprising a plurality of carbonaceous fibers, wherein each carbonaceous fiber is fused to at least one other fiber. The carbonaceous fibers may be fused at fiber-to-fiber contact points by a polymer. The process of making the conductive fibrous material comprises mixing a phenolic polymer with a second polymer to form a polymer solution, preparing phenolic fibers having nano- or micro-scale diameters by electrospinning the polymer solution, and subsequent carbonization of the obtained phenolic fibers, thereby generating carbonaceous fibers, wherein each carbonaceous fiber is fused to at least one other fiber. The conductive fibrous material may be useful in electrode materials for energy storage devices.
US10128502B2	Positive electrode active material and lithium secondary battery including the same Disclosed herein are a positive electrode active material including at least one selected from among compounds represented by Formula 1 below and a lithium secondary battery including the same that is capable of improving lifetime characteristics and rate characteristics while exhibiting excellent safety: xLi2MyMn(1-y)O3-zAz*(1−x)LiM′O2-z′A′z′ (1), where M is at least one element selected from a group consisting of Ru, Mo, Nb, Te, Re, Ir, Pt, Cr, S, W, Os, and Po, M′ is at least one element selected from a group consisting of Ni, Ti, Co, Al, Mn, Fe, Mg, B, Cr, Zr, Zn, and second row transition metals, A and A′ are each independently a negative monovalent or divalent anion, and 0
US10128501B2	Nickel composite hydroxide and manufacturing method thereof, cathode active material for nonaqueous-electrolyte secondary battery and manufacturing method thereof, and nonaqueous-electrolyte secondary battery Provided are a cathode active material having a suitable particle size and high uniformity, and a nickel composite hydroxide as a precursor of the cathode active material. When obtaining nickel composite hydroxide by a crystallization reaction, nucleation is performed by controlling a nucleation aqueous solution that includes a metal compound, which includes nickel, and an ammonium ion donor so that the pH value at a standard solution temperature of 25° C. becomes 12.0 to 14.0, after which, particles are grown by controlling a particle growth aqueous solution that includes the formed nuclei so that the pH value at a standard solution temperature of 25° C. becomes 10.5 to 12.0, and so that the pH value is lower than the pH value during nucleation. The crystallization reaction is performed in a non-oxidizing atmosphere at least in a range after the processing time exceeds at least 40% of the total time of the particle growth process from the start of the particle growth process where the oxygen concentration is 1 volume % or less, and with controlling an agitation power requirement per unit volume into a range of 0.5 kW/m3 to 4 kW/m3 at least during the nucleation process.
US10128497B2	Water-free titania-bronze thin films with superfast lithium ion transport A multilayered structure including a substrate and a layer of calcium-doped bronze is disclosed. A multilayered structure including a substrate, a layer of calcium-doped bronze, and a layer of pure bronze is also disclosed. A method for fabricating a multilayer structure including a substrate and a layer of calcium-doped bronze is also disclosed.
US10128493B2	Negative electrode active material, negative electrode and battery Provided is a negative electrode active material which can improve discharge capacity per amount and charge-discharge cycle characteristics. The negative electrode active material of the present embodiment contains at least one of material A and material B, and material C: material A: carbonaceous powder material in which a ratio of a peak intensity at 1360 cm−1 with respect to a peak intensity at 1580 cm−1 in the Raman spectrum is not more than 0.5; material B: carbonaceous powder material in which a ratio of a peak intensity at 1360 cm−1 with respect to a peak intensity at 1580 cm−1 in the Raman spectrum is more than 0.5; material C: powder material whose main component is an active substance made up of an alloy phase. This alloy phase undergoes thermoelastic diffusionless transformation when releasing metal ions or occluding the metal ions.
US10128492B2	Positive electrode for alkaline storage batteries and alkaline storage battery A positive electrode for alkaline storage batteries that enables to improve the active material utilization rate, while suppressing the self-discharge. The positive electrode for alkaline storage batteries includes a support having conductivity, and a positive electrode active material adhering to the support. The positive electrode active material includes particles of a nickel oxide. The particles of the nickel oxide include a first particle group having a particle diameter of 20 μm or more, and a second particle group having a particle diameter of less than 20 μm. The first particle group includes a first component with cracks, and a second component without cracks. The proportion of the first particle group in the particles of the nickel oxide is 15 vol % or more, and the proportion by number of the first component in the first particle group is 15% or more.
US10128489B2	Surface modifications for electrode compositions and their methods of making Compositions and methods of making are provided for surface modified electrodes and batteries comprising the same. The compositions may comprise a base composition having an active material capable of intercalating the metal ions during a discharge cycle and deintercalating the metal ions during a charge cycle, wherein the active material is selected from the group consisting of LiCoO2, LiMn2O4, Li2MnO3, LiNiO2, LiMn1.5Ni0.5O4, LiFePO4, Li2FePO4F, Li3CoNiMnO6, Li(LiaNixMnyCoz)O2, LiaMn1.5-bNi0.5-cMdO4-x, and mixtures thereof. The compositions may also comprise an annealed composition covering a portion of the base composition, formed by a reaction of the base composition in a reducing atmosphere. The methods of making comprise providing the base composition and annealing the base electrode in a reducing atmosphere.
US10128479B2	Method for manufacturing separator of fuel cell stack A method for manufacturing a separator of a fuel cell stack includes: forming a gasket on the separator of the fuel cell stack; masking a surface of the separator except for a region of the surface of the separator on which the gasket is formed; and inserting the partially masked separator into a chamber to cross-link the gasket.
US10128466B2	Light-emitting device A light-emitting device includes a first electrode and a second electrode opposed to each other, a first stack between the first and second electrodes, the first stack being adjacent to the first electrode and including a first light-emitting layer, a second stack between the first and second electrodes, the second stack being adjacent to the second electrode and including a second light-emitting layer, and a charge generation structure between the first and second stacks, the charge generation structure including an n-type charge generation layer, an interlayer organic layer, and a p-type charge generation layer which are sequentially stacked on the first stack.
US10128465B2	Display device including sealing structure which suppresses water penetration into display region A display device, which includes a display region constituted by a plurality of pixels, includes a first substrate having a hygroscopic agent formed in a peripheral region outside the display region and a sealing film covering the hygroscopic agent, a second substrate disposed facing the first substrate, and an adhesive layer, at least a portion of which is disposed closer to the side of the display region than the hygroscopic agent, and which bonds the first substrate to the second substrate.
US10128463B2	Display device A display device, including a display region formed of a plurality of pixels and a frame region formed on an outer side of the display region, includes a sealing film configured to cover the display region, a blocking portion formed in the frame region surrounding the display region, and buffering portions formed at least at two positions so as to be separated from each other on at least one straight line path extending from the display region to reach the blocking portion.In one embodiment of the present invention, the buffering portions have a wave shape in plan view.
US10128461B2	Display apparatus and method of manufacturing the display apparatus A display apparatus includes a first display area including a first display unit configured to generate light and a first encapsulation unit disposed on the first display unit; a second display area including a second display unit configured to generate light and a second encapsulation unit disposed on the second display unit; and a through area disposed between the first display area and the second display area. The first encapsulation unit includes a first encapsulation layer covering a first side of an area of the first display unit corresponding to the through area. The second encapsulation unit includes a second encapsulation layer covering a second side of an area of the second display unit corresponding to the through area.
US10128459B2	Display device A display device includes: a display panel including a display area and a pad area; a window disposed opposite to the display panel and covering the display area and the pad area; a printed layer located on a portion of the window overlapping the pad area; an adhesive layer located between the window and the display panel and covering at least a portion of an upper surface of the printed layer; and a reflection layer located between the printed layer and the adhesive layer.
US10128457B2	Light-emitting device and power-generating device A light-emitting device having a light-extraction structure includes: a first electrode; a second electrode; a light-emitting layer disposed between the first electrode and the second electrode; and an inorganic-material-based layer disposed between the first electrode and the light-emitting layer or between the second electrode and the light-emitting layer. The inorganic-material-based layer has thickness of 100 nm or more and has conductivity of 10−6 Ω−1 cm−1 or more and 100 Ω−1 cm−1 or less.
US10128448B2	Transition metal complexes with carbene ligands and the use thereof in OLEDs The present invention relates to iridium and platinum carbene complexes of the general formula (I), to OLEDs (Organic Light-Emitting Diodes) which comprise such complexes, to a device selected from the group consisting of illuminating elements, stationary visual display units and mobile visual display units comprising such an OLED, to the use of such a metal-carbene complex in OLEDs, for example as emitter, matrix material, charge transport material and/or charge or exciton blocker.
US10128443B2	Organic light-emitting device An organic light-emitting device includes a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer. The emission layer includes a first material represented by Formula 1 and a second material represented by Formula 2:
US10128437B1	Semiconductor structures including memory materials substantially encapsulated with dielectric materials, and related systems and methods A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.
US10128436B2	Storage element and memory A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.
US10128434B2	Hall element module The present invention provides a Hall element module for achieving miniaturization. A Hall element module includes a Hall element having an element surface and an element back surface, a terminal portion electrically connected to the Hall element and separated from the Hall element as viewed in a z direction, and a resin package covering at least one portion of each of the Hall element and the terminal. The resin package has a rectangular shape with four sides along the x direction and the y direction as viewed in the z direction. The terminal portion includes a terminal back surface facing the z direction and exposed from the resin package. An end edge of the terminal back surface includes a terminal back surface inclined portion opposed to the Hall element and inclined with respect to the x direction and the y direction as viewed in the z direction.
US10128426B1	LS core LED connector system and manufacturing method The present invention relates to a new method, system and apparatus for light emitting diode (LED) packages. An object of the present invention is to provide an LED package having reduced components, a superior heat dissipation property and a compact structure that is easy to assemble, does not largely restrict use of conventional equipment for its manufacture, and is compatible with implementation within present illumination devices packaging.
US10128425B2	Semiconductor light emitting device A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and an insulating layer on the light emitting structure and including first and second through-holes. The insulating layer includes a first lower insulating layer and a second lower insulating layer. The first insulating layer is disposed on the first conductivity-type semiconductor layer and is surrounded by the second lower insulating layer with the first through-hole interposed therebetween.
US10128424B2	Method for producing optoelectronic semiconductor components and optoelectronic semiconductor component The invention relates in at least one embodiment to the production of optoelectronic semiconductor components and comprises the steps: A) providing an intermediate carrier (2) having a plurality of fixing points (23), B) providing optoelectronic semiconductor chips (3) each having a chip upper side (30) and a mounting side (32) located opposite thereto, wherein electric contact points (34) of the semiconductor chips (3) are each located on the mounting sides (32), C) attaching connecting means (4), D) fixing the contact points (34) to the fixing points (23) by means of the connecting means (4), E) producing a potting layer (5), such that the semiconductor chips (3) and the contact points (34) and the connecting means (4) are directly surrounded all round by the potting layer (5), F) detaching the semiconductor chips (3), such that the connecting means (4) are removed from the semiconductor chips (3) and recesses (44) are each provided at the contact points (34) as a negative form in relation to the connecting regions (4), and G) producing electric contact structures (6).
US10128420B2	LED package structure and chip-scale light emitting unit The present disclosure discloses an LED package structure and a chip-scale light emitting unit. The chip-scale light emitting unit includes an LED chip, a phosphor sheet, and at least one light guiding group. The phosphor sheet covers entirely a top surface of the LED chip. The phosphor sheet has a light emitting surface arranged away from the LED chip, and the light emitting surface has a central region and a ring-shaped region surrounding the central region. The light guiding group is disposed on the ring-shaped region and covers at least 60% of an area of the ring-shaped region of the phosphor sheet, and the central region is not covered by the light guiding group. The light guiding group includes a plurality of light guiding micro-structures.
US10128415B2	Light source and display device using the same A light source for a display device, includes: a first LED chip emitting a first light having a peak located within the range of wavelengths 380 nm to 500 nm, and a second LED chip emitting a second light having a peak located within the range of wavelengths 380 nm to 500 nm, wherein the peak wavelength of the second light is longer than the peak wavelength of the first light, and the difference between the peak wavelength of the second light and the peak wavelength of the first light is less than 40 nm and greater than or equal to 10 nm.
US10128406B2	GaN template substrate A device substrate in which no streaked morphological abnormality occurs is achieved. A GaN template substrate includes: a base substrate; and a first GaN layer epitaxially formed on the base substrate, wherein the first GaN layer has a compressive stress greater than or equal to 260 MPa that is intrinsic in an inplane direction, or a full width at half maximum of a peak representing E2 phonons of GaN near a wavenumber of 568 cm−1 in a Raman spectrum is lower than or equal to 1.8 cm−1. With all of these requirements, a device substrate includes: a second GaN layer epitaxially formed on the first GaN layer; and a device layer epitaxially formed on the second GaN layer and made of a group 13 nitride.
US10128405B2	Optoelectronic component and method for the production thereof A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).
US10128399B1	Lateral-effect position-sensing detector A lateral-effect position-sensing detector includes a second lateral-current collector layer, an electron barrier layer on the second lateral-current collector layer, an absorber layer on the electron barrier layer, a first lateral-current collector layer on the absorber layer, and a first elongate electrical contact and a second elongate electrical contact on each of the lateral-current collector layers. Incident light radiates a transparent first lateral-current collector layer to be absorbed by the undepleted absorber layer where electron and holes are generated. The depleted electron barrier layer prevents a flow of electrons from the absorber layer to the second lateral-current collector layer but allows electrons to flow to the second lateral-current collector layer. The lateral-effect position-sensing detector is sensitive to a lateral position between the first elongate electrical contact and the second elongate electrical contact of incident light on each of the lateral-current collector layer.
US10128398B1	Resonance avalanche photodiodes for dynamic biasing Systems and methods implementing a resonance circuit, including an avalanche photodiode, in which a resonance frequency of the resonance circuit is matched with the frequency of a dynamic biasing signal of the avalanche photodiode, can be used in a variety of applications. In various embodiments, a method for blocking and/or compensating current injection associated with the parasitic capacitance of APDs operated under dynamic biasing may be substantially realized by the matching of the resonance frequency of a resonance circuit including the avalanche photodiode with the frequency of an applied dynamic biasing signal. Additional systems and methods are described that can be used in a variety of applications.
US10128397B1	Low excess noise, high gain avalanche photodiodes A system, method, and apparatus for an avalanche photodiode with an enhanced multiplier layer are disclosed herein. In particular, the present disclosure teaches an avalanche photodiode having a multiplier with alternating layers of one or more quantum wells and one or more spacers. A method of making the avalanche photodiode includes growing the multiplier on a substrate.
US10128394B2	Nanowire-based solar cell structure The solar cell structure according to the present invention comprises a nanowire (205) that constitutes the light absorbing part of the solar cell structure and a passivating shell (209) that encloses at least a portion of the nanowire (205). In a first aspect of the invention, the passivating shell (209) of comprises a light guiding shell (210), which preferably has a high- and indirect bandgap to provide light guiding properties. In a second aspect of the invention, the solar cell structure comprises a plurality of nanowires which are positioned with a maximum spacing between adjacent nanowires which is shorter than the wavelength of the light which the solar cell structure is intended to absorbing order to provide an effective medium for light absorption. Thanks to the invention it is possible to provide high efficiency solar cell structures.
US10128392B2	Method for manufacturing a thin film solar cell arrangement and such a thin film solar cell arrangement Solar cell arrangement of a thin film solar cell array on a substrate; each solar cell being layered with a bottom electrode, a photovoltaic active layer, a top electrode and an insulating layer. A first trench and a second trench parallel to the first trench at a first side, separate a first solar cell and an adjacent second solar cell. The first and second trenches are filled with insulating material. The first trench extends to the substrate. The second trench extends into the photovoltaic active layer below the top electrode. A third trench extending to the bottom electrode is between the first and second trench. A fourth trench extending to the top electrode is at a second side of the first trench. The third and fourth trench are filled with conductive material. A conductive bridge connects the third trench and the fourth trench across the first trench.
US10128388B2	Methods for treating a polycarbonate glass surface and forming directed hierarchical nanopatterning and increasing hydrophobicity A method of treating a polycarbonate glass surface, such as a bisphenol A polycarbonate, whereby the glass surface is immersed in a liquid phase polar aprotic solvent, such as dichloromethane, and exposed to a vapor phase polar aprotic solvent, such as acetone thus obtaining a textured glass surface with a hierarchical patterned nanoporous structure wherein the textured glass surface has a higher surface hydrophobicity and a marginally reduced optical light transmittance relative to the polycarbonate glass surface prior to the immersion, the exposure, or both.
US10128385B2	Lateral single-photon avalanche diode and method of producing a lateral single photon avalanche diode A semiconductor body of a first type of conductivity is formed including a base layer, a first further layer on the base layer and a second further layer on the first further layer. The base layer and the second further layer have an intrinsic doping or a doping concentration that is lower than the doping concentration of the first further layer. A doped region of an opposite second type of conductivity is arranged in the semiconductor body, penetrates the first further layer and extends into the base layer and into the second further layer. Anode and cathode terminals are electrically connected to the first further layer and the doped region, respectively. The doped region can be produced by filling a trench with doped polysilicon.
US10128384B2	Semiconductor device A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
US10128381B2	Semiconductor device with oxygen rich gate insulating layer A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes.
US10128374B2	Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
US10128370B2	Semiconductor device A semiconductor device capable of increasing a value of current that flows through the whole chip until a p-n diode in a unit cell close to a termination operates and reducing a size of the chip and a cost of the chip resulting from the reduced size, and including a second well region formed on both sides, as seen in plan view, of the entirety of a plurality of first well regions, a second ohmic electrode located over the second well region, a third separation region of a first conductivity type that is positioned closer to the first well regions than the second ohmic electrode in the second well region and that is formed to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode located on the third separation region.
US10128368B2	Double gate trench power transistor and manufacturing method thereof A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.
US10128365B2	Bypassed gate transistors having improved stability A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
US10128364B2	Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. Embodiments of a method of fabricating the semiconductor device include implanting one or more ion species through the first semiconductor layer to form the enhanced resistivity region.
US10128363B2	Field effect transistor Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0
US10128359B2	Semiconductor device with improved short circuit capability A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.
US10128357B2	Process for forming homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene.
US10128356B2	P-tunneling field effect transistor device with pocket Tunneling field effect transistors (TFETs) are described herein. In an example, a TFET includes a pocket disposed near a junction of a source region, wherein the pocket region is formed from a material having lower percentage of one type of atom than percentage of the one type of atom in source, channel, and drain regions.
US10128355B2	Method for forming fin field effect transistor (FINFET) device Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin structure extending above a substrate and forming an isolation structure over the substrate, and the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure. The method also includes forming a first transistor and a second transistor on the first fin structure and the second fin structure, and the first transistor includes a first gate dielectric layer. The method further includes forming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, and a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure.
US10128352B2	Gate tie-down enablement with inner spacer A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
US10128349B2	Semiconductor device A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor layer containing a crystalline oxide semiconductor with a corundum structure as a major component; and a Schottky electrode on the semiconductor layer, wherein the Schottky electrode is formed by containing a metal of Groups 4-9 of the periodic table, thereby manufacturing a semiconductor device excellent in semiconductor properties and Schottky characteristics without impairing the semiconductor properties to use the semiconductor device thus obtained for a power device and the like.
US10128346B2	Semiconductor device A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.
US10128337B2	Methods for forming fin structures with desired profile for 3D structure semiconductor applications Methods for forming fin structures with desired profile and dimensions for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure. In one embodiment, a method for forming a structure on a substrate includes performing an epitaxial deposition process to form a shaped structure on a fin structure disposed on a substrate, performing a mask layer deposition process to form a mask layer having a first width on the shaped structure, and performing a mask trimming process to trim the mask layer from the first width from a second width.
US10128336B2	Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.
US10128335B2	Nanowire semiconductor device including lateral-etch barrier region A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
US10128334B1	Field effect transistor having an air-gap gate sidewall spacer and method A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.
US10128332B2	Method for fabricating an improved field effect device A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.
US10128331B1	High-voltage semiconductor device and method for manufacturing the same A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.
US10128330B1	Semiconductor device with a buried junction layer having an interspersed pattern of doped and counter-doped materials A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.
US10128327B2	DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.
US10128325B2	Inductor structures for integrated circuits Multiple intertwined inductor coils combine to form one or more transformer devices of a semiconductor device. The intertwined inductor coils are formed of only two metallization layers and vias coupling the layers. The inductor coils are vertically oriented and include a magnetic axis parallel to the substrate surface. A plurality of metal wires are provided on both a first device level and a second device level. Each of the metal wires on the first device level is coupled to two wires on the second device level and forms a first inductor coil. The two metal wires on the second device level that form part of the first inductor coil, are separated by a third wire that is coupled to two different first device level metal wires and forms part of a different second inductor coil intertwined with the first inductor coil.
US10128317B2	Method for eliminating electrical cross-talk in OLED microdisplays An OLED microdisplay comprising a substrate, a pixel array and a patterned conductive layer underneath the anode pad array to form an effective ground plane in order to greatly reduce or eliminate electrical cross-talk between pixels, and a method for fabricating same.
US10128315B2	Methods of forming phase change memory apparatuses Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
US10128314B2	Vertical bipolar transistor The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
US10128313B2	Non-volatile memory device and structure thereof In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.
US10128311B2	Magnetic memory device According to one embodiment, a magnetic memory device includes a memory cell array unit including magnetoresistive elements provided in an array in first and second directions, each including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers, first transistors provided in an array in the first and second directions, and electrically connected to the magnetoresistive elements, respectively, switching units each electrically connected to corresponding ones of the first transistors in series, and each including at least one second transistor, wherein the first magnetic layers are separated from each other in the first and second directions, and the second magnetic layers are continuously provided in the first and second directions.
US10128309B2	Storage layer for magnetic memory with high thermal stability Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.
US10128308B1	Micro LED display device and method of fabricating the same The present invention relates to a puzzle-type micro light emitting diode (LED) display device which is capable of implementing a display having various sizes, the micro LED display device including: a micro LED panel in which a plurality of micro LED pixels is arranged in rows and columns; and a micro LED driving substrate (backplane) configured to include an active matrix (AM) circuit unit including a plurality of CMOS cells corresponding to the plurality of micro LED pixels, and a control circuit unit disposed in an outer region of the AM circuit unit, in which the control circuit unit is disposed to be adjacent to two sides among four sides of the micro LED panel.
US10128303B2	Light absorption apparatus A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.
US10128302B2	IR detector array device We disclose herein a thermal IR detector array device comprising a dielectric membrane, supported by a substrate, the membrane having an array of IR detectors, where the array size is at least 3 by 3 or larger, and there are tracks embedded within the membrane layers to separate each element of the array, the tracks also acting as heatsinks and/or cold junction regions.
US10128301B2	Semiconductor device, solid-state imaging device and electronic apparatus A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
US10128300B2	Solid-state image sensor, imaging device, and electronic equipment The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
US10128294B2	Light-receiving device array and light-receiving apparatus A light-receiving apparatus includes: a light-receiving device array including a semiconductor structure including a plurality of semiconductor mesas, a plurality of grooves each of which defines one of the semiconductor mesas, a plurality of first electrodes disposed on upper surfaces of the semiconductor mesas, a plurality of first bump electrodes disposed on the first electrodes, and a metal body disposed on a bottom surface of at least one of the grooves, the metal body being spaced apart from the first electrodes and the first bump electrodes; a semiconductor device processing an electric signal from the light-receiving device array; and an underfill disposed between the light-receiving device array and the semiconductor device. The metal body is spaced apart from a surface of the semiconductor device. The semiconductor device is joined to the light-receiving device array through the first bump electrodes.
US10128291B2	Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic device The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
US10128287B2	Physical layout and structure of RGBZ pixel cell unit for RGBZ image sensor An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region. The pixel cell unit has a fourth transfer gate transistor gate on the semiconductor surface coupled between a first infrared photodiode region and a second capacitance region.
US10128280B2	Display device and method for driving the same A semiconductor device having a configuration hardly generating variations in the current value due to a deteriorated EL element is to be provided. A capacitance element is disposed between the gate and the source of a driving TFT, video signals are inputted to the gate electrode, and then it is in the floating state. Suppose an EL element is deteriorated and the anode potential rises, that is, the source potential of the driving TFT rises, the potential of the gate electrode of the driving TFT, being in the floating state by coupling of the capacitance element, is to rise by the same amount. Accordingly, even when the anode potential rises due to the deteriorated EL element, the rise is added to the gate electrode potential as it is, and the gate-source voltage of the driving TFT is allowed to be constant.
US10128279B2	Display apparatus having a stepped part Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.
US10128278B2	Thin film transistor substrate and method of manufacturing the same A thin film transistor substrate includes a switching element comprising a gate electrode electrically connected to a gate line extending in a first direction, an active pattern overlapping with the gate electrode, a source electrode disposed on the active pattern and electrically connected to a data line extending in a second direction crossing the first direction, and a drain electrode spaced apart from the source electrode. The thin film transistor substrate further includes an organic layer disposed on the switching element, a first electrode disposed on the organic layer, and a second electrode overlapping with the first electrode, and electrically connected to the drain electrode. A thickness of the second electrode is thicker than a thickness of the first electrode.
US10128277B2	Display device A display device includes a plurality of gate lines extending in a first direction on the display area, a plurality of source lines extending in a second direction, a plurality of lead-out lines extending in the second direction and for transmitting gate signals to the plurality of gate lines. A plurality of connecting portions each electrically connects one gate line to one lead-out line. The plurality of connecting portions pass through a first insulating layer at a plurality of jointing points which are selected among a plurality of overlapping points where the plurality of lead-out lines and the plurality of gate lines overlap in a plane area.
US10128275B2	Display device A display device is provided. The display device includes a display region, a first conductive loop disposed outside the display region, wherein the first conductive loop includes at least one first conductive block and at least two second conductive blocks, wherein a dielectric layer is disposed between the at least one first conductive block and the at least two second conductive blocks and has at least two via holes, and wherein the at least two second conductive blocks are electrically connected the at least one first conductive block by the at least two via holes.
US10128274B2	Thin film transistor array panel and a method for manufacturing the same A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part.
US10128272B2	Thin film transistor array substrate, method for fabricating the same and display device Disclosed are a TFT array substrate, a method for fabricating the same and a display device. The TFT array substrate includes a plurality of pixel units, each of the plurality of pixel units includes a common electrode (9). The common electrode (9), is comb-shaped, and includes a plurality of strip electrodes and a plurality of slits. Each of the strip electrodes is configured for reflecting light incident on the strip electrode, and each of the slits is configured for transmitting light incident on the slit. As the comb-shaped common electrode with both a reflective region and a transmissive region is formed through a single patterning process, the fabrication process is simplified and the fabrication cost and difficulty are reduced.
US10128266B2	Three-dimensional semiconductor memory device A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.
US10128265B2	Memory cells, integrated structures and memory arrays Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.
US10128261B2	Cobalt-containing conductive layers for control gate electrodes in a memory structure A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
US10128260B2	Semiconductor device A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.
US10128259B1	Method for manufacturing embedded memory using high-K-metal-gate (HKMG) technology A method for manufacturing embedded memory using high-κ-metal-gate (HKMG) technology is provided. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. The control gate includes a first material. A gate layer is formed of the first material, and is formed covering the semiconductor substrate and the gate stack. The gate layer is recessed to below a top surface of the gate stack, and subsequently patterned to form a select gate bordering the control gate and to form a logic gate spaced from the select and control gates. An ILD layer is formed between the control, select, and logic gates, and with a top surface that is even with top surfaces of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate of a second material.
US10128256B2	One-time programming cell A one-time programming cell includes a first metal oxide semiconductor (MOS) structure and a second transistor having a common gate electrode electrically connected to a word line. The first MOS structure has a first gate dielectric layer and the second MOS structure has a second gate dielectric layer. The second gate dielectric layer is thicker than the first gate dielectric layer. Source nodes of the first MOS structure and the second MOS structure are electrically connected, and a drain node of the second MOS structure is electrically connected to a bit line.
US10128251B2	Semiconductor integrated circuit structure and method for forming the same A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.
US10128248B1	Aging tolerant apparatus An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.
US10128246B2	Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.
US10128240B2	Semiconductor device and method for fabricating the same A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.
US10128237B2	Methods of gate replacement in semiconductor devices A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.
US10128236B2	Semiconductor device and method for fabricating the same A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
US10128234B2	Electromigration resistant semiconductor device A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.
US10128231B2	Integrated semiconductor device and manufacturing method therefor An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.
US10128229B1	Semiconductor devices with package-level configurability A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.
US10128226B2	Mechanisms for forming package structure A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die.
US10128219B2	Multi-chip module including stacked power devices with metal clip A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.
US10128217B2	Memory devices with controllers under memory packages and associated systems and methods Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.
US10128215B1	Package including a plurality of stacked semiconductor devices having area efficient ESD protection A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient. Furthermore, by only placing ESD protection circuitry on a bottom chip in a stack of semiconductor chips, ESD protection circuitry may not be included on other chips, so that total area may be reduced and more chips may be produced on a single silicon wafer.
US10128214B2	Substrate and the method to fabricate thereof The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
US10128209B2	Wafer bonding process and structure A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
US10128193B2	Package structure and method for forming the same A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.
US10128192B2	Fan-out package structure A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
US10128191B2	Package-on-package type package including integrated circuit devices and associated passive components on different levels A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.
US10128187B2	Integrated circuit structure having gate contact and method of forming same One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.
US10128179B2	Fan-out semiconductor package and electronic device including the same A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.
US10128178B2	Electronic package and method for fabricating the same An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.
US10128174B2	Semiconductor component and method of manufacture In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
US10128166B2	Power semiconductor module A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.
US10128164B2	Electronic device and method of manufacturing the electronic device An electronic component has a semiconductor element and a thermally conductive support member. A heat sink is disposed on one surface of the circuit body, and a thermally conductive insulating member is interposed between the heat sink and the support member. Input and output terminals and a ground terminal are also provided. A sealing resin is formed to expose a part of each of the input and output terminals and the ground terminal and one surface of the heat sink, and to cover a periphery of the electronic component structure. A main body conductor layer is formed to be insulated from the input and output terminals and cover an immersion region of the sealing resin and one surface of the heat sink immersed in a cooling medium. A ground conductor layer covers at least a part of the ground terminal and is electrically connected with the main body conductor layer.
US10128161B2	3D printed hermetic package assembly and method A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.
US10128158B2	Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
US10128156B1	FinFET device with reduced parasitic capacitance and method for fabricating the same A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.
US10128155B2	Integrated circuit device and method of fabricating the same An integrated circuit device includes: a first fin-type active region in a first area of a substrate, the first fin-type active region having a first recess filled with a first source/drain region; a first device isolation layer covering both lower sidewalls of the first fin-type active region; a second fin-type active region in a second area of the substrate, the second fin-type active region having a second recess filled with a second source/drain region; a second device isolation layer covering both lower sidewalls of the second fin-type active region; and a fin insulating spacer on the first device isolation layer, the fin insulating spacer covering a sidewall of the first fin-type active region under the first source/drain region.
US10128153B2	Method of fabricating a semiconductor device and the semiconductor device a method of fabricating a semiconductor device is described below.The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves.The device and the method can provide higher productivity.
US10128150B2	Process of filling the high aspect ratio trenches by co-flowing ligands during thermal CVD Implementations of the present disclosure generally relate to methods for forming thin films in high aspect ratio feature definitions. In one implementation, a method of processing a substrate in a process chamber is provided. The method comprises flowing a boron-containing precursor comprising a ligand into an interior processing volume of a process chamber, flowing a nitrogen-containing precursor comprising the ligand into the interior processing volume and thermally decomposing the boron-containing precursor and the nitrogen-containing precursor in the interior processing volume to deposit a boron nitride layer over at least one or more sidewalls and a bottom surface of a high aspect ratio feature definition formed in and below a surface of a dielectric layer on the substrate.
US10128148B2	Methods for fabricating semiconductor devices including surface treatment processes Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.
US10128146B2	Semiconductor substrate polishing methods and slurries and methods for manufacturing silicon on insulator structures Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.
US10128145B2	Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
US10128143B2	Wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer Temporary adhesive material for wafer processing, the temporary adhesive material being used for temporarily bonding support to wafer having circuit-forming front surface and back surface to be processed, including complex temporary adhesive material layer that has first temporary adhesive layer composed of thermosetting siloxane polymer layer (A), second temporary adhesive layer composed of thermosetting polymer layer (B), and third temporary adhesive layer composed of thermoplastic resin layer (C), wherein the polymer layer (A) is cured layer of composition containing (A-1) an organopolysiloxane having alkenyl group within its molecule, (A-2) an organopolysiloxane having R103SiO0.5 unit and SiO2 unit, (A-3) organohydrogenpolysiloxane having two or more Si—H groups per molecule, and (A-4) platinum-based catalyst. There can be provided a wafer processing laminate, temporary adhesive material for wafer processing, and method for manufacturing thin wafer using the same which facilitate temporary adhesion and delamination, has excellent CVD resistance, and increasing productivity of thin wafers.
US10128138B2	Substrate transfer method and storage medium A substrate transfer method is provided. The substrate transfer method comprises: loading the transfer container to a load port, and separating the cover body from the container main body; detecting an accommodation status of the substrate in the container main body by a detection unit; correcting, by a correction device, the accommodation status of the substrate in the container main body in which the accommodation status of the substrate detected by the detection unit is abnormal; and allowing a substrate transfer device to enter the container main body in which the accommodation status of the substrate is corrected, and unloading the substrate from the container main body.
US10128135B2	Heat treatment method and heat treatment device First, a substrate with one main surface on which a thin film of at least one of a mono-molecular layer and a multi-molecular layer including dopants is formed is prepared. Subsequently, the prepared substrate is placed in a chamber, and dopants included in the thin film are introduced from the thin film into a surface layer of the substrate by providing the substrate, through irradiation with light from a first lamp, with preliminary heat treatment in a first temperature band higher than a temperature before heating. Then, the dopants introduced into the surface layer of the substrate are activated by heating the substrate provided with the preliminary heat treatment and placed in the chamber from the first temperature band to a second temperature band higher than the first temperature band through irradiation with flash light from a second lamp.
US10128131B2	Sealing sheet with separators on both surfaces, and method for manufacturing semiconductor device A sealing sheet with separators on both surfaces is provided with a sealing sheet, a separator (A) stacked on one surface of the sealing sheet and having a thickness of 50 μm or more, and a separator (B) stacked on the other surface of the sealing sheet.
US10128127B2	Thin-film transistor substrate manufacturing method and thin-film transistor substrate manufactured with same A thin-film transistor (TFT) substrate includes a backing plate, a gate electrode formed on the backing plate, a gate insulation layer formed on the gate electrode and the backing plate, an active layer formed on the gate insulation layer, a source electrode and a drain electrode formed on the active layer and the gate insulation layer, a passivation layer formed on the source electrode, the drain electrode, the active layer, and the gate insulation layer, and a pixel electrode formed on the passivation layer. The gate insulation layer is formed of a material that is an oxide of a material that makes the gate electrode. The passivation layer is formed of a material that is an oxide of a material that makes the source electrode and the drain electrode.
US10128123B2	Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.
US10128116B2	Integrated direct dielectric and metal deposition Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
US10128115B2	Method of forming ultra-shallow junctions in semiconductor devices A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.
US10128114B2	Amorphization induced metal-silicon contact formation A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.
US10128112B2	Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.
US10128110B2	Method to enhance growth rate for selective epitaxial growth Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
US10128108B2	Oxide sintered body, sputtering target, and oxide semiconductor thin film obtained using sputtering target Provided are an oxide sintered compact whereby low carrier density and high carrier mobility are obtained when the oxide sintered compact is used to obtain an oxide semiconductor thin film by a sputtering method, and a sputtering target which uses the oxide sintered compact. This oxide sintered compact contains oxides of indium, gallium, and aluminum. The gallium content is from 0.15 to 0.49 by Ga/(In+Ga) atomic ratio, and the aluminum content is from 0.0001 to less than 0.25 by Al/(In+Ga+Al) atomic ratio. A crystalline oxide semiconductor thin film formed using this oxide sintered compact as a sputtering target is obtained at a carrier density of 4.0×1018 cm−3 or less and a carrier mobility of 10 cm−2V−1sec−1 or greater.
US10128103B2	Apparatus and process for wafer cleaning A process and apparatus for cleaning a wafer, the wafer having a front side and a back side, are provided. The process begins with placing the wafer on a platform, and a first gas stream delivering in a direction from a center to an edge of the front side of the wafer. The first gas stream prevents liquid drops entering a work piece region on the front side of the wafer and protects the integrity of the integrated circuits. A cleaning brush is rinsed by a first liquid stream and contacting the edge of the wafer for cleaning the wafer. The cleaning brush scrubs unwanted residual materials from the edge of the wafer, and the first liquid stream flushes the cleaning brush to recover the cleaning ability.
US10128102B2	Methods and apparatus for wetting pretreatment for through resist metal plating Disclosed are pre-wetting apparatus designs and methods for cleaning solid contaminants from substrates prior to through resist deposition of metal. In some embodiments, a pre-wetting apparatus includes a process chamber having a substrate holder, and at least one nozzle located directly above the wafer substrate and configured to deliver pre-wetting liquid (e.g., degassed deionized water) onto the substrate at a grazing angle of between about 5 and 45 degrees. In some embodiments the nozzle is a fan nozzle configured to deliver the liquid to the center of the substrate, such that the liquid first impacts the substrate in the vicinity of the center and then flows over the center of the substrate. In some embodiments the substrate is rotated unidirectionally or bidirectionally during pre-wetting with multiple accelerations and decelerations, which facilitate removal of contaminants.
US10128101B2	Dimmable induction RF fluorescent lamp with reduced electromagnetic interference A dimmable induction RF fluorescent light bulb comprising a power coupler with reduced extraneous electromagnetic radiation wherein a dimming facility utilizes burst-mode dimming that periodically interrupts the high frequency voltage and current to the power coupler with an off period and an on period in order to reduce the power being delivered to the power coupler wherein the off period is shorter than the time required for an electron density of the discharge within the lamp envelope to substantially decrease.
US10128100B2	Drive method and drive circuit for light-emitting device using gas discharge, and ultraviolet irradiation device During a normal operation, alternating drive voltage to be applied between a pair of electrodes provided to face an outer surface of a bottom part of a gas discharge light emitting tube is switched to a voltage value V2 lower than a voltage value V1 at the time of starting lighting. Further, the alternating drive voltage to be applied during the normal discharge operation is intermittently applied in a predetermined cycle and duty ratio to enable adjustment of light emission intensity.
US10128096B2	System and method for ionization of molecules for mass spectrometry and ion mobility spectrometry An ionizing system includes a channel and a heater coupled to the channel. The channel has an inlet disposed in a first pressure region having a first pressure and an outlet disposed in a second pressure region having a second pressure. The first pressure is greater than the second pressure. The heater is for heating the channel, and the channel is configured to generate charged particles of a sample in response to the sample being introduced into the channel.
US10128093B2	Method for deconvolution Systems and methods prevent potentially convolved precursor ion peaks from being excluded in subsequent cycles of an IDA experiment so that additional product ion data is collected. A sample is ionized producing an ion beam. A plurality of cycles of an IDA experiment are performed on the ion beam. During each cycle of the IDA experiment and for each precursor ion peak on a filtered peak list produced in the filtering step of each cycle, several steps are performed. The precursor ion peak is identified in the precursor ion spectrum produced in the MS survey scan step of the cycle. It is determined if the precursor ion peak in the precursor ion spectrum includes a feature of convolution. If the precursor ion peak includes a feature of convolution, the precursor ion peak is prevented from being excluded in a filtering step of one or more subsequent cycles.
US10128089B2	Plasma processing apparatus There is provided a plasma processing apparatus including a focus ring capable of preventing a part of a heat transfer sheet from adhering to and remaining on a mounting table. The plasma processing apparatus comprises: a chamber for performing a plasma process on a target object; a mounting table configured to mount thereon the target object; and a focus ring configured to surround the target object, the focus ring being in contact with the mounting table via a flexible heat transfer sheet. Further, the heat transfer sheet has a contact surface in contact with the mounting table and an anti-adhesion layer formed on the contact surface, and the anti-adhesion layer is located between said contact surface of the heat transfer sheet and a mounting surface of the mounting table. Furthermore, the anti-adhesion layer contains heat conductive particulates, and the heat transfer sheet is formed in an annular shape.
US10128083B2	Ion sources and methods for generating ion beams with controllable ion current density distributions over large treatment areas The presently disclosed ion sources include one or more electromagnets for changing the distribution of plasma within a discharge space of an ion source. At least one of the electromagnets is oriented about an outer periphery of a tubular sidewall of the ion source and changes a distribution of the plasma in a peripheral region of the discharge space.
US10128079B2	MEMs frame heating platform for electron imagable fluid reservoirs or larger conductive samples A heating device having a heating element patterned into a robust MEMs substrate, wherein the heating element is electrically isolated from a fluid reservoir or bulk conductive sample, but close enough in proximity to an imagable window/area having the fluid or sample thereon, such that the sample is heated through conduction. The heating device can be used in a microscope sample holder, e.g., for SEM, TEM, STEM, X-ray synchrotron, scanning probe microscopy, and optical microscopy.
US10128075B2	Ion generation device having attachment devices The present invention provides methods and systems for an ion generator device that includes a base, a generally circular sidewall projecting from the base forming an interior storage compartment and defining an upper edge, a top portion engaged to the upper edge, at least one high voltage wire extending from the device, and a power supply for providing a voltage to the high voltage wire for producing ions.
US10128064B2	Keyboard assemblies having reduced thicknesses and method of forming keyboard assemblies Keyboard assemblies having reduced thicknesses and methods of forming the same. A keyboard assembly may include a printed circuit board (PCB) and a single membrane sheet adhered directly to the PCB. The single membrane sheet may substantially cover the PCB. The keyboard assembly may also include a group of dome switches coupled directly to the single membrane sheet. Another keyboard assembly may include a group of conductive pads and a group of membrane pads. Each of the group of membrane pads may be adhered directly to a corresponding one of the group of conductive pads. The keyboard assembly may also include a group of dome switches coupled directly to the membrane pads. Each of the group of dome switches may be coupled directly to a corresponding one of the group of membrane pads.
US10128060B2	Light switch cover A light switch cover includes a base portion defining a central opening and including a first base engagement member and a second base engagement member, a cover pivotally coupled to the base portion, a first cover engagement member positioned on the cover, where the first cover engagement member has a complementary shape to the first base engagement member, and where the first cover engagement member is selectively engaged with the first base engagement member when the cover is in the closed position, and a second cover engagement member positioned on the cover, where the second cover engagement member has a complementary shape to the second base engagement member, and where the second cover engagement member is selectively engaged with the second base engagement member when the cover is in the closed position.
US10128057B2	Supercapacitor with movable separator and method of operating a supercapacitor A supercapacitor including: a shell; a chamber in the shell; a first electrode and a second electrode on respective walls of the chamber; and a separator arranged between the first electrode and the second electrode through the chamber. The separator includes a first perforated membrane and a second perforated membrane, which is movable with respect to the first membrane between a first position, in which the first membrane and the second membrane are separate and a second position, in which the first membrane and the second membrane are in contact and coupled for rendering the separator impermeable.
US10128055B1	Electrolytic capacitor An electrolytic capacitor includes a body having a casing and a capacitor core. The casing includes a side having an opening intercommunicated with a receiving space of the casing in which the capacitor core is mounted. The sealing cover is mounted in the opening and includes a lid and an enveloping member. The lid includes a first side adjacent to the capacitor core, a second side, and an outer periphery extending between the first side and the second side of the lid. The enveloping member is securely engaged with the lid by insert molding. The enveloping member is engaged with the first side, the second side, and the outer periphery of the lid.
US10128052B1	Methods of thermally induced recrystallization A method for thermally induced recrystallization of a film having a perovskite structure can include exposing the perovskite structure to a liquid phase induction atmosphere sufficient to at least partially liquefy the film. The substrate with the film can be heated while in the atmosphere to a heating temperature above a critical recrystallization temperature until the film recrystallizes to reform the perovskite structure with reduced defects and increased grain size. The liquid phase induction atmosphere can be purged, and the substrate with the film having the reformed perovskite structure can be allowed to cool. The film having the perovskite structure can have a formula ABX3, (RA)2An−1BnX3n+1, or (RA2)An−1BnX3n+1, where A is a monovalent cation, B is divalent metal cation, n is an integer, X is a halide ion, RA is an alkylammonium cation and RA2 is an alkyldiammonium cation.
US10128048B2	Multilayer capacitor and board having the same A multilayer capacitor includes a body including a capacitor body formed by layering a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the capacitor body and disposed to be spaced apart from each other, respectively; and first, second and third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the first, second and third external electrodes each include first, second and third electrode layers which are sequentially stacked, the first and second electrode layers containing metal and glass particles, and the third electrode layer containing a conductive resin.
US10128047B2	Methods and systems for increasing surface area of multilayer ceramic capacitors Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Layers of a capacitor may be modified from its traditional planar shape to a wavy structure. The wavy shape increases surface area within a fixed volume of the capacitor, thus increasing capacitance, and may comprise smooth and repetitive oscillations without the presence of voltage-degrading sharp corners. In addition, the ends of each conductive layer do not have sharp edges, such as comprising of a round corner. The one-dimensional wave pattern may run parallel to the width of the capacitor, or it may align in parallel to the length of the capacitor. In some embodiments, the wave pattern may be parallel to both the width and the length—in two dimensions—such that it forms an egg-crate shape. Further, the wavy structures may comprise of secondary or tertiary wavy structures to further increase surface area.
US10128046B2	Wound/stacked ceramic film capacitors, method for making ceramic film capacitors The invention provides a process for making ceramic film capacitors, the process comprising supplying a flexible substrate, depositing a first electrode on a first region of the flexible substrate, wherein the first electrode defines a first thickness, overlaying the first electrode with a dielectric film; and depositing a second electrode on the ceramic film, wherein the second electrode defines a second thickness. Also provided is a capacitor comprising flexible substrate, a first electrode deposited on said flexible substrate, a dielectric overlaying the first electrode; and a second electrode deposited on said dielectric.
US10128044B2	Film capacitor and the method of forming the same A film capacitor is presented. The film capacitor includes a thermally conductive support. The thermally conductive support includes a core including a first end and a second end. The thermally conductive support further includes a protrusion extending from at least one of the first end and the second end of the core, where at least one of the core and the protrusion includes a phase change material. Further, the film capacitor also includes a plurality of films disposed on at least a portion of the thermally conductive support, where the plurality of films includes a plurality of electrode films and a dielectric film. Further, the thermally conductive support for the film capacitor and a method of forming the film capacitor are also presented.
US10128043B2	Chip-type electronic component A chip-type electronic component 1a mounted on a board includes a chip element assembly 2 having an upper surface, a lower surface, and a side surface; inner electrodes 3a, 3b, and 3c formed inside the chip element assembly 2; and a cover layer 5 that is formed with an insulation material having a lower permittivity than the chip element assembly 2 and is so provided as to cover at least part of the side surface of the chip element assembly 2. With this structure, unnecessary stray capacitance between the inner electrodes 3a, 3b, and 3c formed inside the chip element assembly 2 and other electrode members arranged outside the cover layer 5 in a direction orthogonal to a thickness direction of the chip element assembly 2 can be reduced, whereby the chip-type electronic component 1a capable of realizing the desired characteristics can be provided.
US10128041B2	Magnetic core and method for producing the same A magnetic core includes soft magnetic material particles each including a soft magnetic material and an insulating film on a surface of the soft magnetic material, the insulating film having a thickness in the range of 10 nm or more and 100 nm or less; and a binder that binds the soft magnetic material particles together and contains a non-silicate glass having a softening point in the range of 350° C. or higher and 500° C. or lower. The soft magnetic material contains an amorphous phase and has a transition temperature of 600° C. or lower at which a crystal structure changes, and the magnetic core has a resistivity of 107 Ωcm or more.
US10128040B2	Inductor bridge and electronic device An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.
US10128036B2	AC permanent magnet gain transformer device and its voltage regulation and control method An AC permanent magnet gain transformer device and its voltage regulation and control method. This device adds permanent magnet or permanent magnet assembly to the structure of traditional transformer, the magnetic pole surface of permanent magnet closely clings to laminated iron core, so that the intrinsic permanent magnetic potential of permanent magnet could be elicited under the excitation of the excitation current of primary winding, overlapped and compounded with excitation magnetic potential in the general magnetic loop of closed-loop laminated iron core, and so, it's able to induce the induction electromotive force formed after the superposition of excitation flux and permanent magnet flux at the output end of secondary winding. The method for voltage regulation and control of this invention is to: input a certain amplitude of pulse current to the primary winding in order to guarantee the generation of compound excitation effect, and change the pulse count of pulse current per unit time in order to change and adjust the input and output power of this AC permanent magnet gain transformer device. This AC permanent magnet gain transformer device and its voltage regulation and control method further enhance the power transfer efficiency of transformer device, thus make up the intrinsic spoilage of traditional winding coil and laminated iron core, and save energy.
US10128034B2	Heat dissipation device A heat dissipation device is applied to an electronic device and comprises a heat conduction plate, at least an induction coil and a first heat dissipation plate. The heat conduction plate receives the heat provided by a heat source and includes a first contact element disposed on a first surface of the heat conduction plate. The induction coil is disposed at the heat conduction plate. The first heat dissipation plate is disposed at the first contact element of the heat conduction plate. The first heat dissipation plate and the heat conduction plate form a gap. The first heat dissipation plate includes at least a first magnetic element disposed opposite the induction coil.
US10128030B2	Superconducting magnet coil system A superconducting magnet coil system with high resistance to quench events includes a first coil portion (1) with a first superconducting material and a second coil portion (2) with a second superconducting material. The first superconducting material has a higher critical temperature than the second superconducting material. The first and the second coil portions are bridged by a common quench protection element (6) and together with the quench protection element form a first loop. The magnet coil system also includes a third coil portion (3) which is part of a second electrical loop with a second quench protection element (8, 8′, 8″)as well as a heating element (9) which is supplied with a heating voltage in response to a quench of the third coil portion. Among the series connected coil portions (1, 2) only the second coil portion is in thermal contact with the first heating element (9).
US10128027B2	Electrical wire holder There is provided an electric wire holder for holding electric wires connected to terminal fittings at end portions of the wires, the holder configured to attach to a shielding pipe to cover an edge of the shielding pipe into which the electric wires are inserted and from which the terminal fittings and a portion of the electric wires are drawn out to an outside of the shielding pipe, the holder comprising: a first holding piece configured to hold the portion of the electric wires that is drawn out from the shielding pipe and to fix a draw-out position of the terminal fittings.
US10128026B2	Superconducting wire A superconducting wire having improved electrical and physical properties.
US10128025B2	Oxide superconducting wire, superconducting device, and method for producing oxide superconducting wire An oxide superconducting wire includes: a laminate which is formed by laminating a tape-shaped base, an intermediate layer, and an oxide superconducting layer; a first protective layer which is formed of Ag or an Ag alloy and is laminated on a main surface of the oxide superconducting layer of the laminate; a second protective layer which is formed of Cu or a Cu alloy, is laminated on a main surface of the first protective layer by performing film formation one or more times, and has a thickness of 0.3 μm to 10 μm; and a stabilization layer which is bonded to a main surface of the second protective layer with a solder layer interposed therebetween, wherein the second protective layer is formed to have a thickness of equal to or less than 2.1 μm per film formation.
US10128023B2	Water barrier for submarine power cable An cable that is flexible and watertight by means of a metallic water resistant barrier has at least two protective layers 20, 30 of metal tape wound to a cable core 10 with small gaps 50 between each turn of the tape, and where each layer is displaced 50% relative to each other thus covering the gaps in the layers 20, 30, and where the gaps 50 are filled with a water resistant material.
US10128021B2	Polyester for profile extrusion and/or pipe extrusion Thermoplastic molding compositions containing A) from 29 to 99.99% by weight of a polyester, B) from 0.01 to 3.0% by weight of an alkali metal salt of nitrous acid or of phosphoric acid or of carbonic acid, or a mixture of these, based on 100% by weight of A) and B), and C) from 0 to 70% by weight of further additives, where the sum of the % by weight values for A) to C) is 100%. The compositions are used in the production of cable sheathing or optical waveguide sheathing via blowmolding, profile extrusion, and/or tube extrusion.
US10128020B2	Electrical apparatus An electrical apparatus that includes a cable connected to a transmission optimizer and configured to conduct a current for matching a desired power output. The cable includes at least one insulated conductor core including an innermost insulating layer disposed around the outside of a conducting layer having carbon fiber or graphite fiber as a conductor core. The cable is a single core cable having a single insulated conductor core or a multi-core cable having multiple single insulated conductor cores.
US10128018B2	Copper alloy wire, copper alloy stranded wire, covered electric wire, and terminal-fitted electric wire A copper alloy wire can be used as a conductor. The copper alloy wire is made of a copper alloy containing: not less than 0.4 mass % and not more than 1.5 mass % of Fe; not less than 0.1 mass % and not more than 0.7 mass % of Ti; not less than 0.02 mass % and not more than 0.15 mass % of Mg; not less than 10 mass ppm and not more than 500 mass ppm in total of C and at least one of Si and Mn; and the balance of Cu and impurities. The copper alloy wire has a wire diameter of not more than 0.5 mm. Preferably, a mass ratio Fe/Ti in the copper alloy is not less than 1.0 and not more than 5.5.
US10128017B1	Apparatus for and method of controlling debris in an EUV light source Disclosed is an EUV system in which a source control loop is established to maintain and optimize debris flux while not unduly affecting optimum EUV generation conditions. One or more temperature sensors, e.g., thermocouples may be installed in the vessel to measure respective local gas temperatures. The respective local temperature as measured by the one or more thermocouples can be used as one or more inputs to the source control loop. The source control loop may then adjust the laser targeting to permit optimization of debris generation and deposition while not affecting EUV production, thus extending the lifetime of the source and its collector.
US10128016B2	EUV element having barrier to hydrogen transport Disclosed is an EUV system element having a hydrogen diffusion barrier including a region implanted with species (e.g., ions energetic neutral atoms) of a non-hydrogen gaseous material. Also disclosed is a method of making such a component including the step of implanting species of a non-hydrogen gaseous material to form a hydrogen diffusion barrier and a method of treating an EUV system element including the step of implanting species of a non-hydrogen gaseous material to prevent hydrogen adsorption and diffusion. Also disclosed is subjecting an EUV system element to a flux of non-hydrogen gas ions to displace hydrogen ions in one or more layers of the EUV system element with the non-hydrogen gas species so that the gas ions protect the EUV system element against hydrogen damage.
US10128014B2	Controlling movement of carriage of multi-leaf collimator Methods and devices for controlling movement of a carriage of a multi-leaf collimator are provided. In one aspect, a method includes obtaining a desired position of each of a set of leaves on the carriage in each of a plurality of segments from a field, determining an allowable moving range set of the carriage according to the desired position, the allowable moving range set including a respective allowable moving range of the carriage in each of the segments, determining a respective position of the carriage in each of the segments according to the allowable moving range set, and controlling the movement of the carriage according to the determined positions of the carriage in the segments.
US10128012B2	Method of using a modular container system for radioactive waste A packaging system for radioactive waste is robust, highly functional, and can be used for nearly all radioactive waste streams that require shielded packaging. The packaging system includes a modular container that is configured to receive modular shielding inserts. The packaging system can be used to store, transport, and dispose of radioactive waste.
US10128011B2	Device for supporting packaging for transporting/storing radioactive materials, including a shroud for guiding air for cooling the packaging by natural convection The invention relates to a device (3) for supporting packaging for transporting/storing radioactive materials (1) in a horizontal position, the supporting device including a structural base (10) and structures (12) for supporting the packaging, which structures are supported by the base (10) and project upwards therefrom. According to the invention, the device also includes, located at least in part above the structural base (10), a shroud (30) for guiding air for cooling the packaging by natural convection, the shroud (30) defining a recess (32) which is open towards the top and into which a portion of the packaging is intended to be inserted when the packaging (1) is supported in a horizontal position on the device, the shroud (30) including, at the bottom thereof, at least one opening (34) for allowing cooling air into the recess (32).
US10128006B2	Cryogenic system for spent nuclear fuel pool emergency cooling and safety system An emergency spent nuclear fuel pool cooling system that requires no external electrical power source and relies on the expansion of a cryogenic fluid through an evaporator/heat exchanger submerged within the spent fuel pool, to power various components used to cool the spent fuel pool and adjacent areas and provide makeup water to the spent fuel pool. Other than the evaporator/heat exchanger to which the cryogenic fluid is connected, the remaining components employed to cool the pool and the surrounding area and provide makeup water can be contained in a relatively small, readily transportable skid.
US10128002B2	Subcutaneous outpatient management A method of administering insulin includes receiving subcutaneous information for a patient at a computing device and executing a subcutaneous outpatient program for determining recommended insulin dosages. The subcutaneous outpatient program includes obtaining blood glucose data of the patient from a glucometer in communication with the computing device, aggregating blood glucose measurements to determine a representative aggregate blood glucose measurement associated with at least one scheduled blood glucose time interval, and determining a next recommended insulin dosage for the patient based on the representative aggregate blood glucose measurement and the subcutaneous information. The method also includes transmitting the next recommended insulin dosage to a portable device associated with the patient. The portable device displays the next recommended insulin dosage.
US10127999B2	Nonvolatile memory and semiconductor device including the same A semiconductor device includes a usable address storage unit for selectively storing addresses of a plurality of memory sets using read data of the plurality of memory sets outputted from a nonvolatile memory during a boot-up operation; a register unit for storing the read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation; and an internal circuit for operating by using the read data of the plurality of memory sets stored in the register unit. Addresses corresponding to usable memory sets excluding already-used memory sets and defective memory sets among the memory sets of the nonvolatile memory are extracted and stored, and thus, although an address is not separately inputted when the nonvolatile memory is programmed, data may be programmed in a programmable (usable) memory set.
US10127995B2	Shift register unit and method for driving the same, corresponding gate driving circuit and display device The disclosure discloses a shift register and a method for driving the same, a corresponding gate driving circuit and a display device. In the shift register, a pull-up driving unit is connected with a pull-up unit via a pull-up node, a discharge auxiliary unit is used for pulling low the potential of the pull-up node according to a discharge control signal, a discharge driving unit is used for pulling high the potential of a gate line connected with the signal output terminal of the shift register according to the discharge control signal, and a reset unit is further used for pulling low again the potential of the gate line connected with the signal output terminal of the shift register, after the discharge driving unit pulls high the potential of the gate line and the outputting of it finishes.
US10127993B2	Dielectric fuse memory circuit and operation method thereof One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.
US10127990B1	Non-volatile memory (NVM) with dummy rows supporting memory operations A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.
US10127986B1	Memory device and operating method including a partial program operation and a partial erase operation thereof There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.
US10127981B2	Method, system and device for non-volatile memory device operation Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
US10127979B2	Memory cell located pulse generator The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of transistors is disclosed that allows the transistor pulse signal generator circuit to precharge both sides of the memory cell and, subsequently, bring opposite sides of the memory cell quickly to different voltages. The circuit and wiring fabrication provided, when combined with a related transistor manufacturing process, yields pulse generating logic at the memory cell to enable the formation of a well-defined pulse while fitting within the 4F2 footprint of the memory cell. As such, the speed and pulse shape requirements of PCM, MRAM, other such cross-point memory technologies, sensor arrays, and/or pixel displays may take advantage of the reduced RC circuitry delays.
US10127975B2	Determination circuit A determination circuit of one embodiment includes first and second inverter circuits, a first transistor which turns on when receiving an asserted first signal, and a first capacity component including a first end which receives an inversion signal of the first signal. The second inverter circuit includes an input coupled to an output of the first inverter circuit, and includes an output coupled to an input of the first inverter circuit. The first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node.
US10127974B2	Memory device and memory system performing request-based refresh, and operating method of the memory device Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.
US10127972B2	Apparatuses and methods including two transistor-one capacitor memory and for accessing same Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
US10127965B2	Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
US10127964B2	Circuitry for ferroelectric FET-based dynamic random access memory and non-volatile memory Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.
US10127962B2	Unidirectional spin torque transfer magnetic memory cell structure Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
US10127959B2	Sense amplifier Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.
US10127957B2	Control method for magnetoresistance effect element and control device for magnetoresistance effect element A control method for a magnetoresistance effect element and a control device for the magnetoresistance effect element that provide a higher writing speed and lower power consumption. When the magnetization direction of a second magnetic layer is nearly parallel to the magnetization direction of a first magnetic layer, a first voltage is applied across the first and second magnetic layer so that the magnetization direction of the second magnetic layer is reversed by modifying the direction of the magnetization easy axis thereof, followed by the application of a second voltage. When the magnetization direction of the second magnetic layer is nearly antiparallel to the magnetization direction of the first magnetic layer, a third voltage is applied across the first magnetic layer and the second magnetic layer, followed by the application of a fourth voltage so that current flows from the second magnetic layer toward the first magnetic layer.
US10127956B2	Spin orbit torque magnetic memory device A magnetic memory device may include tunnel junction unit cells, each including a pinned magnetic layer, an insulating layer, and a free magnetic layer which are sequentially stacked, a conductive line structure configured to supply an in-plane current to the unit cells and to include an antiferromagnetic layer, which is provided adjacent to the free magnetic layer, and a ferromagnetic layer, which is provided adjacent to the antiferromagnetic layer and has an in-plane magnetic anisotropy, and a voltage applying unit configured to independently apply a selection voltage to each of the tunnel junction unit cells. Each of the tunnel junction unit cells may have a magnetization direction that is selectively changed by the in-plane current and the selection voltage.
US10127955B2	Memory activation method and apparatus, and memory controller A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.
US10127954B2	Quantizing circuits having improved sensing A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. The quantizing circuit includes a combination circuit configured to combine an analog input signal with an analog feedback signal to produce a delta signal. The quantizing circuit also includes an integrator configured to receive and integrate the delta signal to produce a sigma signal. The quantizing circuit also includes an analog-to-digital converter configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal.
US10127953B2	Circuit for selecting a power supply voltage having a controlled transition A voltage selection circuit, including: first and second nodes of application of first and second input voltages; a third output voltage supply node; first and second MOS transistors respectively coupling the first and third nodes and the second and third nodes; and a control circuit capable of keeping the first and second transistors either respectively on and off or respectively off and on, the control circuit including a feedback loop from the third node to the gate of the first transistor and being capable, during a transition phase, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node.
US10127951B2	Memory device with reduced-resistance interconnect In some embodiments, a memory device comprises first and second conductive lines extending generally in parallel with one another over a row of memory cells. The first and second conductive lines are disposed in a first interconnect layer and are coupled to memory cells of the row. A first plurality of conductive line segments are disposed in a second interconnect layer disposed over the first interconnect layer. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line and are coupled in parallel with the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line. Conductive line segments of the second plurality of conductive line segments are coupled to different locations on the second conductive line and are coupled in parallel with the second conductive line.
US10127950B1	Data storage device with moving ambient temperature sensor A data storage device may be configured with a transducing head separated from a data storage medium by an air bearing. The transducing head and data storage medium are each contained within a housing. The transducing head can consist of a variable resistance sensor that is connected to a temperature module positioned within the housing. One or more operational variables can be measured by the variable resistance sensor to allow an ambient temperature within the housing to be calculated based on a measured operational variable.
US10127947B2	Data storage system enclosure with central mounting plate A data storage system assembly includes a rigid central plate with multiple data storage devices (DSDs) mounted on the central plate, where a first row of DSDs is coupled with a first side of the central plate, and a second row of DSDs is coupled with a second side of the central plate, both in a side-by-side arrangement. A plurality of flexible mounting grommets may be fastened to each DSD and coupled to the central plate, such as in an arrangement in which an even number of grommets are fastened to one side and an odd number of grommets are fastened to an opposing side of the DSD. Each respective DSD may be fastened to a corresponding adaptor plate, where each adaptor plate is coupled with the central plate. Flexible mounting grommets may be fastened to each adaptor plate and coupled to the central plate.
US10127945B2	Visualization of image themes based on image content Implementations relate to visualizations including images based on image content. In some implementations, a computer-implemented method includes obtaining a set of images, determining one or more pixel characteristics of the set of images, and determining one or more faces depicted in the plurality of images based on one or more pixel characteristics. The method selects a group of images of the set of images, where each image in the group of images depicts a different group of faces than depicted in the other images in the set of images. The method generates a visualization including the group of images, and provides the visualization to a user device in response to a user request to cause the group of images to be displayed by the user device.
US10127943B1	Systems and methods for modifying videos based on music Video information defining video content may be accessed. Music information defining a music track providing an accompaniment for video content may be accessed. The music track may have pulses and one or more music events. Individual music events may correspond to different moments within the music track. One or more music events may be individually classified into one or more categories based on intensities of one or pulses occurring within the music event. One or more visual effects may be selected for different moments within the music track based on the categories of the music events. One or more visual effects may be applied to the video content. One or more visual effects may be applied to one or more moments within the video content aligned to one or more different moments within the music track.
US10127942B2	Recording apparatus and recording method A recording apparatus, including a recorder that records moving image data into a recording medium designated as a recording destination among a plurality of recording media; a reader that reads out, from the recording medium, temperature information on a current temperature of the recording medium; and a controller that controls the recorder based on a recording speed corresponding to a temperature indicated by the temperature information read out by the reader, wherein the controller controls, if a recording speed corresponding to a temperature indicated by first temperature information read out by the reader from a first recording medium designated as the recording destination during recording of the moving image data into the first recording medium is lower than a predetermined recording speed, the recorder to switch the recording destination from the first recording medium to another recording medium and continuously record the moving image data into the another recording medium.
US10127940B1	Bolometer with temperature compensation for internal laser power monitoring in heat-assisted magnetic recording device A slider configured for heat-assisted magnetic recording comprises an optical sensor coupled to first and second bond pads. The optical sensor comprises a bolometer and a reference sensor. The bolometer is situated at a location of the slider that receives at least some of the light and exposed to an ambient temperature at the slider. The bolometer produces a signal in response to a change in the ambient temperature and the change in output optical power. The reference sensor is situated at a location of the slider unexposed to the light and exposed to the ambient temperature. The reference sensor is coupled to the bolometer and configured to produce a signal in response to the change in the ambient temperature. The optical sensor is configured to generate a sensor signal indicative of changes in output optical power of a laser source without contribution due to ambient temperature changes.
US10127938B2	Method for forming TE to TM mode converter of heat-assisted magnetic recording head An apparatus includes an input coupler configured to receive light excited by a light source. A near-field transducer (NFT) is positioned at a media-facing surface of a write head. A layered waveguide is positioned between the input coupler and the NFT and configured to receive the light output from the input coupler in a transverse electric (TE) mode and deliver the light to the NFT in a transverse magnetic (TM) mode. The layered waveguide comprises a first layer extending along a light-propagation direction. The first layer is configured to receive light from the input coupler. The first layer tapers from a first cross track width to a second cross track width where the second cross track width is narrower than the first cross track width. The layered waveguide includes a second layer that is disposed on the first layer. The second layer has a cross sectional area in a plane perpendicular to the light propagation direction that increases along the light propagation direction. The cross sectional area of the second layer is smaller proximate to the input coupler and larger proximate to the NFT.
US10127937B1	Optically opaque overlay for a waveguide of a heat-assisted magnetic recording slider A slider having an air bearing surface is configured for heat-assisted magnetic recording (HAMR). The slider comprises a write pole, a near-field transducer (NFT) proximate the write pole, a return pole magnetically coupled to the write pole, and an optical waveguide configured to receive light from a light source and couple the light to the NFT. The optical waveguide comprises first and second opposing major surfaces and opposing first and second edges connected to the first and second major surfaces. An optically opaque overlay is disposed on one or both of the first and second major surfaces of the optical waveguide. The optically opaque overlay can be light reflective or light absorbing.
US10127935B2	Plasmonic gap waveguide An apparatus includes a slider configured for heat-assisted magnetic recording. An input coupler of the slider is configured to-receive light produced by a light source. A waveguide of the slider comprises a waveguide core tapering from a first portion having a first cross sectional width to a second portion having a second cross sectional width along the light propagation direction. The second cross sectional width being smaller than the first cross sectional width, and the second portion having an output end. The waveguide includes at least one cladding layer comprising a metallic material. The at least one cladding layer surrounds at least the core. The at least one cladding layer is configured to sink heat away from the waveguide core. The waveguide is configured to provide a surface plasmon-enhanced near-field radiation pattern proximate the output end in response to the light received at the transducer region.
US10127934B2	Detection of sensor-damaging magnetic tape recording media A computer-implemented method for detecting sensor-damaging tape media, according to one embodiment, includes acquiring a metric for at least one sensor of a tape drive after performing an operation on a magnetic recording tape, and comparing the metric for the at least one sensor after performing the operation to a metric for the at least one sensor acquired before performing the operation. An action is taken in response to a result of the comparing indicating that a difference between the metrics is in a predetermined range. A product, according to one embodiment, includes a magnetic recording tape, and a memory coupled to the magnetic recording tape. At least one value is stored in the memory, the at least one value being indicative of whether the magnetic recording tape is potentially sensor-damaging.
US10127933B2	Multi-track reader for improved signal to noise ratio A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
US10127923B2	Automatic sound level control A method includes identifying, by a computing device including a processor, a plurality of words from data. The method includes determining a location of the computing device. The method includes determining, by the computing device, a sound output level based on the location. The method also includes generating, by the computing device, digital sound data based on the sound output level and the plurality of words identified from the data.
US10127920B2	Acoustic parameter adjustment Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adjusting acoustic parameters. In one aspect, a method includes receiving an identifier associated with an enclosure for a computing device, transmitting data identifying the identifier associated with the enclosure for the computing device, and receiving one or more physical parameters of the enclosure for the computing device. The method also includes based on the one or more physical parameters of the enclosure for the computing device, determining, one or more acoustic parameter adjustments of the computing device in the enclosure, the one or more acoustic parameter adjustments being configured to preserve one or more acoustic characteristics of the computing device out of the enclosure while the computing device is in the enclosure, and based on the one or more acoustic parameter adjustments, adjusting the one or more acoustic parameters of the computing device.
US10127918B1	Methods for reconstructing an audio signal A system configured to reconstruct audio signals. The system may identify missing audio samples due to packet loss or detect distortion caused by audio clipping and may reconstruct the audio data. The system may employ a forward-looking neural network that recursively predicts audio samples based on previous audio samples and/or a backward-looking neural network that recursively predicts audio samples based on subsequent audio samples. The system may generate audio data using only the forward-looking neural network for low latency applications or may generate audio data using both neural networks for mid to high latency applications. To reduce distortion in output audio data, the system may generate the audio data by cross-fading between outputs of the neural networks and/or may cross-fade between the generated audio data and the input audio data.
US10127913B1	Method of encoding of data stream, method of decoding of data stream, and devices for implementation of said methods A method of decoding of syntactic elements of a data stream is disclosed where, before beginning of decoding of the data stream, cells of all context models are initialized with predefined values, so that each context model contains in each cell data on a probability and a counter of a context occurrence number. A number of cells stored in each context model is selected to be not less than a number of all possible states of context elements associated with a respective context model. The process of decoding of at least a portion of bits of the data stream includes, among other steps: selecting a group of context models; calculating values of at least two context elements; extracting data on the probability from the selected cell of the selected context module; updating data in the selected cell; and carrying out a procedure of probability inheritance.
US10127910B2	Speech recognition apparatus and computer program product for speech recognition In a speech recognition apparatus, a speech driver fetches a guidance speech-data as a reference speech-data, and outputs the reference speech-data to a recognition core unit. A guidance speech into which the guidance speech-data is converted is outputted by a speaker to cause a microphone to receive the outputted guidance speech, which will be converted into an inputted guidance speech-data. Even in such case, a speech recognition engine removes the inputted guidance speech-data by using, as the reference speech-data, the guidance speech-data that is before being converted into the outputted guidance speech.
US10127907B2	Control device and message output control system The present invention prevents a plurality of robots from outputting identical messages to a single user. The present invention includes a message determining section (83) that determines whether or not a message to be outputted from a robot (2) is identical to a first message to be outputted from a robot (1) or a second message which has been outputted from the robot (1). In a case where the message to be outputted from the robot (2) is identical to the first message or the second message, the message determining section (83) controls the robot (2) to (i) output a message different from the first message or the second message, or (ii) not to output any message.
US10127905B2	Apparatus and method for generating acoustic model for speech, and apparatus and method for speech recognition using acoustic model Described are an apparatus and method for generating to generate an acoustic model. The apparatus and method include a processor a processor configured to calculate a noise representation that represents noise data by using a noise model, and generate the acoustic model through training using training noisy speech data, which comprises speech data and the noise data, a string of phonemes corresponding to the speech data, and the noise representation.
US10127903B2	Discovering windows in temporal predicates A method and system are provided. The method includes separating a predicate that specifies a set of events into a temporal part and a non-temporal part. The method further includes comparing the temporal part of the predicate against a predicate of a known window type. The method also includes determining whether the temporal part of the predicate matches the predicate of the known window type. The method additionally includes replacing (i) the non-temporal part of the predicate by a filter, and (ii) the temporal part of the predicate by an instance of the known window type, responsive to the temporal part of the temporal predicate matching the predicate of the known window type. The instance is parameterized with substitutions used to match the temporal part of the predicate to the predicate of the known window type.
US10127898B1	Harmonica Cleaning Accumulated saliva, other liquid and/or debris is removed from the interior of a harmonica by placing the harmonica in a carrier and twirling the carrier in an orbital path. The saliva, other liquid and/or debris is ejected from the holes or the harmonica by centrifugal force.
US10127896B2	Musical instrument A musical instrument includes an instrument main body extending in a first direction, a first protruding portion that protrudes from one main side of the body, and at least one second protruding from the one main side and spaced from the first protruding portion in a second direction perpendicular to the first direction. The center of gravity of the main body is interposed between the first and second protruding portions in the second direction and located in a region defined by the first and second protruding portions. The region has a polygon shape.
US10127893B2	Electronic device, code display method of electronic device and recording medium An electronic device including a display, a memory that stores instructions, and a processor. The processor, under control of the instructions, performs processes including a first display process of controlling the display such that the display displays a code while setting the display with a contrast ratio; and in a case where the code is displayed on the display, a contrast change process of automatically changing the contrast ratio of the display at each of intervals, each of the intervals corresponding to a first duration of time.
US10127892B2	Display device using overlapped data lines near center to dim Mura defect A display device using overlapped data lines to dim the Mura defect. The display device includes multiple pairs of data lines, and each pair of data lines includes a top data line and a bottom data line. The top data line and the bottom data line overlap in a center area, and each of the pixels in the center area includes two subpixels respectively connected to the corresponding top and bottom data lines. For each pixels in the center area, each of the two subpixels has a corresponding weighting factor. From top to bottom of the center area, the weighting factors of the top subpixels gradually decrease, and the weighting factors of the bottom subpixels gradually increase.
US10127890B2	Display device with better contrast A display device includes a display area including non-illuminated areas and illuminated areas, wherein centroids of adjacent illuminated areas are located at distances from each other which are smaller than a resolving power of a viewer, and wherein the proportion of non-illuminated areas in the entire display area is more than 70%.
US10127886B2	Modifying hand occlusion of holograms based on contextual information A computing system, such as a head mounted display, is configured for dynamically modifying an occlusion, such as a hand occlusion, that is presented and moved within a mixed reality environment. The occlusion is associated with a movement attribute, such as a velocity or acceleration, corresponding with movement of the occlusion within the mixed reality environment. Upon detecting a movement of the occlusion, it is determined whether the movement attribute meets or exceeds a predetermined threshold. When the threshold is at least met, the visual appearance of the occlusion is modified by at least one of modifying a transparency attribute of the occlusion to cause increased transparency of the occlusion or by modifying an edge display attribute of the occlusion to cause feathering of one or more occlusion edges.
US10127881B2	Display driving circuit, display device and driving method thereof Provided are a display driving circuit, a display device and a driving method thereof, which are capable of avoiding an influence of a feed through effect on a voltage difference between a pixel electrode and a common electrode and thus improving the quality of a displayed picture. The display driving circuit comprises a gate driving unit for controlling a thin film transistor TFT to be turned on, a source driving unit for outputting a signal to a source of the TFT, and a circuit unit for supplying a power to a common electrode, the circuit unit outputs a first voltage to the common electrode when the TFT is in a turn-on state, and the circuit unit outputs a second voltage to the common electrode when the TFT is in a turn-off state, wherein the first voltage is a voltage different from the second voltage.
US10127880B2	Liquid-crystal display device having control line groups A liquid-crystal display device includes a display panel connected to first to nth gate lines and first to nth control lines, where n is a natural number greater than one, and a gate driving unit which sequentially applies first to nth gate signals having a first pulse width to the first to nth gate lines, respectively, for a unit frame, where the first to nth control lines are sorted into first to kth control line groups, where k is a natural number greater than one and less than n, the gate driving unit sequentially applies first to kth control signals having a second pulse width to the first to kth control line group, respectively, for the unit frame, and the first pulse width is smaller than the second pulse width.
US10127878B1	GOA driver circuit and liquid crystal display A gate driver on array (GOA) driver circuit and a liquid crystal display are proposed. The GOA driver circuit includes cascaded GOA units. A gate driver signal is output to an Nth-stage horizontal scan line Gn on a display zone according to an Nth-stage GOA unit output gate driver signal. The Nth-stage GOA unit includes a pull-up module, a pull-up control module, a pull-down holding module, a transferring module, and a bootstrap capacitor module.
US10127877B2	Display device There is provided a display device including a display panel including a gate line operated by a gate signal, a clock source configured to apply a clock signal, a shift register including a stage, the stage including at least one switching element and being configured to generate the gate signal based on the clock signal applied from the clock source, and a control-voltage generator configured to generate a control voltage based on a current generated from at least one of the shift register and the clock source and to apply the control voltage to the at least one switching element.
US10127871B2	Liquid crystal display device including a detection circuit According to an aspect, a liquid crystal display device includes a plurality of pixels arranged in a matrix in a display area; a scanning line that is coupled with pixels arranged in a row direction in the display area and is supplied with a scan signal; a signal line that is coupled with pixels arranged in a column direction in the display area and is supplied with a pixel signal; a common electrode that is commonly coupled with the pixels and is supplied with a common voltage; and a detection circuit that detects a transient potential variation component that is synchronized with the pixel signal and is superimposed on the common voltage.
US10127870B2	Liquid crystal display having two equal common voltages at two opposite sides A liquid crystal display includes a pixel array, a gate driver, a data driver, a common voltage source, and a current duplication module. The gate driver is used to turn on a plurality of rows of pixels in the pixel array in sequence. The data driver is used to provide a plurality of data voltages to the turned-on pixels in the pixel array. The common voltage source is used to provide a common voltage. The current duplication module is coupled to a first side and a second side of the pixel array and is used to input two substantially equal currents to the first side and the second side of the pixel array respectively to provide the common voltage to the first side and the second side of the pixel array.
US10127869B2	Timing controller, display apparatus including the same and method of driving the display apparatus A timing controller for a display apparatus includes a polarity comparison part and a compensation part. The polarity comparison part compares a first polarity of a first data voltage with a second polarity of a second data voltage, the first data voltage corresponding to a first pixel in a first frame and generated based on a first gamma voltage, the second data voltage corresponding to the first pixel in a second frame and generated based on a second gamma voltage. The compensation part compensates the second data voltage based on a first look-up table, if the first polarity is the same as the second polarity, and compensates the second data voltage based on a second look-up table, if the first polarity is different from the second polarity.
US10127868B2	Method of controlling subpixels in an array of electrowetting elements A method of controlling an array of electrowetting elements, comprising: receiving first pixel data; selecting, based on the first pixel data and based on a characteristic of the first display effect, a group of subpixels to display the first display effect; and outputting control data for displaying the first display effect using the group of subpixels.
US10127862B2	Shift register unit, gate drive circuit and display panel The present application discloses a shift register, a gate drive circuit and a display panel. In the shift register, the first node control sub-circuit provides a signal of the input signal terminal to the first node, and provides a signal of the first reference signal terminal to the first node; the second node control sub-circuit provides a signal of the second reference signal terminal to the second node, and provides a signal of the third clock signal terminal to the second node; the first output sub-circuit provides a signal of the second clock signal terminal to the output terminal for stabilizing a voltage difference between the first node and the output terminal when the first node is in a floating state; and the second output sub-circuit provides the signal of the first reference signal terminal to the output terminal.
US10127860B2	Stable driving scheme for active matrix displays A method and system for operating a pixel array having at least one pixel circuit is provided. The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period. The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.
US10127854B2	Display driving method, apparatus and display device that generates ananalog power supply voltage for a source driver chip according to brightness of sub-pixels The present disclosure provides a display driving method, apparatus and a display device. The method comprises: acquiring pixel data of N pixels, N=i*j, i being a coefficient and being a positive integer, and j being the number of pixels in each row; determining, for each pixel data, brightness values of respective sub-pixels in a pixel corresponding to the pixel data; calculating an analog power supply voltage of a source driver chip of a display module according to respective brightness values, the analog power supply voltage being positively correlated with the brightness values.
US10127851B2	Image processing method of OLED display device Disclosed is an image processing method for reducing power consumption of an OLED display device. A method of the present invention comprises the steps of: receiving image data; determining whether a frequency of a predetermined area of the image data is lower than a predetermined reference; deciding a minimum value among a plurality of blue data values of the predetermined area when the frequency of the predetermined area is lower than the reference as a result of the determination; and changing blue data of the predetermined area on the basis of the determined minimum value.
US10127848B2	Display device A display device, including a display panel including a plurality of pixels coupled to scan lines and data lines, the display panel having a display area divided into a first display area at a first side thereof and a second display area at a second side opposite to the first side; a scan driver to supply a scan signal through the scan lines; and a data driver to supply a data signal through the data lines, the scan lines including first sub-scan lines corresponding to the first display area and second sub-scan lines corresponding to the second display area, and switching elements being coupled between the first sub-scan lines and the second sub-scan lines.
US10127845B2	Drive arrangement and rotating mechanism for an advertising or information medium having a drive arrangement of this type A rotating mechanism characterized by a drive arrangement which provides rotating, hoisting and dropping functions with just a single drive.
US10127841B1	Conformable cover and label for the end of a tubular object such as a rolled up set of architectural documents A labeling apparatus for an end of a rolled set of drawings or any similarly shaped elongated object. A potential embodiment of the apparatus comprises a flexible sheet which can be drawn over an end of the elongated object. The flexible sheet comprises a surface which is capable of being written on with pen, pencil, marker or any writing instrument known in the art. The writable surface can be integral to the flexible sheet or can be a separate writable surface which can be coupled with the flexible sheet. The flexible sheet comprises an elastic gripping feature for coupling the sheet over the end of the elongated object. The writable surface can comprise coloring, patterning or other visual cues known to those in the art to assist a user in identifying the label.
US10127838B2	Surgical simulation systems, methods, and compositions A synthetic surgical simulation system includes an anatomical structure comprising a hydrogel and at least 60% water and a tubular structure that is configured to at least partially vaporize, seal, and/or cut in response to an application of energy emitted by an electrosurgical tool. Some exemplary tools are a high-frequency alternating and direct current electrosurgical tool, a high frequency sound wave electrosurgical tool, or an argon beam coagulator. In some embodiments, the system also includes connective tissue. In further embodiments, the connective tissue couples a first anatomical structure and a second anatomical structure. In some embodiments, the tubular structure is at least partially embedded in one or more of the first anatomical structure, the second anatomical structure, and the connective tissue. In some embodiments, one or more of the connective tissue, the anatomical structure, the first anatomical structure, the second anatomical structure, and the tubular structure comprise poly(ethylene glycol)-diacrylate.
US10127835B2	Capacitive touch sensor A capacitive touch sensor is provided, The capacitive touch sensor includes a plate having an upper surface and lying in a plate plane. A generally planar, first electrode is spaced from the plate along an axis generally perpendicular to the upper surface of the plate. The first electrode movable with respect to the plate in response to a force. A plurality of second electrodes are interconnected to the plate and circumferentially spaced about the axis. Each of the plurality of the second electrodes has a corresponding differential capacitance with the first electrode. The differential capacitances between the first electrode and the plurality of second electrodes vary in the response to the movement of the first electrode.
US10127829B1	Method and system for calculating probabilities of causation of specified health conditions by foods A method includes the steps of receiving data indicative of a selected health condition; identifying one or more trigger substances associated with the selected health condition; identifying one or more foods containing the identified one or more trigger substances, including the concentration of the trigger substance; receiving data indicative of a selection of the one or more identified foods, including the amount of the food consumed within a specified time interval; identifying one or more risk factors associated with the one or more trigger substances contained in the selected one or more foods; receiving data indicative of a selection of the one or more identified risk factors; and calculating a probability of causation of the selected health condition based on the selected foods, weight values associated with the identified trigger factors contained in the selected foods indicative of the relative significance of the substance as a trigger of the selected health condition, and the selected risk factors.
US10127822B2	Drone user equipment indication The disclosure relates to drone user equipment (UE) indications that may be conveyed to a wireless network. In particular, a UE that has flight capabilities (i.e., capabilities to operate as an unmanned aircraft system) and optional further capabilities to report a current height level may indicate such capabilities to the wireless network. As such, the wireless network may differentiate the drone UE from other UEs that only operate on the ground. Furthermore, the optional current height level may enable the wireless network to differentiate among drone UEs operating at different heights and/or from other UEs that are operating on the ground. The wireless network may further use the information indicating the flight capabilities either alone or in combination with the optional height information to configure power control parameters, manage interference, provide mobility management functions, generate neighbor lists, control beamforming, or implement a radio resource configuration or management procedure.
US10127820B2	Driver assistance apparatus and vehicle including the same A driver assistance apparatus is provided. The driver assistance apparatus includes a processor determining whether lanes are not identified based on at least one of image information, distance information, sensor information, navigation information, secondary information and adjacent vehicle information, and generating virtual lanes; and an output unit outputting the generated virtual lanes.
US10127816B2	Detection and alert of automobile braking event A method and system alert a driver of a driven vehicle about an unsafe traffic condition. The method detects, by one or more of a radar detector, a Light Detection and Ranging (LIDAR) detector, or a camera, a braking event of a nearby vehicle. The method stores, in a storage device, the braking event of the nearby vehicle. The method communicates a signal indicative of the braking event of the nearby vehicle to a brake system of the driven vehicle. The method also alerts the driver, by one or more of a user display alert or an audible alert, of the braking event of the nearby vehicle.
US10127814B2	Advanced V2X event dissemination Disclosed is a host vehicle including: motor(s), sensors, processor(s) configured to: (i) package sensed data into a first unit; (ii) determine whether a vehicle-to-infrastructure connection is (a) active or (b) inactive; (iii) if (a), append a TRUE flag to the unit and if (b) append a FALSE flag to the unit; (iv) transmit the first appended unit over a vehicle-to-vehicle connection; (v) determine whether a second appended unit, received over a vehicle-to-vehicle connection, includes (c) a TRUE flag or (d) a FALSE flag; (vi) if (d), transmit the second appended unit over the vehicle-to-infrastructure connection; (vii) if (c), not transmit the second appended unit over the vehicle-to-infrastructure connection.
US10127811B2	Method, apparatus and computer program product for comprehensive management of signal phase and timing of traffic lights A method is provided for controlling traffic lights of a road geometry network using a cloud-based traffic control system. Methods may include: receiving map data including road network geometry and traffic light locations relative to intersections of the road network geometry; receiving signal phase and timing of traffic lights at the traffic light locations; receiving probe and sensor data from a plurality of probes traversing the road network geometry; analyzing the received probe and sensor data from the plurality of probes relative to the road network geometry and the traffic light locations; determining revised signal phase and timing for at least one traffic light within the road network geometry based on the analyzed probe and sensor data relative to the road network geometry and the traffic light locations; and providing revised signal phase and timing to the at least one traffic light within the road network geometry.
US10127809B2	Adaptive traffic dynamics prediction The disclosed embodiments relate to prediction of traffic dynamics. A descriptive model is provided that uses historical probe data to create “tidal-like” patterns for the usual dynamics on the road network and creates a framework for taking a future time, e.g. in terms of month, day, time, and suggesting a typical speed for the specified road network link at that specific time. With this model, better predictions for estimated time of arrival will be derived. As opposed to blindly extrapolating from a static model, the disclosed embodiments dynamically adapt to current conditions using real time data to adapt, based on current conditions, the model from which a predicted speed may be determined.
US10127808B2	Infrared learning device An infrared (IR) learning device is disclosed. A hardware device of the IR learning device amplifies, shapes, and samples an IR signal to acquire a better digital signal related to the IR signal. A software device of the IR learning device calculates the waveform of the IR signal and the frequency of a carrier wave of the IR signal according to the digital signal related to the IR signal. Accordingly, the IR learning device can learn the IR signal emitted from an external device by the hardware device and the software device.
US10127806B2	Methods and systems for controlling a garage door opener accessory A modular garage door opener system has an accessory device including a load, and garage door opener including an accessory port for receiving the accessory device. A server receives initial accessory device status and settings data from the garage door opener, stores the data as associated with the accessory port, and sends the data to a peripheral device. The server receives new accessory device status data and sends it to the peripheral device. New settings data is sent by the peripheral device to the server and the server sends it to the garage door opener such that the load of the accessory device is controlled based on the new settings data. Similarly, initial data may be stored and associated with a second accessory port for a second accessory device and a load of the second accessory device is controlled based on new settings data from received from the peripheral device.
US10127799B2	Methods, systems, and devices for managing, reprioritizing, and suppressing initiated alarms Present example embodiments relate generally to methods, systems, devices, computer readable medium, and logic for managing a plurality of alarms initiated by a plurality of alarm sensors. The method may include receiving a plurality of initiated alarm. The method may further include prioritizing one or more of the initiated alarms. The method may further include reprioritizing one or more of the prioritized initiated alarm when the one or more prioritized initiated alarm satisfies a reprioritization condition. The method may further include providing information pertaining to the one or more reprioritized alarms.
US10127797B2	Alternative inexpensive cloud-based mass market alarm system with alarm monitoring and reporting A security system including a wireless alarm sensor that detects a threat within a secured geographic area, a cloud application that monitors the alarm sensor and reports threats detected by the alarm sensor within the secured area to a human user of the secured area and a wireless publically accessible communication system defined by a plurality of relatively low power communication devices and a local base station, the alarm sensor detects a nearby one of the plurality of low power communication devices and wirelessly connects to the cloud application through the nearby one low power communication device and local base station.
US10127796B2	Personal hazard detection system with redundant position registration and communication A system for monitoring the safety of personnel on a work site, by providing workers on the site with portable battery powered safety monitors equipped with alarms, sensors to detect hazardous conditions, at least two forms of geo-location and two forms of voice and data telecommunication and two CPU's sharing the computation load, each CPU equipped to monitor and reset the other in case of failure to function, with each monitor capable of serving as a node in a mesh network and relaying information concerning alarms detected including location thereof to other monitors on the mesh network.
US10127791B2	Internet of things (IoT) event distribution The processing and management of IoT events, in a manner that provides an intuitive and user-friendly design pattern, is described, and may include determining a set of IoT events, corresponding to a set of IoT devices, wherein an IoT event for a particular IoT device corresponds to a state or change of state of the received data for the particular IoT device. User-defined triggers may be evaluated, in which each of the triggers include a conditional expression that is evaluated using one or more of the IoT events. The triggers may generate alerts, which may be routed to a target which determines the actions that may be performed.
US10127785B2	Entry point opening sensor A sensor package is disclosed that includes a compass and/or an accelerometer. The compass may be activated by a microcontroller in response to an indication of movement detected by an accelerometer. The compass's data may be utilized to determine an orientation for the object such as a door on which the sensor package is situated. The orientation data may indicate that the door is ajar and/or that a second magnetic field is present, suggesting tampering. A notice may be dispatched to a controller for the home security system, a client device, a remote system, etc.
US10127783B2	Method and device for processing motion events The disclosed embodiments include an electronic device with a display, processor(s), and memory. The electronic device displays a user interface on the display, the user interface including video information corresponding to a camera, the video information including a field of view of the camera. The electronic device receives user identification of a spatial zone within the user interface, the spatial zone corresponding to at least a portion of the field of view of the camera; and forgoes user notification of subsequent motion events involving the spatial zone.
US10127780B2	Guidance assistance system, guidance assistance method, and computer-readable recording medium A guidance assistance system includes an arrangement evaluation unit which derives a priority of arrangement of detection means for detecting a status of congestion on a travel route or a priority of arrangement of a guide sign for guiding the crowd based on information related to a status of the travel route and an order determination unit which determines an order of arrangement of the detection means or an order of arrangement of the guide sign based on information related to the priority.
US10127779B2	Signalling device A signalling device, in particular for a signalling tower, for purposes of displaying operating states, with at least one signalling module, which has a circuit board element for at least one signalling element for purposes of outputting a signal, in particular for a lighting element for purposes of outputting a signal light, wherein the signalling module can be detachably connected with a further signalling module, and in the connected state the signalling modules are arranged one above another, wherein a connecting conductor, running through the signalling module, is provided for purposes of controlling a circuit board element of the further signalling module, wherein the circuit board element of the signalling module for purposes of forming the connecting conductor has a conducting track assigned to the signalling element of the further signalling module, which conducting track in the connected state of the signalling modules is connected via a contact element with a conducting track; on the circuit board element of the further signalling module, wherein the signalling module has a bayonet coupling element for purposes of connecting with a bayonet coupling element of the further signalling module, wherein in an interconnected, non-rotated state of the bayonet coupling elements the circuit board elements are arranged in a non-contact position, and in an interconnected, rotated state of the bayonet coupling elements the circuit board are arranged in a contact position with one another.
US10127778B2	Haptic actuator including flexure bearing having flexible arm including a bend coupling anchor members and related methods A haptic actuator may include a housing, at least one coil carried by the housing, and a field member having opposing first and second sides. The haptic actuator may also include a respective flexure bearing mounting each of the first and second sides of the field member to be reciprocally movable within the housing responsive to the at least one coil. Each flexure bearing may include a first anchor member coupled to an adjacent portion of the housing, a second anchor member coupled to an adjacent side of the field member, and a first flexible arm coupling the first and second anchor members together and having at least one bend therein.
US10127776B2	Cash drawer and weighing module A cash drawer has a weighing module comprising a plurality of cups; the cash drawer has a front and a rear. The cups are arranged such that four prone note cups, five coin cups and two vertical note cups are provided. The four prone note cups are arranged rearwards of the five coin cups and forwards of the two vertical note cups. A weighing module for a cash drawer is also provided, which comprises a plurality of note cups and coin cups arranged on respective load cells. At least some of the cups are movable relative to respective load cells on which they are arranged.
US10127774B2	Methods, apparatus and article of manufacture for determining an outcome of a game without placing any bets on the game Methods, apparatus and article of manufacture for receiving from a client an amount of money and instructions to place a type of bet in a game. The outcome of the game is determined without placing any bets on the game. Based on the outcome of the game, a portion of the amount of money is provided to the client.
US10127773B2	Multi-player bingo game with multiple cards per player The invention is directed to methods and gaming units for conducting a multi-player wagering game in which at least one of the players may win the occurrence of the wagering game by matching a game-winning pattern of game indicia on one or more game arrays having unique combinations of game indicia based on matching the game indicia on the game arrays to game indicia randomly selected for the occurrence of the wagering game. Each player matching a game-winning pattern may receive game-winning award, and may receive a game-winning award for each game array on which a game-winning pattern is matched. The method and gaming unit may further include an alternate outcome display wherein an outcome of a second wagering game may be displayed that corresponds to the outcome for the player on the one or more game arrays for the occurrence of the multi-player wagering game.
US10127770B2	Game at cash register In various embodiments, a method may include receiving an indication of a price of an item to be purchased by a person from a merchant, receiving an indication of an amount tendered by the person, determining an amount of change due to the person based on the price and based on the amount tendered, determining the rules of a game, generating a first outcome of the game using a random number generator, determining based on the rules whether the first outcome is winning or losing, authorizing, if the first outcome is winning, that the amount tendered be returned to the person and that the person be allowed to keep the item, and authorizing, if the first outcome is losing, that the amount tendered be kept by the merchant.
US10127767B2	Player choice game feature A gaming machine has display means and a game control means. A game is played in which one or more random events are displayed on the display means and, if a predefined winning event occurs, the machine awards a prize. On the occurrence of a predefined event, the player is offered a choice of two or more different prize sets, each containing a plurality of prize outcomes. The prize is drawn from the prize set or sets selected. The sets of prizes may be presented on segments of wheels that can spin before stopping randomly on a segment which defines the prize outcome. Alternatively the sets of prizes are presented on the faces of dice which are arranged to spin before stopping with the front face of the die defining the prize won.
US10127766B1	Distributed secrets for validation of gaming transactions Nested commit/reveal sequences using randomized inputs from each participant in a gaming transaction (e.g., the house and each player) may be employed to provide a selection of outcome or outcomes that can be verified by each participant as free from cheating. In general, techniques may be employed in a variety of distributed gaming transaction environments and as a verification facility for any of a wide variety of games in which the risk of player collusion can be eliminated. Nonetheless, several variations on a distributed card dealing method are illustrative and will be appreciated by persons of ordinary skill in the art as applicable in other gaming environments, including games employing outcomes denominated in die (or dice) rolls, coin toss, wheel spins, blind selection or other ostensibly random selection of an outcome from a predefined set thereof.
US10127761B2	Electronic gaming and/or entertainment device A gaming and/or entertainment device, in the form of a coin or token-operated slot machine and/or gambling device, having a plurality of separate display units for displaying game information. At least one of the display units is provided with a touch panel for inputting control commands by touch. The touch panel is of continuous design over, in each case, at least part of at least two different display units, at least one display unit of which has a concave display surface. As a result of the touch panel extending over the boundary region or the intermediate space between two display units, it is possible, despite the use of a plurality of display units, to obtain a continuously closed-off device front. The design of the corresponding device wall is simplified and the protection against penetration into the housing at gap areas is increased.
US10127750B2	Electronic locking system A system and method for enabling opening of an electronic locking device (12) from a remote location is disclosed. A remotely accessible server (14) receives an opening request to open an electronic locking device (12) which secures a closing member (18). The opening request includes a unique identifier of the electronic locking device (12) and personal identification information of a mobile communications device (28) requesting to open the electronic locking device (12). The server (14) then determines, based on predefined parameters, whether the mobile communications device (28) is permitted to open the electronic locking device (12). If the server (14) determines that the mobile communications device (28) is permitted to open the electronic locking device (12), then it transmits an opening instruction to the electronic locking device (12) to unlock the closing member (18). In an embodiment, the predefined parameters include a proximity range of the mobile communications device (28) to the electronic locking device (12).
US10127746B2	Systems and methods for electronic ticket validation using proximity detection for two or more tickets A system for monitoring two or more persons in an area with an entry point having an access allowed indication or an access denied indication. a token device in communication with at least one wireless proximity detection device which determines a relative location of the token device to provide a detection data point for each of the wireless proximity detection devices and a set of detection data points for the group of detection data points; a system computing device which calculates the shared proximity of the token device according to the set of detection data points and determines that the token device contains at least two valid tickets or does not, if there are valid tickets and the shared proximity of the token device is within a predetermined area the access allowed indication will display to allow entry for a number of persons corresponding to the number of the tickets.
US10127735B2	System, method and apparatus of eye tracking or gaze detection applications including facilitating action on or interaction with a simulated object Techniques are disclosed for facilitating action by a user on a simulated object in an augmented reality environment. In some embodiments, a method includes, detecting a gesture of the user in a real environment via a sensor of the device; wherein, the gesture includes, movement of eye ball or eye focal point of one or more eyes of the user. The gesture can be detected by tracking: a movement of one or more eyes of the user, a non-movement of one or more eyes of the user, a location of a focal point of one or more eyes of the user, and/or a movement of an eye lid of one or more eyes of the user. The gesture can be captured to implement the action on the simulated object in the augmented reality environment.
US10127733B2	Interference based augmented reality hosting platforms Interference-based augmented reality hosting platforms are presented. Hosting platforms can include networking nodes capable of analyzing a digital representation of scene to derive interference among elements of the scene. The hosting platform utilizes the interference to adjust the presence of augmented reality objects within an augmented reality experience. Elements of a scene can constructively interfere, enhancing presence of augmented reality objects; or destructively interfere, suppressing presence of augmented reality objects.
US10127723B2	Room based sensors in an augmented reality system An augmented reality display system comprises a passable world model data comprises a set of map points corresponding to one or more objects of the real world. The augmented reality system also comprises a processor to communicate with one or more individual augmented reality display systems to pass a portion of the passable world model data to the one or more individual augmented reality display systems, wherein the piece of the passable world model data is passed based at least in part on respective locations corresponding to the one or more individual augmented reality display systems.
US10127720B2	Object modeling in multi-dimensional space Embodiments of the invention include a method inserting a new face in a polygonal mesh comprising receiving an input corresponding to: a polygonal mesh having a plurality of faces, a selection of a face (fm) of the plurality of faces, a direction vector (d), a modified target plane (pm), and a threshold angle θ. For each edge (e) of the selected face fm, the method further includes determining each adjacent face (fadj) to selected face fm, and inserting a new face at edge e if no adjacent face exists or if fadj is substantially parallel to pm and within threshold θ. In some embodiments, the new face has a normal orthogonal to e and d.
US10127716B2	Automultiscopic display with viewpoint tracking and scalability for multiple views In one aspect, a computer-implemented method for efficiently rendering and displaying multiple images on an electronic device having an automultiscopic display may generally include detecting, with the electronic device, a position of at least one eye relative to the automultiscopic display. The automultiscopic display may include an array of multipixels, with each multipixel including a plurality of sub-multipixels. In addition, the method may include rendering a viewpoint-specific image for each detected eye position and selectively coloring at least one sub-multipixel within one or more of the multipixels such that colors associated with the rendered viewpoint-specific image are only displayed within a multipixel display zone defined for each of the one or more multipixels with respect to each detected eye position.
US10127710B2	Processor and method for accelerating ray casting A processor and method for accelerating ray casting are disclosed herein. The processor for accelerating ray casting includes a computation unit, a sorting unit, an allocation unit, and an execution control unit. The computation unit calculates the length information of a section in which a ray corresponding to each of the pixels of a two-dimensional (2D) scene corresponding to a viewpoint intersects an effective volume in order to apply ray casting to the pixel. The sorting unit sorts the ray based on the length information of the section in which the ray intersects the effective volume. The allocation unit allocates the sorted rays to respective thread groups having a parallel multiprocessor structure in order of the sorting. The execution control unit transfers control instructions to the allocated thread groups so that the allocated thread groups execute ray casting for the sorted rays.
US10127704B2	Information processing device, program, and recording medium An information processing device 10 includes a command recognition unit 203, a parameter extraction unit 28 and a command execution unit 253. The command recognition unit 203 specifies one of one or more pieces of object creation processing, which include at least one of processing for creating a text box, processing for creating a figure, and table creating processing for creating a table, from a combination of directions where one polygonal line is bent, the one polygonal line being inputted as a handwriting input command to a handwriting input device that enables handwriting input onto a display screen. The parameter extraction unit 208 extracts a parameter such as a position, size and the like of a designated object from a position and length of a segment that composes one polygonal line. Thus, the information processing device 10 allows a user to give a command on a screen by handwriting.
US10127703B2	Image output method and electronic device for supporting the same One or more embodiments of this disclosure provide an image output method. The image output method includes receiving image data for a plurality of image frames and caption data linked with the plurality of image frames. The method also includes outputting parsing the caption data to extract link information according to a data type from the caption data. The method also includes outputting a connection object or a list, for verifying the link information while the plurality of image frames are output on a display of the electronic device.
US10127699B2	Serial visual presentation for wearable displays One embodiment provides a method, including: receiving, at a wearable device, electronic text data; separating the electronic text data to segment the electronic text data into separate parts; and presenting, on a display screen of the wearable device, the separate parts of the electronic text data in a serial visual presentation, each part substantially occupying the display screen. Other embodiments are described and claimed.
US10127698B2	Method, apparatus and system for financial planning incorporating calculated health costs based on actual claims and the actual cost thereof A financial management tool that includes calculated health care costs and health-based longevity to provide information to retirees to be able to calculate the amount of money that needs to be saved to cover retirement expenditures is provided with actual claims and actual related cost data from a database to increase the cost projection reliability of the tool.
US10127695B2	Method for creating period profile for time-series data with recurrent patterns Techniques are described for generating period profiles. According to an embodiment, a set of time series data is received, where the set of time series data includes data spanning a plurality of time windows having a seasonal period. Based at least in part on the set of time-series data, a first set of sub-periods of the seasonal period is associated with a particular class of seasonal pattern. A profile for a seasonal period that identifies which sub-periods of the seasonal period are associated with the particular class of seasonal pattern is generated and stored, in volatile or non-volatile storage. Based on the profile, a visualization is generated for at least one sub-period of the first set of sub-periods of the seasonal period that indicates that the at least one sub-period is part of the particular class of seasonal pattern.
US10127693B2	Dimensional data chart matrixes with drill operations A computing device outputs a chart matrix defined by associating a first data dimension with a row edge and a second data dimension with a column edge. Members of the first data dimension are displayed as row headers of the chart matrix, and members of the second data dimension are displayed as column headers of the chart matrix. The device outputs charts in matrix cells of the chart matrix defined by intersections of rows defined by the row edge and columns defined by the column edge. The computing device provides user options to perform a drill operation on a selected member displayed in the chart matrix. The computing device outputs, in response to the user input to perform the drill operation, a modified chart matrix displaying related members in at least one of the charts, wherein the related members are related by one hierarchical level from the selected member.
US10127692B2	Draggable maps A web server receives a request from a client specifying a location and a bounding area. A mapping engine creates a tile grid centered at the specified location. A seed tile is created, including or adjacent to the center location. The web server creates a resource identifier for each tile in the tile grid, and returns the tile grid including the resource identifiers to the client. The resource identifier for each tile includes the location of the seed tile and a position offset for the tile relative to the seed tile, in one embodiment specified in units of northward and eastward movement. The client requests tiles from the system using the resource identifiers previously provided by the system. Upon receiving the request, the mapping engine dynamically renders each requested tile using map data from the map database, and the web server returns the dynamically-generated tiles to the requesting client.
US10127688B2	System and process for automatically finding objects of a specific color A computer implemented method, system and computer program product for identifying the Main Colors and the matching colors of a visual object, and then viewing on a mobile device select items comprising the matching colors, such as from a merchant's catalog. A visual object is analyzed for color content, and the results are stored on a system database located on the device or on a remote server. The color analysis of the objects comprise advanced image processing techniques, such as Main Color extraction using color space transformation comprising HSV, RGB and CYMK to map between pixels in the image. The user can subsequently view a display on their mobile identifying the visual object's Main Colors and at least one Harmonic Color; and then select and view all items (i.e. products in a database) comprising one Harmonic Color, and/or all items of a specific type and Harmonic Color.
US10127687B2	Calibration device, calibration method, optical device, image-capturing device, projection device, measuring system, and measuring method A calibration device for an optical device including a two-dimensional image conversion element having a plurality of pixels and an optical system that forms an image-formation relationship between the image conversion element and the three-dimensional world coordinate space. The calibration device includes: a calibration-data acquisition unit that acquires calibration data representing the correspondence between two-dimensional pixel coordinates in the image conversion element and three-dimensional world coordinates in the world coordinate space; and a parameter calculating unit that calculates parameters of a camera model by applying, to the calibration data acquired by the calibration-data acquisition unit, a camera model in which two coordinate values of the three-dimensional world coordinates are expressed as functions of the other one coordinate value of the world coordinates and the two coordinate values of the two-dimensional pixel coordinates.
US10127685B2	Profile matching of buildings and urban structures A method and apparatus for determining a building/urban profile image location includes extracting a building/urban profile from an obtained image and comparing the image to a database of building/urban profiles. The database may be created by obtaining point cloud data sets scanned building/urban profiles, converting the obtained point cloud data sets to a corresponding 3D surface model, and creating the database of stored building/urban profiles viewed from multiple locations within each of the 3D surface models. By comparing the extracted building/urban profile image with the stored building/urban profiles contained within the database and finding a match the location from which the extracted building/urban profile image was taken can be determined.
US10127683B2	Method for determining the short axis in a lesion region in a three dimensional medical image A short axis in a 3 dimensional image of a lesion is determined starting from voxels defining the long axis and voxels in the plane of the long axis. Voxels within the plane of the long axis are projected perpendicularly onto the long axis and receive an identifier indicative of the region on the long axis onto which they are projected. Distances between points (projected sub-voxels) in pairs of points within the same range and within adjacent ranges are evaluated in order to determine the longest distance.
US10127681B2	Systems and methods for point-based image alignment Systems and methods for point-based image alignment are disclosed. A method includes: selecting first and second couplets of feature points corresponding to first and second biometric images, respectively, and calculating a rotation-invariant parameter for each of the first and second couplets of feature points; determining that the first couplet matches the second couplet based on a difference between the rotation-invariant parameter for the first couplet of feature points and the rotation-invariant parameter for the second couplet of feature points; determining a candidate transformation operation that aligns the first couplet of feature points to the second couplet of feature points; determining a goodness of fit between a pictorial representation of the first biometric image and a pictorial representation of the second biometric image with the transformation operation applied; and, determining that the candidate transformation aligns the first biometric image to the second biometric image based on the goodness of fit.
US10127679B2	Image alignment method and apparatus An image alignment method and apparatus, where the method and apparatus include obtaining image information of two to-be-aligned images, determining, using a cross-correlation measurement model, first coordinate offset according to the image information of the two images, where the first coordinate offset are used to indicate position deviations of to-be-aligned pixels between the two images in the coordinate system, and aligning the two images according to coordinates of pixels in the first image in the coordinate system and the first coordinate offset.
US10127674B2	Automatic mode switching in a volume dimensioner Dimensioners and methods for dimensioning an object includes capturing, using a dimensioning system with a single sensor, at least one range image of at least one field-of-view, and calculating dimensional data of the range images and storing the results. Wherein, the number of views captured of the object is automatically determined based on one of three modes. The first mode is used if the object is a cuboid, or has no protrusions and only one obtuse angle that does not face the point of view, where it captures a single view of the object. The second mode is used if the object includes a single obtuse angle, and no protrusions, where it captures two views of the object. The third mode is used if the object includes a protrusion and/or more than one obtuse angle, overhang, protrusion, or combinations thereof, where it captures more than two views of the object.
US10127669B2	Estimating distance to an object using a sequence of images recorded by a monocular camera A method for monitoring headway to an object performable in a computerized system including a camera mounted in a moving vehicle. The camera acquires in real time multiple image frames including respectively multiple images of the object within a field of view of the camera. An edge is detected in in the images of the object. A smoothed measurement is performed of a dimension the edge. Range to the object is calculated in real time, based on the smoothed measurement.
US10127668B2	Systems and methods for re-identifying objects in images There is provided a system including a memory and a processor configured to receive a first image depicting a first object and a second image depicting a second object, divide the first image into a first plurality of patches and the second image into a second plurality of patches, extract plurality of feature vectors from each of the first plurality of patches and a second plurality of feature vectors from the second plurality of patches, determine dissimilarities based on a plurality of patch metrics, each patch dissimilarity measure being a dissimilarity between corresponding patches of the first plurality of patches and the second plurality of patches, compute an image dissimilarity between the first image and the second image based on an aggregate of the plurality of patch dissimilarity measures, evaluate the image dissimilarity to determine a probability of whether the first object and the second object are the same.
US10127664B2	Ovarian image processing for diagnosis of a subject Embodiments relate to digital image processing for diagnosis of a subject. More specifically, the embodiments relate to automation of diagnoses through data interpretation. An image is acquired from the subject. Elements are recognized within the image based on morphological features. The image is compared to learned data. Based on the comparison, a probability of a potential diagnosis(es) is calculated. A diagnosis of the subject is determined based on the potential diagnosis(es) and the calculated probability. The diagnosis may be changed based on a new image acquired from the subject.
US10127662B1	Systems and user interfaces for automated generation of matching 2D series of medical images and efficient annotation of matching 2D medical images A system is disclosed by which medical imaging exams may be matched and/or registered so as to reduce and/or substantially eliminate artifactual differences between 2D images of the exams. The system may automatically create new, matching 2D images such that two or more exams may be accurately and efficiently compared by a reading physician. The new, matching 2D images may be generated by automated 3D registration of the exams and/or multiplanar reformation of 3D volumetric data acquired during acquisition of one or both exams (e.g., during imaging scans). Rules may be used to automatically determine exams to be compared, and which exams to match to another. Additionally, the system may automatically add indications to a later acquired image that indicate a corresponding earlier acquired image includes annotations. Additionally, the system may allow the physician to easily add and modify similar annotations to the later acquired image by selection of the indications.
US10127659B2	Deep learning medical systems and methods for image acquisition Methods and apparatus for improved deep learning for image acquisition are provided. An imaging system configuration apparatus includes a training learning device including a first processor to implement a first deep learning network (DLN) to learn a first set of imaging system configuration parameters based on a first set of inputs from a plurality of prior image acquisitions to configure at least one imaging system for image acquisition, the training learning device to receive and process feedback including operational data from the plurality of image acquisitions by the at least one imaging system. The example apparatus includes a deployed learning device including a second processor to implement a second DLN, the second DLN generated from the first DLN of the training learning device, the deployed learning device configured to provide a second imaging system configuration parameter to the imaging system in response to receiving a second input for image acquisition.
US10127657B2	System and method for valve quantification Systems and methods of valve quantification are disclosed. In one embodiment, a method of mitral valve quantification is provided. The method includes generating a 3-D heart model, defining a 3-D mitral valve annulus, fitting a plane through the 3-D mitral valve annulus, measuring the distance between at least two papillary muscle heads, defining an average diameter of at least one cross section around the micro valve annulus, and determining a size of an implant to be implanted.
US10127654B2	Medical image processing apparatus and method A medical image processing apparatus comprises a memory configured to store medical image data representative of a tissue structure and a processing circuitry configured to operationally connect to the memory, extract regions from the medical image data by performing threshold processing of the medical image data using each of a plurality of threshold values, select regions meeting at least one predetermined condition from among the extracted regions, and determine a region representative of the tissue structure in the medical image data based on the selected regions.
US10127651B2	Defect sensitivity of semiconductor wafer inspectors using design data with wafer image data Criticality of a detected defect can be determined based on context codes. The context codes can be generated for a region, each of which may be part of a die. Noise levels can be used to group context codes. The context codes can be used to automatically classify a range of design contexts present on a die without needing certain information a priori.
US10127645B2	Single-molecule image correction method, device and system, and computer-readable storage medium An embodiment of the present disclosure discloses a method and a device of correcting a single-molecule image, the method includes: acquiring the first target simplified matrix corresponding to the first image according to the intensity matrix corresponding to each of pixels in the first image, and acquiring the second target simplified matrix corresponding to the second image according to the intensity matrix corresponding to each of the pixels in the second image; the two-dimensional DFT is performed to the first target simplified matrix and the second target simplified matrix respectively to acquire the first Fourier matrix corresponding to the first target simplified matrix and the second Fourier matrix corresponding to the second target simplified matrix; the method of correcting a single-molecule image acquire the offset of the second image with respect to the first image according to the first Fourier matrix and the second Fourier matrix; and correcting the second image according to the offset. Such method can correct the images of single molecules taken at different moments.
US10127644B2	Generating synthetic video frames using optical flow A novel video system that detects events in a video sequence that causes such distortions and switch off optical flow based frame interpolation is provided. The system detects sudden changes in light intensity and switch to non-optical flow based frame interpolation when such sudden change is detected. When there is no such drastic change in light intensity, the system reverts back to using optical flow frame interpolation. Specifically, the system detects a flash event by computing a sum of differences in histograms of intensity levels between the pair of consecutive actual video frames. When the sum of differences is above a certain threshold, the video system switch to non-optical flow based frame interpolation. When the sum of differences is below the threshold, the video system reverts back to optical flow frame interpolation.
US10127643B2	Inpainting device and method using segmentation of reference region An inpainting device and method using the segmentation of a reference region are disclosed. An inpainting device using the segmentation of a reference region includes a region determination unit configured to determine an inpainting target region and a reference region within video image content, an inpainting group setting unit configured to set inpainting groups using pixel values within the reference region; an inpainting unit configured to perform segmentation inpainting adapted to perform inpainting on a segmented target region using the segmented reference region on an inpainting group basis and non-segmentation inpainting adapted to perform inpainting on the target region using the reference region, and an information provision unit configured to visually provide the result of the segmentation inpainting, the result of the non-segmentation inpainting, and information about the difference between the results of the segmentation inpainting and the non-segmentation inpainting to the user.
US10127635B2	Method and device for image noise estimation and image capture apparatus A method and device for image noise estimation and image capture apparatus are provided. In the device, a global noise estimation unit is configured to determine a plurality of current sample blocks of a current image frame and a plurality of previous sample blocks of a previous image frame, and calculate a block feature of each of the current sample blocks, and calculate a block sum-of-absolute-difference (SAD) between each of the current sample blocks and corresponding one of the previous sample blocks, and cluster the current sample blocks into a plurality of segments according to the block features, and respectively establish a plurality of noise models for the segments according to the block features and the block SAD. A local noise calculation unit is configured to calculate noise level information of a local image block of the current image frame according to a corresponding noise model of the noise models.
US10127634B2	Image editing and repair A method for healing a target region on an input image is described. A preview image is received; the preview image may reflect a down-sampled image of an original image. The method determines a target region for the preview image. The target region indicates a segment of the preview image designated for healing. The method may then heal the target region associated with the preview image using a transformation. The method may store one or more parameters associated with the healed preview image. The method may then provide for display the healed preview image to a user on a mobile device.
US10127633B2	Displaying representative images in a visual mapping system Embodiments provide systems and methods for generating a street map that includes a position identifier that identifies a location on the street map. The method and system may also generate and display a plurality of images representative of the location of the position identifier. A user may interact with a position identifier or one of several scroll icons to view images of other locations on the street map and/or to obtain driving directions between two locations.
US10127632B1	Display and update of panoramic image montages Implementations relate to display and update of panoramic image montages. In some implementations, a computer-implemented method includes causing one or more view portions of a panoramic image montage to be displayed in a display view of a display device. First user input is received at a first time while at least one of the one or more view portions of the panoramic image montage is displayed. In response to the first user input, an image feed is caused to be displayed, the image feed including a plurality of image frames captured by a camera. Second user input is received at a second time later than the first time while a particular view portion of the panoramic image montage is displayed in the display view. In response to the second user input, the particular view portion is updated based on the image feed.
US10127627B2	Mapping graphics resources to linear arrays using a paging system Memory resources that are stored in GPU-specific formats may be accessed as linear arrays by CPU applications. Shared virtual memory (SVM) support enables closer CPU/GPU interaction. This creates a need to efficiently access graphics data using SVM. CPU page mapping and memory management hardware may perform the address/data swizzling and tiled rendering translations required for GPU memory formats. As a result, CPU applications can access GPU resources as if they are stored in a linear array, while also using shared virtual memory.
US10127626B1	Method and apparatus improving the execution of instructions by execution threads in data processing systems In a data processing system, a program to be executed by a programmable processing unit of the data processing system is analyzed to identify a sequence of instructions that would produce the same result for plural execution threads were those plural execution threads each to execute the sequence of instructions using the same input data. Then, when the program is being executed, when an execution thread is to execute the identified sequence of instructions, it is determined whether a result produced by an earlier execution thread executing the sequence of instructions, and that used the same input data, is stored in memory or not. The current thread then either executes the sequence of instructions, or retrieves the stored result produced by the earlier execution of the sequence of instructions and skips execution of the sequence of instructions for which the result is stored, accordingly.
US10127624B1	Block mapping in high efficiency video coding compliant encoders and decoders An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.
US10127623B2	Geometric enumerated watermark embedding for colors and inks The present disclosure relate generally to digital watermarking and signal encoding. Various colors can be evaluated and modified to carry an encoded or auxiliary signal.
US10127621B2	Image sharing system A server system for distributing information securely includes a network interface for receiving, over a network, an information object accompanied by metadata. A repository stores the information object. Metadata is mapped to electronic addresses of trusted recipients. A processor is configured to generate a link for accessing the information object in the repository, acquire an electronic address of a trusted recipient based on the metadata accompanying the information object, insert the link into an electronic message addressed to the electronic address of the trusted recipient, and send the electronic message with the link to the trusted recipient. The processor is further configured to receive, over a second network, a request for the information object sent from a user device in response to an activation of the link, retrieve the information object from the repository, and transmit the information object to a browser of the user device over the second network.
US10127616B2	Method and apparatus for receiving an insurance quote from an image Some aspects of the invention relate to a mobile apparatus including an image sensor configured to convert an optical image into an electrical signal. The optical image includes an image of a vehicle license plate. The mobile apparatus includes a license plate detector configured to process the electrical signal to recover information from the vehicle license plate image. The mobile apparatus includes an interface configured to transmit the vehicle license plate information to a remote apparatus and receive an insurance quote for a vehicle corresponding to the vehicle license plate in response to the transmission.
US10127614B1	Investment evaluator A system, method and software are disclosed for evaluating investments. In one example, managed trust investments are analyzed with respect to one or more indexes. An indication is created of how the managed investment compares to the one or more indexes or their own benchmarks, and suggested changes to the managed investment may be presented.
US10127613B2	Auditing custodial accounts According to one embodiment of the present invention, a system for auditing custodian accounts is provided. The system includes a database system receiving customer and custodian information. A sorting processor performs a sort operation on the received customer and custodian information. A customer and custodian matching processor identifies matches between the sorted customer and custodian information. An interface unit outputs information relating to the existence of matches and non-matches between the customer and custodian information.
US10127611B2	Method and system for requesting a reservation for a set of contract rights to be offered A method and system for the determination of optimal pricing and allocation of securities in an open, competitive environment. The method and system may also be used in developing pre-markets of other items that are difficult to price and allocate in a competitive manner, such as the underwriting/securitization of contracts for property; future revenue/earning streams from an asset and/or group of assets; underwritten insurance portfolios, intellectual property and other goods and services. The system of price optimization and allocation is accomplished by interactive feedback of information using a display and including competitive participation of individual members of the public (and/or their agents) or institutional buyers over a data network e.g., the Internet, uncovering the nature and identification of demand in a self-organizing fashion. Demand emerges through participants' interaction with the system and with each other, via a graphically-supported, interactive reservation process.
US10127608B2	Read-only user access for web based auction A networked computer arrangement and method in which a manufacturer or service provider may communicate to a plurality of traders the items, including goods and/or services, which may be available for purchase, the quantities of those available items, and any other conditions to be met for the purchase of the available items. Traders may apply guest bidder profiles or entitlement schema to the available goods lists to produce offerings for a plurality of guest brokers. Only bid-relevant product information is presented to each guest broker as needed in order to protect the offering party's overall position on the offered good(s). Guest broker profiles or entitlement schema may be based on perspective contractual arrangements between potential brokers, traders, and a manufacturer or service provider. Offerings are presented to the guest brokers, who are restricted from participating in the bidding process.
US10127605B2	Method and server for processing item identifiers, and computer readable storage medium A method and server for processing item identifiers and a computer readable storage medium are disclosed. In one aspect, the method includes obtaining item transform information of the item identifiers and calculating item transform scores of the item identifiers based on the corresponding item transform information. The method also includes sorting the item identifiers according to the item transform scores of the item identifiers. The method further includes providing the sorted item identifiers to a display terminal.
US10127602B2	Systems and methods for transient local commerce search A system, computer-readable storage medium storing at least one program, and computer-implemented method for a transient local commerce search service is provided. Location data identifying a temporary geographic location of a merchant having a particular product available for sale is received. Temporal data indicating a specified time when the particular product is available at the temporary location of the merchant is also received. It is then determined that the particular product is available within a specified location and at the specified period of time. Display data to display at least one merchant providing the particular product within the geographic location and at the specified period of time is then provided.
US10127601B2	Mesh network applied to fixed establishment with movable items therein Mesh node modules are associated with movable and fixed items in a building such as a grocery store or factory floor to maintain a database of the locations of those items as they are processed through the establishment. The items form a mesh network and relay location information through access points, when in range, to control/monitoring computers.
US10127600B2	Online cart and shopping list sharing Systems, methods, and non-transitory computer readable media providing shared online shopping lists and/or carts among users are disclosed. The method includes receiving a primary virtual shopping cart containing related items generated by a first user. A database entry for the primary shopping cart is created and correlated with a shopping cart identifier in response to a user request. The database entry includes one or more keywords associated with the first user of the primary virtual shopping cart. A query is received from a second user, and a list of primary virtual shopping carts is provided to the second user based on relevancy to the query. In response to a request by the second user, the contents of a selected primary virtual shopping cart is duplicated in a secondary virtual shopping cart associated with the second user.
US10127599B2	System and method for assembling a shared shopping cart A system and a method are provided for assembling, and publishing, a persistent cart of products online. The cart can have products from a single vendor or a variety of different vendors. When the cart is published, various deals, discounts, and incentives can be offered. An individual who created the cart can be rewarded. A computer readable non-transitory storage medium stores instructions of a computer program that when executed facilitates creation of the cart of items to be purchased and selects the individual or group of individuals to whom the cart is published. The purchasing of a cart does not eliminate the availability of the cart for subsequent users.
US10127597B2	System and method for identifying true customer on website and providing enhanced website experience A method for identifying a user of a website as a potential customer and presenting the potential customer with enhanced website content includes: identifying that a user has landed on the website; identifying a user traffic-source; determining if the identified traffic-source matches a traffic-source in a list of customer-based reference traffic-sources; identifying a specific user behavior pattern on the website; determining if the identified specific user behavior pattern matches a behavior pattern from a list of customer-based reference behavior patterns; identifying the user as a potential customer if the identified traffic-source matches a traffic-source in a list of reference traffic sources and the identified specific user behavior pattern matches a behavior pattern from a list of reference behavior patterns; and displaying enhanced content tailored to the potential customer based upon the specific user behavior pattern or excluding display of enhanced content to the user if not a potential customer.
US10127596B1	Systems, methods, and devices for generating recommendations of unique items The disclosure herein provides systems, methods, and devices for generating recommendations of dynamic or unique items. A system for generating recommendations of unique items comprises a data collection engine, a scoring engine, a user penalty calculator, and a recommendation compilation engine, wherein the recommendation engine is configured to transmit to a user access point system a list of recommended alternative unique items predicted to be preferred by a user of the user access point system.
US10127595B1	Categorization of items based on attributes Item-level information of a particular item may be processed to categorize the particular item. In some instances, the particular item may be ranked across multiple merchants that are offering the particular item for acquisition. The ranking may be based on the item-level information that relates to an attribute of the particular item for the individual merchants. For example, the item-level information may include a cost of the particular item at a merchant, a rating of the particular item for a merchant, a number of calories of the particular item for a merchant, and so on. Information regarding the ranking may be displayed or otherwise output to enable the user to identify and order the particular item from a merchant that satisfies the user's needs.
US10127589B2	Method, medium, and system for reducing counterfeits online Systems and methods change a user interface for the purpose of guiding a user in supplementing a product listing with an image to evidence the product's authenticity. Example embodiments include a machine-implemented method for accessing at least one database to retrieve an authenticity criterion mapped to a product and at least one reference image that depicts adequate detail of a product specimen to fulfill the authenticity criterion. The machine can further cause a user device to display the reference image to the user along with a suggestion that the user submit a candidate image depicting similar detail of the product. In some example embodiments, the method further includes retrieving the candidate image, confirming receipt of the candidate image, and displaying the candidate image, as well as adjusting a rank for a candidate specimen based on various factors.
US10127585B1	Interactive method and system for ordering and marketing wine and other products A method and system that uses interactive wine lists and consumer driven advertising to increase search engine rankings for restaurants and wines through social media websites. A user may automatically display an interactive wine list having a graphical interface or “skin” that is unique to a restaurant through a single mobile application by entering the restaurant information or by using geolocation to determine the restaurant at which the electronic device is located. A unique badge system promotes wines on the interactive wine list to increases wine sales from vendors. In addition, tracking allows all user actions and information entered into the interactive wine list to be used for marketing data and for bounce back marketing.
US10127580B2	Dynamically and predictively updating mobile devices as mobile users pass through projected locations This description provides tools and techniques for dynamically and predictively updating mobile devices as mobile users pass through projected locations. These tools may provide methods that include defining thresholds applicable to at least portions of travel itineraries on which mobile users are traveling. The methods may also identify advertisements to send to mobile devices associated with the mobile users, upon meeting the threshold. The methods may also send the selected advertisements, as associated with corresponding advertisers, to the mobile devices.
US10127575B1	Systems and methods for determining impact of high-affinity baskets The systems and methods described herein attempt to capture the impact on both the promoted items and other related products. The systems and methods analyze attached sales impact only for items that are more likely to be purchased with the featured product. The systems and methods also allow for measuring a cannibalization impact by analyzing the impact on potential cannibalized products and items that are more likely to be purchased with the cannibalized products. By aggregating the promoted impact and cannibalized impact, including the items with strong co-selling relationships, a full picture of the promotion can be obtained. Further, combining the item-level results into custom groupings can allow for further business insights.
US10127574B2	Internet marketing analytics system An internet marketing analytics system to quantify visitor website activity, the system including a database having a plurality of parameters having any portion of the following; site visits, total revenue, bounce rate, conversion rate, orders, average order value, value per visit, pages per visit, new visits, units, cart additions, cart removals, internal search, click through rate, revenue per visit, open rate, email list, impressions, visit duration, percent new visitors, percent return visitors, post volume, net promoter score, social referring traffic, total cost, search term, exit rate, page views, and product type, plus non website related visitor internet activity. The system producing a multi-variate visual spatial display of the database including at least three parameters being simultaneously displayed and modifying the display to selectively emphasize a parameter to be displayed as an X, Y, or Z axis for clarity, for modifying a component of the database to optimize website efficiency.
US10127567B2	Methods and apparatus to apply household-level weights to household-member level audience measurement data Methods and apparatus to apply household-level weights to audience measurement data at a household-member level are disclosed. An example method to determine demographics of populations to measure media audiences of populations includes determining demographics for members of a first household of a sub-population. First demographics of a first member of the first household are different than second demographics of a second member of the first household. The example method includes calculating a first household-level weight for the first household based on a demographics distribution of the sub-population and aggregate demographics of a population. The example method includes applying the first household-level weight to the first demographics of the first member, applying the first household-level weight to the second demographics of the second member, and estimating a demographics distribution of the population to measure a media audience of the population based on the weighted first demographics and the weighted second demographics.
US10127564B2	System and method for using impressions tracking and analysis, location information, 2D and 3D mapping, mobile mapping, social media, and user behavior and information for generating mobile and internet posted promotions or offers for, and/or sales of, products and/or services A method, apparatus, computer readable medium, computer system, network, or system, is provided for using impressions tracking and analysis, location information, 2D and 3D mapping, social media, and user behavior and information for generating mobile and internet posted promotions or offers for, and/or sales of, products and/or services, for example, through an advertising application programming interfaces (APIs) on mobile devices, tablets, or computers, that provides mobile and web based promotions or offers that connect information and user behavior data to a user or related demographic location or user specified or predicted demographic location(s), such as through the use of as social networking, user or demographic profiles, behavior, and/or relationships, for targeted promotions or offers for products and/or services.
US10127559B2	Integrating metadata from applications used for social networking into a customer relationship management (CRM) system Integrating metadata from applications used for social networking into a customer relationship management (CRM) system includes obtaining, from applications used for social networking, metadata associated with users of the applications, analyzing the metadata from the applications to infer opportunities, relationships for mapping clients, structures, and subject matter experts, and integrating the opportunities, the relationships for mapping the clients, the structures, and the subject matter experts into a CRM system to populate the CRM system.
US10127558B2	Expense tracking, electronic ordering, invoice presentment, and payment system and method Systems and methods for automating an invoice approval process are described herein. Rules are created which are evaluated against a set of attributes. A rules engine is automatically invoked upon receipt of a document in an electronic invoice presentment and payment system. The rules engine determines which rules are applicable to documents received and processed in the system, and applies those applicable rules in a pre-defined sequence.
US10127556B2	Method for logging and reporting driver activity and operation of a vehicle An automated at-the-pump method manages vehicle fuel purchases at a fuel station. The method includes transmitting driver identification data to a mobile device assigned to a vehicle driver. The driver identification data is electronically verified to confirm that the driver identification data received by the mobile device matches the assigned vehicle driver. Vehicle data is transmitted from a data bus of the vehicle to the mobile device for storage in the memory. The vehicle data and driver identification data are transmitted to a remote terminal. Using the remote terminal, the vehicle data and driver identification data are electronically authenticated. An authorization signal is then transmitted from the remote terminal to an at-the-pump fuel control terminal.
US10127555B2	Enhanced communication platform and related communication method using the platform Pre-authorized communication services and/or transactions are provided via a plurality of networks in response to a request received from a user to provide at least one of a communication service, a transaction and user account information via a plurality of networks of different types. Prior to processing the request, there is verification of the users authorization to receive the at least one of the communication service, the transaction, and the user account information, and that an account associated with the user has a sufficient amount currently available for payment of the at least one of the communication service and the transaction. After verification, an authorized account associated with the user is charged in real time as the at least one of the communication service and the transaction is provided.
US10127554B2	Fraud early warning system and method A fraud early warning system and method for monitoring transactional behavior of an account holder and evaluating that behavior by comparing it to biographical data and/or the past behavior of the account holder. The system and method is applicable to real-time wire transfers, online transactions, automated teller machine transactions, point-of-sale transactions, etc.
US10127552B2	Cryptocurrency aggregation system A system includes a memory and a processor. The memory may store a customer account associated with a customer and an enterprise account associated with an enterprise. The processor may be communicatively coupled to the memory and may cause the system to receive a request to deposit a first amount of a cryptocurrency in the customer account from the customer. The processor may also cause the system to determine a public key associated with the customer account and receive the first amount of the cryptocurrency. The processor may further cause the system to determine a first value approximately equivalent to the first amount of cryptocurrency and associate the first value with the customer account. The processor is further able to aggregate the first amount of cryptocurrency with an aggregated amount of the cryptocurrency in the enterprise account and facilitate securing the public key in the enterprise account.
US10127551B2	System for modeling and implementing event-responsive resource allocation structures Embodiments of the invention are directed to systems, methods, and computer program products for implementing a change in a parameter associated with an event-responsive resource allocation structure, such as a named beneficiary, and predicting that the current parameters of an event-responsive resource allocation structure a unlikely to be congruent with a user's desired configuration of the parameters of the event-responsive resource allocation structure.
US10127550B2	Secure authentication and payment system A transaction and payment and processing system securely conducts transactions over the public telephone network. The transactions may be between and among entities of any type such as individuals, merchants, utilities, banks, etc. Nothing more than access to a telephone is required after initial registration of a user.
US10127548B2	System for packaging, processing, and activating a bundled greeting and gift card A greeting card stored-value card combinations and methods of forming said combinations are provided. In one embodiment, these combinations include a greeting card comprising means for affixing a stored-value card thereto. These combinations also include a stored-value card affixed to the greeting card. A single identifier, such as a Stock-Keeping Unit (SKU) or a Universal Product Code (UPC), is assigned to the bundle that uniquely identifies the bundled greeting card and stored-value card. The single identifier provides identification means allowing the stored-value card to be activated. A single capture of the single identifier enables the customer to both purchase the greeting card stored-value card combination product as well as to activate the store-value card.
US10127545B2	Methods and systems for displaying account information Systems and methods are provided for displaying account information. The systems and methods may include a portable smart display device in short-range communication with a mobile device. The smart display device may be configured to provide a user with quick and easy yet secure access to account information, without the need for multi-step login and verification processes. The smart display device may be sized to fit within a wallet and within quick, easy reach of a user. The smart display device may receive up-to-date account information from the mobile device, and display the account information on-demand upon detecting an activation event, thereby providing an enjoyable user experience and a useful tool for quickly informing the user of their financial situation.
US10127543B2	Systems and methods for communicating with a magnetic reader head A device and method for waveform transmission of transaction card data to a merchant point-of-sale device are provided. The device includes a memory device for storing data, a processor, and a transmitter. The device is programmed to receive transaction card data that mimics data stored within a magnetic stripe associated with a transaction card, convert the transaction card data to a first data file for storage within the memory device, transmit the first data file to the transmitter, and transmit a first waveform from the transmitter to the POS device, wherein the first waveform includes changes in a magnetic field that represent the transaction card data.
US10127535B2	Method of and system for authorizing purchases made over a computer network A method of and system for authorizing purchases made over a computer network is provided. In accordance with the present invention, a consumer electronically transmits an ATM card number over the network to an on-line merchant from which the consumer desires to make a purchase. The on-line merchant then electronically forwards the ATM card number to a third party contractor, such as a bank, that will oversee and authorize the transaction. The third party contractor subsequently determines an authentication token type associated with the card and electronically prompts the consumer for the appropriate type of authentication token, such as a PIN or biometric signature or the like. The consumer then inputs and electronically transmits the authentication token over the network to the third party contractor, bypassing the on-line merchant. Having both the ATM card number and the authentication token, the third party contractor verifies that the ATM card number and authentication token are valid, checks for sufficiency of funds, and either authorizes or denies the transaction. The authorization or denial is communicated to the on-line merchant over the network, who either completes or rejects the purchase.
US10127533B2	Managing devices associated with a digital wallet account Managing user devices associated with a digital wallet account comprises associating, using one or more computing devices, one or more user computing devices with a digital wallet account of a user, each of the associated one or more user computing devices being activated to conduct financial transactions with a merchant utilizing the digital wallet account; presenting the associated user computing devices in a list of associated user computing devices; receiving a request to deactivate a particular user computing device from the list of associated user computing devices; deactivating the particular user computing device, the deactivation being sufficient to prevent the user computing device from conducting transactions with a merchant utilizing the digital wallet account; and presenting a deactivated status of the particular user computing device.
US10127532B1	Customized transaction flow Disclosed is a technology for customizing the flow of a payment transaction at a payer's mobile device, based on parameters associated with a payee to which the payer is making the payment. The payee can be an individual person or a specific business entity (e.g., restaurant, political cause, professional service, etc.). The transaction flow technology involves communication between a mobile application installed on the mobile device and a remote payment service system (PSS). A list of potential payees can be displayed for selection by the payer at the mobile application. The payees can be nearby payees identified by using, e.g., BLE, Bluetooth®, Wi-Fi®, geofence, etc. Upon selection of a particular payee by the payer, the PSS identifies one or more parameters of that payee, e.g., payee type, and generates a transaction flow to guide the payer through a payment transaction with the selected payee based on those parameters.
US10127529B2	User attribute value transfer method and terminal A user attribute value transfer method, includes: obtaining a picture; performing facial recognition to recognize human faces in the picture; according to an entered instruction, determining a target human face selected from recognized human faces and determining a corresponding target attribute value; generating an attribute value transfer request according to the target attribute value and corresponding facial recognition information; and sending the attribute value transfer request to a server, so that the server performs an attribute value transfer operation according to the attribute value transfer request.
US10127527B1	Systems and methods for relationship management A relationship management system and method are configured to enable a user to manage a relationship with their contacts from the initial interaction through the life cycle of a transaction or relationship and beyond. For example, a relationship management system may record and sort all communications (for example, phone calls, text messages, and emails) into a contact's profile, empowering a user to easily see the entire relationship at a glance. Moreover, using actionable business intelligence, an exemplary relationship management system may utilize a workflow engine to send notifications, schedule tasks, and allow users to see reports, thus allowing a user to increase productivity and save time. Exemplary relationship management systems are configured for use in the multi-family housing industry.
US10127523B2	Method and apparatus for mobile quality management inspections A mobile Quality Management/Control system for performing mobile product inspections is provided. A mobile device, such as a tablet, is configured to communicate with one or more databases and allow for real time entry (and subsequent access) of the details of product inspections for quality control and management purposes. The details of such inspections are maintained and available for all subsequent inspections. The mobile device is further configured to provide inspectors with inspection procedures and/or tutorials associated with the inspections being performed.

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