| Document | Document Title |
|---|---|
| US10091404B2 |
Illumination apparatus, imaging system, and illumination method
The illumination apparatus according to the present disclosure emits illumination light to an object which is to be captured by an imaging apparatus that captures an imaging area for every predetermined capturing unit. The illumination apparatus includes a controller that acquires imaging information including a scanning timing from the imaging apparatus to calculate an imaging range of the imaging apparatus at each the scanning timing, determines an illumination range at each the scanning timing using a distance to the imaging apparatus from the object present within the imaging range and a positional relation between the imaging apparatus and the illumination apparatus, and controls emission of the illumination light to the determined illumination range in synchronization with the scanning timing. |
| US10091397B2 |
System including image forming apparatus and lattice point group generating device that generates group of pre-color conversion lattice points to be contained in color conversion table used for conversion of colors in RGB color space to colors in CMYK color space in the image forming apparatus
A lattice point group generating method generates a group of pre-color conversion lattice points to be contained in a color conversion table for conversion of colors in a color space having three channels to colors in another color space. The method includes generating sequences and generating lattice points. The generating sequences generates three van der Corput sequences in which the number of terms is equal to a quotient obtained by subtracting a specified number from a maximum number of lattice points allocatable to the color conversion table and dividing the difference by 12 or 6, and whose basis is a positive integer greater than or equal to 2. The generating lattice points generates lattice points each located at coordinates including terms in the same ordinal number out of the three respective van der Corput sequences for six possible associations of the three van der Corput sequences with the three channels. |
| US10091396B2 |
Information analysis system and information analysis method
A reading device scans receipts, and transmits image data of the receipts to an analyzer. The analyzer receives the image data, extracts images of the receipts from the image data; counts a number of the images; executes a character recognition process to obtain text data; transmits, to the display device, a number of all of the images, and sequentially transmits, to the display device, the images for which the character recognition process has been completed, together with the text data. The display device sequentially displays each image, together with the text data; and upon detecting that the number of all of the images matches a number of the sequentially transmitted images, receives a command to report to the analyzer that the reception the images is completed. |
| US10091395B2 |
Image forming apparatus, method, and computer-readable recording medium for login and logout management based on multiple user authentication factors
An image forming apparatus includes a first authenticator, a second authenticator, and an apparatus authenticator. The first authenticator is configured to perform first authentication. The second authenticator is configured to perform second authentication. The apparatus authenticator is configured to permit a user who has been authenticated in both the first authentication and the second authentication to use the image forming apparatus, and cancel the permission of use of the image forming apparatus for the user when the authentication of the user is canceled in at least one of the first authentication and the second authentication. |
| US10091390B2 |
Image processing apparatus and image processing method for extracting feature points of a document image
An image processing apparatus obtains image data of a document image and extracts a plurality of feature points of the document image. The image processing apparatus obtains a skew angle of the document image with respect to a predetermined direction and an assembling angle of an image obtaining unit with respect to a predetermined assembling direction from a coordinate correspondence relationship between coordinates of a plurality of feature points of a registered document image registered in advance and coordinates of the plurality of extracted feature points of the document image. |
| US10091389B2 |
Wireless communication apparatus for determining wireless communication to be used, wireless communication terminal for determining wireless communication to be used, and computer-readable and non-transitory recording medium storing program for selecting wireless communication to be used
A wireless communication apparatus that operates on electric power supplied from a battery includes a first wireless communication unit that performs a first wireless communication, a second wireless communication unit that performs a second wireless communication that consumes less electric power than the first wireless communication, a battery's state detection unit that detects a state of the battery, and a first control unit that controls the first wireless communication unit and the second wireless communication unit. The first control unit determines which one of the first wireless communication and the second wireless communication to adopt as a wireless communication that is to be used for communication, on the basis of the state of the battery detected by the battery's state detection unit. |
| US10091387B2 |
Image forming device supporting short range wireless communication and method for operating same, mobile terminal supporting short range wireless communication and method for operating same, and cloud print system using short range wireless communication
Provided is an operating method of an image forming apparatus, the operating method including broadcasting a plurality of packets comprising identification information of the image forming apparatus; receiving a connection request comprising the identification information of the image forming apparatus from a mobile terminal which received some packets from among the plurality of broadcasted packets; and connecting to the mobile terminal, based on the connection request, wherein the connection request is transmitted from the mobile terminal when received signal strengths of the some packets received by the mobile terminal are equal to or greater than a first threshold value. In this regard, the first threshold value may indicate a received signal strength greater than a minimum received signal strength at which communication with the mobile terminal is available. |
| US10091386B2 |
Circuits for determining parameters for controlling an image sensor of an image capturing device and associated method
A method for controlling an image capturing device includes: calculating luminance data of a first image to generate a plurality of first characteristic values, and calculating luminance data of a second image to generate a plurality of second characteristic values; calculating a plurality of motion values of a plurality of blocks of the second image according to the luminance data of the first image and the luminance data of the second image; determining a plurality of ratio parameters corresponding to the blocks of the second image according to the motion values; generating a plurality of adjusted second characteristic values according to the ratio parameters, the second characteristic values and the first characteristic values; and generating an adjustment signal for controlling the image capturing device according to the adjusted second characteristic values. |
| US10091382B2 |
Illumination apparatus and sensor unit
Provided is an illumination apparatus that applies light to an original, the illumination apparatus including: a light source; and a rod-shaped light guide including: an incident surface that receives the light from the light source; a reflection surface provided with a diffusion portion that diffuses the light incident on the incident surface; and an emission surface that emits, to the original, the light diffused by the diffusion portion. An area of the light guide is reduced by an inclination of the light guide from the incident surface side to a middle part in a longitudinal direction of the light guide, and the light guide is provided with the diffusion portion from the incident surface side to the middle part on the reflection surface. |
| US10091370B2 |
External storage medium processing device and program
An external storage medium processing device includes a plurality of receiving units to and from which the external storage medium can be attached and detached. Further, when detecting that the external storage medium is attached to the receiving unit at the time of startup, a control unit collates identification information stored in a storage unit with identification information acquired from the external storage medium. A notification unit does not perform notification of attachment if identification information is matched and, if not, performs notification of attachment. |
| US10091364B2 |
Reverse power supply method and reverse powering equipment and system
Reverse powering equipment includes: a power supply module, configured to supply power resources to a distribution point unit by using a line; a switch, configured to control whether the power supply module supplies power; a line test module, configured to: when the switch is opened and the power supply module does not supply power, test whether a user terminal is connected to the line; and a system control module, configured to send an alarm signal when the line test module determines that a user terminal exists on the line, and after a user disconnects the user terminal, control the switch to be closed and the power supply module to supply power. The reverse powering equipment can prevent the user terminal from being damaged. |
| US10091361B1 |
Queueing communications for a contact center
Various embodiments of the invention provide methods, systems, and computer program products for routing a communication in a contact center. Specifically, a treatment is selected for a communication from a plurality of treatments supported by the contact center. Here, each treatment includes a set of sub-queues and is applicable to a reason and/or opportunity for conducting a communication with a party. Each sub-queue includes a value range and a plurality of agents assigned to handle communications placed in the sub-queue. Accordingly, in particular embodiments, a communication value is determined for the communication based on a computation specific to the selected treatment and a sub-queue is selected from the set of sub-queues based on the communication value falling within the value range for the sub-queue. The communication is then placed in the selected sub-queue so that it can be connected to an agent assigned to handle communications placed in the sub-queue. |
| US10091358B1 |
Graphical user interface for call center analysis
One or more embodiments related to a method of generating a graphical user interface. The method includes obtaining a metric interface hierarchy having multiple nodes, where each node defines a visualization for the node, and the metric interface hierarchy defines an ordering on the nodes. The method further includes traversing the metric interface hierarchy starting with a selected node to obtain a subhierarchy, and creating the graphical user interface from a general interface by populating the general interface with the visualization from each node in the subhierarchy according to the ordering. The method further includes providing the graphical user interface. |
| US10091357B1 |
System and method for automated performance monitoring
A method and system for evaluating the performance of individuals, such as agents in a call center, each performing multiple tasks may include obtaining a performance score for each execution of a task by individuals in the group of individuals; determining the distribution of the performance scores; comparing single performance scores with the distribution of performance scores; and selecting a single performance score for an individual based on said comparison. An oscillator algorithm may be used to determine whether said selected performance score is part of a trend in performance by that individual. |
| US10091356B2 |
Interactive voice response system crawler
A system for interactive voice response system crawling, comprising an IVR crawler that may be VXML, design specification, DTMF or ASR/NLSR speech-based in nature and traverses an IVR menu to discover possible interaction paths and produces test cases based on those paths, and a database that stores test cases produced by the IVR crawler during operation, and a method for interactive voice response system crawling utilizing the IVR crawler of the invention. |
| US10091353B1 |
Identical conversation detection systems and processes
Systems and methods are described relating to detection of audio of voice communications from different reference points containing an identical conversation or portion of a conversation. A method can use an analytics module operating on at least one processor. Call signatures of a plurality of audio of voice communications are received. An index loaded with the call signatures is created, where segments of the call signatures are associated with buckets of the index. A first subset of one or more of the buckets associated with a number of the segments that exceeds a threshold is identified. An identical conversation portion in two or more of the plurality of audio of voice communications is identified based on a second subset of one or more of the buckets, where the first subset of one or more of the buckets is disregarded. |
| US10091351B2 |
Telecommunication call management and monitoring system with voiceprint verification
Disclosed is a secure telephone call management system for authenticating users of a telephone system in an institutional facility. Authentication of the users is accomplished by using a personal identification number, preferably in conjunction with speaker independent voice recognition and speaker dependent voice identification. When a user first enters the system, the user speaks his or her name which is used as a sample voice print. During each subsequent use of the system, the user is required to speak his or her name. Voice identification software is used to verify that the provided speech matches the sample voice print. The secure system includes accounting software to limit access based on funds in a user's account or other related limitations. Management software implements widespread or local changes to the system and can modify or set any number of user account parameters. |
| US10091349B1 |
Fraud detection system and method
A system and method for fraud detection for a telephony platform based on an analysis of call detail records (CDRs) that are generated by the telephony platform. The analysis is based on collecting, organizing, transforming, analyzing, and quantifying the CDR data into a plurality of data analytics and data correlations and then applying fuzzy logic to the data analytics to generate a fraud risk rating for each incoming call into the platform. |
| US10091348B1 |
Predictive model for voice/video over IP calls
Disclosed is a system and method for forecasting the expected quality of a call. In some examples, a system or method can generate a plurality of scenarios from network metrics, retrieve historical ratings for the network metrics from users, and assign the historical ratings for the network metrics to the plurality of scenarios. The system or method can also filter one or more users based on similarities of the historical ratings for the plurality of scenarios with current network metrics, and forecast an expected call quality based on the historical ratings of the one or more filtered users. |
| US10091345B2 |
Media out interface
Methods, systems, and computer-readable medium for providing a media out interface. In one implementation, a method is provided. The method includes, at a host device, detecting a mobile device coupled to the host device, and displaying on a display device coupled to the host device an interface including interface elements, which can be manipulated by commands received from the mobile device or another device, wherein the interface enables control of the display of content received from the mobile device and displayed on the display device. |
| US10091336B2 |
Computing platform agnostic application server
A method includes providing a cloud-side database storing data, an objects model of the data, and a user interface (UI) model of the data. The method further involves providing an instance of an application server coded in JavaScript, for example, in a Node.js cross-platform runtime environment. The instance of the application server coded in JavaScript includes the logic of an application coded to process the data. The application logic is executed (and data processed) on either the client-side or on the cloud-side. The execution of the application logic (and processing of the data) is dynamically switchable between the client-side and the cloud-side. |
| US10091335B2 |
Data transmission and rendering techniques by a device via a network
A technique is disclosed for generating formatted information for display on a computing device. The computing device may be configured to include at least one interface for communicating with a server computing device. A request is sent from the computing device to the server system. According to one embodiment, the request may correspond to an HTTP request for information relating to a specific HTML page or web page. A response is then received from the server system. According to one embodiment, the response includes response information comprising embedded instructions and data. The embedded instructions may include instructions for using the data to generate formatted markup information for display on the computing device. The embedded instructions are then executed on the data to thereby generate formatted markup information for display on the computing device. According to a specific embodiment, the formatted markup information corresponds to HTML data to be rendered for display on the computing device. |
| US10091333B2 |
System and method for supporting a bypass-domain model for across-domain messaging in a transactional middleware machine environment
A system and method can support across-domain messaging in a transactional middleware machine environment. A transaction domain can import one or more services from a remote transaction domain, wherein said one or more services are registered in a service table that is associated with the transaction domain. Furthermore, a client in the transaction domain can find from the service table a remote server in the remote transaction domain that provides said one or more services, and send a message directly to the remote server to invoke said one or more services by passing one or more domain gateway servers in both the transaction domain and the remote transaction domain. |
| US10091331B1 |
Prioritized download of social network content
A computer-implemented method includes identifying, with a computer system that has a network interface, one or more primary categories of content from a social networking system that are of primary relevance to a user of a computing device, as compared to one or more secondary categories of content from the social networking system that are of lower importance to the user of the computing device; causing content from the primary categories to be downloaded from the social networking system to the computing device automatically and without user interaction with a social networking application that is arranged to display the downloaded content; and causing content from the secondary categories to be downloaded from the social networking system to the computing device separately from the content from the primary categories, and in response to a defined user interaction with a social networking application that corresponds to the social networking system. |
| US10091330B2 |
Interest scheduling by an information and data framework in a content centric network
One embodiment provides a system for facilitating scheduling of interests in a CCN. The system determines, by a scheduler component, network properties associated with name prefixes of interests transmitted by a plurality of local applications, wherein a name for an interest is a hierarchically structured variable length identifier that includes contiguous name components ordered from a most general level to a most specific level, and wherein a name prefix includes one or more contiguous name components. The system generates a first interest which indicates a command to set a window size for a transport stack associated with a respective local application based on the network properties. The system transmits the first interest to a component associated with the transport stack, which causes the component to set the window size for the transport stack, thereby facilitating scheduling of interests based on the network properties. |
| US10091329B2 |
Device gateway
A computing environment is disclosed that receives from devices requests directed toward services accessible in the environment, and that forwards communications from services in the environment to devices registered with the environment. During a registration process at the environment, devices are assigned a device identifier that is used to identify and authenticate each particular device and requests communicated from and to the device via the environment. The computing environment maintains state information for each device that has been registered with the system. As the device interacts with the system, the state information is updated to reflect the changes in the device. When requests to perform functions are received from devices, the computing environment determines for the particular device and the particular function requested what processing needs to be performed by the environment in response to the request. |
| US10091323B2 |
Social discovery feed for facilitating social exploration in social networking environments
Systems and methods of generating a common social timeline to facilitate social discovery in a social networking environment are disclosed. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, of receiving data items associated with users of the social network, identifying a first set of data items associated with a first user, and processing the first set of data items to select a first set of characteristics. The method further comprises comparing the first set of characteristics with other sets of characteristics describing other users to select a subset of the other users having one or more characteristics that are the same or similar to one or more of the first set of characteristics. |
| US10091321B2 |
System and process for dynamically updating a web page
At least one embodiment of the invention relates to a system and process for dynamically updating a web page. This can occur by automatically modifying data over a computer network comprising a first application server, a database server, at least one proxy server, at least one computer network coupling the first application server, the database server, and the at least one proxy server together. The at least one remote computer is coupled to the at least one computer network, wherein the at least one remote computer is configured to communicate through the at least one computer network to the proxy server and wherein the application server is configured to update data to be presented on the proxy server such that a user in communication with the computer network receives an updated web page. |
| US10091320B2 |
Distributed cache for state transfer operations
A network arrangement that employs a cache having copies distributed among a plurality of different locations. The cache stores state information for a session with any of the server devices so that it is accessible to at least one other server device. Using this arrangement, when a client device switches from a connection with a first server device to a connection with a second server device, the second server device can retrieve state information from the cache corresponding to the session between the client device and the first server device. The second server device can then use the retrieved state information to accept a session with the client device. |
| US10091317B2 |
Proximity-based content sharing scheme
A method and apparatus for proximity-based content sharing on wireless devices is presented in which a first device having a wireless communication region surrounding the device detects other wireless devices within the region. Communication connections are formed between the wireless devices. In response to a user action data is pushed from the wireless device to other wireless devices in the region. Communication connections can also be formed between devices in the region and devices outside the region and data may be pushed to the devices outside the region. Users can block other devices either within the region or outside the region so that they do not receive pushed data. |
| US10091315B1 |
Systems and methods of determining a geographic location based conversion
Systems and methods of determining a geographic location based conversion via a computer network. A data processing system can receive, from a computing device, an indication of interest in an online content item that is associated with a commercial entity having a location. The system can also receive data points that each include time information and location information of a computing device. The system can generate a valid cluster indicating an activity at the location of the commercial entity by evaluating the time information and the location information of two or more data points with a duration threshold and a location threshold. The system can use the valid cluster to identify the indication of interest in the online content item as the location based conversion based on the activity at the location of the commercial entity. |
| US10091314B1 |
Systems and methods of determining a geographic location based conversion
Systems and methods of determining a geographic location based conversion via a computer network. A data processing system can receive, from a computing device, an indication of interest in an online content item that is associated with a commercial entity having a location. The system can also receive data points that each include time information and location information of a computing device. The system can generate a valid cluster indicating an activity at the location of the commercial entity by evaluating the time information and the location information of two or more data points with a duration threshold and a location threshold. The system can use the valid cluster to identify the indication of interest in the online content item as the location based conversion based on the activity at the location of the commercial entity. |
| US10091310B2 |
Method and system for high-latency data collection from sensors
A method and system are disclosed that collect data from various devices, such as sensors, to a mobile device traveling in proximity to such devices. The mobile device may travel with a user who is traveling a regular-scheduled route. The devices may output a signal at a low frequency to preserve battery power. The mobile device may form an ad hoc connection with the devices using Bluetooth Low Energy, for example, and retrieve the data while the mobile device is in proximity to each of the devices. In this manner, the devices do not need to transmit data over long ranges or at a high speed, thereby preserving batter power for the devices. |
| US10091307B2 |
Application management method and terminal
An application management method and a terminal, where the method includes acquiring a list of applications needing to retain background data in a terminal and suspending a first timer corresponding to a first application running in the terminal when the first application running in the terminal is not in the list of the applications needing to retain the background data. Further, timers of applications that do not need to retain background data in the terminal can be suspended. Because the timers stop to be run temporarily, the timers do not wake up the terminal from a dormant state, and correspondingly, the applications do not need to interact with a server end to update the background data, thereby reducing the number of times of waking up the terminal from a dormant state, saving electricity consumption and data traffic of the terminal. |
| US10091302B2 |
Service system
A service system in the field of collecting human breast milk or in the field of medical drainage has a base unit assigned to an individual or an entity and at least one mobile data medium. The mobile data medium can be brought by a user into data-communicating connection on the one hand with products in the field and on the other hand with the base unit. The base unit can be brought by the user into communicating connection with an external information and data platform. The system according to the invention offers optimal care and support of users in the field. |
| US10091301B2 |
Automatic external sensor interface
A monitor device having a sensor interface includes a connector portion configured to mechanically interface with one or more sensors of a pre-defined type. A hardware interface layer is configured to determine a sensor type and establish a communication interface with the sensor type. A hardware abstraction layer is configured to store a plurality of protocols corresponding with the one or more sensors of a pre-defined type. The hardware abstraction layer communicates with the sensor using a selected protocol for that type through the communication interface to permit interaction between the device and the sensor type. |
| US10091299B2 |
Vehicle group monitoring
A solution for managing vehicles both individually and as a group of associated vehicles is provided. A vehicle node can be located on each vehicle in the group and obtain and process data from a plurality of sensors also located on the vehicle. The vehicle node can be configured to communicate, either directly or indirectly, with a group system assigned to the group using a wireless communications solution. The group system can acquire monitoring data for all of the group of associated vehicles, which can be used to manage the group of associated vehicles and/or one or more individual vehicles in the group. The group system can be located on a vehicle traveling as part of the group of associated vehicles or at a fixed location. |
| US10091294B2 |
Networking component management in host computing systems in a virtual computing environment
Techniques for managing networking components in a host computing system in a virtual computing environment are described. The networking components include virtual switches and physical network interface cards (NICs). In one embodiment, a virtual switch that is not coupled to any running virtual machines in a host computing system is identified. Further, physical NICs associated with the virtual switch are identified. Furthermore, the virtual switch and the physical NICs associated with the virtual switch are placed into a standby mode. |
| US10091293B2 |
Rapid cloud-based image centralization
A system for a mass centralization approach to full image cloning of multiple computing devices is provided. The system includes a server, and a computing device that includes a disk for data storage, wherein the disk includes a plurality of blocks within a plurality of regions. The system also includes a processor programmed to map each file stored on the disk to at least one of the plurality of blocks, for one or more of the plurality of regions of the disk, determine that a number of files appearing in sequential blocks exceeds a predefined threshold number of files, perform a continuous scan of the one or more of the plurality of regions of the disk occupied by the number of files appearing in sequential blocks exceeding the predefined threshold number of files, and send a copy of the files scanned from the one or more plurality of regions of the disk to the server. |
| US10091291B2 |
Synchronizing a source, response and comment presentation
For displaying a source presentation with accompanying timed responses and comments, a synchronization module synchronizes client time codes with a host time code as a medium module records responses and comments on the source presentation. |
| US10091287B2 |
Determining presence in an application accessing shared and synchronized content
A device collects presence information and other interaction information from an application viewing a content item synchronized with a content management system. The interaction information indicates interactions of a device with respect to a content item, and includes presence information obtained from a native application such as whether the content item is being viewed by the user on a user interface element or the user interface element is modifying the content item. A presence management module receives presence events indicating possible change of presence with respect to a user interface window associated with a process and a synchronized content item. Such presence events include a change in focus of a user interface element indicating that a user is viewing the content item, and changes to a content item indicating a user is editing the content item. |
| US10091286B1 |
Method and system for enhanced client-server communication in a cached communication environment
Enhanced client-server communication in a cached communication environment is described. A server computer executes a server application. The server application requests a server communication application to generate a server object. The server object is independent from a client object that is modified to communicate client data. The server object is associated with a server object identifier. The server application receives a copy of the client object from the server communication application. The copy of the client object is associated with a client object identifier. The server application determines whether the server object identifier has an expected relationship with the client object identifier. The server application applies a disposition rule to data referenced in the copy of the client object if the server object identifier has the expected relationship with the client object identifier. |
| US10091285B1 |
Distributing information over a network
Distributing information over a network is disclosed. Nodes are grouped into regions. Preferred nodes are designated. A source of content to be delivered to a preferred node using a preferred algorithm is indicated to at least one preferred node. At least one common node is assigned the preferred node as a relay of information. |
| US10091280B2 |
Data transfer control apparatus that control transfer of data between nodes and parallel computing system
A data transfer control apparatus controls transfer of data from a plurality of first nodes included in a first region in a network to a plurality of second nodes included in a second region in the network. A control unit of the data transfer control apparatus generates an n-dimensional Latin hypercube in which the number of symbols in each dimension is a value in keeping with a size of the first region. The control unit then associates, in accordance with respective positions of the first nodes in the first region, each first node with a symbol at a corresponding position in the Latin hypercube. The control unit then instructs the first nodes so that parallel data transfers by a plurality of first node sets, where first nodes associated with a same symbol in the Latin hypercube are grouped, are executed in order in first node set units. |
| US10091277B2 |
Method, server, client and software for image processing
A client device is disclosed. The client device comprises: a communication unit configured to receive a plurality of parameters, the parameters defining segments of an image stored on a server, wherein the segments do not overlap; a processing unit configured to allow selection of a segment of the image in accordance with a defined view on the client device and wherein upon selection the segment and an adjacent segment are downloadable from the server; a plurality of the decoders operable to decode the segment and the adjacent segment and a display configured to display on the client device the cut out of the image taken from the segment. |
| US10091272B2 |
Method and apparatus for remotely controlling home device in home network system
A method for remotely controlling a home device in a mobile terminal is provided. The method includes receiving a chat message input to the mobile terminal for controlling at least one home device through an instant messenger application installed in the mobile terminal, and sending the chat message to a messenger server. The sent chat message is converted into a control command, which is sent to the home device. |
| US10091257B2 |
Managing a virtual waiting room for online meetings
A server or other computing device manages meetings in a virtual meeting room on behalf of a virtual meeting room owner. A request is received from an attendee to join a meeting in the virtual meeting room. A determination is made, based on configurations set by the virtual meeting room owner, whether to connect the attendee to a virtual waiting room. The attendee is connected to the virtual waiting room in accordance with the configurations set by the virtual meeting room owner. |
| US10091254B2 |
System, method, and computer program product for resolving addressing in a network including a network address translator
A system, method, and computer program product through which address resolution is performed for nodes of a network that are behind a network address translator (NAT). A determination is made upon the initiation of a communication session as to whether one or more of the nodes included in the session are behind a NAT. Based on the determination, information is exchanged from an independent application server to the nodes included in the session so as to resolve the addressing problems introduced by the NAT. The invention is applicable in applications including, but not limited to, IP telephony, and applications complying with the session initiation protocol (SIP). |
| US10091252B2 |
Endpoint control for a communication session
Techniques for endpoint control for a communication session are described. According to various embodiments, a claim process is performed that establishes a control relationship between a controller and an endpoint device. The controller then causes the endpoint device to initiate a communication session with a different endpoint device using an identity of the controller. The endpoint device outputs a media stream that includes session media exchanged as part of the communication session. |
| US10091250B2 |
Proxy persona to aid facilitation of capturing information on behalf of an end user during real time collaboration
A method for enabling a user to create a proxy persona to attend a meeting on behalf of the user, whereby the meeting is associated with a communication system for requesting a person to be available for a scheduled event is provided. The method may include providing a user interface (UI) to enable the user to create the proxy persona and a plurality of predetermined configuration rules. The method may also include activating the proxy persona in response to a manual activation by the user or an automatic activation based on the plurality predetermined configuration rules being satisfied. The method may further include authorizing the proxy persona to participate in the meeting on behalf of the user, wherein the authorization is in response to the proxy persona being activated. |
| US10091248B2 |
Context-aware pattern matching accelerator
Methods and systems for improving accuracy, speed, and efficiency of context-aware pattern matching are provided. According to one embodiment, a packet stream is received by a first stage of a hardware accelerator of a network device. A pre-matching process is performed by the first stage to identify a candidate packet that matches a string or over-flow pattern associated with access control (e.g., IPS or ADC) rules. A candidate rule is identified based on a correlation of results of the pre-matching process. The candidate packet is tokened to produce matching tokens and corresponding locations. A full-match process is performed on the candidate packet by a second stage of the hardware accelerator to determine whether it satisfies the candidate rule by performing one or more of (i) context-aware pattern matching, (ii) context-aware string matching and (iii) regular expression matching based on contextual information, the matching tokens and the corresponding locations. |
| US10091246B2 |
Methods and systems for protecting a secured network
Methods and systems for protecting a secured network are presented. For example, one or more packet security gateways may be associated with a security policy management server. At each packet security gateway, a dynamic security policy may be received from the security policy management server, packets associated with a network protected by the packet security gateway may be received, and at least one of multiple packet transformation functions specified by the dynamic security policy may be performed on the packets. Performing the at least one of multiple packet transformation functions specified by the dynamic security policy on the packets may include performing at least one packet transformation function other than forwarding or dropping the packets. |
| US10091242B2 |
System and method for establishing a secondary communication channel to control an internet of things (IOT) device
A system and method are described for establishing a secondary communication channel between an IoT device and a client device. For example, one embodiment of a method comprises: establishing a primary secure communication channel between the IoT device and an IoT service using a primary set of keys; performing a secondary key exchange using the primary secure communication channel, the client device and the IoT device each being provided with a secondary set of keys following the secondary key exchange; detecting that the primary secure communication channel is inoperative; and responsively establishing a secondary secure wireless connection between the client device and the IoT device using the secondary set of keys, the client device being provided with access to data and functions made available by the IoT device over the secondary secure wireless connection. |
| US10091241B2 |
Method for purposes of making a “zero knowledge” connection between an electronic unit and a computer
A method of making a “zero knowledge” connection between a computer (2) and an electronic unit (5). At the start of the method, the configuration unit (1) is connected with the computer (2), and a web server is initiated in the configuration unit (1) via the trusted execution environment. A secure network connection is made to a server (3) by the configuration unit (1) and, via the network connection, the items of information required for connection with the electronic units, to which a connection can be made, are synchronized with the trusted execution environment. After synchronization occurs, an electronic unit (5) is selected by the web server via an input of the computer (2), to which electronic unit (5) a connection is made via the trusted execution environment using the stored, synchronized items of information, and via the web server prescribed menu-driven maintenance or configuration steps can be executed. |
| US10091240B2 |
Providing forward secrecy in a terminating TLS connection proxy
An infrastructure delivery platform provides a RSA proxy service as an enhancement to the TLS/SSL protocol to off-load, from an edge server to an external cryptographic server, the decryption of an encrypted pre-master secret. The technique provides forward secrecy in the event that the edge server is compromised, preferably through the use of a cryptographically strong hash function that is implemented separately at both the edge server and the cryptographic server. To provide the forward secrecy for this particular leg, the edge server selects an ephemeral value, and applies a cryptographic hash the value to compute a server random value, which is then transmitted back to the requesting client. That server random value is later re-generated at the cryptographic server to enable the cryptographic server to compute a master secret. The forward secrecy is enabled by ensuring that the ephemeral value does not travel on the wire. |
| US10091239B2 |
Auditing and policy control at SSH endpoints
SSH sessions and other protocol sessions (e.g., RDP) may be audited using an interceptor embedded within an SSH server or other protocol server. Operations performed over an SSH connection may be controlled, including controlling what files are transferred. |
| US10091234B2 |
Combination of remote triggered source and destination blackhole filtering
A method for remote triggered black hole filtering can include advertising a first modified next hop address for a destination address of network traffic, and advertising a second modified next hop address for a source address of network traffic. The first next hop address of the destination address might be overwritten with the first modified next hop address. Filtered traffic then can be forwarded to the first modified next hop address, wherein filtered traffic comprises only network traffic addressed to the destination address or from the source address. In some cases, the filtered traffic is transported and received via a sinkhole tunnel. A second next hop address of the source address can be overwritten to a second modified next hop address. The attack traffic, which can be filtered traffic that is both addressed to the destination address and from the source address, might be forwarded to a discard interface. |
| US10091233B2 |
Method and apparatus for controlling functionality using codes
Disclosed herein are a method and apparatus for controlling functionality of a mobile device. The operation of the element function of the mobile device is blocked by a blocking code, and the operation of the blocked element function is unblocked by an unblocking code. The blocking code is a code used to block the operation of the element function of the mobile device in an area in which a user is located, and the unblocking code is a code that is uniquely generated to correspond to the blocking code and that is used to unblock the operation of the blocked element function. By means of the blocking code and the unblocking code, the blocking and unblocking of the operation of an element function that is required in an area in which the user of the mobile device is located may be easily performed. |
| US10091232B2 |
Solution-centric reporting of security warnings
A new paradigm for security analysis is provided by transitioning code analysis reporting from the problem space (the warnings themselves), to a solution space (potential solutions to the identified problems). Thus, instead of reporting raw findings to the user, the automated system as described here outputs proposed solutions to eliminate the defects identified in the security analysis. A consequence of this approach is that the report generated by the analysis tool is much more consumable, and thus much more actionable. Preferably, the report provides the user with one or more candidate location(s) at which to apply a fix to an identified security problem. These locations preferably are identified by processing overlapping nodes to identify one or more solution groupings that represent an API for a sanitization fix. The report also includes one or more recommendations for the fix, and preferably the report is generated on a per-vulnerability type basis. |
| US10091230B1 |
Aggregating identity data from multiple sources for user controlled distribution to trusted risk engines
Identity data for a user is aggregated from multiple sources into a global profile, the contents of which is distributed under the control of the user to trusted risk engines. The collected identity data is related to the user's use of online services provided by multiple independent service providers. The collected identity data is aggregated into a private, global profile. The user must authorize the portion(s) of the aggregated identity data that is/are distributed, and one or more trusted risk engines to which the aggregated identity data may distributed. The global profile may be distributed to individual trusted risk engines, further based on requests received from individual ones of the trusted risk engines. |
| US10091225B2 |
Network monitoring method and network monitoring device
A device includes a processor configured to accumulate a plurality of logs in the memory, by repeating a capturing process and a logging process, the logging process including extracting a source identifier of a source computer, a destination identifier of a destination computer, and an attribute parameter which is set in an attribute item regarding an operation for the destination computer by the source computer, execute a detection process of detecting a target computer and another infected computer, the detection process including extracting a first destination identifier and a first attribute parameter, from a first log having an identifier of the infected computer in the source identifier, and extracting a second source identifier and a second destination identifier, from a second log having the first attribute parameter in the attribute parameter, and output the first destination identifier, the second source identifier, and the second destination identifier. |
| US10091224B2 |
Implicit crowdsourcing for untracked correction or verification of categorization information
Embodiments of the present disclosure are directed to updating categorization of online content. An analytics engine implemented at least partially in hardware can receive an engagement indicator across a network interface; identify a type of the engagement indicator, the type of the engagement indicator comprising one of a positive engagement indicator or a negative engagement indicator; and update the reputation data stored in memory based on the type of the engagement indicator. A safe harbor time window is described during with user activity with online content is not reported to system administrators. |
| US10091222B1 |
Detecting data exfiltration as the data exfiltration occurs or after the data exfiltration occurs
A device may identify exfiltration information to be used to detect data exfiltration. The exfiltration information may be associated with a file being tested to determine whether the file exfiltrates data. The exfiltration information may include a resource identifier that identifies a resource to be used to detect the data exfiltration. The device may determine that the resource, to be used to detect the data exfiltration, has been accessed. The device may identify, based on determining that the resource has been accessed, the file associated with the exfiltration information. The device may perform an action, associated with the file, to counteract the data exfiltration based on determining that the resource has been accessed and based on identifying the file. |
| US10091218B2 |
System and method to detect attacks on mobile wireless networks based on network controllability analysis
Described is a system for detecting attacks of misinformation on communication networks. Network controllability metrics on a graphical representation of a communication network are computed. Changes in the network controllability metrics are detected, and attack of misinformation on the communication network are detected based on the detected changes in the network controllability metrics. |
| US10091214B2 |
Malware warning
A malware warning system, including a client sending requests to and receiving replies from a server, and a server, including a first warning generator sending to the client a warning including a threat level of content located at a web site, in response to receiving from the client a URL for accessing content at the web site, a second warning generator sending to the client a warning including information about at least one of the nature of the threat of the content located at the web site and a location of the web site, in response to receiving from the client a request for more information about the nature of the threat, and a third warning generator, sending to the client a warning including an instruction to perform a swipe gesture to confirm a request to access the URL, in response to receiving that request from the client. |
| US10091211B1 |
Multiple data store authentication
Systems and methods for authenticating access to multiple data stores substantially in real-time are disclosed. The system may include a server coupled to a network, a client device in communication with the server via the network and a plurality of data stores. The server may authenticate access to the data stores and forward information from those stores to the client device. An exemplary authentication method may include receipt of a request for access to data. Information concerning access to that data is stored and associated with an identifier assigned to a client device. If the identifier is found to correspond to the stored information during a future request for access to the store, access to that store is granted. |
| US10091201B2 |
Mobile device identify factor for access control policies
A secure VPN connection is provided based on user identify and a hardware identifier. A client application may initiate the VPN connection. A client device user may provide identification information to the application, which then sends a VPN connection request to a remote VPN gateway. The VPN gateway may require an equipment identifier to establish the secure VPN gateway. If the hardware ID is registered, the secure VPN connection is established. If the hardware ID is not registered with the VPN gateway, the connection may be denied. In some instances, a connection may be established with an unregistered equipment ID based on settings at the VPN gateway. |
| US10091197B2 |
Configuring, controlling and monitoring computers using mobile devices
A portable computing device captures imagery from a screen of a second computer, decodes information steganographically-encoded in the screen display, and uses the decoded information to establish a secure session with the second computer. Such technology enables a help-desk staffer to interact with a client's desktop computer, without touching the keyboard of the desktop computer, and without interrupting the client's work. A great many other features and arrangements are also detailed. |
| US10091196B2 |
Method and apparatus for authenticating user by using information processing device
A method and apparatus for authenticating a user is disclosed that includes measuring biometric information of the user to create biometric measurement information, determining whether a private key included in a user authentication request signal matches a private key issued in advance to the user, comparing pre-set biometric authentication information for the user with the biometric measurement information, calculating a matching ratio when a match is detected, authenticating the user having provided the biometric information as an authorized user based on a result of comparison of the calculated matching ratio with a pre-determined biometric authentication threshold value, and providing an updated private key to the information processing device based on a result of comparison of the calculated matching ratio with a pre-determined updated threshold value. |
| US10091195B2 |
System and method for bootstrapping a user binding
A system, apparatus, method, and machine readable medium are described for bootstrapping an authenticator. For example, one embodiment of a method comprising: confirming an identity of a user by a first relying party using a first identity verification technique responsive to the user acquiring a device having an authenticator; generating or collecting initial user verification reference data upon verifying the identity of the user through the first identity verification technique; securely providing the initial user verification reference data or data derived from the initial user verification reference data to the authenticator; the authenticator implementing a second identity verification technique by comparing the initial user verification reference data or data derived from the initial user verification reference data to data collected from the user or data collected from a device provided to the user; and providing proof of a successful verification of the identity of the user to a second relying party during a registration request of the authenticator with the second relying party. |
| US10091194B2 |
Preventing unauthorized access to secured information systems using multi-device authentication techniques
A computing platform may receive, from a client portal server, a request to authenticate a first user to a first user account. The computing platform may generate a first one-time passcode for a first computing device associated with the first user account and may send, to the first computing device, the first one-time passcode. The computing platform also may generate a second one-time passcode for a second computing device associated with the first user account and may send, to the second computing device, the second one-time passcode. Thereafter, the computing platform may receive first one-time passcode input and second one-time passcode input, which the computing platform may validate. Based on the validating, the computing platform may generate a validation message directing the client portal server to provide the first user with access to the first user account, which the computing platform may send to the client portal server. |
| US10091191B2 |
Distributed authorization
Systems and methods for distributed authorization are described. In some embodiments, an Information Handling System (IHS) may include a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive a first authentication material from a first device; identify, based upon a policy stored in the IHS, a second device; and distribute a second authentication material to the second device. |
| US10091190B2 |
Server-assisted authentication
Authentication of a device through a constructed authentication token. Components of an authentication key are distributed across at least a device and a server, diminishing a likelihood that an individual account is compromised by an attack. |
| US10091187B2 |
Bypassing certificate pinning
A client application performs certificate pinning as a means of authenticating the identity of a server. A proxy is interposed in the communications path of the client and the hosting server and provides a proxy security certificate to the client. In response to the client extracting a proxy authentication component from the proxy security certificate, operation of the client is paused and a hosting server authentication component is extracted from a hosting server security certificate. The client operation is resumed, providing the extracted hosting server authentication component to the client, in substitution for the proxy authentication component. Based on receiving the extracted hosting server authentication component, the client authenticates the proxy to receive communications directed to the hosting server. |
| US10091178B2 |
Method for supplying protected multimedia content to a terminal
A Method for supplying protected multimedia content during which a terminal a) acquires a service date from a date server and b) evaluates a temporal criterion of a licence with respect to the last acquired service date. A headend associates with each segment of the multimedia content, its transmission date, and transmits it in a stream together with the segment. The terminal extracts from the stream the date of transmission of the segment, then it compares the extracted transmission date to the last acquired service date. And, only if the extracted transmission date is later than the last acquired service date, acquires it as service date, and uses it as last acquired service date on an execution of the step b) between two successive executions of the step a). |
| US10091177B1 |
Controlling access to a computerized resource of a mobile device based on whether the mobile device is within a vehicle that is currently moving
A technique controls access to a computerized resource of a mobile device (e.g., a smart phone, a tablet, etc.). The technique involves, in response to successfully authenticating a user, unlocking access to the computerized resource of the mobile device and starting a timer which is configured to lock access to the computerized resource of the mobile device upon timer expiration. The technique further involves, after the timer is started and while access to the computerized resource of the mobile device is unlocked, receiving a sensor signal from sensor circuitry. The sensor signal indicates whether the mobile device is in a vehicle that is currently moving. The technique further involves, in response to the sensor signal indicating that the mobile device is in a vehicle that is currently moving, restarting the timer which is configured to lock access to the computerized resource of the mobile device upon timer expiration. |
| US10091164B2 |
System and method for mapping physical locations of motors in a network
A motor network mapping device is provided. The motor network mapping device includes a processor coupled to a memory device. The motor network mapping device is configured to determine physical distances between a plurality of motors in a network using properties of electronic test signals transmitted through a power line coupled to the plurality of motors. The motor network mapping device is additionally configured to generate a map of physical locations of the motors using the determined physical distances between the plurality of motors and store the map in the memory device. |
| US10091163B2 |
Server device, control method for the same and computer-readable recording medium
A program which is capable of offering a reward to a user who has registered a simple access means to a predetermined screen is disclosed. The program causes a computer to function as reception means for receiving an access request from a terminal device used by a user; determination means for determining, based on a character string contained in a URL of an access destination of the received access request, whether or not a simple access means to the URL is registered in the terminal device; and offering means for offering a reward to the user who uses the terminal device that performs the access request when the simple access means is determined to be registered. |
| US10091160B2 |
Wireless access gateway
A wireless network including a wireless access gateway (WAG) and methods are provided for routing traffic between non-cellular and cellular networks. The WAG receives a first IP address for the UE in the cellular domain and the WAG allocates a second IP address for the UE in the non-cellular domain from a dedicated pool of IP addresses for that non-cellular domain. The WAG also creates a routing rule between the first and second IP addresses. |
| US10091159B2 |
Assigning network addresses to possible network ports to fullest extent to which addresses can be assigned to ports
The possible network ports of a computing device are determined, regardless of whether they are currently usable. A network address is assigned to each possible network port. The network ports can include physical network ports and virtual network ports. Physical network ports can include physical network ports that are physically present, currently activated, and currently usable within the computing device; physical network ports that are physically present, not currently activated, and not currently usable within the computing device; and physical network ports that are not physically present and not currently usable within the computing device. Virtual network ports can include virtual network ports that have been instantiated and that are currently usable; and virtual network ports that have not been instantiated and that are not currently usable. |
| US10091158B2 |
Systems and methods for resolving data inconsistencies between domain name systems
In one aspect, a computer-implemented method for managing Domain Name System (DNS) information is provided. The method uses a computing device having a processor and a memory. The method includes receiving, in the memory, source DNS data from a plurality of DNS systems including at least first source data from a first source system and second source data from a second source system. The method also includes identifying, by the processor, an inconsistency between the first source data and the second source data. The inconsistency includes an inconsistency type. The method further includes determining a solution to the inconsistency by applying one or more rules from a plurality of inconsistency rules based at least in part on the inconsistency type associated with the inconsistency. The method also includes resolving the inconsistency using the determined solution including generating resultant DNS data. |
| US10091156B2 |
Transmission device that determines a received mail is a reply to a previously sent mail and generates a mail having a BCC recipient
A communication device is provided which includes a transmission unit, a BCC memory unit, a reception unit, a determination module, an accepting module and a mail generation module. The BCC memory unit stores the BCC destination of the mail sent in the past while being associated with the mail. The determination module determines whether or not a mail that the reception unit receives is a reply mail to the mail including the BCC destination that the transmission unit sent in the past. The mail generation module generates a mail addressed to sending destinations to which the BCC destination stored in the BCC destination memory unit while being associated with a mail of a reply source is added in addition to a sending destination that the accepting module accepts for the mail determined to be a reply mail to the mail including the BCC destination and sent in the past. |
| US10091151B2 |
Preempting spam filters based on transactions
Technical solutions are described for a seller to bypass a spam filter. An example method includes sending, by a message preempting apparatus, for receipt by a server corresponding to the seller, a transaction identifier in response to a transaction between a user and the seller. The method also includes sending, by the message preempting apparatus, for receipt by a messaging server, the transaction identifier, where the messaging server, in response, bypasses a spam filter for a message that is associated with the transaction identifier. |
| US10091149B2 |
Spoiler alert scheme
Technologies are generally described for a spoiler alert scheme. In some examples, a spoiler alert system may include an event determination unit configured to determine an event of interest to a user for which a spoiler alert is to be provided, a spoiler identification unit configured to identify one or more posts in an online forum that include spoiler information regarding the determined event of interest, and a spoiler control unit configured to hide the one or more identified posts from the online forum, as displayed to the user. |
| US10091147B2 |
Providing additional information related to a vague term in a message
Methods and apparatus related to providing additional information related to a vague term in a message. For example, in some implementations, one or more messages sent by a sender and received by one or more recipients may be identified, a vague term in the message may be identified, a user-restricted database may be identified that is associated with the sender or a recipient, and additional information related to the vague term may be determined from the user-restricted database. A vague term is a term which may have multiple meanings and that can be clarified with additional information. In some implementations, user-restricted databases may include additional information that is associated with the user that may be utilized to replace the vague term with a clarified term. In some implementations, a user-restricted database may be utilized to identify additional information in another database that may be utilized to clarify the vague term. |
| US10091146B2 |
System and method for monitoring and copying multimedia messages to storage locations in compliance with a policy
The present inventions relate systems and methods for monitoring and managing electronic messages in one or more computer networks. More particularly, the systems and methods of the present invention provide a substantially global or unified approach to messaging management within one or more computer networks that allows network administrators or other authorized users to define and identify electronic messages of interest within the network and store selected messages such that they can be retrieved and examined in connection with an audit or other inquiry. |
| US10091145B2 |
Information processing apparatus and cellular phone terminal
Disclosed is an information processing apparatus including a display unit displaying information on a display screen, an operation unit including a text input key, and a control unit. The control unit displays text in response to input from the operation unit in a state of displaying an initial screen on the display screen, shows an application using text to a user for selection, starts up the application in accordance with the user's selection, and executes the application, using the text inputted from the operation unit. |
| US10091136B2 |
On-chip network device capable of networking in dual switching network modes and operation method thereof
Provided is an on-chip network device which basically operates in a packet switching network mode, establishes an exclusive communication path according to a request for a specific path, performs networking in a circuit switching network mode, and switches a network mode back to the packet switching network mode, when communication in the circuit switching network mode is terminated. |
| US10091135B2 |
System and method for multi-tenancy enablement of enterprise java applications using resource proxies and application tenancy context
In accordance with an embodiment, described herein is a system and method for multi-tenancy enablement of enterprise Java™ applications using resource proxies and application tenancy context. In according with an embodiment, the system and method can provide a plurality of deployable resources which can be used within the application server environment, and one or more application deployments, wherein each application deployment includes at least one of tenant-specific code and shared-tenant code. The system and method can further determine an application tenancy context of a thread, and point to one or more resource proxies, each of the one or more resource proxies being configurable to communicate with a tenant specific resource. Each of the one or more resource proxies can use the application tenancy context of a thread to communicate with a tenant specific resource. |
| US10091128B2 |
Dynamic history multistream long range compression
Dynamic history multistream long range compression (DHC) techniques are described for efficiently compressing multiple, prioritized data streams received over a channel. A history buffer is associated with each received stream and a DHC compressor dynamically allocates fixed sized history sections to and from each history buffer. In implementations, the DHC compressor makes stream history size adjustments prior to compressing a block of data and sends information identifying the change in history size to a DHC decompressor. The DHC decompressor sends signaling information to the DHC compressor that is used to ensure that the DHC decompressor can operate with a fixed amount of total history memory. |
| US10091127B2 |
Enrolling a mobile device with an enterprise mobile device management environment
Embodiments of the present application relate to a method, apparatus, and system for enrolling a mobile device with an enterprise network. The method includes receiving, from a mobile device, a request to access an enrollment address. In response to receiving the request to access the enrollment address, determining whether the mobile device is pre-enrolled with the enterprise network, and in the event that the mobile device from which the request to access the enrollment address is received corresponds to the mobile device that is pre-enrolled with the enterprise network, pushing user-specific settings to the mobile device. |
| US10091126B2 |
Cloud system, control method thereof, management server and control method thereof
A cloud system includes a first application server to perform a user-requested task, a second application server to provide an additional resource to the first application server, a first cache server to provide a caching service to the first application server, a second cache server to provide a caching service to the second application server, and a management server to copy data stored in the first cache server into the second cache server when the second application server provides the additional resource to the first application server. |
| US10091124B2 |
System for early system resource constraint detection and recovery
A system for optimizing network traffic is described. The system includes a quality of service (QoS) engine configured to acquire information regarding a plurality of data packets comprising a plurality of data packet flows operating over a plurality of links. The QoS engine can be further configured to determine a flow priority to the plurality of data packets flows, and to determine TCP characteristics for the plurality of data packet flows. The system further includes a TCP controller configured to acquire the flow priority to the plurality of data packets from the QoS engine. The TCP controller can be configured to obtain queue information associated with the plurality of data packets, and adjust a receive window size based on the flow priority and the queue information. |
| US10091116B2 |
Service chain construction method and server apparatus
A service chain construction method includes partitioning a service chain in which a virtual distribution-function-group is arranged upstream of a most upstream virtual communication-function-group among virtual communication-function-groups arranged at stages, into sections, based on arrangement positions of the virtual distribution-function-group and a virtual communication-function-group of a terminating type among the virtual communication-function-groups, determining, for each of the sections, a communication route between a most upstream virtual distribution-function-group or the most upstream virtual communication-function-group in a section of the sections and a most downstream virtual communication-function-group or a most downstream virtual distribution-function-group in the section, based on a traffic ratio in the most upstream virtual distribution-function-group, the most downstream virtual distribution-function-group, the most upstream virtual communication-function-group, or the most downstream virtual communication-function-group in the section, and setting the communication route to the virtual distribution-function-group and the virtual communication-function-groups arranged in the service chain, by a processor. |
| US10091115B2 |
Handling voice and non-voice data under uplink limited conditions
This disclosure relates to techniques for handling voice and data under uplink limited conditions in a wireless communication system. A wireless device and a base station may establish a wireless communication link. Transmission time interval bundling (TTI-B) may be enabled for uplink communications between the wireless device and the base station. It may be determined that the wireless device is experiencing uplink limited conditions. One or more rules prioritizing a first type of data over a second type of data for uplink communications may be enabled based on TTI-B being enabled and the wireless device experiencing uplink limited conditions. |
| US10091112B1 |
Highly-scalable virtual IP addresses in a load balancing switch
In an example, there is disclosed a load balancing network apparatus, including a first network interface operable to communicatively couple to a first network; a plurality of second network interfaces operable to communicatively couple to a second network; and one or more logic elements providing a load balancing engine operable for: receiving an address mask; receiving an incoming network packet; masking a destination virtual network address with the address mask to match a plurality of virtual ip addresses; and load balancing the incoming network packet to the plurality of service nodes. There is also disclosed one or more computer-readable mediums including instructions for carrying out the operations, and a method of providing load balancing including carrying out the operations. |
| US10091111B2 |
Methods and systems for an end-to-end solution to deliver content in a network
A network infrastructure provisioned according to design information received via a web portal contains one or more nodes and facilitates deployment of services and associated data across physical and virtualized resources for a content delivery path between a content source and a content consumer according to technical and business needs of a content provider. Provisioning is accomplished by storing the design information in one or more repositories, the repositories containing data, packaging information and metadata of the one or more nodes, and one or more map files specifying the respective addresses of the one or more nodes. The network infrastructure is instantiated based on the design information stored in the one or more repositories and the one or more map files by configuring the nodes according to the design information and communicatively coupling the nodes with one another; and registering the instantiated nodes with a global software load balancer. |
| US10091109B2 |
Systems and methods for centrally-assisted distributed hash table
Methods and systems are described managing module for locating a target storage device among a plurality of storage devices connected via a network. A computer implemented method includes sending registration information to a central directory, wherein the registration information includes at least an address of one of the plurality of storage devices, and the central directory stores the registration information in a registry. The method also includes sending a request to the central directory for an address for another one of the plurality of storage devices, receiving the address from the central directory if the address is in the registry, and conducting a successive lookup of a closest known address until the address is located if the address is not in the registry. |
| US10091102B2 |
Tunnel sub-interface using IP header field
In one implementation, sub-interfaces are defined in Layer three (L3) tunnels, such as generic routing encapsulization (GRE) or Internet protocol security (IPsec) tunnels. Sub-interfaces inside a L3 tunnel may be preferred to using several L3 tunnels. The flow label of the tunnel header is used to define sub-interfaces of a tunnel interface. The flow label is populated with a routing instance identifier to index the sub-interfaces. |
| US10091099B2 |
Session continuity in the presence of network address translation
Embodiments of the present invention provide for continuity of “stateful” routing sessions in the presence of source network address translation (NAT). Specifically, a stateful routing session may be moved from one routing path to another routing path, e.g., due to a routing change in the communication network, where the routing paths have different source NAT status. For example, the stateful routing session may be moved from a path having no source NAT to a path having source NAT, from a path having source NAT to a path having no source NAT, or from paths having different source network address translations. When a stateful routing session is moved from an existing routing path to a new routing path, the routers detect the routing change based on the change in source NAT status using a special link monitoring protocol. Upon detecting the change in source NAT status, session metadata is included in at least the first packet forwarded following detection of the change in source NAT status so that the stateful routing session can continue without interruption. |
| US10091098B1 |
Distributed affinity tracking for network connections
An embodiment of the invention may include a method, computer program product, and system for data transfer management. The embodiment may include receiving a data packet, by a first server, from a load balancer. The received data packet is part of a data flow. The embodiment may include determining, by the first server, whether the received data packet is part of an existing data flow connection served by the first server. Based on determining that the received data packet is not part of an existing data flow served by the first server, the embodiment may include determining, by the first server, whether the received data packet is part of a new data flow connection. Based on determining that the received data packet is not part of a new data flow connection, the embodiment may include notifying, by the first server, the load balancer. |
| US10091097B2 |
Transmission path optimization method and software-defined networking controller using the method
A transmission path optimization method for a Multipath Transmission Control Protocol (MPTCP) applied in a software-defined networking controller located in a network topology. The method is based on detected MPTCP information, the SDN controller retrieves and selects one or more optimal routing paths for allocating to sub-flows of the MPTCP connection. The one or more routing paths are obtained from a first disjoint-path-set with highest compatibility. |
| US10091095B2 |
System, node, failure determining system, failure determining method, and computer product
A system has a group of nodes that perform multi-hop communication therebetween and a communications apparatus that communicates with a node included in the group of nodes. The node adds to data transmitted by the node, a hop count updated each time the data is transferred by the multi-hop communication and a reference hop count for the data to be transferred from the node to the communications apparatus, and transmits the data. The communications apparatus, when receiving the data, compares the reference hop count and the hop count added to the data, and based on a result of comparison, determines whether failure has occurred at a given node in the group of nodes. |
| US10091094B2 |
Method for distance-vector routing using adaptive publish-subscribe mechanisms
A distance-vector based routing protocol that integrates with adaptive publish-subscribe mechanisms by establishing routes to well-known controllers using distance-vector signaling. |
| US10091093B2 |
Multi-controller control traffic balancing in software defined networks
A method includes determining a number and placement of multiple controllers in a software defined network (SDN) such that each controller controls a different set of software controlled switches in the SDN and finding optimal forwarding paths for control traffic between the switches and controllers to minimize delay of control traffic over the software defined network. |
| US10091090B2 |
Packet forwarding in software defined networking
Based on an example, two forwarding pipelines are configured in a software defined networking (SDN) switch. After receiving, from an SDN controller, a flow entry adding instruction comprising a flow entry to be added and a table identifier (ID) indicating a flow table that the flow entry is to be added to, an SDN switch adds the flow entry into the flow table corresponding to the table ID, wherein the flow table is in the first forwarding pipeline or the second forwarding pipeline. If the flow table and its next flow table are in different forwarding pipelines, the SDN switch adds an action of forwarding to the internal interface to the flow entry. |
| US10091089B2 |
Storing and expiring non-TCP traffic
Present disclosure provides techniques for dynamically determining how to store and expire non-TCP traffic in a network environment. In some examples, aspects of the present disclosure may implement a state machine operated by the server for managing non-TCP traffic. Critically, in accordance with aspects of the present disclosure, non-TCP traffic may be combined with the use of multiple memory partitions and an expiry algorithm that supports dynamic scaling of non-TCP traffic while achieving faster connection speed, higher system performance, and lower time complexity. |
| US10091087B2 |
Methods and systems for load balancing based on data shard leader
Disclosed are systems, methods, and computer-readable storage media for load balance resources amongst computing nodes. Various embodiments of the present technology can be used to, prior to assigning a first data shard included in a first cluster of data shards as a leader of the first cluster of data shards, determine whether a first computing node storing the first data shard also stores a second data shard designated as a leader of a second cluster of data shards, yielding a determination, and when the determination indicates that the first computing node stores the second data shard designated as the leader of the second cluster of data shards, designate the first data shard as non-electable to be the leader of the first cluster of data shards and electing an alternate data shard included in the first cluster of data shards as the leader of the first cluster of data shards. |
| US10091082B2 |
Methods and apparatus to capture data plane information
Methods and apparatus to capture data plane information are disclosed. An example method includes capturing, via an observation point deployed between core routers of a network, data plane information traversing between the core routers of the network; generating an observational data plane using the data plane information captured via the observation point; and conveying the observational data plane to a data plane process implemented separately from a control plane process. |
| US10091081B2 |
Method for devices in a network to participate in an end-to-end measurement of latency
A method of determining the latency of path segments in a communication network that uses multi-bit data packets comprises generating a test packet for use in determining the latency of path segments in the network; transmitting the test packet from a first device coupled to the network; storing in the test packet the time when a preselected bit in the test packet is transmitted from the first device; when the test packet is received by a second device coupled to the network, storing in the second device at least one of (a) the time when a preselected bit in the test packet is received by the second device and (b) the difference between (i) the time when the preselected bit in the test packet is transmitted from the first device and (ii) the time when the test packet is received by the second device. |
| US10091078B2 |
Method and computing device for shaping traffic across a wide area network
A method for shaping traffic across a wide area network is disclosed. The method involves advertising a data rate limit across a wide area network (WAN) from a first node, measuring the rate of data received at a WAN interface of the first node, and, if the measured rate of data received at the WAN interface of the first node exceeds a maximum threshold, advertising a reduced data rate limit across the WAN, and, if the measured rate of data received at the WAN interface of the first node is below a minimum threshold, advertising an increased data rate limit across the WAN. |
| US10091074B2 |
Hardware acceleration architecture for signature matching applications for deep packet inspection
A signature matching hardware accelerator system comprising one or more hardware accelerator circuits, wherein each of the hardware accelerator circuit utilizes a compressed deterministic finite automata (DFA) comprising a state table representing a database of digital signatures defined by a plurality of states and a plurality of characters, wherein the plurality of states are divided into groups, each group comprising a leader state having a plurality of leader state transitions and one or more member states, each having a plurality of member state transitions is disclosed. The hardware accelerator circuit comprises a memory circuit configured to store the leader state transitions within each group of the compressed DFA, only the member state transitions that are different from the leader state transitions for a respective character within each group of the compressed DFA and a plurality of member transition bitmasks associated respectively with the plurality of member state transitions. |
| US10091073B2 |
Large-scale passive network monitoring using multiple tiers of ordinary network switches
Passive monitoring of a large-scale network using multiple tiers of ordinary network switches, as opposed to purpose-built network monitoring hardware, is accomplished by initially providing network communications to an initial tier of monitoring switches, either from existing switches that copy frames and provide them to the monitoring switches, or from network taps to which the monitoring switches are connected. The initial tier of monitoring switches comprises flow tables that initially simply drop all frames provided to those switches and, subsequently, when specific network issues arise, they are modified to include a specification particular frame criteria whose frames are either forwarded to subsequent tiers of monitoring switches, or statistics regarding those frames are collected. Subsequent tiers of monitoring switches receive frames from the initial tier and direct them to one or more appropriate analysis computing devices. Ordinary network switches are selected based on their ability to provide low latency forwarding. |
| US10091071B2 |
Assigning QoS to cable service flows
A novel method of handling network traffic for cable service flows in a distributed cable system is presented. Such a cable systems use remote distribution nodes in the fields to handle RF communications with cable modems in a distributed fashion. A packet engine is configured to assign a logical interface to each cable service flow in the cable system. Each logical interface in the packet engine is uniquely identifiable by a compound identifier that includes the identifier of the corresponding service flow and the identifier of the remote distribution node. Each service flow is assigned a class of service (CoS) at the packet engine and guarantee a certain level of quality of service (QoS). In some embodiments, each cable service flow is assigned a CoS priority number. For each possible CoS priority number, the packet engine is configured to provide certain resources at certain quality level, i.e., certain level of QoS. Each remote distribution node tags each packet of a cable service flow with its assigned CoS priority number and forwards the tagged packet toward the packet engine. |
| US10091070B2 |
System and method of using a machine learning algorithm to meet SLA requirements
A method includes collecting, at a monitoring and recovery node, a virtual network function key performance index data through multiple channels from a corresponding containerized virtual network function. The method includes maintaining, at the monitoring and recovery node, state information of the corresponding containerized virtual network function and running, at the monitoring and recovery node, a machine learning algorithm that, once trained, learns and predicts whether the corresponding containerized virtual network function requires one of a scaling, a healing or a context switching to sister virtual network function to yield a determination and meet the service level agreement of a network service. |
| US10091067B2 |
Discovering and publishing device changes in a cloud environment
A method for discovering and publishing device changes in a cloud computing environment. The method includes scanning, by a processor, a computing environment to detect a multiple computing elements. The processor generates an index data structure including allocation of nodes that each represent a computing element of the multiple computing elements. The nodes each include a computed hash value that includes computing element status of the node and status of associated child nodes. The index data structure is monitored for discovering a change in status of any of the nodes. In response to determining a change in status of any of the nodes, the index data structure is re-generated and the hash value for each node associated with the change in status is re-computed. An updated status of one or more of the nodes is provided based on the change in status. |
| US10091065B1 |
Zero configuration networking on a subnetted network
Methods and apparatus are described for implementing service discovery protocols on subnetted zero configuration networks. A process for managing service advertisement across a plurality of subnets may comprise: collecting service advertisements on a local network level by designated network devices; sending listings of services from each of the designated devices to a master network device; sending a table of services for the plurality of subnets from the master device to all of the designated devices on the plurality of subnets; creating by each of the designated network devices for the corresponding subnet a service discovery proxy table listing the service advertisements on the subnets of the plurality of subnets beyond the subnet corresponding to the designated device; and periodically transmitting by each of the designated devices on the corresponding subnets service advertisements for the services of the corresponding service discovery proxy table. |
| US10091063B2 |
Technologies for directed power and performance management
Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node. By remotely monitoring and managing system operation and performance over time, future system performance requirements may be anticipated, allowing system parameters to be adjusted proactively in a more coordinated way. The controller node may monitor, control and predict traffic flows in the system and provide performance modification instructions to any of the computer nodes and a network switch to better optimize performance. The target systems collaborate with the controller node by respectively monitoring internal resources, such as resource availability and performance requirements to provide necessary resources for optimizing operating parameters of the system. The controller node may collect local system information for one or all of the computer nodes to dynamically steer traffic to a specific set of computers for processing to meet desired performance and power requirements. |
| US10091062B2 |
Multiple mobility domains with VLAN translation in a multi-tenant network environment
An example method for facilitating multiple mobility domains with VLAN translation in a multi-tenant network environment is provided and includes detecting attachment of a first virtual machine on a first port and a second virtual machine on a second port of a network element, the first port and the second port being configured with a first mobility domain and a second mobility domain, respectively, and the first and second virtual machines being configured on a same original VLAN, determining whether the original VLAN falls within a pre-configured VLAN range, translating the original VLAN to a first VLAN on the first port corresponding to the first mobility domain and to a second VLAN on the second port corresponding to the second mobility domain, and segregating traffic on the original VLAN into the first VLAN and the second VLAN according to the respective mobility domains for per-port VLAN significance. |
| US10091060B2 |
Robust service deployment
A method, system and program product for deploying a service on a network comprising a plurality of network resources, the method comprising providing an actual network model comprising network resources and the configurations of the network resources; providing a computer-implemented network configuration management system controlling the actual network resource configurations in the actual model; providing a service description comprising network resource configuration information for implementing the service on specific network resources; selecting a set of available network resources for deploying the service in the network based on the service description; reserving available network resources for deploying the service in an off-line version of the actual network model, the off-line version including updated network resource configurations to reflect the changes to the configurations of the actual network resources triggered by the deployment of the service; and deploying the service by updating the actual network model using the off-line version. |
| US10091059B2 |
Handling connections between network devices that support multiple port communication modes
Techniques for handling connections between network devices that support multiple port communication modes are provided. In one embodiment, a first network device can detect a communication problem between a local port of the first network device and a peer port of a second network device, where the local port supports a plurality of communication modes including a default mode and one or more non-default modes. The first network device can further set the local port to operate in the default mode, receive on the local port a user-configured mode of the peer port from the second network device, and determine a communication mode for the local port from the plurality of communication modes, where the determining is based on the user-configured mode of the peer port and a user-configured mode of the local port. The first network device can then set the local port to operate in the determined communication mode. |
| US10091058B2 |
Method and apparatus for model-driven, affinity-based, network functions
An approach to affinity-based network configuration is disclosed. In one approach, an apparatus for configuring a network based on affinity is described. The apparatus includes a set of business rules describing the order of importance of a plurality applications, an affinity analysis module that receives the set of business rules and a plurality of application requests and detects affinities between the application requests and an infrastructure of the network based on the set of business rules, an affinity computation module coupled to the affinity analysis module that determines a new network configuration based on the detected affinities, and a network management module that configures the network based on the new network configuration. |
| US10091052B1 |
Assessment of network fault origin
A network endpoint may issue network traces directed to another endpoint. Completed traces may provide information pertaining to possible paths between the endpoints. In response to a failed trace, a component along a possible path between the endpoints may be associated with a value that indicates an assessed contribution of the component to the network failure. The value may be used to initialize a parameter to a statistical calculation that iteratively refines the estimate to form a probability estimate regarding a likelihood that the component is contributing to a network fault. |
| US10091049B2 |
Scripting for implementing policy-based traffic steering and management
Methods, systems, and devices are described for managing network communications. A traffic manager module may receive a script over a management plane of a packet core, interpret the script to identify a traffic management policy; and dynamically modify at least one aspect of a proxy connection over a bearer plane of the packet core at the traffic manager module based on the identified traffic management policy. |
| US10091042B2 |
Apparatus and method for sending and receiving broadcast signals
A broadcast signal transmitter is disclosed. A broadcast signal transmitter according to an embodiment of the present invention comprises an input formatting module configured to perform baseband formatting and to output at least one PLP (Physical Layer Pipe) data; a BICM (Bit Interleaved Coded Modulation) module configured to perform an error correction process on the PLP data; a framing and interleaving module configured to interleave the PLP data and to generate a signal frame; and a waveform generating module configured to generate a broadcast signal by inserting a preamble into the signal frame and performing OFDM modulation. |
| US10091036B1 |
Direct digital sequence detector and equalizer based on analog-to-sequence conversion
Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages. |
| US10091032B2 |
Equalization circuit, semiconductor apparatus and semiconductor system using the same
An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal. |
| US10091030B2 |
Blind channel equaliser
A blind channel equalizer device for a radiofrequency receiver suitable for modulating the constant envelope signal of the transmission includes: an adjustable linear digital filter, defined at a point in time by the coefficients) thereof, able to filter an input signal in order to produce an output signal; an estimator able to estimate a power of the input signal; an adapter able to adapt the filter by calculating the coefficients of the filter at a point in time by subtracting, from the filter coefficients at a preceding point in time, the gradient of a cost function assigned with a correction coefficient. The cost function includes a first distance criterion between the square of the output signal and the power, wherein the correction coefficient is a product including a constant convergence coefficient and a scaling coefficient inversely proportional to the square of the power. Also disclosed is a related Radiofrequency receiver. |
| US10091028B2 |
Hierarchical controller clusters for interconnecting two or more logical datapath sets
Some embodiments provide a novel network control system for managing a set of switching elements in a network. The network control system includes a first set of network controllers for managing a first set of switching elements that enable communication between a first set of machines. The network control system includes a second set of network controllers for managing a second set of switching elements that enable communication between a second set of machines. The second set of switching elements is separate from the first set of switching elements and the second set of machines is separate from the first set of machines. The network control system includes a third set of network controllers for managing the first and second sets of network controllers in order to enable communication between machines in the first set of machines and machines in the second set of machines. |
| US10091020B2 |
Electronic device and gateway for network service, and operation method therefor
A method of operating an electronic device is provided. The method includes displaying a space drawing visualizing an indoor space and at least one icon related to an execution instruction to be transmitted to a network device, recognizing that an icon selected among the displayed at least one icon is overlapped on an image of the network device included in the space drawing, and transmitting the execution instruction corresponding to the selected icon, to the network device. |
| US10091017B2 |
Personalized home automation control based on individualized profiling
Disclosed are methods, systems, and non-transitory, machine-readable media that facilitate personalized home automation control based at least in part on individualized protocol. First sensor data may be received, and may be indicative of an identified individual that is sensed by a set of sensors. A particularized pattern of activity of individual may be determined. Second sensor data may be indicative of an unidentified individual. Identification rules specified by a stored protocol record may include criteria for identifying sensed individuals. The second sensor data and/or identification information from another data source may be analyzed to identify the unidentified individual. A home automation rule may be determined based on the particularized pattern, which rule may include an anticipation of an operational setting of a home automation device. The home automation device may be instructed based on the determined home automation rule. |
| US10091015B2 |
3D mapping of internet of things devices
A method for mapping and controlling network-enabled appliances with a control device may comprise collecting spatial information in three dimensions as at least one sensor of the control device is moved within an environment, receiving registration signals from network-enabled appliances in the environment, and associating each network-enabled appliance with a respective 3D position in the environment based on the spatial information. The method may include generating a digital map of the environment from the spatial information and placing a representation of each network-enabled appliance on the digital map based on the respective 3D position. The method may also include generating a spatially aware rule set that applies to one or more rooms within the environment. The method may also include detecting a trigger event, and in response to the trigger event, commanding the network-enabled appliances according to the spatially aware rule set. |
| US10091008B2 |
Method and apparatus for performing credit reservations for online charging in a communication network
A method and apparatus advantageously consider historic usage data in determining the credit reservations made against subscriber accounts during online charging operations. In particular, with respect to a communication between first and second parties that is subject to online charging, the method and apparatus use historic usage data associated with at least one of the first and second parties, to determine credit reservations against an involved subscriber account. This approach makes the credit reservation better reflect the usage pattern or history of one or both parties. In some embodiments, the historic usage data is generalized with respect to the called or contacted party. In other embodiments, the historic usage data is generalized with respect to the calling or contacting party. In still other embodiments, the historic usage data is particularized to reflect a historic usage pattern of communication between the first and second parties. |
| US10091006B2 |
Certificate pinning using a directory service
A user device obtains a set of one or more public key certificates for a server received from a directory service, and a current public key certificate of the server received from the server. The user device compares the current public key certificate received from the server with the set of public key certificates received from the directory service. If the current public key certificate of the server matches one of the public key certificates in the set of public key certificates for the server, the authenticity of the server is confirmed, and communications are permitted between the user device and the server. Communications between the user device and the server may be prevented unless the current public key certificate from the server matches a public key certificate in the set of public key certificates received from the directory service. |
| US10091000B2 |
Techniques for distributing secret shares
Various embodiments are generally directed to an apparatus, method and other techniques generating one or more polynomial elements for a polynomial function using a node value of a pseudo random number generator tree as a seed value, the polynomial function comprising a secret value and the polynomial elements, and the pseudo random number generator tree at least partially matching at least one other pseudo random number generator tree on another device, generating a plurality of share values based on the one or more polynomial elements and the polynomial function and distributing a share value of the plurality of share values to a device. |
| US10090994B2 |
Automatic detection of change in PLL locking trend
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal. |
| US10090993B2 |
Packaged circuit
A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock. |
| US10090989B2 |
Software defined radio front end
The present application describes a computer-implemented method for configuring a front end including receiving a first signal and a second signal containing interference; characterizing the receive channel using the first tone; processing the compensated first signal using an infinite impulse response filter based on the characterized receive channel to generate an interference cancelling signal; and coupling the interference cancelling signal to the second signal to generate an interference cancelled receive signal. The present application also describes a computer-implemented apparatus for a front end. |
| US10090988B2 |
User terminal, base station and radio communication method
The present invention is designed so that uplink transmission is carried out adequately even when CA to apply different duplex modes between multiple cells is executed. A user terminal communicates with an FDD cell and a TDD cell by employing carrier aggregation, and has a receiving section that receives DL signals transmitted from each cell, and a feedback control section that allocates delivery acknowledgement signals in response to the DL signals received, by allocating the delivery acknowledgment signals in a predetermined UL subframe, and, regardless of the cell that is configured as the primary cell, when UL subframes are configured in both the FDD cell and the TDD cell, the feedback control section feeds back the delivery acknowledgement signals by using a UL subframe of one or both of the cells, and, when a UL subframe is configured only in the FDD cell, the feedback control section feeds back the delivery acknowledgement signals by using the UL subframe of the FDD cell. |
| US10090987B2 |
Cell release mechanism in a wireless device and wireless network
A wireless device receives from a base station at least one first message that comprises one or more parameters of a plurality of cells. The plurality of cells comprise a secondary cell with no configured physical uplink control channel (PUCCH). The wireless device receives a first activation command indicating activation of the secondary cell. The wireless device receives at least one second message that comprises parameters for reconfiguring the secondary cell to a PUCCH secondary cell with a PUCCH on a condition of first releasing the secondary cell. The wireless device releases the secondary cell. The wireless device adds the PUCCH secondary cell with the PUCCH. The wireless device receives a second activation command indicating activation of the PUCCH secondary cell. The wireless device transmits to the base station channel state information via the PUCCH secondary cell. |
| US10090986B2 |
Method and apparatus for transmitting reference signal in multiple antenna supporting wireless communication system
The present invention discloses a method and an apparatus for transmitting a reference signal in a wireless communication system. More specifically, the method comprises configuring a first antenna group on the basis of a plurality of antenna elements configured by a horizontal domain antenna element and a vertical domain antenna element; transmitting a configuration with regard to a specific sub frame to first terminals through a first antenna group; receiving a sounding reference signal (SRS) through the specific sub frame from the first terminals; selecting at least one second terminal among the first terminals on the basis of the sounding reference signal; and transmitting a channel state information-reference signal (CSI-RS) with respect to the at least one second terminal, wherein the specific sub frame is characterized in that at least a part of a source area is configured by a multicast broadcast single frequency network (MBSFN) sub frame. |
| US10090979B2 |
Method for transmitting sounding reference signal in MMO wireless communication system and apparatus therefor
A method for transmitting a sounding reference signal in a MIMO wireless communication system and an apparatus therefor are disclosed. The method for transmitting sounding reference signals (SRSs) in a MIMO wireless communication system comprises receiving sounding reference signal parameters from a base station; receiving information of the number of sounding reference signals which will be transmitted at a transmission time instant from the base station; if a plurality of sounding reference signals are provided, generating the sounding reference signals corresponding to each of the plurality of antennas by using the sounding reference signal parameters; and transmitting the generated sounding reference signals to the base station through their corresponding antennas at a specific transmission instant. |
| US10090976B2 |
User equipment, a network node and methods therein for enabling Device-to-Device (D2D) communication in a radio communications network
A method performed by a first User Equipment, UE, for enabling Device-to-Device, D2D, communication with a second UE in a radio communications network is provided. The first UE is configured to perform the D2D communication on downlink cellular resources in the radio communications network. The first UE measures received signal strengths of Reference Signals, RS, on downlink cellular resources from one or more network nodes in the radio communications network. The first UE then determines a first subset of downlink cellular resources for which the measured received signal strength of RS is above or equal to a threshold value. Also, the network node transmits information indicating the determined first subset of downlink cellular resources to a network node serving the first UE in the radio communications network in order to enable the D2D communication. |
| US10090969B2 |
Method and apparatus for transmission
Aspects of the disclosure provide an apparatus that includes a transceiver circuit and a processing circuit. The transceiver circuit is configured to receive a trigger signal this is transmitted by another apparatus. The trigger signal triggers transmissions by a first group of apparatuses including the apparatus, and defers transmissions by a second group of apparatuses that interfere the transmissions by the first group of apparatuses. The processing circuit is configured to, in response to the trigger signal, generate a frame with a first preamble structure that is different from a second preamble structure that is used by the second group of apparatuses, and provide the generated frame to the transceiver circuit for transmission. |
| US10090961B2 |
Multi-channel optical cross-phase modulation compensator
A method and system for multi-channel optical XPM compensation may include a DCM to improve performance of a feed-forward control loop in an optical path in an optical network. Additionally, various spectral overlap schemes may be used with multi-channel WDM optical signals using XPM compensators in parallel, such as at a ROADM node. Polarization diversity may also be supported for XPM compensation including a DCM. |
| US10090959B2 |
Free space optical communications network with multiplexed bent pipe channels
A free space optical communications network comprises a constellation of relay nodes in serial optical communication to form an optical path. The relay nodes are configured to wavelength-multiplex a plurality of wavelength-dependent optical bent pipe channels into and out of the optical path. |
| US10090958B2 |
High speed MMF (multi-mode fiber) transmissions via orthogonal wavefronts
A system is provided for high speed optical fiber data transmission by generating artificial wavefronts along multiple paths exhibiting spatial mutual orthogonality. Multiple independent signal streams are “structured” over a group of different propagation paths that are coherently organized by wavefront multiplexing and dc-multiplexing techniques. Therefore, signal streams with enhanced throughput and reliability may be fully recovered at destinations via embedded diagnostic signals and optimization loops. Multiple optical channels are matched with multiple orthogonal wavefronts created by a signal pre-processor. A receiving end signal post-processor dynamically aligns propagation paths via diagnostic signals and orthogonality of the propagation wavefronts electronically. The multiple optical channels are coherently bonded into a single virtual channel, thereby increasing data bandwidth while reducing interference and unwanted multi-path effects. The wavefront multiplexing and de-multiplexing functions may be performed in a dedicated signal processor or may reside in a general-purpose microprocessor located in the user terminal. |
| US10090953B2 |
Method and system to add and communicate with remote terminal addresses beyond a standard bus protocol
A method of messaging in a communication system that operates in accordance with a standard protocol limited in the number of uniquely addressable remote terminals by a message frame that sequences the messages into a limited number of time slots includes redefining the message frame into a plurality of major frames. Each major frame includes at least one minor frame occupying a unique time slot to address a unique remote terminal. Messages are sequenced into the at least one minor frame. Each minor frame includes a set of time-division multiplexed messages. Each message in the set includes an address field identifying the address of a remote terminal and an additional message to each major frame encoding an output path. The output path encoded in each major frame and the unique time slot in the minor frame determines which remote terminal is addressed by the message. |
| US10090949B2 |
Transmitting apparatus and receiving apparatus, and signal processing method thereof
Provided are a transmitting apparatus, a receiving apparatus and methods of transmitting and receiving a data frame. The transmitting apparatus includes: a frame generator configured to cluster a predetermined number of frames to generate a frame cluster, at least one of the frames being generated by mapping data contained in an input stream to at least one signal processing path; an information inserter configured to insert signaling information into a signaling area of the at least one frame; and a transmitter configured to transmit the frame with the signaling information inserted therein, wherein the signaling information comprises profile information and duration information about the frame included in the frame cluster. |
| US10090948B2 |
Request to send (RTS) to group within wireless communications
A wireless communication device (alternatively, device) includes a processing circuitry configured to support communications with other wireless communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processing circuitry, among other possible circuitries, components, elements, etc. to support communications with other wireless communication device(s) and to generate and process signals for such communications. A device generates and transmits a request to send (RTS) to group (RTG) frame to other devices. In response to the RTG frame, the device receives clear to send (CTS)(s) from one or more of the other devices and generates and transmits an orthogonal frequency division multiple access (OFDMA) data frame to those one or more of the other devices based thereon. The RTG frame can include different RTSs transmitted via different channels, sub-channels, sub-carriers, etc. to the different other devices. |
| US10090945B2 |
MIMO communication system of transmitting and receiving pilot signals to estimate a channel
A MIMO communication method of performing MIMO communication between a base station having a plurality of antennas and each of a plurality of terminals covered by the base station using uplink data slots and downlink data slots that are alternately placed on a time axis. The method includes, in the base station, despreading a received signal that is transmitted from each of the plurality of terminals demodulating the transmission data transmitted from a respective terminal on the basis of the value of the estimated channel; decoding a received signal included in the uplink data slots, estimating a current channel between each of all antennas of the base station and the respective terminal; and comparing the stored value of the estimated channel with a value of the estimated current channel and updating the stored value of the estimated channel to the value of the estimated current channel. |
| US10090936B2 |
Integrated circuitry systems
There is disclosed herein a circuitry system comprising first and second IC chips, configured or configurable such that; the first IC chip has an output terminal connected to receive an output signal from an output-signal unit of the first IC chip, the output-signal unit being connected between high and low voltage-reference sources of the first IC chip, the high and low voltage-reference sources being connected to respective high and low voltage-reference terminals of the first IC chip; and the second IC chip has an input terminal connected in a potential-divider arrangement between high and low voltage-reference terminals of the second IC chip, wherein: the high and low voltage-reference terminals of the first IC chip are respectively connected to the high and low voltage-reference terminals of the second IC chip; and the output terminal of the first IC chip is connected to the input terminal of the second IC chip. |
| US10090932B2 |
Method and system for transmitting a plurality of audio channels over frequency modulated infrared bands
The present invention pertains to a method for transmitting a plurality of audio channels over frequency modulated infrared bands, the method comprising periodically transmitting a configuration message and associated audio channel messages, said configuration message comprising an indication of the number of said audio channels, wherein the number of audio channels is greater than 32 and the number of audio channels is coded in two non-adjacent fields. The invention also pertains to a system for receiving a plurality of audio channels over frequency modulated infrared bands as transmitted according to the method described above. |
| US10090930B2 |
Apparatus having first and second transceiver cells formed in a single integrated circuit
An apparatus having first and second transceiver cells formed in a single integrated circuit. In one example embodiment, an apparatus includes a first transceiver cell including a first set of components configured to enable communication on a first communication link in a network and a second transceiver cell formed underneath the first transceiver cell in a single integrated circuit (IC). The second transceiver cell is optically isolated from the first transceiver cell. The second transceiver cell includes a second set of components configured to enable communication on a second communication link in the network. |
| US10090929B2 |
Drone-based radio-over-fiber system
The drone-based radio-over-fiber system provides an unmanned aerial vehicle (AV), preferably a multi-rotor drone, connected to a base station by a tether including an optical fiber. A radio frequency-over-fiber system is used for bidirectional data communications between at least one radio frequency (RF) transmitter at the base station and at least one antenna mounted on the drone through the optical fiber in the tether. The system includes wave division multiplexers/demultiplexers that permit ultrahigh bandwidth communication over the tether. An embodiment of the system for 2×2 multiple-input, multiple-output (MIMO) signals in the 700 MHz LTE band is described. |
| US10090928B2 |
Analog optical transmission system using dispersion management technique
Provided is an analog optical transmission system using a dispersion management technique. The analog optical transmission system may include a digital unit (DU) pool including a plurality of DUs to transmit an optical signal; a plurality of radio units (RUs) to receive the optical signal; and one or more dispersion management apparatus to remove a signal distortion component caused by an interaction between a chirp and chromatic dispersion by compensating for the chromatic dispersion before the plurality of RUs receives the optical signal that is transmitted from the DU pool. |
| US10090925B2 |
LED light fixture
An LED light fixture includes one or more optical transceivers that have a light support having a plurality of light emitting diodes and one or more photodetectors attached thereto, and a processor in communication with the light emitting diodes and the one or more photodetectors. The processor is constructed and arranged to generate a communication or data transfer signal. |
| US10090922B2 |
Loss of signal detector
A loss of signal (LOS) detector may include a comparator including a first input, a second input and an output indicating a LOS status. The LOS detector further includes circuitry to compare a first signal on the first input generated by differential input signals and a threshold signal common mode with a second signal on the second input generated by differential threshold signals at a first level and an input signal common mode. The circuit further configured to generate a LOS indicator on the output based on the compare. |
| US10090918B2 |
Collective acquisition-type photodetection device and photodetection method having a time delay adjustment unit wherein each time-adjusted optical signal train is photomixed with an optical frequency comb at different timings in a photomixer
To realize collective measurement of ultrawide-band optical signals which have exceeded an electrical band limit. This photodetection device (100) comprises: a time-delay adjustment means (10) into which is input an optical signal that is a detection object; an optical frequency comb generator (20) that generates an optical frequency comb; a photomixer (30) that photomixes optical signal series which are sequentially output from the time delay adjustment means (10) and which were subjected to time adjustment, and the optical frequency comb signal which is output from the optical frequency comb generator (20); and a photodetector (40) that detects the mixed signal output from the photomixer (30). The time delay adjustment means (10) performs time adjustment on the optical signal series so that each of the time adjusted optical signal series is photomixed with the optical frequency comb at different timings in the photomixer (30). |
| US10090917B2 |
Method and apparatus for automatic determination of a fiber type
A method and apparatus for automatic determination of a fiber type of at least one optical fiber span used in a link of an optical network, the method comprising the steps of measuring a length of said optical fiber span; measuring a chromatic dispersion of said optical fiber span; determining a fiber dispersion profile of said optical fiber span on the basis of the measured length and the measured fiber chromatic dispersion; and determining a fiber category and/or a specific fiber type of said optical fiber span depending on the determined fiber dispersion profile. |
| US10090916B2 |
Optical module availability detection method and apparatus
A detection apparatus concurrently connected to N optical module cages by using N paths. The apparatus accesses a conflict register, acquires an occupancy status of the N paths according to a value of the conflict register, then performs a concurrent probe on M optical module cages connected to M paths that are in the N paths and whose occupancy status are not occupied by system software, to obtain a probe result, where the probe result includes availability information of optical modules of the M optical module cages and a type of the optical modules, and finally, writes the probe result into an availability register, so that the system software can acquire the probe result from the availability register. Therefore, whether an optical module is available in an optical module cage can be monitored in real time and fast insertion and removal operations on the optical module can be sensed. |
| US10090914B2 |
Test probes for smart inspection
One or more embodiments are directed to apparatuses and methods of evaluating an endface of an optical communication link, such as a fiber optic cable. In at least one embodiment, a camera probe includes an imaging device that includes one or more feedback mechanisms, such as an alignment feedback mechanism that communicates alignment information regarding an alignment of the optical communication link under test with an image sensor of the camera probe. The alignment feedback mechanism may be visual and/or aural. The alignment feedback mechanism may provide directional information to the user indicative of a direction to move the imaging device relative to the optical communication link. In addition or alternatively, the feedback mechanism may include a focus feedback mechanism that communicates focus information regarding a focus of the endface in an obtained image of the endface. |
| US10090913B2 |
Automatic bandwidth adjustment on multi-fiber optics
A device is configured to store information indicating a threshold bandwidth with which a multi-lane link is permitted to operate. The device may establish the multi-lane link with a peer device. The multi-lane link may include multiple lanes used to communicate data with the peer device. The device may determine fault states for the lanes included in the multi-lane link. A fault state, for a particular lane, may indicate that the particular lane is faulty. The device may determine an available bandwidth for the multi-lane link based on the fault states for the lanes. The device may selectively terminate the multi-lane link or operate the multi-lane link at the available bandwidth based on whether the available bandwidth satisfies the threshold bandwidth. |
| US10090912B2 |
Antenna system of mobile communication base station
The present invention is an antenna system of a mobile communication base station, comprising: a signal separation unit which is arranged within a radome of an antenna, and which separates a synthetic signal of a wireless signal transmitted from a main system of a base station through a feeder cable, a direct current power signal and a control signal having a preset format for controlling the antenna, in such a manner that the direct current power signal and the control signal are output by being separated from the wireless signal and the wireless signal is provided to an antenna unit; and equipment to be remotely controlled having a modem for receiving the direct current power signal and the control signal output from the signal separation unit and using the direct current power signal as an operating power and converting the control signal into a format which is preset to be internally recognizable in the radome of the antenna, the equipment to be remotely controlled performing an antenna control operation according to a control signal. |
| US10090909B2 |
Maintaining antenna connectivity based on communicated geographic information
Example methods, apparatus, systems, and articles of manufacture (e.g., physical storage media) to facilitate maintaining of antenna connectivity based on communicated geographic information are disclosed. An example method may include receiving, by a device, position information from a base station. The position information may include an altitude associated with the base station. The method may further include determining a positional difference between the device and the base station based at least on the position information. The method may further include configuring an antenna of the device based at least on the positional difference. |
| US10090908B1 |
Data services for wireless communication devices that are attached to wireless repeater chains
A wireless base station receives attachment signaling for User Equipment (UE) from a wireless repeater chain and identifies a number of repeater hops for the UE between the base station and a serving wireless repeater. The base station transfers signaling indicating the UE ID and the number of wireless repeater hops. A network controller receives the signaling and selects data services for the UE based on the UE ID and the number of wireless repeater hops. The network controller exchanges signaling indicating the selected data services for the UE with a network element to deliver the data services to the UE. The network controller transfers signaling indicating the UE ID and the selected data services to the wireless base station. In some examples, the data services comprise Access Point Names (APNs), and the network controller comprises a Mobility Management Entity (MME). |
| US10090907B2 |
Antenna switching system and method
The present invention is applicable to the field of mobile terminals and provides an antenna switching system and method. The antenna switching system includes a radio-frequency transceiver circuit, a primary antenna, and a parasitic antenna, where the primary antenna is connected to the radio-frequency transceiver circuit, and further includes a switch circuit, configured to connect, when the parasitic antenna is used to receive or send a radio-frequency signal, the parasitic antenna and the radio-frequency transceiver circuit. If the parasitic antenna is grounded, the parasitic antenna may be configured to spread a spectrum. In addition, when carrier aggregation is needed, the parasitic antenna is connected to the radio-frequency transceiver circuit, so as to become an independent receive or transmit antenna. |
| US10090901B2 |
Method and apparatus for optimizing antenna precoder selection with coupled antennas
A method and apparatus optimize antenna precoder selection with coupled antennas. A power metric corresponding to each precoder of a plurality of precoders can be received at a receiving device. Reference signals can be received. A transmission channel corresponding to each precoder can be estimated based on the reference signals. The estimate of the transmission channel can be scaled based on the power metric for each precoder. A channel quality metric for each precoder can be generated based on the scaled estimate of the transmission channel. An index of a precoder with the largest channel quality metric can be transmitted. |
| US10090900B2 |
Excursion compensation in multipath communication systems having performance requirements parameters
Methods, apparatuses, and systems that compensate for communication excursions in multipath communication systems (e.g. MIMO communication systems) while satisfying performance requirements parameters of the communication system. A plurality of communication signals may be received in a transmitter. The plurality of communication signals may be precoded (e.g. mixed) into a plurality of precoded communication signals. Excursions in the precoded communication signals may be scaled to generate a plurality of excursion compensated precoded communication signals. The scaling may be based on performance requirements parameters of a communication system and based on parameters of the precoding the plurality of communication signals. The plurality of excursion compensated precoded communication signals may then be amplified by a plurality of amplifiers. |
| US10090899B2 |
Method for determining precoder for hybrid beamforming in wireless communication system, and apparatus therefor
Disclosed in the present application is a method by which a terminal receives a signal, to which hybrid beamforming is applied, from a base station in a wireless communication system. More specifically, the method comprises the steps of: acquiring information on a first precoder for first beamforming of the hybrid beamforming; generating information on a precompensation precoder for the first beamforming by using the information on the first precoder; reporting the information on the precompensation precoder to the base station; and receiving, from the base station, a signal to which the precompensation precoder, the first beamforming, and second beamforming are applied, wherein the precompensation precoder adjusts, to zero degrees, a boresight direction of a signal to which the first precoder for the first beamforming is applied, and a second precoder for the second beamforming is configured to enable the signal to be transmitted in a final boresight direction on the basis of a boresight direction of zero degrees. |
| US10090897B2 |
Communication system and channel estimating method thereof
A communication system includes at least one transmitting unit and at least one receiving unit. The at least one transmitting unit is configured to transmit at least one input signal after precoding it with at least one precoding matrix. The at least one receiving unit wirelessly coupled with the at least one transmitting unit is configured to receive the at least one precoded input signal, and generate at least one channel quality signal corresponding to the at least one precoded input signal, in which the at least one transmitting unit generates at least one magnitude information estimate or at least one phase information estimate or at least one of both for at least one channel state information according to the at least one channel quality signal, the at least one precoding matrix and at least one noise size signal. |
| US10090892B1 |
Apparatus and a method for data detecting using a low bit analog-to-digital converter
An apparatus and a method for detecting data transmitted over a wireless channel are disclosed. For example, for each receive antenna of a plurality of receive antennas, the method converts, by an ADC, an analog signal received by the receive antenna to a respective digital signal, and for each receive antenna of the plurality of receive antennas, the method channel transforms, by a channel transformer, the digital signal to determine a respective equivalent integer representation of the digital signal, and the method detects data by receive combining, by a receive combiner, the respective equivalent integer representations of the digital signals determined for the plurality of receive antennas. |
| US10090891B2 |
MIMO systems with active scatters and their performance evaluation
Presented are MIMO communications architectures among terminals with enhanced capability of frequency reuse by strategically placing active scattering platforms at right places. These architectures will not depend on multipaths passively from geometry of propagation channels and relative positions of transmitters and those of receivers. For advanced communications which demand high utility efficiency of frequency spectrum, multipath effects are purposely deployed through inexpensive active scattering objects between transmitters and receivers enable a same frequency slot be utilized many folds such as 10×, 100× or even more. These active scatters are to generate favorable geometries of multiple paths for frequency reuse through MIMO techniques. These scatters may be man-made active repeaters, which can be implemented as small as 5 to 10 watt lightbulbs for indoor mobile communications such as in large indoor shopping malls. The architecting concept can be certainly implemented via mini-UAV platforms parking on tops of light-poles, or tree tops, or tops of stadiums, or circulating in small “figure-8” or small circles slowly. This systems can be pushed to facilitate >>100× frequency reuses among users. It may be one of possible solutions for 5G deployment and many other applications which needs high efficiency in frequency utility. |
| US10090883B2 |
Radio frequency interconnect having a preamble generator
A radio frequency interconnect includes a transmitter coupled with an input end of a transmission line, and a receiver coupled with an output end of the transmission line. The transmitter includes a first carrier generator configured to generate a clock recovery signal based on a carrier signal, to output a reference clock signal, and to transmit the clock recovery signal to the receiver. The transmitter also includes a modulator configured to modulate a data packet based on the carrier signal. The transmitter also includes a preamble generator configured to generate and add a preamble to data to generate the data packet. The preamble includes a data sequence associated with the reference clock signal. The transmitter further includes a transmitter output configured to transmit the modulated data packet to the receiver by the transmission line. |
| US10090882B2 |
Apparatus suppressing acoustic echo signals from a near-end input signal by estimated-echo signals and a method therefor
In an echo suppressing apparatus suppressing from a near-end input signal acoustic echo signals caused by a far-end signal, an estimated-echo path characteristic is multiplied by a far-end signal to produce an estimated-echo signal for each frame, and frames of the estimated-echo signals thus obtained are stored in an estimated-echo signal storage. A delay amount estimator calculates the total of differences between the near-end input signal and each estimated-echo signal thus stored, and determines the amount of frame delay having its total of differences minimal. A delay estimated-echo signal calculator uses the amount of frame delay to read out an optimum frame and near frames respectively preceding and following the optimum frame and to calculate a corrected, delay estimated-echo signal. An echo suppressor uses the estimated-echo signal thus corrected to suppress the acoustic echo signals from the near-end input signal. |
| US10090877B2 |
Housing for encasing a mobile computing device
An apparatus and a system for housing a device are described. The housing may include top and bottom members that may be removably coupled together so as to form the housing. The bottom member includes a bottom peripheral portion having a sound transmission portion configured to allow sound to traverse through the bottom member. The sound transmission portion is positioned on a back surface of the bottom peripheral portion proximate a speaker portion of the mobile computing device when the mobile computing device is encased by the protective encasement. The speaker transmission port includes a plurality of apertures translating from the interior surface of the bottom member to the external surface of the bottom member and an acoustic vent membrane overlaying the plurality of apertures, the acoustic vent membrane configured to allow sound but not water to pass through the acoustic vent membrane. |
| US10090876B1 |
Electronic devices with masking layers
An electronic device may have transparent structures. The transparent structures may include a transparent member such as a transparent button member, a transparent member that serves as a display cover layer, a transparent member that covers a sensor such as a touch sensor, or other transparent member. The transparent member may have an inner surface that is covered with an opaque masking layer that is free of materials that discolor upon light exposure and that is formed from a layer of polymer and light-scattering inclusions such as solid particles, hollow microspheres, porous particles, and voids. A protective layer such as an inorganic layer may be formed over the polymer layer. A fingerprint sensor, touch sensor, or other structures may be attached to the opaque masking layer using a layer of adhesive. |
| US10090872B2 |
Method and apparatus for estimating a frequency domain representation of a signal
A signal processing method for estimating a frequency domain representation of signal from a series of samples distorted by an instrument function, the method comprising obtaining the series of samples; obtaining a set of coefficients that fit a set of basis functions to a complex exponential function wherein the set of basis functions comprises a plurality of basis functions each defined by a shifted version of the instrument function in a signal domain; estimating the frequency domain representation of the signal based on the series of samples and the coefficients. This is wherein the estimate of the instrument function is based on a characterization of the instrument function in the frequency domain at frequencies associated with the complex exponential function. |
| US10090865B2 |
Performance optimization in soft decoding of error correcting codes
Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords. |
| US10090864B2 |
System and method for decoding variable length codes
A method for decoding a variable length coded input including a plurality of binary code symbols into an output symbol includes: setting, by a decoder including a processor and memory storing a lookup table including a plurality of states, a current state to an initial state and a current branch length to an initial branch length; and identifying, by the decoder using the lookup table, a next state or a symbol of the output symbols based on a current state, a current branch length, and a next binary code symbol of the variable length coded input. |
| US10090862B2 |
Hybrid soft decoding algorithm for multiple-dimension TPC codes
An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure. |
| US10090859B2 |
Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal
A method for transmitting broadcast signals includes LDPC (Low Density Parity Check) encoding broadcast data, where the broadcast data is carried by a physical layer pipe (PLP); padding zero bits to signaling data; LDPC encoding the zero padded signaling data; removing the padded zero bits; time interleaving the LDPC encoded broadcast data, where the time interleaving is performed based on a skip operation by using a twisting parameter; building at least one signal frame including the time interleaved broadcast data and the zero removed signaling data, where when a first PLP and a second PLP are multiplexed, and the signaling data includes information related to the second LP with which the first PLP is associated. |
| US10090855B2 |
Delta-sigma modulator, and transmitter
A delta-sigma modulator is provided with: a loop filter 30; a quantizer 36 that generates quantized data on the basis of an output from the loop filter 30; an internal path 42 connected to the loop filter 30 or the quantizer 36; and a compensator 38 that provides, to the internal path 42, a compensation signal for compensating for distortion that occurs in a frequency component at a target frequency, the frequency component being among frequency components of a pulse train corresponding to the quantized data. |
| US10090853B1 |
Analog-to-digital conversion device
An analog-to-digital conversion device is provided for converting an input signal pair to generate an output signal. The analog-to-digital conversion device includes switch groups, capacitors, a comparator, and a controller. The switch groups receive the input signal pair and reference voltages, and selects to output one of the input signal pair and the reference voltages according to a control signal to generate selection voltages respectively. The capacitors receive the selection voltages respectively and generate a first comparison voltage and a second comparison voltage. The comparator compares the first comparison voltage and the second comparison voltage to generate a comparison result signal. The controller sets conversion times for converting bits of the output signal according to the comparison result signal, wherein at least two of the conversion times are different. |
| US10090848B1 |
Data converters systematic error calibration using on chip generated precise reference signal
A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit. |
| US10090847B1 |
Complete complementary code parallel offsets
A system and method of converting an analog input signal to a digital output signal includes coupling an analog input signal to a plurality of analog-to-digital converters (ADCs) arranged in a parallel configuration. Pseudo-random discrete valued complementary offset voltage levels that span an input voltage range of the sum of the plurality of ADCs are generated. An amount of continuous, analog dither that randomly varies at values between the discrete offset voltage levels is generated, the analog dither being less than steps between the discrete offset voltage levels. On different clock cycles, different discrete offset voltage levels are coupled to at least some of the ADCs. At each ADC, the respectively coupled analog input, discrete offset voltage level, and continuous analog dither are quantized to obtain a digital output. The respective digital outputs are combined to obtain a linearized digital representation of the analog input signal. |
| US10090839B2 |
Reconfigurable integrated circuit with on-chip configuration generation
Reconfigurable Integrated Circuit with On-Chip Configuration Generation A circuit and method are provided in which reconfiguration is achieved through the modification of a dynamic data path using configuration information generated on the basis of run-time variables. Rather than storing a plurality of pre-set configurations, this can allow configurations optimized to processing tasks to be implemented during operation. |
| US10090837B2 |
Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit. |
| US10090831B2 |
Method for electrically aging a PMOS thin film transistor
The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor. |
| US10090830B2 |
Switch apparatus
An apparatus and methods of breaking a circuit using a switch are disclosed. In an example, a variable voltage is applied across a switch, which comprises a series connection of switching elements which are individually controllable between a blocking state and a conductive state. The state of the switching elements is controlled such that at least a portion of switching elements are in the blocking state, and fewer switching elements are in the blocking state when the applied voltage magnitude is low than when the applied voltage magnitude is high. |
| US10090826B1 |
Supply-noise-rejecting current source
Various technologies pertaining to a high-impedance current source are described herein. The current source outputs a substantially constant current by way of a first transistor that draws current from a supply. The current source is configured to feed back noise from the supply to a feedback resistor at an input of an operational amplifier (op-amp) by way of a second transistor. The feedback resistor and the op-amp are configured such that responsive to receiving the supply noise feedback, the op-amp drives a gate voltage of the first transistor to cause the first transistor to reject the supply noise and cause the output of the current source to remain substantially constant. |
| US10090825B2 |
Acoustic wave device
An acoustic wave device includes: a first substrate; a first acoustic wave filter located on a first surface of the first substrate; a pad that is located on the first surface and electrically separated from the first acoustic wave filter in the first surface; a ground pattern that is located on the first surface, and is located between the pad and the first acoustic wave filter in the first surface; and a second acoustic wave filter that is electrically connected to the pad, and at least partially overlaps with the first acoustic wave filter in plan view. |
| US10090824B2 |
Filter apparatus
A filter apparatus includes a plurality of stages of ladder circuits connected between an input terminal and an output terminal, and a band width ratio is about 4.3 % or higher. The ladder circuits of respective stages include series arm resonators, parallel arm resonators, first inductors respectively connected between a ground potential and first end portions, and second inductors respectively connected between the ground potential and second end portions. |
| US10090823B2 |
Elastic wave resonator and ladder filter
An elastic wave resonator includes series divided resonators on a piezoelectric substrate, first and second outer busbars, a first interstage busbar, first to fourth electrode fingers and first and second dummy electrode fingers. Third dummy electrode fingers are not provided at at least one of a side where the second electrode fingers are provided and a side where the third electrode fingers are provided or third dummy electrode fingers having a length smaller than lengths of the first and second dummy electrode fingers are provided at at least one of a side where the second electrode fingers are provided and a side where the third electrode fingers are provided. The third electrode fingers are arranged on an extension to which the second electrode fingers extend. |
| US10090822B2 |
Surface acoustic wave (SAW) resonator
A surface acoustic wave (SAW) resonator includes a piezoelectric layer disposed over a substrate, and a plurality of electrodes disposed over the first surface of the piezoelectric layer. A layer is disposed between the substrate and the piezoelectric layer. A surface of the layer has a smoothness sufficient to foster atomic bonding between layer and the piezoelectric layer. A plurality of features provided on a surface of the substrate reflects acoustic waves and reduce the incidence of spurious modes in the piezoelectric layer. |
| US10090820B2 |
Stealth-dicing compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices
Stealth-dicing-compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices are disclosed. An acoustic wave device comprises a substrate having opposing top and bottom surfaces, where a first portion of the bottom surface has a higher roughness than a second portion of the bottom surface, and an acoustic resonator over the top surface of the substrate. The acoustic resonator comprises a piezoelectric layer having opposing top and bottom surfaces and a plurality of electrodes, at least some of which are disposed on the top surface of the piezoelectric layer. The first portion of the bottom surface of the substrate is below and opposite from the acoustic resonator, and the second portion of the bottom surface of the substrate is not located below and opposite from the acoustic resonator. Multiple first portions, each separated from the other by second portions, may exist. |
| US10090819B2 |
Signal processor for loudspeaker systems for enhanced perception of lower frequency output
A signal processing system for controlling a lower frequency acoustic range of an acoustic output of a loudspeaker system. The system includes an input to receive at least a first channel audio signal, corresponding to the acoustic output of at least one loudspeaker with at least one electro-acoustic transducer with a vibratile diaphragm. The signal processing system includes at least one transpositional gain controller processor for transposition of at least a portion of the amplitude of at least one band of frequencies in a lower frequency audio signal range of the audio signal, to an increased gain in at least one transpositional target frequency in the lower frequency audio signal range. The transpositional gain controller processor includes at least one of at least one, static or dynamic, transpositional gain controller. The system may include at least one additional signal processor, supporting preservation of a perceived fidelity of the acoustic output. |
| US10090817B2 |
System and method for leveling loudness variation in an audio signal
Systems and methods for leveling loudness variation in an audio signal are described. Embodiments use both a perceptual leveling algorithm and a standards-based loudness measure together to minimize audio process artifacts and ensure that the measured loudness of the processed audio is close to a required measure, according to a particular standard measurement of loudness. These systems and methods can be used either offline or in real-time. |
| US10090816B2 |
Current reuse amplifier
A two-stage amplifier of a type of the current re-use configuration is disclosed. The amplifier includes first to third transistors, where the first transistor constitute the first stage, while, the latter two transistors constitute the second stance. The first to third transistors are connected in series between a power supply and ground such that a bias current supplied to the third transistor flows in the second and first transistors. The first transistor in the source thereof is grounded in the DC mode. The second transistor is grounded in the AC mode but floated in the DC mode. The third transistor that outputs an amplified signal is connected in parallel in the AC mode but in series in the DC mode with respect to the second transistor. |
| US10090815B2 |
Common-mode feedback for differential amplifier
An embodiment circuit includes an operational amplifier having a first output terminal and a second output terminal. The circuit further includes a detector coupled between the first output terminal and the second output terminal of the operational amplifier. The detector is configured to detect a common-mode output voltage at the first output terminal and the second output terminal of the operational amplifier. The circuit also includes a feedback amplifier having a first input terminal coupled to the detector and a second input terminal configured to receive a reference voltage. The feedback amplifier is configured to generate a feedback signal based on the common-mode output voltage and the reference voltage and to provide the feedback signal to the operational amplifier. The circuit additionally includes an impedance element having a first terminal coupled to the first input terminal of the feedback amplifier and a second terminal coupled to a supply voltage. |
| US10090814B2 |
Removal of switching discontinuity in a hybrid switched mode amplifier
A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input. |
| US10090813B2 |
Power amplifier
A power amplifier includes an input amplifier, a comparator, a switching circuit, an output filter and a feedback filter. The input amplifier receives an input signal of the power amplifier at a positive input of the input amplifier and an output signal of the feedback filter at a negative input of the input amplifier. The input amplifier has a capacitive feedback from an output of the input amplifier to the negative input of the input amplifier. The comparator receives the output signal of the input amplifier at a positive input of the comparator and the output signal of the feedback filter at a negative input of the comparator. The comparator provides a control signal based on a comparison between signal levels of the signals at the positive and the negative inputs of the comparator. The switching circuit includes power switches and receives the control signal and controls the power switches that connect an output of the switching circuit to either a positive supply voltage or a negative supply voltage based on the control signal. The output filter receives an output signal provided at the output of the switching circuit and provides a filtered signal thereof to an output of the power amplifier. The feedback filter receives the output of the power amplifier and provides a filtered feedback signal to the negative input of the comparator and towards the negative input of the input amplifier. |
| US10090805B2 |
Voltage-controlled oscillator and a method for tuning oscillations
Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network. |
| US10090798B2 |
Machine learning apparatus and method learning predicted life of power device, and life prediction apparatus and motor driving apparatus including machine learning apparatus
A machine learning apparatus that learns predicted life of a power device of a motor driving apparatus converting DC power into AC power by a switching operation of the power device to supply the AC power to an AC motor includes: a state observation unit that observes a state variable constituted by data regarding the number of times of switching of the power device, data regarding junction temperature of the power device, and data regarding presence or absence of a failure of the power device; and a learning unit that learns the predicted life of the power device in accordance with a training data set defined by the state variable. |
| US10090795B2 |
Motor drive having function of protecting dynamic braking circuit
A motor drive according to the present invention includes an inverter, a motor rotational speed obtaining unit, a motor inertia information storage unit, a motor rotational energy calculator, a dynamic braking circuit, a tolerance information storage unit for storing the tolerances of resistors of the dynamic braking circuit, a power element operation unit, a dynamic braking circuit operation unit, and a tolerance comparator for performing a comparison between the rotational energy of a motor and the tolerance of the dynamic braking circuit. When the rotational energy exceeds the tolerance, power elements of one of arms are turned on, while power elements of the other arm are turned off, without actuating the dynamic braking circuit. When the rotational energy is equal to or less than the tolerance, the dynamic braking circuit is actuated, and the power elements of the one of the arms are turned off. |
| US10090793B2 |
Electric motor, compressor, and method for controlling electric motor or compressor
An electric motor, a compressor including the electric motor and a method for controlling the electric motor or the compressor are provided. The electric motor includes: a stator; single-phase or multiphase windings disposed on the stator; and a rotor, where the rotor includes a permanent magnet, and at least part of the permanent magnet is ferrite. By using a permanent magnet synchronous motor in a variable-speed compressor, costs of the variable-speed compressor are significantly reduced, and the performance thereof is basically the same as that of a variable-speed compressor using a rare-earth permanent magnet synchronous motor. By controlling the electric motor or the compressor, costs of the electric motor or the compressor are reduced, and moreover, and the ferrite in the electric motor can be protected from irreversible demagnetization at a low temperature, thereby improving the reliability of the compressor. |
| US10090792B2 |
Self-balancing parallel power devices with a temperature compensated gate driver
A powertrain includes a first and second switch coupled in parallel to drive an electric machine and a gate driver. The gate driver may be configured to, in response to a transition request while a first temperature of the first switch exceeds a second temperature of the second switch, inject a current onto a gate of the second switch to drive rates of change of current through the first and second switch to the electric machine to a same value. |
| US10090790B2 |
Motor control device
The occurrence of torque in the motor due to an unintentional flow of the q-axis current in the motor during discharging of the smoothing capacitor is reduced. A motor control device according to the present invention controls a system including an inverter including a smoothing capacitor connected to a power source via a relay, a motor connected to the inverter, and a current sensor configured to detect a current flowing through the motor, the motor control device including: an electric discharge control unit configured to discharge, in the motor via the inverter, an electric charge accumulated in the smoothing capacitor; and a current sensor calibration unit configured to calibrate the current sensor in a state where no current in the motor flows during a time period from when the relay is cut off to when discharge control by the electric discharge control unit is started, wherein the electric discharge control unit performs discharge by controlling the current in the motor based on a value of the current sensor calibrated by the current sensor calibration unit. |
| US10090785B2 |
Electric arrangement and method for controlling of at least two electric motors
An electric arrangement which, for controlling at least two electric motors, has at least one first H-bridge arrangement and a second H-bridge arrangement, is provided. The electric arrangement comprises a first electric motor, which is electrically connected to a first switching element, a second switching element, a third switching element and a fourth switching element in the first H-bridge arrangement. The electric arrangement furthermore comprises a second electric motor, which is arranged in a second bridge branch of the second H-bridge arrangement) and is connected to a third half-bridge via a third motor contact, wherein the third half-bridge comprises a fifth switching element and a sixth switching element. |
| US10090781B2 |
Piezoelectric motor assembly
A piezoelectric motor assembly for producing rotary motion, according to the present invention, has a motor frame and a circular body rotatably mounted on the motor frame having a diameter, a thickness, and a circumferential outer surface. At least two piezoelectric motors are mounted on the motor frame in tangential engagement with the outer surface of the circular body. The at least two piezoelectric motors are biased against the outer surface, resulting in an unbalanced net force on the circular body. |
| US10090780B2 |
Device with electrode connected to through wire, and method for manufacturing the same
A capacitive transducer includes a substrate having a first surface and a second surface opposite the first surface, the substrate including a through wire extending therethrough between the first surface and the second surface, and a cell on the first surface, the cell including a first electrode and a second electrode spaced apart from the first electrode with a gap between the first electrode and the second electrode. Conductive protective films are disposed over surfaces of the through wire on the first surface side and the second surface side of the substrate. |
| US10090772B2 |
Resonant power converters using impedance control networks and related techniques
An impedance control resonant power converter (converter) operated at a fixed switching frequency includes an impedance control network (ICN) coupled between two or more inverters operated at a fixed duty ratio with a phase shift between them and one or more rectifiers. The phase shift is used to control output power or compensate for variations in input or output voltage. The converter operates at fixed frequency yet achieves simultaneous zero voltage switching (ZVS) and zero or near zero current switching (ZCS) across a wide operating range. Output power may be controlled by: (1) changing phase shift between inverters; or (2) adjusting phase shift between inverters depending upon input and/or output voltages so that an admittance presented to the inverters is conductive and then turning the converter on and off at a frequency lower than the converter switching frequency to control output power below a value set by the phase shift. |
| US10090770B2 |
Isolated power converter with output voltage protection
An apparatus for delivering power to a load, which comprises an isolated power converter that converts input power on a primary side to output power and a supply voltage at a node on a secondary side. On the secondary side, a load switch is located on a current path to the load. A secondary-side control circuitry controls the load switch to operate in an ON mode in which current is provided to the load, and in response to a fault condition corresponding to an effective sudden disconnection of the supply voltage, switches the load switch into an OFF mode in which the current path to the load is blocked. |
| US10090769B2 |
Isolated high frequency DC/DC switching regulator
An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor. |
| US10090766B2 |
Reusing electromagnetic energy from a voltage converter downhole
A biasing circuit for a flyback converter can include a rectifier electrically coupled to an inductor of the flyback converter for generating a direct current signal from an alternating current signal outputted by the inductor in response to the inductor transferring an amount of energy to another inductor. The biasing circuit can also include a storage device electronically coupled to the rectifier to receive the direct current signal and store a charge. The biasing circuit can further include a limiting device electronically coupled to the storage device to provide an amount of the charge that is stored in the storage device to an input lead of a switch of the flyback converter for biasing the switch. |
| US10090762B2 |
Direct current (DC) voltage converter operation mode transition
A direct current (DC) voltage converter configured to transition between operation modes is disclosed. A voltage selection circuitry is provided in a DC voltage conversion circuit to control a buck-boost converter that generates a DC output voltage. As opposed to conventional methods of switching the buck-boost converter between a buck mode and a boost mode based on a single switching threshold, the voltage selection circuitry is configured to switch the buck-boost converter between the buck mode and the boost mode based on multiple voltage thresholds. Each of the multiple voltage thresholds defines a respective range for the DC output voltage. By controlling the buck-boost converter based on multiple voltage thresholds, it is possible to provide a smoother transition between the buck mode and the boost mode, thus reducing voltage errors in the DC output voltage and improving reliability of the DC voltage conversion circuit. |
| US10090758B1 |
Split reservoir capacitor architecture for a charge pump
Embodiments herein provide electronic devices that include a charge pump coupled to a split reservoir capacitor which includes at least two discrete capacitors. Further, the discrete capacitors are coupled together by a switch (e.g., a transistor) which is controlled by an output regulator. In one embodiment, the output regulator monitors an output voltage of the charge pump and the split reservoir capacitor to determine when the output differs from a predetermined target voltage. When the switch isolates the two capacitors, the charge pump can continue to add charge to a first one of the discrete capacitors. Thus, when the output regulator detects a dip in the output voltage and activates the switch to reconnect the two discrete capacitors, the first discrete capacitor has extra charge which can decrease the time needed to bring the output voltage back to the target voltage. |
| US10090755B2 |
Pre-bias startup of a converter
A method includes comparing, by a voltage-second (VS) controller, a first duty cycle used to control a first switch at a primary side of a power transformer of a DC-to-DC converter with a threshold. The method further includes if a value of the first duty cycle is less than the threshold, controlling, by the VS controller, a second duty cycle used to control a second switch at a secondary side of the power transformer, and maintaining a voltage level at an output voltage node at a non-zero value, and if the value of the first duty cycle is greater than the threshold, controlling, by an output voltage loop, the second duty cycle based on the first duty cycle, and monotonically increasing the voltage level the at the output voltage node from the non-zero value to a predetermined value. |
| US10090754B2 |
Photovoltaic inverter
Disclosed herein is a photovoltaic inverter that prevents degradation in the efficiency of photovoltaic generation by applying a reverse voltage of a DC voltage stored in a DC link capacitor to a solar cell array. The photovoltaic inverter includes: a DC link capacitor configured to store a DC voltage output from the solar cell array; a power conversion stage configured to generate an AC power by using the DC voltage stored in the DC link capacitor to transmit the generated AC power to a power system; and a controller configured to apply the DC voltage stored in the DC link capacitor to the power conversion stage or apply a reverse voltage of the DC voltage stored in the DC link capacitor to the solar cell array depending on whether a driving value of the solar cell array satisfies a predetermined driving condition. |
| US10090752B2 |
Power conversion device
A power conversion device has a main switch connected to a positive electrode side line of a battery, at least one semiconductor power element connected between the main switch and a negative electrode voltage line, and an auxiliary circuit having an auxiliary switch, a resonance reactor and an auxiliary diode connected parallel to the main switch. The device further has a voltage detection part which detects an external side voltage of the main switch and a control circuit part performing a switching control of the main switch and the auxiliary switch based on the detection result of the voltage detection part. During the turned-off state of the main switch, the control circuit part turns off the auxiliary switch before the external side voltage of the main switch reaches an input voltage of the main switch. This external side voltage starts to increase when the auxiliary switch is turned on. |
| US10090744B2 |
Vibration motor
A vibration motor is provided in the present disclosure. The vibration motor includes a housing providing an accommodating space, and a first vibration system and a second vibration system elastically suspended within the accommodating space. The first vibration system includes at least one permanent magnet, and the second vibration system includes at least one magnetic force generation part opposite to the permanent magnet. A magnetic field generated by the magnetic force generation part interacts with the permanent magnet to drive the first vibration system and the second vibration system to vibrate in the housing. |
| US10090732B2 |
Connecting structure for mechanical connection of a first housing with a second housing
The invention relates to a connecting structure for mechanical connection of a first housing with a second housing, whereby one face of the second housing has a hollow cylindrical recess for inserting the first housing; according to the invention it is provided that (i) the hollow cylindrical recess is formed of a ring-shaped collar, and (ii) for producing a frictional connection of the first housing with a second housing, the collar has at least one tensioning element, which in radial direction with respect to the collar is in active connection with the first housing. |
| US10090726B2 |
Motor and air-conditioning apparatus
The motor includes a motor body to rotate a shaft by generating a rotating magnetic field; a bearing supporting the shaft; and a bracket being electrically non-conductive, surrounding an outer periphery of the bearing, and supporting the bearing, wherein the bracket is not in contact with any member formed of conductive material at an outer periphery of the bracket. |
| US10090724B2 |
Stator for use in a dual-phased motor and a method for winding the stator
A stator for use in a dual-phased motor includes a magnetic yoke portion, a first magnetic pole, a second magnetic pole, a third magnetic pole and a fourth magnetic pole. The first, second, third and fourth magnetic poles are circumferentially arranged around and coupled with the magnetic yoke portion. Each of the first, second, third and fourth magnetic poles is wound with a coil having a first coil layer and a second coil layer. The first coil layer and the second coil layer of each of the first, second, third and fourth magnetic poles are in different phases. In other embodiments, several methods for winding a stator for use in a dual-phased motor are respectively proposed. |
| US10090711B2 |
Power transmission apparatus and power transmission method
A power transmission apparatus includes a primary coil connected to an AC source; a primary resonance coil configured to receive power from the primary coil; a secondary resonance coil configured to receive power from the primary resonance coil by magnetic field resonance occurred between the primary resonance coil and the secondary resonance coil; a secondary coil configured to receive power from the secondary resonance coil; a phase difference detector detect a phase difference between a phase of voltage supplied to the primary resonance coil and a phase of current flowing through the primary resonance coil; a variable capacitor provided on the primary resonance coil; and a determination part determining a coupling degree between the primary resonance coil and the secondary resonance coil based on a change degree of the phase difference relative to a change amount of capacitance when the capacitance of the variable capacitor changes. |
| US10090708B2 |
Inductive charging device
An inductive charging device, in particular a handheld power tool inductive charging device, having a housing, a receptacle region for accommodating an induction accumulator, a coil unit that includes at least one core element and at least one induction coil that at least partly encloses the at least one core element, and at least one coil housing element that positions at least the coil unit relative to the receptacle region in the housing. |
| US10090707B2 |
Wireless power transmission
A radio-frequency power transmitter. The radio-frequency power transmitter includes an array of patch antennas, an array of phase modulators, each phase modulator having an input port and associated with one or more of the patch antennas, a local oscillator that provides an oscillatory signal to the input port of each of the phase modulators, an array of amplifiers, each amplifier receiving an input from one of the phase modulators, and a microprocessor configured to interface with the array of phase modulators and control a holistic radiative power transmission vector pattern generated by the radio-frequency power transmitter. |
| US10090704B2 |
Display device and display method of electric power system information
A display device of electric power system information comprises a display unit including a display screen; and a screen display control unit for controlling the display unit. The display screen includes a display area that is divided into a plurality of display cells each of which has a mapping function for showing relative positional relations. The display unit includes an electric power system diagram display function unit for displaying an electric system diagram that embodies the state of an electric power system being a monitoring target, a mapping item display function unit for displaying mapping display items in the background of the electric power system diagram using the display cells, and a menu display function for displaying menus and icons, which are used for selecting the mapping display items, on the display screen, and for accepting selection operations to the menus and icons on the display cells on the display screen. The mapping display items represent information of state quantities regarding the state of the electric power system being the monitoring target, and the mapping display items are displayed per display cell with different colors in accordance with the corresponding values of state quantities. |
| US10090703B2 |
Converter module and switchgear assembly for AC and DC power distribution
A converter module for use in a switchgear assembly for power distribution, has: one or more AC supply bus bars for providing AC power supply; one or more AC or DC power distribution bus bars for distributing power to loads; and one or more converter units for converting AC power from the AC supply bus bars to AC or DC power onto AC or DC power distribution bus bars, respectively. |
| US10090701B2 |
Solar power generation system
A solar power generation system includes a plurality of solar cell groups, a plurality of chopper units each of which corresponds to one of the plurality of solar cell groups and raises a DC voltage obtained from the corresponding solar cell group. Each of the plurality of chopper units includes a first operating point control unit that respectively controls an output current of the corresponding chopper unit to optimize an operating point of each of the plurality of solar cell groups so as to obtain maximum power from the respective solar cell groups, and an inverter, which receives the DC voltage obtained from the plurality of chopper units and outputs AC power. The inverter includes a second operating point control unit that controls the DC voltage obtained from the plurality of chopper units to optimize the operating point of each of the plurality of solar cell groups. |
| US10090699B1 |
Wireless powered house
The present disclosure may provide a wireless power system which may be used to provide wireless power transmission while using pocket-forming. The wireless power system may be used in a house for providing power and charge to a plurality of mobile and non-mobile devices. The house may include a single base station that may be connected to several transmitters. The base station may manage operation of every transmitter in an independently manner or may operate them as a single transmitter. The connection between the base station and transmitters may be achieved through a plurality of techniques including wired connections and wireless connections. The base station may include at least one micro-controller and a power source. |
| US10090697B2 |
Wireless power transmitter, wireless power receiver, and control methods thereof
A wireless power transmitter configured to transmit a wireless power to a wireless power receiver and a method for controlling the wireless power transmitted from the wireless power transmitter are provided. The method includes applying a detection power for detecting a change in a load impedance of the wireless power transmitter caused by a placement of the wireless power receiver, detecting the change in the load impedance of the wireless power transmitter, receiving a first signal from the wireless power receiver, determining whether a reception intensity of the first signal is greater than a threshold, and transmitting a second signal to the wireless power receiver based on detecting the change in the load impedance and determining whether the reception intensity of the first signal is greater than the threshold. |
| US10090696B2 |
Wireless power transmitting unit, wireless power receiving unit, and control methods thereof
A control method of a wireless power receiving unit receiving charging power from a wireless power transmitting unit to perform wireless charging is provided. The control method includes receiving the charging power from the wireless power transmitting unit; detecting a change in a wireless charging environment; generating a signal indicating detection of the change in the wireless charging environment; and transmitting the signal indicating the detection of the change in the wireless charging environment to the wireless power transmitting unit. |
| US10090693B2 |
Method, system and device for controlling charging of batteries in electronic cigarettes
A system, a method, and a device for controlling charging of batteries in electronic articles, and more particularly for controlling charging of batteries in electronic cigarettes. In one embodiment, a charging system for an electronic cigarette can comprise a pack that can comprise a pack battery electrically coupled to an ultra-capacitor. The pack battery can be configured to charge the ultra-capacitor. The charging system can further comprise an electronic circuitry configured to temporarily or non-fixedly couple the pack to an electronic cigarette battery. The ultra-capacitor can be configured to charge the electronic cigarette battery at an accelerated rate as compared to a rate at which the pack battery alone can charge the electronic cigarette battery. |
| US10090689B2 |
Overcurrent protection circuit and method for limiting discharge current of battery within safety limiting value
An overcurrent protection circuit and method for battery discharge. The overcurrent protection circuit includes a discharge switch tube; a discharge control module which is used for detecting the discharge current of batteries in real time, and judging whether an overcurrent is generated by way of comparing the detected discharge current with a preset limiting value, the discharge control module controlling switch-on of the discharge switch tube if no overcurrent is generated, the discharge control module controlling switch-off of the discharge switch tube if an overcurrent is generated, and the discharge control module locking the discharge switch tube in a switch-off state when the overcurrent has timed out; and a time delay module which is used for judging whether the overcurrent has timed out by way of comparing the time when the overcurrent is generated with a preset delay time. |
| US10090685B2 |
Electricity providing system including battery energy storage system
Disclosed is a power supply system. A power supply system according to an embodiment includes a system control unit configured to set a first system droop curve for a plurality of batteries and a charging control unit configured to control charging/discharging of the plurality of batteries on the basis of the first system droop curve. |
| US10090683B2 |
Battery management system for controlling an energy storage assembly and method for charging and discharging an energy storage assembly
The invention relates to a battery management system for controlling an energy storage assembly, in particular for controlling the charging or discharging process of an energy storage device. The invention further relates to an energy storage assembly having a plurality of storage modules connected electrically in series, which energy storage assembly is controlled by an aforementioned battery management system. The invention further relates to a method for charging or discharging an aforementioned energy storage assembly. A battery management system (100) for controlling an energy storage assembly (10) is specified, which energy storage assembly comprises a plurality of storage modules (11, 12, 13, 14) connected electrically in series, wherein the battery management system (100) comprises: a measuring apparatus for measuring at least one value of a physical quantity of the storage modules (11, 12, 13, 14), a control apparatus (20), which controls a discharging current or charging current drawn from or supplied to the storage modules (11, 12, 13, 14) in dependence on the measured value of a physical quantity of at least one of the storage modules (11, 12, 13, 14), wherein the control apparatus (20) checks if a value of a physical quantity of one of the storage modules (11, 12, 13, 14) changes more quickly than the corresponding values of the physical quantity of the other storage modules (11, 12, 13, 14) of the energy storage assembly (10) or if a value of a physical quantity of one of the storage modules (11, 12, 13, 14) changes more quickly than a specified change value for the value. |
| US10090680B2 |
High accuracy mains filter monitoring for a multi-phase power system
Provided is an apparatus for delivering electrical power, in particular for delivering regeneratively produced electrical power, which has at least one converter and at least one filter for matching the delivery of power by the converter to a load impedance. Also provided is a method for operating the apparatus for delivering electrical power which allows improved monitoring of the functioning of the filters or mains filters and which uses means for determining at least one filter current in at least one filter, which means are designed in such a manner that said means make it possible to determine the at least one filter current during operation of the apparatus. Comparison means are provided and generate an error information signal using the desired value and actual value of the filter current and a predefinable error criterion. |
| US10090678B2 |
Production energy management system and computer program
A production energy management system is provided, including a production and energy flow model definer configured to define a production and energy flow model wherein the production and energy flow model represents, by directed lines, a flow with regard to an input and output of a production-related material between apparatuses disposed in a plant and a flow with regard to an input and output of energy and associates index values of the production-related material and the energy with a kind of metered data measured in the plant, a data collector configured to collect the metered data from the plant, and an energy calculator configured to perform an energy calculation for each apparatus based on the collected metered data and the defined production and energy flow model. |
| US10090677B2 |
Controlled device, control device, device control method, and device control system
A controlled device that is capable of executing a predetermined operation set in advance and is also capable of executing an instructed operation in accordance with a control instruction transmitted from a control device that performs power control for the consumer's facility. The controlled device includes a communicator configured to acquire a control instruction from the control device; and a controller configured to execute, when the control instruction has been acquired, the instructed operation in accordance with the control instruction, and to measure, each time the control instruction has been acquired, an elapsed time period that has passed since acquisition of the control instruction, wherein the controller executes the predetermined operation once the elapsed time period since the previous acquisition of the control instruction has reached a predetermined time period without additional acquisition of the control instruction. |
| US10090675B1 |
Fast settlement of supplement converter for power loss protection system
A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node. |
| US10090674B2 |
Maximum supply voltage selection
A method includes providing supply voltages to a supply voltage switching circuit that controls routing of the supply voltages to power consuming circuitry associated with the supply voltage switching circuit. The method includes comparing the supply voltages, including using at least one relatively lower precision comparator to compare the supply voltages for a relatively large difference between the supply voltages; and using at least one relatively higher precision comparator to compare the supply voltages for a relatively smaller difference between the supply voltages. The method further includes, based on a result of comparing the supply voltages, selectively coupling the supply voltages to at least one of an isolation well and a power supply rail of the supply voltage switching circuit. |
| US10090668B2 |
Bi-directional transmitter/receiver comprising temperature sensor and driving circuit comprising the same
A bi-directional transmitter/receiver according to an embodiment includes a pin connected with a main control circuit, a transistor connected with a first electrode to the pin, a Schmitt trigger which determines an output according to a voltage of the pin, and a temperature sensor which is connected to the pin and which senses temperature and outputs temperature information to the pin. A driving circuit for controlling switching operation of one or more switches includes a bi-directional transmitter/receiver. |
| US10090667B2 |
Radiation hardened DC-DC converter for operation at cryogenic temperatures
A radiation-hardened DC-DC converter capable of operating at cryogenic temperatures in high radiation environments. The radiation-hardened DC-DC converter can include an input side, the input side producing a high frequency AC voltage; a transformer; and an output side, the output side including a magnetic amplifier, wherein the pre-regulated high frequency AC voltage is fed to the magnetic amplifier through the transformer allowing the magnetic amplifier to provide a pulse width modulation function for voltage regulation. |
| US10090666B2 |
Circuit architectures for protecting against PoDL wire faults
In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed. |
| US10090663B2 |
Over-current protection circuit and method for voltage regulators
A voltage regulator includes a control circuit, a switch circuit, a first over-current protection circuit, and a second over-current protection circuit. The control circuit generates a pulse-width modulation (PWM) signal having a duty cycle proportional to an output voltage of the voltage regulator. The first over-current protection circuit blocks the PWM signal when an over-current condition exists during an off time of the PWM signal until a low-side switch current-sense level in the switch circuit drops below a set current limit level, while the second over-current protection circuit turns off the PWM signal when an over-current condition occurs during an on time of the PWM signal when a ramp adjusted voltage level added to the low-side switch current-sense level exceeds a summed level of the set current limit level and a set threshold. |
| US10090660B2 |
Wire pass through device
The embodiments herein provide a device for sealing an interface having an opening for a wire to pass through the interface. A pair of sealing blocks may be used where one block contains a protrusion and the opposing block contains a recess. The protrusion and recess preferably have an apex with a round having approximately the same dimension as the radius of the wire. A pair of posts may be positioned on opposing sides of the opening. One sealing block may contain an aperture for accepting one of the posts while the second sealing block may contain an aperture for accepting the opposing post. The posts may be threaded so that they can accept a threaded fastener. Exemplary embodiments may utilize mounting plates which may contain a flange such that squeezing the opposing flanges together can cause inward forces on the sealing blocks. |
| US10090659B2 |
Raintight fitting for jacketed metal clad cables
A raintight fitting has a fitting body including a plurality of first cable passageways configured to receive electrical cables. The first cable passageways converge into a second cable passageway, and the second cable passageway is configured to receive the conductors from plural cables received in the first cable passageways. A plurality of cable locks are each located at respective first cable passageways, are engageable with the cables received in the first cable passageways, and are configured to (i) secure the cables within the first cable passageways, and (ii) provide an electrically conductive path between the metallic covering of each cable and the fitting body. A raintight seal extends about the periphery of each first cable passageway, and is configured to form a raintight seal between (i) the fitting body and the electrical cables received within the first cable passageways and (ii) between the first cable passageways and ambient atmosphere. A raintight connector is connectable to a conduit for receiving conductors in the second cable passageway, and is configured to form a raintight seal between (i) the conduit and the fitting body and (ii) the second cable passageway and ambient atmosphere. |
| US10090658B2 |
Wall grommet for power connection
Provided is a wall grommet, which can be installed through the surfaces of walls to route wiring in the walls' interior spaces. In particular, the wall grommet is configured for running power cords inside walls and presenting the electrical connectors of a power cord in a manner such that power cords are hidden from view. The grommet may comprise a housing, which defines an interior space that is adapted to hold either the female connector or male connector of a power cord. The housing may be configured to enclose and secure the electrical connector of the power cord in the housing. |
| US10090653B2 |
Cable gland and method and apparatus for earthing a cable
A cable gland and method for earthing, bonding, and electromagnetic capability with armored, metal-clad, and metallic-sheathed cable types. The cable gland includes an adjustable earthing coil arranged internally in a gland body of the cable gland that secures around a cable inserted in the cable gland. When fully coiled, the adjustable earthing coil is relaxed and as the adjustable earthing coil is expanded it generates a restoring force. An earthing strap attached to the adjustable earthing coil in the cable gland, provides grounding capabilities to the cable gland. |
| US10090651B2 |
Mounting frame for a switchgear cabinet or a rack
A mounting frame for a switchgear cabinet or a rack includes mounting pieces which are arranged, as corner pieces, in the four corner sections of a rectangle or square that extends in an x-y plane, the mounting pieces being produced in a respective shaping process and having outer first and second mounting faces which extend in the x direction and in the y direction at a right angle thereto and which extend in a space direction z at a right angle to the x-y plane, and are provided with hollow spaces which are at least partially surrounded by wall parts and/or bores that are oriented in the z direction. The mounting frame further includes intermediate elements which extend between the mounting pieces in the x direction and in the y direction and the end sections of which are fastened to the mounting pieces. The mounting pieces have wall sections which extend in parallel to the x-y plane, thus making assembly easier. |
| US10090649B2 |
Spark plug having a powder capsule
The present disclosure relates to methods for producing spark plugs and/or spark plug components, and a capsule which may be used to produce a spark plug or spark plug component. The capsule may include a housing of a material which is unstable when heated a threshold temperature, and the capsule may further be filled with one or more powders, whereupon heating of the capsule of the housing may break down and the powders may be sintered or fused into a resistive body. The presently disclosed method may simplify and/or reduce the cost of producing spark plugs using known methods of inserting powdered precursor materials. |
| US10090648B1 |
Spark plug
A spark plug including a bottomed tubular insulator, a tubular metal shell, a conductive layer, and a terminal. The insulator extends along an axial line from a front end side to a rear end side and is closed at a front end. The metal shell has a ledge portion that projects radially inward and locks the insulator from the front end side. The metal shell holds the insulator from an outer peripheral side. The conductive layer covers at least a part of an inner peripheral surface of a portion of the insulator which is located on the front end side with respect to a locking portion locked by the ledge portion. The terminal is electrically connected to the conductive layer and is insulated from the metal shell. |
| US10090646B2 |
Spark plug
Disclosed is a spark plug capable of suppressing high-frequency noise by improving the material of an electrical connection part between a center electrode and a metal terminal within an axial hole of an insulator. A spark plug has an electrical connection part arranged in an axial hole of an insulator to establish electrical connection between a center electrode and a metal terminal. The electrical connection part includes a conductor having a first crystal phase formed of a Fe-containing oxide and a second crystal phase formed of a conductive metal oxide of perovskite crystal structure. |
| US10090643B2 |
Light-emitting device
A light-emitting device is provided. The light-emitting device comprises: an epitaxial structure comprising a first DBR stack, a light-emitting stack and a second DBR stack and a contact layer in sequence; an electrode on the epitaxial structure; a current blocking layer between the contact layer and the electrode; a first opening formed in the current blocking layer; and a second opening formed in the electrode and within the first opening; wherein a part of the electrode fills in the first opening and contacts the contact layer. |
| US10090639B2 |
Laser diode enhancement device
The subject invention includes a semiconductor laser with the laser having a DBR mirror on a substrate, a quantum well on the DBR mirror, and an interior CGH with a back propagated output for emitting a large sized Gaussian and encircling high energy. The DBR mirror has a plurality of GaAs/AlGaAs layers, while the quantum well is composed of AlGaAs/InGaAs. The CGH is composed of AlGaAs. |
| US10090635B2 |
Light module comprising a laser element
The invention relates to a light module including a semiconductor laser element emitting a laser beam in a first cone of light, a photoluminescent element, and an optical means for transforming the light coming from the photoluminescent element into an exit light beam. The optical means has a guiding portion arranged to guide at least a portion of the light emitted in the first cone of light into a second cone of light and a device for detection of incident light. The light module comprises a means of deviation designed to deviate the light of the second cone of light toward a third cone of light directed toward the detection device arranged outside of the second cone of light. |
| US10090634B1 |
Robust laser communications
A laser communication apparatus is provided for sending and receiving messages. A processor encodes user messages for a modulator. The modulator provides control signals related to the encoded message to a plurality of seed lasers. Each seed laser can provide light at a different wavelength. Amplifiers are joined to amplify light from the seed lasers. Amplified light is multiplexed together. Multiplexed light is transmitted by a collimating lens along a target vector. A portion of the light can be monitored by a first detector. A telescope receives light from the target vector and provides focused light to a second detector. The second detector provides a signal responsive to the received light to the processor. The processor decodes this signal to provide the received message. |
| US10090631B2 |
Cladding light stripper and method of manufacturing
A cladding stripper includes a plurality of transversal notches or grooves in the outer surface of an exposed inner cladding of a double clad optical fiber. Position and orientation of the notches can be selected to even out cladding light release along the cladding light stripper, enabling more even temperature distributions due to released cladding light. The notches on the optical fiber can be made with a laser ablation system. |
| US10090630B2 |
Laser ignition device provided with transmissive reflective film
A laser ignition device capable of achieving stable ignition, preventing deterioration of a semiconductor laser element is provided, by suppressing the intensity of oscillated light leakage leaking towards semiconductor laser side from the laser resonator with a simple configuration. A laser ignition device 7 includes an excitation light source 1 emitting coherent excitation light LPMP, an optical element 2 transmitting excitation light LPMP, a laser resonator 3 oscillating oscillated light having high energy density by being irradiated with excitation light LPMP, and condensing means 6 condensing the oscillated light LPLS oscillated by the laser resonator 3. Moreover, the laser ignition device 7 is provided with a light-transmissive-reflective film 5 disposed between the excitation light source 1 and the laser resonator 3. The light-transmissive-reflective film 5 permeating the excitation light LPMP having short wavelength and reflecting oscillated light leakage LLEAK having long wavelength. |
| US10090628B2 |
Cylinder, plasma apparatus, gas laser apparatus, and method of manufacturing cylinder
There is provided a cylinder including a first cylinder having an inner surface exposed; and a second cylinder joined to an outer surface of the first cylinder, the second cylinder containing alumina as a main component, the first cylinder containing yttrium-containing oxide as a main component. |
| US10090627B2 |
Filters for terminal crimping devices using ultrasonic signals
A terminal crimping device includes crimp tooling comprising an anvil and a ram movable toward the anvil with a crimp zone being defined between the anvil and the ram configured to receive a wire and a terminal configured to be crimped to the wire by the crimp tooling. An ultrasonic transmitting transducer is coupled to at least one of the anvil and the ram that transmits acoustic signals through the wire and terminal. A filter is provided on at least one of the anvil and the ram in the path of the acoustic signals that affects the acoustic signals. |
| US10090623B2 |
Enclosure assembly for a connector
An electromagnetic shielding structure for an electrical connector comprises a tubular hollow body and an inner housing. The tubular hollow body has a plurality of contact springs disposed in an annular orientation. The inner housing is disposed within the contact springs and protects the contact springs. |
| US10090621B2 |
Automatic gravity connector
A two sided electrical connection system that automatically connects two connector sides together is provided. A male side and female side of the connector have bodies shaped such that the male side may be received by the female side automatically by a force of gravity. Guiding structure around the female side of the two sided connector allows the male side to be guided into place without requiring perfect alignment of the two sides of the connector. |
| US10090616B1 |
Surgical instrument handle assembly with feature to clean electrical contacts at modular shaft interface
A powered surgical instrument includes a shaft assembly and a handle assembly. The shaft assembly includes a first electrical connector and a flexible element positioned adjacent to the first electrical connector. The handle assembly includes a second electrical connector. The handle assembly is configured to attach to the shaft assembly. The second electrical connector is configured to electrically connect with the first electrical connector when the handle assembly is attached to the shaft assembly. The flexible element is configured to create a liquid-resistant seal against the handle assembly and adjacent to the electrical connection of the first and second electrical connectors when the shaft assembly and the handle assembly are attached. |
| US10090614B2 |
Electrical connector having sealed snap-in locking cavity plugs
An electrical connector assembly includes male and female connector bodies formed with a plurality of terminal cavities in which electrical cables are disposed with the terminals secured against removal from the cavities by flexible lances engaging walls within the terminal cavities. A seal on the cables closes and seals the cavities in which they are installed. At least one of the cavities is unoccupied by a cable and is closed by a non-electrically conductive locking cavity plug. The locking cavity plug has a flexible lance that engages a wall within the unoccupied cavity in which it is installed to secure the plug against removal and carries a seal which engages and seals the unoccupied cavity. |
| US10090613B2 |
Connector device with improved connection reliability of terminal fittings
A connector device includes one or more terminal fittings connected to a wire, a plurality of connectors configured to be fitted into a mating connector by accommodating the one or more terminal fittings, and a holder for holding the plurality of connectors side by side, wherein the holder includes a wire cover portion surrounding the wire drawn out from the plurality of connectors, wherein the wire cover portion includes a contact piece for contacting the drawn wire to suppress a movement of the drawn wire. |
| US10090611B2 |
Cable, cable connection structure, and imaging apparatus
A cable includes: a core wire that is electrically conductive; a first inner insulation layer that covers an outer periphery of the core wire and has an exposing portion that exposes the core wire at a distal end side of the first inner insulation layer; and a first latching portion that is fixed to the core wire in the exposing portion, and is latched onto the first inner insulation layer and holds the core wire by coming into contact with the first inner insulation layer. |
| US10090610B2 |
Cable connector having a slider for compression
A coaxial cable connector is attachable to a coaxial cable. The connector may include a post, a connector body, a coupler, and a slider. The connector body may extend along an axis and include a forward end and a rearward end. The rearward end may be configured to receive a portion of a coaxial cable, and the connector body may be configured to receive at least a portion of the post. The coupler may be configured to be rotatably coupled to the post, and the slider may be configured to receive the connector body. The slider may be configured to move along the axis in a rearward direction from a first position to a second position and to compress a portion of the coaxial cable between the connector body and the post as a result of the slider being moved from the first position to the second position. |
| US10090607B2 |
Connection apparatus for cables
A connection apparatus for electrical cables is provided. In this case, the connection apparatus is intended to engage around a hose, wherein the connection apparatus is formed from two half-shells which are connected to one another in an articulated manner. In addition, at least one contact element, which is designed to make contact with the electrical cables, is arranged on the connection apparatus. The electrical cables can be connected to the contact elements by means of a pressure piece. As an alternative, the contact elements can be arranged such that, when the connection apparatus is locked, the contact elements are connected to the electrical cables at the same time. In this case, the electrical cables in the second half-shell can be arranged in conductor receptacles such that the contact elements on the first half shell enter the connection apparatus when said connection apparatus is closed. |
| US10090605B2 |
Active phased array antenna system with hierarchical modularized architecture
An active phased array antenna system with hierarchical modularized architecture is introduced, which includes an array antenna and a beamforming circuit. The array antenna includes a plurality of antenna units, number of which is N and which are arranged in array form. The beamforming circuit is for receiving a plurality of input signals and a plurality of phase control signals, and includes a hierarchical circuit structure based on phase shifters, for outputting a plurality of output signals based on the input signals according to phase values corresponding to the phase control signals and combinations of the phase values; the output signals are respectively coupled to the antenna units so as to generate a radiation pattern, wherein number of the phase control signals is T, T |
| US10090602B2 |
Waveguide feed for steerable beam antenna
A steerable beam antenna includes a rotatable drum having a diffraction grating surface, and a waveguide feed including first and second conductive metal bases extending axially along the length of the drum, each of the bases having an inner surface spaced from and opposed to the inner surface of the other base, and a proximal surface spaced from the drum surface by a gap. First and second parallel conductive metal plates extend distally from the first and second bases, respectively, the first and second plates having respective inner surfaces separated by an inter-plate space. First and second dielectric strips are flush-mounted on the inner surfaces of the first and second conductive metal bases, respectively, the first dielectric strip extending longitudinally along the inner surface of the first base, and the second dielectric strip extending longitudinally along the inner surface of the second base, opposite the first dielectric strip. |
| US10090598B2 |
Antenna module and method for mounting the same
An antenna module of the present invention is an antenna module 1 including a waveguide slot antenna (1A), a microstripline (1B), and an RFIC (16), the RFIC (16) being disposed to overlap a waveguide (123, 126) of the waveguide slot antenna (1A) as viewed in a stacking direction of layers. This provides an antenna module which can be mounted in a smaller area than a conventional antenna module. |
| US10090597B1 |
Mechanically reconfigurable dual-band slot antennas
In some embodiments, a mechanically reconfigurable slot antenna includes an electrically conductive layer having multiple slots, multiple electrically conductive parasitic patches, each patch associated with one of the slots, and a rack-and-pinion mechanism adapted to simultaneously linearly displace at least two of the patches along their associated slots. |
| US10090595B2 |
Broadband rectenna
A rectenna for high efficiency RF-to-DC wireless energy harvesting that includes an off-center-fed dipole antenna and a rectifying circuit, wherein the rectifying circuit comprises at least one rectifying diode. The input impedance of the antenna may be directly conjugate matched to the impedance of the rectifying circuit over a wide range of frequencies and/or under different operating conditions. The impedance matching network required by a conventional rectenna system may therefore be eliminated using the methods disclosed for the design and implementation of the rectenna. The rectenna offers consistently high RF-to-DC power conversion efficiency over a wide range of frequencies and under different operating conditions. The rectenna may be connectible to a rectifying circuit utilizing different types of rectifying diodes. |
| US10090594B2 |
Antenna system having structural configurations for assembly
Aspects of the subject disclosure may include, for example, an antenna array having a plurality of dielectric antennas and a plurality of dielectric cores. Each dielectric antenna of the plurality of dielectric antennas can have a structural configuration that enables flat surfaces of the plurality of dielectric antennas to be adjacent to each other. Each dielectric antenna of the plurality of dielectric antennas further includes an aperture for radiating a wireless signal in response to an electromagnetic wave received by each dielectric antenna. Each dielectric core of the plurality of dielectric cores can be coupled to a select one of the plurality of dielectric antennas to facilitate guiding a select one of a plurality of electromagnetic waves to the select one of the plurality of dielectric antennas. Other embodiments are disclosed. |
| US10090586B2 |
Wireless communication device with joined semiconductors
A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor. |
| US10090585B2 |
Circuits and methods for antenna-based self-interference cancellation
Circuits and methods for antenna-based self-interference cancellation are provided. In some embodiments, circuits for antenna-based self-interference cancellation are provided, the circuits comprising: a transmit antenna having a transmit port that receives a transmit signal; a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port. |
| US10090582B2 |
Vehicle attached component, and on-board antenna
The purpose of the present invention is to enable a secure attachment of an antenna element and to facilitate adjustment of the antenna element characteristics. Rearward of a spoiler are formed a plurality of lateral grooves extending in a left-right direction of a vehicle, and a plurality of vertical grooves extending in a front-rear direction of the vehicle. The plurality of lateral grooves and the plurality of vertical grooves form latticed grooves as grooves in the shape of a lattice for installing an antenna element. The antenna element is formed by a conductive wire. One end of the antenna element is connected to an amplifier, and the other end is opened. The antenna element extends from the amplifier via a power feeding groove and the right-end one of the vertical grooves to the rear end of the groove, from which the antenna element is fitted in a route along the most rearward one of the lateral grooves to the vicinity of the left-end one of the vertical grooves, thus being securely attached to the spoiler. |
| US10090578B2 |
Radiation-redirecting external case for portable communication device
An external case is configured to attach to a wireless device that has an antenna and a case separate from the external case. The external case has a first case portion and a second case portion. The second case portion is moveably attached to the first case portion and is moveable between a first position corresponding to the external case being closed and a second position corresponding to the external case being open. Additionally, the second case portion has an antenna system. The antenna system is parasitically coupled to the antenna of the wireless device. The antenna system receives from and sends to free space when the wireless device is operational, when the external case is attached to the wireless device, and when the second case portion is in the first position and in the second position. |
| US10090577B2 |
Data communication device
According to one embodiment, a data communication device includes a housing and an antenna. The housing includes a base formed of a carbon material and circumferential edges continuous with edges of the base and formed of a resin material. The antenna is accommodated in the housing and includes a conductive portion grounded via the base and an element portion arranged further away from the base than the conductive portion. |
| US10090575B2 |
Method of manufacturing a waveguide assembly by adhesively bonding two waveguide units and a waveguide structure formed therefrom
The present invention provides a method of manufacturing a waveguide assembly and a structure thereof, wherein the manufacturing method comprises the steps of: providing at least two waveguide units and combining the waveguide units, wherein each waveguide unit has at least one bonding portion formed at a position where each two said waveguide units are combined; and at least one adhesive is applied to the bonding portion to combine the waveguide units into the waveguide assembly. With the practice of the present invention, many advanced functions such as rapid design, rapid manufacture, rapid verification and cost reduction can be achieved. |
| US10090569B2 |
Thermal battery for heating vehicles
A system and a method for heating a component of an electric vehicle may be particularly beneficial in cold weather places and/or during winter time. The vehicle may be primarily powered by a main battery. The system may include a supplementary battery being metal-air battery including an electrolyte, for extending the driving range of the electric vehicle and a reservoir tank for holding an electrolyte volume for the metal-air battery, the electrolyte may be heated to a desired temperature. The system may further include a heat exchanger for conveying heat from the electrolyte volume, said heat is conveyable to said passenger's cabin. |
| US10090567B2 |
Vehicular battery charger, charging system, and method
A vehicle battery charger and a vehicle battery charging system are described and illustrated, and can include a controller enabling a user to enter a time of day at which the vehicle battery charger or system begins and/or ends charging of the vehicle battery. The vehicle battery charger can be separate from the vehicle, can be at least partially integrated into the vehicle, can include a transmitter and/or a receiver capable of communication with a controller that is remote from the vehicle and vehicle charger, and can be controlled by a user or another party (e.g., a power utility) to control battery charging based upon a time of day, cost of power, or other factors. |
| US10090563B2 |
Rechargeable lithium battery and method of preparing same
A rechargeable lithium battery and a method of preparing the same are described. The rechargeable lithium battery includes a positive electrode including a positive active material; a negative electrode including a negative active material; and a liquid electrolyte including a lithium salt and a non-aqueous organic solvent. A separator is interposed between the negative electrode and positive electrode and includes a support. A fluoro-based polymer layer is positioned on both sides of the support. The positive electrode includes the positive active material in an amount from about 30 to about 70 mg/cm2. |
| US10090562B2 |
Thin film lithium ion battery
A method for forming a thin film lithium ion battery includes, under a same vacuum seal, forming a stack of layers on a substrate including an anode layer, an electrolyte, a cathode layer and a first cap over the stack of layers to protect the layers from air. Under a same vacuum seal, the stack of layers is etched with a non-reactive etch process in accordance with a hardmask, and a second cap layer is formed over the stack of layers without breaking the vacuum seal. Contacts coupled to the cathode and the anode are formed. |
| US10090557B2 |
Solid-state multi-layer electrolyte, electrochemical cell and battery including the electrolyte, and method of forming same
An electrochemical cell including a multi-layer solid-state electrolyte, a battery including the cell, and a method of forming the battery and cell are disclosed. The electrolyte includes a first layer that is compatible with the anode of the cell and a second layer that is compatible with the cathode of the cell. The cell exhibits improved performance compared to cells including a single-layer electrolyte. |
| US10090556B2 |
Flexible battery, manufacturing method therefor, and auxiliary battery comprising flexible battery
Provided is a flexible battery. A flexible battery according to an exemplary embodiment of the present invention includes: an electrode assembly; and an exterior material in which the electrode assembly is encapsulated together with an electrolyte, in which the electrode assembly and the exterior material are formed such that patterns for contraction and extension in a longitudinal direction have the same directionality when the flexible battery is bent. As such, the patterns for contraction and extension in the longitudinal direction are formed on both of the exterior material and the electrode assembly, thereby preventing or minimizing deterioration in the required physical properties even though the flexible battery is bent. |
| US10090554B2 |
Non-aqueous electrolyte storage element
Non-aqueous electrolyte storage element including; positive electrode including positive electrode material layer, which contains positive electrode active material capable of reversibly accumulating and releasing anions; negative electrode including negative electrode material layer, which contains negative electrode active material capable of reversibly accumulating and releasing cations; separator disposed between the positive electrode and the negative electrode; and non-aqueous electrolyte containing electrolyte salt, the non-aqueous electrolyte storage element satisfying formulae: 0.5≤[(V1+V2+V3)/V4]≤0.61; and 0.14≤P1/P2≤0.84, where V1 is volume of pores of the positive electrode material layer per unit area of the positive electrode, V2 is volume of pores of the negative electrode material layer per unit area of the negative electrode, V3 is volume of pores per unit area of the separator, and V4 is total volume of the non-aqueous electrolyte storage element, and P1 is porosity of the positive electrode material layer, and P2 is porosity of the separator. |
| US10090553B2 |
Electrode assembly and method of manufacturing the same
An electrode assembly includes a cell stack part having (a) a structure in which one kind of radical unit is repeatedly disposed, or (b) a structure in which at least two kinds of radical units are disposed in a predetermined order, the one kind or the at least two kinds of radical units having same number of electrodes and separators alternately disposed. The one kind of radical unit has four-layered structure in which first electrode, first separator, second electrode and second separator are sequentially stacked or repeating structure of the four-layered structure. Each of the at least two kinds of radical units are stacked by ones to form the four-layered structure or the repeating structure. An outer separator that is a separator among separators of a radical unit positioned at the outermost part of the cell stack part is extended from a side of the cell stack part. |
| US10090552B2 |
Liquid fuel battery
A liquid fuel battery is described, having a vented case, an internal fuel chamber, and a plurality of substantially planar vertically stacked battery elements having separated fuel-sides and air sides. Such sides are separated by a series of anodic and cathodic seals. In one embodiment, a cathode contains doped carbon nanofibers and may be treated with polytetrafluoroethylene or another hydrophobic material. An anode current collector and/or cathode current collector may contain perforated metal, including metal mesh. Battery elements may be U-shaped to maximize the efficiency of the air-fuel interaction. The cathode is active for oxygen reduction and inactive for fuel oxidation. |
| US10090551B2 |
Structure for mounting fuel cell stack
A structure for mounting a fuel cell stack in an enclosure or a frame includes a first mounting mechanism for fastening and mounting a first mounting part located at a first side of the fuel cell stack in a longitudinal direction of the stack, which is a cell stacking direction, to the enclosure or the frame in a completely fixing fashion, and a second mounting mechanism for mounting a second mounting part located at a second side of the fuel cell stack in the longitudinal direction of the stack to the enclosure or the frame in a state of being movable in the longitudinal direction of the stack. |
| US10090548B2 |
Fuel cell system
A fuel cell system includes a desulfurizer that removes a sulfur compound in a raw material, a fuel cell unit that performs electric-power generation using fuel obtained by reforming a raw material from which the sulfur compound is removed and electric-power generation air supplied, a combustion exhaust gas passage through which combustion exhaust gas generated by combusting fuel not utilized for the electric-power generation in the fuel cell unit is emitted, a combustion exhaust gas container that is connected to the combustion exhaust gas passage and accommodates the desulfurizer inside the combustion exhaust gas container, a purifier that removes carbon monoxide included in the combustion exhaust gas, and an air heat exchanger that performs heat exchange of the combustion exhaust gas and the electric-power generation air supplied to the fuel cell unit. |
| US10090546B2 |
Method for activating fuel cell stack without using electric load
A method for activating a fuel cell stack without using an electric load includes chemically adsorbing hydrogen into a catalyst of a cathode. Oxygen remaining in the stack is removed to seal and store the fuel cell stack while maintaining a negative pressure in the fuel cell stack. The method for activating a fuel cell stack does not require an electric load device, and therefore does not increase the number of activation equipment, thereby preventing the total production speed of the fuel cell stack from reducing in response to the stack activation. |
| US10090545B2 |
Structure of fuel cell system and controlling method thereof
A structure of a fuel cell system and a controlling method thereof are provided. The structure of the fuel cell system includes a flow sensor that is configured to detect a flow of air introduced into the fuel cell system and an air compressor that is configured to compress the introduced air and has an air foil bearing to maintain minimum driving revolutions per minute or greater. Additionally, the system includes a flow adjuster that is connected to the fuel cell system. Accordingly, since an amount of air corresponding to a required amount of air of the fuel cell system is supplied by limiting or recirculating an excessive air supply while securing durability and durability of abrasion of the air compressor to which the air foil bearing is applied, a dry phenomenon of the fuel cell system including a stack due to the excessive supply of air is prevented. |
| US10090543B2 |
Fuel cell and control method for the same
A fuel cell includes: a stack having a manifold in which a fluid flows and having a plurality of flowing spaces which communicate with the manifold through openings; a shielding part having a plurality of shielding strips arranged in a stacked direction of the stack and selectively moving along the manifold to shield at least some of the plurality of flowing spaces; and a driver coupled with the shielding part to move the shielding part. |
| US10090542B2 |
Method of compressing fuel cell electrodes, resultant fuel cell, and a housing for the fuel cell which utilizes electrolyte reservoirs
An electrode element and fuel cell and a new method of manufacturing a fuel cell, particularly for use in a breath alcohol detector. This new element includes a reservoir for extra electrolyte that can allow near perfect capillary action to keep the electrode substrate full of electrolyte for long periods of time, increasing its useful life, especially under harsh conditions. Further, the capillary action need not work through a layer of electrode and can be integrally formed with the electrode element to eliminate or reduce loss due to connective surfaces. Wire connections and arrangements are generally of no concern in this design as the reservoirs for electrolyte connect directly to the substrate and electrolyte does not need to pass through an electrode. |
| US10090537B2 |
Seal plate and fuel cell stack using the same
A fuel cell stack includes at least two cell modules adjacent to each other, the at least two cell modules each being formed by stacking a plurality of fuel cells into an integrated unit and a seal plate interposed in a cooling flow channel defined between separators of the at least two cell modules, the cooling flow channel configured to allow a cooling fluid to flow therethrough. The seal plate includes a manifold portion in which a plurality of manifold holes are formed to allow two power-generation gases to flow separately through the plurality of manifold holes and through the plurality of fuel cells and a seal member provided along a peripheral portion of each of the plurality of manifold holes to provide sealing for a corresponding one of the two power-generation gases flowing through the manifold hole. |
| US10090525B2 |
Positive-electrode materials: methods for their preparation and use in lithium secondary batteries
A positive-electrode material for a lithium secondary battery. The material includes a lithium oxide compound or a complex oxide as reactive substance. The material also includes at least one type of carbon material, and optionally a binder. A first type of carbon material is provided as a coating on the reactive substance particles surface. A second type of carbon material is carbon black. And a third type of carbon material is a fibrous carbon material provided as a mixture of at least two types of fibrous carbon material different in fiber diameter and/or fiber length. Also, a method for preparing the material as well as lithium secondary batteries including the material. |
| US10090524B2 |
Lithium titanium sulfide, lithium niobium sulfide, and lithium titanium niobium sulfide
The present invention provides a novel lithium titanium sulfide, lithium niobium sulfide, or lithium titanium niobium sulfide that contains a sulfide containing lithium, titanium and/or niobium, and sulfur as constituent elements, and that has excellent charge-discharge performance (especially excellent charge-discharge capacity and charge-discharge potential) useful as a cathode active material or the like for lithium batteries, such as metal lithium secondary batteries or lithium-ion secondary batteries. Particularly preferred are, for example, (1) lithium titanium sulfide containing lithium, titanium, and sulfur as constituent elements and having a cubic rock salt crystal structure, (2) lithium niobium sulfide containing lithium, niobium, and sulfur as constituent elements and having a diffraction peak at a specific position in an X-ray diffractogram, and (3) lithium titanium niobium sulfide containing lithium, titanium, niobium, and sulfur as constituent elements and having a diffraction peak at a specific position in an X-ray diffractogram. |
| US10090518B2 |
Sulfate containing rechargeable battery cathode with oxidized surface
A method for preparing a positive electrode material for a rechargeable lithium battery, comprising the steps of: —providing a Li metal (M) oxide electroactive material, —providing an inorganic oxidizing chemical compound, —providing a chemical that is a Li-acceptor, —mixing the Li metal (M) oxide, the oxidizing compound and the Li-acceptor, and —heating the mixture at a temperature between 200 and 800° C. in an oxygen comprising atmosphere. In an embodiment the positive electrode material comprises a Li metal (M) oxide electroactive material, and between 0.15 and 5 wt % of a LiNaS04 secondary phase. The Li metal oxide may have the general formula Li1+a′M1−aO2, with a′ |
| US10090517B2 |
Cathode material for lithium-ion secondary battery, cathode for lithium-ion secondary battery, and lithium-ion secondary battery
A cathode material for a lithium-ion secondary battery includes a cathode material A which includes central particles of a cathode active material represented by LixAyMzPO4 and a carbonaceous film with which surfaces of the central particles are coated and a cathode material B which is represented by LixAyMzPO4 and is made of primary particles of a cathode active material having an olivine structure. |
| US10090516B2 |
Electrode material and method of synthesizing
The present disclosure provides a phosphate framework electrode material for sodium ion battery and a method for synthesizing such electrode material. A surfactant and precursors including a sodium precursor, a phosphate precursor, a transition metal precursor are dissolved in a solvent and stirred for sufficient mixing and reaction. The precursors are reacted to yield a precipitate of particles of NaxAbMy(PO4)zXn compound and with the surfactant attached to the particles. The solvent is then removed and the remaining precipitate is sintered to crystallize the particles. During sintering, the surfactant is decomposed to form a carbon network between the crystallized particles and the crystallized particles and the carbon matrix are integrated to form the electrode material. |
| US10090515B2 |
Bipolar hybrid energy storage device
Apparatus and techniques are described herein for providing a plate such as can be included as a portion of a hybrid energy storage device assembly. A hybrid device can include capacitor and battery structures, such as can include a sealed stack of hybrid bipolar plates comprising silicon wafers. |
| US10090513B2 |
Method of forming silicon
A method of forming a particulate material comprising silicon, the method comprising the step of reducing a particulate starting material comprising silica-containing particles having an aspect ratio of at least 3:1 and a smallest dimension of less than 15 microns, or reducing a particulate starting material comprising silica-containing particles comprising a plurality of elongate structural elements, each elongate structural element having an aspect ratio of at least 3:1 and a smallest dimension of less than 15 microns. |
| US10090512B2 |
Electrode including nanostructures for rechargeable cells
A lithium ion battery electrode includes silicon nanowires used for insertion of lithium ions and including a conductivity enhancement, the nanowires growth-rooted to the conductive substrate. |
| US10090510B2 |
Non-aqueous electrolyte secondary battery
An object is to improve the safety of a non-aqueous electrolyte secondary battery at the time of the internal short circuit. The non-aqueous electrolyte secondary battery includes a positive electrode, a negative electrode, and a separator interposed between the positive electrode and the negative electrode. The positive electrode includes a current collector and a positive electrode active material layer formed on the current collector. The current collector includes a metal foil having a roughened surface. The negative electrode includes a silicon-containing negative electrode active material. The metal foil is preferably a metal foil containing aluminum. The metal foil preferably has a surface roughness Ra of 0.1 to 2.0 μm. |
| US10090506B2 |
Rechargeable battery
A rechargeable battery includes: an electrode assembly including a first electrode and a second electrode; an electrode terminal configured to be electrically coupled to the electrode assembly; a case configured to accommodate the electrode assembly; and a cap plate mounted at an opening of the case, the cap plate having a terminal hole. The electrode terminal includes: a first terminal at the terminal hole of the cap plate and configured to be electrically coupled to the electrode assembly; a second terminal at an exterior side of the cap plate and configured to be electrically coupled to the first terminal such that the first terminal is exposed to an exterior of the case; and a third terminal on the second terminal and configured to be elastically deformable and electrically coupled to the first terminal through the second terminal. |
| US10090504B2 |
Non-uniform battery cell
An apparatus is provided that includes a two or more cell elements stacked internally to create a single cell with a non-uniform height. A first bus bar may electrically couple to a first side or first end of the cell elements in order to connect the terminals of the battery elements. A second bus bar may electrically couple to a second side or second end of the cell elements in order to connect the terminals of the battery elements. |
| US10090503B2 |
Connecting member of electrode terminals for preparation of core pack
Disclosed herein is an electrode terminal connecting member to connect two or more battery cells in series and/or in parallel to each other so as to manufacture a battery cell core pack, wherein the electrode terminal connecting member includes a plate body having a size sufficient to connect electrode terminals of the battery cells arranged in at least 2×2 matrix to each other, and the electrode terminals of the battery cells are directly coupled to the plate body in a state in which the plate body is not bent. |
| US10090498B2 |
Modular battery pack apparatus, systems, and methods including viral data and/or code transfer
Intelligent modular battery pack assemblies and associated charging and docking systems are disclosed. In one embodiment a modular battery pack assembly may include an outer casing assembly, a thermally conductive structural housing element configured to house a battery assembly in an interior volume, a lid element configured to cover the opening in the thermally conductive structural housing element and mechanically strengthen the thermally conductive structural housing element, and a circuit element disposed to electrically couple the battery cell to a battery-powered device and provide viral data transfer between the battery and a coupled device. |
| US10090496B2 |
Battery used for unmanned aerial vehicle and an unmanned aerial vehicle
The present invention discloses an unmanned aerial vehicle and a battery thereof. The battery includes a battery body and a shell disposed on one end of the battery body. The shell has a clamp button disposed on the side opposite the unmanned aerial vehicle. One end of the clamp button is fixed on the shell and the other is used for detachably connecting with the unmanned aerial vehicle. The clamp button makes the battery detachably connect with the main body of the unmanned aerial vehicle be possible and it is very convenient for changing the battery. |
| US10090494B2 |
Support structure for battery cells within a traction battery assembly
A traction battery assembly may include an array of battery cells having opposing end faces, opposing side faces, and a bottom face. The assembly may also include a pair of end plates and a pair of side plates arranged to form a four-sided enclosure around the end and side faces and configured to compress and retain the cells without being mechanically attached thereto or covering the bottom face. The side plates may partially cover an upper portion of the array. The side plates may have a lower horizontal edge, an upper horizontal edge, and at least one diagonal reinforcement rib configured to extend from a location where the vertical edge and lower horizontal edge meet upward to the upper horizontal edge. |
| US10090492B2 |
Battery cell with safety improved using inert particles
Disclosed herein is a battery cell having an electrode assembly mounted in a variable cell case in a state in which the electrode assembly is impregnated with an electrolyte, the battery cell being configured to be flexibly deformed in response to the shape of a device, in which the battery cell is mounted, wherein an uppermost end electrode and/or a lowermost end electrode of the electrode assembly in the direction in which electrodes are stacked is provided on an electrode current collector thereof, facing the inner surface of the cell case, with an electrode mixture including inert particles, 10 to 100% of the inert particles being distributed on the surface of the electrode mixture such that a concave-convex structure is formed in the surface of the electrode mixture in vertical section. |
| US10090487B2 |
Thin film packaging structure, method for fabrication thereof and display device
Embodiments of the disclosure provide a thin film packaging structure including a flexible thin film used for packaging a light-emitting display device, wherein the flexible thin film includes at least two layers of organic film layer, at least one layer of inorganic film layer and a light extraction film layer, each layer of the inorganic film layer is located between the two layers of the organic film layer, the light extraction film layer is located between the two layers of organic film layer or located on the outer surface of the outermost layer of the organic film layer, and the light extraction film layer includes a plurality of microstructures with the function of light extraction. The thin film packaging structure provided by embodiments of the disclosure can improve the luminous efficiency of the organic light-emitting display device packaged by the thin film packaging structure. |
| US10090483B2 |
Organic light-emitting device
An organic light-emitting device is provided, including: a first electrode; a second electrode; and an organic layer between the first electrode and the second electrode, wherein the organic layer includes an emission layer; the emission layer includes a first compound, a second compound, a third compound, and a fourth compound; and a lowest excited triplet energy level (HT1) of the first compound, a lowest excited triplet energy level (DFDT1) of the third compound, and a lowest excited triplet energy level (FDT1) of the fourth compound satisfy Inequation 1: HT1>DFDT1>FDT1. |
| US10090482B2 |
Transistors
This invention comprises a field effect transistor which comprises source and drain electrodes (01) which are bridged by a semiconductor which comprises semiconducting crystallites, the conductivity of the semiconductor being controlled by a gate electrode (02) which is insulated from the semiconductor and the source and drain electrodes, to which a potential is applied for controlling the conductivity of the semiconductor, in which at least part of the facing surfaces of the source and drain electrodes are geometrically formed such that they provide current flow of different directions between the electrodes through the said channel. By this means current is caused to flow through more orientations of the crystals resulting in greater uniformity of performance between different transistors when there is a degree of variable crystallographic orientation. |
| US10090479B2 |
Stretchable/foldable optoelectronic device, method of manufacturing the same, and apparatus including the stretchable/foldable optoelectronic device
Provided are a stretchable and/or foldable optoelectronic device, a method of manufacturing the same, and an apparatus including the stretchable and/or foldable optoelectronic device. A stretchable and/or foldable optoelectronic device may include an optoelectronic device portion on a substrate. The substrate may include an elastomeric polymer and may be stretchable. The optoelectronic device portion may be configured to have a wavy structure to be stretchable. The optoelectronic device portion may include a graphene layer and a quantum dot (QD)-containing layer. The stretchable and/or foldable optoelectronic device may further include a capping layer that includes an elastomeric polymer and is on the optoelectronic device portion. The stretchable and/or foldable optoelectronic device may further include a plastic material layer that contacts at least one surface of the optoelectronic device portion. |
| US10090478B2 |
Flexible organic light emitting diode display
The organic light emitting diode display may comprise a cover window including a display region and a non-display region that surrounds the display region; a flexible substrate arranged on a lower portion of the cover window, and including a first region that is spaced apart from the cover window and a second region that extends from the first region toward the cover window; and an adhesive layer arranged between the cover window and the flexible substrate to make the cover window and the flexible substrate adhere to each other. |
| US10090476B2 |
Metal complexes comprising diazabenzmidazolocarbene ligands and the use thereof in OLEDs
The present invention relates to metal-carbene complexes comprising a central atom selected from iridium and platinum, and diazabenzimidazolocarbene ligands, to organic light diodes which comprise such complexes, to light-emitting layers comprising at least one such metal-carbene complex, to a device selected from the group comprising illuminating elements, stationary visual display units and mobile visual display units comprising such an OLED and to the use of such a metal-carbene complex in OLEDs, for example as emitter, matrix material, charge transport material and/or charge or exciton blocker. |
| US10090470B2 |
Semiconductor film and method of forming the same
A method of forming a semiconductor film at pressure between 10−5 atm and 10 atm in the presence of a substrate includes (i) providing a precursor material in a reaction container; (ii) arranging the substrate on the reaction container such that a conductive surface of the substrate is facing towards the precursor material; and (iii) conducting a heat treatment to deposit a semiconductor layer on the conductive surface of the substrate. A semiconductor film is obtained from this method and a device comprising such semiconductor film is also provided. |
| US10090468B2 |
Photoelectric conversion element and method for manufacturing the same
According to one embodiment, a photoelectric conversion element includes a first electrode, a second electrode, a photoelectric conversion layer and a first layer. The photoelectric conversion layer is provided between the first electrode and the second electrode. The first layer is provided between the first electrode and the photoelectric conversion layer. The first layer includes at least a first metal oxide. The first layer has a plurality of orientation planes. At least one of the orientation planes satisfies the relationship L1>L2, where L1 is a length of the one of the plurality of orientation planes, and L2 is a thickness of the first layer along a first direction. The first direction is from the first electrode toward the second electrode. |
| US10090466B2 |
Far-infrared detection using Weyl semimetals
The generation of photocurrent in an ideal two-dimensional Dirac spectrum is symmetry forbidden. In sharp contrast, a three-dimensional Weyl semimetal can generically support significant photocurrent due to the combination of inversion symmetry breaking and finite tilts of the Weyl spectrum. To realize this photocurrent, a noncentrosymmetric Weyl semimetal is coupled to a pair of electrodes and illuminated with circularly polarized light without any voltage applied to the Weyl semimetal. The wavelength of the incident light can range over tens of microns and can be adjusted by doping the Weyl semimetal to change its chemical potential. |
| US10090462B2 |
Resistive memory devices
Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed. |
| US10090461B2 |
Oxide-based three-terminal resistive switching logic devices
Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions. |
| US10090450B2 |
Light emitting device
A light emitting device in which a bonding pad is soldered to a mounting substrate, wherein the bonding pad may be formed in various shapes that can minimize the occurrence of voids during soldering or heat fusion. |
| US10090448B2 |
Light-emitting module, light-emitting device and method of making light-emitting module
A light-emitting module is provided with a light-emitting element, a base, and a wiring pattern. The base includes an installation surface facing in a first direction and a mounting surface facing in a second direction which is at right angles to the first direction. The light-emitting element is installed on the installation surface. The wiring pattern is formed on the base and is in electrical contact with the light-emitting element. The base includes a pair of mounting recesses recessed from the mounting surface and spaced from each other in a third direction which is at right angles to both the first direction and the second direction. The wiring pattern includes a pair of mounting-surface electrodes respectively covering at least a part of the pair of mounting recesses. |
| US10090444B2 |
Wavelength converted light emitting device with small source size
A lighting structure according to embodiments of the invention includes a semiconductor light emitting device and a flat wavelength converting element attached to the semiconductor light emitting device. The flat wavelength converting element includes a wavelength converting layer for absorbing light emitted by the semiconductor light emitting device and emitting light of a different wavelength. The flat wavelength converting element further includes a transparent layer. The wavelength converting layer is formed on the transparent layer. |
| US10090441B2 |
Light emitting device
A light emitting device includes a base including a support having a support surface. The light emitting element has a first surface and a second surface opposite to the first surface. The light emitting element is mounted on the base. The first surface faces the support surface. The reflecting film is provided on the second surface of the light emitting element. The light-transmissive covering member is provided on the base on a side of the support surface to cover the light emitting element and a covered region of the base except for an uncovered region of the base. An average reflectivity in the uncovered region of the base with respect to a peak emission wavelength of light emitted from the light emitting element is higher than an average reflectivity in the covered region of the base with respect to the peak emission wavelength of light. |
| US10090439B2 |
Light emitting device, light emitting device package, and light unit
Disclosed are a light emitting device, a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer comprising a barrier layer which is disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and which has an un-doped area and a doped area with dopants. |
| US10090438B2 |
Opto-electronic device with two-dimensional injection layers
An opto-electronic device with two-dimensional injection layers is described. The device can include a semiconductor structure with a semiconductor layer having one of an n-type semiconductor layer or a p-type semiconductor layer, and a light generating structure formed on the semiconductor layer. A set of tilted semiconductor heterostructures is formed over the semiconductor structure. Each tilted semiconductor heterostructure includes a core region, a set of shell regions adjoining a sidewall of the core region, and a pair of two-dimensional carrier accumulation (2DCA) layers. Each 2DCA layer is formed at a heterointerface between one of the sidewalls of the core region and one of the shell regions. The sidewalls of the core region, the shell regions, and the 2DCA layers each having a sloping surface, wherein each 2DCA layer forms an angle with a surface of the semiconductor structure. |
| US10090435B2 |
III-nitride light emitting device including porous semiconductor
A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire. |
| US10090434B2 |
Illumination device having dual-emitting light emitting diode (LED) die structures
An illumination device has a dual-emitting LED die structure in which a first p-n diode structure emits primary light having a peak at a first wavelength, and a second p-n diode structure emits primary light having a peak at a second wavelength that is longer than the first wavelength. A phosphor medium is positioned to be stimulated by the primary light of the dual-emitting LED die structure, and in response emits secondary, wavelength converted light, thereby contributing to a combined white illumination. Other embodiments are also described and claimed. |
| US10090432B2 |
Photoactive devices having low bandgap active layers configured for improved efficiency and related methods
Photoactive devices include an active region disposed between first and second electrodes and configured to absorb radiation and generate a voltage between the electrodes. The active region includes an active layer comprising a semiconductor material exhibiting a relatively low bandgap. The active layer has a front surface through which radiation enters the active layer and a relatively rougher back surface on an opposing side of the active layer. Methods of fabricating photoactive devices include the formation of such an active region and electrodes. |
| US10090429B2 |
Integrated on chip detector and zero waveguide module structure for use in DNA sequencing
A semiconductor structure for use in single molecule real time DNA sequencing technology is provided. The structure includes a semiconductor substrate including a first region and an adjoining second region. A photodetector is present in the first region and a plurality of semiconductor devices is present in the second region. A contact wire is located on a surface of a dielectric material that surrounds the photodetector and contacts a topmost surface of the photodetector and a portion of one of the semiconductor devices. An interconnect structure is located above the first region and the second region, and a metal layer is located atop the interconnect structure. The metal layer has a zero waveguide module located above the first region of the semiconductor substrate. A DNA polymerase can be present at the bottom of the zero waveguide module. |
| US10090428B2 |
Solar cell and method for manufacturing the same
A solar cell and a method for manufacturing the same are disclosed. The solar cell may include a substrate, an emitter layer positioned at a first surface of the substrate, a first anti-reflection layer that is positioned on a surface of the emitter layer and may include a plurality of first contact lines exposing a portion of the emitter layer, a first electrode that is electrically connected to the emitter layer exposed through the plurality of first contact lines and may include a plating layer directly contacting the emitter layer, and a second electrode positioned on a second surface of the substrate. |
| US10090427B2 |
Package structure of long-distance sensor and packaging method of the same
A package structure of a long-distance sensor includes a substrate, a light-emitting chip, a sensing chip, two packaging gel bodies, a cap, and two sheltering devices. The substrate has a bearing surface. The light-emitting chip and the sensing chip are disposed on the bearing surface and separated from each other. The two packaging gel bodies cover the light-emitting chip and the sensing chip respectively. The top surface of each of the packaging gel bodies is formed with a lens portion and a shoulder portion. The cap is formed on the bearing surface and the packaging gel bodies and provided with a light-emitting hole and a light-receiving hole accommodating the lens portions and the shoulder portions of the top surfaces of the packaging gel bodies respectively. The two sheltering devices are disposed on the shoulder portions respectively for blocking light from passing through the shoulder portions. |
| US10090425B2 |
Axially-integrated epitaxially-grown tandem wire arrays
A photoelectrode, methods of making and using, including systems for water-splitting are provided. The photoelectrode can be a semiconducting material having a photocatalyst such as nickel or nickel-molybdenum coated on the material. The photoelectrode includes an elongated axially integrated wire having at least two different wire compositions. |
| US10090424B1 |
Roll-to-roll solution process method for fabricating CIGS solar cells and system for the same
A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution. |
| US10090419B2 |
Solar cell and method for manufacturing the same
A solar cell includes a substrate formed of n-type single crystal silicon, an emitter region of a p-type which is positioned at a first surface of the substrate and includes a first emitter region having a first sheet resistance and a second emitter region having a second sheet resistance less than the first sheet resistance, a plurality of surface field regions of the n-type locally positioned at a second surface opposite the first surface of the substrate, a plurality of first electrodes which are positioned only on the second emitter region to be separated from one another and are connected to the second emitter region, and a plurality of second electrodes which are positioned on the plurality of surface field regions to be separated from one another and are connected to the plurality of surface field regions. |
| US10090418B2 |
Solar battery module
A solar battery module according to one embodiment comprises: a support substrate having a through-hole formed therein; a plurality of solar battery cells arranged on the support substrate; a busbar which is electrically connected to the solar battery cells; a first connection member which is inserted in the through-hole; and a second connection member which is connected to the first connection member, wherein the second connection member comprises a contact member that contacts the busbar through the through-hole. |
| US10090417B2 |
Silicon carbide semiconductor device and fabrication method of silicon carbide semiconductor device
A p-type region, a p− type region, and a p+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the p− type region are disposed in a breakdown voltage structure portion that surrounds an active region. The p+ type region is disposed in the active region to make up a JBS structure. The p− type region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The p+ type region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger. |
| US10090416B2 |
Radical oxidation process for fabricating a nonvolatile charge trap memory device
A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described. |
| US10090414B2 |
TFT substrate manufacture method
The present invention provides a TFT (Thin Film Transistor) substrate manufacture method, which includes forming a TFT gate electrode on a substrate, sequentially forming a first insulation layer, an active layer, a source electrode, and a drain electrode, and then forming a second insulation layer and coating a photoresist thereon, defining a pixel electrode pattern, forming a drain VIA hole on the second insulation layer, depositing a pixel electrode layer after preparing suede on the photoresist, and permeating the suede with a stripping liquid to remove the photoresist and the pixel electrode layer on the photoresist so as to form a pixel electrode connecting to the drain electrode via the drain VIA hole. |
| US10090411B2 |
Air-gap top spacer and self-aligned metal gate for vertical fets
A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. A top spacer is formed over the gate stack. The top spacer has air gaps directly above the gate stack. A top source/drain region is formed directly on a top surface of the vertical channel fin. |
| US10090407B2 |
Semiconductor device and manufacturing method
To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon. The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium. |
| US10090406B2 |
Non-planar normally off compound semiconductor device
A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride semiconductor transitions at an angle from a first level to a second level different than the first level, and a second III-nitride semiconductor on the first III-nitride semiconductor and having a different band gap than the first III-nitride semiconductor so that a two-dimensional charge carrier gas arises along an interface between the first and second III-nitride semiconductors. The normally-off compound semiconductor device further includes a gate on the second III-nitride semiconductor and a doped semiconductor over the first sloped transition region and interposed between the gate and the second III-nitride semiconductor. The two-dimensional charge carrier gas is disrupted along the first sloped transition region due solely to the slope of the first sloped transition region if steep enough, or also due to the presence of the doped semiconductor. |
| US10090405B2 |
Semiconductor device having group III-V material active region and graded gate dielectric
Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack. |
| US10090403B2 |
Power semiconductor device with semiconductor pillars
A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure. |
| US10090402B1 |
Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled. |
| US10090401B2 |
Thin film transistor, manufacturing method thereof, and display device including the same
A thin film transistor includes a substrate, a semiconductor layer, a first insulating layer, and a gate electrode. The gate electrode overlaps the semiconductor layer. The thin film transistor includes a second insulating layer on the gate electrode, and an electrode structure on the second insulating layer. The electrode structure is connected to the gate electrode through a via hole. The thin film transistor includes a source electrode and a drain electrode passing through the first insulating layer and the second insulating layer to be connected to the semiconductor layer. The semiconductor layer includes a channel area overlapping the gate electrode, a source area connected to the source electrode, a drain area connected to the drain electrode, a lightly doped source area, and a lightly doped drain area. The electrode structure overlaps at least one of the lightly doped source area or the lightly doped drain area. |
| US10090398B2 |
Manufacturing method of patterned structure of semiconductor
A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus. |
| US10090393B2 |
Method for forming a field effect transistor device having an electrical contact
A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region. |
| US10090390B2 |
FinFET with trench field plate
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate. |
| US10090386B2 |
Graphene-metal bonding structure, method of manufacturing the same, and semiconductor device having the graphene-metal bonding structure
Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the graphene-metal bonding structure. According to example embodiments, a graphene-metal bonding structure includes: a graphene layer; a metal layer on the graphene layer; and an intermediate material layer between the graphene layer and the metal layer. The intermediate material layer forms an edge-contact with the metal layer from boundary portions of a material contained in the intermediate material layer that contact the metal layer. |
| US10090385B1 |
Methods of forming a vertical transistor device with a channel structure comprised of alternative semiconductor materials
One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures. |
| US10090384B2 |
Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer
A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins. |
| US10090382B1 |
Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same
The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures. |
| US10090379B2 |
Hydrogen occlusion semiconductor device
When hydrogen penetrates in to the semiconductor device, a gate voltage threshold of a gate structure (Vth) is shifted. Penetrating of hydrogen into the semiconductor device from the edge termination structure section which is positioned at an end portion of the semiconductor device is prevented. To provide a semiconductor device comprising a semiconductor substrate in which an active region and an edge termination structure section which is provided around the active region are provided, a first lower insulating film which is provided in the edge termination structure section on the semiconductor substrate, and a first protective film which is provided on the first lower insulating film, and is electrically insulated from the semiconductor substrate, and occludes hydrogen. |
| US10090378B1 |
Efficient metal-insulator-metal capacitor
Capacitors and methods of forming the same include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities. |
| US10090374B2 |
Organic light-emitting display device
Organic light-emitting display devices are provided. One organic light-emitting display device includes a substrate, a first wire on the substrate, a second wire insulated from and crossing the first wire, and a static electricity dispersion pattern insulated from and crossing the second wire. Another organic light-emitting display device includes: a substrate; a gate line and a data line on the substrate, insulated from and crossing each other; a dummy wire that is part of a same layer as one of the gate line or the data line, and having at least one end aligned with a sidewall of the substrate; a dummy intersection wire insulated from and crossing the dummy wire; and a static electricity dispersion pattern insulated from and crossing the dummy intersection wire. |
| US10090372B2 |
Display device
Provided is a highly reliable display device that does not easily cause a wiring or an interlayer insulating layer to be cracked when being folded. A display device includes a flexible substrate; a plurality of pixels arrayed on the substrate; and a wiring, provided on the substrate, transmitting a signal to drive the plurality of pixels. The wiring includes a first conductive layer having an opening pattern at least in a partial area thereof. |
| US10090371B2 |
Organic light emitting diode display
An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line. |
| US10090370B2 |
Organic light emitting display device and method of manufacturing the same
Discussed is an organic light emitting display device according to the embodiments. The organic light emitting display device includes an anode electrode in each of a plurality of pixels defined on a substrate, a bank and an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, and an auxiliary electrode connected to the cathode electrode. The auxiliary electrode is provided on the bank, thereby the auxiliary electrode is disposed on a layer different from the anode electrode. |
| US10090369B2 |
Organic light emitting diode display
An organic light emitting diode display including a first connection line connected to an organic light emitting diode; a repair line intersecting the first connection line, the repair line being insulated from the first connection line; and a first welding part that is integrally formed with the first connection line or the repair line, the first welding part being aligned with an intersecting portion of the repair line and the first connecting line, and having a closed loop shape in plan view. |
| US10090367B2 |
Display device
A display device includes at least one light-emitting element configured to emit blue light, a red conversion layer disposed on an upper or lower portion of the at least one light-emitting element and including a red light-emitting quantum dot, a green conversion layer disposed on the upper or lower portion of the at least one light-emitting element and including a green light-emitting phosphor, and a substrate comprising thin film transistors electrically connected to the light-emitting element. |
| US10090362B2 |
Display device
A display device includes a plurality of pixels each having a plurality of light-emitting regions including at least a first light-emitting region of a first color, a second light-emitting region of a second color, and a third light-emitting region of a third color and a light-transmitting region. Visibility of the first color is higher than visibility of the second color. The plurality of light-emitting regions are divided into a first group including the first light-emitting region and a second group including the second light-emitting region. The first light-emitting region is adjacent to the second light-emitting region. The light-transmitting region is located between the first light-emitting region and the second light-emitting region. The light-transmitting region is not located in a region between light-emitting regions adjacent to each other in the first group and in a region between light-emitting regions adjacent to each other in the second group. |
| US10090358B2 |
Camera module in a unibody circuit carrier with component embedding
A camera module assembly including a circuit carrier substrate having a first region integrally formed with a second region, the second region being movable with respect to the first region. The camera module assembly may further include an image sensor device positioned within a cavity formed in the first region of the circuit carrier substrate. The image sensor device may have a conductive via and a redistribution layer formed therein. The conductive via and the redistribution layer are electrically connected to the circuit carrier substrate along the side of the image sensor device facing the circuit carrier substrate. The camera module assembly further includes an electronic component positioned within a second cavity formed in the first region, the electronic component being electrically connected to the circuit carrier substrate. |
| US10090356B2 |
Low noise InGaAs photodiode array
A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel. |
| US10090351B2 |
Semiconductor device having gaps within the conductive parts
A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate. |
| US10090350B2 |
Light receiving device
A light receiving device includes: a photoelectric converter including a photodiode and a first pixel electrode disposed on a lower surface of the photodiode; a scanning circuit connected to the first pixel electrode; an electrode pad disposed on a periphery of the scanning circuit; a transparent conductive film extending from an upper surface of the photodiode to the electrode pad, the transparent conductive film having an inclination relative to the upper surface of the photodiode, between the photodiode and the electrode pad; and a sealing resin filled in a space between the photoelectric converter and the scanning circuit, and in a space under the transparent conductive film around the photoelectric converter. |
| US10090349B2 |
CMOS image sensor chips with stacked scheme and methods for forming the same
A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit. |
| US10090348B2 |
Image sensor having guard dams
An image sensor is described. The image sensor may include a substrate including a pixel area, a logic area, and a guard area disposed between the pixel area and the logic area. The guard area may substantially prevent transfer of heat generated in the logic area from reaching the pixel area. |
| US10090341B2 |
Solid-state imaging device
A solid-state imaging device comprises a photodetecting section, an unnecessary carrier capture section, and a vertical shift register. The unnecessary carrier capture section has carrier capture regions arranged in a region between the photodetecting section and the vertical shift register for respective rows. Each of the carrier capture regions includes a transistor and a photodiode. The transistor has one terminal connected to the photodiode and the other terminal connected to a charge elimination line. The charge elimination line is short-circuited to a reference potential line. |
| US10090337B2 |
Thin film transistor with a reaction layer creating oxygen vacancies in an oxide semiconductor
A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide semiconductor pattern which is disposed on the gate insulation layer and includes a channel portion superimposed over the gate electrode, and low resistance patterns provided at edges of the channel portion, respectively, and including oxygen vacancies, a channel passivation layer on the oxide semiconductor pattern, a reaction layer which covers the oxide semiconductor pattern and the channel passivation layer, and includes a metal oxide, and a source electrode and a drain electrode which contact the oxide semiconductor pattern. |
| US10090328B2 |
Semiconductor device
A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns. |
| US10090327B2 |
Semiconductor device and method for forming the same
Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer. |
| US10090326B2 |
Flexible display substrate and a manufacturing method thereof, as well as a flexible display device
The embodiments of the present invention provide a flexible display substrate and a manufacturing method thereof, as well as a flexible display device, which relate to the technical field of display, and can avoid the performance of the thin film transistor from being influenced by light energy when a flexible substrate is striped from a carrying substrate. The method for manufacturing the flexible display substrate may comprise: forming a flexible substrate on a carrying substrate; forming a first buffer layer on the flexible substrate; forming a plurality of display elements on the first buffer layer, each of the plurality of display elements comprising a thin film transistor and an electrode structure, the thin film transistor comprising a metal oxide semiconductor active layer; stripping the flexible substrate from the carrying substrate, wherein the method further comprises: forming a light absorbing layer before the plurality of display elements are formed. |
| US10090322B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information. |
| US10090320B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a plurality of conductive bodies. The stacked body includes a plurality of electrode layers. The stacked body includes a stairstep portion at an end portion of the stacked body. The plurality of first terraces are provided in the stairstep portion. The second terrace is provided in the stairstep portion. The plurality of interconnects are provided from the second terrace to the plurality of first terraces. The plurality of interconnects contact one of the plurality of electrode layers at the stairstep portion. The plurality of conductive bodies are provided above the second terrace. The plurality of conductive bodies extend in a stacking direction of the stacked body. The conductive bodies contact the interconnects above the second terrace. |
| US10090318B2 |
Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure
A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method. |
| US10090316B2 |
3D stacked multilayer semiconductor memory using doped select transistor channel
In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor. |
| US10090313B2 |
NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch. Other embodiments may be described and claimed. The bitline pitch is the distance between bitlines. The cell pitch is the distance between cells. The mismatch is bitline spacing that is different from cell spacing. |
| US10090308B1 |
Semiconductor memory device
A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other. |
| US10090306B2 |
Fin-FET devices and fabrication methods thereof
A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer. |
| US10090301B2 |
Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. |
| US10090296B2 |
Semiconductor device, manufacturing method thereof, and electronic apparatus
A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring. |
| US10090291B2 |
Electrostatic discharge protection semiconductor device and layout structure of ESD protection semiconductor device
A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions. |
| US10090284B2 |
Semiconductor device and method of manufacture
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device. |
| US10090279B2 |
Stray inductance reduction in packaged semiconductor devices and modules
In a general aspect, an apparatus can include a first substrate operatively coupled with a second substrate. The apparatus can also include a power supply terminal assembly including a first power supply terminal aligned along a first plane, the first power supply terminal being electrically coupled with the first substrate. The power supply terminal assembly can also include a second power supply terminal aligned along a second plane, the second power supply terminal being electrically coupled with the second substrate. The power supply terminal assembly can further include a power supply terminal frame having an isolation portion disposed between the first power supply terminal and the second power supply terminal and a retention portion disposed around a portion of the first power supply terminal and disposed around a portion of the second power supply terminal. |
| US10090277B2 |
3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die. |
| US10090272B2 |
Chip package and chip packaging method
According to an embodiment of the present disclosure, a chip package including at least one chip, a first encapsulation layer, a redistribution layer, and a second encapsulation layer is provided. The at least one chip has an active surface, a back surface opposite to the active surface, and sidewall surfaces connecting the active surface and the back surface. The first encapsulation layer covers the sidewall surfaces. The first encapsulation layer has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the active surface and the first surface, and electrically connected to the at least one chip. The second encapsulation layer is disposed on the back surface and the second surface. A thermal expansion coefficient of the second encapsulation layer is less than a thermal expansion coefficient of the first encapsulation layer. Chip packaging methods are also provided. |
| US10090267B2 |
Bump structure and method for forming the same
A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction. |
| US10090266B2 |
Semiconductor device, and method of fabricating the same
A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip. The first lower insulating structure has a top surface positioned at a higher vertical level than that of the second lower insulating structure. |
| US10090261B2 |
Microelectronic package debug access ports and methods of fabricating the same
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact. |
| US10090258B1 |
Crack-stop structure for an IC product and methods of making such a crack-stop structure
One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer. |
| US10090257B2 |
Electrical package including bimetal lid
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided. |
| US10090256B2 |
Semiconductor structure
A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias. |
| US10090255B2 |
Dicing channels for glass interposers
The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel. |
| US10090249B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure. |
| US10090247B1 |
Semiconductor device formed by wet etch removal of Ru selective to other metals
A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and forming an interface layer over the barrier layer. A main conductor is formed over the interface layer, and the main conductor is recessed selectively to the interface layer and the barrier layer to a position below a top surface of the dielectric layer. The interface layer is selectively wet etched to the main conductor and the barrier layer using a chemical composition having an oxidizer, wherein the chemical composition is buffered to include a pH above 7. The barrier layer is selectively etching to the main conductor and the interface layer. |
| US10090246B2 |
Metal interconnect structure and fabrication method thereof
The present disclosure provides metal interconnect structures and fabrication methods thereof. An exemplary fabrication method of the metal interconnect structure includes providing a semiconductor substrate having a surface; forming a first metal layer on the surface of the semiconductor substrate; forming a dielectric layer on the first metal layer; forming contact through holes exposing a surface of the first metal layer, and trenches being over the contact through holes and connecting with the contact through holes in the dielectric layer; forming a first metal barrier layer on inner surfaces of the trenches and the contact through holes; forming a metal nitride barrier layer covering the first metal barrier layer on the inner surfaces of the trenches and the contact through holes; and forming a second metal layer to fill the trenches and the contact through holes. |
| US10090239B2 |
Metal-insulator-metal on-die capacitor with partial vias
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die. The power grid layers have power rails. First and second metal plates are formed in metal layers of the die between the power grid layers. Full vias extend from a power rail of the first polarity of the first power grid layer to a first side of the second metal plate and from a second side of the second metal plate opposite the first side of the metal plate to a power rail of the first polarity of the second power grid layer. Partial vias extend from the power rail of the first polarity of the second power grid layer and end at the second side of the second metal plate. |
| US10090237B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. |
| US10090236B2 |
Interposer having a pattern of sites for mounting chiplets
The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts. |
| US10090234B2 |
Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. |
| US10090232B1 |
Bumpless fan-out chip stacking structure and method for fabricating the same
A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively. |
| US10090231B2 |
Conductive connections, structures with such connections, and methods of manufacture
A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided. |
| US10090230B2 |
Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate
A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. |
| US10090227B1 |
Back biasing in SOI FET technology
In one aspect, the present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) substrate composed of an active layer, a substrate and a buried insulating layer which is positioned on an upper surface of the substrate and below a lower surface of the active layer. At least one gate electrode having a channel region below is positioned above an upper surface of the active layer and at least one vertical connection element extends between the upper surface of the substrate and an opposite lower surface of the substrate below the at least one gate electrode. The at least one vertical connection element serves for back-biasing FETs with back-bias contacts at the rear side of the wafer. |
| US10090225B2 |
Placement base for semiconductor device and vehicle equipment
A placement base (100) of a semiconductor device (90) comprises a body (10) on which the semiconductor device (90) is disposed, and a fixing unit (40) for fixing the semiconductor device (90) to the body (10). The body (10) has a supporting unit (12) and a bottom surface (11) placed in an inner periphery of the supporting unit (12) and placed lower than the supporting unit (12). A difference in height ΔH between the supporting unit (12) and the bottom surface (11) is larger than a sum (H1+H2) of a calculated or measured maximum upward warp H1 of the bottom surface (11) and a calculated or measured maximum downward warp H2 of a base of the semiconductor device (90). |
| US10090222B2 |
Semiconductor device with heat dissipation and method of making same
A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface. |
| US10090221B2 |
Semiconductor device with self-heat reducing layers
A method of forming a semiconductor device includes implanting dopants in a first region of the semiconductor device to form a source region. The method further includes forming a guard ring in a second region of the semiconductor device, the guard ring being separated from the source region by a first spacing. The method further includes depositing a first heat conductive layer over the source region, wherein the first heat conductive layer is directly coupled to the source region and directly coupled to the guard ring. The first heat conductive layer is configured to dissipate heat generated by the semiconductor device from the source region to the guard ring. |
| US10090219B2 |
Cured product
The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an LED or the like, the decrease in brightness may be minimized even upon the long-term use of the device, and since the cured product has excellent cracking resistance, the device having high long-term reliability may be provided. The cured product has excellent processability, workability, and adhesive properties or the like, and does not cause whitening and surface stickiness, etc. Further, the cured product exhibits excellent heat resistance at high temperature, gas barrier properties, etc. The cured product may be, for example, applied as an encapsulant or an adhesive material of a semiconductor device. |
| US10090212B2 |
Evaporation method including stretching a flexible substrate
An embodiment of the present disclosure discloses an evaporation method, including: providing a flexible substrate having an original size; stretching the flexible substrate to have an evaporation size, wherein, the evaporation size is greater than the original size; arranging a mask on a side of the flexible substrate having the evaporation size; evaporating a material onto the flexible substrate having the evaporation size by using the mask, to form a patterned film layer. |
| US10090209B2 |
Methods of predicting unity gain frequency with direct current and/or low frequency parameters
Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg). |
| US10090202B2 |
Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material. |
| US10090201B2 |
Method of manufacturing semiconductor device reducing variation in thickness of silicon layer among semiconductor wafers
A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area. |
| US10090200B2 |
Bipolar junction semiconductor device and method for manufacturing thereof
A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier. |
| US10090192B2 |
Method for producing a conductor line
A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed. |
| US10090188B2 |
Robot subassemblies, end effector assemblies, and methods with reduced cracking
A robot subassembly including roll, pitch, and/or vertical orientation adjustability capability of a ceramic or glass end effector. The robot subassembly includes a robot component, a mounting plate coupled to the robot component, wherein the mounting plate includes adjustable orientation relative to the robot component, and a brittle ceramic or glass end effector coupled to the mounting plate. Methods of adjusting orientation between a robot component and the end effector, as well as numerous other aspects are disclosed. |
| US10090184B2 |
Carrier substrate, method of manufacturing the same, and method of manufacturing flexible display device using the carrier substrate
A carrier substrate includes: a base substrate; a first coating layer on a first surface of the base substrate; and a second coating layer on a second surface of the base substrate. The thermal expansion coefficients of the first coating layer and the second coating layer are greater than a thermal expansion coefficient of the base substrate, and a thickness of the first coating layer is different from a thickness of the second coating layer. |
| US10090180B2 |
Package assembly for thin wafer shipping and method of use
A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof. |
| US10090177B1 |
Cold fluid semiconductor device release during pick and place operations, and associated systems and methods
Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die. |
| US10090166B2 |
Techniques for forming isolation structures in a substrate
A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide. |
| US10090164B2 |
Hard masks for block patterning
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal. |
| US10090159B2 |
Chemical-mechanical polishing compositions comprising one or more polymers selected from the group consisting of N-vinyl-homopolymers and N-vinyl copolymers
Described is a chemical-mechanical polishing (CMP) composition comprising the following components: (A) surface modified silica particles having a negative zeta potential of −15 mV or below at a pH in the range of from 2 to 6 (B) one or more polymers selected from the group consisting of N-vinyl-homopolymers and N-vinyl copolymers (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6. |
| US10090158B2 |
Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst. |
| US10090157B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire. When viewed in cross section taken along third direction, each nanowire in nanowire structure is differently shaped from other nanowires, and each nanowire has substantially same cross-sectional area as other nanowires in nanowire structure. |
| US10090153B2 |
Formation of heteroepitaxial layers with rapid thermal processing to remove lattice dislocations
Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec. |
| US10090152B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a method of manufacturing a semiconductor device, which includes: forming a seed layer doped with a dopant on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a halogen-based first process gas to the substrate, supplying a non-halogen-based second process gas to the substrate, and supplying a dopant gas to the substrate; and supplying a third process gas to the substrate to form a film on the seed layer. |
| US10090149B2 |
Method of manufacturing semiconductor device by forming and modifying film on substrate
A method of manufacturing a semiconductor device includes: forming a base film containing a first element and carbon on a substrate by supplying a film forming gas to the substrate; and oxidizing the base film by supplying an oxidizing gas to the substrate to modify the base film into a C-free oxide film containing the first element. |
| US10090143B2 |
Real time measurement techniques combining light sources and mass spectrometer
The present invention provides a mass spectrometer comprising a sample inlet, an ionization source, a mass analyzer, and an ion detector, wherein the ionization source comprises a photoionization detector lamp. The invention also provides mass spectrometers comprising two photoionization detector lamps. The use of a photoionization detector lamp can provide an increase in the signal of detected compounds as compared to the signal of detected compounds obtained using a comparable mass spectrometer with a conventional electron pumped beam lamp. |
| US10090142B2 |
Apparatus and method for sampling of confined spaces
In various embodiments of the invention, a cargo container can be monitored at appropriate time intervals to determine that no controlled substances have been shipped with the cargo in the container. The monitoring utilizes reactive species produced from an atmospheric analyzer to ionize analyte molecules present in the container which are then analyzed by an appropriate spectroscopy system. In an embodiment of the invention, a sorbent surface can be used to absorb, adsorb or condense analyte molecules within the container whereafter the sorbent surface can be interrogated with the reactive species to generate analyte species characteristic of the contents of the container. |
| US10090141B2 |
Ion guide construction method
A method of constructing an ion guide is disclosed comprising providing an elongated spine member and a plurality of plates. Each plate comprises an aperture therethrough for receiving the spine member and at least one electrode for use in guiding ions. The apertures of the plates are arranged around the spine member and the plates are arranged along the spine member. The plates are then locked in position on the spine member such that the plates are fixed axially with respect to the spine member and so that the electrodes of the plates are arranged so as to form an array of electrodes for use in guiding ions. |
| US10090140B2 |
IRMS sample introduction system and method
A sample introduction system for a spectrometer comprises a desolvation region that receives or generates sample ions from a solvent matrix and removes at least some of the solvent matrix from the sample ions. A separation chamber downstream of the desolvation region has a separation chamber inlet communicating with the desolvation region, for receiving the desolvated sample ions along with non-ionized solvent and solvent ion vapors. The separation chamber has electrodes for generating an electric field within the separation chamber, defining a first flow path for sample ions between the separation chamber inlet and a separation chamber outlet. Unwanted solvent ions and non-ionized solvent vapors are directed away from the separation chamber outlet. The sample introduction system has a reaction chamber with an inlet communicating with the separation chamber outlet, for receiving the sample ions from the separation chamber and for decomposing the received ions into smaller products. |
| US10090139B2 |
Mass analysis device
A mass analysis device capable of reliably detecting the peak in a mass chromatogram of a given m/z is equipped with a control unit, which generates a mass chromatogram and total ion chromatogram. The control unit includes a determination unit which, using the total ion chromatogram, determines the start time and end time of the peak in the total ion chromatogram by searching for the peak based on maximum value of detected intensity and searching for peak start time and end time based on slope of change of detected intensity; and a detection unit, which detects the peak in the mass chromatogram by making the start time and end time of the peak in the mass chromatogram the same as the start time and end time of the peak in the total ion chromatogram. |
| US10090137B2 |
In—Ce—O-based sputtering target and method for producing the same
[Object] To provide: an In—Ce—O-based sputtering target capable of suppressing nodules and abnormal discharge over a long period, even though the Ce content based on an atomic ratio of Ce/(In+Ce) is 0.16 to 0.40, at which a high-refractive-index film can be obtained; and a method for producing the In—Ce—O-based sputtering target. [Solving Means] The sputtering target is an In—Ce—O-based sputtering target which is made of an In—Ce—O-based oxide sintered body containing indium oxide as a main component and cerium, and which is used in producing a transparent conductive film having a refractive index of 2.1 or more. The target is characterized in that the Ce content based on the atomic ratio of Ce/(In+Ce) is 0.16 to 0.40, and that cerium oxide particles having a particle diameter of 5 μm or less are dispersed in the In—Ce—O-based oxide sintered body. |
| US10090136B2 |
Oxide sintered body and sputtering target, and method for producing same
An oxide sintered body which is obtained by mixing and sintering zinc oxide, indium oxide, gallium oxide and tin oxide. The relative density of the oxide sintered body is 85% or more and the average grain size of crystal grains observed on the surface of the oxide sintered body is less than 10 μm. X-ray diffraction of the oxide sintered body shows that a Zn2SnO4 phase and an InGaZnO4 phase are the main phases and that an InGaZn2O5 phase is contained in an amount of 3 volume % or less. |
| US10090135B2 |
Methods of forming coating layers
A method of forming a coating layer, including preparing hollow inorganic particles, each hollow inorganic particle including a shell surrounding a hollow core; preparing inorganic coating particles of a solid structure; forming a mixture of the hollow inorganic particles and the inorganic coating particles; and spraying the mixture on a surface of a base by a plasma spray coating process. |
| US10090134B2 |
Plasma reactor with inductive excitation of plasma and efficient removal of heat from the excitation coil
The plasma reactor of the invention is intended for treating the surfaces of objects such as semiconductor wafers and large display panels, or the like, with plasma. The main part of the plasma reactor is an array of RF antenna cells, which are deeply immersed into the interior of the working chamber. Each antenna cell has a ferromagnetic core with a heat conductor and a coil wound onto the core. The core and coil are sealed in the protective cap. Deep immersion of the antenna cells having the structure of the invention provides high efficiency of plasma excitation, while the arrangement of the plasma cells and possibility of their individual adjustment provide high uniformity of plasma distribution and possibility of adjusting plasma parameters, such as plasma density, in a wide range. |
| US10090132B2 |
Charged particle beam irradiation apparatus
A charged particle beam irradiation apparatus according to an embodiment includes: a first scanning electromagnet device configured to deflect a charged particle beam to a second direction that is substantially perpendicular to a first direction along which the charged particle beam enters, the first scanning electromagnet device having an aperture on an outlet side larger than that on an inlet side; and a second scanning electromagnet device configured to deflect the charged particle beam to a third direction that is substantially perpendicular to the first direction and the second direction, the second scanning electromagnet device having an aperture on an outlet side larger than that on an inlet side, the first scanning electromagnet device and the second scanning electromagnet device being disposed to be parallel with the first direction. |
| US10090130B2 |
Magnetron and method of adjusting resonance frequency of magnetron
Provided are a magnetron whose resonance frequency is easily adjusted and a method of adjusting a resonance frequency of the magnetron. A magnetron includes an anode cylinder extending in a cylindrical shape along a central axis, a plurality of tabular vanes each having at least one end fixed to the anode cylinder and extending toward the central axis from an inner surface of the anode cylinder, and pressure-equalizing rings disposed coaxially with respect to the central axis of the anode cylinder, and alternately electrically connecting the tabular vanes to each other. The tabular vanes have protrusions facing the pressure-equalizing rings in an axial direction of the anode cylinder, and notches serving as base points for deforming the protrusions toward the pressure-equalizing rings sides or opposite sides thereto. |
| US10090126B2 |
Opening and closing device
A switchgear includes a stationary contact, a movable contact able to be shifted between a closed position and an opened position, an electromagnetic actuator able to generate power for shifting the movable contact, the electromagnetic actuator including a stator and a movable element, and a power transmission unit able to shift the movable contact, and to press the movable contact against the stationary contact. The power transmission unit includes a drive unit-side spring bearing portion able to be shifted together with the movable element, a contact-side spring bearing portion to be opposed to the drive unit-side spring bearing portion, and able to be shifted together with the movable contact, and a spring member provided between the drive unit-side spring bearing portion and the contact-side spring bearing portion. |
| US10090125B2 |
Methods of determining the order of operating contactors in high voltage circuits
A method of controlling positive and negative contactors in a high voltage electrical system includes sensing current flowing through each contactor prior to opening of the contactor and/or after closing of the contactor. A negative contactor weighted value is computed based at least partially on the sensed current flowing through the negative contactor during opening and/or closing. A positive contactor weighted value is computed based at least partially on the sensed current flowing through the positive contactor during opening and/or closing. The order of opening and/or closing of the contactors is determined utilizing at least one of the negative contactor weighted value and the positive contactor weighted value. |
| US10090124B2 |
Rotary switching device selection element information display
[Object] To enable to visually recognizing information displayed on an outer circumferential surface of a member from an axial direction of the member and capable of switching selection elements while viewing the device from the axial direction.[Solution] A rotary switching device includes: a cylindrical first member that includes an outer circumferential surface on which predetermined information is displayed; a second member that is rotatable relative to the first member; a plurality of selection elements among which a selection target is switched in accordance with relative positions of the first member and the second member; a mirror surface part that is formed by a surface disposed around the outer circumferential surface of the first member and intersecting an axial direction of the first member, and that is configured to specularly reflect the information displayed on the outer circumferential surface of the first member to enable the information to be visually recognized from the axial direction of the first member; and an indicating part configured to indicate the selection element that is selected. |
| US10090122B2 |
Low profile keyboard backlight module
A low profile keyboard backlight module includes an electrically insulative bottom membrane layer, an intermediate membrane layer including a conducting layer, an insulative layer and a light-emitting layer attached together through lamination and bonded to the top surface of the bottom membrane layer, and an electrically insulative top membrane layer bonded to a top surface of the intermediate membrane layer opposite to the bottom membrane layer and having an integrated elastic layer located at a top surface thereof to support a set of keys. Thus, the low profile keyboard backlight module provides optimal waterproof effects and is practical for use in an electronic product having light, thin, short and small characteristics. |
| US10090119B2 |
Smart speaker with multifunctional faceplate and display
In one embodiment a sound generating system comprises: a housing; a speaker located at least partially inside the housing; and an interactive faceplate subassembly comprising: a front surface, wherein a portion of the front surface contains a first plurality of openings forming a speaker grille; a display operable to display through a first portion of the front surface; the display disposed behind the front surface of the interactive faceplate subassembly and coupled to a second surface having a second plurality of openings, and wherein at least one of the openings in the second plurality of openings aligns with one or more of the openings in the first plurality of openings, thereby promoting improved sound transmission from the speaker. |
| US10090116B2 |
Biological supercapacitor structure and method for manufacturing and use of the same
A biological supercapacitor comprising at least one pair of electrodes that comprise immobilized biological materials that includes enzymes. The enzymes are immobilized to the electrodes and may be isolated enzymes, enzyme cascades comprising multiple enzymes, whole cells, organelles from cells, or parts of organelles from cells. An aspect of the disclosed biological supercapacitor is that a byproduct is water. The disclosed biological supercapacitor combines the energy density of a battery with the power density of a supercapacitor in order to reduce the size and weight of the energy storage devices. Methods of fabrication and of use of the biological supercapacitor are also disclosed. |
| US10090115B2 |
Energy storage device and method for producing energy storage device including a pre-doping targeted electrode
An energy storage device before pre-doping includes positive electrodes, negative electrodes, separators, a cover, an electrolyte solution, a positive terminal, a negative terminal, and pre-doping metal foil. Each of the positive electrodes and the negative electrodes respectively include: positive collector foil and negative collector foil each having holes; and a positive active-material layer and a negative active-material layer arranged on at least one side of the collector foil. Either one or both of the positive electrodes and the negative electrodes include a pre-doping-targeted electrode, in which the pre-doping metal foil is arranged in direct contact with the surface of the active-material layer, and a non-arrangement part, in which the pre-doping metal foil is not arranged, is formed in at least part of the outer periphery of the active-material layer. |
| US10090111B2 |
Method for manufacturing high-voltage solid-electrolyte aluminum electrolytic capacitor
The present invention discloses a method for manufacturing a high-voltage solid electrolyte aluminum-electrolytic capacitor, including: (1) Welding a capacitor core onto an iron bar, applying a voltage for chemical treatment, and after the chemical treatment, washing and drying the capacitor core; (2) impregnating the dried capacitor core in a dispersion A for 1˜30 minutes; (3) removing the capacitor core out of the dispersion A, creating a vacuum and then impregnating the capacitor core in the dispersion A for 1˜10 minutes; (4) keeping the capacitor core in the dispersion A, breaking the vacuum and then performing pressurization, and keeping the pressurized state for 1˜10 minutes; (5) keeping the capacitor core in the dispersion A, performing depressurization to an atmospheric pressure, and keeping the atmospheric pressure for 1˜10 minutes; (6) taking the capacitor core out, placing the capacitor core in a temperature of 65˜100° C. and drying it for 20˜60 minutes, and then placing the capacitor core in a temperature of 135˜165° C. and drying it for 20˜60 minutes; (7) repeating steps (3) to (6) at least once; and (8) putting the capacitor core in an aluminum cover and sealing it, and performing aging treatment, where the dispersion A is a dispersion that includes conductive polymers. This manufacturing method may be performed to obtain a solid capacitor of a lower ESR value and a higher withstand voltage, and obtain a lower leakage current. |
| US10090110B2 |
Crystal unit and method of adjusting crystal unit
A crystal unit includes: a capacitor in which a plurality of dielectrics and a plurality of internal electrodes are alternately stacked; a crystal piece arranged above the capacitor and having excitation electrodes on both surfaces thereof; an external electrode formed on a surface of the capacitor; and a first conductor portion formed within the capacitor, and including one end electrically coupled to a first internal electrode among the plurality of internal electrodes, the other end electrically coupled to the external electrode, and a first exposed portion exposed on the surface of the capacitor between the one end and the other end. |
| US10090109B2 |
Monolithic ceramic capacitor, monolithic ceramic capacitor array, and monolithic ceramic capacitor mounting structure
A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B. |
| US10090107B2 |
Multilayer electronic component having first internal electrode base patterns exposed to an end and opposing side surfaces of a body, and method of manufacturing the same
A multilayer electronic component and a method of manufacturing the same are provided. The multilayer electronic component includes a body including a multilayer structure in which first internal electrode patterns and second internal electrode patterns different from the first internal electrode patterns are alternately stacked and containing a dielectric material. First and second side parts are disposed on respective outer surfaces of a first pair of opposing outer surfaces of the body. First and second external electrodes are disposed on respective outer surfaces of a second pair of opposing outer surfaces of the body, and the first and second external electrodes are electrically connected to the first and second internal electrode patterns, respectively. The first internal electrode patterns are exposed to the outer surfaces of the first pair of outer surfaces of the body on which the first and second side parts are disposed. |
| US10090103B2 |
Method for manufacturing rare-earth magnets
Provided is a method for manufacturing a rare-earth magnet capable of preventing the lubricant from flowing down during hot deformation processing, whereby friction force can be made as uniform as possible at the overall region of the sintered body, and so the rare-earth magnet manufactured can have less distribution of magnetic performance. A method for manufacturing a rare-earth magnet includes: a first step of sintering magnetic powder MF as a material of the rare-earth magnet to prepare a sintered body S; and a second step of placing the sintered body S in a cavity K of a forming die M made up of a die D and a lower punch P and/or an upper punch P sliding in the die D, and performing hot deformation processing of the sintered body S to give magnetic anisotropy to the sintered body to manufacture the rare-earth magnet C. In the second step, a lubrication sheet 10 is disposed between a side face of each of the lower and the upper punches P, P facing the cavity K and the sintered body S, the lubrication sheet including a pair of graphite sheets 11 and glass-based lubricant 12 sandwiched therebetween, and the hot deformation processing is performed while sandwiching the sintered body S between the upper and the lower lubrication sheets 10. |
| US10090102B2 |
Method for producing rare-earth sintered magnet, and molding machine therefor
The present invention provides a method for producing a rare earth sintered magnet and a molding device therefor that can stably mold molded bodies with less variation in unit weight. The method includes: 1) preparing a slurry that includes an alloy powder containing a rare earth element, and a dispersion medium; 2) disposing an upper punch and a lower punch in respective through holes provided in a die, thereby preparing a plurality of cavities; 3) applying a magnetic field in each of the cavities by an electromagnet in a direction substantially parallel to a direction in which at least one of the upper punch and the lower punch is movable, and then supplying the slurry into the plurality of cavities; 4) producing a molded body of the alloy powder in each of the cavities by press molding in the magnetic field; and 5) sintering the molded body. |
| US10090101B2 |
Expandable and flexible terminal assembly
The present invention provides an expandable and flexible apparatus that can be installed on a device including but not limited to a bushing current transformer (BCT), a control power transformer or a toroidal power transformer. Such an apparatus provides at least one connection point on the device that it is installed on. The apparatus comprises a terminal, a terminal plate, a terminal plate expansion strip or a combination thereof. The apparatus is novel because it has an expandable connection that allows for many terminals to link and be positioned in desired configurations and distances, a linking system that makes the apparatus flexible and allows it to follow the contours of the device, and an anti-rotational provision that holds the terminal in position while the user is connecting wires to the apparatus. |
| US10090098B2 |
Arrangement and method for reducing a magnetic unidirectional flux component in the core of a transformer
An arrangement for reducing a magnetic unidirectional flux component in the core of a transformer includes a measurement apparatus which provides a measurement signal corresponding to the magnetic unidirectional flux component, a compensation winding magnetically coupled to the core of the transformer, wherein magnetic flux flowing in the core induces a voltage in the compensation winding, a switch device arranged electrically in series together with the compensation winding in a current path, a control device which controls the switch device via a control parameter, where the switch unit comprises a magnetic core and a winding arrangement which is magnetically coupled to the magnetic core, and the control parameter is supplied to the winding arrangement such that the magnetic saturation state of the core is variable, whereby the conductive state of the switch unit can be produced. |
| US10090095B2 |
Stationary induction electrical apparatus
A stationary induction electrical apparatus includes a disc winding having a structure in which a flow path for a cooling medium is provided between coils where a low voltage is generated between shield wires, an L-shaped insulation barrier is provided between coils where a high voltage is generated between the shield wires, a horizontal portion of the L-shaped insulation barrier is provided so as to closely contact an upper surface or a lower surface of the disc coil, a tip end portion in an axial direction of the L-shaped insulation barrier is provided so as to closely contact an inner surface of the disc coil which is adjacent to a pressboard insulation cylinder, and a height of the tip end portion in the axial direction is lower than a thickness of one coil. |
| US10090094B2 |
Flex-based surface mount transformer
A transformer can include a flexible substrate having at least a first conductive layer and a dielectric layer. The transformer can further include an unbroken toroidal core of a magnetic material. The magnetic material can include material with a relative magnetic permeability greater than unity. The substrate can include a plurality of planar extensions arranged to provide respective windings encircling the core when the planar extensions are folded and attached back to another region of the substrate. Adjacent windings can be conductively isolated from each other. The flexible substrate can further include a second conductive layer separated from the first conductive layer by the dielectric layer. The first conductive layer and the second conductive layer can be coupled via a plurality of interconnects so that the respective windings are formed when the planar extensions are folded and attached back to the another region of the substrate. |
| US10090093B2 |
Multi-winding high sensitivity current transformer
A system includes a sensor configured to detect an electrical leakage current associated with an operation of an industrial machine. The sensor includes a core and a first winding encircling a first portion of the core. The first winding includes a first number of turns. The first winding is configured to obtain a set of electrical current measurements associated with the operation of the industrial machine. The sensor includes a second winding encircling a second portion of the core. The second winding includes a second number of turns. The second winding is configured to obtain the set of electrical current measurements associated with the operation of the industrial machine. The first winding and the second winding are each configured to generate respective outputs based on the set of electrical current measurements. The respective outputs are configured to be used to reduce the occurrence of a distortion of the set of electrical current measurements based on a temperature of the core. |
| US10090092B2 |
Solenoid valve for hydraulic control
A solenoid valve includes a spool valve and a linear solenoid. The spool valve is used inside a hydraulic oil. The linear solenoid includes a resin cylindrical bobbin, a coil, and a case. The solenoid valve further includes a projecting portion, a first terminal, a first coil lead wire, a slit, a first coating portion, and a second coating portion. Each of the first coil lead wire and the second coil lead wire includes an exposed portion. The slit separates an electrical connection between the first terminal and the first coil lead wire from an electrical connection between the second terminal and the second coil lead wire. The first coating portion is formed by coating an entire surface of the exposed portion of the first coil lead wire. The second coating portion is formed by coating an entire surface of the exposed portion of the second coil lead wire. |
| US10090091B2 |
Magnet assembly for a solenoid valve
The invention relates to a magnet assembly for a solenoid valve, comprising a magnetic core (3), composed of at least two core elements (1, 2), and a magnetic coil (4), said magnetic core being connected in an annular recess (5) of a core element (1). According to the invention, the recess (5) on the side of a terminal surface (6) which forms the core element (1), is closed in a media-tight manner via a web portion (7). The invention further relates to a solenoid valve comprising such a magnet assembly. |
| US10090090B2 |
Rare-earth nanocomposite magnet
The invention provides a nanocomposite magnet, which has achieved high coercive force and high residual magnetization. The magnet is a non-ferromagnetic phase that is intercalated between a hard magnetic phase with a rare-earth magnet composition and a soft magnetic phase, wherein the non-ferromagnetic phase reacts with neither the hard nor soft magnetic phase. A hard magnetic phase contains Nd2Fe14B, a soft magnetic phase contains Fe or Fe2Co, and a non-ferromagnetic phase contains Ta. The thickness of the non-ferromagnetic phase containing Ta is 5 nm or less, and the thickness of the soft magnetic phase containing Fe or Fe2Co is 20 nm or less. Nd, or Pr, or an alloy of Nd and any one of Cu, Ag, Al, Ga, and Pr, or an alloy of Pr and any one of Cu, Ag, Al, and Ga is diffused into a grain boundary phase of the hard magnetic phase of Nd2Fe14B. |
| US10090085B2 |
Varistor and production method thereof
The present invention relates to a product and fabrication method for a varistor comprising a solid phase of zinc oxide particles substantially uniformly dispersed within a resin media. The varistor of the present invention is synthesized by mixing a substantially homogenous mixture of solid zinc oxide particles and a resin media, and heating the mixture under conditions to melt the resin and suspend the solid zinc oxide particles therein. |
| US10090083B2 |
System and method for cryogenic fluid delivery by way of a superconducting power transmission line
A combined electrical power and hydrogen energy infrastructure includes a superconducting electrical transmission line. One or more fluid paths are adapted to cool one or more superconductors of the electrical transmission line to a superconducting operating condition and to deliver hydrogen in a liquid state. The combined electrical power and hydrogen energy infrastructure also includes a supply apparatus to pump hydrogen into the one or more paths and to cool and pressurize the hydrogen to maintain the hydrogen in a liquid state. A distribution apparatus is operatively coupled to the one or more fluid paths at a different location along or at an end of the electrical transmission line to draw off the hydrogen for distribution of the hydrogen for use as a hydrogen fuel. An electrical transmission line and a method for supplying a fluid via an electrical transmission line are also described. |
| US10090081B2 |
Cable and method for its manufacture
A cable, in particular a data cable, extends in a longitudinal direction and has a number of lines and a structural element extending in the longitudinal direction for stiffening the cable. The lines are embedded in the structural element. Here, the lines and the structural element are surrounded by a common shield made of a conductive material. Due to the special arrangement of the shield, a particularly compact structure can be provided. A method for producing the cable is also provided. |
| US10090078B2 |
Nanocomposite films and methods of preparation thereof
Nanocomposite films comprising carbon nanotubes dispersed throughout a polymer matrix and further comprising at least two surfaces with differing amounts of carbon nanotubes and differing electrical resistivity values are provided. Nanocomposite films comprising a polymer layer, a conductive nanofiller layer, and a polysaccharide layer having antistatic properties are provided. In particular, nanocomposites comprising polyvinyl alcohol as the polymer, graphene as the conductive nanofiller and starch as the polysaccharide are provided. In addition, processes for forming the nanocomposites, methods for characterizing the nanocomposites as well as applications in or on electrical and/or electronic devices are provided. |
| US10090077B2 |
Resin composition and molded article containing the same
The present invention provides a polyamide resin composition not only having an appropriate melt viscosity despite addition of a conductive filler thereto but also having excellent moldability, conductivity, low-temperature impact resistance, and fuel barrier properties. The present invention is a polyamide resin composition containing specific amounts of a polyamide, a modified resin, and a conductive filler. The polyamide contains: dicarboxylic acid units containing 50 mol % or more of terephthalic acid units and/or naphthalenedicarboxylic acid units; and diamine units containing 60 mol % or more of aliphatic diamine units having 4 to 18 carbon atoms, and has terminal amino groups in an amount of 5 to 60 μmol/g. The modified resin has been modified with an unsaturated compound having a carboxyl group and/or an acid anhydride group. In the polyamide resin composition, a difference between the number of moles (MI) of the terminal amino groups of the polyamide and the number of moles (MII) of the carboxyl groups and the acid anhydride groups of the modified resin in 1 g in total of the polyamide and the modified resin is −5.0 μmol or more and less than 4.0 μmol, and the number of moles (MII) is more than 4.0 μmol. |
| US10090070B2 |
Electronic dental charting
Systems, methods, electronic devices and computer-readable media for charting dental information are described. The method includes generating or retrieving a dental data set including separately-modifiable parameters defining dental information relative to a base parametric model, the parameters providing information for generating signals for displaying a three-dimensional (3D) representation of at least a portion of a dentition represented by the dental data set; receiving an input via the 3D representation; and based on the received input, adjusting at least one of the parameters. |
| US10090069B2 |
Systems and methods for data cleansing such as for optimizing clinical scheduling
A scheduling system and method for data cleansing may be used to optimize clinical scheduling. The present disclosure describes receiving clinical record data, in an agnostic manner, from a system including a source scheduling database containing the clinical record data; mapping the clinical record data to a desired format; conforming the clinical record data to standardized scheduling elements of the scheduling system; cleansing, in a manner configurable by a user, the clinical record data to purge portions of the clinical record data; providing the clinical record data to an optimization engine for optimization of the clinical record data; optimizing the clinical record data by applying configurable logic to the clinical record data; and uploading one or more newly defined optimized scheduling templates via an outbound connection back to the scheduling system. |
| US10090068B2 |
Method and system for determining whether a monitored individual's hand(s) have entered a virtual safety zone
A system and method that allows caregivers, central monitoring services, and other persons to monitor whether a monitored individual's hand(s) have entered into an area where the caregiver has determined the monitored individual's hand(s) should not be, such as where the monitored individual may remove or disturb a piece of medical equipment. Where the monitored individual's hand(s) do enter the restricted area that is represented by an electronic virtual safety zone, an alert can be generated by the system and method. |
| US10090066B2 |
Semiconductor memory devices, memory systems including the same and method of correcting errors in the same
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array. |
| US10090061B2 |
Memory test data generating circuit and method
A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series. |
| US10090057B2 |
Dynamic strobe timing
Apparatuses, systems, methods, and computer program products are disclosed for dynamic strobe timing. A controller is configured to generate a strobe signal to facilitate data transfer. A controller is configured to receive a feedback signal in response to initiation of a strobe signal. A controller is configured to control a duration of a strobe signal based on a feedback signal. |
| US10090056B2 |
Semiconductor memory device
A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted. |
| US10090055B2 |
Memory device having negative voltage generator
Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit. |
| US10090054B2 |
Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. |
| US10090051B2 |
Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. |
| US10090049B2 |
Semiconductor integrated circuit with resistive change elements intersect with first and second plurality wiring lines, control circuit and plurality of current limiter circuits corresponding to the first and second wiring lines
An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element. |
| US10090048B2 |
Semiconductor memory devices including a memory array and related method incorporating different biasing schemes
Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided. |
| US10090046B2 |
Nonvolatile memory device and read method thereof
Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result. |
| US10090045B2 |
Programming method of non volatile memory device according to program speed of memory cells
Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups. |
| US10090044B2 |
System and method for burst programming directly to MLC memory
A memory system can program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming are selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which include one or more of a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, are used to program the blocks selected for burst mode programming. In this regard, burst mode programming is performed more quickly than normal mode programming. |
| US10090041B2 |
Performing logical operations using sensing circuitry
Apparatuses and methods related to performing logical operations using sensing circuitry are provided. One apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry. |
| US10090038B2 |
Semiconductor memory device for deconcentrating refresh commands and system including the same
A memory device includes a buffer memory configured to receive commands from a memory controller via first to Nth channels, wherein N denotes an integer which is equal to or greater than ‘2’; and first to Nth core memories each connected to the buffer memory via one of the first to Nth channels. The buffer memory may deconcentrate refresh commands corresponding to the first to Nth core memories, based on a number of commands input during a specific time. |
| US10090037B2 |
Methods of retaining and refreshing data in a thyristor random access memory
A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein. |
| US10090036B2 |
Non-volatile memory cell having pinch-off ferroelectric field effect transistor
The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET. |
| US10090035B2 |
Semiconductor devices having separate source line structure
A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation. |
| US10090034B2 |
Magnetoelectric memory cells with domain-wall-mediated switching
A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain wall to be trapped within a magnetoelectric antiferromagnetic (MEAF) active layer. An extension of this architecture applies to multiple-gate linear arrays that can offer advantages in memory density, programmability, and logic functionality. Applying a small anisotropic in-plane shear strain to the MEAF can block domain wall precession to improve reliability and speed of switching. |
| US10090032B2 |
Word line driving unit with a boost voltage generator and memory device including the same
A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed. |
| US10090027B2 |
Memory system with low read power
A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. The second memory bank includes a plurality of second memory cells. The first path selector includes a plurality of input terminals coupled to the first memory cells through a plurality of first bit lines, and two output terminals. The second path selector includes a plurality of input terminals coupled to the second memory cells through a plurality of second bit lines, and two output terminals. The sensing device is coupled to the output terminals of the first bank selector and the second bank selector, and senses the difference between currents outputted from two of the reference current source, and the terminals of the two bank selectors according to the required operations. |
| US10090023B2 |
Memory device including memory circuit and selection circuit
To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor. |
| US10090022B2 |
Semiconductor device and method for operating the semiconductor device
To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor. |
| US10090019B2 |
Method, system and computer program product for editing movies in distributed scalable media environment
A movie editor converts a received movie into a proxy format, and creates a texture strip representing the frames of the movie. An editor can use the texture strip to edit the movie, rather than editing the movie directly. Deep tags and/or special effects can be defined for the texture strip using a graphical interface. The graphical interface enables movies to be combined into a playback product according to a control structure graphically presented in the graphical interface. |
| US10090018B2 |
Method and device for generating video slides
A method and device for generating video slides, which relate to the technical field of picture and video processing, comprising: selecting pictures for generating video slides; creating and displaying a time axis, the selected pictures being distributed on the time axis according to a time sequence corresponding to time attributes of the pictures; receiving user settings for playing effects of subsequently generated video slides, wherein, the settings comprise settings for changing locations of the selected pictures on the time axis; generating the video slides according to the playing effects of the settings so as to play the selected pictures according to a location sequence on the time axis. The invention is suitable for a situation where playing effects of the video slides generated from pictures can be set conveniently. |
| US10090017B2 |
Apparatus and method for dynamic multiple actuator drive data access
An apparatus and method for dynamic multiple actuator drive data access includes: partitioning a data package of a received data transfer request into a plurality of data segments; assigning actuator drivers and actuator controllers; initiating a data transfer to or from the data storage medium using one or more of the plurality of actuators corresponding to the one or more assigned actuator controllers; storing or retrieving an individual data package of the data transfer request to or from the data storage medium wherein the entire data package is wholly accessible to a single actuator, if the data transfer request is a random data mode request; and storing or retrieving an individual data segment of the data transfer request to or from the data storage medium wherein the data package is accessible to the plurality of actuators, if the request is a parallel data mode request. |
| US10090016B2 |
Variable written track widths for attribute-based storage
A storage device controller is configured to select one of multiple written track widths for a storage location based on a write attribute of data to be recorded at the storage location. According to one implementation, the storage device controller is further configured to select a power level for a heat-assisted magnetic recording (HAMR) device based on the write attribute. |
| US10090011B2 |
Procedure for setting laser and heater power in HAMR device
A heater power of a heat-assisted magnetic recording head is set to an initial power to induce an initial head-medium clearance. For a plurality of iterations, a heater power at an optimum laser power is determined that achieve a target clearance. If differences in the heater power and optimum laser power between the two subsequent iterations are below a threshold, the iterations are stopped and the heater power and the optimum laser power for one of the two subsequent iterations is used as an operational heater power and laser power for the heat-assisted magnetic recording head. |
| US10090010B1 |
Using disk drive parallelism to increase drive capability while maintaining a baseline performance
A baseline performance of a disk drive is found based on a media speed and a bit aspect ratio of the drive. A parallelism architecture is chosen for the disk drive based on an end-use application of the drive. The parallelism architecture includes two heads capable of simultaneously accessing one or more disks of the disk drive. An increased performance of the disk drive is determined due to the parallelism architecture, and at least one of the media speed and bit aspect ratio are reduced such that a final drive performance with the parallelism architecture satisfies the baseline performance, the baseline performance being less than the increased performance. The reduction of the media speed and/or bit aspect ratio increases another capability of the drive over that of the equivalent drive. |