| Document | Document Title |
|---|---|
| US09742720B2 |
Intelligently sharing messages across groups
Identifying recipients to receive communication based on content selection may be provided. An indication of content selected by a user is received. The content may be part of group communication that is communicated among users via an online communication application. The content and an author of the content are identified. One or more criteria may be applied to the content to determine the recipients of the communication. The communication may be transmitted as a single message to the recipients simultaneously. |
| US09742718B2 |
Message optimization utilizing term replacement based on term sentiment score specific to message category
Techniques are described herein for predicting one or more behaviors by an email recipient and, more specifically, to machine learning techniques for predicting one or more behaviors of an email recipient, changing one or more components in the email to increase the likelihood of a behavior, and determining and/or scheduling an optimal time to send the email. Some advantages of the embodiments disclosed herein may include, without limitation, the ability to predict the behavior of the email recipient and suggest the characteristics of an email which will increase the likelihood of a positive behavior, such as a reading or responding to the email, visiting a website, calling a sales representative, or opening an email attachment. |
| US09742717B2 |
Internet e-mail bridge
An Internet mail bridge is provided for downloading e-mail messages from Internet mail servers supporting different email protocols, such as the Post Office Protocol 3 (POP3) and Web Distributed Authoring and Versioning (Web DAV) protocol, and delivering the downloaded messages, which are in different formats, to a mail server on a local area network. The Internet mail bridge has a mail manager that is independent from particular e-mail protocols or e-mail formats. For each e-mail account, the mail manager instantiates a mail connector object that contains logic for downloading e-mail according to the e-mail access protocol of that account, and invokes the mail connector object to download e-mail messages from that account. The mail manager then instantiates and invokes mail deliverer objects tailored for handling different message formats to deliver the downloaded messages to the local mail server. |
| US09742713B2 |
Apparatus and method for maintaining a message thread with opt-in permanence for entries
A server has a processor and a memory storing a message thread module with instructions executed by the processor to maintain a message thread between users of client devices. Message thread state changes are queued at the server. The message thread is revised based upon the message thread state changes to form shared message thread state. The shared message thread state is stored. The shared message thread state is supplied in response to a request for the message thread from a user. |
| US09742711B2 |
Communication systems and related methods for notifying devices having a plurality of unique identifiers about missed communications
Apparatuses and methods for notifying a group of communication devices about a missed call are disclosed. Each communication device is associated with a group identifier that is shared with all the communication devices in a group. Each communication device is also associated with an individual identifier that is unique to that communication device. An unanswered communication to the group identifier is received on all the communication devices in the group. A first communication device transmits to a remote server an acknowledgement notification that the unanswered communication related to the group identifier has been acknowledged by the user. A clear indicator indicating that the unanswered communication has been acknowledged is transmitted from the remote server to all the devices in the group except the first communication device. Each of the communication devices receiving the clear indicator can then clear its indicator that notifies the user of a missed call. |
| US09742704B2 |
Physical layer management at a wall plate device
One embodiment is directed to a wall plate device including one or more jacks. Each jack includes a rear attachment point configured to couple to one or more communication paths in a semi-permanent manner. Each jack also includes a front attachment point configured to mate with a connector of a corresponding physical communication media, and to couple such physical communication media to the rear attachment point. Each jack also includes a media reading interface configured to interface with a PLM interface of a connector connected to the front attachment point. The wall plate device also includes a programmable processor coupled to each of the media reading interfaces and configured to access a storage device of a connector connected to the front attachment point through the media reading interface to obtain PLM information. The programmable processor is configured to communicate the PLM information to another device. |
| US09742702B1 |
End-to-end cache for network elements
A method in a network element includes processing input packets using a set of two or more functions that are defined over parameters of the input packets. Each function in the set produces respective interim actions applied to the input packets and the entire set produces respective end-to-end actions applied to the input packets. An end-to-end mapping, which maps the parameters of at least some of the input packets directly to the corresponding end-to-end actions, is cached in the network element. The end-to-end mapping is queried with the parameters of a new input packet. Upon finding the parameters of the new input packet in the end-to-end mapping, an end-to-end action mapped to the found parameters is applied to the new input packet, without processing the new input packet using the set of functions. |
| US09742699B2 |
Network apparatus and selective information monitoring method using the same
The present invention presents a network apparatus and a selective information monitoring method using the network apparatus, which allow a user to monitor only required information (the field information of packets) from all received packets. The network apparatus one or more physical interfaces connected to a monitoring target host and configured to receive network packets from the monitoring target host, and a switch fabric module including a configurable monitoring module configured to perform filtering so that selective information is extracted from the network packets collected through the one or more physical interfaces. |
| US09742698B2 |
Switch and setting method
A disclosed switch includes: plural ports each of which is connected to another apparatus; a determination unit that determines, for each of the plural ports, whether the port is connected to one of plural switches integrated logically; and a setting unit that sets, for each of the plural ports, a port type or propriety of use based on a result of determination by the determination unit. |
| US09742689B1 |
Channel negotiation for a high speed link
Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices. |
| US09742685B2 |
Enhanced mechanisms for granting access to shared resources
Mechanisms are provided, in a data processing system comprising a plurality of nodes, each node being a computing device, for controlling access to a critical section of code. These mechanisms send, by a sender node of the data processing system, an access request for requesting access to the critical section of code. The critical section of code is a portion of code that accesses a shared resource. The mechanisms receive, in the sender node, from a plurality of receiver nodes in the data processing system, responses to the access request. Each response in the responses includes a number of active nodes perceived by a corresponding receiver node that transmitted the response. The mechanisms control, by the sender node, access to the critical section of code based on the number of active nodes identified in each of the responses received from the receiver nodes. |
| US09742684B1 |
Adaptive service scaling
Disclosed are various embodiments for a service scaling application. Requests for predicted future usage of a service are obtained. Resources required to satisfy the requests are calculated and aggregated. Growth functions facilitate determining usage of a service over time. An acquisition of resources is then generated from the required resources. |
| US09742681B2 |
Session-based traffic routing policies
The invention is directed to systems, methods and computer program products for optimizing a configuration associated with a network. An exemplary method comprises: determining a node of the network is running a data session associated with an amount of data greater than a predetermined amount of data, and associated with a duration greater than a predetermined duration; configuring the network such that the node acts as an access point; and establishing a direct connection between the access point and a backbone of the network. |
| US09742680B2 |
Configuring traffic allocations in a router
Disclosed herein are methods and calculators for configuring traffic allocations for service classes with different Quality of Service (QoS) in a router. Example embodiments involve setting allocations at a router based on traffic rate values and/or traffic weight values provided by a user. The router may monitor actual traffic rates to ensure that traffic is not being dropped due to improper rate allocations and to provide historical data for optimizing traffic allocations. In addition, the router may automatically adjust traffic allocations to avoid dropping high(er) priority traffic. The router may also transmit alarms to the user and/or to other network devices to prompt traffic re-routing and/or re-allocation of traffic rates. Example methods and apparatus ensure appropriate traffic allocation to meet certain QoS metrics. |
| US09742678B2 |
E-tree service with optimal forwarding in EVPN
In one embodiment, when an ingress provider edge (PE) device of a computer network domain receives a frame at the ingress PE device destined to a destination media access control (MAC) address, it can determine whether the frame was received on a root or leaf Ethernet ingress segment, and also whether the destination MAC address is located via a root or leaf Ethernet segment. Accordingly, the ingress PE device may either drop or forward the frame based on the ingress Ethernet segment and destination MAC address Ethernet segment being either a root or a leaf, respectively. |
| US09742677B2 |
Methods and apparatus for managing communications network loading
There is provided a method comprising estimating bit rate information for first traffic if said first traffic were to be routed between a user equipment which is attached to a first network and a network access point of a second network and determining if said first traffic is to be routed between said user equipment and said network access point in dependence on said estimated bit rate information. |
| US09742676B2 |
Highly available servers
Techniques for maintaining high availability servers are disclosed. For example, a method comprises the following steps. One or more client requests are provided to a first server for execution therein. The one or more client requests are also provided to a second server for storage therein. In response to the first server failing, the second server is configured to execute at least one client request of the one or more client requests provided to the first server and the second server that is not properly executed by the first server. |
| US09742673B2 |
Increasing multicast scale via localization of indices
A plurality of line cards with each line card having a respective network forwarding engine and a respective outgoing interface (OIF) list and at least one fabric module communicatively coupled with each line card with each fabric module can have a respective network forwarding engine. The local OIF list can be asymmetrically programmed. The network forwarding engine of a line card can be configured to receive a multicast packet, compare a multicast address associate with the received multicast packet with entries in the local OIF list of the line card and forward the received multicast packet to at least one interface associated with the multicast address in response to the comparison resulting in a match. |
| US09742672B1 |
Signaling priority information for encapsulated packets
In one example, an edge routing device of a service provider network includes one or more network interfaces configured to send and receive packets and a processing unit configured to retrieve, from a packet received via the one or more network interfaces, priority data from an Internet protocol (IP) header of the packet, form a first tag including a first set of data in a first priority field of the first tag, wherein the first set of data represents a first portion of the priority data, form a second tag including a second set of data in a second priority field of the second tag, wherein the second set of data represents a second portion of the priority data, encapsulate the packet with the first tag and the second tag, and forward, via the one or more network interfaces, the encapsulated packet. |
| US09742668B1 |
Packet forwarding path programming using a high-level description language
In general, this disclosure describes a high-level forwarding path description language (FPDL) for describing internal forwarding paths within a network device. The FPDL enables developers to create a template that describes a section of an internal forwarding path within the forwarding plane of a network device. The FPDL provides syntactical elements for specifying the allocation of forwarding path structures as well as enabling the run-time construction of internal forwarding paths to interconnect the forwarding path structures in a manner specific to packet, packet flow, and/or interface properties, for example. In conjunction with late binding techniques, whereby the control plane of the network device provides arguments to template parameters that drive allocation by the packet forwarding engines of forwarding path structures specified by the FPDL, the techniques provide control plane processes a unified interface with which to manage the operation of the packet forwarding engines. |
| US09742667B2 |
Packet processing method, device and system
The present application provides a packet processing method, device and system. A controller sends a first flow entry to a network device. The first flow entry comprises first importance information used for indicating importance of a first flow entry, where the first importance information is used by the network device to determine, according to a second importance information of a second flow entry in the flow table and the first importance information of the first flow entry, whether to add the first flow entry into a flow table of the network device when there is no idle flow entry resource in the flow table. |
| US09742665B2 |
Communication network control system, control method thereof, and non-transitory computer readable medium of control program
A communication network control system (1) eliminates, in a communication network (G) in which a plurality of nodes (Ni) are connected via a plurality of links (2), a node (Nx) having a trouble and implements a reconnection in the communication network (G). The nodes (Ni) each comprise: a path information calculation means (3) that calculates path information of the communication network (G) when a trouble occurs in an adjacent node (Nx); an order information calculation means (4) that calculates, for a set of reconnection destination candidate nodes (Ni), order information in which the reconnection destination candidate nodes are sequenced in order of inter-node distance on the path information calculated by the path information calculation means (3); and a determination information calculation means (5) that calculates, on the basis of the order information calculated by the order information calculation means (4), such a combination that the inter-node distance on the path information in the whole communication network (G) after the reconnection becomes larger and that determines the calculated combination as a reconnection destination node of the local node (Ni). |
| US09742664B2 |
System, method, and device for utilizing network connectivity by combining allocated bandwidth for optimized broadband access
A system for network aggregation/disaggregation includes an aggregation/disaggregation server; an aggregation/disaggregation router; and at least one carrier network; such that the aggregation/disaggregation router aggregates individual bandwidth subscriptions to provide an aggregated bandwidth local area network connection, which is accessed by a plurality of mobile devices. An aggregation/disaggregation router can include a processor; a non-transitory memory; an input/output; a proxy connection manager; a software-defined radio; a local area network manager; and a subscriber controller; all connected via a data bus. Also disclosed is a method of network aggregation/disaggregation, including creating proxy connections; aggregating proxy connections; accessing proxy connections; disaggregating inbound network data, wherein the aggregation/disaggregation server distributes data across a plurality of network connections; and aggregating outbound network data, wherein the aggregation/disaggregation server aggregates and routes outbound data to a final internet destination. |
| US09742662B2 |
Fabric discovery for a cluster of nodes
Implementations of discovery functionalities in accordance with the present invention are characterized by being exceptionally minimalistic. A primary reason and benefit for such minimalistic implementations relate to these discovery functionalities being implemented via a management processor and associated resources of a system on a chip (SoC) unit as opposed to them being implemented on data processing components of a cluster of nodes (i.e., central processing core components). By focusing on such a minimalist implementation, embodiments of the present invention allow discovery functionalities to be implemented on a relatively low-cost low-power management processor coupled to processing cores that provide for data serving functionality in the cluster of nodes. |
| US09742661B2 |
Uniform resource locator mapping and routing system and method
A uniform resource locator (URL) mapping and routing system and method for generating, routing, and managing URLs is used to route internet users to application landing pages or websites based on a URL mapping scheme. Routing instructions for the URL may route a user accessing a URL to a destination landing page or an alternate landing page depending on routing instructions in the URL mapping scheme. |
| US09742660B2 |
Validating a routing function
Certain examples described herein provide a system and method for validating a routing function for a network device. In one example, a network device has a run-time policy engine, wherein the run-time policy engine implements a routing configuration file and the routing configuration file defines a routing function for network traffic. A file editor is also provided that loads the routing configuration file. The file editor has an editor policy engine that duplicates a functionality of the run-time policy engine. In one example, the routing configuration file has at least one validation portion that has one or more route statements with definitions indicative of expected routing function behavior. The file editor parses the routing configuration file by implementing the routing configuration file using the editor policy engine. The editor policy engine applies the routing function defined by the routing configuration file to the one or more route statements and indicates where a result of the routing function does not conform to the definitions indicative of expected routing function behavior. These examples may help to reduce routing errors due to configuration errors in network devices. |
| US09742659B2 |
Multipath bandwidth usage
Embodiments of the present invention include systems and methods for identifying a primary flow and its corresponding subflow(s) so that the subflow(s) may be routed to more efficiently use bandwidth between a source host and a destination host. In embodiments, a table correlates flows and their corresponding keys for Multipath TCP flows. When a new subflow is initiated between a source device and a destination device, the new flow can be identified as being a subflow of a primary flow using data in the table. Having identified the subflow and its corresponding primary flow, the new subflow may have an installed route path that differs from its primary flow, thereby improving the bandwidth usage. |
| US09742658B2 |
Inter-medium bridging with inter-domain routing and multi-medium domain coordination
Various embodiments of inter-medium bridging are described. In one aspect, a method may involve a plurality of inter-domain bridging devices transmitting a message that describes inter-domain routing capability of the inter-domain bridging devices to a respective domain master of each of a plurality domains to which the inter-domain bridging devices are connected. The method may also involve the plurality of domain masters exchanging messages that describe the inter-domain routing capability of the plurality of inter-domain bridging devices connected to the respective domain of each domain master. The method may further involve each domain master determining one of the domain masters to serve as a global domain master for calculating inter-domain routing paths. |
| US09742654B1 |
Communication interface testing
Systems and methods are disclosed for testing performance of communications interfaces of computing devices. An electronic device tester is disclosed including a downstream communication interface configured to communicatively couple the electronic device tester to a device under test (DUT), wherein the electronic device tester is configured to identify a first internal hub of the DUT over the downstream communication interface, identify a second hub device connected to the DUT over a downstream interface port of the DUT, verify performance of the downstream interface port of the DUT at a first data rate by receiving data over a first downstream port of the second hub device via the downstream interface port of the DUT, and verify performance of the downstream interface port of the DUT at a second data rate by receiving data over a second downstream port of the second hub device via the downstream interface port of the DUT. |
| US09742645B2 |
Method and apparatus for measuring performance of multi-service in tunnel
Embodiments of the present application provide a method for measuring performance of multi-service in a tunnel, including: receiving a measurement message corresponding to a service packet, where a priority of the measurement message is the same as that of the service packet, and the measurement message includes at least one of the three: a packet loss measurement parameter, a delay measurement parameter, and a jitter measurement parameter; and measuring performance of a service in a tunnel according to a measurement parameter in the measurement message. According to the embodiments of the present application, a problem that performance measurement cannot be performed for different services transmitted in a tunnel in the prior art may be solved. |
| US09742644B2 |
Verification of connection of meters to network
To determine network coverage of a device within a network a user may send an instruction to the device using a mobile configuration tool of a mobile device. Upon receiving the instruction, the device of which the network coverage is to be determined may broadcast a message using a standard protocol, and listen to one or more responses from other devices in the network. In response to receiving the one or more responses, the device at issue may relay the one or more responses, or a processing result of the network coverage (determined based on the one or more responses) to the mobile configuration tool for display to the user. The user may determine whether the network coverage of that device meets one or more network coverage criteria and, if not, may take some corrective action. |
| US09742643B2 |
Methods, systems, and product for twisted tabulation
Methods, systems, and products describe a robust solution for the dictionary problem of data structures. A hash function based on tabulation is twisted to utilize an additional xoring operation and a shift. This twisted tabulation offers strong robustness guarantees over a set of queries in both linear probing and chaining. |
| US09742641B2 |
System and method for identifying real users behind application servers
A monitoring device and method for identifying the identity of users requesting database accesses. The data request from application servers to an application server are monitored and parsed. The SQL statements associated with the data request from the application server are also monitored and parsed, so are the SQL responses from the database server. The SQL responses are sent back to the user as data responses. The data responses are also monitored and parsed. The monitoring device matches the parsed data request with the parsed SQL statements, the parsed SQL responses, and the parsed data responses. By matching the string portion of these parsed data, the monitoring device can then identity the identity of the user making such data base request. |
| US09742636B2 |
Reliable address discovery cache
Reliable address discovery cache techniques are described. In an implementation, a reliable communication channel is established for control messages related to address resolution in a network. The communication channel is employed for communication of messages for internet protocol (IP) address acquisition, release, and mapping staleness between clients (e.g., nodes or endpoints) in the network and a cache manager component configured to maintain and update an address map for the clients. The cache manager component may also be configured to send directed messages via the communication channel to propagate changes in the mapping to the clients. Further, clients may provide explicit notifications regarding address release and staleness to the cache manager component to facilitate updating of the address map. In this way, a reliable and up-to-date address map is maintained and the amount of broadcast discovery messages and bandwidth consumed overall for address discovery operations may be reduced. |
| US09742634B2 |
System and method for automatically learning and maintaining IP address allocation topology
A topology map engine obtains, from a dynamic host control protocol relay device, a relayed request, of a client, for a dynamic host control protocol lease. The relayed request has at least one given IP address of the dynamic host control protocol relay device inserted therein. A search is made in a database for that IP address. If not found, dynamic host control protocol relay device information is obtained. This information includes: an identifier of the dynamic host control protocol relay device; and at least one network interface of the dynamic host control protocol relay device and any internet protocol addresses assigned to same. This information is obtained at the topology map engine and stored in the database. |
| US09742626B2 |
Methods and systems for multi-tenant controller based mapping of device identity to network level identity
A method includes executing at a controller a horizontally scalable service Identity Definitions Manager (IDM) Service, mapping active directory (AD) domains to WAN network elements DNS ROLE and LDAP ROLE, instructing a plurality of network elements associated with a tenant to discover a plurality of AD domains and AD servers in an enterprise using the DNS ROLE, receiving from the plurality of network elements running DNS ROLE information indicative of changes to network attributes selected from the group consisting of AD domains, additions and subtractions of AD servers and changes in an IP address of AD servers and transmitting the received AD domains and AD servers to a tenant administrator and requesting credentials to communicate with added AD servers using LDAP. |
| US09742625B2 |
Automated electronic computing and communication system event analysis and management
Systems, apparatuses, and methods for automatic automated electronic computing and communication system event analysis and management are disclosed. Automatic automated electronic computing and communication system event analysis and management may include identifying an event, generating a computer readable representation of the electronic computing and communication system using automated topology enumeration, identifying an element of the electronic computing and communication system based on the representation, identifying a metric for the element, automatically investigating to determine a value for the metric, generating a remediation priority for the element based on a metric weight associated with the metric and a network layer value associated with a network layer associated with a network layer role associated with the element, and generating a graphical representation of the electronic computing and communication system indicating the remediation priority. |
| US09742624B2 |
Logging incident manager
Systems, methods, and other embodiments associated with intelligently processing log messages are described. In one embodiment, a computer-implemented method includes analyzing, by a logging appliance that includes at least hardware, communications received from a plurality of handlers to determine whether at least one of the communications indicates an error has been encountered by one of a plurality of components associated with the plurality of handlers. The method includes scheduling a subset of the plurality of handlers to provide reports that include a detailed set of log messages in response to detecting the error. The subset of the plurality of handlers includes handlers that are associated with the error. |
| US09742617B2 |
Virtual machine migration in a cloud fabric
Technologies are generally described for systems and methods configured to migrate a virtual machine. Some systems may include a memory configured to store terms of a service level agreement for a first virtual machine. The first computing device may determine the terms of the service level agreement for the first virtual machine. The first computing device may be configured to determine that the first virtual machine is operating on the first computing device using operating resources in violation of the terms of the service level agreement. The first computing device may be configured to identify a second virtual machine operating on the first computing device. The first computing device may be configured to migrate one of the first virtual machine or the second virtual machine to a second computing device in response to the determination of the violation. |
| US09742612B2 |
Method and device for transmitting data by using multidimensional constellation diagram
Embodiments of the present invention relate to the field of communications, and provide a method and a device for transmitting data by using a multidimensional constellation diagram, which can further improve bit error rate-signal to noise ratio performance by means of a multidimensional constellation diagram. The method is: First, bit data is mapped, by using an n-dimensional constellation diagram, into a column vector including n real numbers, then the n real numbers included in the column vector are modulated by using a resource element and sent, and after demodulating the n real numbers from a received signal, a receiving device finds, in the n-dimensional constellation diagram, a constellation point with coordinate values having a closest Euclidean distance to a point with coordinates being the n real numbers, and finally maps the coordinate values of the constellation point back into the bit data. |
| US09742609B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data. |
| US09742606B2 |
Pilot design for OFDM systems with four transmit antennas
Pilot, preamble and midamble patterns are provided that are particularly suited for four transmit antenna OFDM systems. Pilots are inserted in a scattered manner for each of the four antennas, either uncoded, space-time coded in pairs, space-time frequency coded in pairs, or space-time-frequency coded. |
| US09742603B1 |
Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces
In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal. |
| US09742602B2 |
High-speed signaling systems with adaptable pre-emphasis and equalization
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. |
| US09742599B2 |
Partial response signaling techniques for single and multi-carrier nonlinear satellite systems
New partial response signaling systems and methods for high spectral efficiency communications are described. In a first implementation, a communication system includes a partial response signaling transmitter and a nonlinear satellite transponder. The partial response signaling transmitter includes a partial response transmit filter configured to convert complex-valued data symbols to a transmit signal using a partial response pulse shaping function; and a modulator configured to modulate the transmit signal onto a carrier wave. The transponder receives and non-linearly amplifies the modulated transmit signal for broadcast to receivers. In a second implementation, a receiver includes circuitry for downconverting a received input signal; a partial response filter with a partial response impulse function for filtering the downconverted signal; circuitry for downsampling the partial response filtered signal; circuitry for equalizing the downsampled signal; and a linear and non-linear interference cancellation module including circuitry for removing linear and non-linear ISI in the input signal. |
| US09742598B2 |
System information convolutional decoding
A mobile communication device may include a radio transceiver configured to transmit and receive communication signals, and a baseband modem circuit configured to determine a decoded information field of a first encoded system information packet, set one or more bits of the decoded information field as an initial encoder state of a convolutional decoder for decoding the first encoded system information packet, decode the first encoded system information packet with the initial encoder state to obtain a first decoded system information packet, and use the decoded system information packet to transmit or receive data with one or more network cells. |
| US09742583B2 |
Method of data retransmission in collaborative service transmission and access network gateway thereof
The present invention discloses a method of data retransmission in coordination service transmission and access network gateway thereof. Wherein, the method includes: in coordination service transmission, access network gateway receives the service data requested by the coordination terminal, caches the data and transmits it to the corresponding destination terminal; the access network gateway executes retransmission strategy, and when decides data retransmission is needed, retransmits the cached data to the corresponding destination terminal. The access network gateway is used to receive the service data requested by the coordination terminal, to cache the data and transmit it to the corresponding destination terminal, to retransmit the cached data to the corresponding destination terminal when data retransmission is needed. Using the present invention, to the problem of service data retransmission in coordination service transmission, the service data transmission efficiency is effectively improved. |
| US09742580B2 |
Wireless control device
A wall-mountable wireless control device may include an antenna (e.g., a slot antenna or a hybrid slot-patch antenna) for transmitting and/or receiving radio-frequency signals. The wireless control device may comprise a user interface, an antenna, a radio-frequency communication circuit, a control circuit, and/or a conductive faceplate. The radio-frequency communication circuit may be configured to transmit or receive radio-frequency signals via the antenna. The user interface may be configured to receive a user input. The conductive faceplate may be configured to operate as a radiating element of the antenna when the conductive faceplate is mounted to the wireless control device and the user interface is received in the opening of the conductive faceplate. The conductive faceplate may comprise a conductive material arranged over a plastic carrier, for example, the conductive material may be provided adjacent to greater than or equal to approximately 85% of the front surface. |
| US09742569B2 |
System and method for filtering digital certificates
One example discloses a system for filtering digital certificates within a communications network, comprising: a first set of network-nodes, having a first attribute and a respective first set of digital certificates; a second set of network-nodes, having a second attribute and a respective second set of digital certificates; and a digital certificate authority, having a digital certificate validity list which includes the first and second sets of digital certificates; wherein the certificate authority filters the validity list based on the first attribute and transmits the filtered validity list to the first set of network nodes. Another example discloses a method for filtering digital certificates, comprising: maintaining a digital certificate validity list; identifying a set of network-nodes, having an attribute; filtering the validity list based on the attribute; and transmitting the filtered validity list to the set of network-nodes. |
| US09742568B2 |
Trusted support processor authentication of host BIOS/UEFI
An information handling system (IHS) prevents execution of corrupted bootup instructions in flash memory. A memory component contains basic input/output system (BIOS) instructions to execute during boot up of the IHS. A host processor is in communication with the memory component via the system interconnect to execute the BIOS instructions to configure the IHS. A support processor executes instructions to configure the IHS to: (a) calculate a current hash value for the BIOS instructions; (b) access a trusted encrypted hash value and the unique key from a secure storage; (c) decrypt the trusted encrypted hash value using the unique key to obtain a trusted hash value; (d) determine whether the current hash value is identical to the trusted hash value; and (e) allow execution of the BIOS instructions by the host processor in response to determining that the encrypted current hash value is identical to the trusted hash value. |
| US09742566B2 |
Homomorphic evaluation including key switching, modulus switching, and dynamic noise management
Homomorphic evaluation of a function is performed on input ciphertext(s), which were encrypted using a public key of an encryption scheme that also includes multiple secret keys and multiple integer moduli. The homomorphic evaluation of the function includes performing operations(s) on the input ciphertexts. The function includes operation(s) including one or more of addition, multiplication, and automorphism. A key-switching transformation is performed on selected input ciphertext(s), and includes converting a first version of a selected ciphertext with respect to a first of the multiple secret keys and a first modulus to a second version of the selected ciphertext with respect to a second of the multiple secret keys and a second modulus, where the second modulus is an integer factor p times the first modulus, p>1. Each of the key switching transformations is performed prior to or after the operation(s) are evaluated. Results of the operation(s) are output. |
| US09742564B2 |
Method and system for encrypting data
A processing device may generate a data encryption key configured to encrypt unique data within a clone of an encrypted data set and associated with a set of transaction identifiers of a transaction based file system. The processing device may further wrap the data encryption key with a wrapping key, create a cloned encrypted data set with the data encryption key, and store the wrapped data encryption key with the cloned encrypted data set indexed by at least one of the set of transaction identifiers. |
| US09742562B2 |
Key derivation for a module using an embedded universal integrated circuit card
A module with an embedded universal integrated circuit card (eUICC) can include a received eUICC profile and a set of cryptographic algorithms. The received eUICC profile can include an initial shared secret key for authentication with a wireless network. The module can receive a key K network token and send a key K module token to the wireless network. The module can use the key K network token, a derived module private key, and a key derivation function to derive a secret shared network key K that supports communication with the wireless network. The wireless network can use the received key K module token, a network private key, and the key derivation function in order to derive the same secret shared network key K derived by the module. The module and the wireless network can subsequently use the mutually derived key K to communicate using traditional wireless network standards. |
| US09742561B2 |
Secure remote authentication of local machine services using secret sharing
A method for authentication of a computing device so that shares of a secret may be delivered, over a network that uses a communications protocol which does not require use of an address, and on which an authentication server is listening, comprising the steps of dividing the secret into a first share and a second share, or more; destroying the secret; transmitting the second share, together with a unique identifier, out of band to a pre-designated location; erasing the second share from the computing device; storing the first share at the computing device; broadcasting the unique identifier over the network; accepting a request over the network from an authentication server to initiate an authentication protocol; responding to the request; receiving the second share from the authentication server; and reconstructing the secret using the received second share and the stored first share. |
| US09742557B2 |
Compressing encrypted data without the encryption key
A method, system and computer program product are disclosed for compressing encrypted data, wherein the data is encrypted by using a block encryption algorithm in a chained mode of operation, and the encrypted data is comprised of a set of N encrypted blocks, C1 . . . CN. In one embodiment, the method comprises leaving block CN uncompressed, and compressing all of the blocks C1 . . . CN in a defined sequence using a Slepian-Wolf code. In an embodiment, the data is encrypted using an encryption key K, and the compressing includes compressing all of the blocks C1 . . . CN without using the encryption key. In one embodiment, the compressing includes outputting the blocks C1 . . . CN as a set of compressed blocks CmprC1 . . . CmprCN-1, and the method further comprises decrypting CN to generate a reconstructed block {tilde over (X)}n, and decrypting and decompressing the set of compressed blocks using {tilde over (X)}n. |
| US09742554B2 |
Systems and methods for detecting a synchronization code word
Systems and methods for detecting a synchronization code word embedded in a plurality of frames of a signal are described. In one example embodiment, the synchronization code word contains “s” bits, embedded one bit per frame in “s” frames of an input signal. The method of detecting this synchronization code word includes: initiating a first segmentation procedure wherein “n” segments are defined in each signal frame of the input signal. A first correlation threshold value, which is based on the synchronization code word, is used to identify in the “n” segments, a first segment having the highest likelihood of containing at least a portion of the synchronization code word. The first segment is used to initiate a recursive detection procedure incorporating one or more additional segmentation procedures and one or more additional correlation threshold values, to detect the synchronization code word in a sub-divided portion of the first segment. |
| US09742553B2 |
Transmission apparatus and plug-in unit
A transmission apparatus includes: a first plug-in unit including: a clock generator to generate a first clock, a first frame-pulse generator to generate a first frame-pulse-signal based on the first clock; a detector to detect a phase-difference between a first phase of the first frame-pulse-signal and a second phase of a second frame-pulse-signal transmitted from other plug-in unit, and generate phase-difference information based on the phase-difference, and a first transmitter to transmit a control-signal including the phase-difference information to the other plug-in unit; and a second plug-in unit being the other plug-in unit, including: a receiver to receive the control-signal, a controller to control a phase of a second clock of the second plug-in unit, based on the phase-difference information, a second frame-pulse generator to generate the second frame-pulse-signal based on the second clock, and a second transmitter to transmit the second frame-pulse-signal to the first plug-in unit. |
| US09742545B2 |
Method for transmitting control information in wireless communication system and apparatus therefor
A method is provided for generating Acknowledgement/Negative Acknowledgement (ACK/NACK) information at a user equipment in a wireless communication system. The user equipment receives a plurality of codewords corresponding to data blocks through a plurality of downlink carriers from a base station, wherein each of the plurality of downlink carriers carries one or more codewords. The user equipment generates the ACK/NACK information by concatenating ACK/NACK bits corresponding to the plurality of codewords. When a corresponding downlink carrier carries two or more codewords, the ACK/NACK bits corresponding to the two or more codewords associated with the corresponding downlink carrier are concatenated in accordance with an index order of a corresponding data block. The ACK/NACK bits concatenated in accordance with the index order of the corresponding data block associated with each of the downlink carriers are concatenated again in accordance with an index order of a corresponding downlink carrier. |
| US09742539B2 |
Method and apparatus for transmitting uplink
A method, performed by a user equipment (UE), is provided for uplink transmission. The UE determines transmission power of a sounding reference signal (SRS) toward a first cell belonging to a first timing advance group (TAG) and a physical uplink shared channel (PUSCH) toward a second cell belonging to a second TAG and whether to transmit both the PUSCH and the SRS, or drop the SRS. The UE transmits only the PUSCH but drops the SRS when the UE determines that the plurality of TAGs including the first and second TAGs are configured, that at least one symbol of a first subframe which is used to transmit the SRS toward the second cell of the second TAG is overlapped with a second subframe on which the PUSCH is transmitted toward the first cell of the first TAG and that a total uplink transmission power exceeds a maximum value. |
| US09742538B2 |
Automatic configuration sub-system for distributed antenna systems
Systems and methods for automatically configuring a distributed antenna system are provided. A configuration sub-system of the distributed antenna system can identify signal parameters for downlink signals received from one or more base stations via inputs of a unit in the distributed antenna system. The configuration sub-system can automatically determine a configuration plan for the distributed antenna system based on the automatically identified signal parameters. The configuration plan specifies how to combine subsets of the downlink signals for routing to remote antenna units of the distributed antenna system. |
| US09742537B2 |
Terminal device, base station device, integrated circuit, and wireless communication method
A subframe in a certain cell that satisfies criteria which includes at least a criterion (i) is regarded as being valid as a CSI reference resource. In a case where, in the criterion (i), information which is signaled on a PDCCH and that indicates an UL-DL configuration for a cell is detected, the UL-DL configuration for the cell is given by the information. In a case where, in the criterion (i), the information is not detected, the UL-DL configuration for the cell is same as an UL-DL configuration that is indicated by a higher layer parameter. The criterion (i) stipulates that, in a case where multiple cells with different UL-DL configurations are aggregated and the terminal device is not capable of simultaneous reception and transmission in the multiple cells, a subframe in a primary cell is a DL subframe or a special subframe that is indicated by an UL-DL configuration for the primary cell. |
| US09742528B2 |
Method and arrangement for reducing the amount of messages sent in a communication network
The invention relates to a method and an arrangement for reducing the amount of messages sent in a communication network comprising a first communication network entity, a second communication network entity connected to said first communication network entity over a communication interface and one or more user equipments connected to said second communication network entity over a radio interface, whereby messages are sent on said interfaces using at least a first and a second protocol. General rules are provided for sending first protocol messages packed inside second protocol messages, so called “piggybacking”, and each first protocol message is provided with an instruction field defining a co-ordination of procedure steps to be taken for performing an action. |
| US09742520B1 |
Optical switching system with a colorless, directionless, and contentionless ROADM connected to unamplified drop channels
Components of an optical communications network are described at a node of the network providing switching from one or more degrees of received optical signal routed to a plurality of receivers. The switch at the node generally includes a passive reconfigurable optical add drop multiplexer (ROADM) having drop or output ports that connector to optical channels leading to optical receivers without optical amplifiers between the ROADM outputs and the receivers. Configurations of the node and corresponding parameters are described that provide for use of lower cost components due to the absence of an array of optical amplifiers connected to the ROADM outputs. |
| US09742519B2 |
Photonic cross-connect with reconfigurable add-drop-functionality
A photonic cross-connect arrangement is presented which is able to cope with the transmission of super-channels, wherein complete super-channels are dropped and added to change a direction of transport. At least a cyclic filter is used in a drop-branch of a cross-connect for dividing a super-channel into sub-channels and/or at least a further cyclic filter is used in an add-branch to configure a super-channel. |
| US09742518B2 |
Flexible interconnection of scalable systems integrated using optical networks for datacenters
A network capable of being used in a datacenter is described. In some embodiments, the network can comprise a set of optical fiber rings, wherein each optical fiber ring carries data traffic on one or more wavelengths, and wherein each optical fiber ring is partitioned into multiple sectors. A reconfigurable optical add-drop multiplexer (ROADM) can be coupled to at least one optical fiber in each of at least two sectors. An electro-optical-switch can be coupled to each ROADM in each of the at least two sectors. A set of switches can be coupled to each electro-optical-switch in each of the at least two sectors. The set of switches can comprise a first layer of aggregation switches that is coupled to a second layer of edge switches, wherein the edge switches can be coupled to servers in a datacenter. |
| US09742516B2 |
Method and system for control format detection in heterogeneous cellular networks
A user equipment having a first mechanism to obtain a control region size of a sub-frame of a cell, the user equipment having a processor; and a communications subsystem, wherein the processor and communications subsystem are configured to cooperate to: determine having a first mechanism to obtain a control region size of a sub-frame of the first cell, second cell, or both, whether the user equipment is within an area of the second cell; and utilize, a second mechanism to obtain a control region size of a sub-frame of the second cell while the user equipment is within the area of the second cell. |
| US09742513B2 |
Transmission apparatus and clock regeneration method
A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock. |
| US09742512B2 |
Broadcast content preview notification in wireless communication networks
A system including a wireless communication network entity and a wireless terminal having a broadcast receiver for receiving content. The network entity is, for example, a broadcast content provider and/or a wireless communication network. A process includes sending preview information to the terminal wherein the preview information references content not yet received by the wireless terminal, and sending expiration notification information metadata for the content referenced by the preview information wherein the expiration notification metadata enables presentation of content expiration information on a user interface of the terminal. |
| US09742509B2 |
Apparatus and method in radio communications system
An apparatus and a method in a radio communications system. The apparatus in the radio communications system includes an estimation unit and a statistics collection unit. The estimation unit is used for estimating a signal receiving strength of each of multiple transmission positions, compared with a signal transmission strength of each of one or more possible transmission positions of a first-type node of a to-be-test communications system on a transmission resource block. The statistics collection unit is used for collecting, according the estimation result, statistics on power space distribution of the first-type node of the to-be-tested communications system. |
| US09742506B2 |
Terminal device, control device, fault diagnosis system, and fault diagnosis method
A state updating unit updates first information stored in a storage unit whenever the state of a control unit transitions from an idle state to an active state or from the active state to the idle state. A second power supply unit induces electric power from radio waves received by the antenna unit. An information acquiring unit operates after receiving the supply of electric power from the second power supply unit, acquires second information indicating whether electric power is supplied from the first power supply unit, acquires the first information from the storage unit, and transmits the acquired first and second information to the control device. A diagnosing unit diagnoses faults in the terminal device based on the first and second information transmitted from the information acquiring unit of the terminal device. |
| US09742505B2 |
Testing device and testing method thereof
A testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is electrically coupled with a plurality of communication devices under tests (DUTs) synchronously. The processor determines a schedule for the communication DUTs and tests the communication DUTs according to the schedule. A testing method is applied to the testing device to implement the operations. |
| US09742500B2 |
Optical transmission apparatus and optical signal processing method
An optical transmission apparatus includes an amplifier array device; and a switch device coupled to the amplifier array device via an optical cable, wherein the amplifier array device includes a plurality of amplifiers configured to amplify a plurality of optical signals at mutually different wavelengths and to output the plurality of amplified optical signals, a plurality of beam separators configured to generate a plurality of separated light beams by separating the plurality of amplified optical signals and to output the plurality of separated light beams, a beam combiner configured to generate combined light by combining the plurality of separated light beams and to output the combined light to the switch device through the optical cable, and a photo-detector configured to detect a power of the combined light returned from the switch device through the optical cable. |
| US09742499B2 |
Adaptive signaling based MFSK modulation scheme for ultrasonic communications
An ultrasonic communication circuit is disclosed. The circuit includes an ultrasonic transmitter arranged to transmit a training signal having a frequency to a remote transceiver over an ultrasonic communication channel. An ultrasonic receiver is arranged to receive information from the remote transceiver in response to the training signal. The ultrasonic transmitter is arranged to transmit a data signal to the remote transceiver. The data signal has a duty cycle determined by the information. |
| US09742493B2 |
Reconstructing light-based communication signals captured with a rolling shutter image capture device
Methods and systems are described for sampling an LCOM message and accurately reconstructing the entire LCOM message using a light receiver (e.g., digital camera) of a typical mobile computing device, such as a smartphone, tablet, or other mobile computing device. These including receiving segments of an LCOM signal from at least two repetitions of the LCOM signal. The location of each segment within the LCOM signal is identified and each segment is stored in a corresponding location in a buffer configured to have a length equal to the LCOM signal. The buffer is a ring buffer, in some embodiments. |
| US09742492B2 |
Systems and methods for ad-hoc networking in an optical narrowcasting system
Systems and methods for optical narrowcasting are provided for transmitting various types of content. Optical narrowcasting content indicative of the presence of additional information along with identifying information may be transmitted. The additional information (which may include meaningful amounts of advertising information, media, or any other content) may also be transmitted as optical narrowcasting content. Elements of an optical narrowcasting system may include optical transmitters and optical receivers which can be configured to be operative at distances ranging from, e.g., 400 meters to 1200 meters. Moreover, the elements can be implemented on a miniaturized scale in conjunction with small, user devices such as smartphones, thereby also realizing optical ad-hoc networking, as well as interoperability with other types of data networks. Optically narrowcast content can be used to augment a real-world experience, enhance and/or spawn new forms of social-media and media content. |
| US09742488B2 |
Modular, expandable system for data reception and distribution
A satellite reception assembly may comprise a first module operable to demodulate a first one or more channels of a signal output by a direct broadcast satellite (DBS) low noise block downconverter (LNB). The first module may output a signal to a second module which may demodulate a second one or more channels of the signal output by the DBS LNB. The second module may be installed after the satellite reception assembly has been deployed upon a number of clients served by the satellite reception assembly reaching a threshold. |
| US09742487B2 |
Systems and methods for shared analog-to-digital conversion in a communication system
Methods and systems for frequency generation may comprise in a low-noise block down-converter (LNB) comprising an analog-to-digital converter (ADC) and a channel stacking switch (CSS): receiving a first satellite signal centered at a first frequency; receiving a second satellite signal centered at a second frequency; combining the first and second satellite signals to form a combined signal; the analog-to-digital converter transforming the combined signal from an analog signal to a digital signal; providing the digital signal to the CSS; receiving a third satellite signal centered at a third frequency; receiving a fourth satellite signal centered at a fourth frequency; translating the third satellite signal to a fifth frequency, combining the translated third satellite signal with fourth satellite signals to form a second combined signal; a second analog-to-digital converter transforming the combined signal from an analog signal to a second digital signal; and providing the second digital signal to the CSS. |
| US09742486B2 |
High temperature operation of an airborne satellite terminal
Methods, systems, and devices are described for operating an airborne satellite terminal in high temperature conditions. In one method, a satellite terminal is located within an enclosure beneath a radome on an exterior of an aircraft. The satellite terminal includes a transmit amplifier that may operate in different power modes, a temperature sensor thermally coupled with the transmit amplifier, and an antenna. A transmit signal is amplified using the transmit amplifier to generate an amplified signal, which signal may be transmitted through the radome using the antenna. The temperature of the transmit amplifier may be monitored with the temperature sensor while transmitting the amplified signal. Operation of the transmit amplifier may be switched from a normal power mode to a reduced power mode to reduce a power level of the amplified signal when the monitored temperature of the transmit amplifier exceeds a temperature threshold. |
| US09742483B2 |
Relaying device
A relaying device includes a wireless apparatus interface, a signal processing unit connected to the wireless apparatus interface, a network interface, and a packet processing unit connected to the network interface. The relaying device is provided with multiple communication paths including the wireless apparatus interface, the signal processing unit, and the packet processing unit, and each communication path has a mixing unit configured to additively synthesize an uplink audio signal and a downlink audio signal of other communication path to the uplink audio signal and input the synthesized signal to the packet processing unit, and configured to additively synthesize an uplink audio signal and a downlink audio signal of other communication path to the downlink audio signal and input the synthesized signal to the signal processing unit. |
| US09742482B2 |
Wireless communication device with switched polarization and methods for use therewith
A wireless communication device includes a polarity setting module configured to set a plurality of polarity modes for the wireless communication with the plurality of external devices. The plurality of polarity modes includes selected ones of at least: a first polarity mode, and a second polarity mode. The polarity setting module sets the plurality of polarity modes based on information received from the plurality of external devices. A framing module is configured to generate data for transmission to the plurality of external devices based on the plurality of polarity modes set by the polarity setting module. |
| US09742475B2 |
Proximity beacon
A system and method are provided in which a radio-frequency channel is used in combination with a second validation channel to verify the proximity of two devices to each other. An RF channel is used to detect whether two devices are within a first, larger distance from one another and to enable communication between the two devices, whilst a second, validation channel is used to accurately verify that the two devices are within second, smaller distance from one another. In some embodiments, the second verification channel is a magnetic channel. |
| US09742471B1 |
NFMI based synchronization
One example discloses an apparatus for synchronization, including: a first wireless device, having a first device profile, a near-field magnetic induction (NFMI) signal input and a wireless signal input; wherein the first wireless device is configured to, receive, through the wireless signal input, a first set of data; optimize the first set of data based on the first device profile; receive, through the NFMI signal input, a second set of data optimized for a second device profile of a second wireless device; and synchronize the first and second sets of optimized data based on a set of common data attributes. |
| US09742470B2 |
Device for authenticating wanted NFC interactions
An electronic device that includes a sensor module, a measuring module and a near field communication (NFC) device. The sensor module receives an input signal. The measuring module measures the strength of the input signal and determines whether the input meets a predefined threshold. If the strength of the input signal meets the predefined threshold, the measuring module activates the NFC device. If the strength of the input signal does not meet the predefined threshold, the measuring module de-activates the NFC device. |
| US09742466B2 |
MOSCAP-based circuitry for wireless communication devices, and methods of making and using the same
A wireless (e.g., near field or RF) communication device, and methods of manufacturing and using the same are disclosed. The wireless communication device includes a receiver and/or transmitter, a substrate with an antenna thereon, an integrated circuit, and one or more continuity sensors. The antenna receives and/or backscatters a wireless signal. The integrated circuit processes the wireless signal and/or information therefrom, and/or generates the wireless signal and/or information therefor. The continuity sensor(s) are configured to sense or determine the presence of a chemical or substance in the package or container, and thus a continuity state of a package or container on which the communication device is placed or to which the communication device is fixed or adhered. The continuity sensor(s) are electrically connected to a set of terminals of the integrated circuit different from the set of terminals to which the antenna is electrically connected. |
| US09742464B2 |
Apparatus and method for semi-circular routing for transmission line signals
An information handling system includes a stripline transmission line, the stripline transmission line including a plurality of conductors, each one of the conductors having a mitigation conductor section and a non-mitigation conductor section. The mitigation conductor section includes a first linear section having a first side surface and a second side surface, and a plurality of substantially semi-circular stubs extending from the first side surface of the first liner section. The mitigation conductor section is configured to mitigate near end cross talk between the mitigation conductor section and adjacent conductors. |
| US09742463B2 |
Copper wire interface circuit
A copper wire interface circuit is provided, where a current output amplifier is connected to a port impedance component and a transmit end, and the current output amplifier is configured to amplify a to-be-transmitted signal; the port impedance component is connected to a high-pass filter, impedance, after undergoing impedance transformation performed by the high-pass filter, of the port impedance component is used for performing impedance matching with equivalent impedance of a cable and a load; the high-pass filter is connected to the port impedance component and the cable, the high-pass filter is configured to filter the to-be-transmitted signal or a received signal and perform impedance transformation on the port impedance component; and an echo cancellation module is connected to the port impedance component and a receive end. |
| US09742458B2 |
Protective cover for a tablet computer
A protective cover for a tablet computer is disclosed, which comprises a back cover and a front cover. The front cover includes an input side and a connector including a planar portion and a coupler for removably connecting the front cover to the back cover. The planar portion engages at least portion of a front surface of the tablet computer and the coupler engages an edge of the back cover. |
| US09742457B2 |
Electronic device privacy case
An electronic device privacy case. The electronic device privacy case includes a tray configured to store an electronic device having a display. A pair of foldable side panels extend upward from the tray and connect to support members, each of which are hingedly connected at one end to the tray via a locking hinge. A top panel is slidably disposed within channels in the support members and connected at one end to a rotatable shaft disposed in a housing attached to one end of the tray. The top panel may be retracted and rolled up along the rotatable shaft or may be extended to obscure the display from view. Further, the foldable side panels may be in a stored configuration within the tray, or may be lifted to a deployed configuration in order to prevent other individuals in public from viewing the display of the electronic device. |
| US09742454B2 |
Method, apparatus and terminal for electromagnetic radiation conversion
A method, an apparatus and a terminal for electromagnetic radiation conversion relates to the field of electromagnetic radiation protection technique, the method includes the steps of receiving a high frequency electromagnetic radiation by a high frequency receiving module, converting the high frequency electromagnetic radiation into a low frequency electromagnetic radiation by a frequency conversion module, and emitting, by a low frequency emission module, the low frequency electromagnetic radiation converted by the frequency conversion module. The method, apparatus and terminal for electromagnetic radiation conversion can be used to convert the harmful electromagnetic radiation emitted by the terminal into the electromagnetic radiation which benefits the human health and can also have a cosmetic effect. |
| US09742452B2 |
Receiver, receiving method for receiving RF signal in superheterodyne system
A local oscillator outputs a local oscillator signal that provides an upper side heterodyne mode or a lower side heterodyne mode for a received RF signal. A first converter converts the received RF signal into an IF signal, based on the local oscillator signal output from the local oscillator. An FM detector subjects the IF signal produced by conversion to detection. A first measurement unit measures a signal intensity of the IF signal before the IF signal is input to the FM detector. A second measurement unit measures a squelch voltage of a signal detected by the FM detector. A controller that controls the local oscillator based on the signal intensity measured by the first measurement unit and the squelch voltage measured by the second measurement unit. |
| US09742449B2 |
Wireless receiver
A wireless receiver includes an RSSI generation circuit that obtains RSSI output corresponding to a carrier strength level of a received RF signal; a lookup table from which a threshold value corresponding to temperature information from a temperature sensor is read based on the temperature information; a comparison circuit that generates comparison output when the RSSI output is below the threshold value read from the lookup table, in which the threshold value is one input, and the RSSI output from the RSSI generation circuit is the other input; and a muting circuit that closes a signal line of an audio signal demodulated from the RF signal, and cuts off output of the audio signal, based on the comparison output from the comparison circuit. The above configuration enables the wireless receiver to eliminate fluctuation of a reception reaching distance relative to temperature change, and ensure stable mute operation. |
| US09742448B1 |
Channelized multicarrier digitizer
A method is provided for individually processing multiple frequency bands in a composite RF signal is disclosed. The composite RF signal is separated into a plurality of gain controlled and bandlimited frequency bands. The gain controlled and bandlimited frequency bands are then recombined to produce a controlled composite RF signal, which is then digitized by undersampling with an ADC to produce a plurality of unambiguous frequency bands convolved around baseband. The sample frequency can be substantially less than the Nyquist Limit of twice the highest frequency present for digitization. Each baseband signal is monitored for amplitude spikes therein. In response to an amplitude spike, the appropriate frequency band is modified by a control signal to hold the ADC to within its dynamic range. |
| US09742445B1 |
High power radio frequency amplifier architecture
A solid-state amplifier architecture is disclosed. In some embodiments, the disclosed architecture may include first and second channel chipsets configured to amplify either the entire instantaneous frequency band of a radio frequency (RF) input signal or, respectively, sub-bands thereof, which may be divided proportionally between the two chipsets. In some cases, the chipsets may be configured to amplify frequencies in excess of the entire K-band and Ka-band frequencies simultaneously. In some cases, the architecture may be configured to address a signal received, for instance, from an electronic warfare (EW) system to a log amplifier stage configured to output a signal to the EW system, in response to which the EW system may generate a RF signal for amplification by the architecture for transmission. To facilitate heat dissipation, the architecture may be coupled, in part or in whole, with a thermally conductive carrier, optionally with an intervening diamond heat spreader layer. |
| US09742443B2 |
Pulse shaping for radio frequency transmitters
Transients caused by load modulation can fee compensated far by adjusting pulse shapes. A radio frequency (RP) carrier signal can be modulated using load modulation. For the modulated RF carrier signal a particular pattern can be detected for a symbol period that precedes a second symbol that does not use load modulation. In response to the detecting, a pulse shape of the first symbol can be adjusted to mitigate the transients. |
| US09742440B2 |
HARQ rate-compatible polar codes for wireless channels
A method, apparatus, and chipset are provided for constructing hybrid automatic repeat request (HARQ) rate-compatible polar codes for communication channels. The method includes constructing, in a terminal, a base polar code of length 2n; and determining a sequence of m<2n bits to puncture in the base polar code by testing a predetermined criterion at most (22n+2n)/2−1 times. |
| US09742433B2 |
Communication of user specific control information in a wireless network
A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0. |
| US09742432B2 |
Accelerometer data compression
A method of compressing data output from one or more accelerometers configured to be transported, carried or worn by a user is provided. Acceleration values indicative of the movement of the user are measured at a first frequency and values representative of the measured acceleration values are generated at a second frequency, which is lower than the first frequency. The step of generating comprises: defining a plurality of time windows, each time window containing a plurality of measured acceleration values; and applying a transformation to the measured acceleration values within each time window to generate a plurality of transformed values. For each time window, storing at least one of said plurality of transformed values and/or one or more parameters associated therewith. |
| US09742431B1 |
Quaternary decoder
Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state. |
| US09742430B1 |
System and method for analog to digital conversion
In some embodiments, a method of operating a sigma-delta analog-to-digital converter (ADC) includes converting an analog input signal into a sequence of digital data using a sigma-delta modulator of the sigma-delta ADC, setting a first configuration for a decimation filter of the sigma-delta ADC according to a first condition of a measurement window, filtering the sequence of digital data using a low-pass filter (LPF) of the decimation filter, and in response to a change in the measurement window, setting a second configuration for the decimation filter according to a second condition of the measurement window. |
| US09742429B1 |
Superconductor analog to digital converter
Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB. |
| US09742424B2 |
Analog-to-digital converter
An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit. |
| US09742423B1 |
Separating most significant bits and least significant bits in charge storage elements of an analog-to-digital converter
In an example embodiment, an apparatus includes: a first sampling capacitor to switchably couple between an input analog voltage, a reference voltage (VREF) and a ground voltage; a second sampling capacitor to switchably couple between the reference voltage and the ground voltage; and a comparator having a first input terminal to couple to the first sampling capacitor and a second input terminal to couple to the second sampling capacitor. The comparator may be configured to compare a voltage level at the second input terminal to a sum voltage based at least in part on the input analog voltage to generate at least one bit of a digital output. |
| US09742422B2 |
Receiver with adjustable reference voltages
A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators. |
| US09742421B2 |
Localized dynamic element matching and dynamic noise scaling in digital-to-analog converters (DACs)
Methods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements. |
| US09742420B2 |
Baseline compensation system
An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier. |
| US09742418B2 |
Phase lock loop with dynamic lock ranges
A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates. |
| US09742416B2 |
IC phase detector with re-timed reference clock controlling switches
A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided. |
| US09742413B2 |
Electronic device and information processing apparatus
An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element. |
| US09742409B2 |
Electronic assembly supported by a plurality of cards
A subsea electronics module for use in a subsea well installation, comprising: a backplane connecting a plurality of slots; a plurality of physical cards each supporting an electronic assembly having an identical architecture including a programmable logic module and a memory, the physical cards each being inserted into a respective slot of the backplane; and wherein the identical electronic assembly of each physical card is configured by program instructions stored in the memory thereon to be configured to perform in use a set of electronic functions of one of a plurality of different defined card roles in dependence on either one or both of: the position of the slot into which that card is inserted; an indication of a card role configuration selection for that card. |
| US09742407B2 |
Circuit and method for shifting voltage level
A circuit is disclosed that includes a first switch unit, a first level shift unit and a second level shift unit. The first switch unit is configured to receive a first dynamic input voltage, and to generate a first operation voltage at a first operation terminal or generate a second operation voltage at a second operation terminal according to the first dynamic input voltage. The first level shift unit is coupled to the first switch unit at the first operation terminal, and is configured to shift the first operation voltage to a first output voltage having a first level at an output terminal according to a first supply voltage. The second level shift unit is coupled to the first switch unit at the second operation terminal, and is configured to shift the second operation voltage to the first output voltage having a second level according to a second supply voltage. |
| US09742406B2 |
Circuit skew compensation trigger system
A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew. |
| US09742404B2 |
Level shifter circuit with improved time response and control method thereof
A level shifter circuit with improved time response and a control method thereof are disclosed herein. The level shifter circuit includes the output stage circuit of a level shifter and a booster circuit. The output stage circuit of the level shifter includes a first pass switch configured to transfer a voltage level of the first power supply of the level shifter to an output node, and a second pass switch connected between a second power supply and the first pass switch. The booster circuit accelerates the switching operation of the level shifter by accelerating a time response during the turning on or off operation of the first pass switch using charge sharing between a first capacitor and the parasitic capacitance of the control node of the first pass switch, which occurs via a first switch. |
| US09742403B2 |
State-retaining logic cell
A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail. |
| US09742401B2 |
Low-leak potential selection circuit
First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off. |
| US09742398B2 |
Methods and apparatus for sensing current through power semiconductor devices with reduced sensitivity to temperature and process variations
Current sensing through a power semiconductor device with reduced sensitivity to temperature and process variations. An example arrangement includes a power switch coupled between a voltage input and an output voltage terminal supplying current to a load; a first isolation switch coupled between the voltage input and a first node; a comparator amplifier having a pair of differential inputs coupled to the first node and a second node outputting a voltage in response to the difference at the differential inputs; and a first current source coupled between a positive supply voltage and the first node to output a first current responsive to the voltage output from the comparator amplifier; wherein the first current is proportional to the current through the power switch and a ratio of the on resistance of the power switch and the on resistance of the first isolation switch. Methods and additional arrangements are also disclosed. |
| US09742394B2 |
High-voltage, high-current, solid-state closing switch
A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications. |
| US09742393B2 |
Voltage supply circuit with an auxiliary voltage supply unit and method for starting up electronic circuitry
A voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source. |
| US09742392B2 |
Semiconductor device performing boot-up operation
A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled. |
| US09742386B2 |
Efficient duty-cycle balanced clock generation circuit for single and multiple-phase clock signals
Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed. |
| US09742385B2 |
Bidirectional semiconductor switch with passive turnoff
A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain. |
| US09742378B2 |
Pulse output circuit and semiconductor device
A highly reliable semiconductor device in which a shift in threshold voltage of a transistor due to deterioration can be inhibited is provided. A pulse output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. A clock signal is supplied to a drain of the first transistor. A first power supply potential is applied to a source of the second transistor, and a drain of the second transistor is connected to the drain of the first transistor. A second power supply potential is applied to a drain of the third transistor. The first power supply potential is applied to a source of the fourth transistor, and a drain of the fourth transistor is connected to the drain of the third transistor. The first power supply potential is applied to a source of the fifth transistor, and a drain of the fifth transistor is connected to a gate of the third transistor. One of a source and a drain of the sixth transistor is connected to the drain of the first transistor, and the other of the source and the drain of the sixth transistor is connected to the gate of the third transistor. The first transistor and the third transistor include back gates connected to each other. The first to sixth transistors have the same conductivity type. |
| US09742375B2 |
Method and apparatus for adapting a variable impedance network
The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed. |
| US09742363B2 |
Crossover and amplifier based canalphone system
A canalphone system may include a high audio driver, and a low audio driver adjacent to the high audio driver. The system may also include an amplifier that amplifies an audio signal and delivers that amplified audio signal to the high audio driver and/or the low audio driver. The system may further include a passive audio crossover, the passive audio crossover receives the amplified audio signal from the amplifier and then delivers the amplified audio signal in a suitable frequency range to the high audio driver and/or the low audio driver. The system may additionally include a second amplifier, and a high portion of the passive audio crossover, the high portion of the passive audio crossover to receive the audio signal from the second amplifier and to limit the audio signal delivered to the high audio driver to a high frequency portion of the amplified audio signal. |
| US09742359B2 |
Power amplifier with wide dynamic range am feedback linearization scheme
Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry. |
| US09742355B2 |
Buffer circuit robust to variation of reference voltage signal
A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal. |
| US09742353B2 |
CMOS VCO with implicit common-mode resonance
A circuit for an oscillator with common-mode resonance includes a first oscillator circuit and a second oscillator circuit coupled to the first oscillator circuit. Each of the first oscillator circuit or the second oscillator circuit includes a tank circuit, a cross-coupled transistor pair, and one or more capacitors. The tank circuit is formed by coupling a first inductor with a pair of first capacitors. The cross-coupled transistor pair is coupled to the tank circuit, and one or more second capacitors are coupled to the tank circuit and the cross-coupled transistor pair. Each of the first oscillator circuit or the second oscillator circuit allows tuning of a respective common mode (CM) resonance frequency (FCM) to be at twice a respective differential resonance frequency (FD). |
| US09742352B2 |
Voltage-controlled oscillator
A voltage-controlled oscillator includes two first inductors having a common node, two varactors respectively coupled to the first inductors, a cross-connected pair coupled to the first inductors, and a reversely tunable source degeneration module coupled to the cross-connected pair. The reversely tunable source degeneration module cooperates with the cross-connected pair to form a negative equivalent capacitance seen into the cross-connected pair from the common node of cross-connected pair and each first inductor. An oscillatory signal pair is provided at the first terminals of the first and second transistors. |
| US09742349B2 |
PV junction unit, PV junction box and method for monitoring current in PV string
A PV junction unit for joining a plurality of PV strings into a single string, comprising: a plurality of anode branch circuits; an anode busbar adapted to connect with an anode output end of each PV string via one corresponding anode branch circuit; a plurality of cathode branch circuits; a cathode busbar adapted to connect with a cathode output end of each PV string via one corresponding cathode branch circuit; resistors each of which is connected in series in one corresponding anode branch circuit connecting the anode output end of one corresponding PV string with the anode busbar, wherein each resistor has a theoretical resistance; voltage measuring devices each of which is connected in parallel with one corresponding resistor; and a processor connected with each of the voltage measuring devices, the processor configured to determine a current value in one PV string at least based on the theoretical resistance of the resistor in one anode branch circuit connected with the one PV string and based on a voltage value from the voltage measuring device in said one anode branch circuit connected with the one PV string. |
| US09742348B2 |
Foldable array of three-dimensional panels including functional electrical components
Embodiments disclosed herein relate to a foldable array of three-dimensional panels, which may include one or more functional electrical components. For instance, the three-dimensional multi-panel array may be reconfigured from a substantially planar configuration into a three-dimensional configuration. |
| US09742347B2 |
Modular strap mount for solar panels
A method and apparatus for mounting a solar collector panel by itself or supported within a frame, to a surface comprising: a strap assembly, a first attachment device attached to and between the panel or frame and the strap assembly; and a second attachment means for attaching the strap assembly to the surface. The strap assembly comprises a plurality of straps attached end to end. The first attachment device could be a bolt, a screw, adhesive, etc. Alternatively, there could be a support between the panel or frame and the strap assembly. The second attachment means may be: a nail, a spike, adhesive, bolting to a stud attached to the surface, welding, ballast, adhesive tape or combinations of these. |
| US09742346B2 |
Method of discharging at least one electrical energy storage unit, in particular a capacitor, of an electrical circuit
Method of discharging at least one electrical energy storage unit of an electrical circuit (1), the electrical circuit (1) furthermore comprising a switching system (2) comprising a plurality of arms (3) each extending in parallel between a positive conductor (4) and a negative conductor (5) of a DC bus (7), each arm (3) comprising in series at least two switching cells (10), in which method, to discharge the capacitor (20, 40), a short-circuit between the positive conductor (4) and the negative conductor (5) of the DC bus (7) is produced in at least two of the arms (3) of the switching system (2) so as to allow the discharge current (IDC) of the electrical energy storage unit to flow from said positive conductor (4) to said negative conductor (5). |
| US09742342B2 |
Motor driving apparatus
A motor driving apparatus includes: a switch having a first terminal that receives an external voltage, and a second terminal; a driving circuit coupled to the first terminal of the switch, and powered by the external voltage; a control circuit coupled to the second terminal of the switch; and a power circuit coupled across the switch, and outputting an internal voltage associated with the external voltage to power the control circuit to control the driving circuit to drive a motor of a power tool to rotate in a first direction when the switch operates in the ON state and to rotate in a second direction for a predetermined time period counting from each instance the switch transitions to the OFF state. |
| US09742341B2 |
AC motor drive system
An AC motor drive motor system includes a charge and discharge controller controlling a charging and discharging circuit based on a DC voltage value on the output side of a converter and a charging and discharging current value of a power storage device. The charge and discharge controller, when regenerative power via an inverter from an AC motor exceeds a power threshold, charges the power storage device such that the DC voltage value becomes a voltage threshold corresponding to the power threshold. When regenerative power is the power threshold or less, the converter performs regeneration when the DC voltage value reaches a regeneration start voltage threshold or higher, and ends regeneration when the DC voltage value reaches a regeneration end voltage threshold or lower. The DC-voltage-value time averaged value during regeneration is set lower than that at no-load time when the converter does not perform power supply and regeneration. |
| US09742332B2 |
Electrical actuator systems and methods for limiting force in the event of a wiring harness failure
Controller is provided for electromechanical actuator such as an electric brake actuator having a motor driven in response to motor drive signal generated by controller. Controller includes first current limiter and second current limiter. First current limiter limits current command to maximum current limit in response to detecting that current command at least one of exceeds maximum current limit setpoint or is less than minimum current limit setpoint. Second current limiter further limits current and to limited current command in response to detecting that current command exceeds topper current detection limit for specified time duration. Controller may further include intermediate current limiter between first and second current limiters for further limiting current command from first current limiter in response to detecting current command from first current limiter at least one of exceeds maximum power limit setpoint or is less than minimum power limit setpoint. |
| US09742325B2 |
Control device, driving device, and image forming apparatus
A control device includes a motor driving unit that supplies electric power to a motor according to a magnetic-pole-phase signal output from the motor; and a rotational-position detecting unit that converts the magnetic-pole-phase signal into a rotational-position detection signal and outputs the rotational-position detection signal. The rotational-position detection signal indicates a rotation amount and a rotation direction of an output shaft of the motor and has a higher resolution than the magnetic-pole-phase signal. |
| US09742324B2 |
Integrated circuit
In an integrated circuit formed into a single chip, a drive signal generating unit generates drive signals for switching elements of a power conversion circuit. A monitoring unit monitors a microcomputer that calculates generation information that is information used to generate the drive signals, and determines whether or not an abnormality has occurred in the microcomputer. An angle converting unit converts an output signal of an angle sensor to rotation angle information of a rotating electric machine. A drive signal generating unit generates the drive signals for controlling driving of the rotating electric machine based on the generation information and the rotation angle information when the monitoring unit determines that an abnormality has not occurred in the microcomputer, and generates the drive signals based on the rotation angle information, without using the generation information, when the monitoring unit determines that an abnormality has occurred in the microcomputer. |
| US09742323B2 |
Phase control circuit for brushless motor, brushless motor and method for controlling the phase of brushless motor
A phase control circuit for a brushless motor includes a signal output unit that outputs M signals, whose phases differ from each other, in response to a change in the magnetic field resulting from the rotation of magnets placed in a rotor, and a control signal generator that generates two or more different kinds of group of phase control signals, based on at least the M signals, the group of phase control signals being used to control drive voltages, whose phases differ from each other, which are supplied to each phase of an N-phase coil (N being an integer greater than or equal to two). The control signal generator is configured such that a first phase control signal group and a second phase control signal group can be generated. |
| US09742320B2 |
Torque ripple reduction in switched reluctance motor drives
A method for controlling a switched reluctance motor, the method comprising: receiving a reference torque Te ref; receiving an indication of a present rotor position θ for the switched reluctance motor; determining at least one of: a reference current ie_ref(k−1) for a (k−1)th phase, a reference current ie_ref(k) for a (k)th phase, and a reference current ie_ref(k+1) for a (k+1)th phase; and outputting the determined at least one reference current to a current controller operatively coupled to the switched reluctance motor, wherein the determined at least one reference current is based on an objective function comprising the squares of phase current and derivatives of current reference. |
| US09742317B2 |
Regenerative braking controlling system and method
The regenerative braking controlling system includes an armature current sampling module, a calculating module, and an adjusting module. The calculating module includes a power calculating unit, an optimum phase angle calculating unit, an optimum regenerative current calculating unit, and a sub-optimum regenerative current calculating unit. The armature current sampling module samples current of the three phase armature windings. The power calculating unit determines a relationship between a regenerative power and a phase angle of the armature currents. The optimum phase angle calculating unit calculates an optimum phase angle, and obtain a phase regenerative path based on the optimum phase angle. The optimum regenerative current calculating unit calculates an optimum regenerative current limit point. The sub-optimum regenerative current calculating unit calculates a sub-optimum regenerative current limit point. The adjusting module adjusts regenerative current according to the optimum regenerative current limit point and the sub-optimum regenerative current limit point. |
| US09742312B2 |
Apparatus and electrical assembly for converting a direct voltage into an alternating voltage
Embodiments relate to an electrical assembly (1) for converting a direct voltage into an alternating voltage, comprising a first supply voltage area (10) for distributing a first DC supply voltage, and a second supply voltage area (12) for distributing a second DC supply voltage. The electrical assembly (1) comprises at least one first power semiconductor (24) having an input terminal connected to the first supply voltage area (12) and an output terminal (28) connected to an alternating voltage output (20a) of the assembly. The electrical assembly (1) further comprises at least one second power semiconductor (26) having an input terminal (32) connected to the second supply voltage area (12) and an output terminal connected to the alternating voltage output (20a) of the assembly, wherein the first supply voltage area (10) extends on the side of the first power semiconductor (24) facing the input voltage terminal of the first power semiconductor (24). Furthermore the second supply voltage area (12) extends on the side of the second power semiconductor (26) facing away from the input voltage terminal (32) of the second power semiconductor (26). |
| US09742311B2 |
Systems and methods for controlling inverters
A method of controlling an inverter includes receiving output voltage target waveforms for phases of an inverter, generating uncompensated midpoint duty cycle waveforms for the inverter phases, selecting an uncompensated midpoint duty cycle waveform for one of the inverter phases based on the magnitudes of the uncompensated midpoint duty cycle waveforms, and applying a compensation signal to the selected uncompensated midpoint duty cycle waveform. An inverter controller and inverter employ the method for generating switch command signals for solid-state switch devices of the inverter. |
| US09742305B2 |
Power conversion apparatus
A frame portion is a plate-like member to which a cooler is attached for cooling an electric circuit element configured to operate for power conversion that causes generation of heat. The capacitor is a structural member disposed in a direction perpendicular to the frame portion and including a capacitor element electrically connected to the electric circuit element. The capacitor includes a first support surface and a second support surface that are external surfaces facing in opposite directions from each other and parallel to the direction perpendicular to the frame portion. The first frame and the second frame each have an end portion fixed to a connection frame. The first frame includes a first attachment surface fixed to a first support surface. The second frame includes a second attachment surface fixed to a second support surface. |
| US09742304B2 |
Driver board and power converter
Provided is a driver board capable of miniaturizing itself while ensuring insulation voltage resistance performance. In the driver board: a transformer 114 is configured, so as to cross a first insulating region 120a, such that a primary side terminal 114a is connected to a primary side circuit 112a and a secondary side terminal 114b is connected to a secondary side circuit 113a; a power supply control IC 115 is configured, so as to cross a insulating region 120b, such that a primary side terminal 115a is connected to a primary side circuit 112b and a secondary side terminal 115b is connected to a secondary side circuit 113b; and the insulating region 120a and the insulating region 120b are formed so as to at least partially face each other via an insulating board 111 such that the primary side circuit 112a and the secondary side circuit 113b do not face each other via the insulating board and the primary side circuit 112b and the secondary side circuit 113a do not face each other via the insulating board. |
| US09742298B2 |
Transformer and control method thereof
A transformer includes a first switch, a first winding, a second winding, a third winding, a first current direction control unit, a second current direction control unit and a loading capacitor. The first switch is coupled between the second winding and the third winding. The first winding is disposed at a primary side and coupled between an input voltage terminal and a first ground. The second winding is disposed at a secondary side and coupled between a second ground and the first switch. The third winding is disposed at the secondary side. The first current direction control unit is coupled between the second winding and an output voltage terminal. The second current direction control unit is coupled between the third winding and the output voltage terminal. The first switch is turned on for adjusting a winding ratio when the transformer is used to output a high voltage. |
| US09742291B2 |
Control circuit and related integrated circuit and switching-type converter
A control circuit can include: a power supply circuit having a bias capacitor coupled between a power terminal and a common node, where the power supply circuit supplies power to the control circuit via the bias capacitor; a detection circuit coupled between the common node and a current output terminal of a main power switch of a power stage circuit, to detect current flowing through the main power switch; a current feedback circuit that generates a feedback signal according to a difference value between a sense value obtained from a voltage at the power terminal during an off state of the main power switch and a present voltage at the power terminal, where the feedback signal represents an inductor current of the power stage circuit; and a control signal generator that generates a control signal according to the feedback signal to control the main power switch. |
| US09742290B2 |
Control arrangement for increasing the available output from a source
A control arrangement for use in controlling the electrical supply from a power supply unit including an internal capacitance to an output is described, the control arrangement comprising an inductor, a switch arranged in parallel with internal capacitance, and a controller operable to control the operation of the switch such that closing of the switch results in the formation of an LCR circuit, the internal capacitance forming the capacitance of the LCR circuit. An associated control method is also described. |
| US09742287B2 |
Switched-mode power supply comprising a module for charging and discharging an energy store including an electrical transformer
The disclosure concerns a switched-mode power supply comprising a module for charging and discharging an energy store including an electrical transformer. The device provides high configuration flexibility. |
| US09742285B2 |
Semiconductor device and automobile
A semiconductor device of the present invention includes a transistor having a drain and a source, a voltage being applied between the drain and the source from a high-voltage power supply, a drive device that generates a source voltage and a gate voltage for the transistor from a voltage of a low-voltage power supply lower than that of the high-voltage power supply, and a voltage dividing circuit connected to the low-voltage power supply, wherein when the source voltage is lower than a certain value, an output voltage from the voltage dividing circuit is applied to the source. |
| US09742284B2 |
Multiphase power circuit
A power circuit includes: first and second switching circuits coupled in parallel between an input terminal and an output terminal; a control signal generator that performs an ON/OFF control of the first and second switching circuits individually and generates a first control signal and a second control signal having different phases; a frequency converter that converts a frequency of the first control signal after converting a frequency of the second control signal; and a phase shifter that shifts the phase of the second control signal when a first interrupt is introduced as the first control signal is turned ON after the frequency converter has converted the frequency of the second control signal. |
| US09742275B2 |
Variable voltage converter with direct output voltage clamping for inverter system controller
A power conversion circuit includes a variable voltage converter (VVC) with a stabilizing means for stabilizing its output voltage. The stabilizing means can be in the form of a diode that clamps the VVC output voltage to the VVC input voltage so that the output voltage does not drop below the input voltage when a load imposes a sudden power demand. The stabilizing means also enables a bypass mode in which transient power can be provided from a power source to an inverter without current flow through the VVC inductor or switches. When embodied as a diode, the stabilizing means can increase the maximum power that can be transferred by the power conversion circuit, improve the power response of the circuit, minimize control instability, and reduce power losses. |
| US09742273B2 |
Power switching voltage regulator
A power switching voltage regulator includes a high-side switch, a low-side switch, an inductor, a detection circuit, and a gate voltage adjusting unit. The high-side switch is coupled to a voltage source; the low-side switch is coupled between the high-side switch and a ground. A connection node is located between the high-side switch and the low-side switch. The inductor is coupled between the connection node and a power output terminal of the power switching voltage regulator. The detection circuit detects an output voltage of the power output terminal, when the output voltage swings out of a predetermined range. The gate voltage adjusting unit dynamically adjusts a gate voltage on-resistances of the high-side switch and the low-side switch. |
| US09742272B2 |
AC-DC converter
An AC to DC converter includes a plurality of rectifier circuits connected in series to an AC voltage source at an input side to collectively receive an output voltage of the AC voltage source; and a plurality of switching units respectively connected to the plurality of rectifier circuits, each of the switching units having a semiconductor switching device, a diode, and a capacitor, and performing ON/OFF switching of the semiconductor switching device provided therein to step up a voltage received from the corresponding rectifier circuit, each of the switching units supplying the stepped-up voltage to said capacitor through said diode so that a resulting DC across said capacitor can be provided, as a DC output voltage of the switching unit, to a respective load to be connected to terminals of said capacitor. |
| US09742266B2 |
Charge pump timing control
Cycle timing of a charge pump is adapted according to monitoring of operating characteristics of a charge pump and/or peripheral elements coupled to the charge pump. In some examples, this adaptation provides maximum or near maximum cycle times while avoiding violation of predefine constraints (e.g., operating limits) in the charge pump and/or peripheral elements. |
| US09742265B2 |
Power supply method for avoiding audio noise and power supply apparatus for avoiding audio noise
A power supply apparatus (10) includes a voltage input side (102), a power switch circuit (104), a voltage output side (106), a pulse width modulation signal generating circuit (108) and a burst frequency detection circuit (110). According to a pulse width modulation signal (114), the pulse width modulation signal generating circuit (108) controls the power switch circuit (104), so that the power supply apparatus (10) enters a burst mode. The burst frequency detection circuit (110) detects a burst frequency of the power switch circuit (104). The burst frequency detection circuit (110) informs the pulse width modulation signal generating circuit (108) that the burst frequency is in an audio frequency range if the burst frequency is in the audio frequency range. The power supply apparatus (10) leaves from the burst mode to avoid audio noise. |
| US09742256B2 |
Actuator
To provide an actuator in which an unstable movement of a rotor is controlled. An actuator includes a coil, a bobbin around which the coil is wound, a rotor positioned inside the bobbin, a shaft to which the rotor is fixed and which is rotatably supported, a stator including a base portion positioned on one end side of the shaft, outer magnetic pole portions extending from the base portion along the shaft and positioned outside the bobbin and inner magnetic pole portions extending from the base portion along the shaft and positioned between the rotor and the inside of the bobbin, a stator including a base portion positioned on the other end side of the shaft, outer magnetic pole portions extending from the base portion along the shaft and positioned outside the bobbin and inner magnetic pole portions extending from the base portion along the shaft and positioned between the rotor and the inside of the bobbin and a cover positioned between the rotor and the stator and contacting tip portions of the inner magnetic pole portions to regulate the approach of the inner magnetic pole portions to the rotor. |
| US09742255B2 |
Apparatus and method for electricity generation
An apparatus comprising: a permanent magnet providing magnetic flux; an electric field generator comprising at least one conductive loop and high permeability material configured to direct magnetic flux preferentially through the at least one conductive loop adjacent a first portion of a length of the at least one conductive loop; and a supporting system configured to support the permanent magnet at a distance from the electric field generator and enable relative movement between the permanent magnet and the electric field generator. A corresponding method. |
| US09742246B2 |
Multiple speed motor with thermal overload protection
An electric motor includes a stator and a rotor. The stator has a plurality of low speed windings and a plurality of separate high speed windings. A first type of thermal overload protector is coupled with at least one of the low speed windings and a second type of thermal overload protector is coupled with at least one of the high speed windings. |
| US09742241B2 |
Low profile pump motor lead protector
A low profile pump motor lead protector with a head guard and a trailing guard, the head guard including a front section with a front end and a rear section with a rear end, the trailing guard having a pin end for insertion in a head guard socket, the lead protector for protecting a motor lead of a pump and motor assembly of a downhole production string for surfacing fluid from a reservoir such as a subterranean oil well. |
| US09742236B2 |
Terminal for vehicle traction motor and method of manufacturing the same
A terminal of a vehicle traction motor includes a plurality of bus bars placed on an assembly jig, a plurality of insulation spacers, where an insulation spacer is inserted between the a pair of bus bars, and a terminal mold placed over the plurality of bus bars and the plurality of insulation spacers, the terminal mold being coupled to an outermost bus bar of the plurality of bus bars, wherein a diameters of each of the plurality of bus bars is different from the other bus bars, and a diameters of each of the insulation spacers is different from the other insulation spacers. |
| US09742227B2 |
Electric machine
An electric machine comprise a first carrier having an array of electromagnetic elements and a second carrier having electromagnetic elements defining magnetic poles, the second carrier being arranged to move relative to the first carrier. An airgap is provided between the first carrier and the second carrier. The electromagnetic elements of the first carrier include posts, with slots between the posts, one or more electric conductors in each slot, the posts of the first carrier having a post height in mm. The first carrier and the second carrier together define a size of the electric machine. The magnetic poles having a pole pitch in mm. The size of the motor, pole pitch and post height are selected to fall within a region in a space defined by size, pole pitch and post height that provides a benefit in terms of force or torque per weight per excitation level. |
| US09742224B2 |
Pole shoe of a generator, preferably a generator of a wind turbine generator system
The invention concerns a pole shoe, in particular of a generator, comprising a pole assembly which is of a laminated configuration, at least one winding arranged around the pole assembly, and a body which passes through the laminated pole assembly in the longitudinal direction and which has a plurality of transversely directed engagement locations, preferably at most three transversely directed engagement locations, into which a respective holding means can engage to fasten the pole shoe on a support, in particular the rotor or stator of a generator. The present invention further concerns a pole shoe, in particular of a generator, comprising a pole assembly which is of a laminated configuration, at least one winding arranged around the pole assembly, and an insulating means arranged between the pole assembly and the winding, wherein the insulating means has a fiber composite material. |
| US09742221B2 |
Power supply device, power supply method, and program
A power supply device includes a power supply unit that wirelessly supplies power to a power reception device, a reception unit that receives an interrupt request from a second power reception device during power supply to a first power reception device by the power supply unit, a determination unit that determines whether the interrupt of the second power reception device is to be permitted, and a power supply control unit that stops the power supply to the first power reception device and starts power supply to the second power reception device when the determination unit has determined that the interrupt is to be permitted. |
| US09742220B2 |
Auxiliary power supply devices and electronic systems employing the same
An auxiliary power supply device can include an auxiliary power source configured to provide auxiliary power. An auxiliary power state detection circuit electrically can be coupled to an input or an output of the auxiliary power source and an auxiliary power supply circuit that can be electrically coupled to the output of the auxiliary power source, where the auxiliary power supply circuit can be configured to provide the auxiliary power to a target system when power supplied to the target system by a main power source is abnormal. Related systems are also disclosed. |
| US09742217B2 |
Charge control apparatus and charge control method
A charge control apparatus has a charger for charging a battery with rectified power obtained by rectifying AC power supplied from a power supply by full-wave rectification or half-wave rectification as charge power, a sensor for detecting a state of the battery, and controller for setting voltage lower than a limit voltage of the battery as an upper limit charge voltage chargeable to the battery. The controller manages the power chargeable to the battery on a basis of a detected value of the sensor and the upper limit charge voltage, controls the charge power on a basis of the chargeable power, sets the upper limit charge voltage to first upper limit charge voltage when the charge power is higher than a predetermined threshold value, and sets the upper limit charge voltage to second upper limit charge voltage when the charge power is lower than the threshold value. |
| US09742216B2 |
Wireless charging system for variable charging mode
A wireless charging system for a variable charging mode includes: an information receiver configured to receive information about a wireless power receiver including a wireless charging mode that is supported by the wireless power receiver through a wireless communication connected to the wireless power receiver; wireless power transmitting units configured to wirelessly transmit power by a plurality of different wireless charging modes; and a controller configured to control the wireless power transmitting units to wireless transmit power by the wireless charging mode corresponding to the received information. |
| US09742214B2 |
Wireless power transfer system and wireless charging system
Disclosed is a wireless power receiving apparatus for wirelessly receiving power. The wireless power receiving apparatus includes a power receiving unit configured to wirelessly receive power, a charging unit configured to receive the power from the power receiving unit, and supply the power to a battery, and a control unit configured to determine an output voltage, which enables a charging efficiency of power, supplied to the battery, to be the maximum, based on an output capacity output from the power receiving unit, and control the power receiving unit for the battery to be charged with the output voltage. |
| US09742212B2 |
Wireless power receiver and electronic device including the same
A wireless power receiver according to an exemplary embodiment in the present disclosure may include a coil receiving power transmitted wirelessly in an inductive-coupling scheme; an electrode receiving power transmitted wirelessly in a capacitive-coupling scheme; and a rectifying unit connected to the coil and the electrode and rectifying input power to output supply power. |
| US09742208B2 |
Electrical charging case for wireless headsets
A charging case for a plurality of headsets is disclosed. Each headset includes two headphone units connected together in opposing relationship along a diametric axis by a headband. Each headset contains a battery and a charge receiving circuit coupled to the battery. The charging case comprises a portable, cylindrically shaped carrying case and a charging station contained in the carrying case. The charging station includes a plurality of charging receptacles and a charge distribution circuit. The charging receptacles are disposed in a circular pattern about a center area and are configured to support the headsets, respectively, in an orientation where the diametric axes of the headsets are positioned radially in the circular pattern. The distribution circuit distributes electricity to the charging receptacles. At each receptacle electricity is transferred to the charge receiving circuit of a headset when the headset is in the receptacle, to charge the battery of the headset. |
| US09742207B2 |
Cell protection system
A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current MOSFET has a drain and a gate common with discharge control MOSFET. The charge current detection resistances and the discharge current detection resistance are provided in correspondence to the charge current detection MOSFET and the discharge current detection MOSFET, respectively. The control circuit generates a gate control signal for the charge control MOSFET and the charge current detection MOSFET by using the charge current detection resistance and generates a gate control signal for the charge control MOSFET and the discharge current detection MOSFET by using the discharge current detection resistance. |
| US09742206B2 |
Rechargeable battery system and method of controlling power consumption
A rechargeable battery system includes: a first battery pack; and a second battery pack in a daisy chain connection with the first battery pack to form a communication path, the second battery pack consuming a larger power for communication than a power consumed in the first battery pack for communication. A power consumed in the second battery pack for an additional process other than communication is smaller than power consumed in the first battery pack for the additional process. |
| US09742204B2 |
Wireless energy transfer in lossy environments
Described herein are improved configurations for a wireless power transfer for electronic devices that include at least one source magnetic resonator including a capacitively-loaded conducting loop coupled to a power source and configured to generate an oscillating magnetic field and at least one device magnetic resonator, distal from said source resonators, comprising a capacitively-loaded conducting loop configured to convert said oscillating magnetic fields into electrical energy, wherein at least one said resonator has a keep-out zone around the resonator that surrounds the resonator with a layer of non-lossy material. |
| US09742203B2 |
Distributed resonators for wireless power transfer
An apparatus for wireless charging may include a casing for housing an electronic device and a plurality of power receiving elements that can couple to an externally generated magnetic field to wirelessly power or charge a load in the electronic device. At least one of the power receiving elements may comprise an electrically conductive segment of the casing. |
| US09742191B2 |
Method for controlling an arrangement for supplying electric current to a power supply system
The invention relates to a method for controlling a feed arrangement having a wind energy installation for feeding electrical power into an electrical supply system, comprising the following steps: generating electrical power using the wind energy installation from wind, feeding a first proportion of the generated electrical power into the electrical supply system, supplying a second proportion of the generated electrical power to an electrical consumer for consuming the supplied second proportion of the generated electrical power, and wherein, depending on at least one monitored system state and/or depending on the prevailing wind, the second proportion of the generated electrical power which is supplied to the consumer is reduced wholly or partially and the first proportion of the electrical power fed into the electrical supply system is increased correspondingly, and to a corresponding feed arrangement. |
| US09742190B2 |
Device and method for electrically decoupling a solar module from a solar system
Devices and methods for electrically decoupling a solar module from a solar system are described. In one embodiment, a solar system includes a string of a plurality of solar modules coupled with an inverter through a DC power line. An AC input is coupled with the DC power line. A device is also included and is configured to provide a closed circuit for one of the plurality of solar modules if an AC signal voltage from the AC input is present on the DC power line, and is configured to provide an open circuit for the one of the plurality of solar modules if no AC signal voltage from the AC input is present on the DC power line. |
| US09742187B2 |
Power supply circuit with active under-voltage protection
A power supply circuit includes a protection circuit interconnected with an input voltage to the power supply. The protection circuit includes a detection circuit to detect whether a magnitude of the input voltage is below a defined threshold. The detection circuit comprises a plurality of detectors, each for detecting for a defined voltage waveform, whether its magnitude is below a defined threshold voltage. Logic interconnects the detection circuit to provide a control signal for inhibiting the power supply from providing said output voltage if the input voltage is below the defined threshold for that defined voltage waveform, as detected by the detection circuit. |
| US09742186B2 |
Electronic equipment item comprising a housing and at least one electronic board protected against lightning
An electronic equipment item for an electronic system, comprising a housing, a backplane board, at least one daughterboard and at least one lightning protection board housed in the housing. A connector is fixed to the backplane board and configured to be connected to the rest of the electronic system. For each daughterboard there is provided one lightning protection board. For each lightning protection board, a first port is arranged to connect the lightning protection board to the backplane board, and a second port is arranged to connect the daughterboard to the lightning protection board. |
| US09742183B1 |
Proactively operational over-voltage protection circuit
Systems and methods are disclosed for providing over-voltage protection for power converters. An over-voltage protection loop includes an error amplifier that maintains an external reference voltage within a highly precise range that can be used to provide a highly precise output voltage from the over-voltage protection loop. The over-voltage protection loop may also include feedback impedance that delays the output of the over-voltage protection loop. The delay may prevent the over-voltage protection loop from being engaged due to voltage transients output from a main servo loop circuit that provides a nominal output voltage under normal operation, thus allowing the threshold voltage and output voltage of the over-voltage protection loop to be set close to the nominal output voltage of the main servo loop circuit. |
| US09742182B1 |
Acclimation sensing and control of electronic equipment
Embodiments are directed to apparatuses used with a computer-implemented method for controlling power flow to an electronic device, including: receiving a transmission from a service processing device, the transmission to trigger an open switch between the electronic device and a power supply; and causing an open switch to occur through use of an interlock mechanism. Embodiments provide a temperature-driven interlock mechanism and moisture-driven interlock mechanism. |
| US09742179B2 |
Conduit and end fitting for offshore cable assembly
A conduit for an offshore cable assembly that includes a conduit body that has at least one longitudinal strength member embedded therein. The at least one longitudinal strength member extends the length of the conduit body. A plurality of cables, hoses, or a combination are received inside of the conduit body. |
| US09742178B2 |
Medical device feedthrough assemblies with strain relief
Feedthrough assemblies for medical devices having various embodiments of strain relief members extending around portions of the feed through pin are described. |
| US09742175B2 |
Child resistant electrical outlet and switch cover
A safety cover system for a household electrical switch or outlet is provided. A wall plate is provided having an aperture for an electrical device such as an outlet or switch. The wall plate has a rim with upper and lower locking lips. A cover plate is provided that is pivotally connected to the wall plate by hinges for covering the wall plate. There is provided upper, lower and side release mechanisms. Each release mechanism includes a release button with a portion of the release button exposed to an exterior of the cover plate through an aperture in the cover plate. The release also includes a latch connected with the button having an arm overlapping the wall plate rim lip to prevent the cover plate from being pivoted open from the wall plate. |
| US09742173B2 |
Roof top junction box
A roof top junction box to protect wiring systems and a roof top from water leakages. The junction box includes a storage unit and an enclosure. A mounting component is fastened at an internal storage area of the storage unit to secure a terminal component thereon. Threaded screw elements are aligned in at least two of a plurality of screw hole channels utilizing a first sealing gaskets, a plurality of rubber washers and a plurality of press fit flutes. The plurality of threaded screw elements is affixed at a flashing member attached to the roof top. A compression ring and a multithreaded flute are aligned at a bottom conduit port in the storage unit. A conduit is inserted through the bottom conduit port and an opening at the flashing member to connect the conduit with at least one wiring system of a building. |
| US09742163B2 |
Subsea switchgear
A subsea switchgear for switching the power supply to plural subsea loads includes a subsea enclosure, to allow the deployment of the subsea switchgear at a subsea location; a power input for receiving AC electrical power from a power source; at least two power outputs for giving out AC electrical power; and a power distribution bus for distributing the received AC electrical power to the at least two power outputs. In at least one embodiment, between each power output and the power distribution bus, a contactor is connected which is controllable to connect or disconnect the respective power output from the power distribution bus. |
| US09742162B2 |
Gas-insulated medium-voltage switchgear assembly
In order to develop a gas-insulated medium-voltage switchgear assembly, which has an encapsulated container for accommodating components of the medium-voltage switchgear assembly, a grounding contact and a grounding busbar terminal provided on the outer side of the container, such that it has a simple and economical design, it is proposed that the grounding contact is secured by integral bonding in a container opening and has the grounding busbar connection terminal. |
| US09742159B1 |
Spark plug for a gas-powered internal combustion engine and method for the manufacture thereof
A spark plug for a gas-powered internal combustion engine, having a center conductor, an insulator surrounding the center conductor, a body surrounding the insulator, a center electrode connected in an electrically conductive manner to the center conductor, and at least one ground electrode that is connected in an electrically conductive manner to the body and forms a spark air gap with the center electrode. A shield that shields the spark air gap in the radial direction of the spark plug is located at the front end of the body. The shield includes multiple shield components that are attached to the front end of the body adjacent to one another in the circumferential direction of the spark plug. |
| US09742157B2 |
Spark plug
A spark plug includes an insulator having a through hole formed in the direction of an axis, a rod-shaped center electrode inserted in the through hole and extending in the direction of the axis, a metal shell disposed around an outer circumference of the insulator, and a ground electrode electrically conducted with the metal shell and adapted to define a gap between the ground electrode and the center electrode. A front end part of the insulator has a front end surface, an outer circumferential surface and a curved surface region formed between the front end surface and the outer circumferential surface. In a cross section including the axis, a front end of an inner circumferential surface of the metal shell faces the curved surface region in a direction perpendicular to the axis. The curved surface region has a curvature radius of 0.2 mm to 0.8 mm. |
| US09742146B2 |
Shock resistant laser module
Laser modules are provided having electrical connections that are resistant to damage caused by transient or higher order accelerations. |
| US09742142B1 |
Heat exchangers with tapered light scrapers for high-power laser systems and other systems
An apparatus includes a heat exchanger with a body having a passage through the body. The passage defines apertures on multiple sides of the body, and the passage is configured to allow optical signals to pass through the body. One or more tapered edges are at least partially around one or more of the apertures, and each tapered edge is configured to reflect optical radiation inward into the passage. One or more absorptive surfaces are within the passage, and the one or more absorptive surfaces configured to absorb the reflected optical radiation. The heat exchanger is configured to convert the absorbed optical radiation into heat, and the body further includes one or more cooling channels configured to receive coolant that absorbs the heat. |
| US09742138B2 |
Belt strip for contact elements
Provided is a belt strip for contact elements, which includes of a flat metal strip, from which individual tabs are angle by approximately 90°, wherein the tabs each have two retaining arms which are bent towards one another, wherein the retaining arms each have a constant direction of curvature, and wherein the radius of curvature is greater in the direction of the ends of the respective retaining arms. |
| US09742132B1 |
Electrical connector on circuit board
An electrical connector includes an insulating body, plural conductive terminals, and a shielding body. The insulating body includes a top board, a bottom board, and two side boards that form a docking chamber. The top board has a first surface, the bottom board has a second surface facing to the first surface, and plural terminal grooves are formed on the first surface and the second surface. Each of the conductive terminals has a contacting portion and a tail portion connected to the contacting portion. The contacting portion is located in a corresponding one of the terminal grooves, and the tail portion is extended to outside of the insulating body. The shielding body has two side walls opposite to each other and is fixed to an opening of the docking chamber in which two convex portions are respectively located on inner surfaces of the side walls. |
| US09742125B2 |
Electrical connector having improved terminals
An electrical connector includes an insulative housing, a number of first contacts and second contacts carried by the housing, a metallic shielding plate received in the housing, and a shielding shell attached to the insulative housing. The first contacts and the second contacts have a number of grounding contacts. Each grounding contact of the first contacts has a first end portion located at a front end thereof. Each grounding contact of the second contacts has a second end portion located at a front end thereof and corresponding to the first end portion. The metallic shielding plate respectively is contacted with the first end portion and the second end portion. |
| US09742119B2 |
Plug connector assembly with shielding shell
A plug connector assembly includes a bottom metallic shell having a lower wall, a front wall, a rear wall, a left wall, and a right wall, and defining a receiving slot. The front wall has an inserting groove extending therethrough along a front-to-back direction and a mounting slit extending downwardly from a top edge of the front wall and communicating to the inserting groove. A top metallic shell assembled to the bottom metallic shell along a top-to-bottom direction has a plurality of side walls, an opening defined by the side walls, and a front wall extending downwardly from of the side walls and abutting against the front wall of the bottom metallic shell to seal the mounting slit. A printed circuit board (PCB) is located in the receiving slot and enclosed by the bottom and top shells. A connector connects with a top section of the PCB. |
| US09742115B2 |
Connector
A connector includes a first housing including a first lock part, a second housing including a second lock part that can be locked to the first lock part, and a fitting detection member that can move from an initial position to a fitting assured position with the second lock part locked to the first lock part and includes a third lock part that can ride over the first lock part and the second lock part in succession along with the movement from the initial position to the fitting assured position to be locked to the second lock part at the fitting assured position. The first lock part includes a drawing slope surface inclining from a protruding tip toward a first lock face and a protrusion protruding from the drawing slope surface. The second lock part includes a notch that can house the protrusion. |
| US09742112B1 |
Automatic gravity connector
A two sided electrical connection system that automatically connects two connector sides together is provided. A male side and female side of the connector have bodies shaped such that the male side may be received by the female side automatically by a force of gravity. Guiding structure around the female side of the two sided connector allows the male side to be guided into place without requiring perfect alignment of the two sides of the connector. |
| US09742106B2 |
Electrical connection apparatus and method
A technique facilitates mechanical and electrical connection between components. The components may be coupled mechanically by a threaded engagement and electrically by first and second electrical couplers. The first and second electrical couplers may each have a plurality of electrical contacts oriented for linear engagement. The electrical contacts of the second electrical coupler are mounted on a first portion of the second electrical coupler which is rotatably received by a second portion to enable linear engagement of the electrical contacts while rotating the components relative to each other to form the mechanical connection. |
| US09742102B2 |
Connector seal device
A connector seal device includes, in one embodiment, a seal body extendable along an axis and configured to receive an end of a coupler. The coupler is configured to be rotatably coupled to a coaxial cable connector, and the seal body is configured to engage a portion of the coupler to establish a first environmental seal between the seal body and the coupler. The connector seal device also includes a seal neck integral with the seal body configured to extend along the axis beyond the end of the coupler. The seal neck is configured to engage an interface port to establish a second environmental seal between the seal neck and the interface port. |
| US09742098B2 |
Electrical connector having waterproof function
An electrical connector includes an insulative housing, a number of contacts accommodated in the insulative housing, a metal shell attached to the housing and defining a receiving space and a waterproof portion formed behind the receiving space. The insulative housing includes a groove, a tongue portion located in front of the groove, and a holding potion located behind the groove. The holding portion has a dispensing port communicating with the groove and an exterior. Each contact has a contacting section exposed on the tongue portion, a connecting section exposed from the groove, a holding section accommodated in the holding portion of the insulative housing, and a soldering section extending from the holding portion. The waterproof portion is received in the groove. |
| US09742093B2 |
Power box for a backpack vacuum
A power box adapted for use with a vacuum cleaning unit adapted to be carried on the back of a user, comprises an external housing including a power outlet recessed therein, the recessed power outlet further comprising a male power attachment, wherein the power box further comprises structures for receiving a power nozzle adapted for use with the vacuum cleaning unit. |
| US09742085B2 |
Portable electronic device connector
In various embodiments, an affixing structure of a connector is configured to attach to an affixing structure interface of a portable electronic device that is configured to also couple to an attachment member. A connector plug including conductors coupled to an electrical conduit is coupled to the affixing structure. The conductors are configured to electrically connect to one or more electric components of the portable electronic device and the electrical conduit is configured to electrically connect to one or more diagnostic devices. In some embodiments, an attachment member may include one or more electronic components and spring pins or other conductors connectible to a wearable device. The attachment member additionally includes a connector operable to connect the wearable device to another electronic device. |
| US09742081B1 |
Press-fit circuit board connector
A press-fit circuit board connector is provided including a housing having a mating end and a mounting end. The housing has a contact holder including a plurality of contact channels. Contacts are received in corresponding contact channels. Each contact has a mating pin and a mounting pin opposite the mating pin. The mating pin is compliant and configured for compliant mating with a corresponding socket contact of a mating connector. The mounting pin is compliant and configured for press-fit mechanical and electrical connection to a circuit board. The mating pins of the contacts are arranged at the mating end to define a pin mating interface having a first pattern and the mounting pins of the contacts are arranged at the mounting end to define a pin mounting interface having a second pattern different than the first pattern. |
| US09742077B2 |
Mm-wave phased array antenna with beam tilting radiation pattern
A system according to one embodiment includes a phased array antenna comprising a plurality of antenna elements, the plurality of antenna elements configured in a planar array, wherein each of the plurality of antenna elements generates a beam pattern directed at an angle out of the plane of the planar array; and driver circuitry coupled to each of the plurality of antenna elements, wherein the driver circuitry comprises a plurality of transceivers, the plurality of transceivers configured to provide independently adjustable phase delay to each of the plurality of antenna elements. |
| US09742069B1 |
Integrated single-piece antenna feed
The invention is an integrated single-piece antenna feed, turnstile polarizer and antenna system suitable for satellite communications. One embodiment of the integrated single-piece antenna includes a circular waveguide input, a circular polarizer, a coaxial feed horn, subreflector and subreflector support. One embodiment of the circular polarizer features four branches of wrapped-single-ridged waveguide. |
| US09742068B2 |
Microstrip antenna transceiver
A microstrip antenna transceiver with switchable polarization, used in a satellite signal reception device, includes a base board, having a first surface and a second surface; a ground metal plate, disposed on the first surface of the base board; an antenna module, disposed on the ground metal plate, having a radiating metal patch, a vertically polarized feeding hole and a horizontally polarized feeding hole; a first switch, set on the second surface of the base board; a second switch, set on the second surface of the base board; a first microstrip wire, electrically connected between the vertically polarized feeding hole of the antenna module and the first switch; and a second microstrip wire, electrically connected between the horizontally polarized feeding hole of the antenna module and the second switch. |
| US09742064B2 |
Low height, space efficient, dual band monopole antenna
A low height, space efficient, dual band monopole antenna is provided. The antenna includes a first conductive post, a second conductive post and a third conductive post extending between a lower oblong shaped PCB and an upper oblong shaped PCB. A signal is applied to a bottom end of a first conductive post and bottom ends of the remaining two posts are coupled to ground. The top of the first post is connected to the tops of the second and third posts by a serpentine trace which in one embodiment is symmetric and in another embodiment is asymmetric. The asymmetric embodiment achieves improved dual band operation without the need for an impedance matching network. |
| US09742063B2 |
External LTE multi-frequency band antenna
An antenna is provided. The antenna includes a substrate having a first end and a second end opposite to the first end, wherein a direction from the first end to the second end is an extending direction of the antenna; a radiating portion; a feed-in conductor; and a ground portion electrically connected to the radiating portion, coupled to the feed-in conductor, disposed on the substrate from the first end along the extending direction, and including a main ground conductor; and a high frequency band bandwidth adjusting conductor extended from the main ground conductor along the extending direction. |
| US09742062B2 |
Small switchable directional control antenna
Provided is a small switchable directional control antenna that can perform direction control according to shapes and sizes of various devices. The antenna includes a dielectric layer, a radiation patch formed on a side of the dielectric layer, a ground plane formed on a side of the dielectric layer opposite to the side on which the radiation patch is formed and configured to have a plurality of slots formed at edges thereof, and a control module insulated from the ground plane and configured to control electrical connection between the radiation patch and the ground plane. |
| US09742047B2 |
Battery pack with phase change material
A battery pack may include a housing; at least one battery cell supported in the housing; a phase change material; and a bladder containing the phase change material, the bladder defining a channel having an opening, the bladder being in a heat transfer relationship with the at least one battery cell. The phase change material in the bladder may also surround a portion of the channel. The phase change material may include a paraffin wax. |
| US09742045B2 |
Lithium electrochemical storage battery having a casing providing improved thermal dissipation, associated battery pack and production processes
A lithium electrochemical storage battery including: at least one electrochemical cell; two current collectors, one of which is connected to the anode and the other to the cathode; and a casing of longitudinal axis X, the casing including a cap, a bottom, a lateral jacket joined both to the bottom and to the cap, and a central core arranged along the axis X, the central core being hollow at least over some of its height and made of a material the melting point of which is higher than the temperature reached by the cell when it malfunctions, the hollow portion of the central core opening onto the exterior of casing via the bottom and/or the cap and the central core having, at least one end of its hollow portion, an internal thread into which an external thread of a part forming one pole of the storage battery may be screwed. |
| US09742043B2 |
Battery pack temperature control structure for electric vehicles
A battery pack temperature control structure is provided for an electric vehicle, and basically includes first and second battery modules, a temperature control unit and an air duct. The first and second battery modules are disposed inside a battery pack case. The second battery module has a lower height than the first battery module. The temperature control unit has an air blowing port for blowing a temperature control air to the first and second battery modules. The air duct is connected to the air blowing port of the temperature control unit, and has an air blowout opening arranged to blow out the temperature control air to a front of the first battery module at a location above the top of the second battery module. The air blowout opening-extends in a vehicle width direction and blows out the temperature control air toward the first battery module. |
| US09742039B2 |
Current collector, negative electrode and battery
A current collector including a first principal plane and a second principal plane with a roughness of a first principal plane and a roughness of a second principal plane being mutually different. |
| US09742034B2 |
Cyano-benzimidazole salts for electrochemical cells and method for synthesis thereof
The present invention discloses a new metal cyano-substituted benzimidazolide salt having formula (I) and its preparation. This new cyano-substituted benzimidazole derivatives exhibited excellent thermal stability. The organic salt of the present invention were soluble in an alkyl carbonate solvent, such as propylene carbonate (PC), dimethyl carbonate (DMC) and ethylene carbonate (EC)/DMC cosolvent. The non-aqueous electrolyte prepared by mixing the organic metal salt of the present invention with the alkyl carbonate solvent shows high conductivity and excellent electrochemical stability. The non-aqueous electrolyte is suitable for use in primary or secondary rechargeable batteries. |
| US09742032B2 |
Compound and electrolyte of lithium secondary battery containing the same
Provided are a novel compound, an electrolyte for a lithium secondary battery containing the same, and a lithium secondary battery containing the electrolyte for a lithium secondary battery according to the present invention. The electrolyte for a secondary battery according to the present invention may have significantly excellent high-temperature stability, low-temperature discharge capacity, and life cycle characteristics. |
| US09742030B2 |
Ionic gel electrolyte, energy storage devices, and methods of manufacture thereof
An electrochemical cell includes solid-state, printable anode layer, cathode layer and non-aqueous gel electrolyte layer coupled to the anode layer and cathode layer. The electrolyte layer provides physical separation between the anode layer and the cathode layer, and comprises a composition configured to provide ionic communication between the anode layer and cathode layer by facilitating transmission of multivalent ions between the anode layer and the cathode layer. |
| US09742027B2 |
Anode for sodium-ion and potassium-ion batteries
A first method for fabricating an anode for use in sodium-ion and potassium-ion batteries includes mixing a conductive carbon material having a low surface area, a hard carbon material, and a binder material. A carbon-composite material is thus formed and coated on a conductive substrate. A second method for fabricating an anode for use in sodium-ion and potassium-ion batteries mixes a metal-containing material, a hard carbon material, and binder material. A carbon-composite material is thus formed and coated on a conductive substrate. A third method for fabricating an anode for use in sodium-ion and potassium-ion batteries provides a hard carbon material having a pyrolyzed polymer coating that is mixed with a binder material to form a carbon-composite material, which is coated on a conductive substrate. Descriptions of the anodes and batteries formed by the above-described methods are also provided. |
| US09742024B2 |
Secondary battery, battery pack, electronic apparatus, electric tool, electric vehicle, and power storage system
A secondary battery including: spirally wound electrode body in which positive electrode and negative electrode are laminated via separator and spirally wound, wherein the positive electrode includes an inner circumference side positive electrode active material layer and an outer circumference side positive electrode active material layer while including a single side active material layer formation region, the ratio A/(A+B) of an area density A (mg/cm2) of the inner circumference side positive electrode active material layer and an area density B (mg/cm2) of the outer circumference side positive electrode active material layer, an inner diameter C (mm) of the coil opening portion, and the ratio D/E of a thickness D (μm) of the positive electrode and a thickness E (μm) of the positive electrode collector satisfy the relationship expressed in Formula 1, and a length F (mm) of the single side active material layer formation region satisfies the relationship expressed in Formula 2. |
| US09742023B2 |
Fuel cell, fluid distribution device for fuel cell, and vehicle provided with fuel cell
A fuel cell contains two or more fluid-supplying internal manifolds and fluid-discharging internal manifolds for each fluid. External manifolds include fluid-supplying external manifolds, which connect to the fluid-supplying internal manifolds, and fluid-discharging external manifolds, which connect to the fluid-discharging internal manifolds, for each fluid. The respective fluid-supplying and fluid-discharging external manifolds are positioned approximately in parallel with each other, extending in the width direction of a cell laminate body. |
| US09742021B2 |
High solubility iron hexacyanides
Stable solutions comprising high concentrations of charged coordination complexes, including iron hexacyanides are described, as are methods of preparing and using same in chemical energy storage systems, including flow battery systems. The use of these compositions allows energy storage densities at levels unavailable by other iron hexacyanide systems. |
| US09742019B1 |
Method for forming a nanoporous grain boundary structure
Gadolinium-doped cerium oxide slurries used to form a patchwork type surface structure with nanoporous grain boundary prepared by mixing gadolinium-doped cerium oxide and a polymer binder to form a first mixture; wet-atomizing the first mixture under a pressure of at least 100 MPa to obtain a second mixture; coating the second mixture to a substrate to fog in a coated substrate; and sintering the coated substrate. The patchwork type structure is a polygonal or honeycomb structure having a size of from 0.1 μm to 3 μm. |
| US09742018B2 |
Hydrogen oxidation and generation over carbon films
An electrode comprises an acid treated, cathodically cycled carbon-comprising film or body. The carbon consists of single walled nanotubes (SWNTs), pyrolytic graphite, microcrystalline graphitic, any carbon that consists of more than 99% sp2 hybridized carbons, or any combination thereof. The electrode can be used in an electrochemical device functioning as an electrolyser for evolution of hydrogen or as a fuel cell for oxidation of hydrogen. The electrochemical device can be coupled as a secondary energy generator into a system with a primary energy generator that naturally undergoes generation fluctuations. During periods of high energy output, the primary source can power the electrochemical device to store energy as hydrogen, which can be consumed to generate electricity as the secondary source during low energy output by the primary source. Solar cells, wind turbines and water turbines can act as the primary energy source. |
| US09742017B2 |
Fuel cell having multiple duplicate anode substrate layers
The fuel cell (100) includes an oxidant flow plate (212), an adjacent cathode substrate layer (216) having a cathode catalyst (222), a matrix (224) for retaining a liquid electrolyte (230), wherein the matrix (224) is secured adjacent and between the cathode catalyst (222) and an anode catalyst (232). A first anode substrate (102) is secured adjacent the anode catalyst (232), and at least a second duplicate anode substrate layer (108) is secured adjacent the first anode substrate layer (102) for providing greater pore volume for storage of the liquid electrolyte (230) and to limit obstruction of the pore volume of the anode substrates (102, 108). The duplicate anode substrate layer (108) may be partially filled with the liquid electrolyte (230) at the beginning of life of the fuel cell (100). |
| US09742012B2 |
Fuel cell and manufacturing method thereof having integrated membrane electrode assembly and gas diffusion layer
A fuel cell having a membrane electrode assembly (MEA) comprising an electrolyte membrane, an anode and a cathode; and a gas diffusion layer (GDL) combined with both surfaces of the MEA is provided. In particular, the GDL includes a first layer having a first surface that comes in contact with a reaction region of the MEA, a second layer formed on a second surface of the first layer, and a third layer formed along a peripheral portion between a first region in which both the first layer and the second layer are formed and a second region in which only the second layer is formed. The first layer may be a first microporous layer, the third layer may be a second microporous layer having a viscosity lower than that of the first microporous layer, and the second layer is not the first microporous layer and the second microporous layer. |
| US09742011B2 |
Tethering of confactors on graphene-like materials
A family of customizable tethering molecules for tethering cofactors such as, but not necessarily limited to, nicotinamine adenine dinucleotide (NAD+/NADH, NAD(P)+/NAD(P)H) to substrates or structures formed from or including graphene-like materials is described. The tethered cofactor can then be used, for example, as biosensors employed for clinical diagnostic, food industry, medical drug development and environmental and military applications, as well as in reagentless biofuel cells for power generation. |
| US09742010B2 |
Catalyst layer material, method for fabricating the same, and fuel cell
A catalyst layer material, a method for fabricating the same, and a fuel cell are provided. The catalyst layer material utilized for the fuel cell includes a catalyst support and a catalyst distributed on the catalyst support. The catalyst support contains TixM1−xO2, wherein M is selected from the group consisting of a Group IB metal, a Group IIA metal, a Group IIB metal, a Group IIIA, a Group VB metal, a Group VIB metal, a Group VIIB metal and a Group VIIIB metal, and 0 |
| US09742008B2 |
Solid, ionically conducting polymer material, and methods and applications for same
A rechargeable alkaline battery including an anode; a cathode; and an electrolyte is described. At least one of the anode, the cathode and the electrolyte includes a solid, ionically conducting polymer material. Methods for the manufacture of same are also described. |
| US09742003B2 |
Method of producing a silicon/carbon composite material and use of such a material
A method of producing a silicon/carbon composite material which includes the following successive steps: providing a silicon/polymer composite material from silicon particles and a carbonaceous polymer compound, precursor of carbon and able to be cross-linked, performing at least partial cross-linking of the polymer of the silicon/polymer composite material so as to obtain a cross-linked silicon/polymer composite material, the polymer having a cross-linking rate greater than or equal to 50% and, pyrolyzing the cross-linked silicon/polymer composite material until said silicon/carbon composite material is obtained. |
| US09742002B2 |
Positive electrode composition for nonaqueous electrolyte secondary battery
A positive electrode composition for nonaqueous electrolyte secondary battery comprises a lithium transition metal complex oxide represented by a general formula LiaNi1−x−yCoxM1yWzM2wO2, where 1.0≦a≦1.5, 0≦x≦0.5, 0≦y≦0.5, 0.002≦z≦0.03, 0≦w≦0.02, 0≦x+y≦0.7, M1 represents at least one selected from the group consisting of Mn and Al, and M2 represents at least one selected from the group consisting of Zr, Ti, Mg, Ta, Nb and Mo; and a boron compound comprising at least boron element and oxygen element. |
| US09741996B2 |
Construction of electrochemical storage cell
An electrochemical storage cell is disclosed that comprises a core and a rectangular shell that receives the core snugly therein. The rectangular shell has first and second open ends. A first end cap is used to close the first open end. An anode terminal extends through the first end cap from an interior portion of the electrochemical storage cell to an external portion thereof. A first gasket is secured within the rectangular shell between the first end cap and the core to resiliently hold the core away from the first end cap. A second end cap is used to close the second open end. A cathode terminal extends through the second end cap from an interior portion of the electrochemical storage cell to an external portion thereof. A second gasket is secured within the rectangular shell between the second end cap and the core to resiliently hold the core away from the second end cap. |
| US09741994B2 |
Secondary battery with current breaking mechanism
A rectangular secondary battery includes a current breaking mechanism with improved rigidity against vibration and impact. The current breaking mechanism is interposed in the middle of a current path electrically connected between an external terminal and a wound electrode group to break the current path by the rise of battery internal pressure. The current breaking mechanism includes a connection electrode arranged inside a battery lid and electrically connected to the external terminal, and a conductive plate bonded to the connection electrode and deformed by the rise of the battery internal pressure. The connection electrode includes a tabular member having a through hole in communication with the outside of the battery opening on a planar portion. The conductive plate includes a dome-shaped diaphragm portion gradually reducing its diameter as shifting in an axial direction and a flange portion extending radially outward from an outer peripheral portion of the diaphragm portion. |
| US09741983B2 |
Battery unit comprising an accommodating device and a plurality of electrochemical cells and battery module comprising a plurality of such battery units
A battery unit (1) comprising a plurality of electrochemical cells (2), which each have an electrode arrangement (3) comprising a cathode contact-making element (4) and an anode contact-making element (5), and an accommodating device (6) comprising a plurality of accommodating units (7), which are each separated from one another by side walls (8), wherein in each case the electrode arrangement (3) of an electrochemical cell (2) of the battery unit (1) is introduced into the accommodating units (7), and the accommodating units (7) are closed by at least one electrolytic barrier (10), which is connected to the accommodating device (6), in such a way that the closed accommodating units (7) with the electrode arrangements (3) arranged therein form the electrochemical cells (2) of the battery unit (1). |
| US09741982B2 |
Battery storage structure
A battery storage structure includes a battery storage portion, a battery terminal, a separate member, and an overhang portion. The battery storage portion includes a bottom surface portion and peripheral wall portion extending from the perimeter of the bottom surface portion in a direction that intersects with the bottom surface portion and forms a first opening. The battery terminal has a contact portion and is supported by the peripheral wall portion. The separate member is formed as a separate body from the battery storage portion. The overhang portion is provided on the separate member, is positioned on a first direction side with respect to the contact portion, and protrudes toward an inner side of the peripheral wall portion in a second direction. The first direction is a direction from the bottom surface portion toward the first opening. The second direction is a direction that intersects the first direction. |
| US09741978B2 |
Pulse laser welding aluminum alloy material, and battery case
This aims to provide a pulse laser welding aluminum alloy material, which can prevent the occurrence of an abnormal portion, when an A1000-series aluminum material is welded with a pulse laser, so that a satisfactory welded portion can be homogeneously formed, and a battery case. The pulse laser welding aluminum alloy material is made of an A1000-series aluminum material, and has a viscosity of 0.0016 Pa·s or less in a liquid phase. Alternatively, the pulse laser welding aluminum alloy material has such a porosity generation rate of 1.5 (μm2/mm) or less in the pulse-laser welded portion as is numerically defined by dividing the porosity total area (μm2), as indicated by the product of the sectional area and the number of porosities, by the length (mm) of an observation section. |
| US09741974B2 |
Battery cell having round corner
Disclosed herein is a battery cell configured to have a structure in which an electrode assembly, including positive electrodes, negative electrodes, and separators disposed respectively between the positive electrodes and the negative electrodes, is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, wherein the battery case is made of a one-unit member, which is bent to form an upper case and a lower case, at least one of the upper and lower cases is provided with a receiving part, in which the electrode assembly is mounted, the receiving part having a round corner formed at at least one side edge thereof, and sealed portions, which are formed at the upper case and the lower case by thermal welding, are located at an upper side of the battery case at which at least one electrode terminal is located, a first lateral side of the battery case adjacent to the upper side, and a lower side of the battery case opposite to the upper side, and a second lateral side of the battery case adjacent to the upper side is formed by a bent structure of the battery case. |
| US09741972B2 |
OLED device and preparation method thereof, and display device
An OLED device and a preparation method thereof, and a display device are provided. The OLED device comprises a substrate and a plurality of functional layers disposed sequentially on the substrate. One functional layer of the plurality of functional layers is a transition functional layer, the transition functional layer comprises a first sub-layer and a second sub-layer provided on the first sub-layer, the first sub-layer and the second sub-layer are made of a same material; and the first sub-layer is prepared by using a first process, and the second sub-layer is prepared by using a second process different from the first process. |
| US09741970B2 |
Method of manufacturing organic light emitting display
A method of manufacturing an organic light emitting display includes forming a first light-emitting layer on a substrate, forming a first portion of a second light-emitting layer on the first light-emitting layer, forming a third light-emitting layer on the first light-emitting layer, and forming a second portion of the second light-emitting layer on the first portion of the second light-emitting layer. |
| US09741959B1 |
Light emitting device
A light emitting device includes an electrode layer, a first metal layer, an organic material layer and a second metal layer stacked sequentially. The first metal layer includes a first metal portion and a second metal portion separated from the first metal portion at a first lateral distance, and the first metal portion and the second metal portion have a first period. The organic material layer includes a first emitting region separating the first metal portion and the second metal portion. The first lateral distance and the first period enable a lateral plasma coupling generated between the first metal portion and the second metal portion, such that light generated by the organic material layer at the first emitting region has a gain in a first waveband, or a peak wavelength of the light generated by the first emitting region shifts to the first waveband. |
| US09741958B2 |
Organic light emitting diode display panel and display device
An organic light emitting diode display panel is provided. The organic light emitting diode display panel comprises a glass substrate, a conductive layer, an anode, a hole inject layer, a hole transport layer, an organic light-emitting layer, an electron inject layer and a cathode. The present invention further provides an organic light emitting diode display device. The organic light emitting diode display panel and the organic light emitting diode display device can effectively reduce a horizontal resistance of the organic light emitting diode display panel through setting the conductive layer, thereby improving the luminous uniformity of the organic light emitting diode display panel. |
| US09741954B2 |
Optical detector and method for manufacturing the same
An optical detector (110) is disclosed. The optical detector (110) comprises: —an optical sensor (112), having a substrate (116) and at least one photosensitive layer setup (118) disposed thereon, the photosensitive layer setup (118) having at least one first electrode (120), at least one second electrode (130) and at least one photovoltaic material (140) sandwiched in between the first electrode (120) and the second electrode (130), wherein the photovoltaic material (140) comprises at least one organic material, wherein the first electrode (120) comprises a plurality of first electrode stripes (124) and wherein the second electrode (130) comprises a plurality of second electrode stripes (134), wherein the first electrode stripes (124) and the second electrode stripes (134) intersect such that a matrix (142) of pixels (144) is formed at intersections of the first electrode stripes (124) and the second electrode stripes (134); and —at least one readout device (114), the readout device (114) comprising a plurality of electrical measurement devices (154) being connected to the second electrode stripes (134) and a switching device (160) for subsequently connecting the first electrode stripes (124) to the electrical measurement devices (154). |
| US09741953B2 |
Organic field-effect transistor
An organic transistor including at least one lower substrate made of plastic material, two electrodes, respectively a source electrode and a drain electrode, deposited on the plastic substrate, a semiconductor layer made of an organic semiconductor material and deposited on the electrodes and the plastic substrate, a dielectric layer deposited on the semiconductor layer, and a gate electrode formed on said dielectric layer. It further includes a porous layer extending between the plastic substrate and the semiconductor layer, said porous layer extending at least between the source and drain electrodes, to decrease the dielectric constant of the surface of said plastic substrate. |
| US09741951B2 |
Substrate for organic electronic device and method for manufacturing same
Provided are a substrate for an organic electronic device (OED) and a use thereof. Provided is a substrate for a device having excellent durability by preventing interlayer delamination occurring due to internal stress in a structure in which an organic material and an inorganic material are mixed. In addition, provided is an OED having another required physical property such as excellent light extraction efficiency using the substrate, as well as the excellent durability. |
| US09741950B2 |
Polycyclic aromatic compound
The invention provides a polycyclic aromatic compound or a salt thereof having a partial structure represented by the following general formula (I): wherein X, ring A, ring B, ring C, and ring D are as defined in the specification. |
| US09741947B2 |
Organometallic complex and organic light-emitting device including the same
An organometallic complex represented by Formula 1 below and an organic light-emitting device including the same: Formula 1 is as defined in the specification. |
| US09741946B2 |
Light-emitting element containing organic iridium exhibits blue-green to blue light emission
An organometallic complex which can be provided at low cost and which emits blue phosphorescence is provided. An organometallic complex in which nitrogen at the 1-position of a 5-aryl-4H-1,2,4-triazole derivative is coordinated to a Group 9 metal or a Group 10 metal, the aryl group is bonded to the Group 9 metal or the Group 10 metal, and the 5-aryl-4H-1,2,4-triazole derivative is a 3-aryl-5,6,7,8-tetrahydro-4H-[1,2,4]triazolo[4,3-a]pyridine derivative is provided. The organometallic complex emits green to blue phosphorescence and is also advantageous in terms of cost. |
| US09741945B1 |
Tunable photoluminescent metal-organic-frameworks and method of making the same
The present disclosure is directed to new photoluminescent metal-organic frameworks (MOFs). The newly developed MOFs include either non rare earth element (REE) transition metal atoms or limited concentrations of REE atoms, including: Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Ru, Ag, Cd, Sn, Sb, Ir, Pb, Bi, that are located in the MOF framework in site isolated locations, and have emission colors ranging from white to red, depending on the metal concentration levels and/or choice of ligand. |
| US09741931B1 |
Semiconductor integrated circuit device including switching elements and method of manufacturing the same
A semiconductor integrated circuit device may include a first signal line, a second signal line, a variable resistance material layer, and a third signal line. The second signal line may be positioned coplanar with the first signal line. The second signal line may be parallel to the first signal line. The variable resistance material layer may include a horizontal region arranged on the first and second signal lines, and may include a vertical region extending upwardly from an end of the horizontal region. The third signal line may be positioned on a plane different from a plane on which the first and second signal lines may be positioned. The third signal line may be arranged on an end of the vertical region of the variable resistance material layer. |
| US09741928B2 |
Magnetoresistive element and magnetic random access memory
According to one embodiment, a magnetoresistive element comprises a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, a second nonmagnetic layer, and a third magnetic layer. The first magnetic layer has a variable magnetization direction. The second magnetic layer has an invariable magnetization direction and includes a nonmagnetic material film and a magnetic material film. The first nonmagnetic layer is arranged between the first magnetic layer and the second magnetic layer. The second nonmagnetic layer is arranged on a surface of the second magnetic layer. The third magnetic layer is arranged on a surface of the second nonmagnetic layer. The second nonmagnetic layer is in contact with the nonmagnetic material film included in the second magnetic layer. |
| US09741927B2 |
Method and system for providing magnetic junctions having a gradient in magnetic ordering temperature
A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer has a gradient in a magnetic ordering temperature such that a first portion of the free layer has a first magnetic ordering temperature higher than a second magnetic ordering temperature of a second portion of the free layer. The first portion of the free layer is closer to the reference layer than the second portion of the free layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. |
| US09741926B1 |
Memory cell having magnetic tunnel junction and thermal stability enhancement layer
A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material. |
| US09741924B2 |
Magnetic sensor having a recessed die pad
A magnetic sensor has a pair of Hall elements formed in spaced-apart relationship on a front surface of a semiconductor substrate. A die pad is bonded to a back surface of the semiconductor substrate and overlaps the Hall elements. The die pad has formed therein a magnetic converging plate holder having a recessed portion, and a magnetic converging plate having the same shape and size as the recessed portion is fitted in the recessed portion of the magnetic converging plate holder. |
| US09741919B2 |
Nano-scale superconducting quantum interference device and manufacturing method thereof
A nano-scale superconducting quantum interference device and a manufacturing method thereof, comprising the following steps of: S1: providing a substrate and growing a first superconducting material layer thereon; S2: forming a photo-resist layer and performing patterning; S3: etching the first superconducting material layer in a predetermined region; S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3; S5: growing a second superconducting material layer; S6: removing the structure above the plane where the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted; S7: forming at least one nanowire vertical to the insulating interlayer, to obtain the nano-scale superconducting quantum interference device. The width of the superconducting ring and the length of the nano junction are determined by the insulating interlayer. |
| US09741917B2 |
Thermoelectric module apparatus
Provided is a thermoelectric module apparatus including: a pipe-shaped housing having a hole that is longitudinally formed; a thermoelectric module coupled to the housing; and heat sinks combined with the thermoelectric module, in which the pipe-shaped housing has a plurality of mount holes having predetermined width and length, longitudinally extending, and arranged circumferentially in parallel with each other, the thermoelectric module has a plurality of thermoelectric plates having predetermined width, length, and thickness, the housing is connected to first sides in the width direction of the thermoelectric plates, the thermoelectric plates are disposed in the mount holes respectively with a portion in the width direction inserted and exposed inside the hole as much as a predetermined width and a portion in the width direction protruding and exposed outside the housing as much as a predetermined width, and the heat sinks are connected to the portions exposed outside the housing. |
| US09741916B2 |
System and method for harvesting energy down-hole from an isothermal segment of a wellbore
Systems and methods of generating power in a wellbore extending through a subterranean formation are described. A swirling flow of pressurized fluid is passed through a vortex tube to generate a temperature differential between first and second outlets of the vortex tube. The temperature differential is applied to a thermoelectric generator configured to convert the temperature differential into a voltage. The thermoelectric generator produces electrical power that is transmittable to down-hole tools within the wellbore such as an inflow control valve. |
| US09741910B1 |
Optoelectronic component
An optoelectronic component includes a housing having a cavity in which an optoelectronic semiconductor chip having an emission face that emits light rays and a transparent potting material are arranged, wherein the cavity includes at least one side wall at least partly reflecting light rays incident on the side wall and reflectivity of which decreases as an operating period of the component increases, conversion particles are embedded into the potting material, which conversion particles convert light rays having a first wavelength incident on the conversion particles into light rays having a second wavelength, and scattering particles are embedded into the potting material, which scattering particles scatter light rays incident on the scattering particles and the scattering capability of which scattering particles increases as the operating period increases. |
| US09741908B2 |
Wavelength converting member, light-emitting device, and method for producing wavelength converting member
A wavelength converting member includes silica glass and a plurality of fluorescent material particles including an oxynitride or nitride fluorescent material and dispersed in the silica glass. The plurality of fluorescent material particles include at least two kinds of fluorescent material particles including (i) first fluorescent material particles that emit a fluorescence having a first peak wavelength and (ii) second fluorescent material particles that emit a fluorescence having a second peak wavelength. The wavelength converting member has a density within a range from 0.8 g/cm3 to 1.2 g/cm3. |
| US09741904B2 |
Light emitting device
A light emitting device includes a light emitting chip which generates a first light having a first color, a first cavity layer disposed on the light emitting chip and which generates a second light having a second color and has a first refractive index, a second cavity layer disposed on the first cavity layer and which generates a third light having a third color and has a second refractive index, a first half mirror layer disposed between the first cavity layer and the light emitting chip and which reflects at least a portion of the second light, a second half mirror layer disposed between the first cavity layer and the second cavity layer and which reflects at least a portion of the third light, and a third half mirror layer disposed on the second cavity layer and which transmits the first light. |
| US09741902B2 |
Optoelectronic semiconductor chip
An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation. The semiconductor body includes a p-side and an n-side, between which the active layer is arranged. The p-contact layer is intended for electrical contacting the p-side. The n-contact layer is intended for electrical contacting the n-side 1b. The n-contact layer contains a TCO layer and a mirror layer, the TCO-layer being arranged between the n-side of the semiconductor body and the mirror layer. |
| US09741901B2 |
Two-terminal electronic devices and their methods of fabrication
Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV. |
| US09741897B2 |
Thin light emitting diode and fabrication method
A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure. |
| US09741886B2 |
Thin film solar collector and method
A flexible, CPV array having high incident light conversion efficiency, the CPV array comprising: a reflective surface; a plurality of photovoltaic cells configurable to collect radiation from the reflective surface; a concentrating lens (optics) configurable to concentrate the incident light onto the reflective surface and onto the plurality of photovoltaic cells; and a conductor adapted to conduct electricity and heat from the plurality of photovoltaic cells, wherein the CPV array is exposed to incident solar radiation to generate electricity without an incident solar tracking mechanism. |
| US09741884B2 |
Solar cell and method of fabricating the same
A solar cell according to the embodiment includes a plurality of back electrode patterns spaced apart from each other on a substrate; a light absorption layer including contact patterns to connect electrodes to each other and division patterns to divide cells into unit cells on the substrate formed with the back electrode patterns; top electrode patterns spaced apart from each other by the division patterns on the light absorption layer; and insulating patterns among the back electrode patterns or on the back electrode patterns. The top electrode patterns are filled in the contact patterns and electrically connected to the back electrode patterns. |
| US09741882B2 |
Tandem junction photovoltaic cell
A tandem junction photovoltaic cell has a first p-n junction with a first energy band gap, and a second p-n junction with a second energy band gap less than the first energy band gap. The junctions are separated by a quantum tunneling junction. The first p-n junction captures higher energy photons and allows lower energy photons to pass through and be captured by the second p-n junction. Quantum dots positioned within the first p-n junction promote quantum tunneling of charge carriers to increase the current generated by the first p-n junction and match the current of the second p-n junction for greater efficiency. |
| US09741879B2 |
SPAD photodiode covered with a network
The invention relates to a single-photon avalanche diode (SPAD) photodiode having a layer made of semiconductor material, including an N doped zone and a P doped zone separated by an avalanche zone. The semiconductor material layer is intercalated between a periodic structure and a low index layer having a refractive index less than that of the semiconductor material layer and less than that of the periodic structure. The periodic structure is deposited directly on the semiconductor material layer. The photodiode provides low temporal dispersion and high quantum efficiency, without requiring a strong charge acceleration voltage. |
| US09741878B2 |
Solar cells and modules with fired multilayer stacks
Intercalation pastes for use with semiconductor devices are disclosed. The pastes contain precious metal particles, intercalating particles, and an organic vehicle and can be used to improve the material properties of metal particle layers. Specific formulations have been developed to be screen-printed directly onto a dried metal particle layer and fired to make a fired multilayer stack. The fired multilayer stack can be tailored to create a solderable surface, high mechanical strength, and low contact resistance. In some embodiments, the fired multilayer stack can etch through a dielectric layer to improve adhesion to a substrate. Such pastes can be used to increase the efficiency of silicon solar cells, specifically multi- and mono-crystalline silicon back-surface field (BSF), and passivated emitter and rear contact (PERC) photovoltaic cells. Other applications include integrated circuits and more broadly, electronic devices. |
| US09741876B2 |
Composition for solar cell electrodes and electrode fabricated using the same
A composition for solar cell electrodes includes a silver powder; a glass frit; and an organic vehicle, wherein the glass frit includes bismuth (Bi), tellurium (Te), and chromium (Cr). |
| US09741873B2 |
Avalanche-rugged silicon carbide (SiC) power Schottky rectifier
In at least one general aspect, a SiC device can include a drift region of a first conductivity type, a shielding body, and a Schottky region. The SiC device can include a rim having a second conductivity type at least partially surrounding the shielding body and the Schottky region. The SiC device can include a termination region at least partially surrounding the rim and having a doping of the second conductivity type. The termination region can have a transition zone disposed between a first zone and a second zone where the first zone has a top surface lower in depth than a depth of a top surface of the second zone and the transition zone has a recess. |
| US09741872B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode, is provided beside the second semiconductor region in a second direction crossing a first direction from the first electrode toward the second electrode, and a portion of the first semiconductor region is positioned between the third and second semiconductor regions. The fourth semiconductor region is provided between the portion of the first semiconductor region and the second electrode and has a greater impurity concentration than the second and third semiconductor regions. |
| US09741866B2 |
Semiconductor device
To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer. A metal element contained in the glass substrate has a concentration lower than or equal to 5×1018 atoms/cm3 at the interface between the first gate insulating film and the second gate insulating film or the interface between the gate electrode layer and a gate insulating film. |
| US09741865B2 |
Method of forming semiconductor device including oxide semiconductor stack with different ratio of indium and gallium
A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer. |
| US09741864B2 |
Thin-film transistor and method for manufacturing same
The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage. |
| US09741858B2 |
Amorphous silicon semiconductor TFT backboard structure
The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT. |
| US09741856B2 |
Stress retention in fins of fin field-effect transistors
Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. |
| US09741855B2 |
Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. |
| US09741852B2 |
Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess. |
| US09741849B1 |
Integrated circuits resistant to electrostatic discharge and methods for producing the same
Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel. |
| US09741848B2 |
Multi-gate tunnel field-effect transistor (TFET)
A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region. |
| US09741847B2 |
Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device
One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region. |
| US09741840B1 |
Electronic device including a multiple channel HEMT and an insulated gate electrode
An electronic device can include a lower channel layer, an upper channel layer overlying the lower channel layer and having an opening extending through the upper channel layer. The electronic device can further include an insulator within the opening; and a gate electrode extending into the opening, wherein the insulator is disposed between the gate electrode and the second channel layer. A double channel transistor can include the lower and upper channel layers and the gate electrode. In a further embodiment, a conductive member can be used to electrically short the channel layers near the gate electrode. In an embodiment, the transistor can be enhancement-mode transistor. A process can include forming the insulator such that it is in the form of a sidewall spacer or as an insulating layer along the sidewall and bottom of the opening through the upper channel layer. |
| US09741839B1 |
Gate structure of thyristor
A thyristor device that can include a disc-shaped device comprising a semiconductor material forming alternating p-n-p-n type layers. The device can include a gate area extending from an external gate lead contact point to a plurality of thyristor units connected in parallel. Each thyristor unit can include at least one exposed pB layer portion to form at least one plural point to which gate current can be directed. Further, an insulator layer can be formed over the gate area to insulate at least a portion of the gate electrode from the pB layer so that displacement current can be directed to short dots and then to the plural points. Current entering each thyristor unit can generate a turned-on area at each thyristor unit that spreads throughout the thyristor device. |
| US09741834B2 |
Heterojunction bipolar transistor architecture
A transistor includes a sub-collector, a base, a collector between the sub-collector and the base, and an emitter on the base opposite the collector. The collector includes a first region adjacent to the base and a second region between the first region and the sub-collector. The first region has a graduated doping profile such that a doping concentration of the first region decreases in proportion to a distance from the base. The second region has a substantially constant doping profile. By providing the collector with a doping profile as described, the linearity of the transistor is significantly improved while maintaining the radio frequency (RF) gain thereof. |
| US09741830B2 |
Method for forming metal oxide semiconductor device
The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same. |
| US09741829B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer. |
| US09741825B1 |
Method for manufacturing field effect transistor having widened trench
A method for manufacturing a field effect transistor having a widened trench forms sequentially an epitaxial layer, a trench, an oxidation layer, a trench-oxidation layer, a polysilicon layer, a residual oxidation layer, an electrode portion, a lower trench, a widened trench, a gate portion, a body region, a source region, an interlayer dielectric layer and a source electrode. The trench is formed at the epitaxial layer. The oxidation layer, the trench-oxidation layer and a polysilicon layer are then formed. The residual oxidation layer and the electrode portion are formed in the trench by etching the polysilicon layer and the trench-oxidation layer. The lower trench is formed by etching the epitaxial layer. The widened trench is formed by widening a portion of the trench away from a trench bottom so as to have the electrode portion and the residual oxidation layer disposed at the lower trench. |
| US09741823B1 |
Fin cut during replacement gate formation
A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack. |
| US09741821B1 |
Two-step dummy gate formation
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor substrate between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin. A dummy gate electrode is formed to cover a middle portion of the semiconductor fin, with an end portion of the semiconductor fin uncovered by the dummy gate electrode. The dummy gate electrode includes a lower dummy gate electrode portion, and an upper dummy gate electrode portion including polysilicon over the lower dummy gate electrode portion. The lower dummy gate electrode portion and the upper dummy gate electrode portion are formed of different materials. Source/drain regions are formed on opposite sides of the dummy gate electrode. The dummy gate electrode is replaced with a replacement gate electrode. |
| US09741819B2 |
Transistor device and fabrication method
The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance. |
| US09741818B2 |
Manufacturing method of semiconductor structure for improving quality of epitaxial layers
A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers. |
| US09741817B2 |
Method for manufacturing a trench metal insulator metal capacitor
A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial layer and to the first metal layer; removing the sacrificial layer by a second removal process that is less aggressive than the first removal process; fabricating an insulator layer on the first metal layer; and depositing a second metal layer on the insulator layer. |
| US09741802B2 |
Semiconductor device with breakdown preventing layer
A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film or a low conductive film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film or the low conductive film. The conducting elements can vary in at least one of composition, doping, conductivity, size, thickness, shape, and distance from the device channel along a lateral length of the insulating film or the low conductive film, or in a direction that is perpendicular to the lateral length. |
| US09741801B2 |
Method for producing a semiconductor device
A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A nitride film is deposited and a first oxide film is deposited that contains an impurity having a second conductivity type that differs from the first conductivity type. The first oxide film, the nitride film, and the second oxide film are etched to form a contact hole. An epitaxial growth process is carried out form a first pillar-shaped silicon layer in the contact hole. The nitride film is removed and epitaxial growth process is performed to form an output terminal. |
| US09741800B2 |
III-V multi-channel FinFETs
A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric. |
| US09741799B2 |
Silicon carbide semiconductor device and method for manufacturing the same
A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode. |
| US09741798B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a structure, an insulating film, a control electrode, first and second electrodes. The structure has a first surface, and includes a first, a second, and a third semiconductor region. The structure has a portion including the first, second, and third semiconductor regions arranged in a first direction along the first surface. The insulating film is provided on the first surface. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The insulating film includes a charge trap region. A bias voltage is applied to the first and second electrodes, and includes a shift voltage. The shift voltage shifts a reference potential of a voltage applied to the first and second electrodes by a certain voltage. |
| US09741796B2 |
Graphene-based valley filter and method for operating the same
A graphene-based valley filter includes a bottom gate, a bilayer graphene and two top gates. The bilayer graphene is deposited on the bottom gate and includes scattering defects. The top gates are deposited on the bilayer graphene. The top gates define a channel in the bilayer graphene, and the scattering defects are located in the vicinity of the channel. A vertical electric field is formed to open a band gap and produce electronic energy subbands in the channel. A transverse in-plane electric field is formed to produce pseudospin splitting in the subbands of the bilayer graphene. The scattering defects are for producing scattering between two opposite energy valley states of the bilayer graphene, couples subband states of opposite pseudospins and opens a pseudogap at a crossing point of the two subbands. Electrons are passed through the channel to become valley polarized in the bilayer graphene. |
| US09741795B2 |
IGBT having at least one first type transistor cell and reduced feedback capacitance
An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric. |
| US09741792B2 |
Bulk nanosheet with dielectric isolation
Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided. |
| US09741790B2 |
Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs. |
| US09741787B2 |
Methods and apparatus for high voltage integrated circuit capacitors
High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed. |
| US09741785B2 |
Display tile structure and tiled display
A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer. First and second electrically conductive tile micro-wires and first and second conductive tile contact pads are electrically connected to the first and second tile micro-wires, respectively. The light emitter includes a plurality of semiconductor layers and the first and second electrodes are disposed on a common side of the semiconductor layers opposite the emitter side of the tile layer. The first and second tile micro-wires and first and second tile contact pads are disposed on the backplane side of the tile layer. |
| US09741784B2 |
Organic light emitting display device and method of manufacturing the same
An organic light emitting display device includes a substrate including a plurality of pixel areas, each of the plurality of pixel areas including a light emitting region and a transmission region, a first electrode disposed on the light emitting region of the substrate, a second electrode opposing the first electrode, an organic light emitting layer which is disposed on the light emitting region of the substrate and disposed between the first electrode and the second electrode, and an auxiliary electrode which is disposed on the transmission region of the substrate and electrically connected to the second electrode. |
| US09741781B2 |
Optoelectronic component with adjustable light emission and method for producing the same
Various embodiments may relate to an optoelectronic component, including an optoelectronic structure, which is designed to provide a first electromagnetic radiation, and a measuring structure, which is designed to measure electromagnetic radiation, wherein the measuring structure has an optically active structure and at least one electro-optical structure. The optically active structure is optically coupled to the optoelectronic structure. The optically active structure is designed to absorb an electromagnetic radiation in such a way that the optically active structure produces a measured signal from the absorbed electromagnetic radiation. The absorbed electromagnetic radiation at least partially includes the first electromagnetic radiation and/or at least one second electromagnetic radiation of an external radiation source. The electro-optical structure is designed in such a way that the electro-optical structure has an adjustable transmittance, such that the fraction of the second electromagnetic radiation incident on the optically active structure can be adjusted. |
| US09741775B2 |
Display device
A display device includes a plurality of pixels on a substrate including an insulating surface. Each of the plurality of pixels includes: a transistor above the insulating surface; a planarization film covering the transistor; a pixel electrode above the planarization film and electrically connected with the transistor; an insulating layer filled in a recess located around the pixel electrode between the pixels adjacent to each other; a light-emitting layer covering a surface of the pixel electrode and at least a part of a surface of the insulating layer; and a counter electrode above the light-emitting layer. A distance between a surface of the substrate and a face of the light-emitting layer in contact with the insulating layer is equal to or smaller than a distance between the surface of the substrate and a face of the light-emitting layer in contact with the pixel electrode. |
| US09741771B2 |
Method for manufacturing organic light emitting diode display
A manufacturing method of an organic light emitting device may include the following. A panel displaying an image is formed. A buffering member including a dummy buffering member is adhered to the panel. A film is adhered to an upper surface of the buffering member. The film and the dummy buffering member are removed. |
| US09741768B1 |
Controlling memory cell size in three dimensional nonvolatile memory
A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material. |
| US09741767B2 |
Electronic device
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction. |
| US09741765B1 |
Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer. |
| US09741764B1 |
Memory device including ovonic threshold switch adjusting threshold voltage thereof
A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction. |
| US09741756B2 |
Image sensor including planar boundary between optical black and active pixel sensor areas
An image sensor includes a substrate including a sensor array area, a pad area, and a circuit area, a wiring layer on the pad area, and a light-shielding pattern on the sensor array area. The sensor array area includes a first area including active pixels and a second area including optical back pixels. The wiring layer is apart from the substrate by a first distance on the pad area. The light-shielding pattern includes a first portion spaced apart from the substrate by a second distance less than the first distance, a second portion disposed between the first portion and the wiring layer and extending on the same level as the wiring layer, and a third portion disposed between the first portion and the second portion and integrally formed with the first portion and the second portion. |
| US09741755B2 |
Physical layout and structure of RGBZ pixel cell unit for RGBZ image sensor
An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region. The pixel cell unit has a fourth transfer gate transistor gate on the semiconductor surface coupled between a first infrared photodiode region and a second capacitance region. |
| US09741753B2 |
Array substrate and manufacturing method thereof, and display apparatus thereof
An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof and a display apparatus. The array substrate includes a base substrate, wherein, the base substrate is provided with a bonding region; a bonding pad and a first bonding lead connected with the bonding pad and extending to an edge of the base substrate are provided in the bonding region, and one or more metal patterns are arranged above the first bonding lead, the one or more metal patterns crossing over the first bonding lead and being insulated from the first bonding lead. |
| US09741742B2 |
Deformable electronic device and methods of providing and using deformable electronic device
Some embodiments include a method of providing an electronic device. The method includes: (i) providing a carrier substrate, (ii) providing a device substrate comprising a first side and a second side opposite the first side, the device substrate having a flexible substrate, (iii) coupling the first side of the device substrate to the carrier substrate; and (iv) after coupling the first side of the device substrate to the carrier substrate, providing two or more active sections over the second side of the device substrate, each active section of the two or more active sections being spatially separate from each other and having at least one semiconductor device. Other embodiments of related methods and devices are also disclosed. |
| US09741735B2 |
Vertical memory devices having charge storage layers with thinned portions
A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion. |
| US09741732B2 |
Integrated structures
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material. |
| US09741731B2 |
Three dimensional stacked semiconductor structure
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer. |
| US09741727B2 |
Semiconductor memory with U-shaped channel
A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a first layer of insulation film arranged on the U-shaped channel region, a floating gate provided with a notch, a second layer of insulation film, a control gate, a p-n junction diode arranged between the floating gate and the drain region, and a gate controlled diode formed by the control gate, the second layer of insulation film, and the p-n junction diode and using the control gate as a gate. Under the precondition of not increasing the manufacturing cost and difficulty of the semiconductor memory with a U-shaped channel and not affecting the performance of the semiconductor memory with a U-shaped channel, the dimension of a semiconductor storage device is further reduced and the chip density is increased by arranging the notch in the floating gate. |
| US09741725B2 |
Semiconductor device
A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode. |
| US09741723B2 |
Semiconductor device having shallow trench isolation structure
A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c. |
| US09741719B2 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures. |
| US09741714B2 |
Inductor structure
An inductor structure includes a first inductor and a second inductor. The second inductor includes a loop that surrounds the first inductor. The first inductor includes a first loop and a second loop, and a crossover section coupling the first loop to the second loop so as to cause current flowing through the first inductor to circulate around the first loop in a first rotational direction and around the second loop in a second rotational direction opposite to the first rotational direction; wherein the first and second inductors are arranged in an equilibrated configuration about a first axis that bisects the inductor structure such that the first loop is on one side of the first axis and the second loop is on a second side of the first axis, such that the magnetic interaction between the inductors due to current flow in the inductors is cancelled out. |
| US09741711B2 |
Cascode semiconductor device structure and method therefor
In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. |
| US09741710B2 |
Electrostatic discharge protection device and method for manufacturing the same, and chip component with the same
An electrostatic discharge protection device includes a base, a plurality of electrodes arranged on the base separated from each other, a function layer supplied on a separation space between the electrodes and a composite insulating layer disposed on the base and composed of inorganic particles dispersed in a resin, the composite insulating layer covering the electrodes and the function layer. |
| US09741709B2 |
ESD protection device
The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and electrically connected to first and second input/output terminals of the ESD protection circuit, a rewiring layer formed on the surface of the Si substrate for electrically connecting the pads and metal plated films, and an insulating resin film formed on the rear surface of the Si substrate. Thus, provided is an ESD protection device which can suppress the influence of external noise, etc. |
| US09741707B2 |
Immunity to inline charging damage in circuit designs
Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device. |
| US09741703B1 |
Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one TS-short-related failure mode, and one AA-short-related failure mode. |
| US09741702B2 |
Semiconductor power modules and devices
An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. |
| US09741695B2 |
Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate. |
| US09741691B2 |
Power delivery network (PDN) design for monolithic three-dimensional (3-D) integrated circuit (IC)
Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die. |
| US09741690B1 |
Redistribution layers in semiconductor packages and methods of forming same
An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant. |
| US09741688B2 |
Method for manufacturing a semiconductor device
A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components. |
| US09741687B2 |
Integrated circuit structure with active and passive devices in different tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure. |
| US09741686B2 |
Electronic package and method of connecting a first die to a second die to form an electronic package
Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity. |
| US09741682B2 |
Structures to enable a full intermetallic interconnect
A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process. |
| US09741676B1 |
Tin-indium based low temperature solder alloy
A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0 wt. % of silver (Ag), 0.25-2.0 wt. % of copper (Cu), 0.1-0.5 wt. % of zinc (Zn), and a remainder of tin (Sn). In implementations, a sulfur compound may be included in a concentration of 100 ppm to 500 ppm in the alloy to prevent oxidation of zinc and indium on the surface of the alloy. The solder alloy is particularly useful for but not limited to solder on pad applications in first level interconnect semiconductor device packaging. |
| US09741671B1 |
Semiconductor die with backside protection
A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A signal net is connected to the first polysilicon layer by way of a metal contact and a conductive wire is formed above the active region. During an invasive attack, when a trench is formed in the substrate and an electrically conductive filling is deposited in the trench, the signal net, the conductive wire, and the first polysilicon shape form a short-circuit, which renders the die dysfunctional and thereby foiling the invasive attack. |
| US09741658B2 |
Electrical fuse structure and method of formation
A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed at a first end and a cathode disposed at a second end. A fuse link extends between and contacts the anode and the cathode. A boundary between the fuse link and the cathode has a center point, and each connector of a plurality of cathode connectors has a center point that is an equal distance from the center point of the boundary between the fuse link and the cathode. In some such embodiments, each connector of the plurality of cathode connectors is a different size than an anode connector, whereas in some such embodiments, each connector of the plurality of cathode connectors is substantially a same size as the anode connector along at least one axis. |
| US09741653B2 |
Devices and methods related to radio-frequency switches having reduced-resistance metal layout
Devices and methods related to radio-frequency (RF) switches having reduced-resistance metal layout. In some embodiments, a field-effect transistor (FET) based RF switch device can include a plurality of fingers arranged in an interleaved configuration such that a first group of the fingers are electrically connected to a source contact and a second group of the fingers are electrically connected to a drain contact. At least some of the fingers can have a current carrying capacity that varies as a function of location along a direction in which the fingers extend. Such a configuration of the fingers can desirably reduce the on-resistance (Ron) of the FET based RF switch device. |
| US09741650B2 |
Wiring board and semiconductor package
A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of the metal layer facing away from the bottom surface of the recess is closer to the bottom surface of the recess than is the surface of the wiring layer. |
| US09741643B2 |
Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns. |
| US09741640B2 |
Semiconductor device
A light-emitting element according to the present invention includes a semiconductor light-emitting element having a front surface and a rear surface so that light is extracted from the rear surface, and having a first n-side electrode and a first p-side electrode on the front surface, and a support element having a conductive substrate having a front surface and a rear surface as well as a second n-side electrode and a second p-side electrode formed on the front surface of the conductive substrate, the first n-side electrode and the second n-side electrode, and the first p-side electrode and the second p-side electrode are so bonded to one another respectively that the semiconductor light-emitting element is supported by the support element in a facedown posture downwardly directing the front surface, and the support element has an n-side external electrode and a p-side external electrode formed on the rear surface of the conductive substrate, a conductive via passing through the conductive substrate from the front surface up to the rear surface for electrically connecting the second n-side electrode and the n-side external electrode and/or the second p-side electrode and the p-side external electrode with each other, and an insulating film formed between the via and the conductive substrate to cover the side surface of the via. |
| US09741636B1 |
Nano-thermal agents for enhanced interfacial thermal conductance
A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport across boundary or interfacial layers that exist at bulk material interfaces is disclosed. The nanoparticles do not need to be used in a fluid carrier or as filler material within a bonding adhesive to enhance thermal transport, but simply in a dry solid state. The nanoparticles may be equiaxed or acicular in shape with large aspect ratios like nanorods and nanowires. |
| US09741633B2 |
Semiconductor package including barrier members and method of manufacturing the same
A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire. |
| US09741632B2 |
Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and a buried oxide (BOX) layer over the at least one device layer. A polymer layer is disposed over the BOX layer, wherein the polymer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm. |
| US09741628B2 |
Method for manufacturing semiconductor module and intermediate assembly unit of the same
A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights different from each other to a metal foil disposed at one side of an insulating substrate; connecting a plurality of wiring members, not interconnecting the semiconductor elements, to front face electrodes of the semiconductor elements through solder so that heights from a surface of the insulating substrate to top faces of the wiring members become same level with each other; inspecting a leakage current while applying electricity on each one of semiconductor elements individually through the wiring members; and connecting the top faces of the wiring members with a bus bar. |
| US09741623B2 |
Dual liner CMOS integration methods for FinFET devices
One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for an NFET device and an upper portion of a second fin for a PFET device, performing a first conformal deposition process to form a conformal etch stop layer around the upper portion of both the first and second fins, with the NFET device masked, performing a second trench etching process to define a lower portion of the second fin, and performing a second conformal deposition process to form a conformal protection layer adjacent the upper portion of the second fin and on sidewalls of the lower portion of the second fin. |
| US09741621B2 |
Nano wire structure and method for fabricating the same
A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings. |
| US09741619B2 |
Methods for singulating semiconductor wafer
Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies. |
| US09741617B2 |
Encapsulated semiconductor package and method of manufacturing thereof
Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer. |
| US09741616B2 |
Method for producing optoelectronic semiconductor components, leadframe assembly and optoelectronic semiconductor component
In one embodiment, the method is configured for producing optoelectronic semiconductor components (1) and includes the steps of: providing a leadframe assembly (20) with a multiplicity of leadframes (2), each having at least two leadframe parts (21, 22); forming at least a part of the leadframe assembly (20) with a housing material for housing bodies (4); dividing the leadframe assembly (20) between at least one part of the columns (C) and/or the rows (R), wherein the leadframes (2) remain arranged in a matrix-like manner; equipping the leadframes (2) with at least one optoelectronic semiconductor chip (3); testing at least one part of the leadframes (2) equipped with the semiconductor chips (3) and formed with the housing material after the step of dividing; and separating to form the semiconductor components (1) after the step of forming and after the step of testing. |
| US09741614B1 |
Method of preventing trench distortion
A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask. |
| US09741611B2 |
Method of forming semiconductor device including protrusion type isolation layer
A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion. |
| US09741610B2 |
Sacrificial amorphous silicon hard mask for BEOL
A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon. |
| US09741607B2 |
Photo pattern method to increase via etching rate
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided. |
| US09741604B2 |
MOSFETs with channels on nothing and methods for forming the same
A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer. |
| US09741599B2 |
High voltage chuck for a probe station
A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface. |
| US09741593B2 |
Thermal management systems and methods for wafer processing systems
A workpiece holder includes a puck having a cylindrical axis, a radius about the cylindrical axis, and a thickness. At least a top surface of the puck is substantially planar, and the puck defines one or more thermal breaks. Each thermal break is a radial recess that intersects at least one of the top surface and a bottom surface of the cylindrical puck. The radial recess has a thermal break depth that extends through at least half of the puck thickness, and a thermal break radius that is at least one-half of the puck radius. A method of processing a wafer includes processing the wafer with a first process that provides a first center-to-edge process variation, and subsequently, processing the wafer with a second process that provides a second center-to-edge process variation that substantially compensates for the first center-to-edge process variation. |
| US09741591B2 |
Wafer level packaging of microbolometer vacuum package assemblies
An apparatus for the wafer level packaging (WLP) of micro-bolometer vacuum package assemblies (VPAs), in one embodiment, includes a wafer alignment and bonding chamber, a bolometer wafer chuck and a lid wafer chuck disposed within the chamber in vertically facing opposition to each other, means for creating a first ultra-high vacuum (UHV) environment within the chamber, means for heating and cooling the bolometer wafer chuck and the lid wafer chuck independently of each other, means for moving the lid wafer chuck in the vertical direction and relative to the bolometer wafer chuck, means for moving the bolometer wafer chuck translationally in two orthogonal directions in a horizontal plane and rotationally about a vertical axis normal to the horizontal plane, and means for aligning a fiducial on a bolometer wafer held by the bolometer wafer chuck with a fiducial on a lid wafer held by the lid wafer chuck. |
| US09741588B2 |
Method of manufacturing thin-film transistor substrate
A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed. |
| US09741585B1 |
Reactive radical treatment for polymer removal and workpiece cleaning
A method for removing polymer is provided. An aqueous solution is applied to a semiconductor workpiece with polymer arranged thereon. The aqueous solution comprises an energy receiver configured to generate reactive radicals in response to energy. Energy is applied to the aqueous solution to generate the reactive radicals in the aqueous solution and to remove the polymer. A process tool for generating the reactive radicals is also provided. |
| US09741584B1 |
Densification of dielectric film using inductively coupled high density plasma
A method for densifying a dielectric film on a substrate includes arranging a substrate including a dielectric film on a substrate support in a substrate processing chamber; supplying a gas mixture including helium and oxygen to the substrate processing chamber; controlling pressure in the substrate processing chamber to a pressure greater than or equal to a predetermined pressure; supplying a first power level at a first frequency to a coil to create plasma in the substrate processing chamber. The coil is arranged around an outer surface of the substrate processing chamber. The method includes densifying the dielectric film for a predetermined period. The pressure and the first power level are selected to prevent sputtering of the dielectric film during densification of the dielectric film. |
| US09741582B2 |
Method of forming a semiconductor device including a pitch multiplication
Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer. |
| US09741575B2 |
CVD apparatus with gas delivery ring
The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber. |
| US09741573B2 |
NAND flash memory and fabrication method thereof
A method is provided for fabricating a NAND flash memory. The method includes providing a semiconductor substrate having an isolation material layer formed on the semiconductor substrate, a selection gate material layer formed on the isolation material layer, and a plurality of alternately stacked gate dielectric material layers and control gate material layers formed on the selection gate material layer; forming a hard mask layer having a plurality of openings on a surface of the uppermost control gate material layer; forming a stacked gate structure on the semiconductor substrate, wherein the stacked gate structure includes a selection gate on the semiconductor substrate and control gates on the selection gate, and a width of the stacked gate structure is the same as a width of the hard mask layer on a top surface of the stacked gate structure; isolating the selection gate and the control gates by a gate dielectric layer. |
| US09741572B1 |
Method of forming oxide layer
A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time. |
| US09741571B2 |
Bipolar transistor device with an emitter having two types of emitter regions
Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recombination region is located at least in the first type emitter regions and the third type emitter regions. |
| US09741570B1 |
Method of manufacturing a reverse-blocking IGBT
A method of manufacturing a reverse-blocking IGBT (insulated gate bipolar transistor) includes forming a plurality of IGBT cells in a device region of a semiconductor substrate, forming a reverse-blocking edge termination structure in a periphery region of the semiconductor substrate which surrounds the device region, etching one or more trenches in the periphery region between the reverse-blocking edge termination structure and a kerf region of the semiconductor substrate, depositing a p-type dopant source which at least partly fills the one or more trenches and diffusing p-type dopants from the p-type dopant source into semiconductor material surrounding the one or more trenches, so as to form a continuous p-type doped region in the periphery region which extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate after thinning of the semiconductor substrate at the bottom surface. |
| US09741569B2 |
Forming memory using doped oxide
A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip. |
| US09741567B2 |
Method of forming multiple patterning spacer structures
Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening. |
| US09741562B2 |
Method for forming polysilicon film
Provided is a method for forming a silicon film, and more particularly, to a method for forming a polycrystalline silicon film including pretreatment process in a process for forming a silicon film. According to an embodiment of the present invention, a method for forming a polycrystalline silicon film by annealing a amorphous silicon film deposited on a base, the method includes a pretreatment process of allowing a pretreatment gas including at least one of N, C, O and B to flow. |
| US09741555B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device, includes: supplying a first precursor and a first nitriding agent onto a substrate having a surface formed thereon with an oxygen-containing film in order to form an initial film on the oxygen-containing film; modifying the initial film into a first nitride film by nitriding the initial film with plasma; and supplying a second precursor and a second nitriding agent onto the substrate in order to form a second nitride film on the first nitride film. |
| US09741554B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate. |
| US09741548B2 |
Mass spectrometer
The mass spectrometer (1) provides an ionization chamber (11) therein with: a probe (15) having a sample to be measured flow path (155) for spraying a sample to be measured; and a standard sample flow path (255) for spraying a standard sample used for the calibration of the mass-to-charge ratio of the mass spectrum into the ionization chamber. The standard sample is intermittently introduced into the ionization chamber via a pulse valve (216). Thus, mixing of the sample to be measured and the standard sample can be prevented, while the timing according to which the standard sample is introduced can be appropriately controlled. It also becomes possible to acquire an accurate mass spectrum for each sample to be measured even in the case where a number of types of samples to be measured are introduced into the ionization chamber one after another over a short period of time. |
| US09741547B2 |
Low-pressure plasma system with sequential control process
The low pressure plasma system includes a treatment chamber which is pumped out in a first process step by means of a pump. In a second process step a gas supply valve is opened in order to achieve a defined gas composition in the treatment chamber at low pressure. In a third process step a plasma generator is switched on in order to ignite a plasma in the treatment chamber. In a fourth process step a flushing valve can be opened in order to flush the treatment chamber. In a fifth process step the treatment chamber can be ventilated by way of a ventilation valve. The sequential switching element can be a rotary switch and include a zero switching position where the low pressure plasma system is off. The sequential switching element renders possible a simple embodiment of the low pressure plasma system and its intuitive operation. |
| US09741543B2 |
Multi-range voltage sensor and method for a voltage controlled interface of a plasma processing system
A voltage sensor for a voltage controlled interface of a plasma processing system. The voltage sensor receives a RF signal generated by a pickup device. The RF signal is indicative of a RF voltage provided at a substrate in a plasma chamber. The voltage sensor includes first and second dividers corresponding to first and second channels and having first and second capacitance ratios. The dividers receive the RF signal and respectively generate first and second reduced voltage signals. A first output of the first channel outputs a first output signal based on the first reduced voltage signal and while the RF signal is in a first voltage range. A second output of the second channel outputs a second output signal based on the second reduced voltage signal and while the RF signal is in a second voltage range. |
| US09741540B2 |
Method for surface treatment of upper electrode, plasma processing apparatus and upper electrode
In a method for surface treatment of an upper electrode, a first step is performed to roughen a facing surface of the upper electrode facing a lower electrode while depositing a CF-based deposit on the facing surface by using a plasma of a processing gas by supplying a first and second high frequency powers to the lower and upper electrode. A second step is performed to remove a part of the CF-based deposit by using a plasma of a processing gas by supplying the second high frequency power to the upper electrode only, and a third step is performed to remove the CF-based deposit remaining in the second step by using a plasma of a processing gas by supplying the first and second high frequency powers to the lower and upper electrode. Further, the first, second and third steps are repeated multiple times. |
| US09741538B2 |
Plasma processing apparatus, plasma processing method, and method for manufacturing electronic device
Linear coils, a first ceramic block, and a second ceramic block are arranged in an inductively-coupled plasma torch. A chamber has an annular shape. Plasma generated inside the chamber is ejected to a substrate through an opening portion in the chamber. The substrate is processed by relatively moving the chamber and the substrate in a direction perpendicular to a longitudinal direction of the opening portion. The coil is arranged inside a rotating cylindrical ceramic pipe. Accordingly, the plasma can be generated with excellent power efficiency, and fast plasma processing can be performed. |
| US09741537B1 |
Method and apparatus for supplying ion beam in ion implantation process
A method for generating an ion beam in an ion implantation process is provided. The method includes supplying a working gas into a first portion of an arc chamber which is separated from a second portion of the arc chamber by an intermediate plate. The method further includes guiding the working gas into the second portion of the arc chamber via a plurality of gas outlets formed at two opposite edges of the intermediate plate. The method also includes generating an ion beam from the working gas in the second portion of the arc chamber. |
| US09741536B2 |
High aspect ratio structure analysis
Curtaining artifacts on high aspect ratio features are reduced by reducing the distance between a protective layer and feature of interest. For example, the ion beam can mill at an angle to the work piece surface to create a sloped surface. A protective layer is deposited onto the sloped surface, and the ion beam mills through the protective layer to expose the feature of interest for analysis. The sloped mill positions the protective layer close to the feature of interest to reduce curtaining. |
| US09741533B2 |
Image type electron spin polarimeter
Provided is an image type electron spin polarimeter. It at least comprises a scattering target, a two-dimensional electron detector and an electron bending unit, wherein the electron bending unit is used for bending the orbit of the incident (scattered) electrons to a first (second) angle to arrive the scattering target (two-dimensional electron detector) with an optimal incident angle, and to transfer the image of the electron intensities from the entrance plane (scattering target) to the scattering target (two-dimensional electron detector) with small aberrations, and to separate the orbits of incident and scattered electrons to increase the degree of freedom of the geometric configuration of each component of the spin polarimeter. At least one of the first and second angles is not 0°, thereby achieving the first transfer of the two-dimensional image of electron intensities on the entrance plane to the scattering target and the second transfer from scattering target to the two-dimensional electron detector respectively with small aberrations, and then achieving multichannel measurements of the electron spin. |
| US09741531B2 |
Charged particle beam device enabling facilitated EBSD detector analysis of desired position and control method thereof
A charged particle beam device allowing an analysis position in a sample analyzable with an EBSD detector to be acquired beforehand, and allowing a sample to be adjusted to a desired analysis position in a short time. A charged particle beam device is provided with a charged particle source (111), a charged particle optical system (115), an EBSD detector (101), a sample stage (116), an image display unit (117) for displaying a portion of the sample observable with the EBSD detector and a non-observable portion of the sample such that said portions are distinguished from each other, an operation input unit (121) where a position to be observed by the EBSD detector is entered, and a control unit (118) for controlling a planar movement, an inclination movement and a rotation movement of the sample stage so as to allow the observation position entered from the operation input unit to be observed with the EBSD detector. |
| US09741526B2 |
Charged particle beam apparatus and sample image acquiring method
Disclosed is a charged particle beam apparatus wherein a partitioning film capable of transmitting a charged particle beam is provided between a charged particle optical system and a sample, said charged particle beam apparatus eliminating a contact between the sample and the partitioning film even in the cases where the sample has recesses and protrusions. On the basis of detection signals or an image generated on the basis of the detection signals, a distance between a sample and a partitioning film is monitored, said detection signals being outputted from a detector that detects secondary charged particles discharged from the sample due to irradiation of a primary charged particle beam. |
| US09741519B2 |
Lockout relay device
This disclosure relates to various embodiments of lockout relay devices. In one embodiment, a lockout relay device may transition between a closed position and a lockout position in response to an action of a deck device. The lockout relay may further be configured to transition from the lockout position to the closed position only in response to one of a manual adjustment and a reset operation. A manual actuator may permit a manual transition of the lockout relay device from the closed position to the lockout position and from the lockout position to the closed position. The lockout relay device may remain in the lockout position until the occurrence of one of a manual adjustment and a reset operation. |
| US09741516B2 |
Electromagnetic relay for vehicle
In an electromagnetic relay, terminal slits into which a coil terminal connected to a coil, a fixed contact terminal to which a fixed contact is attached, and a movable contact terminal electrically connected to a movable contact are inserted into is formed in a base, and the base is formed with ventilation holes used to discharge gas generated in an internal space and discharge vapor generated in the internal space. The ventilation holes are formed so as to be connected with the terminal slits. |
| US09741513B2 |
Double-contact switch with vacuum switching chambers
A double-contact switch has first and second tubular vacuum switching chambers; a stationary electrode, between the first and second vacuum switching chamber, having a first stationary contact protruding into the first chamber and a second stationary contact protruding into the second chamber; a first electrode, arranged in the first chamber, moveable axially therein, having a contact support region and sealed off from the first chamber exterior; a second electrode, arranged in the second chamber, moveable axially therein, having a contact support region and scaled off from the second chamber exterior; a first contact compression spring applying a first spring force to the first movable electrode so the first electrode contact presses onto the contact protruding into the first chamber; and a second contact compression spring applying a greater, second spring force to the second movable electrode so the second electrode contact presses onto the contact protruding into the second chamber. |
| US09741504B2 |
Electronic component having movable contact
An electronic component comprising: a case; a switching mechanism incorporated within the case; an actuator configured to actuate the switching mechanism, the actuator being mounted in the case so as to be displaceable by sliding; and a rubber cap configured to seal a sliding part of the actuator, wherein the rubber cap is made of a hydrin-based rubber. |
| US09741502B2 |
Mechanical axle structure for key
A mechanical axle structure suitable for a key includes a base, a function axle for generating a switch signal and a cover plate. The base, the function axle and the cover plate are connected in order from bottom to top. An upper portion of a supporting piece is fixed with a bottom surface of the cover plate, while a lower portion is fixed with the base. The function axle passes through the supporting piece to support against the bottom surface of the cover plate. |
| US09741500B1 |
Terminal connecting mechanism for molded case circuit breaker
A terminal connecting mechanism for a molded case circuit breaker that does not need a tool for connection or release between a wire and a terminal is disclosed. The terminal connecting mechanism of a molded case circuit breaker comprises a supporter having a through hole portion for allowing passing through of a terminal of the molded case circuit breaker and a terminal seat portion where the terminal, which has passed through the through hole portion, is mounted; a spring of which one end is supported by the supporter; and a lever member being in contact with the other end of the spring, rotataby moving to a position for allowing insertion of a wire to contact the terminal, and pressurizing the wire by means of an elastic force of the spring to maintain a contact state between the wire and the terminal. |
| US09741496B2 |
Stacked-type solid electrolytic capacitor package structure and method of manufacturing the same
A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit, and a conductive unit. The capacitor unit includes a plurality of first stacked-type capacitors sequentially stacked on top of one another, and each first stacked-type capacitor has a first positive portion and a first negative portion. The package unit includes a package resin body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion and a first exposed portion, and the second conductive terminal has a second embedded portion and a second exposed portion. An outermost one of first stacked-type capacitors has a plurality of first exposed soldering microgrooves formed on an outer surface thereof for contacting the package resin body. The instant disclosure further provides a method of manufacturing a stacked-type solid electrolytic capacitor package structure. |
| US09741491B2 |
Multilayer ceramic electronic component including a pair of side outer electrodes and a center electrode
A multilayer ceramic electronic component includes a multilayer ceramic element with first through sixth surfaces, a center outer electrode located between a first-side outer electrode and a second-side outer electrode on the multilayer ceramic element. A first plated film is provided on the center outer electrode, second plated films are provided on the first-side outer electrode and the second-side outer electrode, respectively, and a thickness of each of the second plated films is greater than a thickness of the first plated film. |
| US09741488B2 |
Power transmission coil
A power transmission coil includes a plane coil including a no-wire portion and a coil wound about a no-wire portion, a cover for covering the plane coil from above, a first foreign-matter-detecting unit provided at the no-wire portion, and a power control circuit electrically connected to the plane coil and the first foreign-matter-detecting unit. An upper surface of the cover has a first inclining portion inclining toward the first foreign-matter-detecting unit. The power control circuit transmits power through the plane coil if a foreign matter is not detected in the no-wire portion based on an output from the first foreign-matter-detecting unit. The power control circuit is configured to stop transmitting power through the plane coil if foreign matter is detected in the no-wire portion based on an output from the first foreign-matter-detecting unit. This power transmission coil is capable of detecting a small foreign matter that may generate heat. |
| US09741482B2 |
Electromagnetic actuator with reduced performance variation
An electromagnetic actuator includes a housing and a bobbin positioned within the housing and secured relative thereto so as to be centered therein, the bobbin comprising a bobbin formed of a non-magnetic material. The electromagnetic actuator also includes a coil wound about the bobbin and a magnetic circuit comprising a plurality of actuator components positioned within the housing and on or adjacent to the bobbin. The actuator components include a permanent magnet that induces a magnetic flux flow through the magnetic circuit so as to generate a magnetic force, and an armature selectively movable within an opening formed through the bobbin responsive to the magnetic force and to current selectively provided to the coil. The bobbin locates and centers the components of the magnetic circuit about the central axis and provides a bearing surface for the armature as it moves within the opening formed through the bobbin. |
| US09741481B2 |
Electromagnetic actuating mechanism
An electromagnetic actuating mechanism comprising an armature unit (10) which can be moved by a certain armature excursion along an axial direction of travel as a result of stationary coil means being energized, plunger means (16) which are associated with the armature unit, are designed such that the end thereof cooperates with an external actuating partner, and can be moved by a certain plunger excursion along the direction of travel from a starting position into an engagement position, and spring means (22) which bias the plunger means in the direction of travel. |
| US09741479B2 |
Magnetic powder for magnetic recording medium
Provided is magnetic powder capable of enhancing simultaneously both magnetic characteristics including SNP and durability of a magnetic recording medium. The hexagonal ferrite magnetic powder for a magnetic recording medium has a Ba/Fe molar ratio of 8.0% or more, a Bi/Fe molar ratio of 2.5% or more and an Al/Fe molar ratio of from 3.0 to 6.0%. The magnetic powder preferably has an activation volume Vact of from 1,400 to 1,800 nm3. The magnetic powder particularly preferably has a coercive force Hc of from 159 to 279 kA/m (which is approximately from 2,000 to 3,500 Oe) and a coercivity distribution SFD of from 0.3 to 1.0. The magnetic powder may contain, as an element that substitutes an Fe site of the hexagonal ferrite, at least one kind selected from divalent transition metals M1 and tetravalent transition metals M2. |
| US09741477B2 |
Sintered body for varistor, multilayer substrate using same, and production method for these
To provide a zinc oxide-based varistor that exhibits adequate characteristics without using antimony. Disclosed is a sintered body for a varistor, including zinc oxide as a main component; 0.6 to 3.0 mol % of bismuth oxide in terms of bismuth (Bi); 0.2 to 1.4 mol % of cobalt oxide in terms of cobalt (Co); 0.1 to 1.5 mol % of chrome oxide in terms of chrome (Cr); and 0.1 to 1.5 mol % of manganese oxide in terms of manganese (Mn), wherein the contents of antimony (Sb), a rare earth element and tin (Sn) are not more than a level of impurities. |
| US09741476B2 |
Covers for distribution lines and insulators
A protective cover assembly for an electrical power distribution line conductor mounted on a horizontally oriented post insulator includes an insulator cover and a retaining pin. The insulator cover includes a cover body defining an insulator cavity configured to receive the insulator and a mounting bracket integral with the cover body. The mounting bracket defines a bracket slot having a bottom entry opening configured to receive the horizontally oriented insulator to couple the cover body to the insulator. The retaining pin is configured to close off the bottom entry opening to secure the insulator cover to the insulator. The cover body is formed of a flexible first material and the mounting bracket is formed of a second material that is more rigid than the first material. |
| US09741472B2 |
Method for manufacturing MgB2 superconductor, and MgB2 superconductor
Provided are a method for manufacturing MgB2 superconductor by pressure molding a mixture of Mg powder or MgH2 powder and B powder and heat-treating the mixture, the method including (I) a step of adding a polycyclic aromatic hydrocarbon to the B powder, while heating the mixture to a temperature higher to or equal to the melting point of the polycyclic aromatic hydrocarbon at the time of this addition, and thereby covering the surface of the B powder with the polycyclic aromatic hydrocarbon; and (II) a step of mixing the B powder having the surface covered with the polycyclic aromatic hydrocarbon, with the Mg powder or the MgH2 powder, or a step of combining the B powder having the surface covered with the polycyclic aromatic hydrocarbon, with an Mg rod; and an MgB2 superconducting wire which has high critical current density (Jc) characteristics and less fluctuation in the critical current density (Jc). |
| US09741469B2 |
Data cable for high-speed data transmissions
A data cable for high-speed data transmissions includes at least one wire pair formed of wires extending in a longitudinal direction and being surrounded by a shielding foil to form a pair shielding. A dielectric intermediate film or foil having a varying lay length is spun around the wire pair between the shielding foil and the wire pair, in order to effectively avoid a damping peak at high transmission frequencies. |
| US09741468B2 |
Power cable filler device and power cable comprising the same
A power cable and filler device adapted to bear against a first and second power cores in a power cable, including a first arced wall which defines a portion of a first circle having a first diameter, a second and third arced wall, each defining a portion of a second circle having a second diameter which is smaller than the first diameter. A chamber is formed between the first, second and third arced walls. |
| US09741465B2 |
Electrical cable assembly
In accordance with an embodiment, an electrical cable can be configured to electrically connect to contact pads that are carried by a substrate. The electrical cable can include at least one, such as a pair, of electrical signal conductors and at least one, for instance a pair, of electrically conductive drain wires. A drain wire in the electrical cable can define a first surface that is configured to face the signal conductors and a second surface that is opposite the first surface. The drain wire can define a width that is greater than 0.12 mm as measured from the first surface to the second surface along a straight line. At least one auxiliary wire can be attached to at least one drain wire. The auxiliary wire can be configured to attach to the substrate. |
| US09741459B2 |
Modularized process flow facility plan for storing hazardous waste material
A modularized system for processing, storing and/or disposing of a hazardous waste material is described. In one exemplary embodiment, the modularized system includes a container configured to sealingly contain hazardous waste material; a first cell, the first cell comprising a first area for manipulating the container; and a second cell, the second cell comprising a second area for manipulating the container. The second cell is isolated from the first cell. The first cell is held at a first pressure and the second cell held at a second pressure, the first pressure being less than the second pressure. An interlock couples the first cell to the second cell. The first cell, second cell and interlock are configured to allow the container to be transferred from the first cell to the second cell while maintaining at least one seal between the first cell and the second cell. |
| US09741458B2 |
Multimodal debris trap
In a debris trap that may be used in an Emergency Core Cooling System of a nuclear power plant, the filter media is arranged to define both filtration and bypass flowpaths that are in fluid communication with one another. At least initially, each of the filtration and bypass flowpaths are open, and the filtration and bypass flowpaths have relatively low and relatively high head loss, respectively. The debris trap is operative so that flow through the debris trap may passively, and typically gradually, transition from the filtration flowpaths to the bypass flowpath in response to the filter media collecting increasing amounts of debris. More specifically, initially substantially all of the flow may be through the filtration flowpaths, and thereafter the filtration flowpaths may become substantially obstructed so that substantially all of the flow is through the bypass flowpath. |
| US09741457B2 |
Method and apparatus for the generation, heating and/or compression of plasmoids and/or recovery of energy therefrom
Method and apparatus for heating and/or compressing plasmas to thermonuclear temperatures and densities are provided. In one aspect, at least one of at least two plasmoids separated by a distance is accelerated towards the other. The plasmoids interact, for instance to form a resultant plasmoid, to convert a kinetic energy into a thermal energy. The resultant plasmoid is confined in a high energy density state using a magnetic field. One or more plasmoids may be compressed. Energy may be recovered, for example via a blanket and/or directly via one or more coils that create a magnetic field and/or circuits that control the coils. |
| US09741450B2 |
Memory comprising a circuit for detecting a glitch on a line of the memory
A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal. |
| US09741442B2 |
System and method of reading data from memory concurrently with sending write data to the memory
A data storage device includes a memory, a controller, and a communication bus coupled to the memory and to the controller. The controller is configured to send a read-write command and write data to the memory via the communication bus. The read-write command indicates an address of requested data to be read from the memory. The controller is further configured to receive the requested data read from the memory. Communicating the requested data over the communication bus overlaps the write data being stored into the memory. |
| US09741435B1 |
Sense amplifier circuit
A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a transistor that includes a current terminal. The memory read operation includes two phases. During a first phase, a terminal of the capacitor is coupled to a first cell. During a second phase, the terminal of the capacitor is coupled a second cell. |
| US09741432B2 |
Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period. |
| US09741430B2 |
Static random access memory with reduced write power
A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes. |
| US09741425B2 |
Memory device and memory system including the memory device
A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank. |
| US09741423B2 |
Methods and apparatus for synchronizing communication with a memory controller
A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. |
| US09741417B1 |
Sense amplifier circuit
In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read. |
| US09741416B1 |
Memory devices based on gate controlled ferromagnestism and spin-polarized current injection
Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional (2D) topological insulator (TI) having an active area body. One or a pair of ferromagnetic storage units are provided on top of the 2D TI with a dielectric and a gate thereon. A first contact can be at one end of the 2D TI and a second contact can be at the other end of the 2D TI, with the one or pair of ferromagnetic storage units on the 2D TI between the two contacts to facilitate 2D TI transport along a one-dimensional edge of the first and/or second lateral side. Application of biases via the gate and the first and second contacts enable read and write operations. |
| US09741412B2 |
Semiconductor apparatus
A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas. |
| US09741411B2 |
Bank control circuit and semiconductor memory device for data access with limited bandwidth for commands
A bank control circuit includes an implicit signal generation unit suitable for activating an implicit signal when a first active signal corresponding to a bank which is in an activated state bank, among a plurality of banks; and a delay unit suitable for delaying the implicit signal by a predetermined time, wherein the bank corresponding to the first active signal is precharged based on the implicit signal and activated again based on the delayed implicit signal. |
| US09741410B2 |
Memory circuitry using write assist voltage boost
Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal. |
| US09741408B2 |
Semiconductor memory device having dummy word lines and operating method thereof
A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. A program voltage is supplied to a program word line that is electrically coupled to a memory cell to be programmed, and a level of a first dummy word line voltage supplied to a parallel dummy word line, which is disposed parallel to the program word line in the first direction is different from a level of a second dummy voltage supplied to a nonparallel dummy word line other than the parallel dummy word line. |
| US09741407B2 |
Semiconductor devices and semiconductor systems including the same
A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data. |
| US09741400B2 |
Semiconductor device, memory device, electronic device, and method for operating the semiconductor device
A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor. |
| US09741398B1 |
Using out-of-band signaling to communicate with daisy chained nonvolatile memories
Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling. |
| US09741390B1 |
Optical disc drive
An optical disc drive includes a spindle connected to an optical assembly. A disc clamp device is configured to hold an optical disc on the spindle. A contiguous opening on at least two adjacent sides in a plane of a disc mount position intersect at a common corner of the optical disc drive. |
| US09741385B1 |
Digital automatic power control
Systems and methods of digital automatic power control are presented. A preamplifier circuit may include a digital-to-analog converter (DAC) circuit to sample a power signal, such as a from a laser power monitor. The preamplifier may store the sample in an internal preamplifier memory. The sample may be utilized to update a current output of the preamplifier that affects the power signal. These systems and methods may be particularly useful for lasers and heat-assisted magnetic recording (HAMR), which may be utilized during a read mode or a write mode of a HAMR data storage device. |
| US09741384B1 |
Non-rotating optical storage
Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating. |
| US09741381B1 |
Near field transducers (NFTs) including a protective layer and methods of forming
Devices having air bearing surfaces (ABS), the devices include a near field transducer (NFT) that includes a disc; a peg, the peg including gold (Au), silver (Ag), copper (Cu), aluminum (Al), rhodium (Rh), iridium (Ir), or combinations thereof; and the peg having a front surface at the air bearing surface of the device, an opposing back surface, a top surface that extends from the front surface to the back surface, two side surfaces that extend from the front surface to the back surface and a bottom surface that extends from the front surface to the back surface; and a protective layer disposed on at least one surface of the peg, the protective layer comprising an oxide of a metal that has a higher oxidation tendency than that of the material of the peg. |
| US09741380B1 |
Generating defect signals in time based servo tape storage systems
In one embodiment, a computer-implemented method includes creating a spike in a servo channel from a predetermined start position to an end position, and storing servo data including at least a portion thereof generated during the spike. The spike has a predetermined amplitude. In another embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a controller to perform the foregoing method. |
| US09741374B1 |
Thermally-assisted magnetic recording head and manufacturing method therefor
A head includes a head body having a medium facing surface, and a protective film covering the medium facing surface. The head body includes a main pole, a waveguide, a plasmon generator, and a main light-blocking section. The waveguide has an entrance end face and an exit end face. The plasmon generator has a near-field light generating surface. The medium facing surface includes a first region including neither of the exit end face and the near-field light generating surface, and a second region including the exit end face and the near-field light generating surface. The protective film includes a first portion covering the first region, and a second portion covering the second region. The main light-blocking section is located to intersect an imaginary straight line connecting the entrance end face and the first region. |
| US09741360B1 |
Speech enhancement for target speakers
A method of speech enhancement for target speakers is presented. A blind source separation (BSS) module is used to separate a plurality of microphone recorded audio mixtures into statistically independent audio components. At least one of a plurality of speaker profiles are used to score and weight each audio components, and a speech mixer is used to first mix the weighted audio components, then align the mixed signals, and finally add the aligned signals to generate an extracted speech signal. Similarly, a noise mixer is used to first weight the audio components, then mix the weighted signals, and finally add the mixed signals to generate an extracted noise signal. Post processing is used to further enhance the extracted speech signal with a Wiener filtering or spectral subtraction procedure by subtracting the shaped power spectrum of extracted noise signal from that of the extracted speech signal. |
| US09741358B2 |
Method and system for interference suppression using blind source separation
A method of interference suppression is provided that includes receiving a first audio signal from a first audio capture device and a second audio signal from a second audio capture device wherein the first audio signal includes a first combination of desired audio content and interference and the second audio signal includes a second combination of the desired audio content and the interference, performing blind source separation using the first audio signal and the second audio signal to generate an output interference signal and an output audio signal including the desired audio content with the interference suppressed, estimating interference remaining in the output audio signal using the output interference signal, and subtracting the estimated interference from the output audio signal to generate a final output audio signal with the interference further suppressed. |
| US09741345B2 |
Method for segmenting videos and audios into clips using speaker recognition
A method for segmenting video and audio into clips using speaker recognition is provided to segment audio according to speaker audio, and to make audio clips correspond to the audio and video signals to generate audio and video clips. The method instantly trains an independent speaker model by increasing an unknown speaker source audio signal, and the speaker recognition result is applied to determine the audio and video clips. Independent speaker clips of source audio are determined according to the speaker model and the speaker model is renewed according the independent speaker clips of source audio. This method segments audio by the speaker model without waiting for complete speaker feature audio signals to be collected. The method is also able to segment the audio and video into clips based on the recognition result of speaker audio, and can be used to segment TV audio and video into clips. |
| US09741341B2 |
System and method for dynamic noise adaptation for robust automatic speech recognition
A speech processing method and arrangement are described. A dynamic noise adaptation (DNA) model characterizes a speech input reflecting effects of background noise. A null noise DNA model characterizes the speech input based on reflecting a null noise mismatch condition. A DNA interaction model performs Bayesian model selection and re-weighting of the DNA model and the null noise DNA model to realize a modified DNA model characterizing the speech input for automatic speech recognition and compensating for noise to a varying degree depending on relative probabilities of the DNA model and the null noise DNA model. |
| US09741337B1 |
Adaptive self-trained computer engines with associated databases and methods of use thereof
In some embodiments, the present invention provides for an exemplary computer system which includes at least the following components: an adaptive self-trained computer engine programmed, during a training stage, to electronically receive an initial speech audio data generated by a microphone of a computing device; dynamically segment the initial speech audio data and the corresponding initial text into a plurality of user phonemes; dynamically associate a plurality of first timestamps with the plurality of user-specific subject-specific phonemes; and, during a transcription stage, electronically receive to-be-transcribed speech audio data of at least one user; dynamically split the to-be transcribed speech audio data into a plurality of to-be-transcribed speech audio segments; dynamically assigning each timestamped to-be-transcribed speech audio segment to a particular core of the multi-core processor; and dynamically transcribing, in parallel, the plurality of timestamped to-be-transcribed speech audio segments based on the user-specific subject-specific speech training model. |
| US09741336B2 |
System and method for generating manually designed and automatically optimized spoken dialog systems
Disclosed herein are systems, computer-implemented methods, and tangible computer-readable storage media for generating a natural language spoken dialog system. The method includes nominating a set of allowed dialog actions and a set of contextual features at each turn in a dialog, and selecting an optimal action from the set of nominated allowed dialog actions using a machine learning algorithm. The method includes generating a response based on the selected optimal action at each turn in the dialog. The set of manually nominated allowed dialog actions can incorporate a set of business rules. Prompt wordings in the generated natural language spoken dialog system can be tailored to a current context while following the set of business rules. A compression label can represent at least one of the manually nominated allowed dialog actions. |
| US09741335B2 |
Steerable acoustic resonating transducer systems and methods
An acoustic transducer system for ultrasonic imaging may include an array of sub-wavelength ultrasonic transducer elements; at least one electromagnetically resonant element with an electromagnetic resonance within the electromagnetic frequency band coupled to each of the sub-wavelength ultrasonic transducer elements; at least one electromagnetically resonant element with an electromagnetic resonance within the electromagnetic frequency band coupled to each of the sub wavelength ultrasonic transducer elements; an electromagnetic transmission module configured to modify one or more characteristics of transmitted electromagnetic energy to effectuate an acoustic emission by the array of sub-wavelength transducer elements according to an acoustic transmission pattern corresponding to the respective electromagnetic resonance characteristics of at least some of the electromagnetically resonant elements coupled to the sub-wavelength ultrasonic transducer elements; and a common port configured to facilitate electromagnetic communication with each of the electromagnetically resonant elements coupled to the sub-wavelength transducer elements. |
| US09741329B2 |
Method for the synthetic generation of a digital audio signal
A method for the synthetic generation of a digital audio signal by means of periodic sampling of a waveform shall permit the user a particularly simple and intuitive access to the changing and creative transformation of the waveform on which the sampling is based. For this purpose, according to the invention, the waveform is specified by using control points, which, in addition to position parameters, may contain further attributes, of which the parameters and attributes can be changed individually over time by means of control signals or spontaneouseous intervention. The control-point values which result in this way can be interpreted either as direct amplitude-period phase or as magnitude-frequency or phase-frequency pairs. A continuous waveform is generated by interpolation or approximation of the control points and the parameters/attributes of the latter, which assume a time-specific value depending on the current control signals and other influences, and is used for further processing, e.g. spectral band limiting. |
| US09741327B2 |
Automatic transcription of musical content and real-time musical accompaniment
Various embodiments provide techniques for generating real-time musical accompaniment for musical content included in an audio signal. A real-time musical accompaniment system receives the audio signal via an audio input device. The system extract, from the audio signal, musical information characterizing at least a portion of the musical content. The system generates musical information that has at least one of a rhythmic relationship and a harmonic relationship with the musical information. The system generates an output audio signal that is complementary to the musical information. The system transmits, substantially immediately after receiving the audio signal, the output audio signal to an audio output device. |
| US09741322B2 |
Capturing device
A capturing device joins with an instrument to capture an accumulated body fluid in the instrument. The device has a tubular shape for capturing and containing a superfluous amount of fluid that has accumulated inside an instrument from performing on the instrument. The device joins with the instrument, proximally to an instrument fluid accumulation portion. For example, the device is oriented on the instrument to capture the fluid that accumulates in the spit valve. The instrument may require tilting or other manipulations to enable fluid to flow from the instrument fluid accumulation portion to a reception aperture. The device is capped on each end, whereby one of the capped ends form a secure seal for trapping the body fluid inside the device, and may also be removed for removing the body fluid. The device has an absorbent portion to absorb the fluid in an interior region. |
| US09741318B2 |
Image data encoding device and method
An image data encoding device includes a data block generating unit configured to split image data into a plurality of data blocks, and a compressing unit configured to generate compressed data with respect to each of the plurality of data blocks, the compressed data including position information regarding positions of first pixels each having a gray scale value equal to a reference gray scale value, and difference values between the reference gray scale value and gray scale values of second pixels, which are different from the reference gray scale value. |
| US09741316B2 |
Method and system for displaying pixels on display devices
A method for displaying pixels on display devices, comprising the steps of (a) Providing virtual pixel storage means, preferably one or more virtual frame buffers (6), for temporarily storing the pixel data, (b) Receiving pixel data into the virtual pixel storage means (6) from one or more pixel sources (5), (c) Processing the pixel data stored in the virtual pixel storage means, based on characteristic display parameters characterizing the display devices; and (d) Transmitting the pixel data from the virtual pixel storage means (6) to one or more virtual displays attached to the virtual pixel storage means via a network (7), based on a network transmission protocol. The invention further relates to a system for displaying pixels on display devices. |
| US09741314B2 |
Image data processing circuit and display system
There is an image data processing circuit including a memory storing input image data, the input image data being limited to a specific number of colors or to a specific image range, and a correction processing part replacing, when a predetermined tone change is present between a pixel in image data previous by one frame whose data is stored by the memory and a pixel in image data in a current frame whose data is input, a relevant pixel in the current frame with a color of a specific tone. The memory is built in an integrated circuit included in the correction processing part. |
| US09741311B2 |
Data line driver, semiconductor integrated circuit device, and electronic appliance with improved gradation voltage
In a data line driver, successively input image data are sequentially stored in a first data storage unit and a second data storage unit. A subtracter calculates a difference value between the image data stored in the first data storage unit and the image data stored in the second data storage unit. A timing pulse generator generates a timing pulse based on the calculated difference value, and a charge supply circuit supplies a charge to a gradation voltage output terminal in accordance with the timing pulse. The rising and falling characteristics of gradation voltage when the image data is changed are improved in this way. |
| US09741309B2 |
Method for driving display device including first to fourth switches
To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed. |
| US09741307B2 |
Display apparatus and method of driving the same
A display apparatus includes a timing controller for converting data values of black image signals to have one polarity with respect to a common voltage and for converting data values of low gray scale image signals to have one polarity with respect to the common voltage, a data driver for converting the image signals outputted from the timing controller into data voltages, and a plurality of pixels for receiving the data voltages in response to gate signals to display an image. The low gray scale image signals displays a gray scale equal to or less than a reference gray scale at a surrounding temperature lower than a reference temperature. |
| US09741303B2 |
Display apparatus with decreased afterimage
A display apparatus includes a display panel which includes a gate line, a data line and a storage line, and displays an image, a gate driving part configured to output a gate signal to the gate line, a data driving part configured to output a data signal based on an image data of the image to the data line, and a voltage providing part configured to apply an alternating current voltage to the storage line. |
| US09741301B2 |
Driving circuit of display panel, display device, and method for driving the driving circuit of the display panel
A driving circuit of a display panel includes a switching unit, a clamping unit that prevents reverse current leakage, a reference signal line coupled to a low level signal, a pull-up unit, and a pull-up control unit that drives the pull-up unit. An input end of the pull-up unit receives a second clock signal, and an output end of the pull-up unit is coupled to a current scan line, where the current scan line is coupled to a pull-down maintain unit, and the pull-down maintain unit includes a first switching unit and a second switching unit. The first switching unit and the second switching unit are connected between the current scan line and the reference signal line in parallel, where a control end of the first switching unit and a control end of the second switching unit are coupled to an output end of the switching unit, a control end of the switching unit receives a first clock signal, and an input end of the switching unit receives the second clock signal through the clamping unit. |
| US09741300B2 |
Liquid crystal apparatus
A drive circuit has a ferroelectric liquid crystal panel that operates at a given switching angle and response speed, a sensor that measures temperature, a drive circuit that supplies driving voltage to the ferroelectric liquid crystal panel, a waveform generation circuit that supplies a waveform signal to the drive circuit, and a control circuit that controls the waveform generation circuit; and in a first frame of the driving voltage, outputs during a first interval, a first voltage that is positive and outputs during a second interval that is longer than the first interval, a second voltage that is positive, and in a second frame, outputs during the first interval, the first voltage that is negative and outputs during the second interval that is longer than the first interval, the second voltage that is negative. The control circuit varies the first voltage and the second voltage according to the measured temperature. |
| US09741298B2 |
Display apparatus and method of driving the same
A display apparatus includes a display panel which displays an image, a timing controller which determines an inversion driving method of the display panel based on a waveform of a fed back common voltage from the display panel, and a data driver which outputs a data voltage to the display panel according to the inversion driving method. |
| US09741284B2 |
Mobile terminal and method of driving same
The present invention relates to a mobile terminal and a method of driving the same. The mobile terminal includes: a display configured to display information; and a controller configured to calculate FPS data indicative of the FPS rate for a running program and control the frame frequency of the display based on the FPS data. The method of driving the mobile terminal includes: displaying information on a display; and calculating FPS data indicative of the FPS rate for a running program and controlling the frame frequency of the display based on the FPS data. |
| US09741281B2 |
Coupling compensator for display panel and display device including the same
A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N−1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2. |
| US09741275B2 |
Panel detection circuit and display panel
The present disclosure relates to a panel detection circuit and a display panel. The panel detection circuit comprises a source detection unit comprising a source testing line and several source switching units, a gate detection unit comprising a gate control line, a gate testing line and several gate switching unit, wherein the source switching unit and the gate switching unit each comprise at least two switching elements to keep the source switching unit and the gate switching unit disenabled after the panel detection is completed. |
| US09741274B1 |
Vehicle mounted sign assembly and related methods
A vehicle mounted sign assembly comprises a base member having a top surface, a bottom surface, a leading edge, a trailing edge and side surfaces between the leading edges and the trailing edge, with the side surfaces tapering rearwardly to the trailing edge. The assembly further comprises a mounting assembly configured to support the base member. The mounting assembly comprises a first and a second vertical bars extending through respective openings on the bottom surface of the base member, a first and a second horizontal bars mounted in parallel and positioned between the first and second vertical bars, and a first and a second suction cups attached to respective bottom end of the first and second vertical bars for attachment to the body or a window of a vehicle. |
| US09741272B1 |
Methods, apparatuses, and control systems for adaptive wind-driven outdoor all-surrounding information display
A method for adaptive wind-driven outdoor all-surrounding information display is disclosed, the method including: 1) installing an outdoor information display apparatus, of which a support means cooperates with a wind rotating means to achieve wind power generation and rotational speed control of an information display means; 2) disposing a plurality of electronically controlled light-emitting display strips on the sails; 3) installing a plurality of working units of a motor/electric generation assembly; 4) installing a control system so that the dynamic trajectories of the rotating electronically controlled light-emitting display strips after they are lit are successively connected with each other thereby creating an all-surrounding and continuous visible graphic and textual image. Apparatuses and control systems implementing the above method are also provided. |
| US09741268B2 |
Point of purchase display
A point of purchase display for coupling to a commercial product on display at a retail store. The point of purchase display includes a flexible and wrinkle-resistant sheet material having indicia displayed thereon and at least one coupling member for coupling the sheet material to the commercial product. In example forms, the indicia being displayed on the sheet material is provided for advertisement or instructional purposes of the commercial product. |
| US09741264B2 |
Clinical assessment and training system
A system for medical training includes an anatomical simulator modeled after at least a portion of a body, the simulator including at least one external surface, and at least one cavity in fluidic communication with the external surface via a cavity. The system further includes at least one internal sensor positioned at an internal location of the anatomical simulator, the internal sensor positioned to receive an internal input based on forces applied from within the cavity, at least one external sensor positioned at an external location of the anatomical simulator and to receive an external input based on forces applied to the external surface, and a feedback display system in communication with the sensors to simultaneously record external sensor readings from the at least one external sensor and internal sensor readings from the at least one internal sensor and at least one time measurement device. |
| US09741260B2 |
Internet-based educational framework for the correlation of lessons, resources and assessments to state standards
An apparatus assists educators in selecting achievement tools to meet an applicable one of a plurality of sets of educational standards. A first table holds a plurality of educational standards and a plurality of linked keywords. A second table holds a plurality of achievement tools, such as lesson plans, assessments and resources, and a plurality of linked keywords. A table manipulator program permits an educator to select an educational standard and shows achievement tools applicable to the selected educational standard by having a matching of keywords linked to the achievement tools to keywords linked to the educational standards. |
| US09741247B2 |
Parking monitoring system
There is provided a parking monitoring system comprising one or more sensors adapted to be deployed within a parking slot; a controller unit adapted to be connected to the one or more sensors for receiving information from the one or more sensors when a vehicle is parked in the parking slot, wherein the received information comprises activation and de-activation signals of the one or more sensors; and wherein the controller unit is adapted to determine whether the vehicle parked within the parking slot is allowed to be parked inside the parking slot based on the received activation and de-activation signals. The system is particularly adapted to monitor whether vehicles of certain categories such as bicycles, vans, cars and trucks are parked within their respective parking zones reserved for these categories of vehicles. |
| US09741246B2 |
System for determining traffic information
A system determines traffic information. The system contains a terminal having a position determination device for determining a position of the vehicle, a storage device for storing reference positions defined by location coordinates, and a processor which works together with the position determining device and the storage device. The processor compares a specific position of the vehicle with stored reference positions to determine whether the vehicle has passed a reference position. A reference position is defined by a safety line extending through the location coordinates thereof. The processor also determines whether the vehicle has traversed a safety line and evaluates the traversing of a determined safety line as the vehicle passes the reference position defined by the safety line. Therefore, the system can determine a position in a simple and reliable manner, including in an inner-city road network. |
| US09741244B2 |
Methods, smart objects, and systems for naming and interacting with smart objects
A control device executing a networking framework for controlling a network of smart objects registered with a framework may interact with only those smart objects in a room. A radio frequency signal broadcast on the networking framework for reception by smart objects registered with the networking framework may cause each of the plurality of smart objects to transmit an ultrasound signal that may include an identifier, such as a generic identifier of the smart object that was assigned during registration with the network framework. The control device may receive the ultrasound signals only from the smart objects in the room. The control device may rename each smart object from which ultrasound signals were received with new identifying information that may include a reference to the room. The device may then communicate with the smart objects via the networking framework using the new identifying information. |
| US09741236B2 |
Consumer alarm with quiet button
An alarm system is disclosed. The alarm system includes an enclosure; at least one sensor, the sensor is configured to communicate a signal to the enclosure; and at least one of a wireless transceiver positioned in the enclosure, the transceiver configured to receive an activation signal and transmit an alarm signal. |
| US09741235B2 |
Digital real security system, method and program
A digital real security system, method and program reliably report the occurrence of an emergency situation in real time. The digital real security system comprises an abdominal pressure signal acquisition unit (101) that acquires an abdominal pressure signal from an abdominal pressure sensor (10) for detecting a user's abdominal pressure and acquires a respiration signal from a respiration sensor (20) for detecting the user's breathing, and a storage unit (105) that stores a normal-time number of breathing times and abdominal pressure pattern of the user detected by the abdominal pressure signal acquisition unit (101), and an abnormality determination unit (112) matches a number of breathing times and abdominal pressure pattern detected by the abdominal pressure signal acquisition unit (101) to that user's normal-time number of breathing times and abdominal pressure pattern stored in the storage unit (105), and determines whether it is abnormality based on the match result. |
| US09741234B2 |
Method and system for broadcasting a panic alert notification
The present invention relates to a method and system for broadcasting a panic alert notification in a communication network comprising a primary user and at least one secondary user. The method comprises the steps of receiving data relating to a panic alert and processing information and geo-location of the primary user. Further, a list of one or more secondary users to be notified of the primary user's emergency situation is determined and a broadcast alert message is transmitted to the one or more secondary users. The step of determining a list of one or more secondary users comprises determining a search range criteria in the vicinity of the geo-location of primary user, identifying a list of secondary users within the search range criteria and determining one or more first level and second level secondary users by mapping the list of secondary users with a list of users known to the primary user. |
| US09741228B1 |
Personal safety tracking using an apparatus comprising multiple sensors
A system and method for facilitating personal safety tracking monitoring via an apparatus with multiple sensors are disclosed. The sensors may include a water sensor, an accelerometer, a water pressure sensor, an ambient temperature sensor, and/or any other sensors. The apparatus may be configured to generate various alerts in response to signals generated by the sensors. For example, the apparatus may generate a drowning alert when a submersion signal is generated and a drowning acceleration signature is detected in the same period. As another example, an abduction alert may be generated when an abduction acceleration signature and an out-of-boundary situation is detected for the apparatus. The alerts generated by the apparatus may be transmitted to a server or a client device associated with the apparatus for further processing, which may include generating a notification for presentation on the client device in response to an alert being received from the apparatus. |
| US09741226B1 |
System, method and device for monitoring the status of an entity based upon an established monitoring profile
A method for monitoring a status of an entity presents an interface for defining status parameters for configuring a monitoring profile, receives input defining status parameters for configuring the monitoring profile, establishes the monitoring profile for a monitored entity based upon the received input defining status parameters for configuring the monitoring profile and executes the established monitoring profile according to the defined status parameters. A processor generates a user interface for receiving input defining status parameters for configuring a monitoring profile, establishes the monitoring profile for a monitored entity based upon the received input defining status parameters for configuring the monitoring profile and executes the established monitoring profile according to the defined status parameters. |
| US09741225B1 |
Safety detection system and method
There is provided a safety method of detecting and signaling presence of a danger related to a danger source, the method comprising providing a base station at the danger source comprising first detectors and second detectors, the base station being adapted to determine an angular position of a target detected by a first detector among the first detectors within a detection zone based on an angular orientation of the first detector known a priori by the base station, and to determine a distance of the target by activating a second detector among the second detectors to measure the distance between the target and the base station in response to the target detection; and providing targets with portable target devices adapted to send signals in response to signals received from the first detectors of the base station. The first detectors are radio frequency transceivers and the second detectors are ultrasound transceiver. There is also provided a safety system for detecting and signaling presence of a target in danger zone. |
| US09741223B2 |
Automated security system for schools and other structures
Disclosed are various embodiments for security systems for schools and similar structures. Various security devices may be monitored in a structure, such as a school, where at least one of the security devices includes a wall-mounted duress alarm, an electronic keypad, a radio-frequency identification (RFID) reader, a card access reader, a decibel meter, a smoke detector, or a mobile computing device. In response to a signal from one of the security devices being indicative of a breach having occurred in the structure, a predetermined breach policy may be automatically implemented that may include, for example, compartmentalizing a region of the structure by performing an automated closing of a door that separates the region of the structure from another region of the structure. |
| US09741216B1 |
Skin stretch instrument
A sensor records information about skin stretch perceived by a user based on an interaction with a real object. The sensor includes a mechanical housing configured to be worn on a finger of a user, and a mechanism coupled to the mechanical housing. The mechanism includes a first bearing that rotates in a first direction in response to an interaction with a surface. The mechanism also includes a second bearing coupled to the first bearing, such that rotation of the first bearing causes the second bearing to rotate in a direction opposite to the first direction. The second bearing is in contact with a portion of the finger, and includes a feedback surface that simulates a force associated with the interaction with the surface. The sensor includes a controller configured to monitor rotation of the second bearing and record skin stretch information responsive to the interaction with the surface. |
| US09741210B2 |
Gaming system and method providing a battling symbol generators game
Various embodiments of the present disclosure provide a gaming system and method providing a battling symbol generators game. In various embodiments, each symbol generator of a set of symbol generators employed for the battling symbol generators game is associated with one of a plurality of different characteristics. During play of the battling symbol generators game, the gaming system modifies the set of symbol generators upon the occurrence of various symbol generator set modification events such that more symbol generators of the set are associated with a particular characteristic and/or such that fewer symbol generators of the set are associated with another characteristic. The gaming system provides a bonus when a designated quantity of the symbol generators of the set are each associated with a particular characteristic. |
| US09741202B2 |
Method of online valuating a client and a system thereof
There is provided a system and method of online valuating a client in a computerized service system (e.g. game system). The method comprises: identifying all clients directly involved in a monetary event; for each identified directly involved client Ci, searching a stored plurality of records for all records informative of monetary chunks tagged with the client Ci as an owner, and associating with the client Ci a virtual account Ai, the virtual account Ai being informative of all monetary chunks in an ownership of the client Ci, thereby giving rise to a plurality of virtual accounts associated with the identified directly involved clients, wherein each monetary chunk is further tagged with a depositor client who introduced the respective monetary chunk into the service system and with respective timestamp; identifying every client tagged as depositor client to at least one monetary chunk corresponding to at least one virtual account of the plurality of virtual accounts, thereby giving rise to a plurality of clients indirectly involved in the event; and valuating one or more clients directly or indirectly involved in the event, wherein a value of each given client is calculated with consideration of all monetary chunks corresponding to the plurality of virtual accounts and tagged to the given client as a depositor client. |
| US09741201B2 |
Connected interleaved wagering system
A connected interleaved wagering system is disclosed, including an interactive controller configured to: communicate, to an application controller, first application telemetry, the first application telemetry associated with a first interactive application; communicate, to the application controller, second application telemetry, the second application telemetry associated with a second interactive application; receive a wager outcome; provide a display of the received wager outcome; a wager controller constructed to: receive a wager request; determine a wager outcome; and communicate, to the application controller, the wager outcome; and the application controller operatively connecting the interactive controller and the wager controller, the application controller constructed to: receive the first application telemetry; communicate, to the wager controller, the wager request; receive the wager outcome; communicate, to a session controller, updated user session information; receive, from the interactive controller, the second application telemetry; and communicate, to the interactive controller, the wager outcome. |
| US09741200B2 |
Modular gaming terminal configurations
Gaming machines, gaming systems, module systems for providing gaming machines, and methods for assembling modular gaming machines are disclosed. A module system is disclosed for providing gaming machines for conducting wagering games. The module system includes first and second display modules each with distinct dimensions and a respective display device operable to display randomly selected outcomes of a wagering game. The module system also includes first and second sets of outer fascia elements, and a core module with a housing that attaches to and supports the display modules, one at a time. Mounting the first display module and first set of fascia elements onto the core housing provides one distinct gaming machine configuration with a distinct appearance and footprint, whereas mounting the second display module and second set of fascia elements onto the core housing provides another distinct gaming machine configuration with a distinct appearance and/or footprint. |
| US09741198B2 |
Gaming device with special symbol
A gaming machine that provides a game in which an array of symbol positions are populated with game symbols from a set of game symbols, the set of game symbols including ordinary game symbols and at least one special symbol, the gaming machine being adapted to award an award if a winning combination of game symbols is displayed, the gaming machine including a user interface in communication with a game controller, wherein the game controller is adapted to enhance the characteristics of at least one of the ordinary game symbols to create at least one enhanced symbol based upon the relative location of the ordinary game symbol to a special symbol. |
| US09741197B2 |
Automated prescription dispensing system and method
An automated prescription dispensing system and method for facilitating dispensing of medications from an automated prescription dispenser designed for in-home use. The dispenser may connect to a remote patient monitoring center for monitoring of the patient's dispenser use and adherence to a medication regime. The dispenser may further connect to a remote medication operations center for monitoring replenishment of the patient's medications and to a remote medical center for monitoring the patient's reaction to medications and clinical signs. A connection to a data analytics center and analytical engine facilitates communications among and between the users and/or caregivers at the remote centers. The dispenser may be loaded with a standardized cartridge that is replenished according to the patient's needs. The dispenser is further equipped with a camera that allows a caregiver at the remote patient monitoring center to view the patient while the patient uses the dispenser. |
| US09741194B2 |
Banknote discrimination apparatus
A banknote discrimination apparatus includes a plurality of photoelectric conversion elements in which an incident light including fluorescence emitted from a banknote irradiated with excitation light enters; a plurality of organic film filters that are arranged so as to overlap each of the plurality of photoelectric conversion elements, and have mutually different transmission bands; a circuit including a plurality of pixel circuits which are each connected to one corresponding element among the plurality of photoelectric conversion elements and output a pixel signal converted by each photoelectric conversion element in accordance with an intensity of the incident light that transmits through the organic film filter and enters to the photoelectric conversion element; a spectral processor; and a discriminator. At least one of the plurality of organic film filters is a filter obtained by overlapping two or more filter layers on each other. |
| US09741192B2 |
Self-turning device with the ability to mix and identify balls, located in a portable compartment with auxiliary control elements
The present invention relates to a self-turning device with the ability to mix and identify balls located in a portable compartment with auxiliary control elements. The device is presented as a whole as a small portable stand-alone device with the ability to perform random drawings. The invention is therefore in the field of devices intended for games of chance and arcade games, such as lotteries, bingo, roulettes, board games, etc. |
| US09741191B1 |
System and method for recording waypoint images along a route
The present disclosure is directed to a route logging system. The route logging system includes a geographic location server, a user profile server, a mobile client device, and image recording device(s). The geographic location server has access to a waypoint database. The user profile server has access to a user profile database, which includes a plurality of user profiles each including at least one route log. Each route log includes at least one waypoint image. The mobile client device is associated with one or more of the plurality of user profiles included in the user profile database. When the mobile client device determines it is within a threshold distance of a specific geographic position, the mobile client device updates the respective route log. The one or more image recording device(s) record waypoint images that can be included in route logs and associated with specific geographic positions. |
| US09741184B2 |
Door handle with optical proximity sensors
A door handle including light emitters for emitting light out of the handle, light detectors, lenses oriented relative to the emitters and detectors such that for each emitter-detector pair, when a reflective object is located at a target position near the handle, corresponding to that emitter-detector pair, then the light emitted by that emitter passes through one of the lenses and is reflected by the object back through one of the lenses to that detector, a keyless lock that, when activated, scans for a digital key via wireless communication, and a processor operable to synchronously activate emitter-detector pairs, to recognize from the amounts of light received by the activated detectors, and from the target positions corresponding to the activated emitter-detector pairs, that the object is approaching the handle and performing a sweep gesture and, in response thereto, to activate the keyless lock. |
| US09741183B2 |
Systems and methods for optimizing data gathering in a network of moving things
Systems and methods for optimizing data gathering in a network of moving things. As non-limiting examples, various aspects of this disclosure provide systems and methods for operating sensor systems and collecting data from sensor systems in a network resource-efficient manner. |
| US09741181B2 |
Evaluating image values
Images of items are evaluated. A first image of the item, having a view of two or more of its surfaces, is captured at a first time. A measurement of at least one dimension of one or more of the surfaces is computed and stored. A second image of the item, having a view of at least one of the two or more surfaces, is captured at a second time, subsequent to the first time. A measurement of the dimension is then computed and compared to the stored first measurement. The computed measurement is evaluated based on the comparison. |
| US09741177B2 |
Transit fare collection system
A method and apparatus for collecting transit fares is disclosed. The method implements databases contained within a central database that receive data indicating value. Detectable objects are associated with an identifier, which is then associated with one of the databases. Each identifier stores available fare value data in a database. Detectors that read the identifiers are placed at trip starting and/or endings locations and are coupled or couplable to a local memory that stores the identifiers and associated available fare data. Data sets from the central database comprising an available fare value and its associated identifier are downloaded on to the local memories from the databases. Once a detectable object is detected, its associated identifier is read and a fare is debited from the available fare value. The databases and local memories are periodically updated with updated fare values associated with each identifier. |
| US09741175B2 |
Display apparatus assembly
A display apparatus assembly including: a display apparatus; and a speed measuring device that measures a movement speed of the display apparatus, wherein the display apparatus includes a glass-type frame that is mounted on a head of an observer and two image displaying devices for left and right eyes that are mounted in the frame, each of the image displaying devices includes an image forming device, an optical system that forms light output from the image forming device to be parallel light, and an optical device to which light output from the optical system is incident and in which the light is guided so as to be output, and a convergence angle is changed based on the movement speed of the display apparatus that is measured by the speed measuring device. |
| US09741173B2 |
System and method of operation for remotely operated vehicles with superimposed 3D imagery
The present invention provides a system and method of utilizing superimposed 3D imagery for remotely operated vehicles, namely 3D, reconstructed images of the environment of the ROV. In another aspect, it includes generating a virtual video of 3D elements in the operation environment, synchronizing the angle and position of the camera of a virtual video with the angle and position of a real camera, superimposing the virtual video and the real video from the real camera; superimposing these video feeds such that one is manipulated to show transparencies in areas of less interest, in order to show through the other video. It furthermore may include superimposing information, whether graphic, textual or both on to the hybrid virtual-real 3D imagery. The subject invention is also networked, such that the immersive visual interface described above accessible to a plurality of users operating from to plurality of locations. |
| US09741170B2 |
Method for displaying augmented reality content based on 3D point cloud recognition, and apparatus and system for executing the method
An augmented reality content display method and an apparatus and system for performing the same are disclosed. The method includes extracting, by a feature point classification device, feature points from a plurality of images captured while changing a capture point such that at least one of a capture position and a capture orientation is changed, tracking, by the feature point classification device, feature points extracted from the same area of the plurality of images to associate the tracked feature points with one another, calculating, by the feature point classification device, uncertainty about a position of the associated feature points, and classifying and storing, by the feature point classification device, the associated features as a recognition reference feature point group or a dummy feature point group according to the position uncertainty. |
| US09741164B2 |
3D map display system
A three-dimensional (3D) map display system displays a 3D map on which a ground surface and a feature are represented three-dimensionally. The 3D map display system includes (a) a map database for storing map data representing a 3D shape of the ground surface and the feature, (b) a first drawing unit for drawing the ground surface and the feature by executing depth determination by referring to the map database, and (c) a second drawing unit for drawing a target feature, which is a feature in which at least a part thereof is hidden by a ground surface or other features in the drawing by the first drawing unit, by overwriting the target feature on a drawing result by the first drawing unit by using the map data without executing depth determination with respect to the drawing result by the first drawing unit. |
| US09741162B2 |
Functional visualization in system-level multi-domain simulators
A functional visualization of high-level system variables is based on information from a simulation environment. A functional model is imported from the simulation environment, including function nodes and connections. Each function node includes a function name, an associated component from the simulated system, and an associated physical variable. Each connection includes source and destination functions and a connection type. Values for the physical variables are obtained via a subscription with the simulation environment. The functional visualization is created and displayed based on the functional model and the values. |
| US09741152B2 |
Image processing apparatus, image processing method, and computer program
An image processing apparatus includes a 3D image converter and a 3D image generator. The 3D image converter performs conversion processing for converting a 2D image including a plurality of planes that are created with virtual distances into a 3D image on the basis of the virtual distances among the plurality of planes of the 2D images. The 3D image generator generates a 3D image from the two-dimensional image on the basis of the conversion processing performed by the 3D image converter and displays the generated 3D image. When a virtual distance between the corresponding planes of the 2D image is changed while the 3D image is being displayed by use of the 3D image generator, the 3D image converter performs the conversion processing in accordance with a change in the virtual distance. |
| US09741150B2 |
Systems and methods for displaying representative images
A system, method, and computer program product for displaying representative images within a collection viewer is disclosed. The method comprises receiving a notification indicating a new orientation for the collection viewer, computing a current animation state for a current animation sequence associated with the collection viewer, identifying representative images to render in an animation frame, and generating an animation frame by rendering one or more rendered representative images in place, according to the animation state. |
| US09741137B2 |
Image-based color palette generation
Systems and methods for generating an image-based color palette based on a color image. A color palette can be a collection of representative colors each associated with a weight or other metadata. A color palette may be generated based on palette generation criteria, which may facilitate or control a palette generation process. Illustratively, the palette generation process may include image pre-processing, color distribution generation, representative color identification, palette candidate generation and palette determination. Representative colors with associated weight can be identified from a distribution of colors depicted by the color image, multiple palette candidates corresponding to the same color image can be generated based on various palette generation criteria, and a color palette can be identified therefrom. |
| US09741133B2 |
Identifying shapes in an image by comparing Bézier curves
The present disclosure is directed to identifying shapes in an image. For example, a shape identification system may identify an unknown shape represented by a Bézier path that has at least one Bézier curve. The shape identification system may also identify a stored Bézier path that has at least one stored Bézier curve, for example, in a database of known shapes. Using the Bézier curve of the unknown shape and the stored Bézier curve of the known shape, the shape identification system can determine a transformation matrix that transforms the transforms the Bézier curve of unknown shape to the stored Bézier curve of the known shape. Then, the shape identification system can compare the transformed Bézier curve to the stored Bézier curve to determine whether the unknown shape matches the known shape. |
| US09741131B2 |
Anatomy aware articulated registration for image segmentation
Disclosed herein is a framework for facilitating image processing. In accordance with one aspect, the framework receives first image data acquired by a first modality and one or more articulated models. The one or more articulated models may include at least one section image acquired by the first modality and aligned with a local image acquired by a second modality. The framework may align an anatomical region of the first image data with the section image and non-rigidly register a first region of interest extracted from the section image with a second region of interest extracted from the aligned anatomical region. To generate a segmentation mask of the anatomical region, the registered first region of interest may be inversely mapped to a subject space of the first image data. |
| US09741128B2 |
Method and system for characterizing plan phenotype
The present disclosure provides a computer-implemented method of, and system for, characterizing the phenotype of a plant. The method includes: (i) obtaining mesh data representing a surface of the plant, said mesh data including data representing a plurality of polygons having respective sets of vertices, each vertex having a spatial coordinate; and (ii) applying at least two segmentations of progressively finer resolution to the mesh data to assign the vertices to distinct morphological regions of the plant. |
| US09741125B2 |
Method and system of background-foreground segmentation for image processing
Techniques for a system, article, and method of background-foreground segmentation for image processing may include obtaining pixel data including both non-depth data and depth data for at least one image, where the non-depth data includes color data or luminance data or both and associated with the pixels; determining whether a portion of the image is part of a background or foreground of the image based on the depth data and without using the non-depth data; and determining whether a border area between the background and foreground formed by using the depth data are part of the background or foreground depending on the non-depth data without using the depth data. |
| US09741120B2 |
Infrared imaging detection and positioning method for underground building in planar land surface environment
An infrared imaging detection and positioning method for an underground building in a planar land surface environment comprises: obtaining an original infrared image g0 formed after stratum modulation is performed on an underground building, and determining a local infrared image g of a general position of the underground building in the original infrared image g0; setting an iteration termination condition, and setting an initial value h0 of a Gaussian thermal diffusion function; using the local infrared image g as an initial target image f0, and performing iteration solution of a thermal expansion function hn and a target image fn by using a maximum likelihood estimation algorithm according to the initial value h0 of the Gaussian thermal diffusion function; and determining whether the iteration termination condition is met, if the iteration termination condition is met, using the target image fn obtained by means of iteration solution this time as a final target image f; and if the iteration termination condition is not met, continuing to perform iteration calculation. In the method, by performing demodulation processing on the infrared image formed after stratum modulation is performed on the underground building, the display of the infrared image of the original underground building is clearer, and the real structure of the underground building can be inverted. |
| US09741119B2 |
Display apparatus and control method thereof
A display apparatus including a camera configured to capture a user's figure, a storage configured to store information about stress areas on a body in accordance with corresponding postures of a user, a processor configured to determine a user's posture from an image captured by the camera, determine a position of one or more stress areas on a body corresponding to the determined posture based on the stored information about the one or more stress areas on the body, and process a stress-related image, in which the determined one or more stress areas are marked on an image corresponding to a user's figure, and a display configured to display the stress-related image. |
| US09741107B2 |
Full reference image quality assessment based on convolutional neural network
Embodiments generally relate to providing systems and methods for assessing image quality of a distorted image relative to a reference image. In one embodiment, the system comprises a convolutional neural network that accepts as an input the distorted image and the reference image, and provides as an output a metric of image quality. In another embodiment, the method comprises inputting the distorted image and the reference image to a convolutional neural network configured to process the distorted image and the reference image and provide as an output a metric of image quality. |
| US09741103B2 |
Method and system for processing image content for enabling high dynamic range (UHD) output thereof and computer-readable program product comprising UHD content created using same
Implementations disclosed herein (e.g., systems, methods, and computer-readable program products) provide a high definition range “UHD” compatible version of classic image content (e.g., as-released motion pictures) that was created in an era of limited dynamic range and that maintains aesthetic characterization defined by “Director's Intent” of the classic image content. Such implementations advantageously use clues to the Director's Intent found in the classic image content to make intelligent estimations as to what a Director (or other image content editing professional) was attempting to achieve in the classic image content relative to a corresponding original image content (e.g., as-shot image content). The original image content holds original imagery details that have been altered or omitted during creation of corresponding classic image content. The classic image content exhibits attributes that reflect the Director's Intent such as, for example color, contrast, vignetting, saturation, and the like. |
| US09741101B2 |
Electronic device including sub-array based deblurring of a blurred finger image and related methods
An electronic device may include a finger biometric sensor that includes an array of electric field sensing pixels and image data output circuitry coupled thereto and capable of processing the image data from each of sub-arrays of the array of electric field sensing pixels. The electronic device may also include a dielectric layer over the array of electric field sensing pixels and causing electric field diffusion so that the image data output circuitry generates image data corresponding to a blurred finger image. The electronic device also includes deblurring circuitry coupled to the image data output circuitry and capable of processing the image data from each of the plurality of sub-arrays of the array of electric field sensing pixels to produce processed image data representative of a deblurred finger image. |
| US09741092B2 |
Method and system for image resizing based on interpolation enhanced seam operations
Methods and systems for resizing an image utilizing content-aware seam operations include defining low-energy seams defining contextually less-important information and utilizing such information for interpolation based on one-dimensional manifolds. The interpolation can form new seams and/or regenerated pixels that can be combined with the image to provide a content-aware resized image exhibiting smooth and continuous features. |
| US09741090B2 |
Graphics display processing device, graphics display processing method, and vehicle equipped with graphics display processing device
A graphics display processing device including: a graphics processor that executes GPU instructions based on a primary drawing instruction and a secondary drawing instruction; an acquirer) that acquires the primary drawing instruction and the secondary drawing instruction; an estimator that calculates an estimated GPU processing time required for executing the GPU instructions; a determiner that determines, using the estimated GPU processing time, which of the primary drawing instruction and the secondary drawing instruction is to be executed first; an issuance controller that performs a control when the primary drawing instruction is to be executed first, causing the primary drawing instruction to be issued and issuance of the secondary drawing instruction to be postponed; an instruction issuer that issues each drawing instruction according to the control of the issuance controller; and a graphics driver that generates the GPU instructions by executing each drawing instruction issued. |
| US09741087B2 |
Parallel image processing method and system
A hybrid processing-based image processing system performs image chain flattening, token queue creation and pipeline prior to image rendering in order to allow various portions of the image processing to be performed in parallel. Tokens are passed between the filters of the pipeline generated from the flattened image chain to allow order-preserving operations to be performed which result in the same image as would have been produced by the original image chain using sequential processing. |
| US09741086B2 |
Image processing apparatus, image processing method, and storage medium storing program
The present invention provides an image processing method that allows filter processing to be easily and appropriately performed on divided images. An image processing unit 105 performs the filter processing on pixels in a divided image 1, and pixels that do not require reference to pixels in a divided image 3 that are not stored in a pixel storage unit 103, among margin pixels 3T stored in the pixel storage unit 103. Further, an image processing unit 106, which performs the filter processing in parallel with the image processing unit 105, performs the filter processing on pixels that do not require reference to the pixels in the divided image 1, among pixels in the divided image 3. |
| US09741085B2 |
System and method of encoding content and an image
A method of encoding content data into a digital image includes determining bit values of a pixel within the digital image, and modifying the bit values within the pixel based on content data to be encoded in order to encode the content data into the digital image. The step of determining the bit values of a pixel within the digital image includes determining a binary representation of the bit values of the pixel. The step of modifying the bit values includes determining a binary representation of the content data to be encoded within the pixel and encoding the content data using a reversible binary operation. |
| US09741082B2 |
Distributed HVAC system cost optimization
Various embodiments herein include at least one of systems, devices, methods, and methods for distributed HVAC system cost optimization. Such embodiments are generally implemented within a controller of HVAC system component, such as within boiler, cooler, air handling unit, and rooftop unit controllers. In some embodiments, multiple controllers exchange data to control various components of an HVAC system. One of the controllers, such as a primary plant of the system for heating or cooling, is designated as a master controller and the other component controllers are designated as slave controllers. Each controller, both master and slave controllers, includes at least one model that models variable settings of the component or components for which the respective controller is responsible. The model is utilized by the respective controller to both adjust the modeled variable component settings and to determine a cost-variable of operation. |
| US09741081B2 |
Perturbing a subject's contextualization of a proposition about an item considered in a quantum representation by altering the item
The present invention concerns methods and apparatus for detecting perturbations to previously established and known contextualizations practiced or exhibited by subjects when confronted by certain propositions about original items. The subjects are understood to be any sentient beings, e.g., human beings that use the known contextualizations modulo the propositions and also exhibit known measurable indications in response to these propositions. Measurable indications can take on the form of responses, actions, behaviors or any measurable aspects that can be collected from the subjects in response to the propositions. The perturbation to the contextualization that is adopted by the subjects is due to altering the original item to generate an altered item and placing the altered item at the center of the proposition that was previously apprehended by the subjects to be about the original item. |
| US09741076B2 |
System and method for displaying trade information for electronic trading exchange
An application is disclosed that receives from a host exchange a plurality of trade notifications, each trade notification corresponding to an executed trade, and for each executed trade of interest, may determine whether the executed trade belongs in an aggregated set with one or more other executed trades. The application provides an indicator for indicating whether the corresponding executed trade or aggregated trade traded on the bid side or on the offer side of the market, and which indicates whether additional volume is available at the associated trade price. |
| US09741074B2 |
Dynamic handling for resource sharing requests
A system or method is provided to allow users to share or donate a portion of their credit line to others. In particular, the system may provide an interface between credit line donors and recipients and allow a user's friends or family to donate portions of their credit lines to the user. With the system serving as an intermediary between the borrowers and the lenders, the credit line donation arrangement may be hidden from the lenders. The system may manage the distribution of the credit line from the five donor friends to the beneficiary friend. Further, the system may manage the payoff or pay back of the credit lines from the beneficiary friend back to the lenders. In particular, based on the donation arrangement, the system may receive the payoff amount from the beneficiary user and distribute the payoff back to the lenders. |
| US09741072B2 |
Systems and methods for providing a customizable virtual gift card template
According to one aspect, embodiments of the invention provide a method for administering a virtual gift card, the method comprising acts of receiving a request from a server of a retailer, providing, in response to the request, an interface to a terminal operated by a purchaser, the interface comprising fields for receiving a value and a recipient for the virtual gift card, receiving from the terminal, in response to input from the purchaser, the value and the recipient for the virtual gift card, generating a code for the virtual gift card, and sending a message to the recipient of the virtual gift card, the message including the code for the virtual gift card. |