| Document | Document Title |
|---|---|
| US09722875B2 |
Master device, slave device, and methods thereof
A master device, a slave device, and methods are disclosed. The method is performed by a first slave device connected to a master-slave tree network, comprising: determining whether a beacon has not been received within a predetermined time period; and distributing a first beacon to a second slave device if no beacon has been received within the predetermined time period; wherein for the first slave device to remain in the master-slave-network, a beacon be received by the first slave device within the predetermined time period. |
| US09722873B2 |
Zero-downtime, reversible, client-driven service migration
A computer system may provide zero-downtime, reversible, client-driven service migration to migrate a client from a current service to a new service. The computer system may configure the client to operate in a dual-write, old-read mode in which the client issues write requests to both the current service and the new service and issues read requests only to the current service. The computer system may configure the client to operate in a dual-write, new-read mode in which the client issues write requests to both the current service and the new service and issues read requests only to the new service. |
| US09722868B2 |
System and method for extending cloud services into the customer premise
A cloud extension agent can be provided on a customer premise for interfacing, via an outbound secure connection, cloud based services. The cloud extension agent can reach the cloud based services through existing firewall infrastructure, thereby providing simple, secure deployment. Furthermore, the secure connection can enable substantially real-time communication with a cloud service to provide web-based, substantially real time control or management of resources on the customer premises via the cloud extension agent. |
| US09722867B2 |
Resource management method, resource management system and resource manager
A resource management method, a resource management system and a resource manager are disclosed, and the method includes: acquiring a resource allocation request, where the resource allocation request carries a resource requirement list and an access domain name of an application requesting allocation of resources; searching for a resource index locally according to the resource requirement list, and acquiring addresses of at least two available resources, where the at least two available resources are located at different platform as a service layer devices, respectively, and the two available resources both satisfy the resource requirement of the resource requirement list; establishing a correspondence between an address of each available resource and the access domain name; and configuring at least two access routes according to the correspondence, where an access route is used for routing an access request accessing the access domain name to the available resource. |
| US09722866B1 |
Resource allocation to reduce correlated failures
Implementation resources are operated in a manner furthering a particular purpose while excluding use of the implementation resources for other purposes. At least some of the implementation resources have capacity that is usable to implement multiple other resources. The capacity of the implementation resources is allocated in a manner that satisfies one or more conditions on the capacity of the implementation resources that is used. Generally, the capacity is allocated in a manner that reduces the likelihood that resources initiated close in time will fail together should underlying implementation resources fail. The implementation resources may be hardware devices that implement virtual computer systems. |
| US09722864B2 |
Systems, methods, and apparatus to configure embedded devices
Systems, methods, and apparatus to configure embedded devices are described. An example apparatus includes a network interface to communicatively couple the apparatus with a network, an antenna to receive a radio frequency signal including 1) configuration data and 2) power, a memory coupled to the antenna to receive the power and to store the configuration data, a network configurer to retrieve the configuration data from the memory and to configure the network interface based on the retrieved data, and a power source other than the antenna to provide power to the memory and the network configurer during operation of the network configurer. |
| US09722861B2 |
Fault-resilient broadcast, multicast, and unicast services
In general, various capabilities related to fault-resilient services within communication networks are presented. The services may include broadcast services, multicast services, unicast services, or the like, as well as various combinations thereof. A capability for providing local protection to unicast traffic at a node associated with a pair of redundant trees is presented herein. A capability for providing local protection to multicast traffic at a node associated with a pair of redundant trees is presented herein. A capability for constructing a pair of redundant trees is presented herein. A capability for constructing a pair of redundant trees includes partitioning a graph into a pair of partitions based on a link coloring mechanism and constructing the pair of redundant trees based on the pair of partitions. |
| US09722858B2 |
Management infrastructure analysis for cloud migration
In a source computing system having a source management infrastructure, at least one source infrastructure management component is discovered. A description of a target cloud infrastructure having a target management infrastructure is obtained. The description includes at least one mandatory target infrastructure management component. The at least one source infrastructure management component is analyzed to determine whether at least one conflict exists with the at least one mandatory target infrastructure management component. |
| US09722856B2 |
System and method to orchestrate and control sequence of recovery actions for resumption of business services by dynamically changing recovery action sequence based on feedback received from agent/open flow based devices catering to both traditional and software defined networks
Disclosed is a system and method for enabling a SNMP based Network Management System in cooperation with at least one SDN Controller to control sequence of recovery actions and dynamically change the recovery action sequence for a given fault based on the feedback received from an SNMP Agent/Open flow based devices across various systems/platforms for recovering a business service which is achieved by way of Open flow stack enhancements and OF-CONFIG enhancements at the controller end and device end. The present invention is essentially about extending the ability to initiate and perform dynamic recovery actions in a network supporting both the traditional SNMP based management systems & Open flow based SDN Control. |
| US09722851B1 |
Optimized retrieval of network resources
Features are described with regard to the analysis of network and content characteristics that may affect the retrieval of network content, and the determination by a network computing device, based at least partly on that analysis, of whether a client computing device should bypass the network computing device and retrieve requested and related content directly from content sources. Additional features are described with regard to the determination of network resources to be cached, and to the determination of a computing device from which to initiate the caching. The network computing component or the client computing device can also monitor characteristics of the network connection between the computing devices and with other computing devices associated with content providers. |
| US09722849B2 |
Method and apparatus to track gain variation in orthogonal frequency division multiplexing (OFDM) systems
Gain variations during a packet can lead to significant performance degradation in communications systems that use high order quadrature amplitude modulation (QAM). A method and the associated apparatus track such variations in an OFDM system and completely eliminate any performance degradation. Gain estimation and compensation is employed with the use of pilot subcarriers in the payload of an OFDM data packet. Estimated pilot magnitude ratios are averaged, throughout the processing life of a packet, to yield accurate gain estimations. A gain compensation factor is used to adjust data carriers. An exclusion method is also employed to eliminate pilot carriers which contribute to noise. |
| US09722848B2 |
Techniques for using a modulation and coding scheme for downlink transmissions
Examples include techniques for using a modulation and coding scheme (MCS) for downlink transmissions. In some examples information elements (IEs) for either a physical multicast channel (PMCH) or a physical multicast control channel (PMCCH) include information to indicate an MCS for downlink transmission over a PMCH or PMCCH between an evolved Node B (eNB) and user equipment (UE). For these examples, the information in the IEs include indications of whether higher order modulation for quadrature amplitude modulation (QAM) have or have not been enabled. Both the UE and the eNB may operate in compliance with one or more 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) standards. |
| US09722847B2 |
Transmitter, receiver, transmission method, and reception method
A preamble generating unit generates first and second synchronization preambles having different numbers of subcarriers. A transmission signal generating unit generates an OFDM transmission signal through time-division multiplexing by using the generated first and second synchronization preambles. A transmission RF unit converts the generated OFDM transmission signal into a radio-frequency OFDM signal and transmits the radio-frequency OFDM signal. The preamble generating unit adds a predetermined dummy period between the first synchronization preamble and the second synchronization preamble. |
| US09722846B2 |
Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method
Disclosed herein is a method of receiving a broadcast signal. The method comprises receiving the broadcast signal; an Orthogonal Frequency Division Multiplexing (OFDM) demodulating on the received broadcast signal; parsing at least one signal frame from the demodulated broadcast signal to extract service data or service component data; converting the service data or service component data into bits; decoding the converted bits; and outputting a data stream comprising the decoded bits. |
| US09722845B2 |
Bluetooth low energy frequency offset and modulation index estimation
A Bluetooth Low Energy (BLE) device, having a demodulator configured to translate in-phase and quadrature components of a received BLE signal into a differential phase signal; an estimator configured to estimate a frequency offset of the differential phase signal; and a detector configured to detect information in the differential phase signal corrected by the estimated frequency offset. |
| US09722842B2 |
Transmission of data using a plurality of radio frequency channels
Methods and systems are described for transmitting data to a node using a plurality of radio frequency channels. The data may be allocated, based on feedback from the node, into various portions amongst multiple radio frequency channels and/or amongst tones associated with the radio frequency channels. The data portions may be transmitted to the node, using frequency diversity, via respective radio frequency channels as at least part of respective orthogonal frequency division multiplexing (OFDM) transmissions, which may be at least partially concurrent transmissions. |
| US09722841B1 |
Channel-based coding for wireless communications
Disclosed are techniques for channel-based coding for wireless communications. A transmitter includes circuitry and multiple antennas. The circuitry selects a subset of the antennas, determines a respective channel response for each of the antennas in the subset, generates a respective coded system for each of the antennas in the subset, and transmits the coded symbols using the antennas in the subset. |
| US09722840B2 |
Apparatus and method for sending and receiving broadcast signals
Disclosed herein is a broadcast signal receiver. A broadcast signal receiver according to an embodiment of the present invention includes a synchronization/demodulation module configured to perform signal detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to perform FEC decoding on the data, and an output processing module configured to receive the data of the at least one PLP and to output a data stream. |
| US09722838B2 |
Apparatus and method for sending and receiving broadcast signals
An apparatus for transmitting a broadcast signal includes an input formatting module configured to de-multiplex an input stream into at least one Data Pipe (DP); a BICM module configured to perform error correction processing on data of the at least one DP; a signal frame building module configured to map the data of the DP to symbols within a signal frame; and an OFDM generation module configured to generate a transmission broadcast signal by inserting a preamble into the signal frame and performing OFDM modulation. The OFDM generation module includes a pilot signal insertion module configured to insert a pilot signal including Continual Pilots (CP) and Scattered Pilots (SP) into the transmission broadcast signal, and the CPs are inserted into every symbol of the signal frame, and location and number of the CPs are determined based on a Fast Fourier Transform (FFT) size. |
| US09722836B2 |
Data processing apparatus and method
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. |
| US09722832B1 |
Frequency control circuit, frequency control method and phase locked loop circuit
A frequency control circuit, adapted to be utilized in a phase locked loop circuit. The frequency control circuit includes a first frequency control block, a second frequency control block, a pump control unit and a charge pump unit. The first frequency control block generates a first control signal according to a frequency of an output signal from the phase locked loop circuit, in which the first control signal is configured to control the frequency of the output signal located within a predetermined frequency region. The second frequency control block generates a second control signal according to a frequency of an input signal and the frequency of the output signal, in which the second control signal is configured to control the frequency of the output signal located at a target frequency. |
| US09722830B1 |
Detection of low level communication signals in high level noise
The disclosure is directed to a signal detection system. The system includes a receiver configured to receive data comprising noise and a signal having an amplitude lower than that of the noise received by the receiver. The system also includes a detection module configured to receive the data received by the receiver, define a region of interest of the data, compare a plurality of portions of the region of interest, and identify a portion of the region of interest that is more likely to contain the signal. |
| US09722829B2 |
Pulse shaping circuit for improving spectrum efficiency and on-off keying (OOK) transmitter including pulse shaping circuit
A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter. |
| US09722828B2 |
Switch capacitor decision feedback equalizer with internal charge summation
In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal. |
| US09722824B2 |
Embedded clock in communication system
A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion. |
| US09722821B2 |
Channel state information transmission method, apparatus and system
A precoding method, a precoding apparatus, a Frequency Domain Equalization (FDE) method, and an FDE apparatus are provided in the embodiments of the present invention. The precoding method includes: performing offset modulation for a transmitting signal vector; calculating a precoding matrix according to the offset-modulated transmitting signal vector and a receiver decision signal vector, where the precoding matrix is used for performing precoding for the transmitting signal vector; and performing precoding for the transmitting signal vector according to the precoding matrix. Linear precoding is performed by using the offset-modulated signal on the transmitter, and therefore, the interference caused by multiple antennas and multipath propagation is reduced, the system BER is reduced, and the complexity of implementation is low. |
| US09722818B2 |
Decision feedback equalizer summation circuit
A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. |
| US09722817B2 |
Equalization method for a parsimonious communication channel and device implementing the method
A method for equalizing a signal comprising modulated symbols comprising a block of N received symbols comprises: demultiplexing the N received symbols by factor L to generate a predetermined number L of sub-blocks of symbols, each comprising a version of the N received symbols sub-sampled by factor L, the independent equalization of each sub-block using an identical equalization algorithm, multiplexing the equalized symbols of each sub-block to obtain a block of N equalized symbols, removing instances of interference linked to paths other than two paths of higher power comprising generating an interference term resulting from the influence, on the equalized symbols, of all paths of the channel having the impulse response of the transmission channel except two paths of higher power, subtracting the interference term from the symbols of the block of N received symbols, and, a second equalization step equal to a second iteration of the first equalization step. |
| US09722808B2 |
Data transmission system, a terminal device, and a recording medium
A data transmission system including a plurality of terminal devices arranged in a communication network and configured to transmit or receive content data. At least one terminal devices configured to receive content data transmitted from another terminal device, among the plurality of terminal devices, includes a reception priority management unit configured to manage priority of two or more content data addressed to the own terminal device, and a data reception control unit configured to, based on an output time interval of output signals corresponding to priority data whose priority managed by the reception priority management unit is high among two or more content data being received, request a transmission source configured to transmit content data having priority lower than the priority data, to perform control to stop transmitting the content data. |
| US09722807B2 |
Systems and methods for webpage creation and updating
A computer network system for posting content at a web site includes computer servers configured to host a web site for a group of users, and a data storage configured to store an email address in association with a destination at the website. The computer servers can receive an electronic message at the email address by the computer servers from a user. A computer processor can automatically extract content from the electronic message. The computer servers can automatically post the content extracted from the electronic message at the destination at the website. |
| US09722804B2 |
Cryptographic security functions based on anticipated changes in dynamic minutiae
Dynamic key cryptography validates mobile device users to cloud services by uniquely identifying the user's electronic device using a very wide range of hardware, firmware, and software minutiae, user secrets, and user biometric values found in or collected by the device. Processes for uniquely identifying and validating the device include: selecting a subset of minutia from a plurality of minutia types; computing a challenge from which the user device can form a response based on the selected combination of minutia; computing a set of pre-processed responses that covers a range of all actual responses possible to be received from the device if the combination of the particular device with the device's collected actual values of minutia is valid; receiving an actual response to the challenge from the device; determining whether the actual response matches any of the pre-processed responses; and providing validation, enabling authentication, data protection, and digital signatures. |
| US09722803B1 |
Systems and methods for device authentication
Embodiments include methods, and systems and computing devices configured to implement the methods of authenticating a computing device. A processor of a first computing device may obtain a transitory identity and may send the transitory identity to a second computing device and a third computing device. A processor of the second computing device may send the transitory identity to the third computing device with a request to authenticate the first computing device. The processor of the third computing device may authenticate the identity of the first computing device in response to determining that the transitory identity received from the first computing device matches the transitory identity received from the second computing device. |
| US09722801B2 |
Detecting and preventing man-in-the-middle attacks on an encrypted connection
A client device may provide, to a host device, a request to access a website associated with a host domain. The client device may receive, based on the request, verification code that identifies a verification domain and a resource, associated with the verification domain, to be requested to verify a public key certificate. The verification domain may be different from the host domain. The client device may execute the verification code, and may request the resource from the verification domain based on executing the verification code. The client device may determine whether the requested resource was received, and may selectively perform a first action or a second action based on determining whether the requested resource was received. The first action may indicate that the public key certificate is not valid, and the second action may indicate that the public key certificate is valid. |
| US09722799B2 |
Distributed system for multi-function secure verifiable signer authentication
A distributed multi-function secure system for verifiable signer authentication having a personal private key stored in a secure storage of a mobile device where the mobile device connects to a fragmented distributed signing engine by a secure protocol and is issued a signer certificate from a circle of trust certificate server to securely electronically sign documents. |
| US09722797B2 |
Computer-based optimization of digital signature generation for records based on eventual selection criteria for products and services
A method for generating a digital signature includes grouping, with a processing device, a first record with a second record, and generating a first digital signature based at least in part on the first record and the second record. |
| US09722793B2 |
Personal identification via acoustically stimulated biospeckles
An optical sensing device can receive a speckle pattern generated by a laser's interaction with acoustically stimulated tissue. A computing device can identify one or more characteristics within the received speckle pattern. The computing device can then identify a match of the one or more characteristics to a user biometric signature stored within a storage device. Based upon the identified match, the system can authenticate a user within a computer system. |
| US09722791B2 |
Three-tiered security and computational architecture
A computing system, method, and computer program product provide cryptographic isolation between a client device and a server computer for providing a network service to the client device. The computing system stores encrypted user authentication data of the client device and its user, and encrypted service authorization data of the server computer in such a way that neither the client device nor the server computer can obtain information about the other. Upon subsequent receipt in the computing system of purported user authentication data and a request to access the network service, the computing system encrypts the purported authentication data and compares it against the stored, encrypted data. Only when these encrypted data match is the computing system able to decrypt the service authorization data and provide it to the server computer to gain access to the network service. |
| US09722788B1 |
Rekeying encrypted virtual machines in a cloud
A method, system, and computer program product comprising intercepting communication between a virtual machine and encrypted replication data stored on a storage medium and redirecting the communication to a remote replication appliance; and using a key stored on the remote replication appliance to enable the virtual machine to facilitate communication with the encrypted replication data stored on the storage medium; wherein facilitating communication enables the virtual machine to interact with the encrypted replication data as unencrypted data. |
| US09722786B2 |
Apparatus and method for processing authentication information
Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key. |
| US09722781B2 |
Vehicle software update verification
A mobile device may be associated with a vehicle for verification of software updates. The mobile device may be configured to receive a message including an encryption key with which a software update for the vehicle is encrypted, provide a user interface requesting user verification of installation of the software update, and responsive to receipt of the user verification, provide the encryption key to the vehicle to allow the vehicle to decrypt the software update. An update server may be configured to send a software update encrypted using an encryption key to a vehicle, receive a request from the vehicle requesting that the encryption key used to encrypt the software update be provided to a mobile device associated with the vehicle for verification of software updates, and send the encryption key to the mobile device responsive to the request. |
| US09722779B1 |
Computer programs, secret management methods and systems
There is provided a computer program which, when executed by a processor of an information processing device, causes the processor to function as a secret splitting module and a control module. The secret splitting module is configured to recover secret data from at least two pieces of split data using secret splitting and the control module is configured to control reading out or writing each piece of the split data. Secret data is maintained within a virtual drive. The control module is further configured to read out first split meta-data from a first storage device, read out second split meta-data from a second storage device, cause the secret splitting module to recover virtual drive meta-data at least from the first and second split meta-data, and generate the virtual drive based on the recovered virtual drive meta-data. Corresponding method and system are also provided. |
| US09722777B2 |
Homomorphic database operations apparatuses, methods and systems
The HOMOMORPHIC DATABASE OPERATIONS APPARATUSES, METHODS AND SYSTEMS (“HEDO”) transform transaction storage requests and homomorphic model queries using HEDO components into homomorphic model query results. In some implementations, the disclosure provides a processor-implemented method of securely querying a shared homomorphically encrypted data repository and performing cross-table homomorphic joins. |
| US09722774B2 |
Non-leaky helper data: extracting unique cryptographic key from noisy F-PUF fingerprint
A method generating a cryptographic key and corresponding helper data includes measuring an analog value associated with a physical property of cells of a memory array; digitizing the measured analog value to generate the cryptographic key; quantizing the measured analog value to generate the corresponding non-leaky helper data. |
| US09722773B2 |
Method of determining a representation of a product of a first element and a second element of a finite set, method of evaluating a function applied to an element of a finite set and associated devices
A method for determining a representation of a product of a first element and a second element is disclosed comprising, picking a random value for each pair of a first integer between 1 and d and a second integer greater than the first integer, adding the random value to the product of a first value and a second value, and adding the result of the first addition and the product of the first value and the second value. Then summing, for each integer between 1 and d, a product of the first and second values associated with the integer, the random values associated with the pairs of which the first integer is the integer concerned, and the values obtained for the pairs of which the second integer is the integer concerned. |
| US09722769B2 |
Equalizer
An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit. |
| US09722763B2 |
Highly utilized communication channel with order and retransmissions
A communication link comprising: a first transceiver configured to transmit a first set of packets at a predetermined rate with a first error resistance level, store the transmitted data in a buffer, receive a retransmission request, and retransmit the relevant data using one or more packets encoded with a second error resistance level that is higher than the first error resistance level. And a second transceiver configured to receive the first set of packets, detect an erroneous packet, request retransmission of the erroneous packet, and forward the data received in the packets according to its original order approximately after a fixed delay. |
| US09722761B2 |
Secondary cells in overlapping bands
Systems and methods relating to configuring a Secondary Component Carrier (SCC) for a wireless device in a cellular communications network are disclosed. In some embodiments, the method comprises obtaining capabilities of the wireless device, where the capabilities indicate a frequency band combination supported by the wireless device. The frequency band combination supported by the wireless device includes a first frequency band supported by a base station and the wireless device used for a Primary Cell (PCell) of the wireless device and a second frequency band supported by the wireless device but not supported by the base station. The method further comprises identifying an overlap between the second frequency band supported by the wireless device but not supported by the base station and a third frequency band supported by the base station but not supported by the wireless device and configuring the SCC for the wireless device in the overlap. |
| US09722753B2 |
Method and apparatus for transmitting/receiving response signal in wireless communication system
A method and an apparatus for transmitting and receiving a response signal in a wireless communication system are provided. In a method for transmitting a response signal in a broadcasting system, Acknowledgement (ACK) information for uplink packet data for each user is generated. A symbol and a subcarrier which will transmit the ACK information for each user inside a transmission frame are determined. ACK transmission related information is transmitted via a control channel inside the transmission frame. The ACK information for each user is transmitted via the determined symbol and subcarrier inside the transmission frame. |
| US09722752B2 |
Method and apparatus for transmitting sounding reference signal
A method is provided for receiving a sounding reference signal (SRS) in a wireless communication system. A base station transmits downlink control information to a user equipment at a first serving cell of the plurality of serving cells. The downlink control information includes a carrier indicator and a downlink assignment. When the downlink control information includes an aperiodic SRS request that indicates a triggering of an SRS transmission, the base station receives an SRS from the user equipment at the second serving cell. If the first serving cell is a frequency division duplex (FDD) and the second serving cell is a time division duplex (TDD) cell, the downlink control information includes the aperiodic SRS request. If the first serving cell is the TDD cell and the second serving cell is the FDD cell, the downlink control information does not include the aperiodic SRS request. |
| US09722749B2 |
Method and an apparatus for providing channel quality information in a wireless communication system
A method for transmitting channel quality information for a downlink channel; a user equipment (UE) therefore; a method for receiving channel quality information for a downlink channel; and a base station therefore are discussed. The method for transmitting channel quality information for a downlink channel includes according to one embodiment receiving, by a user equipment (UE), configuration information on periodic channel state information (CSI) reporting by higher layer signaling; determining, by the UE, a channel quality information index at least based on a number of a specific resource element; and transmitting the determined channel quality information index to a base station. The number of the specific resource element is determined based on a UE-specific reference signal overhead. A resource element allocated for a Channel Status Information-Reference Signal (CSI-RS) is regarded as the specific resource element regardless of transmitting the CSI-RS. |
| US09722744B2 |
Determining signal transmission bandwidth
Example embodiments presented herein are directed towards a first radio node (400), and corresponding methods therein, for determining a bandwidth of a second radio node (402). The first and second radio nodes are configured for use in a communications network. The bandwidth is determined based on a correlation between a signal received form the second radio node and at least one known signal which are transmittable on one or more known radio resources. Such bandwidth determination eliminates the need for the wireless terminal to receive such information via system information broadcasted from a cell. |
| US09722742B2 |
Method and apparatus for implementing coordinated multiple point transmission
The present invention discloses a method for implementing coordinated multiple point transmission CoMP, including: configuring, by the network side, a range setting group to a user equipment, UE, and acquiring the original mapping pattern of various cells in the group; receiving the channel information of various cells in the group returned by the UE; selecting, by the network side, cells for practically sending data to the UE currently, determining the update mapping patterns for the cells selected in the group performing CoMP, and controlling the selected various cells to send a physical downlink shared channel to the UE according to the update mapping pattern. The present invention further discloses an apparatus for implementing CoMP In accordance with the method and apparatus for implementing CoMP of the present invention, the mapping patterns of the cells for practically sending data to a UE are updated by acquiring the CRS and CSI-RS mapping locations of the original mapping pattern of cells of the range setting group to get the update mapping pattern for use in the CoMP, so that it is possible to meet the design principle of CRS and CSI-RS and guarantee the normal application of CoMP at the same time. |
| US09722741B1 |
Multiple access in wireless telecommunications system for high-mobility applications
A wireless telecommunications system that mitigates infrasymbol interference due to Doppler-shift and multipath and enables multiple access in one radio channel. Embodiments of the present invention are particularly advantageous for wireless telecommunications systems that operate in high-mobility environments, including high-speed trains and airplanes. |
| US09722735B2 |
Signaling uplink control information in LTE-A
Methods and systems for transmitting uplink control information in an LTE Advanced system are disclosed. A user device may determine whether uplink control information and/or available channels meet certain criteria and determine whether the uplink control information should be transmitted on a physical uplink control channel, a physical uplink shared channel, or both, based on the criteria. Criteria may include the size of the uplink control information (absolute size or relative to space available on a channel or a threshold value), the type of control information bits, the number of available (i.e., active or configured) component carriers, and the amount of power that may be required to transmit the uplink control information on more than one channel. |
| US09722731B2 |
Techniques for aggregating data from WWAN and WLAN
Certain aspects of the present disclosure relate to techniques for aggregating data from a wireless wide area network (WWAN) and wireless local area network (WLAN). In some aspects, a packet convergence entity (e.g., PDCP layer entity) communicates with first and second radio access technology (RAT) links. The packet convergence entity may determine from which of the first and second RAT links a data packet is received and may monitor a sequence number value of each of the received data packets. The packet convergence entity may perform one or more actions based on a determination that one or more packets are missing based on the monitored sequence number values. The packet convergence entity may send a status report in response to one or more events on one or both of the first RAT link and the second RAT link. |
| US09722727B2 |
Multi-level ACK defining decoding margin
The present disclosure relates to methods of transmitting and receiving transmission feedback in a radio network node. More particularly the disclosure pertains to transmitting and receiving messages acknowledging reception and successful decoding of a transport block in a radio network node. The disclosure also relates to a wireless device providing transmission feedback and to a radio network node receiving the transmission feedback. The disclosure proposes a method, performed in a radio network node, of receiving transmission feedback. The method comprises transmitting, using a set of transmission properties, a transport block to a receiving wireless device and receiving, from the receiving wireless device, an acknowledgement (ACK) confirming reception and successful decoding of the transport block in the receiving wireless device, wherein the ACK defines a decoding margin of the decoding. The disclosure also proposes a corresponding method in a wireless device and corresponding devices as well as a corresponding computer program. |
| US09722723B2 |
Dynamic hitless ODUflex resizing in optical transport networks
The present invention and its embodiments are made to provide for dynamic hitless resizing in optical transport network without any identification of matching time slots by the Network Management System (NMS) or any control plane signaling including Generalised Multi Protocol Label Switching (GMPLS). An aspect of the invention provides for a method of hitless ODUflex connection resizing in an optical transport network by incrementing or decrementing the ODUflex connection between the nodes, based on an indication command given to a source node for bandwidth increase or decrease, by identifying and matching at least one time slot through Link Connection Resizing (LCR) protocol message exchanges. Another aspect of the invention provides for a method of hitless ODUflex connection resizing in an optical transport network by decrementing the matching time slot used for the incrementing operation, in case of unsuccessful incrementing operation between nodes. |
| US09722721B2 |
Method and device for transparent connection of different DWDM systems by NxN AWGs
A system for connecting two or more dense wavelength division multiplex (DWDM) systems in an optically transparent manner includes a first DWDM system with a first optical line amplifier (OLA) for amplifying the signal to be transmitted and a second DWDM system which has a second OLA for amplifying the signal to be transmitted. The first OLA and the second OLA are connected to each other via a passive N×N AWG, arrayed waveguide grating. |
| US09722720B2 |
Scaling wireless full duplex in multi-cell networks with spatial interference alignment
A method, system, and computer program product for minimizing intra-cell and inter-cell interference in a multi-cell full duplex communication system in a wireless network. The method includes selecting, by a client selector, a plurality of clients, wherein the plurality of clients includes a plurality of uplink clients configured to transmit signals and a plurality of downlink clients configured to receive signals over a plurality of data streams in each cell of the multi-cell full duplex communication system, and performing, by a spatial interference aligner, spatial interference alignment on interfering data streams to align the interfering data streams of uplink clients towards downlink clients in its own cell and downlink clients in a neighboring cell. |
| US09722718B2 |
System for establishing and maintaining a clock reference indicating one-way latency in a data network
A method for indicating one-way latency in a data network, with continuous clock synchronization, between first and second node having clocks that are not synchronized with each other includes a continuous synchronization session and a measurement session. The method repetitively sends predetermined synchronization messages from the first node to the second node and from the second node to the first node, calculates a round trip time for each message at the first node, updates a synchronization point if the calculated round trip time is smaller than a previously calculated round trip time, stores the updated synchronization points of a synchronization window, and calculates a virtual clock from the updated synchronization points of the synchronization window. The measurement session collects multiple measurements of one-way latency between the first and second nodes using the virtual clock, and generates a latency profile by interpolating the multiple measurements. |
| US09722717B2 |
Technologies for ethernet link robustness for deep sleep low power applications
Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed. |
| US09722716B2 |
Rotary control device
A touch-sensitive rotary control device with an illumination function includes a rotary encoder having a conductive outer casing and a rotatable shaft extending from it, the shaft operating as a light guide for a light source located in the rotary encoder, a conductive sleeve mechanically coupled to and surrounding the side of shaft, and electrically coupled to the conductive outer casing of the rotary encoder, so that touch-sensitivity is provided and light is allowed to exit the shaft and such that the device can be provided as a kit of parts or form part of a mixing console. |
| US09722712B2 |
Interference management for a distributed spatial network
A communication network comprising of at least one remote base station; and a plurality of antenna ports connected to the at least one remote base station; wherein the remote base station controls the plurality of antenna ports. The remote base station is configured for defining mutually exclusive entry and exit points for the antenna ports in at least one of time; or frequency. Also, disclosed herein is a communication network comprising of at least one network controller and at least one base station, wherein the network controller is configured for assigning entry and exit points for each base station. |
| US09722709B2 |
Systems and methods for transmitting routable optical energy packets
A system for transmitting routable energy packets includes an optical power source and a processing circuit. The optical power source is configured to generate an optical power packet having optical energy, generate an optical data packet comprising routing information configured to control a route of the optical power packet, and transmit the optical power packet and the optical data packet via a conduit. The processing circuit is configured to generate the routing information to be transmitted within the optical data packet, and control a transmission by the optical power source. |
| US09722707B2 |
Dual-channel orthogonal carriers assisted optical signal transmitting device, direct detection method and system
The present disclosure relates to a dual-channel orthogonal carriers assisted optical signal transmitting device, and a direct detection method and a direct detection system using the dual-channel orthogonal carriers assisted optical signal. The direct detection system using the dual-channel orthogonal carriers assisted optical signal comprises a transmitting device and a receiving device. The transmitting device is configured to generate and transmit a dual-channel orthogonal carriers assisted optical signal to be detected, wherein the dual-channel orthogonal carriers assisted optical signal is modulated with a modulation signal. The receiving device is configured to receive the dual-channel orthogonal carriers assisted optical signal, and recover amplitude and phase information of the modulation signal based on the dual-channel orthogonal carriers assisted optical signal. |
| US09722706B1 |
Multiple wavelength light-source with tracking multiplexer
A transmitter assembly incorporating multiple laser diodes that are wavelength multiplexed together using a planar lightwave circuit, and where the multiplexer's transmission spectrum depends on temperature at the same rate as the laser diodes. This allows a design for lower loss in the multiplexer and therefore is more power efficient. |
| US09722705B2 |
Method and apparatus for controlling, monitoring, and communicating with tunable optical devices and subassemblies
An apparatus for controlling, monitoring, and communicating with an optical device, photonic integrated circuit or subassembly is provided. The apparatus includes an optical device or subassembly; and afield programmable device including programmable hardware gates coupled to the optical device or subassembly. The field programmable device may be configured to implement a plurality of functions at a gate level for controlling, monitoring, and/or communicating with the optical device or subassembly, each of the plurality of functions being configured to execute as a concurrent process, without use of a microprocessor or a microcontroller. Further, a programmable optical device, such as a programmable optical transmitter, optical subassembly, or transceiver based on a tunable laser having field programmable device centric control systems with software-enabled features offer extensive real-time control and monitoring functionality based on for example actual traffic flows. |
| US09722697B2 |
Polarization division multiplexing optical communication reception device, polarization division multiplexing optical communication system, and polarization division multiplexing optical communication method
A polarization demultiplexing optical communication receiver is provided with a signal quality change imparting means which imparts a signal quality change to multiplexed two optical signals; and a signal quality monitoring means which compares signal qualities of the two optical signals with each other after the multiplexed two optical signals imparted with the signal quality change are subjected to polarization separation so as to specify the two optical signals based on a result of the comparison. This makes it possible to reduce transmission characteristics degradation of a polarization-multiplexed optical signal, and to implement transmission having high reliability. |
| US09722695B2 |
Optical network unit and optical detecting method
An optical network unit (ONU) includes an optical transceiver module, a switch, a detecting module, and an ONU chip. The switch is electronically coupled between the optical transceiver module and a power supply. The detecting module is electronically coupled between the switch and the power supply. The detecting module includes a sensor, an amplifier, and a comparator. The sensor is electronically coupled between the power supply and the switch to sense a driving current output from the power supply to the optical transceiver module and output a voltage signal to the amplifier, the amplifier amplifies the voltage signal and outputs an amplified voltage signal to the comparator, the comparator compares the amplified voltage signal with a predetermined voltage signal and outputs a comparison result. The ONU chip controls the switch to connect/disconnect the electrical connection between the optical transceiver module and the power supply according to the comparison result. |
| US09722687B2 |
Polarization-angle-division diversity wireless transmitter, wireless receiver, and wireless communication system
A wireless transmitter has a modulator modulating an information signal of a frequency f1 by a carrier wave of a frequency f2 to output a first modulated signal, a transmitting antenna transmitting the first modulated signal using a linearly polarized wave, and a motor rotating the transmitting antenna at a frequency f3 to rotate the outgoing linearly polarized wave at the frequency f3 thereby multiplexing the first modulated signal with a linearly polarized wave component and a horizontally polarized wave component, the two components being independent of each other. A wireless receiver has diversity receiving antennas receiving the signal on a plurality of polarization planes to obtain a plurality of input signals; a path difference phase shifter compensating each of the input signals for the phase shift stemming from path differences, and a composer composing the corrected received signals. |
| US09722685B2 |
Method and apparatus for transmitting and receiving feedback information in a mobile communication system
A method and user equipment for transmitting channel state information (CSI) are provided. The method includes identifying a first CSI configuration with a first channel measurement information, a first interference measurement information, and a first information for a period and an offset; identifying a second CSI configuration with a second channel measurement information, a second interference measurement information, and a second information for a period and an offset; generating a first CSI based on the first channel measurement information and the first interference measurement information; generating a second CSI based on the second channel measurement information and the second interference measurement information; transmitting the first CSI for the first CSI configuration based on the first information; and transmitting the second CSI for the second CSI configuration based on the second information. |
| US09722683B2 |
Mobile device transmitter and methods for transmitting signals in different signal dimensions for 3GPP LTE
Embodiments of a mobile device transmitter and methods for transmitting signals in different signal dimensions are generally disclosed herein. The mobile device transmitter comprises a mapper to map a block of two or more input modulation symbols to different signal dimensions comprising two or more spatial dimensions, and linear transform circuitry to perform a linear transform on the block of mapped input modulation symbols to generate a block of precoded complex-valued output symbols such that each output symbol carries some information of more than one input modulation symbol. The mobile device also comprises transmitter circuitry to generate time-domain signals from the blocks of precoded complex-valued output symbols for each of the spatial dimensions for transmission using the two or more antennas. The precoded complex-valued output symbols are mapped to different signal dimensions comprising at least different frequency dimensions prior to transmission. |
| US09722682B2 |
Diversity for MIMO systems
The invention is directed to systems, methods and computer program products for determining an operational mode for a device in a network. An exemplary method comprises determining a device has a first antenna and a second antenna; determining a first number of multipath components and associated power levels for the first antenna; determining a second number of multipath components and associated power levels for the second antenna; and determining an operational mode for the device based on the first number of multipath components and its associated power levels for the first antenna and the second number of multipath components and its associated power levels for the second antenna. |
| US09722678B2 |
Coordinated multi-point transmission method and equipment
Disclosed in the present invention are a coordinated multi-point transmission method and network equipment. In the present invention, a CoMP (Coordinated Multi-Point) auxiliary node provides CoMP auxiliary information for CoMP-participating cells via inter-cell interfaces, in order to assist the CoMP-participating cells in realizing CoMP. |
| US09722676B2 |
Communication control method, base station, and processor
A base station is connected to a first user terminal in a mobile communication system that performs spatial multiplexing transmission for the first user terminal and a second user terminal by applying a same radio resource and a same precoder matrix. The base station comprises: a control unit that notifies another base station connected to the second user terminal of a first statistic for each piece of first precoder matrix information fed back from the first user terminal and a second statistic for each downlink radio resource in the first user terminal. |
| US09722674B2 |
System and method for close proximity communication
A method for close proximity communication is disclosed. The method comprises detecting a signal transmitted by a close proximity communication (CPC) device at one of a distance of greater than or less than a CPC detection perimeter with a multi-mode magnetic induction communication (MMMIC) device with at least one antenna. The method further comprises identifying the type of device transmitting the detected signal. The method further comprises enabling the MMMIC device to communicate with the close proximity communication device at one of the distance of greater than the CPC detection perimeter and the distance of less than the CPC detection perimeter based on the type of device that is identified. |
| US09722671B2 |
Oscillator circuits for wireless power transfer
A signal generator generates an electrical signal that is sent to an amplifier, which increases the power of the signal using power from a power source. The amplified signal is fed to a sender transducer to generate ultrasonic waves that can be focused and sent to a receiver. The receiver transducer converts the ultrasonic waves back into electrical energy and stores it in an energy storage device, such as a battery, or uses the electrical energy to power a device. In this way, a device can be remotely charged or powered without having to be tethered to an electrical outlet. |
| US09722662B2 |
Semiconductor device and serial data transmission line system
A semiconductor device and a serial data transmission line system have a reception circuit and an adaptive equalizer circuit. A supply source of a power supply supplied with the reception circuit is selected based on correction intensity of the correction value calculated by the adaptive equalizer circuit. When correction intensity of the correction value calculated by the adaptive equalizer circuit is not less than a threshold value, the supply source of the power supply supplied to the reception circuit and the adaptive equalizer circuit is switched, and a noise level of the power supply is reduced. |
| US09722657B2 |
Mobile electronic device covering
A protective covering configured for use with a mobile electronics device, including a front wall and a plurality of side walls defining a primary cavity. A back wall is disposed within the primary cavity separating the primary cavity into a protective covering electronics housing cavity and a mobile electronic device housing cavity. One or more apertures are disposed within the front wall. A light source is disposed within the protective covering electronics housing cavity, wherein at least a portion of the light source is disposed outside of the protective covering electronics housing cavity and through at least one of the one or more apertures in the front wall. A heat sink is disposed within the protective covering electronics housing cavity and in contact with the light source. |
| US09722656B2 |
Mobile device videography system
A system for mobile device photography and videography comprises a camera-shaped case configured to retain a mobile device. A lens of the case may be configured to direct an image into a camera lens of the mobile device, with the lens and the camera lens of the mobile device arranged substantially perpendicularly to each other. The camera-shaped case may also comprise a viewfinder that directs any visible content displayed on a portion of the graphical user interface into an eyepiece attached to the viewfinder. Additionally, the camera-shaped case may comprise an eyepiece connected to the viewfinder, a button disposed configured to actuate a camera function of the mobile device, and a cable to be inserted into the mobile device. The system may also include a downloadable software application executable on the mobile device configured to display an image and one or more videography controls on the graphical user interface. |
| US09722652B2 |
Mobile apparatus, control method, and control program
A mobile apparatus includes a touch screen and a controller. The controller estimates that the mobile apparatus is being immersed in water when a detection result of the touch screen satisfies a predetermined condition. |
| US09722650B2 |
Method for noise power estimation
Described herein are technologies related to an implementation of noise power estimation in a receiver of a device. |
| US09722644B2 |
Frequency switching within time domain digital pre-distortion
Appropriate signal processing may be beneficial in a variety of communication systems and elements thereof. For example, time domain digital pre-distortion may benefit from suitable treatment of frequency switching. A method can include determining whether an instantaneous frequency of an input signal is positive or negative. The method can also include selecting a pre-distortion model from a set of pre-distortion models based on the determination of positive or negative instantaneous frequency. The method can further include applying the selected pre-distortion model to the input signal for a time corresponding to the determination of instantaneous frequency to provide an output signal. The method can additionally include providing the output signal to a power amplifier. |
| US09722634B2 |
Multiple component codes based generalized low-density parity-check codes for high-speed optical transport
Systems and methods for data transport, including encoding streams of input data using generalized low-density parity check (GLDPC) encoders, the one or more GLDPC encoders being configured to generate GLDPC coded data streams using a plurality of component local codes to improve error correction strength, employ single-parity checks and two or more local block codes during generation of the GLDPC codes, and enable continuous tuning of code rate using the generated GLDPC codes. Signals may be generated using mappers, the mappers configured to assign bits of signals to signal constellations and to associate the bits of the signals with signal constellation points. The signal may be modulated using an I/Q or 4-D modulator composed of one polarization beam splitter, two I/Q modulators, and one polarization beam combiner. The modulated signals are multiplexed using a mode-multiplexer, transmitted over a transmission medium, and the signals are received and decoded using GLDPC decoders. |
| US09722632B2 |
Sliding window list decoder for error correcting codes
A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison. |
| US09722628B2 |
Method in a computer system, computer program and data processing system
In a method in a computer system for recoding a coded intermediate variable into a recoded result variable a product is formed by multiplying an input constant by an input variable to be coded. The coded intermediate variable is formed as a function of the product and a multiplicative inverse is determined on the basis of the input constant. The multiplicative inverse is applied to the coded intermediate variable, so that no uncoded or partially uncoded interim result is produced and/or an error information potentially contained in the coded intermediate variable is still detectable in the interim result. |
| US09722626B2 |
Method and system using computational sigma-delta modulators
An analog-to-digital converter (ADC) is provided includes a first sigma-delta modulator (SDM) electrically coupled to a first signal input. The first SDM includes a first summing junction configured to receive a plurality of inputs to the first SDM. The ADC further includes a second sigma-delta modulator (SDM) electrically coupled to a second signal input. The second SDM includes a second summing junction configured to receive a plurality of inputs to the second SDM. The first SDM also includes a cross-coupled feedback loop from an output of the first SDM to a negative input of the first summing junction and to a positive input of the second summing junction. The second SDM also includes a cross-coupled feedback loop from an output of the second SDM to a negative input of the first summing junction and to a negative input of the second summing junction. |
| US09722618B1 |
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided. |
| US09722617B2 |
Phase locked loop and associated method for loop gain calibration
A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal. |
| US09722616B2 |
Reception circuit
A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses. |
| US09722602B2 |
Transmitter
A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver. |
| US09722597B2 |
Initialization signal generation device and nonvolatile memory apparatus using the same
An initialization signal generation device may be provided. The initialization signal generation device may include a power supply circuit configured to provide one of an external voltage and an internal voltage in response to an initialization signal. The initialization signal generation device may include an initialization signal generator configured to sense the level of the voltage outputted from the power supply circuit and generate the initialization signal. |
| US09722596B2 |
Electronic switch, and corresponding device and method
A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal. |
| US09722592B2 |
Semiconductor integrated circuit device and power supply system
A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET. |
| US09722590B1 |
Skew adjustment circuit, semiconductor device, and skew calibration method
A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits. |
| US09722589B1 |
Clock distribution network for a superconducting integrated circuit
A superconducting integrated circuit including a clock distribution network for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network may include a clock structure having unit cells, where each of the unit cells may include at least one spine and at least one stub. The clock structure may further include at least one spine connected to the at least one stub, where the at least one stub may further be inductively coupled to at least one superconducting element. The clock signal may have a wavelength. Each of the unit cells may be spaced apart from each other along the clock structure by a distance, where the distance may be less than one tenth of the wavelength. |
| US09722587B2 |
Power supply circuit
A power supply circuit has, for example, an overshoot suppressor 100, a control circuit 10, a first transistor M1, a second transistor M2, an inductor L, a capacitor C1, resistors R1 and R2, and an error amplifier ERR. As the load becomes light, the ON-period of the second transistor M2 increases. When the load RL turns from a heavy load to a light or no load, the overshoot suppressor 100 detects an increase in the ON-period of the second transistor M2, and then forcibly turns OFF the second transistor M2. Thus, an overshoot in the output voltage Vo is suppressed. Detecting an increase in the period for which the driving signal S2remains at high level H helps reduce malfunctioning due to noise. |
| US09722585B2 |
Circuit and method to extend a signal comparison voltage range
A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal. |
| US09722582B2 |
Semiconductor device with output driver pre-emphasis scheme
A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal. |
| US09722581B2 |
Methods and systems for operating hybrid power devices using driver circuits that perform indirect instantaneous load current sensing
An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal. |
| US09722579B1 |
Semiconductor device
A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage. |
| US09722575B2 |
Duplexer
A duplexer includes: a transmit filter connected between a transmit terminal and an antenna terminal and including series resonators and parallel resonators connected in a ladder form; and a receive filter connected between a receive terminal and the antenna terminal, wherein at least one of resonators, which are resonators other than a first series resonator and a first parallel resonator located at a first stage as viewed from a side of the transmit terminal and a second series resonator and a second parallel resonator located at a first stage as viewed from a side of the antenna terminal and have electrostatic capacitances less than an electrostatic capacitance of at least one of the first series resonator, the first parallel resonator, the second series resonator, and the second parallel resonator in the series resonators and the parallel resonators, is divided in series. |
| US09722572B2 |
Quartz vibrator and manufacturing method of the same
Embodiments of the invention provide a quartz vibrator, including a long side in a Y′ axis direction, a side in the Y′ axis direction including a first crystal face and a second crystal face formed thereon, and another side including an AT-cut quartz piece including a first crystal face and a second crystal face formed thereon and electrode layers formed on the AT-cut quartz piece. |
| US09722571B2 |
Radio frequency transmitter, power combiners and terminations therefor
A power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding; wherein, the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. In addition, there is provided a radio frequency (RF) transmitter having a power combiner, where the power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding, wherein the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. |
| US09722569B1 |
Multi-band low frequency impedance tuner
A multi-band, electro-mechanical programmable impedance tuner for the frequency range between 10 and 200 MHz uses cascades of three or more continuously variable mechanical capacitors interconnected with sets of low loss flexible or semi-rigid cables; for each frequency band a different set of cables and capacitors are used. The cables and/or variable capacitors inside each tuning block are switchable manually or remotely. Multi-section variable capacitors are also used. Instantaneous impedance tuning is effectuated by changing the state of the capacitors using electrical stepper motors. The tuner is calibrated using a vector network analyzer and the data are saved in the memory of the control computer, which then allows tuning to any user defined impedance within the tuning range. Reflection factor values between 0 and higher than 0.9 can be obtained using this tuner at all frequency bands. |
| US09722568B2 |
Thin film surface mount components
Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads which are exposed to the outside of the surface mount component and electrically connected to external terminations. External terminations may include at least one layer of conductive polymer. Optional shield layers may protect the surface mount components from signal interference. A cover substrate may be formed with a plurality of conductive elements that are designed to generally align with the conductive pads such that conductive element portions are exposed in groups along surfaces of a device. |
| US09722567B2 |
Variable-frequency resonance circuit and variable-frequency filter
A variable-frequency resonance circuit includes first and second input/output terminals and a resonance circuit portion. The resonance circuit portion includes a first inductor and first and second LC series circuits. The resonance circuit portion is connected between a ground and a transmission line that connects the first and second input/output terminals. The first LC series circuit includes a second inductor and a variable capacitor connected in series with each other. The second LC series circuit includes a third inductor and a fixed capacitor connected in series with each other. The first and second LC series circuits are connected in parallel between the first inductor and a ground. The first and second inductors are configured such that positive-coupling mutual inductance is produced therebetween. |
| US09722564B2 |
Reconfigurable electromagnetic interference filter network
An EMI filter network may be used to provide interference filtering for multiple loads (referred to collectively as a dynamic load). In one aspect, the EMI filter network includes electrical switches that establish different configurations or arrangements of passive circuit elements (e.g., inductors and capacitors) where each configuration generates a different filter value. The EMI filter network may be communicatively coupled to a controller which changes the configuration of the EMI filter network using the switches in response to the dynamic load changing operational states. For example, each configuration of the EMI filter network may correspond to one of the operational states of the dynamic load. Thus, as the operational state of the dynamic load changes—e.g., different motors become operational—the controller alters the configuration of the EMI filter network to provide a filter value that corresponds to the current operational state of the dynamic load. |
| US09722563B2 |
System and method for high input capacitive signal amplifier
In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block. |
| US09722561B2 |
Systems and apparatus providing frequency shaping for microphone devices and methods of operation of the same
A device is provided. The device includes: a sensor adapted to receive an acoustic wave and generate an electrical signal in response to receipt of the acoustic wave; clock frequency detection circuitry adapted to receive a clock signal, detect a frequency of the clock signal and generate information representative of the frequency; and digital filter circuitry coupled to the clock frequency detection circuitry. The digital filter circuitry is adapted to: receive the clock signal and the information representative of the frequency; access a first set of one or more digital filter coefficient values; and selectively change the first set of the one or more digital filter coefficient values to a second set of one or more digital filter coefficient values based on the information representative of the frequency, wherein the one or more digital filter coefficient values are included within a plurality of digital filter coefficient values. |
| US09722554B2 |
Differential amplifier and display driver including the same
When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal. |
| US09722553B2 |
High-frequency amplifier circuit
A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential. |
| US09722550B2 |
Power amplifying radiator (PAR)
A power amplifying radiator is disclosed that includes an electric field receiver or radio frequency (RF) energy coupling and impedance matching element, a capacitive coupler, a cavity combiner including a coaxial-cavity section providing electromagnetic communication with the capacitive coupler, and a phased-array antenna/one or more phased-array antennas. The RF energy coupling and impedance matching element is in electromagnetic communication with the one or more phased-array antennas via the cavity combiner. The cavity combiner includes a center conductor configured and disposed to project from the coaxal-cavity section such that the cavity combiner defines a co-axial cross-sectional configuration. The power amplifying radiator may be included within a high power microwave system. |
| US09722545B2 |
Emphasis circuit
Provided is an emphasis circuit capable of obtaining a desired emphasis amount with which waveform deterioration of an output signal in a high frequency band (high frequency band deterioration) is suppressed without increasing power consumption (current consumption). In the emphasis circuit, a baseband amplifier section and a peaking amplifier section are connected in parallel to each other, and respective drive current setting sections are adjusted to adjust respective drive current values thereof so that the sum of the drive current value of the baseband amplifier section and the drive current value of the peaking amplifier section may be constant. |
| US09722542B2 |
Power amplification module
A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage. |
| US09722540B2 |
Method and apparatus for setting frequency of wireless power transmission
The present disclosure relates to a method and apparatus for setting the frequency of wireless power transmission. To this end, the method for setting the frequency of a wireless power transmission apparatus can include the steps of: obtaining power transmission information from the wireless power receiving apparatus receiving a wireless power signal; and setting the transmission frequency of the wireless power signal on the basis of the obtained power transmission information. |
| US09722534B2 |
Computation of glint, glare, and solar irradiance distribution
Described herein are technologies pertaining to computing the solar irradiance distribution on a surface of a receiver in a concentrating solar power system or glint/glare emitted from a reflective entity. At least one camera captures images of the Sun and the entity of interest, wherein the images have pluralities of pixels having respective pluralities of intensity values. Based upon the intensity values of the pixels in the respective images, the solar irradiance distribution on the surface of the entity or glint/glare corresponding to the entity is computed. |
| US09722530B2 |
Motor drive circuit
A drive circuit for an electric motor, has a driving source unit, configured to generate a driving source signal and a driving unit, connected to the motor and configured to drive the motor according to the driving source signal. A sensing unit senses the actual speed of the motor. A control unit stops operation of the motor when the actual speed of the motor falls below a predetermined level. A timing unit counts a predetermined time period from the time the motor stops operation. The motor resumes operation at the end of the predetermined time period. |
| US09722529B2 |
Control for pulse width modulated driven motors
A method for assisting in operating a PWM driven motor comprising for at least one phase of the PWM driven motor: generating a pulse width modulated phase voltage scheme according to a desired phase profile with a base scaling factor, by time multiplexing a first pulse and at least a further pulse within a pulse width modulation period of the phase the first pulse having a pulse width according to a first profile, for that rotor position, multiplied with a first scaling factor, the first profile being in phase with the desired phase profile, and the at least a further pulse having a pulse width corresponds with a further profile, for that rotor position, multiplied with a further scaling factor, the further profile being not in phase with the desired phase profile, whereby the first pulse and the at least one further pulse are positioned within the pulse width modulation period of the phase in at least partially non-overlapping way. |
| US09722526B2 |
Modular motor drive communication system and method
A motor drive system includes a control module and a power module for generating control signals and power signals, respectively, for driving an electric motor. An add-on module or subassembly is physically positionable between the control and power modules, and communicates with the control module to allow for communication with external devices. |
| US09722525B2 |
Protective redundant subsystem for power tools
A protective redundancy circuit is provided for a power tool having an electric motor. The protective redundant subsystem is comprised of: a motor switch coupled in series with the motor; a motor control module that controls the switching operation of the motor switch; and a protective control module that monitors switching operation of the motor switch and disables the power tool when the switching operation of the motor switch fails. In the context of an AC powered tool, the switching operation of the motor switch is correlated to and synchronized to the waveform of the AC input signal. During each cycle or half cycle, the motor control module introduces a delay period before closing the motor switch and the protective control module determines the operational status of the motor switch by measuring the voltage across the motor switch during the delay period. |
| US09722521B2 |
Digital control for a microelectromechanical element
A control circuit for a microelectromechanical element includes: a waveform generator, which is designed to generate a digital trigger signal for the microelectromechanical element, a modulator, which is designed to oversample the digital trigger signal, to subject the signal to a noise shaping, and to output the oversampled and noise-shaped digital trigger signal; and a digital driver device, which is designed to drive the microelectromechanical element using the oversampled and noise-shaped digital trigger signal. |
| US09722520B2 |
Direct power and stator flux vector control of a generator for wind energy conversion system
A method for controlling a variable speed wind turbine generator is disclosed. The generator is connected to a power converter comprising switches. The generator comprises a stator and a set of terminals connected to the stator and to the switches of the power converter. The method comprises: determining a stator flux reference value corresponding to a generator power of a desired magnitude, determining an estimated stator flux value corresponding to an actual generator power, determining a difference between the determined stator flux reference value and the estimated stator flux value, and operating said switches in correspondence to the determined stator flux reference value and the estimated stator flux value to adapt at least one stator electrical quantity to obtain said desired generator power magnitude. |
| US09722516B2 |
Motor drive circuit and method
In accordance with an embodiment, a drive circuit is provided for driving for a motor wherein the drive circuit includes a first signal generator coupled to a second signal generator. A bias generator is connected to the second signal generator. In accordance with another embodiment, a method for driving a motor is provided that includes comparing a first signal at a first output of a Hall sensor with a second signal at a second output of the Hall sensor to generate a comparison signal. An indicator signal is generated in response to the comparison signal, wherein the indicator signal has a first edge and a second edge. A bias signal for the Hall sensor is generated in response to the indicator signal in response to the indicator signal. |
| US09722515B2 |
Motor drive having integral automation controller
A system, in one embodiment, includes a drive having a housing, a stator disposed in the housing, a rotor disposed in the stator, and a programmable logic controller disposed inside, mounted on, or in general proximity to the housing. In another embodiment, a system includes a network, a first motor having a first integral programmable logic controller coupled to the network, and a second motor having a second integral programmable logic controller coupled to the network. In a further embodiment, a system includes a rotary machine having a rotor and a stator disposed concentric with one another, a microprocessor, memory coupled to the microprocessor, a power supply coupled to the microprocessor and the memory, and a machine sensor coupled to the microprocessor. |
| US09722514B2 |
Motor drive and method of controlling a temperature of a motor drive
There is provided a motor drive comprising: a temperature sensor arranged to sense a temperature of the drive; a braking resistor; switching means arranged when activated to cause current to flow to the braking resistor; and controlling means arranged to activate the switching means when the sensed temperature falls below a predetermined threshold. There is also provided a method of controlling a temperature of a motor drive comprising a braking resistor. The method comprising comprises: monitoring a temperature of the drive; and activating switching means to cause current to flow to the braking resistor when the monitored temperature falls below a predetermined threshold. |
| US09722512B2 |
Method for controlling an inertial drive
A method for controlling an inertial drive on the basis of pulse trains is disclosed. The pulse trains include pulses having sections of different gradients and having variable amplitude and/or frequency. A pulse interval occurs between the individual pulses, wherein the selected pulse duration is so short that is substantially less than the cycle duration of the natural oscillation of the system to be driven. |
| US09722504B2 |
Apparatus for converting direct current to alternating current using multiple converters
An inverter for converting an input direct current (DC) waveform from a DC source to an output alternating current (AC) waveform for delivery to an AC grid includes an input converter, an output converter, and an active filter, each of which is electrically coupled to a bus. The bus may be a DC bus or an AC bus. The input converter is configured to convert the input DC waveform to a DC or AC bus waveform. The output converter is configured to convert the bus waveform to the output AC waveform at a grid frequency. The active filter is configured to reduce a double-frequency ripple power of the bus waveform by supplying power to and absorbing power from the power bus. |
| US09722502B2 |
Converter arrangement
A converter arrangement comprises first and second modular multilevel converters, Each of the modular multilevel converters comprises two converter branches. Each converter branch comprises a plurality of series-connected converter cells. Each converter cell comprises a cell capacitor and semiconductor switches for connecting and disconnecting the cell capacitor to the converter branch. At least two converter branches of the first modular multilevel converter are connected via first branch connection point and at least two converter branches of the second modular multilevel converter are connected via second branch connection point. The multilevel converters are connected in parallel via a phase connection point for connecting the converter arrangement to a load or a power source, wherein the phase connection point is connected via a first inductance with the first branch connection point and/or via a second inductance with the second branch connection point. At least one of the modular multilevel converters comprises a protection system. |
| US09722496B2 |
Transmission voltage loss compensation circuit, compensation method, controlling chip and switching power supply
In one embodiment, a method of compensating for transmission voltage loss from a switching power supply, can include: (i) receiving a sampling signal that represents an output current of the switching power supply; (ii) delaying the sampling signal to generate a delayed sampling signal; (iii) converting the delayed sampling signal to generate a compensation signal; and (iv) regulating an output voltage of the switching power supply based on the compensation signal to compensate for the transmission voltage loss from the output voltage transmission to a load such that a voltage at the load is maintained as substantially consistent with an expected voltage at the load. |
| US09722493B1 |
Power converter for ground-referenced system and floating system
Power converters that can allow for the transfer of DC power between a ground-referenced bus and a floating system are provided. In one embodiment, the power converter includes a ground-referenced DC bus associated with a DC voltage. The power converter further includes a first switching element, a second switching element, and a third switching element coupled in series between the ground-referenced DC bus and a ground reference. The power converter further includes a floating system associated with a floating DC voltage. The floating system can include a first terminal coupled to a first node between the first switching element and the second switching element. The floating system can further include a second terminal coupled to a second node between the second switching element and the third switching element. |
| US09722489B1 |
Apparatuses and methods for mixed charge pumps with voltage regulator circuits
Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first output, a second charge pump circuit configured to provide a second output, a plurality of coupling circuits configured to voltage couple and current couple the first output and the second output to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first output and the second output based on the regulated voltage. |
| US09722487B2 |
Hysteresis controllers for power factor correction in AC/DC power converters
Methods, devices, and integrated circuits are disclosed for controlling a power converter. In one example, a controller includes a peak current reference module configured to output a peak current reference. The controller further includes a valley current reference module configured to output a valley current reference. The controller further includes one or more comparators configured to compare a current through the power converter to the peak current reference and the valley current reference, to turn a gate switch of the power converter on when the current through the power converter falls to the valley current reference, and to turn the gate switch of the power converter off when the current through the power converter rises to the peak current reference. |
| US09722486B2 |
Protection circuit
A first detector compares an electric signal to be monitored with a first threshold. A second detector compares the electric signal with a second threshold. A first memory stores setting data of the first threshold. A second memory stores setting data of the second threshold. An interface circuit receives data from an external processor, and writes the data thus received to the first memory and the second memory. The protection circuit is configured such that data writing to the first memory is possible only when a predetermined condition is satisfied. |
| US09722485B2 |
Switching power supply device, electric device, and vehicular device
A switching power supply device includes a switching circuit and a control circuit. The switching circuit includes multiple switching elements, an inductor, and a capacitor. The control circuit compares an input voltage of the switching circuit with a predetermined threshold voltage set for an operation switch, and controls the switching circuit to perform the operation switch between at least two power control operations based on a comparison result. The at least two power control operations includes at least two of a buck operation, a buck-boost operation, or a boost operation. The control circuit further performs an inrush current restriction operation in response to the operation switch in order to restrict a flowing of an inrush current to one of the switching elements, which turns on and outputs the input voltage through the inductor in response to the operation switch. |
| US09722482B2 |
Digital pulse skipping modulation for buck converter with auto-transition to pulse frequency modulation (PFM)
An apparatus and method for a buck converter and regulation loop with pulse skipping modulation (PSM) and auto-transition to pulse frequency modulation (PFM) comprising of a peak current loop configured to provide a method of generating a constant minimal inductor peak current, a system configured to provide a method of skipping pulses utilizing a pulse skipping modulation (PSM) mode of operation, and, the peak current loop configured to provide a method of auto-transition from the pulse skipping modulation (PSM) to a pulse frequency modulation (PFM) mode of operation. |
| US09722478B2 |
Stepping motor
A stepping motor may include a rotor having a rotation shaft and a permanent magnet, a fixed body having a cylindrical stator provided with a plurality of pole teeth so as to face the permanent magnet, an urging member which urges the rotor toward one side in a motor axial line direction, a supported face of the rotor which faces the one side in the motor axial line direction, and a support face of the fixed body which slidably supports the supported face of the rotor on the one side with respect to the supported face. When a first sliding load which is a total sliding load applied to the rotor is “Ta”, a detent torque acted on the rotor is “Td”, and a dynamic torque acted on the rotor by the stator is “Te”, then “Ta”, “Td” and “Te” satisfy the following expression: “Td”<“Ta”<“Te”. |
| US09722475B2 |
Apparatus and method for manufacturing components of dynamoelectric machines
Apparatus and method for winding coils of dynamoelectric machines, wherein a coil comprises members formed of leg portions (19a, 190a). The leg portions (19a, 190a) being inserted in slots (17, 170) of cores (18, 180) of the dynamo electric machine, wherein the slots (17, 170) are provided with insulation members (33, 330) for lining the walls of the slots (17, 170). The leg portions (19a, 190a) are inserted in the slots (17, 170) of the cores (18, 180) of the dynamoelectric machines. A passage member (20, 200) having passages (22, 220) is provided aligned with a core (18 ,180) to align the passages (22, 220) with the slots (17, 170). The area (23, 230) adjacent an edge of a passage (22) is aligned with the end (32, 320) of an insulation member (33, 330) of a slot (17, 170) for engaging the end (32, 320) of the insulation member (33, 330) during insertion of the leg portions (19a, 190a). |
| US09722464B2 |
Gas turbine engine actuation systems including high temperature actuators and methods for the manufacture thereof
Embodiments of a gas turbine engine actuation system are provided, as are embodiments of a high temperature actuator and methods for the manufacture thereof. In one embodiment, the gas turbine engine actuation system includes an actuated gas turbine engine component and a high temperature actuator, which has a rotor mechanically linked to the actuated gas turbine engine component and a stator surrounding at least a portion of the rotor. The stator includes, in turn, a coil support structure having a plurality of spokes extending radially therefrom. A plurality of pre-formed electromagnetic coils is circumferentially distributed about the coil support structure. Each of the plurality of pre-formed electromagnetic coils is inserted over at least one of the plurality of spokes in a radial direction. The stator further includes an inorganic dielectric material in which each of the plurality of pre-formed electromagnetic coils is at least partially embedded. |
| US09722461B2 |
Printing apparatus, method for controlling the same, and program
A digital multifunction peripheral including a contactless power feeding unit having a function of communicating with a terminal apparatus and a function of feeding the power in a contactless manner to the terminal apparatus is configured to detect a status of the digital multifunction peripheral, detect the presence or absence of a power receiving apparatus capable of communicating with the contactless power feeding unit, and, when such a power receiving apparatus is present, detect the status of the power receiving apparatus, and perform power-saving control based on the result of the detections. |
| US09722460B2 |
Coil and ferrite configuration to facilitate near field coupling
Described herein are techniques related to near field coupling (e.g., wireless power transfers (WPF) and near field communications (NFC)) operations among others. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09722457B2 |
Semiconductor chip and solar system
There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal. |
| US09722454B2 |
Wireless charging apparatus including an adapter that holds a device to be charged with a side external to the wireless charging apparatus
A wireless charging apparatus can include an exciter that initiates and shapes electromagnetic fields of microwave frequency. The exciter can include a ground structure and a feed structure disposed within the ground structure. The wireless charging apparatus can also include an adapter configured to hold a device to be charged with a side of the device to be charged exposed external to the apparatus while charging the device to be charged. The adapter can transmit the microwave power from the exciter to the device to be charged. |
| US09722452B2 |
Integrating a wireless charging device with a human machine interface (HMI)
A system and method for integrating a wireless charging device with a display is provided herein. The system includes an information receiver to receive information from the wireless charging device; an information processor to process the information, and the processed information being about a wireless charging device or an electronic device on the wireless charging device; and an information communicator to communicate the processed information to a display coupled to the system. |
| US09722450B2 |
Inductive power transmission geometry
A first electronic device includes an inner inductive coil positioned at least partially around a shield core and a second electronic device includes an outer inductive coil positioned around an aperture. The first electronic device is operable to receive power from and/or transmit power to the second electronic device when a portion of the first electronic device is inserted into the aperture of the second electronic device, positioning the inner inductive coil within the aperture and within the outer inductive coil. When power is being transmitted between the first and second electronic devices, the shield core concentrates magnetic flux around the inner inductive coil and/or the outer inductive coil. In some implementations, an outer shield may be positioned at least partially around the outer inductive coil and may also concentrate magnetic flux around the inner inductive coil and/or the outer inductive coil. |
| US09722446B2 |
Wireless power transmitter, wireless power receiver, and control methods thereof
A control method of a wireless power transmitting unit transmitting charging power to a wireless power receiving unit is provided. The control method includes receiving first signals from one or more wireless power receiving units; classifying wireless power receiving units to be communicated with from among the one or more wireless power receiving units based on reception intensities of the received first signals; transmitting wireless transmission power with predetermined level; receiving second signals including voltage information of the classified wireless power receiving units from the classified wireless power receiving units; and communicating with one or more wireless power receiving unit among the classified wireless power receiving units based on the wireless transmission power and the voltage information of the second signals. |
| US09722445B2 |
Control of hybrid energy storage system for high pulse load
A hybrid energy storage system (HESS) and method of controlling a HESS is provided. The HESS comprises a common direct current (DC) bus having a DC bus voltage, an energy storage device electrically coupled to the common DC bus, a power device electrically coupled to the common DC bus, and a controller in operable communication with the energy storage device, the power device and the common DC bus. The controller is configured to, when the energy storage device is charging, increase a power device charging current if an energy storage device charging current is greater than a charging limit for the energy storage device, and when the energy storage device is discharging, increase a power device discharging current if an energy storage device discharging current is greater than a discharging limit for the energy storage device. The HESS can be part of a power system. |
| US09722443B2 |
Power distribution device
There is a request for charging and discharging of a lithium-ion battery with as less degradation as possible. In an operation using only binary values as in conventional technology, however, in a charged state in which the battery is used, there is a high possibility that the battery is used toward accelerating the degradation thereof. In a power distribution device for distributing power between a plurality of batteries and a plurality of customers, when distributing the power of the batteries to the loads of the customers, by being based at least on the degradation information of the batteries, the state of charge, and the temperature data of the batteries, a battery discharging function is achieved that makes the degradation of the batteries minimum. |
| US09722442B2 |
System and method for transferring energy between vehicles
An embodiment of the present invention relates to a vehicle. The vehicle includes an energy storage device and a traction motor electrically connected to the energy storage device. The traction motor is configured to convert electrical energy supplied by the energy storage device into a mechanical output to propel the vehicle. The vehicle also includes a vehicle connecting mechanism electrically coupled to the energy storage device and being configured for electrical coupling with a second vehicle connecting mechanism of a second vehicle to establish an electrical interface between the vehicle and the second vehicle. The electrical interface enables the transfer of electric power between the vehicle and the second vehicle. |
| US09722438B2 |
Integrated power output service disconnect
The present teachings provide for an electrical connector including a first housing, power terminals, and first and second shunts. The terminals and shunts are located within a cavity of defined by the first housing. The first housing is configured to mate with a second housing to transfer power between a power storage device and components of an electric or hybrid electric vehicle. The first shunt is configured to complete an interlock circuit. The second shunt is configured to complete a service disconnect circuit. The interlock circuit prevents the transfer of power between the first and second housings when the circuit is broken and allows it when complete. The service disconnect circuit causes the power storage device to be substantially electrically isolated from the rest of the vehicle when the circuit is broken. |
| US09722435B2 |
Battery charge balancing device and battery charge balancing system
Disclosed is a battery charge balancing device which includes: a charge-measuring unit that measures charge of a plurality of batteries storing power through a plurality of power converters connected with a plurality of input power sources; a mode-conversion parameter calculating unit that calculates mode conversion parameters for determining mode conversion such that the power converters operate in a power conversion mode for converting power or in a balancing mode for balancing charge between the batteries; and a control unit that controls power transmission path of the power converters by switching a plurality of switches connected between the power converters and the batteries in accordance with the calculated mode conversion parameters. |
| US09722434B2 |
Wireless power transfer system, control method of wireless power transfer system, wireless power transmitting apparatus, control method of wireless power transmitting apparatus, and storage medium
A wireless power transfer system comprising a wireless power transmitting apparatus and a plurality of wireless power receiving apparatuses, the wireless power transmitting apparatus comprising: a power transmitting unit adapted to transmit power to the wireless power receiving apparatus; a recognition unit adapted to recognize the wireless power receiving apparatus; and a transmitting unit adapted to transmit predetermined charging delay information according to a recognition result of the recognition unit to the wireless power receiving apparatus recognized by the recognition unit, and the wireless power receiving apparatus comprising: a power receiving unit adapted to receive power transmitted from the power transmitting unit; a receiving unit adapted to receive the predetermined charging delay information transmitted from the transmitting unit; and a display unit adapted to make a display based on the predetermined charging delay information received by the receiving unit. |
| US09722433B2 |
Power receiving device, power transmitting device and power transfer system
A power transmitting device includes power transmitting coils, which contactlessly transmit electric power to a power receiving coil, and a switching device. When the power receiving coil is a solenoid coil, the switching device connects the power transmitting coils in parallel with each other such that magnetic fluxes generated inside the power transmitting coils flowing in the same direction along a winding axis. When the power receiving coil is a circular coil, the switching device connects the power transmitting coils in series with each other such that magnetic fluxes generated inside the power transmitting coils flowing in opposite directions along the winding axis. |
| US09722431B2 |
Specimen processing system
In the specimen processing system in which each of a specimen input portion which inputs a specimen, a specimen processing portion which processes the specimen, a specimen recovery portion which recovers the processed specimen, and a specimen transporting line which transports the specimen between the specimen input portion, the specimen processing portion, and the specimen recovery portion, are connected to each other by a plurality of processing (analysis) units, the processing (analysis) unit is provided with a CPU that controls the operation, and provided with a mechanism control portion which receives an electric signal from the CPU and operates the mechanism parts in the processing unit, and the mechanism part control portion includes means which can supply and stop the power of one or more arbitrarily specified mechanism parts by the electric signal from the CPU. |
| US09722430B2 |
Method and system for analyzing user loads in combination with time information
A method for analyzing a user load in conjunction with time information and a system thereof are provided. In the case that an enterprise operates in a non-full-time operational mode, operation periods of the enterprise are adjusted, electricity prices for respective adjusted operation periods are obtained, and the electricity prices are multiplied with electricity consumptions to obtain electricity charges of the enterprise. In the case that the enterprise operates in a full-time operational mode, electricity consumptions in respective hours of the enterprise are adjusted, the electricity consumptions are multiplied with electricity prices for the respective hours to obtain electricity charges of the respective hours of the enterprise, and the electricity charges of the respective hours are accumulated to obtain a total electricity charge of the enterprise. |
| US09722425B2 |
Determining a string configuration in a multistring-inverter
In operating an inverter including input connectors, (i) to which strings of photovoltaic cells are connected, (ii) each of which is connected via a DC/DC converter to a common DC voltage link, and (iii) which are bridgeable, the partial powers flowing through the individual DC/DC converters are determined, and for some time at least two DC/DC converters are either operated with the aim of balancing the partial currents flowing through them or connected through. During this operation or connecting through, the partial powers flowing through the at least two DC/DC converters are compared with each other, and if a difference between the partial powers exceeds a threshold value, the DC/DC converters are subsequently operated in a way adjusted to the fact that they connect different strings to the DC voltage link. |
| US09722424B2 |
Arrangement comprising a fuel cell system
A system (0) includes an electrical load system (54) with a load network battery (82), and a fuel cell system (1). Operation is simplified, especially during start of the fuel cell system (1) if the fuel cell system (1) has a system battery (56). A system voltage across the system battery (56) can be supplied to electrical system loads (80) of the fuel cell system (1) and, via a load voltage converter (77) and at least one additional voltage converter (86), to the load system (54) and secondary electrical loads (84, 85). |
| US09722422B2 |
DC plant for selecting among multiple power sources
Various embodiments of a DC plant. In one embodiment, the DC plant includes (1) power sources couplable to a common DC bus, (2) rectifiers and DC-DC converters associated with the power sources and (3) a DC plant controller. The DC plant controller includes a source identifier configured to identify the power sources, a source prioritizer coupled to the source identifier and configured to prioritize the power sources based on at least one criterion, and an output characteristic assigner coupled to the source prioritizer. |
| US09722421B2 |
DC plant controller and method for selecting among multiple power sources
Various embodiments of a DC plant controller and methods of selecting among multiple power sources. In one embodiment, the DC plant controller includes: (1) a source identifier configured to identify power sources couplable to a common DC bus, (2) a source prioritizer coupled to the source identifier and configured to prioritize the power sources based on at least one criterion, (3) an output characteristic assigner coupled to the source prioritizer and configured to place ones of the power sources on standby based on a calculated battery holdup time. |
| US09722420B2 |
Adaptive power control for energy harvesting
Advances in the arts are disclosed with novel methods and circuit systems for controlling power in an energy harvesting system. Techniques and related systems for controlling power output of an energy harvesting device provide for monitoring at least one power parameter at a power source and monitoring at least one power parameter at a load such as a storage medium. The power source output is adjusted in order to optimize energy harvesting and/or storage based on real-time performance parameters. |
| US09722416B2 |
Isolating faulty converter module in converter system with interconnected DC links
According to an embodiment, a power generation system is provided comprising a power generator; a plurality of converter modules, each converter module having a DC link, wherein the DC link of each converter module is connected to the DC links of the other converter modules of the plurality of converter modules via a fuse associated with the converter module; and a controller configured to, if it is detected that there is a fault in one of the converter modules, disconnect the converter module in which there is a fault from the power generator and connect two or more other converters module of the plurality of converter modules to the power generator and to control the power generation system to supply power to the DC links of the two or more other converter modules such that power is supplied to the converter module in which there is a fault via the fuse associated with the converter module such that the fuse associated with the converter module melts. |
| US09722415B2 |
Regulating temperature on an actuator
A safety device for an actuator that can modulate power to an electric motor in response to a fault condition (e.g., stall). In one embodiment, the actuator can include a motor with a shaft, a sensor disposed in proximity to the shaft, and a control processor coupled with the sensor and the motor. The control processor can be configured to receive a signal from the sensor that conveys operating data that relates to rotation of the shaft, use the operating data to identify a fault condition on the motor, and change the motor from an energized condition to a de-energized condition in response to the fault condition. |
| US09722413B2 |
Devices for ground-resistance detection
A ground-resistance detection device, which is coupled to a power system including a first power line, a second power line, and a protective earth, includes a ground-resistance detection circuit and a controller. The ground-resistance detection circuit includes a first input node and a second input node. The first input node is coupled to either the first power line or the second power line. The second input node is coupled to a ground terminal. The ground-resistance detection circuit generates a DC output voltage according to the voltage of the first input node, the voltage of the second input node, and the DC reference voltage. The controller determines the ground resistance between the protective earth and the ground terminal according to the DC reference voltage and the DC output voltage. |
| US09722410B2 |
Burning protection circuit, display device and method of protecting a display device from burning
A burning protection circuit of a display device includes a plurality of current measuring units and a control unit. The display device includes a plurality of pixel blocks. Each of the pixel blocks includes a plurality of pixels. The pixel blocks are respectively supplied with power through a plurality of power supply lines. The current measuring units are configured to respectively generate a plurality of measured current values by respectively measuring a plurality of currents respectively supplied to the pixel blocks through the power supply lines. The control unit is configured to respectively generate a plurality of block data for the pixel blocks based on pixel data for the pixels of corresponding ones of the pixel blocks, and determine whether an overcurrent occurs based on a plurality of ratios of the measured current values to corresponding ones of the block data. |
| US09722407B2 |
Guided cable storage assembly with switchbacks
A cable handling assembly is adapted to store and pay-out a telecommunications cable. The assembly includes first and second sets of pulleys, a housing, and a cable route. The first and second sets of pulleys are spaced from each other by a take-up distance that decreases upon the cable being paid-out. The housing supports the pulleys and also guides the pulleys as the take-up distance changes. The cable route is routed between the first and second sets of pulleys. A stack of pulley sets may be formed and may include at least one intermediate pulley set positioned between the first and second pulley sets. The cable route is routed between adjacent pulley sets of the stack of pulley sets. A route length decreases as the take-up distance decreases. A rack unit for organizing a plurality of telecommunications cables in a telecommunications rack may include a plurality of the cable handling assemblies. At least one of the cable handling assemblies may include a retraction apparatus that further adapts the at least one cable handling assembly to retract the corresponding telecommunications cable. |
| US09722400B2 |
Application and maintenance of tension to transmission line in pipe
A method for providing tension to a data or power transmission line in a pipe includes inserting a transmission line into a transmission line channel of a pipe. The transmission line has a first end and a second end and is inserted into a first end of the pipe second-end-first and has a first tension-load-supporting mechanism attached to the first end of the transmission line. The method includes applying a first level of tension to the transmission line in the pipe and applying a second tension-load-supporting mechanism to the second end of the transmission line while the first level of tension is applied to the transmission line. The method further includes removing the first level of tension from the transmission line to maintain a second level of tension along the transmission line between the first and second tension-load-supporting mechanisms. |
| US09722399B2 |
Electrical system, and connection device and method of powering a switchgear bus in an electrical system
A connection device is for an electrical system. The electrical system has a powering apparatus, an electrical switching apparatus, and a switchgear bus. The electrical switching apparatus is coupled to the powering apparatus. The connection device includes: a mounting assembly having a panel and a support wall opposite the panel; an electrical transfer assembly including: a number of interconnect assemblies each having a load interconnect member, the load interconnect member being coupled to the panel and electrically connected to the powering apparatus; and a number of base assemblies each including: a number of stud members each coupled to the support wall. At least one of the number of stud members is electrically connected to the load interconnect member and electrically connected to the switchgear bus. |
| US09722393B2 |
Laser diode chip and flip chip type laser diode package structure
A flip chip type laser diode includes a first substrate, a first semiconductor layer disposed on the first substrate, an emitting layer disposed on one part of the first semiconductor layer, a second semiconductor layer disposed on the emitting layer and forming a ridge mesa, a current conducting layer disposed on another part of the first semiconductor layer, a patterned insulating layer covering the second semiconductor layer and the current conducting layer and including a first zone and a second zone which respectively expose a part of the current conducting layer and a part of the second semiconductor layer, a first electrode and a second electrode respectively disposed on the first zone and the second zone. A projection of the ridge mesa projected to the first substrate covers a part of projections of the first electrode and the second electrode projected to the first substrate. |
| US09722392B2 |
Laser systems and related methods
A MOPA laser system that includes a seed laser configured to output pulsed laser light, an amplifier configured to receive and amplify the pulsed laser light emitted by the seed laser; and a pump laser configured to deliver a pump laser beam to both the seed laser and the amplifier. |
| US09722391B2 |
Laser system
A laser system according to an embodiment of the present invention includes an oscillation unit to generate a laser output, a connection unit to connect the oscillation unit with an optical fiber loop, an amplifying unit to amplify the laser output on the optical fiber loop, a conversion unit disposed on the optical fiber loop to convert pulsed wave laser output into continuous wave laser output, and an output unit disposed between the connection unit and the conversion unit to split a part of the laser output toward the conversion unit. The system for generating a high output pulsed wave laser and converting the pulsed wave laser into a continuous wave laser may be implemented in a simple structure and small size with high stability and high reproducibility. In addition, a high output laser may be obtained. Also, since conversion from the pulsed wave into the continuous wave is easy, both of the high output pulsed wave and the high output continuous wave may be obtained as necessary. |
| US09722389B2 |
Fiber laser having optical resonator comprising tapered element
A laser system for generating optical pulses at an operating wavelength of the laser system. The system has an optical resonator comprising first and second reflectors, and a tapered optical fiber disposed between the first and second reflectors. The tapered optical fiber has a core which has a tapered input section which tapers from single mode to multimode at the laser operating wavelength, an inner section of substantially constant diameter capable of supporting multiple modes at the laser operating wavelength and a tapered output section which tapers from a first diameter to a second diameter that is smaller than the first diameter. |
| US09722388B2 |
Multi-core optical amplifying fiber device and multi-core optical fiber amplifier
A multi-core optical amplifying fiber device includes a plurality of multi-core optical amplifying fibers including a plurality of core portions doped with amplification medium and a cladding portion formed at outer peripheries of the plurality of core portions; and a connection portion connecting the core portions of the plurality of multi-core optical amplifying fibers to one another. The connection portion connects the core portions to restrain deviation, between every connected core portions, of amplification gain for a total length of the core portions connected one another. |
| US09722387B2 |
Compact optical fiber amplifier
A fiber-based optical amplifier is assembled in a compact configuration by utilizing a flexible substrate to support the amplifying fiber as flat coils that are “spun” onto the substrate. The supporting structure for the amplifying fiber is configured to define the minimal acceptable bend radius for the fiber, as well as the maximum diameter that fits within the overall dimensions of the amplifier package. A pressure-sensitive adhesive coating is applied to the flexible substrate to hold the fiber in place. By using a flexible material with an acceptable insulative quality (such as a polyimide), further compactness in the final assembly is achieved by locating the electronics in a space underneath the fiber enclosure. |
| US09722386B2 |
Laser oscillator comprising heat exchanger having function of collecting foreign matters
A laser oscillator comprises a heat exchanger which cools a gas medium. The heat exchanger includes a cooling part which performs heat exchange between the gas medium and a cooling medium, a tubular member fixed to a frame body, and a foreign matter collection container. The tubular member is disposed so that the gas medium which flows out of the cooling part moves along an outer surface of the tubular member and then changes a proceeding direction to flow into an inlet portion. The foreign matter collection container collects foreign matters which are separated from a flow of the gas medium. |
| US09722385B2 |
Laser chamber
A laser chamber for a discharge excited gas laser apparatus may include: a first discharge electrode disposed in the laser chamber; a second discharge electrode disposed to face the first discharge electrode in the laser chamber; a fan configured to flow laser gas between the first discharge electrode and the second discharge electrode; a first insulating member disposed upstream and downstream of a laser gas flow from the first discharge electrode; a metallic damper member disposed upstream of the laser gas flow from the second discharge electrode; and a second insulating member disposed downstream of the laser gas flow from the second discharge electrode. |
| US09722383B2 |
Electrical connector having insulative housing and method of making the same
An electrical connector (100) includes a shielding plate (1), a base portion (2) insert molded with the shielding plate and defining two rows of passageways (21), two rows of terminals (3) affixed to the base portion, and an insulative housing (4) over molded with the base portion. The two rows of passageways extend through the base portion along a front-to-back direction and exposed completely upwardly and downwardly. Each terminal includes a contacting beam (31) having a contacting portion (311). The shielding plate is located between the two rows of terminals. |
| US09722373B2 |
Insertion plug
An insertion plug includes:a rotor fixed around a blade, and housed in an insulating plug case;a guide unit in the insulating plug case to guide the rotor around an axis extending in a longitudinal direction of the blade and within a rotation angle of at least 90 degrees between a first rotation position at which the blade becomes substantially parallel with another blade and a second rotation position at which the blade becomes substantially orthogonal to the other blade; anda positioning unit that positions the rotor at the first rotation position or the second rotation position,the blades caused to project from a position corresponding to an AC power source outlet if the rotor is positioned at the first rotation position, andthe blades caused to project from a position corresponding to a DC power source outlet if the rotor is positioned at the second rotation position. |
| US09722368B2 |
Cylindrical folding cable
Embodiments generally relate to a cable that substantially forms itself into a cylindrical shape when not extended, yet can be extended with a slight force to provide an electrical coupling as, for example, for earphones used with a mobile device such as a mobile phone. |
| US09722361B2 |
Connector with shield shell for cable
A connector is provided to facilitate the connection work of a connection terminal and to enhance the connection reliability. A connector includes an attachment part that includes a terminal stand; a connector main body that includes a connection terminal connected to a cable, the connection terminal being fastened and fixed to the terminal stand in a state in which the connector main body is mounted to the attachment part; a cable shield shell that covers an introduction part for the cable in the connector main body; and a connection part shield shell that covers a fastening area between the connection terminal and the terminal stand so as to accommodate the cable shield shell inside the connection part shield shell. |
| US09722356B2 |
Connector
A connector includes a ground frame, an insulator held by the ground frame and having a connection target housing portion, a contact having a contact portion and held by the insulator such that the contact portion is exposed at the connection target housing portion, and a cover member held by the ground frame to be rotatable between an open position and a closed position and having a cover member side locking portion, the ground frame having a projection that is fitted to a positioning shaped portion of the connection end of the connection target, when the connection end is housed in the connection target housing portion, to position the connection target and that catches on the cover member side locking portion, when the cover member is in the closed position, to lock the cover member in the closed position. |
| US09722350B1 |
Connector terminal and method of assembling the same
A connector terminal with a unit-mountable connector of that includes a connector body having an adapter engagement end and a unit engagement end, and a mounting member therebetween for mounting the connector body to a unit. An insert extends through the connector body and has an inner bore extending between a cable interface end and a unit interface end, and a connector body interface portion between the ends. One or more double-sided contacts are received in the insert. The double-sided contact is one-piece with one end that is a cable termination end configured to terminate to a conductor of a cable and an opposite end that is a unit termination end configured to terminate to a conductor of the unit. The unit-mountable connector is adapted to mate with a cable sealing adapter. The cable sealing adapter is devoid of contact. |
| US09722349B2 |
Wire harness
It is an object of the present invention to ensure a high water-stopping property of a wire harness including a waterproofing connector section that is molded from a resin, by suppressing a variation in the outer size of a seal section of the connector section. The connector section is made from a first synthetic resin that is insert-molded with a part of a terminal fitting of the terminated electric cable used as an insert section. A water-stopping section is made from a second synthetic resin that is insert-molded with a section extending from a part of the terminal fitting to an insulation coating of the terminated electric cable used as an insert section. The seal section is made from the second synthetic resin that is insert-molded with a part of the connector section used as an insert section. The second synthetic resin is softer than the first synthetic resin. |
| US09722342B2 |
Electrical connector
An electrical connector includes a main body mounted to the circuit board, a shielding plate assembly fastened to the main body, and a plurality of conductive terminals mounted to the main body and arranged in two rows. The shielding plate assembly is located between the two rows of the conductive terminals. Each of the conductive terminals has a fastening portion, a contact portion and a soldering portion. A front end of the contact portion has a contact surface. Thicknesses of two opposite sides of the front end of the contact portion are smaller than a thickness of a middle of the front end of the contact portion. The contact surfaces of the contact portions of the conductive terminals are exposed to a top surface and a bottom surface of the main body, respectively. |
| US09722340B2 |
Electric wire connector structure
A connector structure includes a plurality of terminals to be connected to an electric wire, an electronic component configured to control an external component to be connected to the terminals, and a housing holding the terminals and the electronic component to accommodate the terminals and the electronic component. Each terminal includes a connection portion to be connected to the electric wire, and an extension portion having a cross section of an arc shape and extending from the connection portion. The housing is configured to hold the plurality of terminals and the electronic component such that the cross sections of the extension portions are arranged to form a substantially circular shape that surrounds the electronic component. |
| US09722335B2 |
Dual in line memory module (DIMM) connector
An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place. |
| US09722334B2 |
Power tool with light unit
A power tool includes a housing coupled to an electrical power source, a motor contained in the housing, and a motor control circuit that controls output speed of the motor. A light unit is coupled to the housing to illuminate a work surface. A light unit control circuit controls illumination of the light unit. A switch unit is coupled to the housing and selectively operable to control the operation of the motor control circuit and the light unit control circuit. The light unit control circuit includes a timer configured to cause the light unit to illuminate a first brightness level when the switch unit is actuated, and to remain illuminated at the first brightness level for a predetermined time period after the trigger is actuated. The predetermined time period restarts if the switch unit is not deactivated before the end of the predetermined time period. |
| US09722329B2 |
Apparatus for making electrically conductive contact
Apparatus for making electrically conductive contact with an electrically conductive, elongated, body, for example a pipe or cable. Apparatus includes a base body having a metal carrier element configured as a clamp clampable around body to be contacted, and open in circumferential direction. Apparatus includes a connecting device with a connecting member, by which ends of carrier element are connectable or connected to one another when mounted. Apparatus has a contact device for establishing electrically conductive connection between body contacted and conductor, such as grounding cable. A connecting member configured for cooperating with a guide device for guiding translatory motion of connecting member, and situated at free ends of carrier element so that in mounted position of apparatus, translatory motion of the connecting member between a guide start and a guide end of guide device achieves a nondestructively detachable form fit, connecting free ends of the carrier element. |
| US09722328B2 |
Contact part and method for producing a contact part
Embodiments disclose a contact part comprising a sleeve forming a receiving space for inserting a plug-in contact in an insertion direction, at least one contact spring secured to the inside of the sleeve, and a locking pin configured to be displaceably guided in the sleeve between first and second end positions in sliding contact with the contact spring, wherein the locking pin is configured to push the contact spring in the direction of the receiving space to varying degrees depending on the position of the locking pin between the two end positions. Embodiments disclose a method for producing a contact part comprising providing a sheet metal part and at least one contact spring held in a form-locked manner in the sheet metal part, and forming the sheet metal part to obtain a sleeve that forms a receiving space for inserting a plug-in contact in the insertion direction. |
| US09722326B2 |
Circular base station antenna array and method of reconfiguring a radiation pattern
Aspects of the present disclosure may be directed to a reconfigurable antenna system including a reconfigurable antenna capable of providing various types of radiation patterns without having to be replaced or needing its orientation changed. The reconfigurable antenna may create various types of quasi-omni directional radiation patterns of different shapes depending on the environment. |
| US09722324B2 |
Method and apparatus to control mutual coupling and correlation for multi-antenna applications
The present invention provides a method and apparatus to manipulate the mutual coupling and the correlation between the antennas (502, 504) on the handset (202) without the need to change the physical distance between them or to change their orientation. The manipulation in the mutual coupling and in the correlation is achieved using a circuit that is connected between the antennas' terminals (506, 508) and the terminals (510, 512) of the RF front end/power amplifier (514). This circuit can be fixed or tunable. The coupling control takes place between two transmitting antennas (502, 504) or two receiving antennas (502, 504). |
| US09722323B2 |
Isolation structures for dual-polarized antennas
An antenna, including a first dipole having a first polarization, the first dipole including a first pair of dipole arms, a second dipole having a second polarization, the second dipole including a second pair of dipole arms, at least one dipole arm of the first pair of dipole arms being located with respect to at least one dipole arm of the second pair of dipole arms so as to form at least one isolation slot therebetween, currents along the at least one isolation slot being operative to at least partially cancel mutual coupling between the first dipole and the second dipole, and a feed arrangement for feeding the first and second dipoles. |
| US09722320B2 |
Electromagnetic field induction for inter-body and transverse body communication
A electromagnetic induction wireless communication system including: a magnetic antenna; an electric antenna; a tuning capacitor coupled to the antenna combination configured to tune the antenna combination; a controller configured to control the operation of the communication system; a signal source coupled to the controller configured to produce a communication signal used to drive the magnetic antenna and the electric antenna; a voltage control unit coupled to the signal source configured to produce one of an amplitude difference, phase difference, and an amplitude and a phase difference between the communication signal used to drive the magnetic antenna and electric antenna. |
| US09722318B2 |
Method and apparatus for coupling an antenna to a device
Aspects of the subject disclosure may include, for example, an antenna structure that includes a dielectric antenna comprising a dielectric feedline having a feed point, and a collar that facilitates aligning a port of a waveguide system to the feed point of the dielectric feedline for facilitating transmission or reception of electromagnetic waves exchanged between the port and the feed point of the dielectric feedline, the electromagnetic waves guided by the dielectric feedline without an electrical return path. Other embodiments are disclosed. |
| US09722315B2 |
Ultra-wideband (UWB) dipole antenna
An ultra-wideband (UWB) antenna for wireless communication in proximity to a human body and between devices having no line-of-sight, includes symmetrical radiators disposed on a side of a dielectric layer, and a differential microstrip feeding line disposed on the side and an opposite side of the dielectric layer. The UWB antenna further includes a top dielectric layer disposed over the side of the dielectric layer, a bottom dielectric layer disposed over the opposite side of the dielectric layer, and a top connecting plate disposed on an outer surface of the top dielectric layer. The UWB antenna further includes a bottom connecting plate disposed on an outer surface of the bottom dielectric layer, and an inter-layer connector configured to connect ends of each of the symmetrical radiators to the top connecting plate and the bottom connecting plate, respectively. |
| US09722309B2 |
Mobile radio antenna comprising a multi beam forming device
A mobile radio antenna comprises a multi beam forming device which comprises a drivable drive element having a drive shaft and at least two output shafts. Each output shaft is substantially parallel to the drive shaft. At least one output gear is rotationally fixed to the output shaft. At least two phase shifters are each operatively connected to a respective output shaft via a respective drive device. A changeover device enables the drive element to be operatively connected selectively to at least one of the output gears. |
| US09722308B2 |
Low passive intermodulation distributed antenna system for multiple-input multiple-output systems and methods of use
Low passive intermodulation (PIM) antenna assemblies and methods for utilizing the same. In one embodiment, the low PIM antenna assemblies described herein offer the lowest PIM level for the DAS antenna as compared with current PIM solutions currently available in the market place as well as the improvement of isolation between the radiating elements using inserted isolation rings as well as a more omni-directional radiation pattern using the insertion of slots into the radiating elements themselves. Methods of manufacturing and using the aforementioned low PIM antenna assembly are also disclosed. |
| US09722306B2 |
Antenna unit
An antenna unit is disclosed. A hearing device, such as a hearing aid, having an antenna device is disclosed. The antenna unit allows wireless communication to and from the hearing device. |
| US09722304B2 |
Mobile device
A mobile device includes a ground element and an antenna structure. The antenna structure includes a ground branch, a feeding branch, a low-frequency radiation branch, and a high-frequency radiation branch. The feeding branch is coupled through the ground branch to the ground element. The low-frequency radiation branch is coupled to the feeding branch. The high-frequency radiation branch is coupled to the feeding branch. The low-frequency radiation branch has a meandering structure for reducing the SAR (Specific Absorption Rate) of the antenna structure. |
| US09722299B2 |
Antenna assembly, wireless communication device and method of manufacturing same
An antenna assembly includes a holder having a first surface and a second surface opposite from the first surface. The antenna assembly defines a number of holes through the first surface and the second surface. A number of connectors are correspondingly received and secured in the holes. The connectors includes an elastic thimble portion on one end. An antenna module is formed on the holder. One end of the connectors connects to the antenna module, while the end with elastic thimble protrudes from the second surface for connecting to a circuit board. A wireless communication device employing the antenna assembly and a method of manufacturing the wireless communication device are also disclosed. |
| US09722296B2 |
Clamp device for mounting antenna to rail
A device for mounting an antenna to a rail is provided. The device includes a first clamp member and a second clamp member. The first clamp member includes a planar base plate having a first surface and a second surface. The planar base plate has at least two slots spaced apart on a longitudinal axis. At least two extension sections extend from the first surface of the planar base plate and being spaced apart along the longitudinal axis and closer to a center than the at least two slots. Each extension section includes a patterned cutout area configured to receive the rail. A plurality of threaded fasteners extend from the first surface of the planar base plate and being positioned outside the patterned cutout area along a transverse axis perpendicular to the longitudinal axis. The second clamp member has a plurality of through-holes configured to receive the plurality of threaded fasteners and a planar surface facing toward the first surface of the first clamp member. |
| US09722295B2 |
Bracket for mounting radio equipment to a radio tower
A bracket for mounting radio equipment to a radio tower comprises a frame including first and second longitudinal pipe members opposed from each other, the first and second pipe members including a top portion, a center portion and a bottom portion, the first and second longitudinal pipe members being disposed vertically. The frame includes top, center and bottom rails attached to, respectively, to the top portion, the center portion and the bottom portion. The frame includes a front side and a rear side. Longitudinal plate members are attached to the first and second longitudinal pipe members between the top rail and the center rail and between the center rail and the bottom rail, the longitudinal plate members facing the front side and the rear side of the frame, the longitudinal plate members being disposed vertically along the first and second longitudinal pipe members. A radio plate is removably attached to and positionable along the longitudinal plate members between the top rail and the center rail; and a filter plate removably attached to and positionable along the longitudinal members between the center rail and the bottom rail. |
| US09722294B2 |
Antenna structure and wireless communication device using the same
An antenna structure includes a feed end, a first ground end, a first antenna, a second ground end, a second antenna, and a holder. The first antenna is connected to the feed end and the first ground end. The second antenna is a parasitic antenna, the second antenna is connected to the second ground end, and is opposite to the first antenna. The holder is connected between the first antenna and a second antenna. |
| US09722287B2 |
Frame for secondary battery including cooling plate and main frame having unit frame horizontally spaced apart and battery module including the same
Disclosed is a frame for a secondary battery, which has an improved structure to prevent a cooling plate from being deformed or distorted due to shrinkage of a main frame. The frame for a secondary battery includes a cooling plate made of a thermally conductive material with a plate shape, and a main frame having a plurality of unit frames spaced apart from each other in a horizontal direction by a predetermined distance, the main frame being configured to surround a rim of the cooling plate and made of a material different from the cooling plate. |
| US09722284B2 |
Nonaqueous secondary battery and battery control system
A nonaqueous secondary battery includes an ion supply unit which supplies ions identical to ions in an electrolyte into the electrolyte at a reaction potential higher than the uncharged potential of a positive electrode. The ion supply unit includes an ion supply source which elutes the ions into the electrolyte by being in contact with the electrolyte in a state of being electrically connected to the positive electrode, and a first covering portion which covers at least a part of the ion supply source. Then, the first covering portion maintains the ion supply source and the positive electrode in an electrically disconnected state by being interposed between the ion supply source and the positive electrode, and is dissolved or disappears at the reaction potential. |
| US09722282B2 |
Method and device for setting a maximum depth of discharge of an energy store for a time period
A method and apparatus for setting a maximum depth of discharge of an energy reservoir for a time period. The method includes: defining a first target aging value of the energy reservoir for a first time period; determining a first aging value that describes an aging of the energy reservoir during the first period; calculating a first difference between the first target aging value of the energy reservoir and the first aging value of the energy reservoir; defining a second target aging value of the energy reservoir for a second time period; calculating a maximum aging value of the energy reservoir for the second time period, based on the second target aging value and at least the first difference; calculating a maximum depth-of-discharge value based on the maximum aging value; setting the maximum depth of discharge of the energy reservoir for the second time period to the maximum depth-of-discharge value. |
| US09722275B2 |
Anode protective layer compositions for lithium metal batteries
The present invention provides a battery cell, comprising: (a) an anode comprising an active metal or a metal ion storage material (e.g., an intercalation compound that accommodates lithium ion); (b) a cathode structure; and (c) an ionically conductive protective layer on a surface of the anode and interposed between the anode and the cathode structure. This protective layer comprises a porous membrane having pores therein and a soft matter phase disposed in at least one of the pores, wherein the soft matter phase comprises oxide particles dispersed in a non-aqueous alkali, alkaline, or transition metal salt solution. Most preferably, this battery cell is a lithium metal secondary cell that is essentially free from dendrite and exhibits a safer and more stable cycling behavior. Such a high-capacity rechargeable battery is particularly useful for powering portable electronic devices and electric vehicles. |
| US09722274B2 |
Manufacturing method and manufacturing device of secondary battery
A manufacturing method of a secondary battery includes a first sealing process that stores a power generation element inside an exterior body formed by overlapped exterior films and that seals the exterior body at a first sealing part, the power generation element being arranged with a space from at least a part of the first sealing part, a conditioning process that performs conditioning, an hole forming process that forms a degassing hole between the first sealing part and the power generation element, and a second sealing process that seals the degassing hole, in which the hole forming process includes a pressing process that presses, from both sides of the exterior body, a portion where the degassing hole is formed in the exterior body so that the overlapped exterior films are brought into contact with each other, before the degassing hole is formed in the exterior body. |
| US09722268B2 |
Gas generator with starter mechanism and catalyst shield
The present application is directed to gas generators comprising a fuel mixture and a catalyst. The catalyst is contained in a self-regulated reactor or buoy, and selectively opens and closes to produce a gas in accordance with the demand for gas. This fuel mixture is generally a solution formed by dissolving a solid fuel component in a liquid fuel component. The mixing preferably occurs before the first use, and more preferably occurs immediately prior to the first use. The inventive gas generators preferably further comprises a starting mechanism that isolates the solid fuel from the liquid fuel or vice versa before the first use. In one embodiment, the starting mechanism further comprises a catalyst shield mechanism that isolates the catalyst in the reactor or buoy from the liquid and/or the solid fuel prior to the first use. |
| US09722266B2 |
Method for controlling temperature of fuel cell system
The present invention provides a method for controlling the temperature of a fuel cell system by controlling the rotational speeds of a coolant pump and a cooling fan based on the coolant outlet temperature, the amount of heat generated by a fuel cell stack, etc. In particular, the present invention controls the temperature of a fuel cell system by utilizing a controller which receives a coolant outlet temperature from a sensor in a state where a reference temperature for each stage is determined with respect to the coolant outlet temperature and a target rotational speed for each stage is determined based on the coolant outlet temperature. Then the controller performs proportional integral (PI) control with respect to each rotational speed of a coolant pump and a cooling fan at the target rotational speed for each stage determined based on the current coolant outlet temperature detected by the water temperature sensor. |
| US09722262B2 |
Fuel cell stack for preventing deterioration of end cell
A fuel cell stack preventing deterioration of an end cell, which has a structure for preventing cooling of a neighbor cell adjacent to a closed end plate, is provided. To this end, an open end plate and a closed end plate, which are provided on a first side and a second side, respectively, of the fuel cell stack, fasten a plurality of working cells together. More specifically, a hollow flow space is formed in an inner wall of the closed end plate to form an air pocket therein. |
| US09722260B2 |
Fuel cell ion exchanger and fuel cell system
An ion exchanger includes a lower casing, an upper casing, and a cartridge. The lower casing includes an upper opening and a circumferential wall, which includes an intake port and a discharge port. The upper casing includes a lid, which is arranged on the opening of the lower casing, and a cylinder, which extends downward from the lid and is accommodated in the circumferential wall. The cartridge, which is provided integrally with the inner side of the cylinder, accommodates an ion exchange resin. The cylinder includes a communication hole, through which the inner side of the cylinder is in communication with the intake port. The upper casing includes an accumulation limiting structure that limits the air remaining immediately below the lower surface of the lid in the upper casing after flowing into the cylinder together with coolant. |
| US09722258B2 |
Method of direct resistance welding—self brazing of aluminum to molybdenum pin
A direct welding process for joining a current collector to a terminal pin in the construction of electrochemical cells is described. The resistance welding process utilizes increased current combined with an applied force to bond dissimilar metals with a melting temperature differential of preferably more than 500° C. Preferably, the method is used to bond the terminal pin to the cathode current collector. This method of attachment is suitable for either primary or secondary cells, particularly those powering implantable biomedical devices. |
| US09722256B1 |
Imidazole-derived materials
In the present disclosure, imidazole-derived materials including M-N—C catalysts, imidazole-derived MOFs and MOF-based M-N—C catalysts as well as methods for preparing the same utilizing mechanochemical synthesis and/or a sacrificial support-based methods are described. |
| US09722252B2 |
Electronically conductive polymer binder for lithium-ion battery electrode
A family of carboxylic acid groups containing fluorene/fluorenon copolymers is disclosed as binders of silicon particles in the fabrication of negative electrodes for use with lithium ion batteries. Triethyleneoxide side chains provide improved adhesion to materials such as, graphite, silicon, silicon alloy, tin, tin alloy. These binders enable the use of silicon as an electrode material as they significantly improve the cycle-ability of silicon by preventing electrode degradation over time. In particular, these polymers, which become conductive on first charge, bind to the silicon particles of the electrode, are flexible so as to better accommodate the expansion and contraction of the electrode during charge/discharge, and being conductive promote the flow battery current. |
| US09722245B2 |
Sulfur-carbon nanocomposites and their application as cathode materials in lithium-sulfur batteries
The invention is directed in a first aspect to a sulfur-carbon composite material comprising: (i) a bimodal porous carbon component containing therein a first mode of pores which are mesopores, and a second mode of pores which are micropores; and (ii) elemental sulfur contained in at least a portion of said micropores. The invention is also directed to the aforesaid sulfur-carbon composite as a layer on a current collector material; a lithium ion battery containing the sulfur-carbon composite in a cathode therein; as well as a method for preparing the sulfur-composite material. |
| US09722243B2 |
Negative active material for secondary battery and secondary battery using the same
The present invention provides a negative active material for a secondary battery with an improved expansion rate, which is formed by a formula below, and in which an expansion rate of the negative active material after 50 cycles is 70 to 150%, and an amorphization degree on a matrix within an alloy has a range of 25% or more, and Si has a range of 60 to 70%, Ti has a range of 9 to 14%, Fe has a range of 9 to 14%, and Al has a range larger than 1% and less than 20%. Formula: SixTiyFezAlu (x, y, z, and u are at %, x: 1−(y+z+u)). |
| US09722242B2 |
Hollow silicon-based particle, preparation method thereof and anode active material for lithium secondary battery including the same
A hollow silicon-based particle including silicon (Si) or silicon oxide (SiOx, 0 |
| US09722237B2 |
Secondary battery
A secondary battery having improved safety includes an electrode assembly, a case, and a cap assembly. The electrode assembly has first and second non-coating portions. The case accommodates the electrode assembly. The cap assembly includes a cap plate coupled to the case, and first and second collector plates. In the secondary battery, the first and second non-coating portions and the first and second collector plates are connected or coupled by first and second lead tabs, respectively, and the first and/or second lead tabs include a fuse portion. |
| US09722234B2 |
Secondary battery including cap plate comprising reinforcing element
A secondary battery, which can improve safety during a longitudinal compression test by reinforcing strength of a cap plate, is provided. In one embodiment, the secondary battery includes an electrode assembly, a can accommodating the electrode assembly, and cap plate coupled to a top portion of the can and sealing the can, wherein a reinforcement unit is formed on at least one side of the cap plate. |
| US09722230B2 |
Battery pack and vehicle provided with same
A battery pack includes a single cell having a cylindrical shape, the single cell having a positive electrode at one end of the single cell and a negative electrode at the other end of the single cell, a plurality of the single cells being arranged in a radial direction of the single cell; a fuse; a first bus bar connected via the fuse to one electrode, from among the positive electrode and the negative electrode; a second bus bar directly connected to the other electrode, from among the positive electrode and the negative electrode; and a retaining member configured to retain the plurality of single cells from the radial direction of the single cell, in a manner such that when the fuse is disconnected, retaining force with which the single cell is retained by the retaining member decreases and the single cell moves in a direction away from the fuse. |
| US09722228B2 |
Electrical connecting member for secondary battery
Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. |
| US09722226B2 |
Polyolefin microporous membrane and separator for nonaqueous electrolyte battery
The present invention provides a polyolefin microporous membrane made of a polyolefin resin and an inorganic particle, and the puncture strength of the microporous membrane is 3 N/20 μm or more and the membrane thickness retention ratio in penetration creep is 16% or more, thereby being excellent in safety and long-term reliability, and a separator for a nonaqueous electrolyte battery, and the like can be provided. |
| US09722225B2 |
Polyolefin microporous membrane and separator for nonaqueous electrolyte battery
The present invention provides a polyolefin microporous membrane made of a polyolefin resin and an inorganic particle, and the puncture strength of the microporous membrane is 3 N/20 μm or more and the membrane thickness retention ratio in penetration creep is 16% or more, thereby being excellent in safety and long-term reliability, and a separator for a nonaqueous electrolyte battery, and the like can be provided. |
| US09722219B2 |
Battery, assembled battery, and mounting device
A battery includes a bottomed case of box shape housing a power-generating element, a lid component for the case, a terminal electrode provided outside the case and extending in the direction of the thickness of the lid component, a take-out electrode passing through the lid component, provided for taking out an electric power of the power-generating element to the outside of the case, and disposed at a position different from that of the terminal electrode within a plane including the lid component, and a connecting member connecting the terminal electrode and the take-out electrode and including a thinner portion allowing bending of the connecting member in response to an external force applied to the terminal electrode in the direction of the thickness of the lid component. |
| US09722217B2 |
Pouch type battery cell
A pouch type battery cell includes an electrode assembly having a first electrode plate, a second electrode plate, and a separator located between the first and second electrode plates; a first case having a first accommodating portion in which at least one portion of the electrode assembly is accommodated, wherein the first accommodating portion is generally concave; and a second case covering the first case, wherein the first case includes a metal layer including steel or hard aluminum, and wherein a depth of the first accommodating portion is between about 1 mm and about 4 mm, and wherein a thickness of the metal layer is between about 40 μm and about 100 μm. |
| US09722216B2 |
Energy storage device and method
An energy storage device that includes a housing, which includes at least one end panel that includes at least one aperture therethrough. The device further includes a battery cell housed in the housing. The battery cell includes mutually opposed first and second faces joined at their edges. The device also includes a heat sink adjacent to the battery cell and in thermal contact with the first face of the battery cell. The heat sink defines at least one cooling medium passage extending parallel to the face of the adjacent battery cell. The cooling medium passage opens onto the at least one aperture formed through the at least one end panel of the housing. |
| US09722215B2 |
Cylindrical battery
A battery includes a cylindrical battery case and an electrode group including a positive electrode, a negative electrode, and a separator. The electrode group and the battery case define a space communicated from a top to a bottom, and one of the positive electrode and the negative electrode has a current collecting terminal that extends from the electrode group in a direction away from a center axis of the battery case and is in contact with a bottom surface of the battery case. |
| US09722210B2 |
OLED light emitting device and display device
An OLED light emitting device and a display device are provided. The OLED light emitting device has a cathode, a light-emitting layer, an anode, a substrate, and a light extraction layer; the light extraction layer at least has a first material layer and a second material layer; a first contact surface of the first material layer and a second contact surface of the second material layer contact each other; a longitudinal section of the first contact surface and that of the second contact surface have sawtooth portions fitted with each other; nA>nsubstrate>nB. |
| US09722209B2 |
Organic light-emitting diodes (OLEDS) with high efficiency and its manufacturing method
The present invention relates to an organic light emitting device that has a structure which is capable of maximally extracting light generated in the organic light emitting device to the outside. In detail, the organic light emitting device according to the present invention is characterized in that the organic light emitting device includes a high refractive index layer or an electrode that includes a light reuse pattern. |
| US09722207B2 |
Organic light-emitting display device
Provided is a display device, including two light-emitting elements having different turn-on voltages. Each of the light-emitting elements includes a patterned electrode, a common layer, a patterned light-emitting layer, and a common electrode. The light-emitting element with the lower turn-on voltage among the two light-emitting elements includes a functional layer which suppresses a hole from being leaked from the light-emitting layer with the higher turn-on voltage through the common layer when the light-emitting element with the higher turn-on voltage among the two light-emitting elements is driven at a low gray scale to move into the patterned light-emitting layer of the light-emitting element with the lower turn-on voltage. Therefore, the light emission of an undesired pixel due to the leakage current is reduced, thereby improving the display quality. |
| US09722206B2 |
Display device and apparatus and method for manufacturing the same
A display device and an apparatus and method for manufacturing the same are disclosed. The display device includes: a substrate; a display unit formed on the substrate; and an inorganic layer formed on the display unit, wherein a water vapor transmission rate (WVTR) of the inorganic layer is 5×10−5 g/m2 day or less. The apparatus for manufacturing a display device includes: a chamber; a shower head for spraying a mixed gas into the chamber; a plasma generation unit for forming plasma from the mixed gas; a susceptor facing the shower head and on which a substrate is seated; and a power supply unit electrically connected to the plasma generation unit, wherein a frequency of a current supplied from the power supply unit to the plasma generation unit is between about 27 MHz and about 42 MHz. |
| US09722202B2 |
Display apparatus having auxiliary line and method for manufacturing the same
Display apparatus, including a substrate; a pixel electrode on the substrate and corresponding to a pixel; an auxiliary line on the substrate and insulated from the pixel electrode; an insulation layer on the pixel electrode and the auxiliary line, the insulation layer covering at least a portion of the pixel electrode and at least a portion of the auxiliary line; an organic light emitting layer on the pixel electrode, the auxiliary line, and the insulation layer; a first electrode on the organic light emitting layer and overlapping at least a portion of the auxiliary line; an opening in each of the organic light emitting layer and the first electrode to correspond to the auxiliary line; and a second electrode on the first electrode and an exposed portion of the auxiliary line, the second electrode electrically connecting the auxiliary line to the first electrode, the exposed portion of the auxiliary line being exposed by the opening. |
| US09722198B2 |
Nanoparticle material and light-emitting device
A light-emitting device having a first light-emitting layer with a first quantum dot having a first core part and a first shell part. The first shell part has a surface coated with a surfactant, and the first shell part has a thickness of 3 to 5 ML based on the constituent molecule of the first shell part. The light-emitting device also can have second light-emitting layer with a second quantum dot having a second core part and a second shell part. The second shell part has a surface coated with two types of hole-transporting and electron-transporting surfactants, and the second shell part has a thickness of less than 3 ML based on the constituent molecule of the second shell part. |
| US09722196B2 |
Method for producing an organic field effect transistor and an organic field effect transistor
Methods for producing organic field effect transistors, organic field effect transistors, and electronic switching devices are provided. The methods may include providing a gate electrode and a gate insulator assigned to the gate electrode for electrical insulation on a substrate, depositing a first organic semiconducting layer on the gate insulator, generating a first electrode and an electrode insulator assigned to the first electrode for electrical insulation on the first organic semiconducting layer, depositing a second organic semiconducting layer on the first organic semiconducting layer and the electrode insulator, and generating a second electrode on the second organic semiconducting layer. |
| US09722187B2 |
Compound and organic light-emitting device including the same
A compound, an organic light-emitting device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, and including and emission layer, where the organic layer includes at least one compound represented by Formula 1, and a display apparatus, the compound being represented by Formula 1 below: |
| US09722184B2 |
Thiadiazole, compound for light-emitting elements, light-emitting element, light-emitting apparatus, authentication apparatus, and electronic device
A thiadiazole contains a basic skeleton represented by any of formulae (1), (2), and (3) in the molecule. |
| US09722182B2 |
Heterocyclic compound and organic light-emitting device including the same
A heterocyclic compound represented by Formula 1 below, and an organic light-emitting device including the heterocyclic compound: |
| US09722181B2 |
Laminate having organic mask and method for manufacturing organic electroluminescent device using same
Provided are a laminate including an organic material mask and a method for preparing an organic light emitting device using the same. The laminate includes a substrate; and a mask provided on the substrate and including an organic material. |
| US09722180B2 |
Mask-stack-shift method to fabricate organic solar array by spray
An all-spray fabrication method for large scale inverted organic solar array is provided. Zinc oxide sol gel solutions and revised layers shorten the fabrication process from 2 days to 5 hours and concurrently improve transparency and visual effect of solar windows, and improve power conversion efficiency over 2× compared to previous devices, due to enhanced device characteristics like increased shunt resistance and fill factor. The method also eliminates human factors such as manual erasing of active layer to make series connections by providing a complete solution processable manufacturing process. The semi-transparency of the solar module allows for applications on windows and windshields. The inventive modules are more efficient than silicon solar cells in artificial light environments, significantly expanding their use in indoor applications. Additionally, these modules can be integrated into soft fabrics such as tents, military back-packs or combat uniforms, providing a highly portable renewable power supply for deployed military forces. |
| US09722177B2 |
Resistive random access memory device with a solid electrolyte including a region made of a first metal oxide and doped by a second element distinct from the first metal
A resistive random access memory device includes a first electrode made of inert material; a second electrode made of soluble material; a solid electrolyte including a region made of an oxide of a first metal element, referred to as first metal oxide doped by a second element, distinct from the first metal and able to form a second oxide, the second element being selected such that the band gap energy of the second oxide is strictly greater than the band gap energy of the first metal oxide, the atomic percentage of the second element within the region of the solid electrolyte being comprised between 5% and 20%. |
| US09722175B2 |
Single-chip bridge-type magnetic field sensor and preparation method thereof
The present invention discloses a design and manufacturing method for a single-chip magnetic sensor bridge. The sensor bridge comprises four magnetoresistive elements. The magnetization of the pinned layer of each of the four magnetoresistive elements is set in the same direction, but the magnetization directions of the free layers of the magnetoresistive elements on adjacent arms of the bridge are set at different angles with respect to the pinned layer magnetization direction. The absolute values of the angles of the magnetization directions of the free layers of all four magnetoresistive elements are the same with respect with their pinning layers. The disclosed magnetic biasing scheme enables the integration of a push-pull Wheatstone bridge magnetic field sensor on a single chip with better performance, lower cost, and easier manufacturability than conventional magnetoresistive sensor designs. |
| US09722170B2 |
Piezoelectric material, piezoelectric element, and electronic device
There is provided a piezoelectric material not containing any lead component, having stable piezoelectric characteristics in an operating temperature range, a high mechanical quality factor, and satisfactory piezoelectric characteristics. The piezoelectric material includes a main component containing a perovskite-type metal oxide that can be expressed using the following general formula (1), and subcomponents containing Mn, Li, and Bi. When the metal oxide is 100 parts by weight, the content of Mn on a metal basis is not less than 0.04 parts by weight and is not greater than 0.36 parts by weight, content α of Li on a metal basis is not less than 0.0013 parts by weight and is not greater than 0.0280 parts by weight, and content β of Bi on a metal basis is not less than 0.042 parts by weight and is not greater than 0.850 parts by weight (Ba1-xCax)a(Ti1-y-zZrySnz)O3 (1) (in the formula (1), 0.09≦x≦0.30, 0.074 |
| US09722169B1 |
Thin-film piezoelectric material element, head gimbal assembly and hard disk drive
A thin-film piezoelectric material element includes a laminated structure part having a lower electrode film, a piezoelectric material film laminated on the lower electrode film and an upper electrode film laminated on the piezoelectric material film. The thin-film piezoelectric material element includes a surface layer insulating film disposed on side surfaces of the laminated structure part, a first top surface of the upper electrode film and a second top surface of the lower electrode film, and has a first through hole formed on a first top disposed part and a second through hole formed on a second top disposed part. Further, the surface layer insulating film has an upper electrode pad being in directly contact with a first inside exposed surface and a lower electrode pad being in directly contact with a second inside exposed surface. |
| US09722153B2 |
Light-emitting device and method of manufacturing same
A light-emitting device includes a substrate; a light-emitting element mounted on the substrate; a first light-transmissive member bonded to an upper surface of the light-emitting element via an adhesive; and a second light-transmissive member placed on an upper surface of the first light-transmissive member. In a plan view of the light-emitting device, a peripheral edge of a lower surface of the first light-transmissive member is positioned more inward than a peripheral edge of the upper surface of the light-emitting element. The adhesive extends from the upper surface of the light-emitting element to a lower surface of the second light-transmissive member, the adhesive covers a side surface of the first light-transmissive member, and the adhesive is separated from the substrate. |
| US09722146B2 |
Phosphor film, method of manufacturing the same, coating method of phosphor layer, method of manufacturing LED package and LED package manufactured thereby
There are provided a phosphor film, a method of manufacturing the same, and a method of coating an LED chip with a phosphor layer. The phosphor film includes: a base film; a phosphor layer formed on the base film and obtained by mixing phosphor particles in a partially cured resin material; and a cover film formed on the phosphor layer to protect the phosphor layer. |
| US09722145B2 |
Light emitting device and fluidic manufacture thereof
Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively. |
| US09722141B2 |
Optoelectronic semiconductor element, optoelectronic semiconductor device and method for producing a plurality of optoelectronic semiconductor elements
An optoelectronic semiconductor element may include at least one LED chip which emits infrared radiation via a top side during operation. The radiation has a global intensity maximum at wavelengths between 800 nm and 1100 nm. The radiation has, at most 5% of the intensity of the intensity maximum at a limit wavelength of 750 nm. The radiation has a visible red light component. The semiconductor element may further include a filter element, which is arranged directly or indirectly on the top side of the LED chip and which has a transmissivity of at most 5% for the visible red light component of the LED chip, wherein the transmissivity of the filter element is at least 80%, at least in part, for wavelengths between the limit wavelength and 1100 nm, and a radiation exit surface provided for emitting the filtered radiation. |
| US09722137B2 |
LED having vertical contacts redistributed for flip chip mounting
A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described. |
| US09722129B2 |
Complementary traveling masks
A method of processing a solar cell is disclosed, where a chained patterned ion implant is performed to create a workpiece having a lightly doped surface having more heavily doped regions. This configuration may be used in various embodiments, such as for selective emitter solar cells. Additionally, various mask sets that can be used to create this desired pattern are also disclosed. The mask set may include one or more masks that have an open portion and a patterned portion, where the union of the open portions of the masks comprises the entirety of the surface to be implanted. The patterned portions of the masks combine to create the desired pattern of heavily doped regions. |
| US09722127B2 |
Photocoupler having light receiving element, light emitting element and MOSFET on a die pad unit of a mounting member that includes terminals with multiplied conductive regions
A mounting member includes: an insulating substrate, a first die pad unit, first and second terminals. The insulating substrate has a rectangular first surface, a second surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A through hole is provided from the first surface to the second surface. The first die pad unit is provided on the first surface. The first terminal has a conductive region covering the first side surface, the first surface, and the second surface. The second terminal has a conductive region covering the second side surface and the second surface, connected to the first die pad unit by conductive material provided in the through hole or on a side wall of the through hole. The first die pad unit, the first terminal, and the second terminal are apart from one another. |
| US09722126B2 |
Photoconductive device, measurement apparatus, and manufacturing method
A photoconductive device that generates or detects terahertz radiation includes a semiconductor layer; a structure portion; and an electrode. The semiconductor layer has a thickness no less than a first propagation distance and no greater than a second propagation distance, the first propagation distance being a distance that the surface plasmon wave propagates through the semiconductor layer in a perpendicular direction of an interface between the semiconductor layer and the structure portion until an electric field intensity of the surface plasmon wave becomes 1/e times the electric field intensity of the surface plasmon wave at the interface, the second propagation distance being a distance that a terahertz wave having an optical phonon absorption frequency of the semiconductor layer propagates through the semiconductor layer in the perpendicular direction until an electric field intensity of the terahertz wave becomes 1/e2 times the electric field intensity of the terahertz wave at the interface. |
| US09722125B1 |
Radiation sensor, method of forming the sensor and device including the sensor
A radiation sensor includes a fin structure including semiconductor material formed on a substrate, a gate formed on an inner side of the fin structure, and a charge collector dielectric layer formed on an outer side of the fin structure. |
| US09722123B2 |
Solar cell
A solar cell of an embodiment has a first solar cell, a second solar cell, and an intermediate layer between the first and second solar cells. The first solar cell has a Si layer as a light absorbing layer. The second solar cell has as a light absorbing layer one of a group I-III-VI2 compound layer and a group I2-II-IV-VI4 compound layer. The intermediate layer has an n+-type Si sublayer and at least one selected from a p+-type Si sublayer, a metal compound sublayer, and a graphene sublayer. The metal compound sublayer is represented by MX where M denotes at least one type of element selected from Nb, Mo, Pd, Ta, W, and Pt and X denotes at least one type of element selected from S, Se, and Te. |
| US09722115B2 |
Solar cell encapsulating module and method for manufacturing the same
The disclosure provides a solar cell encapsulating module including a first substrate, a first encapsulating material layer, a metal particle layer, multiple solar cells, a routing layer, a second encapsulating material layer and a second substrate. The first substrate is formed from a light transmittance material. The first encapsulating material layer is formed on the first substrate. The metal particle layer is formed on the first encapsulating material layer. The solar cells are disposed on the metal particle layer. The routing layer is disposed on the solar cells for being electrically connected to the plurality of solar cells. The second encapsulating material layer is formed on the routing layer. The second substrate is disposed on the second encapsulating material layer. The routing layer is disposed on only one side of the solar cells. |
| US09722110B2 |
Plasmonic graphene and method of making the same
Plasmonic graphene is fabricated using thermally assisted self-assembly of plasmonic nanostructure on graphene. Silver nanostructures were deposited on graphene as an example. |
| US09722109B2 |
Image sensor device and method
A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. |
| US09722098B1 |
Semiconductor device package and method of manufacturing the same
A method of manufacturing a semiconductor device package includes disposing at least one die over a substrate, dispensing a liquid material on the die, and curing the liquid material so that the liquid material forms a protective layer attached to a portion of the die. The method further includes forming an encapsulant covering at least a portion of the substrate and a portion of the die, where the protective layer is exposed from the encapsulant in a cavity defined by the encapsulant. The method further includes removing the protective layer from the die, and disposing a cap over the cavity. |
| US09722096B2 |
Method of manufacturing semiconductor device
A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired. |
| US09722095B2 |
Semiconductor device and display device including the semiconductor device
A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations. The gate electrode, the source electrode, and the drain electrode contain the same metal element. |
| US09722093B1 |
Oxide semiconductor transistor and manufacturing method thereof
An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor. |
| US09722085B2 |
Electronic device and method of manufacturing the same
A transistor includes a channel layer in which a plurality of graphene whose edge portions are terminated with modifying groups different from each other are bonded to each other; a gate electrode formed on the channel layer via a gate insulating film; and a source electrode and a drain electrode formed on the channel layer. |
| US09722083B2 |
Source/drain junction formation
An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium. |
| US09722080B2 |
Semiconductor device
The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines. |
| US09722079B2 |
Fin-type field effect transistor structure and manufacturing method thereof
A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack. |
| US09722073B2 |
Lateral super-junction MOSFET device and termination structure
A lateral superjunction MOSFET device includes a gate structure and a first column connected to the lateral superjunction structure. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the lateral superjunction MOSFET device further includes termination structures for the drain, source and body contact doped region fingers. |
| US09722072B2 |
Manufacturing method of high-voltage metal-oxide-semiconductor transistor
A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure. |
| US09722070B2 |
Methods of manufacturing trench semiconductor devices with edge termination structures
Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example. |
| US09722069B2 |
Vertical DMOS transistor
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor. |
| US09722068B2 |
Semiconductor devices and methods of manufacturing the same
Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor. |
| US09722067B2 |
Semiconductor device
A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film. |
| US09722064B2 |
Isolated gate field effect transistor and manufacture method thereof
An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions. |
| US09722063B1 |
Protective insulator for HFET devices
A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode. |
| US09722058B2 |
Bipolar transistor having collector with doping spike
This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. |
| US09722056B2 |
Method for manufacturing semiconductor device
A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device. |
| US09722054B2 |
Semiconductor device and method for manufacturing the same
An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized. |
| US09722048B1 |
Vertical transistors with reduced bottom electrode series resistance
A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped semiconductor layer, and a second doped semiconductor layer arranged on the layer of metal; a channel extending from the second doped semiconductor layer to a drain including an epitaxial growth; a gate disposed on sidewalls of the channel between the second doped semiconductor layer and the drain; an interlayer dielectric (ILD) disposed on the second doped semiconductor layer and the gate; and a source contact extending from a surface of the ILD to abut the layer of metal of the source. |
| US09722045B2 |
Buffer layer for modulating Vt across devices
The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness. |
| US09722043B2 |
Self-aligned trench silicide process for preventing gate contact to silicide shorts
A method of forming a finFET device includes forming a plurality of fins on a substrate; forming a plurality of dummy gate structures over the plurality of fins, the dummy gate structures including gate sidewall spacers; performing an epitaxial growth process to merge the plurality of fins at locations not covered by the dummy gate structures; forming an interlevel dielectric (ILD) layer over the dummy gate structures and merged fins, the ILD layer comprising a first dielectric material; removing portions of the ILD layer and the merged fins so as to define trenches; and filling the trenches with a second dielectric material having an etch selectivity with respect to the first dielectric material, and wherein the gate sidewall spacers also comprise the second dielectric material such that regions of the merged fins in active areas are surrounded by the second dielectric material. |
| US09722042B2 |
Group-III nitride semiconductor device and method for fabricating the same
The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride. |
| US09722038B2 |
Metal cap protection layer for gate and contact metallization
A CMOS fabrication process provides metal gates and contact metallization protected by metal cap layers resistant to reagents employed in downstream processing. Cobalt gates and contact metallization are accordingly feasible in CMOS processing requiring downstream wet cleans and etch processes that would otherwise compromise or destroy them. Low resistivity metal cap materials can be employed. |
| US09722036B2 |
Semiconductor device with field electrode structure
According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm. |
| US09722030B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material. |
| US09722027B2 |
Silicon carbide semiconductor device and method for manufacturing the same
A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type. |
| US09722016B2 |
Semiconductor device and method for producing semiconductor device
Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n− drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n− drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer. |
| US09722007B2 |
Light emitting display device
Provided is a light emitting display device.The emitting display device comprises: a substrate including a plurality of pixels which are arranged in a first direction and a second direction that crosses the first direction, the plurality of pixels comprising a first main pixel block and a second main pixel block; a planarization pattern arranged on the substrate; a first electrode on the planarization pattern for each of the plurality of pixels; a pixel defining layer partitioning the respective pixels on the substrate and having an opening for exposing the first electrode; an organic layer on the first electrode; and a second electrode on the organic layer, wherein a thickness of the planarization pattern of the pixel in the second main pixel block is larger than a thickness of the planarization pattern of the pixel in the first main pixel block. |
| US09722006B2 |
Organic light-emitting device and method for producing same
An organic light-emitting device includes at least an underlayer, a partition wall, and an organic film. The underlayer is disposed above a substrate. The partition wall covers a first part and surrounds a second part of the surface of the underlayer. The organic film includes organic material, is disposed in a recess formed by the partition wall surrounding the second part, and is in contact with the surface of the underlayer and a surface of the partition wall. The surface of the underlayer has a protruding portion that protrudes in an upward direction. The protruding portion is composed of a top surface and an inclined surface surrounding the top surface. The first part includes least the top surface and a portion of the inclined surface, and an inner edge of the partition wall is in contact with the inclined surface or a level portion of the surface of the underlayer. |
| US09722004B2 |
Package method of substrate and package structure
A package structure includes a substrate and a package plate. A frame is formed of a seal glue arranged between the substrate and the package plate. An underfill is positioned inboard of the frame. The package plate has a spreading surface, and at least one groove is formed in a spreading path of the frame on the spreading surface of the package plate. |
| US09722003B2 |
Bottom emission organic electroluminescence display device, preparation method thereof, and display apparatus
A bottom emission organic electroluminescence display, a preparation method thereof, and a display apparatus are provided. The display includes a base substrate (100), and at least one dielectric thin film layer group (200) and a thin film transistor (300) that are successively arranged on the base substrate; each dielectric thin film layer group (200) comprising at least two stacked dielectric thin film layers (201, 202, 203), the refractive indices of which are increased progressively from the base substrate towards the thin film transistor. Because at least one group of at least two stacked dielectric thin film layers, the refractive indices of which are increased progressively from the base substrate towards the thin film transistor, are added between the base substrate and the thin film transistor, not only the reflectance of the surface of the metal layers contained in the thin film transistor (300) may be decreased, but also the loss rate of the emitted light may be decreased, thereby improving the image quality and display effect. |
| US09721996B2 |
Display device
A display device includes a display unit in which pixels are arranged in a matrix. The pixels each include a first sub-pixel having the largest area among sub-pixels, a second sub-pixel adjacent to the first sub-pixel and having an area smaller than that of the first sub-pixel, and a third sub-pixel adjacent to the first and second sub-pixels, having an area smaller than that of the first sub-pixel, and arranged in the same column as that of second sub-pixels. First, second, and third pixels are aligned in at least one of a column direction or a row direction and each include the first, second, and third sub-pixels that can display different one of first, second, and third colors. Areas of the first, second, and third colors displayable by the first, second, and third pixels in total are equal to one another. |
| US09721994B2 |
Semiconductor device and imaging device for reading charge
According to an embodiment, a semiconductor device includes a silicon substrate, a photoelectric conversion layer, a termination layer, and an electrode layer. In the silicon substrate, first semiconductor regions and second semiconductor regions are alternately arranged along a first surface on a light incident side of the silicon substrate. The first semiconductor regions are doped with impurities of first concentration and have a conductivity of either one of p-type and n-type. The second semiconductor regions are doped with impurities of a second concentration lower than the first concentration and have a conductivity of the other type. The photoelectric conversion layer is disposed on a first surface side of the silicon substrate. The termination layer is disposed between the silicon substrate and the photoelectric conversion layer, in contact with the first surface, and to terminate dangling bonds of the silicon substrate. The electrode layer is provided on the light incident side. |
| US09721993B2 |
Method for operating an organic optoelectronic component
A method is specified for operating an organic optoelectronic component, which has at least one organic light-emitting element having an organic functional layer stack with at least one organic light-emitting layer between two electrodes and at least one organic light-emitting element having an organic light-detecting layer. These elements are arranged on a common substrate in laterally adjacent area regions. The at least one organic light-detecting element detects ambient light, which is incident onto the organic optoelectronic component. The intensity of the light emitted by the at least one organic light-emitting element is regulated depending on a signal of the at least one organic light-detecting element with a characteristic signal form. |
| US09721991B2 |
Organic optoelectronic component and method for operating the organic optoelectronic component
An organic optoelectronic component and a method for operating the organic optoelectronic component are disclosed. In an embodiment the organic optoelectronic component includes at least one organic light emitting element including an organic functional layer stack having at least one organic light emitting layer between two electrodes and at least one organic light detecting element including at least one organic light detecting layer, wherein the at least one organic light detecting element and the at least one organic light emitting element are laterally arranged on a common substrate. |
| US09721990B2 |
Magnetic tunnel junction and 3-D magnetic tunnel junction array
A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped. |
| US09721989B2 |
Image sensors including conductive pixel separation structures and methods of fabricating the same
An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed. |
| US09721986B2 |
Image-capturing unit including chips, substrates, and a connecting section
Provided is an image-capturing unit including an image-capturing chip that includes a first surface having a pixel and a second surface that is on an opposite side of the first surface and has provided thereon an output section that outputs a pixel signal read from the pixel; a transparent substrate that is arranged facing the first surface and includes a wire pattern; a mounting substrate that is arranged facing the second surface and supports the image-capturing chip; and a relay section that is arranged on the mounting substrate and relays, to the wire pattern, the pixel signal output from the output section. Also provided is an image-capturing apparatus including the image-capturing unit described above. |
| US09721985B2 |
Solid-state imaging device, method of manufacturing the same, and electronic equipment
A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film. |
| US09721984B2 |
Image sensor manufacturing methods
Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process. |
| US09721980B2 |
MOS-transistor structure as light sensor
Described is an arrangement for registering light, comprising: a MOS-transistor structure having a first source/drain region, a second source/drain region, and a bulk region at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region charge carriers are generated in dependence of light impinging on the bulk region, wherein the generated charge carriers control a current flowing from the first source/drain region to the second source/drain region via at least a portion of the bulk region. |
| US09721977B2 |
Display device and electronic unit
A display device includes a substrate, a display element, a transistor as a drive element of the display element, and a holding capacitance element holding electric charge corresponding to a video signal, and including a first conductive film, a first semiconductor layer including an oxide semiconductor, an insulating film, and a second conductive film in order of closeness to the substrate. The display element, the transistor, and the holding capacitance element are provided on the substrate. |
| US09721974B2 |
Array substrate and method for manufacturing the same, and display device
The present invention relates to an array substrate, a method for manufacturing the same and a display device. The array substrate comprises a substrate, and a first region and a second region that are provided on the substrate and adjacent to each other and a difference in level between the two exceeds a threshold, a difference-in-level compensation pattern is provided on the substrate, which overlaps with both the first region and the second region in a direction perpendicular to the substrate and does not exceed the first region and the second region. By the technical solution of the present invention, the difference in level between the data line and an adjacent region on the array substrate is reduced, so that during a rubbing process, the rubbing area of a polyimide solution is increased, and the risk of light leakage is reduced without a decrease of the pixel aperture ratio. |
| US09721971B2 |
Display device and electronic device including the same
One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor. |
| US09721970B2 |
Gate all-around FinFET device and a method of manufacturing same
A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer. |
| US09721967B2 |
Nonvolatile memory device and method of manufacturing the same
A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern. |
| US09721962B1 |
Integration of a memory transistor into high-k, metal gate CMOS process flow
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions. |
| US09721960B2 |
Data line arrangement and pillar arrangement in apparatuses
Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl. |
| US09721958B2 |
Method of forming self-aligned split-gate memory cell array with metal gates and logic devices
A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical. |
| US09721956B2 |
Methods, structures and devices for intra-connection structures
Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure. |
| US09721955B2 |
Structure and method for SRAM FinFET device having an oxide feature
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure. |
| US09721954B2 |
Static random access memory (SRAM) device
To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. |
| US09721952B2 |
Semiconductor devices having gate patterns in trenches with widened openings
A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench. |
| US09721947B2 |
Semiconductor device and method of manufacturing
A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor. |
| US09721944B2 |
Hybrid wide-bandgap semiconductor bipolar switches
A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes. |
| US09721934B2 |
LED lighting apparatus
An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED chip is mounted on the main surface of the LED substrate. The sealing resin member is made of a material that transmits light from the LED chip. The sealing resin member covers the LED chip. The sealing resin member has a shape bulging in the direction in which the main surface faces. The reflecting face surrounds the sealing resin member. |
| US09721931B2 |
Semiconductor light emitting device and fabricating method thereof
A semiconductor light emitting device including a substrate, a plurality of semiconductor light emitting units and a plurality of non-conductive walls is provided. The semiconductor light emitting device is disposed on the substrate in an array. Each of the semiconductor light emitting units has a first electrode and a second electrode opposite to the first electrode. Each of the semiconductor light emitting units is electrically connected to the substrate through the first electrode, and the semiconductor light emitting units are electrically connected together to a conducting layer through the second electrodes. The semiconductor light emitting units have different emission colors. The non-conductive walls are disposed between adjacent semiconductor light emitting units, to separate the semiconductor light emitting units. A fabricating method of semiconductor light emitting device is also provided. |
| US09721925B2 |
Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. |
| US09721924B2 |
Thin stack packages
The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip. |
| US09721916B2 |
Concentric bump design for the alignment in die stacking
An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other. |
| US09721912B2 |
Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality
Semiconductor devices are described that have bump assemblies configured to furnish shock absorber functionality. In an implementation, a wafer-levelchip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., solder bumps that do not include a core). The array further comprises a plurality of second bump assemblies that includes a solder bump having a core configured to furnish shock absorber functionality to the integrated circuit chip. |
| US09721909B1 |
Hybrid microwave integrated circuit
A radio frequency (RF) integrated circuit includes a first layer of semiconductor material in which a high electron mobility transfer (HEMT) device is formed. A semiconductor heat spreader substrate supports the first layer of semiconductor material. A pair of matching circuits are electrically connected to the HEMT device, wherein the pair of matching circuits are supported on a semiconductor substrate of a semiconductor material different than the semiconductor material of the first semiconductor heat spreader substrate. The first layer of semiconductor material and the first semiconductor heat spreader substrate have a thickness that is less than a second thickness of the semiconductor substrate supporting the pair of matching circuits. |
| US09721907B2 |
Wafer edge shape for thin wafer processing
A wafer that includes a front surface, a back surface, and an edge between the front surface and the back surface having a curved edge profile between an edge of the front surface and a side face of the edge of the wafer. The edge profile includes a first convex curve that joins the edge of the front surface, a second convex curve that joins the side face, and an intermediate concave curve that joins the first convex curve and the second convex curve. |
| US09721906B2 |
Electronic package with corner supports
An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die. |
| US09721905B2 |
Semiconductor package and mobile device using the same
According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer. |
| US09721904B2 |
Semiconductor packages including a shielding part and methods for manufacturing the same
A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. Edge portions of the conductive elastic plate may be inserted into the trenches of the conductive guard rails and supported by the conductive guard rails by a force trying to stretch by the elastic restoring force of the wing portions of the conductive elastic plate. |
| US09721901B2 |
Thin-film transistor substrate, display apparatus, method of manufacturing thin-film transistor substrate, and method of manufacturing display apparatus
Disclosed is a thin-film transistor substrate including: a substrate; a thin-film transistor formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; an identification (ID) mark formed on the substrate; and a metal layer contacting an upper surface of the ID mark. |
| US09721900B2 |
Semiconductor package and its manufacturing method
Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via. |
| US09721899B2 |
Embedded component package structure and method of manufacturing the same
An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die. |
| US09721894B2 |
Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer. |
| US09721893B2 |
Self-forming barrier for subtractive copper
A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines. |
| US09721887B2 |
Method of forming metal interconnection
A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a trench in the dielectric layer, forming a first barrier layer in the trench. The first barrier layer has a first portion disposed along sidewalls of the trench and a second portion disposed over a bottom of the trench. The method also includes applying an anisotropic plasma treatment to convert the second portion of the first barrier layer into a second barrier layer, removing the second barrier layer while the first portion of the first barrier layer is disposed along sidewalls of the trench. The method also includes forming a conductive feature in the trench. |
| US09721883B1 |
Integrated circuit and manufacturing method thereof
Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer. |
| US09721881B1 |
Apparatus and methods for multi-die packaging
A method of forming a semiconductor device assembly includes forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The method further includes attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device. |
| US09721880B2 |
Integrated circuit package structures
Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate. |
| US09721878B2 |
High density second level interconnection for bumpless build up layer (BBUL) packaging technology
An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body. |
| US09721876B2 |
Semiconductor device and method of making the same
A semiconductor device includes a first electronic component mounted to an upper face of a plated interconnect layer, a second electronic component mounted to a lower face of the plated interconnect layer, a first resin part covering the first electronic component on an upper side of the plated interconnect layer, and a second resin part covering the second electronic component on a lower side of the plated interconnect layer, wherein the first and second electronic components at least partially face each other across the plated interconnect layer, wherein the plated interconnect layer includes a sloping portion disposed on a sloping boundary between the first and second resin parts, and wherein an end part of the sloping portion is bent to have a face thereof exposed from the second resin part, and a lower surface of the second resin part is flush with the face of the end part. |
| US09721874B2 |
Pre-encapsulated lead frames for microelectronic device packages, and associated methods
Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers. |
| US09721872B1 |
Methods and structures for increasing the allowable die size in TMV packages
A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized. |
| US09721871B2 |
Heat exchanger methods, apparatuses and systems with a manifold structure
Methods, apparatuses and systems associated with a heat exchanger for cooling an IC package are disclosed herein. In embodiments, a heat exchanger may include a base plate having a bottom side to be thermally coupled to the IC package, and a fin side, wherein the fin side is to include a plurality of fins to dissipate thermal energy emanated from the IC package. The heat exchanger may further include a manifold structure disposed on top of the base plate, having one or more layers, to regulate a coolant fluid flow to cool the plurality of fins, wherein the one or more layers are to include a plurality of channels and ports complementarily organized to distribute the coolant fluid flow to the plurality of fins tailored to a thermal energy emanation pattern of the integrated circuit package. Other embodiments may be described and/or claimed. |
| US09721870B2 |
Cooling structure for electronic boards
A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels. |
| US09721867B1 |
Graphene heat dissipating structure
Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height. |
| US09721865B2 |
Semiconductor device with a semiconductor chip connected in a flip chip manner
A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip. |
| US09721864B2 |
Low cost hermetic micro-electronics
A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant. |
| US09721855B2 |
Alignment of three dimensional integrated circuit components
A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location. |
| US09721851B2 |
Silicon-germanium fin formation
Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an insulator layer stacked on the silicon substrate, and a plurality of silicon semiconductor fins each stacked directly on the insulator layer. Forming the set of semiconductor fins can include depositing a first atomic layer of germanium atoms on a first set of semiconductor fins in the plurality of semiconductor fins and annealing the first atomic layer and the first set of semiconductor fins. Forming the set of semiconductor fins can include forming, from the annealing, a first set of silicon-germanium semiconductor fins. |
| US09721850B2 |
Method for making a three dimensional integrated electronic circuit
A method for making a three-dimensional integrated electronic circuit is provided, including making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that it is disposed between the first and second dielectric layers, and a second semiconductor layer disposed on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the first electronic component to the first electrically conductive portion. |
| US09721846B1 |
Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device
The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device. |
| US09721840B2 |
Method of forming complementary metal oxide semiconductor device with work function layer
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same. |
| US09721833B2 |
Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the semiconductor device
A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void. |
| US09721832B2 |
Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding
A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication. |
| US09721826B1 |
Wafer supporting structure, and device and method for manufacturing semiconductor
A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring. |
| US09721824B2 |
Wafer bonding method and device with reduced thermal expansion
A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer. |
| US09721823B2 |
Method of transferring micro-device
A method of transferring micro-devices is provided. A carrying unit including a carrying substrate, a plurality of electrodes, a dielectric layer covering the electrodes, and a plurality of micro-devices disposed on the electrodes, including a first micro-device and a second micro-device, are also provided. A voltage is applied to an electrode corresponding to the first micro-device, so that an electrostatic force generated on the first micro-device by the carrying unit is larger than a force generated on the second micro-device by the carrying unit. A transfer stamp contacts the first micro-device and the second micro-device, and moves when the transfer stamp contacts the first micro-device and the second micro-device and the electrostatic force is greater than the force generated by the carrying unit, so that the second micro-device is picked up by the transfer stamp and transferred to a receiving unit, and the first micro-device remains on the carrying unit. |
| US09721822B2 |
Electrostatic chuck apparatus
Disclosed is an electrostatic chuck apparatus which is configured of: an electrostatic chuck section; an annular focus ring section provided to surround the electrostatic chuck section; and a cooling base section which cools the electrostatic chuck section and the focus ring section. The focus ring section is provided with an annular focus ring, an annular heat conducting sheet, an annular ceramic ring, a nonmagnetic heater, and an electrode section that supplies power to the heater. |
| US09721821B2 |
Electrostatic chuck with photo-patternable soft protrusion contact surface
In accordance with an embodiment of the invention, there is provided a soft protrusion structure for an electrostatic chuck, which offers a non-abrasive contact surface for wafers, workpieces or other substrates, while also having improved manufacturability and compatibility with grounded surface platen designs. The soft protrusion structure comprises a photo-patternable polymer. |
| US09721820B2 |
End effector for transferring a substrate
Embodiments of the present invention provide an end effector capable of generating an electrostatic chucking force to chuck a substrate disposed therein without damaging the substrate. In one embodiment, an end effector for a robot, the end effector includes a body having an electrostatic chucking force generating assembly, and a mounting end coupled to the body, the mounting end for coupling the body to the robot. |
| US09721819B2 |
Method for mounting semiconductors provided with bumps on substrate locations of a substrate
The invention relates to a method for mounting semiconductor chips provided with bumps as flip chips on substrate locations of a substrate. The method comprises the placing of a flip chip in a cavity arranged in a stationary manner where the bumps are wetted with a fluxing agent and the position of the flip chip is determined by means of a camera. The method further comprises the use of a transport head and a bonding head, which allow rapid and highly precise mounting. |
| US09721818B2 |
Pressurized gas stopper for leadframe transporting apparatus
An apparatus for transporting a leadframe sheet during semiconductor die assembly includes a rail having sub-rails defining a machine track and an inner space along which the leadframe sheet is moved. A position detector senses a position of the leadframe sheet as the leadframe sheet moves along the machine track. A controller including a processor is coupled to the position detector for receiving the position of the leadframe sheet. A pressurized gas stopper is positioned within the inner space including a gas distributor having at least one gas inlet for receiving a pressured gas supply and at least one gas outlet for directing a flow of gas toward the leadframe sheet sufficient to stop movement of the leadframe sheet. The controller provides control signals for controlling the flow of gas to provide non-contact stopping of the leadframe sheet at one or more locations along the machine track. |
| US09721817B2 |
Apparatus for measuring impurities on wafer and method of measuring impurities on wafer
Provided are an apparatus for measuring impurities on a wafer and a method of measuring impurities on a wafer. The apparatus includes: a wafer aligning device for aligning a wafer; a loading robot for moving and loading the aligned wafer; a rotation stage for rotating the loaded wafer; a scan robot for holding a natural oxide layer etching solution for the wafer and a metallic impurity recovery solution; and a container for receiving a predetermined etching solution and a recovery solution, wherein the scan robot removes an oxide layer on an edge region of the wafer. |
| US09721814B2 |
Substrate processing apparatus
In a substrate processing apparatus, an election head from a position above a substrate held by a substrate holding part to an inspection position above a standby pod disposed outside a cup part. At the inspection position, a processing liquid ejected from the ejection head toward the standby pod is irradiated with planar light emitted from a light emitting part. An imaging part acquires an inspection image including bright dots appearing on the processing liquid, and a determination part determines the quality of the ejection operation of the ejection head on the basis of the inspection image. Accordingly, it is possible to eliminate the influence of reflected light from the substrate and droplets, mist, or the like of the processing liquid having collided with the substrate and to accurately determine the quality of the ejection operation of the ejection head. |
| US09721813B2 |
Liquid processing apparatus with cleaning jig
The present disclosure provides a cleaning method which enables a cup and a member around the cup to be cleaned thoroughly. In this cleaning method, a cleaning liquid is supplied to a cleaning jig from the upper side of the cleaning jig while rotating the cleaning jig held by a substrate holding unit. The cleaning liquid supplied to the cleaning jig is scattered obliquely upward along an inclined surface of an inclined portion which is provided around the entire circumference of the cleaning jig in the vicinity of the outer circumferential edge of the cleaning jig, thereby cleaning cups. |
| US09721811B2 |
Method for manufacturing a semiconductor device having an oxide semiconductor layer
A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. |
| US09721807B2 |
Cyclic spacer etching process with improved profile control
Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile. |
| US09721806B2 |
LDMOS device and fabrication method thereof
The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode. |
| US09721805B1 |
Formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The method includes forming first and second fin structures over a semiconductor substrate. Each of the first and second fin structures has an upper portion and a lower portion. The method also includes forming a phosphosilicate glass (PSG) layer surrounding the upper and lower portions of the first fin structure. The method further includes doping the PSG layer to form a doped PSG layer. In addition, the method includes forming a borosilicate glass (BSG) layer surrounding the upper and lower portions of the second fin structure. The BSG layer extends over the doped PSG layer. The method also includes forming an isolation layer over the BSG layer. The method further includes partially etching the isolation layer, the BSG layer and the doped PSG layer to expose the upper portions of the first and second fin structures. |
| US09721800B2 |
Apparatus for wetting pretreatment for enhanced damascene metal filling
Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer. |
| US09721797B2 |
Semiconductor device
A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer. |
| US09721795B2 |
Methods of forming patterns having different shapes
A method of forming patterns includes forming pillars and first peripheral patterns on an underlying layer, forming a separation wall layer covering sidewalls of the pillars and the first peripheral patterns, forming blocking portions on the separation wall layer to fill first openings between the first peripheral patterns, forming a block copolymer layer filling gap regions between the pillars, annealing the block copolymer layer to form first domains and a second domain surrounding the first domains, removing the first domains and removing portions of the separation wall layer to form second openings, removing the second domain and the blocking portions, removing the pillars and the first peripheral patterns to form third openings and fourth openings, and patterning the underlying layer to form fifth openings that extend from the second and third openings and sixth openings that extend from the fourth openings. |
| US09721781B2 |
Device for mass spectrometry
A device for mass spectrometry in continuous operation can be equipped with a focused electron beam source or laser radiation source. It can further include a vacuum chamber, a stage for placing the specimen, and an ion beam column with a plasma source for producing a primary ion beam and a secondary ion mass spectrometer for secondary ion analysis. The ion beam column is connected to an inert gas source and to a reactive gas source and is modified for simultaneous introduction of at least two gases from the inert gas source and reactive gas source. The secondary ion mass spectrometer is of an orthogonal Time-of-Flight type to ensure the function with the ion beam column in continuous operation. |
| US09721779B2 |
Orthogonal acceleration coaxial cylinder time of flight mass analyser
A Time of Flight mass analyzer is disclosed comprising an annular ion guide having a longitudinal axis and comprising a first annular ion guide section and a second annular ion guide section. Ions are introduced into the first annular ion guide section so that the ions form substantially stable circular orbits within the first annular ion guide section about the longitudinal axis. The ions are then orthogonally accelerated ions from the first annular ion guide section into the second annular ion guide section. An ion detector is disposed within the annular ion guide and has an ion detecting surface arranged in a plane which is substantially perpendicular to the longitudinal axis. |
| US09721776B2 |
Sample preparation method and sample preparation device for MALDI including depositing matrix substance on sample substrate in two steps
After a sample such as a biomedical tissue section is attached to an electrically-conductive slide glass (S1), the film layer of a matrix substance is appropriately formed by vapor deposition so as to cover the sample (S2). The crystal of the matrix substance in the film layer is very fine and uniform. Subsequently, the slide glass on which the matrix film layer is formed is placed in a vaporized solvent atmosphere, and the solvent infiltrates into the matrix film layer (S3). When the solvent sufficiently infiltrated is vaporized, a substance to be measured in the sample takes in the matrix and re-crystallized. Furthermore, the matrix film layer is formed again on the surface by the vapor deposition (S4). The added matrix film layer absorbs excessive energy of a laser beam during MALDI, which suppresses the denaturation of the substance to be measured and the like, so that high detection sensitivity can be achieved while high spatial resolution is maintained. |
| US09721775B2 |
Charging plate for enhancing multiply charged ions by laser desorption
A sample plate for an ion source is disclosed comprising a plurality of ionization regions, each ionization region comprising a first electrode and a second separate electrode separated by an insulator. |
| US09721774B2 |
Interface for ion source and vacuum housing
A mass spectrometer or ion mobility spectrometer is disclosed comprising: an ion block for receiving ions; a heater for heating the ion block; a vacuum housing; and an interface block arranged between the ion block and the vacuum housing; wherein the interface block is formed from a polymer. The polymer interface block inhibits the heat transfer from the ion block to the vacuum housing and also electrically isolates the ion block and vacuum housing. The interface block further comprises at least one conduit through the body of the interface block. This enables gas to be transmitted through the interface block to the ion block, and also enables the interface block to be cooled. |
| US09721773B2 |
Mass spectrometric device and mass spectrometric device control method
This mass spectrometric device is provided with a sample container (8) for placing a measurement sample (12) therein, a detector (9) analyzing the mass of a sample and detecting a drug, or the like, in the sample, a dielectric container (3) linked to the sample container for running a discharge current into air to provoke ionization, a valve (2) for sending air intermittently to the sample container, the dielectric container and the detector, a barrier discharge high-voltage power source (6) to be discharged by the dielectric container, a current detection unit (5) connected to the barrier discharge high-voltage power source for detecting a discharge current (28), a discharge-start timing detection unit (7) connected to the current detection unit for detecting the discharge-start timing based on the current detection result from the current detection unit to send a discharge-start timing signal (17), and a control unit (11) for controlling each constituent. |
| US09721772B2 |
Ion chamber enclosure material to increase gamma radiation sensitivity
A radiation detection assembly that includes an ionization chamber having a cathode and an anode. The ionization chamber detects radiation that passes into the ionization chamber. The assembly includes an exterior enclosure defining a hollow internal volume within which the ionization chamber is enclosed. The exterior enclosure includes at least two layers. At least one of the layers provides an electromagnetic shield to the hollow internal volume and the ionization chamber enclosed therein. |
| US09721764B2 |
Method of producing plasma by multiple-phase alternating or pulsed electrical current
A method of producing a plasma is provided. The method includes providing at least three hollow cathodes, including a first hollow cathode, a second hollow cathode, and a third hollow cathode. Each hollow cathode has a plasma exit region. The method further includes providing a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave. The first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase. Each hollow cathode is electrically connected to the source of power such that the first hollow cathode is electrically connected to the first output wave, the second hollow cathode is electrically connected to the second output wave, and the third hollow cathode is electrically connected to the third output wave. Electrical current flows between the at least three hollow cathodes that are out of electrical phase. A plasma is generated between the hollow cathodes. |
| US09721762B2 |
Method and system managing execution of preventative maintenance operation in semiconductor manufacturing equipment
Provided are a method and a system for managing semiconductor manufacturing equipment. The method may be performed using an equipment computer and may include ordering to perform a preventive maintenance to a chamber and parts in the chamber, monitoring a result of the preventive maintenance to the chamber and the parts, and performing a manufacturing process using plasma reaction in the chamber, if the result of the preventive maintenance is normal. The monitoring the result of the preventive maintenance may include a pre-screening method monitoring the result of the preventive maintenance using electric reflection coefficients obtained from the chamber and the parts without using the plasma reaction. |
| US09721761B2 |
Open plasma lamp for forming a light-sustained plasma
An open plasma lamp includes a cavity section. A gas input and gas output of the cavity section are arranged to flow gas through the cavity section. The plasma lamp also includes a gas supply assembly fluidically coupled to the gas input of the cavity section and configured to supply gas to an internal volume of the cavity section. The plasma lamp also includes a nozzle assembly fluidically coupled to the gas output of the cavity section. The nozzle assembly and cavity section are arranged such that a volume of the gas receives pumping illumination from a pump source, where a sustained plasma emits broadband radiation. The nozzle assembly is configured to establish a convective gas flow from within the cavity section to a region external to the cavity section such that a portion of the sustained plasma is removed from the cavity section by the gas flow. |
| US09721760B2 |
Electron beam plasma source with reduced metal contamination
In a plasma reactor for processing a workpiece, an electron beam is employed as the plasma source, and sputtered metal atoms are removed from the electron beam to reduce contamination. |
| US09721759B1 |
System and method for distributing RF power to a plasma source
Described herein are techniques for supplying radio frequency (RF) power to a large area plasma source so as to produce a plasma that is substantially uniform in two spatial dimensions. The RF power may be supplied by a power supply system, which may comprise a RF source and a distribution network. The distribution network may comprise a matching network, and a branching circuit that divides the RF power into several branches. Each of the branches of the distribution network may include a phase shifter that shifts the RF signal (which carries the RF power) by an odd multiple of 90°, and a blocking filter which blocks any harmonics and other unwanted frequencies which are reflected from a plasma source. The output of the branches may be coupled to feed points that are spatially distributed over the one or more electrodes of the plasma source. |
| US09721757B2 |
Elongated capacitively coupled plasma source for high temperature low pressure environments
A modular plasma source assembly for use with a processing chamber is described. The assembly includes an RF hot electrode with an end dielectric and a sliding ground connection positioned adjacent the sides of the electrode. A seal foil connects the sliding ground connection to the housing to provide a grounded sliding ground connection separated from the hot electrode by the end dielectric. A coaxial feed line passes through a conduit into the RF hot electrode isolated from the processing environment so that the coaxial RF feed line is at atmospheric pressure while the plasma processing region is at reduced pressure. |
| US09721748B2 |
X-ray generation
An apparatus for generating x-rays includes an electron beam generator and a first device arranged to apply an RF electric field to accelerate the electron beam from the generator. A photon source is arranged to provide photons to a zone to interact with the electron beam from the first device so as to generate x-rays via inverse-Compton scattering. A second device is arranged to apply an RF electric field to decelerate the electron beam after it has interacted. The first and second devices are connected by RF energy transmission means arranged to recover RF energy from the decelerated electron beam as it passes through the second device and transfer the recovered RF energy into the first device. |
| US09721747B2 |
Grid, method of manufacturing the same, and ion beam processing apparatus
A grid of the present invention is a plate-shaped grid provided with a hole. The grid is formed of a carbon-carbon composite including carbon fibers arranged in random directions along a planar direction of the grid, and the hole is formed in the grid so as to cut off the carbon fibers. |
| US09721746B2 |
Display device and method for manufacturing the same
Display device includes a display panel. The display panel includes a first substrate, a sealant, and, a second substrate fastended to the first substrate via the sealant. At least one of the first substrate and the second substrate is a non-planar substrate including at least two portions correspondingly extending in different planes. |
| US09721743B2 |
Fuse component and electric motor incorporating the same
A fuse component (36) configured to provide overcurrent protection for an electric motor (20) comprises a spiral (41) of a plurality of coaxial wire loops (44) and an outer insulating sleeve (39) surrounding at least a portion of the spiral (41). The overcurrent threshold of the fuse component (36) may be adjusted by changing the number of loops in the spiral (41) or the cross-section area of the wire in the spiral (41). The fuse component (41) may also function as an inductor (35) and/or connected to a speed adjustable resistor. |
| US09721741B2 |
Electromagnetic contactor
An electromagnetic contactor capable of coupling either one of an alternating current (AC) electromagnet or a direct current (DC) electromagnet with an identical contact support is provided. The electromagnetic contactor includes an electromagnet including either one of the AC electromagnet (12AC) including a movable core or the DC electromagnet (12DC) including an armature, and a contact support (36) configured to hold plural movable contacts in alignment to be coupled with and driven by the electromagnet. The contact support includes a coupling portion (40) including a movable core contact portion (41), coupling spring edge accommodation portions (46), and armature contact portions (51) arranged on opposite sides with respect to the movable core contact portion of the coupling spring edge accommodation portion. The AC electromagnet (12AC) includes an AC electromagnet coupling spring (56) and the DC electromagnet (12DC) includes a DC electromagnet coupling spring (161). |
| US09721739B2 |
DC voltage switch for high voltage electrical systems
A DC voltage switch for high-voltage on-board electrical systems having a housing, at least two stationary contacts, and a moving contact, wherein, in each case, a first contact region of the stationary contacts is routed out of the housing and, in each case, a second contact region of the stationary contacts is arranged in a switching chamber of the housing with the moving contact, wherein the housing is hermetically encapsulated, wherein a cooling chamber which is separated from the switching chamber by a partition wall is arranged above the switching chamber, wherein the partition wall has at least one outlet opening and at least one inlet opening. |
| US09721736B2 |
Button module and electronic device having the same
An electronic device includes a housing, a button module and a control board. The button module includes a button cap having a space, a follower movably disposed in the space, and an elastic member. A movable cavity is defined by a portion of the follower located in the space and an inner surface of the button cap. The elastic member is disposed in the movable cavity, and two ends of the elastic member respectively abut against the inner surface of the button cap and the follower. An amount of compression of the elastic member is varied in response to the size of the movable cavity. When the button cap is in an unpressed state, the elastic member has a first amount of compression and generates a restoring force; when the button cap is in a pressed state, the follower abuts against a switch unit of the control board correspondingly. |
| US09721735B2 |
Multi-function charger
A multi-function charger is provided. The multi-function charger includes a main body, a first plug, a first base, a second base, and a linkage element. The main body has a first surface having a recess and a second surface opposite thereto. The first plug having a first connector, a second connector, and a third connector is arranged in the main body and exposed on the first surface. The first base is connected to the first and second connectors, and the second base is connected to the third connector. The linkage element is pivotally connected to the first and second bases so that the first connector, the second connector, and the third connector are capable of rotating in the same direction until to be arranged in the recess. The linkage element is located in a connecting region defined between the central section of the first base and the second base. |
| US09721733B1 |
Method for forming a dye-sensitized solar cell having a porous film of an inorganic substance on a base material by spraying dry fine particles of an inorganic substance on the base material
The present invention is a method for forming a porous film of an inorganic substance on a base material by spraying fine particles of an inorganic substance on the base material such that the fine particles are bonded to the base material and bonded to one another, in which the fine particles include at least two kinds of fine particles which are small-size particles and large-size particles having different average particle sizes. According to the present invention, it is possible to provide a film forming method for forming a porous film formed of an inorganic substance without requiring a baking step, a body having a film formed thereon that is produced by the film forming method, and a dye-sensitized solar cell including the body having a film formed thereon. |
| US09721731B2 |
Systems and methods to connect sintered aluminum electrodes of an energy storage device
This document provides an apparatus including a sintered electrode, a second electrode and a separator material arranged in a capacitive stack. A conductive interconnect couples the sintered electrode and the second electrode. Embodiments include a clip interconnect. In some embodiments, the interconnect includes a comb-shaped connector. In some embodiments, the interconnect includes a wire snaked between adjacent sintered substrates. |
| US09721729B2 |
Vacuum variable capacitor
A vacuum variable capacitor includes a pre-vacuum enclosure for reducing a pressure differential across the bellows, wherein a drive is disposed outside the enclosures of the vacuum variable capacitor. The vacuum force load on the drive system can thereby be reduced, allowing faster movement of the movable electrode, faster capacitance adjustment of the vacuum variable capacitor and longer lifetimes of the device. |
| US09721728B2 |
Biaxially oriented polypropylene film for capacitor, metallized film, and film capacitor
A biaxially orientated polypropylene film for capacitor includes protrusions on both surfaces. The biaxially orientated polypropylene film has a thickness (t1) of 1 to 3 μm, has a ten point average roughness (SRz) of 50 nm or more and less than 500 nm on both surfaces, and meets equations (1) and (2) where one surface and the other surface are referred to as a surface A and a surface B, respectively: 150≦Pa≦400 (1) 50≦Pb≦150 (2) wherein Pa denotes number of protrusions per 0.1 mm2 on the surface A and Pb denotes number of protrusions per 0.1 mm2 on the surface B. |
| US09721726B2 |
Graphene mounted on aerogel
An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate. |
| US09721724B2 |
Method for producing R-T-B sintered magnet
[Problem] To provide a highly efficient manufacturing method including an RH supply-diffusion process by which the number of magnets processed at a time can be increased without allowing sintered R-T-B based magnets to stick to holding members.[Solution] A method for producing a sintered R-T-B based magnet including the steps of: forming a stack of RH diffusion sources and sintered R-T-B based magnet bodies by stacking the diffusion sources and the magnet bodies alternately with a holding member having openings interposed; and carrying out an RH supply-diffusion process by loading the stack into a process vessel and creating an atmosphere with a pressure of 0.1 Pa to 50 Pa and a temperature of 800° C. to 950° C. within the process vessel. |
| US09721720B2 |
Power use reduction transformer
A power conditioning device reduces capacitive-in-nature, out of phase current (verses voltage), non-linear distortion, and/or leading power factor “noise” in electrical current in an electrical panel, improving the power efficiency of devices connected to the panel. The physical and electrical specifications of the device allow it to be more easily installed and give it a more robust installation environment. |
| US09721719B1 |
Coupled inductors with leakage plates, and associated systems and methods
A coupled inductor includes a ladder magnetic core, a first common leakage plate formed of a magnetic material, and N windings, where N is an integer greater than one. The ladder magnetic core includes first and second rails and N rungs, where each of the N rungs connects the first and second rails. Each of the N windings includes a respective first portion. Each of the N windings is wound around a respective one of the N rungs, and at least two of the N windings are wrapped at least partially around the first common leakage plate such that a first portion of the winding is disposed between an outer surface of the first rail and an outer surface of the first common leakage plate. |
| US09721718B2 |
Transformers and methods for fabricating transformers
A transformer includes multiple differential ports and first and second transformer windings. The first transformer winding includes a first transformer half-winding coupled to a first differential port of the differential ports. The first transformer winding also includes a second transformer half-winding coupled to a second differential port of the differential ports. An amplifier system that has a transformer is also provided. The amplifier system includes a first and a second stage amplifier. The first stage amplifier includes a first and a second amplifier. The second stage amplifier includes a third and a fourth amplifier. The transformer is coupled between the first stage amplifier and the second stage amplifier, where the transformer has a primary loop and a secondary loop. The primary loop of the transformer may be configured to receive differential signals of the first amplifier. A method for fabricating a transformer is also provided. |
| US09721712B2 |
Hybrid mechanical and magnetic fastening system
The present disclosure relates to a hybrid fastener system involving combining mechanical tensile features with magnetic components. |
| US09721710B2 |
Axial magnetic suspension
The present invention generally relates to an apparatus and method for axially supporting a shaft. In one aspect, a magnetic suspension system for supporting a shaft in a housing is provided. The magnetic suspension system includes an array of magnet members disposed between the shaft and the housing. The array of magnet members comprising a first magnet member, a second magnet member, and a third magnet member, wherein the first magnet member and the second magnet member generate a first force that is substantially parallel to a longitudinal axis of the shaft and the second magnet member and the third magnet member generate a second force that is substantially parallel with the longitudinal axis of the shaft The first force and the second force are configured to position the shaft axially within the housing. In another aspect, a method of supporting a shaft along a longitudinal axis of a housing is provided. In a further aspect, a suspension system for supporting a shaft in a housing is provided. |
| US09721709B2 |
Inductively decoupled dual SMES in a single cryostat
Various SMES systems that include two magnets in a single cryostat are disclosed. These dual SMES systems can be used, for example, to provide uninterrupted power to a data center. The two coil sets are arranged such that they are magnetically decoupled from each other. In one embodiment, a toroidal coil set is used as the primary coil set. The toroidal coil set has a plurality of toroidal field (TF) coils extending radially outward and evenly spaced in the circumferential direction. The second coil set may be a solenoidal coil set having a main coil and a plurality of shielding coils. The toroidal coil set may be disposed in the space between the main coil and the shielding coils of the solenoidal coil set. Alternate designs are also presented. |
| US09721706B2 |
Non-oriented electrical steel sheet, manufacturing method thereof, laminate for motor iron core, and manufacturing method thereof
A value of a parameter Q represented by “Q=([Ti]/48+[V]/51+[Zr]/91+[Nb]/93)/([C]/12)” is not less than 0.9 nor more than 1.1, when contents of Ti, V, Zr, Nb, and C (mass %) are represented as [Ti], [V], [Zr], [Nb], and [C] respectively. A matrix of a metal structure is a ferrite phase, and the metal structure does not contain a non-recrystallized structure. An average grain size of ferrite grains constituting the ferrite phase is not less than 30 μm nor more than 200 μm. A precipitate containing at least one selected from the group consisting of Ti, V, Zr, and Nb exists with a density of 1 particle/μm3 or more in the ferrite grain. An average grain size of the precipitate is not less than 0.002 μm nor more than 0.2 μm. |
| US09721693B2 |
Collimator for x-ray, gamma, or particle radiation
A collimator for x-ray, gamma, or particle radiation has a plurality of collimator elements made of a tungsten-containing material to reduce scattered radiation. At least one collimator element consists of a tungsten alloy having a tungsten content of 72 to 98 wt.-%, which contains 1 to 14 wt.-% of at least one metal of the group Mo, Ta, Nb and 1 to 14 wt.-% of at least one metal of the group Fe, Ni, Co, Cu. The collimator also has very homogeneous absorption behavior at very thin wall thicknesses of the collimator elements. |
| US09721687B2 |
Method of storing a chimney assembly of a reactor pressure vessel during a nuclear reactor outage
A method of storing a chimney assembly of a reactor pressure vessel during a nuclear reactor outage includes detaching a chimney barrel with upper chimney partitions therein from a top guide assembly of the reactor pressure vessel. A height of the upper chimney partitions is less than a height of the chimney barrel so as to leave a plenum region in a top section of the chimney barrel. The top guide assembly includes lower chimney partitions therein. The lower chimney partitions are removed from the top guide assembly and inserted into the plenum region of the chimney barrel so as to be on the upper chimney partitions. As a result, the chimney assembly can be stored in a relatively compact form during a reactor outage. The chimney assembly includes a combination of at least the chimney barrel, the upper chimney partitions, and the lower chimney partitions. |
| US09721685B2 |
Valve assembly with isolation valve vessel
Apparatuses for reducing or eliminating Type 1 LOCAs in a nuclear reactor vessel. A nuclear reactor including a nuclear reactor core comprising a fissile material, a pressure vessel containing the nuclear reactor core immersed in primary coolant disposed in the pressure vessel, and an isolation valve assembly including, an isolation valve vessel having a single open end with a flange, a spool piece having a first flange secured to a wall of the pressure vessel and a second flange secured to the flange of the isolation valve vessel, a fluid flow line passing through the spool piece to conduct fluid flow into or out of the first flange wherein a portion of the fluid flow line is disposed in the isolation valve vessel, and at least one valve disposed in the isolation valve vessel and operatively connected with the fluid flow line. |
| US09721684B2 |
Systems and methods for detecting a leaking fuel channel in a nuclear reactor
Methods and systems for detecting an individual leaking fuel channel included in a reactor. One system includes a plurality of inlet lines and a plurality of outlet lines. Each of the plurality of inlet lines feeding annulus fluid in parallel to an annulus space of each of a first plurality of fuel channels included in the reactor, and each of the plurality of outlet lines collecting in parallel annulus fluid exiting an annulus space of each of a second plurality of fuel channels included in the reactor. In some embodiments, the system also includes a detector positioned at an outlet of each of the plurality of outlet lines configured to detect moisture in annulus fluid and identify a first position of an individual leaking fuel channel, and an isolation valve positioned at an inlet of each of the plurality of inlet lines operable to stop annulus fluid from circulating through one of the plurality of inlet lines and to identify a second position of the individual leaking fuel channel. |
| US09721683B2 |
Wireless transmission of nuclear instrumentation signals
A system for monitoring a condition of a nuclear reactor pressure vessel disposed in a radioactive environment includes an instrument structured to monitor a condition of the nuclear reactor pressure vessel; a powered wireless transmitting modem disposed in the radioactive environment, the wireless transmitting modem being electrically coupled to the instrument; a receiving modem disposed in the line of sight of the transmitting modem, the receiving modem being in wireless communication with the transmitting modem; and a signal processing unit electrically coupled to the receiving modem, the signal processing unit being structured to determine the condition of the nuclear reactor pressure vessel from the instrument. The transmitting modem is powered by a thermocouple disposed in or on the reactor pressure vessel. |
| US09721680B2 |
Operating a nuclear reactor using a deposit model of a nuclear reactor heat transfer surface
A method of operating a nuclear reactor is provided. The method includes defining a layer increment of a deposit layer modeling a deposit on a heat transfer surface of the nuclear reactor; periodically updating a thickness of the deposit layer by adding the layer increment to the deposit layer; recalculating properties of the deposit layer after each layer increment is added to the deposit layer; determining a temperature related variable of the heat transfer surface as a function of the recalculated properties of the deposit layer; and altering operation of the nuclear reactor when the temperature related variable of the heat transfer surface reaches a predetermined value. A method of modeling a deposit on a heat transfer surface of a nuclear reactor is also provided. |
| US09721674B2 |
GOA unit and method for driving the same, GOA circuit and display device
Embodiments of the present disclosure provide a GOA unit and a method for driving the same, a GOA circuit and a display device. The embodiments of the preset disclosure relate in particular to the field of display manufacture. The GOA unit specifically comprises: a first node control module and a second node control module, wherein the first node control module is connected to a first control node, an input signal terminal, a first clock signal terminal, and an output signal terminal, wherein the second node control module is connected to a reset signal terminal, a second clock signal terminal, a third clock signal terminal, a first level terminal, the output terminal, and the first control node. The embodiment of the present disclosure may simplify the structure of a GOA circuit and be used for display manufacture. |
| US09721672B1 |
Multi-die programming with die-jumping induced periodic delays
Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses. |
| US09721664B2 |
Memory devices and methods of operating the memory devices by programming normal cells after programming a first dummy cell
A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells. |
| US09721661B1 |
Content addressable memories
An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor. |
| US09721658B1 |
Memory devices and methods for storing single data value in multiple programmable resistance elements
A memory device can include a plurality of bit lines; plurality of memory elements coupled to the bit lines, each memory element including a memory layer formed between two electrodes, the memory layer being programmable between a plurality of different resistance states by creation and removal of conductive regions therein by application of electric fields; and at least one sense amplifier (SA) configured to compare a first value, corresponding to a resistance state of a first memory element, to a second value, corresponding to a resistance state of a second memory element. |
| US09721655B2 |
Memory cell having dielectric memory element
Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell. |
| US09721653B2 |
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. |
| US09721649B1 |
Circuit for and method of implementing a write operation of a memory
A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described. |
| US09721648B2 |
Semiconductor device
There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width. |
| US09721647B2 |
Semiconductor device
An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line. |
| US09721646B1 |
Prevention of SRAM burn-in
Embodiments are directed to a static random access memory (SRAM) device that prevents burn-in of potentially sensitive information. After an SRAM device is fabricated in a semiconductor material, a heating wire is placed in the layers above portions of the SRAM device. By applying current to the heating wire, a certain temperature is reached for a certain amount of time, and the burn-in of the SRAM is prevented. Other embodiments are also presented. |
| US09721644B2 |
Semiconductor memory device for improving signal integrity issue in center pad type of stacked chip structure
A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die. |
| US09721643B2 |
Row hammer monitoring based on stored row hammer threshold value
Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row. |
| US09721642B2 |
Memory component with pattern register circuitry to provide data patterns for calibration
A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. |
| US09721640B2 |
Performance of additional refresh operations during self-refresh mode
Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles. |
| US09721638B1 |
Boosting a digit line voltage for a write operation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased. |
| US09721634B2 |
Decoupling of source line layout from access transistor contact placement in a magnetic tunnel junction (MTJ) memory bit cell to facilitate reduced contact resistance
Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance. |
| US09721632B2 |
Redundant magnetic tunnel junctions in magnetoresistive memory
Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state. |
| US09721629B2 |
On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device. |
| US09721628B1 |
Address based memory data path programming scheme
Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches. |
| US09721619B2 |
Hermetic sealing of hard disk drive using laminated film seal
A hermetically-sealed hard disk drive (HDD) utilizes a laminated film seal to seal an interface of an electrical feed-through connector and an HDD enclosure base. The laminated film seal may be constructed of a heat sealant layer that bonds with a surface of the base and a surface of the electrical connector, a barrier layer which inhibits gas from escaping from inside the HDD, and a film surface protective layer which protects the heat sealant and barrier layers. Embodiments may include a heat sealant layer comprising a thermoplastic polymer such as polypropylene, a barrier layer comprising a metal such as aluminum, and a film surface protective layer comprising a thermoplastic polymer such as polyethylene terephthalate. |
| US09721612B2 |
Method and apparatus for providing content lists using connecting user interface elements
An approach is provided for providing content lists using connecting user interface elements. The content-based patching platform causes, at least in part, a rendering of a user interface depicting at least one location-based content list and at least one other location-based content list. Next, the content-based patching platform determines one or more interactions with at least one connecting user interface element to cause, at least in part, an association of the at least one location-based content list with the at least one other location-based content list. Then, the content-based patching platform determines to create at least one mixed content list from the at least one location-based content list, the at least one other location-based content list, or a combination thereof based, at least in part, on the association. |
| US09721610B2 |
Method of managing, writing, and reading file on tape
Managing a file on a tape. In response to a request to write a first file to a tape, whether a second file including data identical to the first file already exists on the tape is detected. If the second file exists, a first index of the second file is updated. After completing the write of the first file, metadata, including data starting position and size of the first file, is added to the first index. In response to a request to read the first or second files, the metadata of the first and second indexes are read. Based on the metadata, which of the first or second files can be accessed faster from a current head position is determined. The first file or the second file that can be accessed faster is then read from the tape. |
| US09721607B2 |
Magnetic recording medium and method of manufacturing the same
The magnetic recording medium has a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, wherein the ferromagnetic powder is ferromagnetic hexagonal ferrite powder, and the ferromagnetic hexagonal ferrite powder has a crystallite volume as determined by X-ray diffraction analysis ranges from 1,000 nm3 to 2,400 nm3, and a ratio of the crystallite size Dx(107) obtained from a diffraction peak of a (107) plane to a particle size in a direction of an easy axis of magnetization DTEM as determined by observation with a transmission electron microscope, Dx(107)/DTEM, is greater than or equal to 1.1. |
| US09721604B2 |
Perpendicular magnetic recording (PMR) write head with improved shapes of side shield and main pole
A perpendicular magnetic recording writer is disclosed with a side shield separated from a write pole side by a gap layer at an air bearing surface (ABS) where the side shield has a first sidewall facing the write pole with an end at height (h1) from the ABS, and a second sidewall at height h1 that is parallel to the ABS. The write pole side is curved such that a first portion proximate to the ABS is at an angle of 0 to 40 degrees with respect to a center plane formed orthogonal to the ABS, and a second section proximate to a corner where the curved side connects with a flared main pole side is formed substantially parallel to the second sidewall. When h1 is 30-80 nm, and the corner is 80-150 nm from the ABS, overwrite is improved while cross-track field gradient is enhanced. |
| US09721603B2 |
Head-medium contact detection using an oscillating electromagnetic force
An apparatus comprises circuitry configured to apply an AC signal having a frequency to one of a slider of a recording head and a magnetic recording medium. The applied AC signal causes an oscillation in an electrostatic force and clearance between the slider and the medium at the frequency of the AC signal. A thermal sensor is configured to generate a sensor signal at the AC signal frequency in response to sensing changes in temperature resulting from the oscillating clearance. A detector is coupled to the circuitry and the thermal sensor. The detector is configured to detect one or both of head-medium spacing changes and head-medium contact using a phase of a first harmonic or an amplitude of a second harmonic of the thermal sensor signal. |
| US09721600B2 |
Apparatus, systems and processes for reducing a hard disk drive's access time and concomitant power optimization
Rotational latency is reduced in a standard conventional form factor HDD system by replacing, for example, the prior art rotary arm actuator of a conventional HDD, with one or more belts and pulleys and one or more read/write heads mounted on, or otherwise associated with the belts. Multiple scaled iterations facilitate energy savings and power optimized systems, without compromise to data access performance. |
| US09721598B2 |
Terminal pad of a flexure for a head suspension having a padding plating and method of forming the terminal pad
A terminal pad of a flexure for a head suspension connected to a functional part through a bonding material includes a terminal body, a base plating formed on a surface of the terminal body and having an uniform thickness, a padding plating made of a same material as the base plating and integrated with the base plating so that the padding plating swells with respect to the base plating, and a surface plating formed on a surface of the padding plating. |
| US09721597B2 |
TMR head design with insulative layers for shorting mitigation
An apparatus according to one embodiment includes a transducer structure having: a lower shield having recesses in an upper surface thereof; an upper shield formed above the lower shield; a sensor between the upper and lower shields, the recesses being positioned on opposite sides of the sensor; and a first insulating layer in the recesses in the upper surface of the lower shield. An upper surface of the first insulating layer is coplanar with an uppermost portion of the upper surface of the lower shield. An apparatus according to another embodiment includes a transducer structure having: a lower shield having recesses in an upper surface thereof; an upper shield formed above the lower shield, the upper shield having recesses in a lower surface thereof; a sensor between the shields, the recesses being positioned on opposite sides of the sensor; and insulating layers in the recesses in the shields. |
| US09721594B2 |
Method of manufacturing spin torque oscillator
According to one embodiment, there is provided a spin torque oscillator including an oscillation layer formed of a magnetic material, a spin injection layer formed of a magnetic material and configured to inject a spin into the oscillation layer, and a current confinement layer including an insulating portion formed of an oxide or a nitride and a conductive portion formed of a nonmagnetic metal and penetrating the insulating portion in a direction of stacking. The conductive portion of the current confinement layer is positioned near a central portion of a plane of a device region including the oscillation layer and the spin injection layer. |
| US09721590B2 |
Varying write pole side shield gap
A magnetic element can be constructed by forming a write pole with a tip portion that continuously extends from an air bearing surface (ABS) along a plane orthogonal to the ABS to a body portion that continuously extends from the tip portion distal the ABS. A first write gap layer can then be deposited in contact with the write pole before a processing layer is deposited in contact with the first write gap layer. A magnetic shield may then be formed atop the processing layer with the magnetic shield being separated from the write pole by a first gap distance on the ABS throughout the tip portion and by a second gap distance distal the ABS along the plane orthogonal to the ABS along the body portion. The first and second gap distances can be measured parallel to the ABS with the second gap distance being greater than the first gap distance. |
| US09721587B2 |
Visual feedback for speech recognition system
Embodiments are disclosed that relate to providing visual feedback in a speech recognition system. For example, one disclosed embodiment provides a method including displaying a graphical feedback indicator having a variable appearance dependent upon a state of the speech recognition system. The method further comprises receiving a speech input, modifying an appearance of the graphical feedback indicator in a first manner if the speech input is heard and understood by the system, and modifying the appearance of the graphical feedback indicator in a different manner than the first manner if the speech input is heard and not understood. |
| US09721585B2 |
Signal processing apparatus, signal processing method, and program
A processing buffer unit stores an audio signal. A pitch calculation unit and a pitch cycle correction unit calculate a multiple of N as the number of samples in a pitch cycle of the audio signal, in which N is an integer equal to or more than 1. A processing control unit and a start-position movement amount correction unit sequentially determine, as a sample in a start position of a compression process in a time axis domain of the audio signal, a (multiple of N)-th sample from a start position immediately before the start position. An operation unit compresses samples in a predetermined number times the pitch cycle from the sample in the start position in a time axis domain, and sets the number of samples after the compression to be the multiple of N. The present technology, for example, may be applied to an audio signal processing apparatus. |
| US09721584B2 |
Wind noise reduction for audio reception
Wind noise reduction is described for audio signals received in a device. In one embodiment, an audio signal is decomposed into a plurality of sub-bands, the audio signal including wind noise, a first sub-band of the plurality of sub-bands low-pass filtered, wind noise is removed from the first sub band and the first sub-band is combined with the other sub-bands after removing wind noise. |
| US09721579B2 |
Coordinating and mixing vocals captured from geographically distributed performers
Despite many practical limitations imposed by mobile device platforms and application execution environments, vocal musical performances may be captured and continuously pitch-corrected for mixing and rendering with backing tracks in ways that create compelling user experiences. Based on the techniques described herein, even mere amateurs are encouraged to share with friends and family or to collaborate and contribute vocal performances as part of virtual “glee clubs.” In some implementations, these interactions are facilitated through social network- and/or eMail-mediated sharing of performances and invitations to join in a group performance. Using uploaded vocals captured at clients such as a mobile device, a content server (or service) can mediate such virtual glee clubs by manipulating and mixing the uploaded vocal performances of multiple contributing vocalists. |
| US09721573B2 |
Decoding-time prediction of non-verbalized tokens
Non-verbalized tokens, such as punctuation, are automatically predicted and inserted into a transcription of speech in which the tokens were not explicitly verbalized. Token prediction may be integrated with speech decoding, rather than performed as a post-process to speech decoding. |
| US09721572B2 |
Device control method and electric device
A method for controlling an operation of a target device using a plurality of input devices is disclosed. The method comprises: receiving from one of the plurality of the input devices a first operation instruction issued to the target device, with a first data format; recognizing the first operation instruction and the first data format; determining that the one of the plurality of the input devices is a first input device corresponding to the first data format; and providing to a user of the target device a recommendation for a second input device, a type of the second input device being different from a type of the first input device, when it is determined that a type of the first operation instruction is identical to a type of a second operation instruction received from the second input device earlier than the reception of the first operation instruction. |
| US09721568B1 |
Signal processing based on audio context
Described herein are systems, methods, and apparatus for determining audio context between an audio source and an audio sink and selecting signal profiles based at least in part on that audio context. The signal profiles may include noise cancellation which is configured to facilitate operation within the audio context. Audio context may include user-to-user and user-to-device communications. |
| US09721566B2 |
Competing devices responding to voice triggers
At a first electronic device with a display and a microphone: sampling audio input using the first microphone; in accordance with the sampling of audio input using the first microphone, sending stop instructions to a second electronic device with a second microphone, the second electronic device external to the first electronic device, wherein the second electronic device is configured to respond to audio input received using the second microphone, and wherein the stop instructions instruct the second electronic device to forgo responding to audio input received using the second microphone, wherein responding to audio input received using the second microphone comprises providing perceptible output. |
| US09721564B2 |
Systems and methods for performing ASR in the presence of heterographs
Systems and methods for performing ASR in the presence of heterographs are provided. Verbal input is received from the user that includes a plurality of utterances. A first of the plurality of utterances is matched to a first word. It is determined that a second utterance in the plurality of utterances matches a plurality of words that is in a same heterograph set. It is identified which one of the plurality of words is associated with a context of the first word. A function is performed based on the first word and the identified one of the plurality of words. |
| US09721560B2 |
Cloud based adaptive learning for distributed sensors
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sound parameter information is extracted from the analog signal and compared to a sound parameter reference stored locally with the sound recognition sensor to detect when the signature sound is received in the analog signal. A trigger signal is generated when a signature sound is detected. A portion of the extracted sound parameter information is sent to a remote training location for adaptive training when a signature sound detection error occurs. An updated sound parameter reference from the remote training location is received in response to the adaptive training. |
| US09721559B2 |
Data augmentation method based on stochastic feature mapping for automatic speech recognition
A method of augmenting training data includes converting a feature sequence of a source speaker determined from a plurality of utterances within a transcript to a feature sequence of a target speaker under the same transcript, training a speaker-dependent acoustic model for the target speaker for corresponding speaker-specific acoustic characteristics, estimating a mapping function between the feature sequence of the source speaker and the speaker-dependent acoustic model of the target speaker, and mapping each utterance from each speaker in a training set using the mapping function to multiple selected target speakers in the training set. |
| US09721555B2 |
Vibration damping material
A material for audio equipment housing containing a polylactic acid resin composition containing a polylactic acid resin, a plasticizer, an organic crystal nucleating agent, and an inorganic material, wherein the content of the plasticizer is from 1 to 50 parts by mass based on 100 parts by mass of the polylactic acid resin; and a vibration-damping material containing a polylactic acid resin composition containing a polylactic acid resin, a plasticizer, an organic crystal nucleating agent, and an inorganic material, wherein the content of the plasticizer is from 1 to 50 parts by mass based on 100 parts by mass of the polylactic acid resin. The material of the present invention can be suitably used as materials for audio equipment of, for example, speakers, television, radio cassette players, headphones, audio components, or microphones, and manufactured articles, such as electric appliances, transportation vehicles, construction buildings, and industrial equipment, or parts or housing thereof. |
| US09721554B2 |
Detachable fingergrip whistle system
A whistle system that enables an official or other user to not only have the whistle in a secure position for quick and easy use while also enabling the user to be able to use both hands as well. In particular, the whistle system includes a fingergrip that allows the user to quickly move the the whistle in position for use in a natural motion, while allowing the fingergrip to then quickly separate from the whistle to allow both hands of the user to be utilized. Alternatively, the whistle allows individuals with restricted movement in one arm to still officiate. A user having restricted movement in one arm can simply wear the whistle on one hand, move it into position in the mouth to be blown, and then quickly separated from the whistle to allow the signal to be indicated with one hand. The whistle system includes a whistle with a fingergrip. The fingergrip is securely attached to the whistle by a securement system that also allows the fingergrip to be separated from the whistle with an application of force. |
| US09721551B2 |
Machines, systems, processes for automated music composition and generation employing linguistic and/or graphical icon based musical experience descriptions
Automated music composition and generation machine, systems and methods, and architectures that allow anyone, without possessing any knowledge of music theory or practice, or expertise in music or other creative endeavors, to instantly create unique and professional-quality music, synchronized to any kind of media content, including, but not limited to, video, photography, slideshows, and any pre-existing audio format, as well as any object, entity, and/or event, wherein the system user only requires knowledge of ones own emotions and/or artistic concepts which are to be expressed in a piece of music that will ultimately composed by the automated composition and generation system of the present invention. |
| US09721549B2 |
Drum stand basket with spring adjustment and other features
Drum stands and drum stand baskets, including those for use with a snare drum, are described. Drum stands and drum stand baskets according to the present disclosure can include an adjustment feature which enables the basket to fit differently sized drums. Additionally, drum stands and drum stand baskets according to the present disclosure can include elements which result in less interference with the sound of a snare drum compared to a snare drum in a prior art drum stand. Finally, embodiments of the present disclosure can be compacted for easy storage or transport. |
| US09721543B1 |
3-point separable guitar neck attachment system
A 3-point neck attachment system is disclosed where the neck of a guitar is mounted on a guitar body with the neck and body making contact at three points, each contact point consisting of a screw-adjustable member and a contact surface. Two screw-adjustment members are located in the neck pocket of the guitar body and allow fine adjustment of neck yaw angle and overall scale length. A third screw-adjustable member is mounted vertically in the heel of the neck and allows fine adjustment of the neck angle. The geometry of the contact surfaces can be configured to allow the neck to be easily and securely mounted to the guitar body without fasteners, employing only the strings' tension. When combined with a quick string de-tensioning mechanism, the fastener-free neck joint allows the guitar to be quickly disassembled, either for transport or rapid substitution of interchangeable guitar components, and then to be easily and rapidly re-assembled to pitch and precisely adjusted for optimum playing. The neck attachment further allows the guitar to be sold as a kit of parts that can be easily, quickly and precisely assembled by the user. |
| US09721539B2 |
Image display system, image display apparatus, and control method thereof
Upon receiving a communication switching instruction from a first wireless access point used for communication with an image processing apparatus, an image display apparatus disconnects communication with the first wireless access point. Simultaneously, the image display apparatus transmits, to a second wireless access point, a link request to establish communication with the second wireless access point of a new communication destination included in the switching instruction. The image display apparatus displays, on a display unit, a captured image continuously acquired from am image capturing unit until switching from the first wireless access point to the second wireless access point finishes as communication destination switching. |
| US09721538B2 |
Information display apparatus, information display system, control method thereof, and program
An information display system capable of reducing a trouble about display caused by display of content information corresponding to numerous markers and reducing process loads and a control method of the information display system are provided. In this system, a movement speed and a movement direction of a client apparatus operated by a user are detected, and a size and a position of a marker recognition area for recognizing a marker in an imaged image are determined according to the detected movement speed and the detected movement direction. Then, the content information corresponding to the marker recognized in the marker recognition area is superposed on the imaged image and output to a display screen. |
| US09721536B2 |
Display apparatus with touch detection function and electronic apparatus
A display apparatus with a touch detection function includes: a substrate; a display area including a plurality of pixels; a touch detection electrode including a plurality of small electrode portions; a plurality of wiring portions electrically coupling the small electrode portions to a terminal portion formed; and a plurality of drive electrodes forming capacitance between the drive electrodes and the touch detection electrode. The small electrode portions each include one conductive thin wire in which one first thin wire segment and one second thin wire segment are coupled in a first direction, the first thin wire segment makes a first angle with respect to the first direction, the second thin wire segment makes a second angle with respect to the first direction, and the wiring portions each include the one first thin wire segment and the one second thin wire segment that are coupled in the first direction. |
| US09721532B2 |
Color chart detection apparatus, color chart detection method, and color chart detection computer program
A color chart detection apparatus that detects a color chart from an image representing the color chart having a plurality of palettes arranged in a predefined order is provided. The color chart detection apparatus: extracts any pixel having a color component corresponding to each designated one of a predetermined number of palettes; selects at least three palettes to form a first group and, when a combination of pixels selected on a palette-by-palette basis from among the pixels extracted for the respective palettes included in the first group is arranged in the predefined order, detects each of the pixels included in the combination as being a candidate pixel; and based on the candidate pixel, computes color information representing color of the palette corresponding to the candidate pixel on the image and position information representing position of the corresponding palette on the image. |
| US09721529B2 |
Dual screen display for mobile computing device
A mobile computing device is disclosed for displaying backlight and diffuse reflecting information. The mobile computing device is configured to include a processor, a first LCD display unit connected to the processor, and a second diffuse reflecting display unit connected to the processor. The mobile computing device is further provided with a display panel interface, such as a mouse or a gravity detecting device like an accelerometer, configured to detect a property for activating a display type. The processor is configured to send information to be displayed to the first display unit or the second display unit or both depending on the display type property detected. |
| US09721528B2 |
Processing system display controller interface to programmable logic
In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic data to the programmable logic. |
| US09721524B2 |
Power supply circuit, display panel driver and display device incorporating the same
A semiconductor integrated circuit includes a power line and a power supply circuitry. The power supply circuitry includes: a first power supply circuit operating on a first power supply voltage and having an output connected with the power line; and a second power supply circuit operating on a second power supply voltage higher than the first power supply voltage and having an output connected with the power line. The first power supply circuit is configured to drive the power line to a first preset, voltage. The second power supply circuit is configured to drive the power line to a second preset voltage lower than the first preset voltage. The second power supply circuit is configured not to decrease a third power supply voltage generated on the power line when the third power supply voltage is higher than the second preset voltage. |
| US09721519B2 |
Display device and electronic device
According to one embodiment, a display device includes first interconnects, second interconnects, an electrode layer, pixel electrodes, a display layer and a controller. The first interconnects extend in a first direction and are arranged in a second direction. The second interconnects extend in the second direction and are arranged in the first direction. The electrode layer is aligned with a plane including the first and the second direction, and has openings. The second interconnects include a first signal line of a first color and a second signal line of the first color most proximal to the first signal line. The controller performs a first operation of supplying signals of a first polarity to the first and the second signal lines. The controller performs a second operation of supplying signals of a second polarity to the first and the second signal lines. |
| US09721515B2 |
Liquid crystal display panel and grayscale voltage compensating method thereof
A liquid crystal display panel and a grayscale voltage compensating method thereof are provided. The compensating method includes: obtaining an actual voltage distribution of a common voltage on a common electrode; and compensating positive polarity grayscale voltages as well as negative polarity grayscale voltages of respective pixel electrodes according to the actual voltage distribution to make that: for a same grayscale value, a difference value between the compensated positive polarity grayscale voltage of each pixel electrode and the common voltage on an opposing position of the pixel electrode on the common electrode is equal to a difference value between the compensated negative polarity grayscale voltage of the pixel electrode and the common voltage on the opposing position. By the above method, the invention can eliminate the flicker phenomenon when the liquid crystal display panel is displaying and therefore the display effect is improved. |
| US09721513B2 |
NAND gate latched driving circuit and NAND gate latched shift register
The invention provides a NAND gate latched driving circuit and a NAND gate latched shift register. The NAND gate latched driving circuit includes multiple cascade connected shift register circuits, each of the shift register circuits including a clock control transmission circuit and a NAND gate latch circuit. The clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a driving pulse of a former stage to the NAND gate latch circuit, the driving pulse then is latched by the NAND gate latch circuit. The NAND gate latch circuit further is triggered by a subsequent second clock pulse of a first clock signal to output the latched driving pulse. By the above solution, the NAND gate latched driving circuit of the invention is suitable for CMOS process and can achieve low power consumption and wide noise tolerance. |
| US09721510B2 |
Gate driving unit for outputting gate driving signals of two rows of pixel units, gate driving circuit thereof, and display device thereof
A gate driving unit includes an input circuit, a pull-up circuit, a reset circuit, and an output circuit. The pull-up driving signals received by the input circuit include the gate driving signals for pixel units of row n−2 and row n+4. The reset driving signals received by the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8. The gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6. Where, n is a positive integer and nε[3,∞). The gate driving unit can output gate driving signals of two rows of pixel units and thus has a high service efficiency. An area occupied by a gate driving circuit made of the gate driving units is reduced, and a driving efficiency of the gate driving circuit is increased. |
| US09721507B2 |
AMOLED pixel driving circuit and pixel driving method with compensation of threshold voltage changes
The present invention provides an AMOLED pixel driving circuit and a pixel driving method. The AMOLED pixel driving circuit utilizes a 5T2C structure, comprising a first, a second, a third, a fourth and a fifth thin film transistors (T1, T2, T3, T4, T5), a first, a second capacitors (C1, C2) and an organic light emitting diode (OLED), and the first thin film transistor (T1) is a drive thin film transistor; and a first, a second and a third global signal (G1, G2, G3) are involved, and the three and the scan signal (Scan) are combined with one another and correspond to an initialization stage (1), a data signal writing stage (2), a threshold voltage compensation stage (3) and a drive stage (4) one after another. The data writing signal stage (2) and the threshold voltage compensation stage (3) are separately implemented. The threshold voltage changes of the drive thin film transistor and the organic light emitting diode can be effectively compensated by source following of the drive thin film transistor to make the display brightness of the AMOLED more even and to raise the display quality. |
| US09721506B2 |
Electro-optical device and electronic apparatus
An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines. |
| US09721503B2 |
Display device to correct a video signal with inverse EL and drive TFT characteristics
According to one embodiment, a display device includes a plurality of pixels arranged in a matrix on a substrate, each including a luminescent element and a drive transistor configured to supply current to the luminescent element for light emission, and a panel characteristics correction unit configured to correct for display a video signal supplied from outside, to be supplied to a respective one of the pixels, and the panel characteristics correction unit includes an EL characteristics correction unit configured to correct the video signal with inverse luminescent characteristics of the luminescent element, and a TFT characteristics correction unit configured to correct the video signal with inverse drive characteristics of the drive transistor. |
| US09721502B2 |
Organic light-emitting diode display with compensation for transistor variations
A display may include an array of organic light-emitting diode display pixels having transistors characterized by threshold voltages subject to transistor variations. Compensation circuitry may be used to measure at transistor threshold voltage for a pixel. The threshold voltage may be sampled by controlling the pixel to sample the threshold voltage onto a capacitor at the pixel. The compensation circuitry may include sense circuitry that may be operated in combination with the pixel to transfer charge from the capacitor to the sense circuitry such that the threshold voltage is produced at an output of the sense circuitry. The compensation circuitry may generate compensation data based on the measured threshold voltage. During display operations, data circuitry may receive digital image data and process the digital image data along with the compensation data to generate analog data signals for the pixel. |
| US09721501B2 |
Organic light-emitting display panel, organic light-emitting display apparatus, and method of repairing the organic light-emitting display panel
An organic light-emitting display panel including a plurality of pixels arranged at a display area in column and row directions, the plurality of pixels being configured to receive power voltages; a voltage line associated with a pixel column, the voltage line being configured to apply a power voltage to the plurality of pixels included in the pixel column, the power voltage being supplied from a power line; and an auxiliary line coupled to a center node of the voltage line, the center node being located at a middle point of the voltage line, wherein the power voltage supplied from the power line is configured to be applied to the voltage line through the center node. |
| US09721497B2 |
Organic light emitting display device
An organic light emitting display device includes a plurality of pixels, each of the plurality of pixels including: a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color that is different from the first color; a third sub-pixel configured to emit light of a third color that is different from the first and second colors; and a transmission sub-pixel configured to selectively transmit external light in response to an electrical signal. |
| US09721496B2 |
Display panel and display device
A display panel and a display device, where, the display panel includes a trigger signal controller, and the trigger signal controller is configured to convert N primary trigger signals generated by a first driving unit into 2N secondary trigger signals according to a display control signal generated by a second driving unit, and sequentially outputting the 2N secondary trigger signals to 2N gate controlling circuits, each of the 2N gate controlling circuits is configured to drive a group of pixels in a display region, where, rows of pixels respectively from different groups of pixels are alternately arranged, the secondary trigger signals are configured to control gate controlling circuits to simultaneously drive two paired groups of pixels under a first display mode, and alternately drive two paired groups of pixels under a second display mode. |
| US09721495B2 |
Methods for driving electro-optic displays
An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme. |
| US09721494B2 |
Controller
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal. |
| US09721490B2 |
Dual-screen display and display method
A dual-screen display and a display method. The dual-screen display comprises: a display unit, a control unit and controllable light-transmitting bodies. Each display unit comprises at least three sub-pixel units. The controllable light-transmitting bodies are distributed on an upper surface and a lower surface of the sub-pixel units. The control unit is used for controlling, according to an instruction of a user, a control signal applied to the controllable light-transmitting bodies, so as to control the transparency of the controllable light-transmitting bodies. The controllable light-transmitting bodies are distributed on the two surfaces of the sub-pixel unit, and a control signal is applied according to an instruction of the user, so that the controllable light-transmitting bodies present corresponding transparency, thereby respectively controlling light of the sub-pixel unit irradiated to the two surfaces. |
| US09721488B2 |
Device for retrofitting automobile window flag assemblies to surfaces other than automobile windows
Disclosed is a mounting assembly adapted for retrofitting automobile window flags on surfaces other than automobile windows. The device includes a continuous bracket having two opposing ends that are interconnected by a flexible hinge positioned there between. The first opposing end of the continuous bracket is configured to receive and carry a slotted portion of the automobile window flag assembly and the second opposing end of the continuous bracket has a securing member formed thereon that is configured to secure the automobile window flag assembly to the device when the two opposing ends of the continuous bracket are fastened to one another. |
| US09721486B2 |
Frame panel for three-dimensional sign board
A frame panel for a three-dimensional sign board, a three-dimensional sign board including the panel, and a manufacturing method therefor. The frame panel includes a band-shaped frame panel which is cut into a predetermined length and wound in the form of a coil so that the frame panel can be bent and shaped into a desired pattern such as a character; and hitch units on which an upper panel is fixated, which are formed along the longitudinal direction of the frame panel and which are spaced apart from each other on two ends of one side of the frame panel. The hitch units are made of a soft synthetic resin material, which is the same material as used for the upper panel. |
| US09721478B2 |
Integrated live and simulation environment system for an aircraft
A method and apparatus comprising an aircraft, a network interface, a display system, a sensor system, and a computer system. The network interface, the display system, the sensor system, and the computer system are associated with the aircraft. The network interface is configured to exchange data using a wireless communications link. The computer system is configured to run a number of processes to receive simulation data received through the network interface over the wireless communications link. The computer system is configured to generate simulation sensor data using the simulation data. The computer system is configured to receive live sensor data from the sensor system associated with the aircraft. The computer system is also configured to present the simulation sensor data with the live sensor data on the display system. |
| US09721468B2 |
Navigation aid for a motor vehicle with autopilot
A method for operating a navigation system for a motor vehicle with autopilot is disclosed, wherein the autopilot is designed to automatically carry out longitudinal and lateral guidance of the motor vehicle in the activated state during a piloted journey without assistance from a driver. The navigation system determines, for a destination prescribed by the user, a route to the destination on the basis of navigation data. The roads on which the activation of the autopilot is likely to be possible is determined using traffic data and on the basis of a predetermined activation condition for the autopilot. |
| US09721467B2 |
LED traffic lamp control system
A traffic lamp and a method of controlling the traffic lamp based on a power signal are provided. The traffic lamp can include a controller and a light emitting element When a plurality of light emitting elements is included in the traffic lamp, each light emitting element is coupled with a separate controller. Each controller can be configured to include a predetermined light emitting timing sequence for the corresponding light emitting element. When the power signal is supplied to the traffic lamp, each controller determines a power signal characteristic such as a frequency or a period of the power signal and controls a light output of the light emitting element: based on the power signal characteristic and the light emitting timing sequence. A plurality of light emitting elements can be synchronized using the power signal applied to the traffic lamp. |
| US09721466B2 |
Method of pairing a remote control
Systems and methods are described for automatically pairing a remote control device with a target device (e.g., electronically controllable device). In one embodiment, IR communication data and auto-pairing discovery requests are transmitted from the remote control device to the target device. The target device may be configured to accept auto-pairing discovery requests during a predetermined pairing time window. The target device may be further configured to confirm whether received IR communication data and auto-pairing discovery requests were transmitted from the same remote control device. In other embodiments, the remote control device may be configured to receive data from the target device indicating one or more parameters for automatically initiating a pairing and validation process. The remote control device may be further configured to initiate a blackout period upon attempting a predetermined number of unsuccessful discovery operations with a target. |
| US09721460B2 |
In-vehicle surrounding environment recognition device
An in-vehicle surrounding environment recognition device includes: a photographic unit that photographs a road surface around a vehicle and acquires a photographic image; an application execution unit that recognizes another vehicle on the basis of the photographic image, and detects a relative speed of the other vehicle with respect to the vehicle; a reflection determination unit that, on the basis of the photographic image, determines upon presence or absence of a reflection of a background object from the road surface; a warning control unit that controls output of a warning signal on the basis of the result of recognition of the other vehicle; and a warning prevention adjustment unit that suppresses output of the warning signal on the basis of the relative speed of the other vehicle, if it has been determined that there is the reflection of the background object from the road surface. |
| US09721457B2 |
Global positioning system equipped with hazard detector and a system for providing hazard alerts thereby
The present invention relates to detectors of hazardous environmental conditions (e.g., smoke, gas, motion). Specifically, the invention relates to a hazard detector configured to transmit and/or receive information related to hazardous environmental conditions based at least in part on the location of the hazard detector as identified through one or more location based service means (e.g., global positioning systems (GPS), cellular triangulation, Internet IP geolocation). |
| US09721454B2 |
Method for protecting terminal devices and the terminal device thereof
The present disclosure relates to a method for protecting a terminal device and the terminal device thereof. The method includes: obtaining status information of a terminal device plugged with an earphone; determining whether the status information meets a preset condition; and activating an alarm mode of the terminal device when the status information meets the preset condition. According to the present disclosure, given that activating the alarm mode of the terminal device is based on the status information of the terminal device, the alarm mode of the terminal device can be activated based on environment information of the terminal device without a user manually activating the alarm mode of the terminal device, therefore user experience is improved. Moreover, the security of the terminal device is further improved by avoiding an incident of the user forgetting to start the alarm mode, thus further protecting the terminal device. |
| US09721453B2 |
Controlling the spread of pathogens
Systems, methods, and computer program products to perform an operation comprising receiving, based on a unique identifier of an identification device in a room, clinical information of a first patient present in the room, receiving a unique identifier from an identification device associated with a garment worn by a health care professional in the room, receiving a history of the garment based on the unique identifier, and upon determining that the history of the garment violates a predefined rule, outputting a notification of the violation. |
| US09721448B2 |
Wireless communication systems for underground pipe inspection
Wireless communication system for underground pipeline inspection. The system includes a plurality of sensor nodes moved by robots within the pipeline and each sensor node includes a radio transceiver. A plurality of spaced apart, above ground relay nodes are deployed along the pipeline, each relay node including a radio transceiver for communication with the sensor nodes. A remote monitoring center is provided in communication with the relay nodes, whereby a leak detected by a sensor node is communicated to the remote monitoring center. Each sensor node may further include a microcontroller, an accelerometer and a timer. |
| US09721438B2 |
Gaming system with dynamically defined win lines and a method of use
A gaming system includes a display, a memory, and a processor. The display includes a display area having display positions. The memory stores symbols and normal win line definitions for use in a base game, and stores win line elements for use in a feature game. The processor is coupled to the memory and is configured to (a) randomly select a set of symbols for display at the display positions, (b) award a base game payout when the set of symbols satisfies at least one normal win line definition, (c) randomly select a set of win line elements for display at the display positions, (d) define a special win line including contiguous win line elements of the set of win line elements, and (e) award a feature game payout when the set of symbols satisfies the special win line. |
| US09721433B2 |
Methods and systems for generating a lottery ticket
A method of generating a lottery ticket comprises the steps of: providing a succession of selection stages; providing for each stage two or more selection options; said selection options comprising a selection area which in response to a lottery player's interaction reveals either a winning or a losing indicator; wherein for each stage at least one of the selection options is a winning selection and at least one of the options is a losing selection. |
| US09721426B2 |
Autoplay mechanism for wagering game systems
A wagering game system and its operations are described herein. In some embodiments, the operations can include initiating a wagering game title for presentation on a display device of a gaming machine, and receiving, from the gaming machine, player input indicating autoplay settings selected by a player for the wagering game title. The operations can also include initiating an autoplay mode for the wagering game title in response to receiving an autoplay trigger from the gaming machine, managing the autoplay mode for the player according to the autoplay setting selected by the player, and generating results for each wagering game of the wagering game title played during the autoplay mode. The operations can further include monitoring game events associated with the wagering games played during the autoplay mode to determine when to stop the autoplay mode, and stopping the autoplay mode for the player based on the autoplay settings selected by the player. |
| US09721424B2 |
Supplementary mode of an interleaved wagering system
An interleaved wagering system is disclosed. The system includes an interactive controller constructed to communicate application telemetry associated with an interactive application provided by the interactive controller. The system also includes a wager controller constructed to communicate a wager result associated with a received wager request. The system also includes the application controller operatively connected to the interactive controller and the wager controller, and constructed to: receive application telemetry; upon receiving application telemetry, determine whether to trigger a supplementary mode; when triggering the supplementary mode is determined, communicate a notification to provide a supplementary mode session. The interactive controller is further constructed to: provide the supplementary mode session upon receiving the supplementary mode notification; communicate results of the supplementary mode session. The application controller is further constructed to: receive the results of the supplementary mode session; and when the received results are successful, communicate a request for benefits. |
| US09721415B2 |
Magnetic head for banknote detection
A magnetic currency verification head may include a magnetoresistive sensor chip, and a magnetic bias unit disposed on the side of the magnetoresistive sensor chip away from the detection surface of the magnetic currency verification head, and separated from the magnetoresistive sensor chip; the magnetoresistive sensor chip comprises a gradiometric bridge circuit that includes magnetic sensor elements; the sensitive direction of the magnetic sensor elements is parallel to the detection surface of the magnetic currency verification head; and the magnetic bias unit has a recessed magnetic structure configured such that the magnetic field generated by the magnetic bias unit only has a small magnetic field component in the direction parallel to the detection surface, thereby enabling the magnetic sensor elements to operate in their linear range. As a result, the magnetic currency verification head has high sensitivity and signal-to-noise ratio. |
| US09721412B2 |
Door lock and arrangement for transferring power and information to door lock
Lock arrangement including a counterpart of the lock and a lock with a lock case. The lock case, which can be installed in a door, includes a locking latch and a latch mechanism, which includes an electrical device for opening and/or closing the locking latch. The counterpart of the lock can be installed in the frame of the door. A device for wirelessly sending electrical power to the lock case and/or into connection with the lock case is arranged in the counterpart of the lock; a mechanism is arranged in connection with the lock case for wirelessly receiving electrical power from the device for sending electrical power that is arranged in connection with the counterpart of the lock. Electrical power is arranged to be transmitted from the device for sending electrical power to the mechanism for receiving electrical power, when the lock case and the counterpart of the lock are at a certain distance from each other. The mechanism for receiving and device for sending electrical power are also arranged to transfer encrypted information relating to the operation of the lock. |
| US09721411B2 |
Proximity-initiated physical mobile device gestures
An interaction spot is provided that may detect the presence of an electronic device such as a smartphone. A user may make a physical motion with the smartphone proximal to the interaction spot such as moving it upward. The interaction spot may communicate with a second device such as a light or a household appliance. A setting of the second device may be adjusted based on the motion of the electronic device. |
| US09721406B2 |
System and method for door unlocking using a payment account
Disclosed herein are systems, methods, and computer-readable storage media for door unlocking using a payment account. The system receives registration of a user at a business entity, such as a hotel and receives identification of a payment account associated with the user. Then the system establishes a policy such that the payment account is used as a key to unlock a door at the business entity, such as a hotel room. The system receives data associated with the payment account by receiving a card swipe at the hotel room door using a card associated with the payment account or via a wireless communication at the door. The door is unlocked based on validation of the data provided at the door. |
| US09721402B2 |
Access control apparatus with modular encoder subassembly
Apparatuses are provided for performing physical access control using various types of encoding technologies by removably incorporating modular encoder subassemblies. An access control apparatus includes access control electronics and at least one docking bay or slot for removably housing at least one modular encoder unit. The encoder unit can be removably house in the docking bay or slot of the access control apparatus and be removably linked, communicatively and/or physically, to the access control electronics when housed in the access control apparatus, and can interface with and write or read information to or from a credential. When removably housed in the docking bay or slot, the encoder unit can receive identity data from the access control electronics and bind the identity data to the credential. |
| US09721396B2 |
Computer and computer system for controlling object manipulation in immersive virtual space
Action of a head around which an HMD main body is worn is related to manipulation of an object in an immersive three-dimensional virtual space. Information on a sight in a virtual space may be determined based on information on head inclination sensed with an inclination sensor; an image of the sight in the virtual space may be generated based on the sight information in order to display the sight image in the head mounted display; an object placed on a reference sight line in the virtual space may be identified, the reference sight line being determined in correspondence with a predetermined position in the sight image; and an object the identified object may be manipulated in response to the identification of the object in accordance with action of inclining in a predetermined direction the head around which the head mounted display is worn. |
| US09721385B2 |
Generation of three-dimensional imagery from a two-dimensional image using a depth map
A method for generating stereoscopic images includes obtaining image data comprising a plurality of sample points. A direction, a color value, and a depth value are associated with each sample point. The directions and depth values are relative to a common origin. A mesh is generated by displacing the sample points from the origin. The sample points are displaced in the associated directions by distances representative of the corresponding depth values. The image data is mapped to the mesh such that the color values associated with the sample points are mapped to the mesh at the corresponding directions. A first image of the mesh is generated from a first perspective, and a second image of the mesh is generated from a second perspective. The first and second images of the mesh may be caused to be displayed to provide an illusion of depth. |
| US09721380B2 |
Removing redundant volumetric information from a volume-based data representation
An environment includes different objects that are each made up of one or more 3-dimensional volumes. These volumes can overlap one another, resulting in situations in which a particular volume that is overlapped is redundant and can be removed from the set of volumes describing the environment. A two-phase approach is applied in determining whether a particular volume is redundant. In the first phase, a candidate list of source volumes is quickly generated with a small amount of computational effort. In the second phase, the source volumes on the candidate list are analyzed to determine whether the particular volume is fully overlapped by one or a combination of the source volumes. |
| US09721378B2 |
Display interposing a physical object within a three-dimensional volumetric space
A visual display unit creating a three-dimensional volumetric space. The display includes a first screen in a first focal plane, wherein the first screen displays a first image. The display includes a second screen in a second focal plane distinct from the first focal plane, wherein the second screen displays a second image, and wherein the second screen at least partially overlaps the first screen. The display includes a physical object located between the first screen and said second screen, wherein at least one of the first and second images is displayed in response to a placement of the physical object. |
| US09721373B2 |
Generating instructions for nonverbal movements of a virtual character
Programs for creating a set of behaviors for lip sync movements and nonverbal communication may include analyzing a character's speaking behavior through the use of acoustic, syntactic, semantic, pragmatic, and rhetorical analyses of the utterance. For example, a non-transitory, tangible, computer-readable storage medium may contain a program of instructions that cause a computer system running the program of instructions to: receive a text specifying words to be spoken by a virtual character; extract metaphoric elements, discourse elements, or both from the text; generate one or more mental state indicators based on the metaphoric elements, the discourse elements, or both; map each of the one or more mental state indicators to a behavior that the virtual character should display with nonverbal movements that convey the mental state indicators; and generate a set of instructions for the nonverbal movements based on the behaviors. |
| US09721371B2 |
Systems and methods for stitching metallographic and stereoscopic images
A method includes receiving a first image and a plurality of other images of a planar surface of a specimen. The method also includes identifying first scale-invariant features in the first image. The first scale-invariant features are based on a scale-invariant feature transform of the first image. The method includes storing the first scale-invariant features in a grouping. The method includes, for each respective image of the plurality of other images, identifying scale-invariant features based on a scale-invariant feature transform of the respective image; matching the scale-invariant features to the grouping; based on the matching, determining a planar homography of the respective image with respect to the grouping; and adding the scale-invariant features of the respective image to the grouping. The method also includes stitching the first image and the plurality of other images into a composite image based on the planar homographies. A field of view of the specimen in the composite image is greater than a field of view of at least one of the first image or the plurality of other images. |