| Document | Document Title |
|---|---|
| US09673857B2 |
Frequency hopping sequence generation
Techniques for frequency-hopping sequence-generation are described herein. In one example, a sequence of pseudo random numbers may be used to generate a scrambling sequence. The scrambling sequence may be used to map an unscrambled sequence of channels into a scrambled sequence of channels. Channel-repeats may be detected in the scrambled sequence of channels and resolved. Channel whitening may be performed to reduce channel overuse resulting from the channel-repeat resolutions. The scrambled sequence of channels may be provided to a radio to enable the radio to tune to the channels indicated by the scrambled sequence of channels. |
| US09673855B2 |
Adaptive transmission methods for multiple user wireless networks
An exemplary wireless communication network that includes a base that communicates with remote units located in a cell of the network. The base concatenates information symbols with a preamble corresponding to a destination remote unit. One or more remote units communicating with the base each concatenates information symbols with a preamble corresponding to that remote unit. An adaptive receiver system for a base unit rapidly adapts optimal despreading weights for reproducing information symbols transmitted from multiple remote units. A transmitter system for a base unit concatenates information symbols with a preamble associated with a remote unit in the cell. An adaptive receiver system for a remote unit in a communication network rapidly adapts optimal weights for reproducing a signal transmitted to it by a specific base unit in the network. |
| US09673853B2 |
Cascode power amplifier with voltage limiter
Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold. |
| US09673851B2 |
Retaining device for a mobile communication device
A retaining device for a mobile device having an accommodating module, into which the device can be inserted and on which a guide, support, and/or positioner for the device and a connector for electrically contacting the communication device are provided, and having a rotation module, on which the accommodating module is retained. The accommodating module can be rotated together with the rotation module about a first pivot axis from and to a first operating position and a second operating position. A housing is provided, in which the accommodating module and the rotation module are provided at least in some sections and on which the rotation module is retained. The accommodating module can be moved from an accommodating position, in which the device can be inserted into the accommodating module, to the first operating position and/or to the second operating position by rotating the accommodating module about a second pivot axis. |
| US09673849B1 |
Common mode extraction and tracking for data signaling
Systems, apparatuses, and methods for performing common mode extraction for data communication are disclosed. A circuit is configured to receive a single-ended data signal on a first input port and couple the data signal to a positive input terminal of a receiver component. The circuit is also configured to receive a differential clock signal on second and third input ports and generate a reference signal from the differential clock signal. In one embodiment, the reference signal is generated from an average of the differential clock signal. The circuit is configured to couple the reference signal to a negative input terminal of the receiver component. In one embodiment, the receiver component is an amplifier. |
| US09673847B1 |
Apparatus and methods for transceiver calibration
Apparatus and methods for transceiver calibration are provided. In certain configurations, a transceiver includes a transmit channel and an observation channel. The transmit channel includes a transmit mixer that up-converts a transmit signal by a first or transmit local oscillator frequency. The observation channel includes an observation mixer that down-converts an observed signal from the transmit channel by a second or observation local oscillator frequency that is offset from the first local oscillator frequency. By observing the transmit channel using a local oscillator frequency that is offset relative to the transmit channel's local oscillator frequency, the observation channel can observe transmit channel impairments substantially independently from observation channel impairments. |
| US09673842B2 |
Combining multiple desired signals into a single baseband signal
A transceiver for receiving multiple desired signals is described. The transceiver includes a first downconverter that receives a first received signal. The transceiver also includes a second downconverter that receives the first received signal. The transceiver further includes a first adder that receives an output of the first downconverter and a second received signal. The transceiver also includes a second adder that receives an output of the second downconverter. |
| US09673840B2 |
Turbo product codes for NAND flash
A method of encoding data in a data block includes generating a first XOR parity from an XOR of all data bits in the data block and an XOR of all row parities of all rows in the data block besides a last row, storing the first XOR parity in the last row, and generating a second XOR parity from an XOR of all column parities of all columns in the data block and an XOR of a parity of the last row. |
| US09673838B2 |
Parallel bit interleaver
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. |
| US09673826B2 |
Receiving device
According to one embodiment, a receiving device includes a first PLL circuit, a second PLL circuit, and a control circuit. The first PLL circuit includes a first VCO and extracts a first clock from a received first packet. The second PLL circuit includes a second VCO and outputs a second clock acquired by multiplying the received clock by N. The control circuit applies a control signal of the second VCO to a first line controlling the first VCO during a first time from start of reception of the first packet. |
| US09673822B2 |
Single wire interface
A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase. |
| US09673820B2 |
Low latency glitch-free chip interface
A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output. |
| US09673819B2 |
Metastability glitch detection
This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal. |
| US09673818B2 |
Semiconductor integrated circuit with data transmitting and receiving circuits
A data transmitting method used in a semiconductor device having a controller and a transmitter is described. A first write command is output by the controller and then a second write command is output by the controller. An interval time between the first write command and the second write command is calculated. The transmitter is activated by the controller and a first data is transmitted by the transmitter in accordance with the first write command, and then the transmitter is inactivated based on the interval time. Then the transmitter is activated when the transmitter is inactivated. Then, the second data is transmitted by the transmitter in accordance with the second write command. |
| US09673817B2 |
Mobile terminal and control method thereof
A method for operating a terminal according to an embodiment includes detecting an object that contacts the terminal, determining an operation of the terminal corresponding to the detected object, and performing the determined operation of the terminal. |
| US09673803B2 |
Semiconductor device, and on-vehicle electronic device and automobile each including semiconductor device
A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active. The temperature detector TD1 sets the temperature difference detection signal dt_ot to inactive when the temperature difference Tdif between the output transistor temperature Ttr and the ambient temperature becomes equal to or less than a reference temperature difference Tdref2, and sets the over temperature detection signal at_ot to inactive when the output transistor temperature Ttr becomes equal to or lower than a reference temperature Tref2. |
| US09673799B2 |
Sensing circuit with reduced bias clamp
A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner. |
| US09673797B2 |
Peak detector using charge pump and burst-mode transimpedance amplifier
A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor. |
| US09673791B2 |
Schmitt trigger circuit and power supply monitoring apparatus
A Schmitt trigger circuit according to an embodiment includes a voltage dividing circuit that divides an input voltage and outputs a divided voltage, and a basic Schmitt trigger circuit that includes a transistor as a current controlling element and controls current flowing through a light emitting diode (LED) included in an external photocoupler on the basis of the output voltage of the voltage dividing circuit proportional to the input voltage. The voltage dividing circuit has a positive temperature coefficient. |
| US09673788B2 |
Input buffer with selectable hysteresis and speed
A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage. |
| US09673783B2 |
Adaptive continuous-time filter adjustment device
A device includes a controller and an adaptive continuous-time filter that includes a control input and a first array of elements. The controller generates a digital word responsive to a time constant and compares a select bit of the digital word to a corresponding reference word to generate a control bit. The controller includes a duplicate array of elements, and applies the control bit to an adjustable element of the duplicate array of elements to modify the time constant. The controller provides the output word to the control input of the adaptive continuous-time filter to generate a filter response that accounts for effects of semiconductor process variation in the first array of elements. |
| US09673782B1 |
Center frequency and Q tuning of biquad filter by amplitude-limited oscillation-based calibration
Certain aspects of the present disclosure provide methods and apparatus for calibrating a tunable active filter. One example apparatus is a filter circuit that generally includes a tunable active filter comprising at least one amplifier and a first feedback path coupled between an input and an output of the at least one amplifier, the first feedback path comprising at least one switch; and an amplitude limiter coupled to the tunable active filter and comprising at least one transistor disposed in a second feedback path coupled between the input and the output of the at least one amplifier. |
| US09673771B2 |
Multilayer resonator and multilayer filter
A multilayer filter includes a plurality of mutually coupled resonant circuits provided within a multilayer body. Capacitor internal electrodes, inductor internal electrodes, and inductor via electrodes, ground via electrodes, and input-output via electrodes are arranged within the multilayer body. The ground via electrodes and the input-output via electrodes are provided on a dielectric layer on a mounting surface, or a second dielectric layer on a first dielectric layer provided on the mounting surface. The capacitor internal electrodes arranged towards the side of the mounting surface do not overlap the input-output electrodes when viewed in plan view. With this configuration, degradation in frequency characteristics of a resonant circuit is effectively prevented by controlling one of an inductive component and a capacitive component of the resonant circuit. |
| US09673770B2 |
Frequency domain multiband dynamics compressor with spectral balance compensation
A multiband dynamics compressor implements a solution for minimizing unwanted changes to the long-term frequency response. The solution essentially proposes undoing the multiband compression in a controlled manner using much slower smoothing times. In this regard, the compensation provided acts more like an equalizer than a compressor. What is applied is a very slowly time-varying, frequency-dependent post-gain (make-up gain) that attempts to restore the smoothed long-term level of each compressor band. |
| US09673767B2 |
MEMS microphone and method of operating the MEMS microphone
The present invention concerns a MEMS Microphone (1) comprising, a transducer element (2) for providing an electrical signal, a first part (3) for receiving the electrical signal from the transducer element (2) and for providing a processed signal, a second part (4) for receiving the processed signal from the first part (3) and for providing an output signal of the MEMS microphone (1), and a gain control unit (5) that is enabled to adjust a gain setting of the first part (3) and to adjust a gain setting of the second part (4). Further, another aspect of the present invention concerns a method of operating said MEMS microphone (1) comprising the step of adjusting a gain setting of the first part (3) and adjusting a gain setting of the second part (4). |
| US09673766B1 |
Class F amplifiers using resonant circuits in an output matching network
The embodiments described herein provide class F amplifiers and methods of operation. So implemented, the class F amplifiers can be used to provide high efficiency amplification for a variety of applications, including radio frequency (RF) applications. In general, the class F amplifiers are implemented with at least one transistor and an output matching network, where the output matching network includes a plurality of resonant circuits configured to facilitate class F amplifier operation. In addition to facilitating class F amplifier operation, the plurality of resonant circuits can also be implemented with other circuit elements to provide output impedance transformation in a way that facilitates efficient amplifier operation. |
| US09673765B2 |
Concurrent dual-band signal amplifier
A signal amplifier includes a band suppression filter configured to suppress a preset band among bands included in an input signal, a first common source-type amplifier connected between a supply terminal of a driving voltage and a ground terminal and configured to amplify a first input signal separated from an output signal of the band suppression filter in a common input node to provide a first amplified signal to a common output node, a second common source-type amplifier configured to amplify a second input signal separated from the output signal of the band suppression filter in the common input node to provide a second amplified signal to the common output node, and an output matcher configured to match levels of impedance between the common output node and an output terminal and to transfer a combined signal to the output terminal. |
| US09673762B2 |
Amplifier with adjustable ramp up/down gain for minimizing or eliminating pop noise
A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier. |
| US09673757B2 |
Modified tunneling field effect transistors and fabrication methods
Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided. |
| US09673755B1 |
Controlling a switched capacitor bank in a voltage controlled oscillator for wireless sensor devices
In some aspects, a wireless sensor device includes a voltage controlled oscillator. The voltage controlled oscillator includes a resonator circuit, a multiplexer and control logic. The resonator circuit includes a switched capacitor bank operable to tune the resonator circuit. The multiplexer is communicatively coupled to the switched capacitor bank to select combinations of capacitor bank elements based on input values representing digital capacitance levels. The multiplexer includes a first multi-bit input configured to receive a first set of values representing a first combination of the capacitor bank elements; a second multi-bit input configured to receive a second set of values representing a second combination of the capacitor bank elements; and a multi-bit output configured to communicate the first or second set of values to the switched capacitor bank. The control logic is configured to generate the first and second sets of values for each of the digital capacitance levels. |
| US09673753B1 |
Voltage-controlled oscillator with improved tuning curve linearization
In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear. |
| US09673752B2 |
Photovoltaic array skirt and mounting hardware
A photovoltaic array skirt assembly, where the array skirt has a double-groove structure which can accommodate both a splice and a photovoltaic module mounting device. The splice is mounted within the inner channel of the double-groove structure to connect adjacent array skirt sections, and can be locked into the double groove structure to prevent adjacent array skirt sections from uncoupling. One or more photovoltaic module mounting devices are also located in the groove structure, within the outer channel of the double-groove structure, each of which can be further secured in the array skirt with anti-rotation element. |
| US09673751B2 |
Rotating furling catenary solar concentrator
The present invention relates to a rotating solar concentrating device wherein reflective sheets hung in a catenary trough shape capable of solar concentration may be protectively furled and balanced and rotated about a vertical axis. The reflective sheets may be furled to protect them from damage from wind, rain, and dust. In some embodiments, rotating parts of the device may be hung from supports above. In some embodiments, a furling mechanism may initiate protective furling in response to damaging environmental factors. Some embodiments may concentrate light on a photovoltaic cell wherein the photovoltaic cell is cooled by immersion in a heat pipe. In some embodiments, reflective surfaces may be supported by cables that are tensioned by a hanging, rotating ballast. In some embodiments, the device may be employed in a ganged array. In some embodiments, the invention may harvest wind energy as a vertical axis wind turbine (VAWT). |
| US09673749B2 |
Power equipment and harmonic suppression method in power equipment
Provided is a power equipment which obtains a power saving effect according to the operation of an electric motor by providing a harmonic suppression function on the side of a power trunk line for supplying power to the electric motor without changing the electric motor side. The power equipment includes an electric motor (14) which is supplied with power from a power trunk line (12) connected to a power source transformer (11) to be operated. A harmonic generation unit (13) is provided in the power trunk line (12) and generates a harmonic voltage having a phase opposed to but the same degree as that of a harmonic voltage of a degree acting as a braking force on a rotor (14-2) in a rotational magnetic flux of harmonics generated between a stator (14-1) and the rotor when the electric motor (14) is operated. |
| US09673746B2 |
Motor driving circuit, motor device, and electric vehicle
A motor driving circuit has a supply line connected to a DC power source, an inverter whose input side is connected to the supply line and whose output side is connected to a motor, a power switch inserted in the supply line for switching the supply line between conducting and cut-off states, a voltage detector for detecting a voltage between the direct-current power source and the power switch, and an insulation resistance detector for first detecting, based on a result of detection by the voltage detector with the power switch in the cut-off state, an insulation resistance on the preceding-stage side of the power switch and subsequently detecting, based on a result of detection by the voltage detector with the power switch in the conducting state, an insulation resistance on the succeeding-stage side of the power switch. |
| US09673745B2 |
Servomotor control system including a buffer servomotor with a plurality of windings
A servomotor control system of the present invention includes: a multiple number of first servomotors for driving axes in a machine tool or others; a multiple number of converters for converting AC voltage into DC voltage; a multiple number of first inverters for converting DC voltage into AC voltage; second servomotors for rotating inertial bodies; a multiple number of second inverters for converting DC voltage into AC voltage; and a servomotor control unit for controlling the multiple first servomotors and the second servomotors, and is constructed such that the number of the second servomotors is less than that of the multiple second inverters, and at least one of the second servomotors includes a multiple number of independent windings, and at least part of the multiple second inverters are connected to the multiple independent windings provided for one of the second servomotors. |
| US09673744B2 |
Operating state circuit for inverter and method for setting operating states of an inverter
The invention relates to an operating state circuit for actuating an inverter (3), which supplies an n-phase electrical machine (5) with an n-phase supply voltage via phase connections (4a, 4b, 4c), wherein n≧1, comprising an evaluation device (6) which is connected to the phase connections (4a, 4b, 4c) of the inverter (3) and which is configured to detect output voltages of the inverter (3) to the phase connections (4a, 4b, 4c) and to determine a speed of the electrical machine (5) on the basis of the detected output voltages, and an actuating device (7) which is coupled to the evaluation device (6) and which is configured to switch to an idle state or an active short-circuit in dependence on the determined speed of the inverter (3). |
| US09673742B2 |
Controlling magnetic flux in an automotive electric machine
A method of compensating for magnetic flux resulting from variance from a first electric machine to a second electric machine. A magnetic flux change for the first machine is calculated as a function of a flux difference between the first machine and the second machine. Operation of the first machine is controlled using the magnetic flux change. |
| US09673739B2 |
Machine type identification
For identifying the machine type of an alternating current machine, a direct current is first applied to the stator for aligning the d-axis of the rotor and the magnetic field direction of the stator. Secondly, a direct current is applied to the stator at a current angle which causes the rotors of a permanent magnet machine and a synchronous reluctance machine to exert torque in different directions. The torque direction of the rotor is detected and the machine type is identified based on the torque direction information. The machine type is recognized as a permanent magnet machine or a synchronous reluctance machine depending on the torque direction. If no torque is detected, then the machine type is recognized as an induction machine. |
| US09673738B2 |
Multi-battery pack for power tools
A power tool including a motor, a first battery pack, a second battery pack, a first switching element coupled between the first battery pack and the motor, a second switching element coupled between the second battery pack and the motor, and controller coupled to the first switching element and the second switching element. The controller includes a first pulse-width modulation (PWM) output coupled to the first switching element and a first PWM signal to selectively close the first switching element. The controller further includes a second PWM output coupled to the second switching element and a second PWM signal to selectively close the second switching element. |
| US09673735B2 |
Power converter
A power converter includes first through sixth switching elements, first through tenth diodes, first through fourth capacitors, and a controller. The first through fourth capacitors are connected in parallel with the first through fourth switching elements, respectively. The seventh diode is connected in series with the first capacitor and is connected inversely in parallel with the first switching element. The eighth diode is connected in series with the second capacitor and is connected in parallel with the second switching element. The ninth diode is connected in series with the third capacitor and is connected inversely in parallel with the third switching element. The tenth diode is connected in series with the fourth capacitor and is connected in parallel with the fourth switching element. |
| US09673733B2 |
Control apparatus for photovoltaic inverter
There is provided a control apparatus for a photovoltaic inverter. The control apparatus includes a system voltage detector, a DC voltage detector that detects a DC voltage applied to the inverter, an output voltage deficiency detector that detects an output voltage deficiency of the inverter based on the system voltage and the DC voltage, an output-current detector, an output-current distortion detector that detects distortion of the output current based on a harmonic included in the output current, a MPPT controller, and an output-current distortion controller that performs control to set the DC voltage applied to the inverter to a voltage at a power point less than a maximum power point when the output voltage deficiency is detected and the distortion of the output current is detected. |
| US09673730B2 |
Double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and modulation method
Provided are a double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and a modulation method. The circuit includes a three-phase main inverter circuit and a three-phase double auxiliary resonant commutator circuit. An A-phase double auxiliary resonant commutator circuit, an A-phase main inverter circuit, a B-phase double auxiliary resonant commutator circuit, a B-phase main inverter circuit, a C-phase double auxiliary resonant commutator circuit and a C-phase main inverter circuit are connected in parallel in sequence and simultaneously connected with a DC power supply in parallel. The present invention can achieve the separation of the resonant current of the double auxiliary resonant commutator circuit from the load current at the moment of current commutation, thereby effectively reducing the current stress of the auxiliary switching tubes and the efficiency can be greatly increased particularly under light load condition. |
| US09673729B2 |
Power processing methods and apparatus for photovoltaic systems
High power output may be obtained from a photovoltaic (PV) system by controlling each photovoltaic cell of a solar array individually to operate at its maximum power point. Each cell may have associated power electronics and control circuitry that may be integrated together on a chip which may be advantageously implemented in CMOS, enabling reductions in cost and size. A perturb and observe algorithm may be used to find the maximum power point by measuring the power produced at different operating points, and modifying the operating point in the direction of increased power production. In one aspect, performance of a perturb and observe algorithm may be improved in the presence of noise. |
| US09673728B2 |
Converter arrangement with a capacitance
A converter arrangement can include a first rectifier having an AC input and a DC output with two DC output poles, a capacitance (C) connected between the DC output poles of the first rectifier, a second rectifier having an AC input with two AC input poles and a DC output with two DC output poles, wherein the DC output of the second rectifier is connected between the DC output poles of the first rectifier. A magnetic amplifier includes at least one control winding (L2) and at least one AC winding (L11, L12), wherein the at least one control winding is connected between the DC output poles of the first rectifier, and wherein the at least one AC winding (L2) of the magnetic amplifier is connected in series with the AC input of the second rectifier. |
| US09673727B2 |
Switching power supply control circuit and switching power supply
A jitter control circuit, which reduces conducted EMI noise by giving jitter (frequency diffusion) to the operating frequency for driving a switching element, determines an operating frequency fc (e.g., 40 kHz) at which reduction effects change from a feedback voltage that represents magnitude of a load. The jitter control circuit causes a, for example, 8-bit counter that generates a modulation frequency to operate with, for example, 8 bits when 40 kHz≦fc and 7 bits when fc<40 kHz. In this way, even when the range of the EMI noise measurement frequency is extended to the lower frequency side, for example, to 25 kHz, the maximum reduction effect is maintained in the entire frequency range. Thus, the maximum EMI noise reduction effect is obtained. |
| US09673725B2 |
Converter circuit with adjustable DC bus voltage
A method for controlling voltage of a DC bus in a converter circuit is provided. The method includes monitoring a duty cycle of a switch that connects a resistive circuit across the DC bus, the switch being closed when the DC bus voltage reaches an upper voltage value and opened when the DC bus voltage reaches a lower voltage value and altering the lower voltage value based upon the duty cycle of the switch. |
| US09673724B2 |
Matrix converter and method for generating an AC voltage in a second AC voltage grid from an AC voltage in a first AC voltage grid by means of a matrix converter
A matrix inverter is connected to a first and a second multi-phase A.C. voltage network. First inductive elements are connected to the first A.C. voltage network and second inductive elements are connected to the second A.C. voltage network. A switch matrix connects the ends of the first inductive elements, to the ends of the second inductive elements. The switch matrix has inverter units. A regulation arrangement is connected to control inputs of the inverter units. The matrix inverter has a first inverter unit, which is arranged between the ends of the first inductive circuit elements and earth potential. The matrix inverter has a second inverter unit, connected between the ends of the first inductive circuit elements and the ends of the second inductive circuit elements. The regulation arrangement insures that the electrical power flowing to the matrix inverter is equal to the electrical power flowing out of the matrix inverter. |
| US09673721B2 |
Switching synchronization for isolated electronics topologies
One or more first switches coupled to one of a primary transformer winding and a secondary transformer winding are controlled based on a first switch control reference clock signal. A reflected voltage across the other of the primary and secondary windings is sensed, and a second switch control reference clock signal is synchronized to the first switch control reference clock signal based on the reflected voltage. One or more second switches coupled to the other of the primary and secondary windings are controlled based on the second switch control reference clock signal. A digital isolator could instead be used to transfer a switch control reference signal across an isolation boundary. Switch control signals for controlling a set of switches on one side of the isolation boundary may be derived from a switch control reference signal that is synchronized with the transferred switch control reference clock signal. |
| US09673719B2 |
Dual Active Bridge with flyback mode
A dual active bridge (DAB) converter operates in a power conversion operation by controlling multiple bridge configured switches to charge a magnetization inductance from an input supply during a charge phase of a power cycle and to discharge the magnetization inductance into an output of the DAB during a discharge phase of the power cycle. The DAB converter includes an input converter connected to the input supply, an inductance connected to the input converter, a transformer comprising a primary and a secondary winding, and an output converter connected to the transformer. The input and output converters each include a first pair of switches forming a first circuit path, and a second pair of switches forming a second circuit path parallel to the first circuit path. The first and second circuit paths are both completed by a third circuit path including the inductance and the primary winding of the transformer. |
| US09673717B2 |
Electrical circuit for delivering power to consumer electronic devices
An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes an input terminal configured to receive an input power signal, an output terminal configured to provide an output power signal, and a plurality of voltage reduction circuit cells coupled between the input terminal and the output terminal. Each of the voltage reduction circuit cells includes a pair of flyback capacitors, a switching circuit, and a hold capacitor. The switching device is configured to operate the corresponding voltage reduction circuit cell at a charging phase and at a discharging phase. The plurality of voltage reduction circuit cells are configured to deliver the output power signal having a voltage level that is less than the voltage level of the input power signal. |
| US09673714B2 |
Power supply apparatus for an electrical appliance
A power supply apparatus includes a power supply circuit and a power-on circuit. The power-on circuit detects a remotely transmitted control signal and causes a transition of the power supply circuit to a turned on state. The power-on circuit includes a transducer configured to provide a power-on signal in response to the remote control signal. The transducer triggers transition to the turned on state through a switch driven by the power-on signal output from the transducer and arranged to supply a power supply circuit enable signal. A DC blocking capacitor is connected between an output of the transducer and a control terminal of the switch. |
| US09673707B2 |
Apparatus and methods for bypassing an inductor of a voltage converter
Apparatus and methods for bypassing an inductor of a voltage converter are provided. In one embodiment, a voltage converter includes an inductor and a bypass circuit that selectively bypasses the inductor based on a state of a bypass control signal. The inductor includes including a first end electrically connected to a first node and a second end electrically connected to a second node. The bypass circuit includes a first p-type field effect transistor and a second p-type field effect transistor electrically connected in series between the first node and the second node. The first p-type field effect transistor includes a body electrically connected to a first voltage, and the second p-type field effect transistor includes a body electrically connected to a second voltage greater than the first voltage. |
| US09673703B2 |
Bidirectional temperature communication between controller and converter for multiple phase buck converters
A converter arrangement, in particular a switched DC/DC converter arrangement, comprises a control die and a converter die. The control die comprises a control logic for generating a control signal and a control output for controlling the converter die by means of the control signal. The converter die comprises at least one converter that is designed for converting an input signal into an output signal in dependence on the control signal, wherein the control signal can be received at a control input. A single-line interface connects the control output to the control input. |
| US09673702B2 |
Negative current clocking
A switching mode power supply (SMPS) is capable of clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits. |
| US09673701B2 |
Slew rate enhancement for transient load step response
A power conversion circuit, such as a buck converter/regulator, includes a feedback loop operatively coupling the output voltage to the controller for the switching mechanism. The feedback loop includes an analog error amplifier that sources current to the controller when the output voltage falls below a predetermined reference voltage and sinks current from the controller when the output voltage rises above a predetermined reference voltage. The feedback loop further includes at least one of a sinking boost circuit that sinks additional current from the controller when the output voltage falls below a low voltage threshold or a sourcing boost circuit that sources additional current to the controller when the output voltage rises above a high voltage threshold. The boost circuits can include analog amplifiers, digital comparators, or a combination thereof. |
| US09673696B2 |
Ultra low-voltage circuit and method for nanopower boost regulator
At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry. |
| US09673694B2 |
Electromagnetic induction type power supply device
Disclosed is an electromagnetic induction type power supply device, which generates electric power through an electromagnetic induction method using a transformer from current flowing through a transmission line, can adjust an output thereof by detecting and feeding back the output, enables a transformer and a power converting unit to be added or removed as necessary. The electromagnetic induction type power supply device includes a transformer module including a plurality of transformers for outputting electric power by inducing, in an electromagnetic induction method, secondary current from primary current flowing through a transmission line; a power source module including a plurality of power converting units for converting the electric power output from the plurality of transformers to direct current power and outputting the converted power; and a power summing unit for summing the direct current power output from the plurality of transformers and providing the summed power to a load. |
| US09673690B2 |
Electromagnetic retarder rotor for a vehicle, retarder comprising such a rotor, and vehicle provided with such a retarder
An electromagnetic retarder rotor (1) for a vehicle, includes: an armature (2) having an inner surface (4); an end (5) having an inner surface that faces the inner surface (4) of the armature (2) and is at a distance therefrom, the end (5) being secured to the armature (2); a ring (13) for coaxial attachment to the armature (2); and an arm (15) defined between an upper edge and a lower edge and having a first end portion secured to the inner surface (7) of the end (5), on the lower edge, and a second end portion secured to the attachment ring (13), the upper edge of the arm (15) being at a distance from the inner surface of the armature (2) over the entire radial dimension of the arm (15). |
| US09673689B2 |
Rotating electric machine and power transmission device including rotors and electric power unit
Provided is a compound motor (14) comprising a magnet rotor (19) supported by bearings (B3, B4) in a rotatable manner, a winding rotor (20) supported by bearings (B5, B6) in a rotatable manner relative to the magnet rotor (19) at the inner side of the magnet rotor (19) and having rotor winding units (20b), and slip ring mechanisms (25). A space is formed in the inner circumference of the winding rotor (20). At least a part of the slip ring mechanisms (25) is arranged in the space of the inner circumference of the winding rotor (20). The bearings (B3 to B6) include bearings (B3, B6), the internal diameter of each is larger than the size of slip ring mechanisms (25) with respect to the radial direction. The bearings (B3, B6) are arranged outside the slip ring mechanisms (25) with respect to the radial direction. |
| US09673680B2 |
Electromechanical flywheels
An electromechanical flywheel machine includes a flywheel mass and a motor-generator having a rotor rotatable about a stationery inner stator having stator windings. |
| US09673679B2 |
Driving device
A driving device is provided with a gear unit and a plurality of motors. The gear unit includes a plurality of input shafts supported by a supporting member, and a driven member to which the plurality of input shafts is engaged. Each motor rotor is respectively attached to a corresponding one of the input shafts. Each motor stator is attached to a housing that is detachably attached to the supporting member. When the housing is attached to the supporting member, phase angles of the rotors of all of the motors are equal. |
| US09673675B2 |
Stator of an axial flow electric machine and the process for making it
Described is a stator for an axial flow electric machine comprising a toroidal core (2) made from ferromagnetic material and a plurality of windings (3) and teeth (4) angularly distributed on the core (2) in an alternating configuration. The teeth have, on at least one relative lateral surface, a shaped profile defining at least one gripping surface (12) such as to act in conjunction with a matrix of resin designed to stably press the teeth (4) on the core (2). |
| US09673673B2 |
Motor air flow cooling
In one possible embodiment, an aircraft electric motor cooling system is provided having an airflow path through a spinner which includes a first airflow path between an inner rotor and a stator, a second airflow path between an outer rotor the stator and a third airflow path along an outer surface of the outer rotor. |
| US09673672B2 |
Individual-segment rotor having retaining rings
The aim is to propose an individual-segment rotor that is simple to construct and suitable for series production. Therefore, an individual-segment rotor having a plurality of laminated core segments (2) arranged in a star shape and a permanent magnet (1) between each pair of adjacent laminated core segments (2) is provided, whereby the laminated core segments and the permanent magnets are arranged in a hollow cylindrical assembly. The laminated core segments each have a plurality of individual sheets, which are rigidly connected to one another. The hollow cylindrical assembly has a groove on each of two outer edges, into which groove a ring (11) is inserted in order to fasten the assembly. |
| US09673668B2 |
Compression band shim pack for stator core, related stator and generator
A shim pack to reduce vibration of a stator core is disclosed. The stator core may include a plurality of laminates coupled to a dovetail of a keybar and separated by a space block. The shim pack may include an elongated body extending from a first end including a dovetail slot configured to couple to the dovetail of the keybar to a second end extending radially at least substantially an entire length of an adjacent space block. A stator and related generator including the shim pack may also be provided. |
| US09673662B2 |
Battery disconnect safeguard
In embodiments, a mobile device includes a primary battery as a power source to power components of the mobile device, and includes a secondary battery as an additional power source to power the components of the mobile device. A sensor is implemented to detect an acceleration of the device that indicates an impending secondary battery disconnect event due to the mobile device falling. A battery controller is implemented to receive a sensor input of the detected acceleration from the sensor. The battery controller can then switch from the secondary battery to the primary battery as the power source based on the detected acceleration of the mobile device. The battery controller can switch back from the primary battery to the secondary battery as the power source based on the acceleration of the mobile device no longer being detected. |
| US09673655B2 |
Apparatus and methods of charging to safe cell voltage
This document discusses, among other things, a charge regulator configured to optimize charging of an energy storage device by measuring an internal voltage drop of the energy storage device using an open circuit voltage (OCV) across the terminals of the energy storage device during charging and a voltage across the terminals of the energy storage device during charging (CCV). |
| US09673652B2 |
Fast charging high energy storage capacitor system jump starter
A fast charging high energy storage capacitor system jump starter is described. The jump starter apparatus incorporates a method of using reserve energy from a depleted electrical system such as an automobile battery, combined with a fast charging high energy capacitor bank to enable the rapid and effective way to jump start a vehicle. |
| US09673648B2 |
Lithium-based battery pack for a hand held power tool
A method for conducting an operation including a power tool battery pack. The battery pack can include a housing, a first cell supported by the housing and having a voltage, and a second cell supported by the housing and having a voltage. The battery pack also can be connectable to a power tool and be operable to supply power to operate the power tool. The method can include discharging one of the first cell and the second cell until the voltage of the one of the first cell and the second cell is substantially equal to the voltage of the other of the first cell and the second cell. |
| US09673647B2 |
Charging apparatus for mobile device
A charging apparatus for a mobile device is provided. The apparatus includes a terminal casing and a charging mount. A pattern electrode part has concentric electrode patterns. A first magnet is provided underneath the pattern electrode part, and a second magnet having multiple magnet elements is disposed around the pattern electrode part. The charging mount has a pin terminal part which comes into contact with the pattern electrode part. A third magnet being magnetically coupled with the first magnet is provided underneath the pin terminal part. A fourth magnet being magnetically coupled with the second magnet is provided around the pin terminal part. |
| US09673644B2 |
Battery module having overcharge preventing device, and overcharge preventing device for battery module
The present invention relates to a battery module mounted with an overcharge preventing device, and an overcharge preventing device for a battery module. The battery module mounted with an overcharge preventing device of the present invention includes: a battery cell including a first battery cell and a second battery cell, which are spaced apart from each other; and an overcharge preventing device inserted and disposed between the first battery cell and the second battery cell, and configured to block power supplied to the battery cell when the battery cell is expanded according to overcharge, in which the overcharge preventing device is configured as one module separately from the battery cell, and is replaceably disposed between the first battery cell and the second battery cell, which are spaced apart from each other. |
| US09673637B2 |
Ultra-capacitor based energy storage in a battery form factor
An ultra-capacitor based energy source may replace rechargeable and conventional batteries. It may have the form factor of a conventional battery and may emulate the discharge characteristics of the replaced battery. |
| US09673636B2 |
Power reception control device and power reception control method for non-contact power transmission
A power reception control device provided in a power reception device of a non-contact power transmission system includes a power-reception-side control circuit that controls an operation of the power reception device, and a power supply control signal output terminal that supplies a power supply control signal to a charge control device, the power supply control signal controlling power supply to a battery. The power-reception-side control circuit controls a timing at which the power supply control signal (ICUTX) is output from the power supply control signal output terminal. The operation of the charge control device is compulsorily controlled using the power supply control signal (ICUTX). |
| US09673635B2 |
Self sustaining energy harvesting system
Systems (100) and methods (400) for powering an electrical load (322) in an environment. The methods involve using a battery (310) to simultaneously supply electrical energy to control electronics (308, 316) and a Super Capacitor (“SC”) storage element (314) immediately after a system has been disposed in the environment and turned on. In effect, the control electronics are caused to perform intended functions thereof nearly instantaneously after turning on the system. The SC storage element is charged from a first charge state in which approximately zero volts exist across terminals thereof to a second charge state in which greater than zero volts exists across the terminals. The SC storage element is then used to supply electrical energy to the electrical load of the system so as to cause the electrical load to perform intended functions thereof. |
| US09673624B2 |
Power supply device and power supply switching method
A power supply device (10) includes a plurality of constant current output circuits (14) that can supply power to a load (12). The constant current output circuit (14) includes a pulse generation unit (20) that generates a pulse voltage, and a communication unit (34) that transmits and receives drive information, between the constant current output circuit (14) and the other constant current output circuit (14). When an abnormality occurs in the constant current output circuit (14) supplying power to the load (12) and the constant current output circuit (14) supplying power to the load (12) is switched to the other constant current output circuit (14), the other constant current output circuit (14) drives the pulse generation unit (20) by using the drive information that has been received through the communication unit (34) from the power supply means having supplied power to the load. |
| US09673623B2 |
Sequentially operated modules
Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power. The system may use remote powering wherein few or all of the modules are powered from the same power source connected to the system in a single point. The power may be carried over dedicated wires or concurrently with the conductors carrying the activation signal. The payload may be a visual or an audible signaling device, and can be integrated within a module or external to it. The payload may be powered by a module or using a dedicated power source, and can involve randomness associated with its activation such as the delay, payload control or payload activation. |
| US09673619B2 |
Excess voltage protection apparatus and diagnostic method for multi-stage excess voltage protection apparatuses
The invention relates to a diagnostic method for multiple-stage excess voltage protection apparatuses that include at least one gas discharge distance between an input and a reference potential as a first stage, at least one diode path between an output and the reference potential as a second stage, and at least one decoupling inductance interposed between the input and the output. The diagnostic method is characterized in that a secondary voltage applied to a secondary inductance, which is actively connected, inductively, to the decoupling inductance, is measured and evaluated with a view to excess voltage events in the excess voltage protection apparatus. The invention also relates to a two-stage excess voltage protection apparatus. |
| US09673617B2 |
Pre-charge circuit for an electromechanical relay
A pre-charge circuit is provided for an electromechanical relay having a coil and relay contacts. The pre-charge circuit includes a semiconductor switch configured to be electrically connected across the relay contacts of the electromechanical relay. The pre-charge circuit includes a resistor configured to be electrically connected in series with the semiconductor switch between the coil and the relay contacts of the electromechanical relay. The pre-charge circuit includes a driver configured to be electrically connected between the coil of the electromechanical relay and the semiconductor switch such that the driver is configured to power operation of the semiconductor switch. The semiconductor switch is configured to pre-charge a capacitor of a load of the electromechanical relay with electrical current through the resistor for limiting in-rush electrical current supplied to the relay contacts of the electromechanical relay. |
| US09673615B2 |
Isolator circuit
An isolator circuit (25) for a unit of a safety system (10) includes a power control line (14) connectable to a first loop of a safety system and a power connection (16) connectable to a second loop of the safety system. A switch (26) is connected to the power control line (14), and the switch has a closed configuration and an open configuration. A controller (28) controls the configuration of the switch (26). If a voltage across the circuit (10) from the power connection (16) to the power control line (14) falls below a predetermined level, the controller (28) opens the switch (26), thereby causing a disconnection to occur in the first loop. |
| US09673613B2 |
Surge protection device
A surge protection device detects whether a surge voltage occurs at a power input port by using a first Zener diode and a second Zener diode. When the power input port receives a normal voltage, the surge protection device turns on a first transistor to transmit the normal voltage to a load. Otherwise, when the power input port receives the surge voltage, the surge protection device prohibits the first transistor from conducting so as to protect the load from being damaged by the surge voltage. The surge protection device protects the load by controlling conducting or not of the first transistor and is manufactured without a surge protection unit. Therefore, manufacturing cost of the surge protection can be decreased. |
| US09673608B2 |
Disconnection indicator of an active component of a device for protecting an electrical installation
A device for protecting an electrical installation including an insulating body electrically defining an internal housing, the protective device including, within the internal housing: an active component of a device for protecting an electrical installation; a disconnection system for disconnecting the active component moveable between a contact position corresponding to a connected state of the active component and an open position corresponding to a disconnected state of the active component; a disconnection indicator, where the disconnection indicator is secured in movement to the disconnection system and the disconnection indicator and the insulating body are arranged to have a first configuration, which corresponds to the contact position, and a second configuration, which corresponds to the open position, the relative positioning of the disconnection indicator with respect to the insulating body in the first configuration being visually distinct from the outside of the insulating body from the relative positioning of the disconnection indicator with respect to the insulating body in the second configuration. |
| US09673606B2 |
Pressurized electromechanical cable
An inventive pressurized cable is provided that simultaneously provides electrical connections and a supply of air, gas, or vacuum to an electromechanical device utilizing an existing connection on the device. The use of an existing cable connection for the supply of air or gas to provide positive pressure or a vacuum condition to an electromechanical enclosure allows for the use of standard electromechanical components without alteration and potential voiding of existing warranties. The present invention finds particular utility in the field of industrial automation where motors are subjected to coolant liquids and other types of contaminants that tend to infiltrate the motor seals, especially when the motor is shut down which causes a negative pressure inside the motor case that draws moisture in. Reactive gasses may be introduced with the inventive positive pressure cable that act to neutralize or condition harmful pollutants generated by the motor such as ozone. |
| US09673605B2 |
Boot seal
The boot seal may include an elastomeric body constrictively stretched over an end of a cable and a retainer to grip the cable. The retainer may be a body having a central opening to receive the cable and have a plurality of inclined tines extending radially inwardly from the body with the inclined tines having distal ends forming the central opening. The elastomeric body may have a first sleeve on an end of the boot seal for receiving the end of the cable. |
| US09673603B2 |
Divided conduit
A divided conduit containing a thermoplastic conduit and at least one strip-shaped film having a first longitudinal edge and a second longitudinal edge which are embedded into the inner surface of the conduit forming at least two flexible, longitudinal channels for enveloping cables or other elongated structures. |
| US09673600B2 |
Grommet
A grommet (10) is mounted on a burred part (54) formed on an inner periphery of a through hole (52) formed on a panel (50). The grommet (10) includes a small-diameter tubular portion (12), a large-diameter tubular portion (20) and a coupling (16) connecting the small-diameter tubular portion (12) and the large-diameter tubular portion (20). The small-diameter tubular portion (12) is held in close contact with an outer peripheral surface of the wire (60), and the a large-diameter tubular portion (20) is fit on an outer peripheral side of the burred part (54) of the panel (50). A rib (40) projects from an inner peripheral surface of the coupling (16) and covers at least a part of an inner peripheral surface side of the burred part (54) of the panel (50). |
| US09673597B2 |
Wall clamping junction box
An enclosure such as an electrical junction box has fixed clamping flanges exterior to the enclosure, screws rotatable relative to the enclosure and operative for drawing clamping brackets from an initial elevated position towards the clamping flanges for clamping the edges of an opening cut in drywall or the like, thereby to fasten the enclosure inside a wall or ceiling. The clamping brackets are initially retracted in the enclosure and rotation of the screws releases the brackets to an extended clamping position relative to the clamping flanges. |
| US09673596B2 |
Back box with mounting posts projecting from recessed portions in sidewalls
A weatherproof back box for receiving a fire alarm notification or other fire alarm device includes a back wall and sidewalls that project from the back wall and define a mouth. The sidewalls further include recessed portions that extend from the back wall toward the mouth, and end prior to the mouth. The back box further includes mounting posts, which are preferably less than 50% of the depth of the back box, that project from the recessed portions into the mouth. Additionally, these mounting posts receive fasteners for securing the fire alarm notification device in the mouth of the back box. |
| US09673593B2 |
Spark plug having firing pad
A spark plug has a firing pad attached to a center electrode or to a ground electrode. The firing pad is attached via laser welding and has a sparking surface with an overall fused area and an unfused area. In one or more embodiments, the overall fused area is located in part or more inboard of a peripheral edge of the firing pad. |
| US09673592B2 |
X-ray tube
An x-ray tube includes a vacuum housing. A cathode and an anode are disposed in the vacuum housing and insulated by at least one insulation element. Upon application of a high voltage, the cathode emits electrons that strike the anode as an electron beam. A voltage arrester device with an insulation path has a field strength that is higher than a field strength at the insulation element. If a voltage flashover occurs, the voltage is discharged via the voltage arrester device. |
| US09673590B2 |
Semiconductor stripe laser
A semiconductor stripe laser has a first semiconductor region having a first conductivity type and a second semiconductor region having a different, second conductivity type. An active zone for generating laser radiation is located between the semiconductor regions. A stripe waveguide is formed in the second semiconductor region and is arranged to guide waves in a one-dimensional manner and is arranged for a current density of at least 0.5 kA/cm2. A second electrical contact is located on the second semiconductor region and on an electrical contact structure for external electrical contacting. An electrical passivation layer is provided in certain places on the stripe waveguide. A thermal insulation apparatus is located between the second electrical contact and the active zone and/or on the stripe waveguide. |
| US09673586B2 |
Method of waterproofing coated electric wire attached connector terminal
A method of waterproofing a coated electric wire attached connector terminal which is formed of metal material and which includes a barrel part which is crimped to a conductor which is exposed from a sheath, a terminal part, a connecting plate which is formed between the barrel part and the terminal part, and connects the barrel part and the terminal part. The method includes an adhesive material applying step in which adhesive material is applied to the connecting plate, and a molded part molding step in which the coated electric wire attached connector terminal is placed in a metal mold to form an injection space around the connecting plate, the barrel part and the sheath and resin is injected into the injection space to cover the connecting plate, the barrel part and the sheath with a resin molded part. |
| US09673583B2 |
Photovoltaic mounting rail connector with drop-down connection to first photovoltaic module and slide-in connection to second photovoltaic module
A connector for attaching first and second photovoltaic modules to a mounting rail, with a lower body portion that rotates to lock into a mounting rail groove and an upper body portion with a hook that is lowered towards the lower body portion to grasp onto the first photovoltaic module and a key that receives the second photovoltaic module slidably-connected thereon. |
| US09673581B1 |
Electrical connector
An electrical connector comprising an insulating housing, a USB Type-C connector arranged in the insulating housing, a circuit board and a plurality of transferring terminals is disclosed. One side of the circuit board is connected with twenty-four connection terminals of the USB Type-C connector, other side of the circuit board is connected with the plurality of transferring terminals which are corresponding to USB Type-A standard. The circuit board is arranged with a connecting line, which is used to integrate signal transmitted through the twenty-four connection terminals of the USB Type-C connector into USB Type-A standard adopted outputting signal, and outputs the outputting signal through the plurality of transferring terminals. |
| US09673579B2 |
Portable USB charging hand controller with twist-on cover
The present invention discloses a portable remote controller, which comprises a remote controller body and a cover covering the remote controller body; hooks are arranged on the back of the cover, and slots to fit the hooks are arranged at corresponding positions in an upper rim of the remoter body; press buttons are arranged in a front of the cover. The portable remote controller with added USB charging function can not only fulfill the regular remoter control functions for intelligent living, but its USB interface is also able to charge almost all intelligent devices in the market, including almost all intelligent phones and tablets; thus when people are using intelligent devices in daily life, they will no longer worry about low batteries; also the cover is easy to remove and install, convenient to users. |
| US09673577B2 |
Power plug device and the manufacturing method thereof
This invention provides a power plug device and the manufacturing method thereof, the power plug device comprises a power-connected base; a cover is configured to the power-connected base, wherein the cover can cover the internal components of the power-connected base, such as at least one plug and a printed circuit board, a gap between the cover and a lid is filled with an insulating compound for preventing liquid ingress, and then the power plug device is sealed by using an ultrasonic welding. |
| US09673575B1 |
Electrically conductive wall hooks
The invention is an electrically conductive wall hook. The invention is a means to provide power to an object that is being stored in a hanging position. The invention is made up of two parts. The first part is a housing attached to an object to be stored that contains an opening. The second part is a hook attached to a wall. Both the housing and the hook contain electrical conductors. When the hook is fitted securely inside the opening of the housing, the object is suspended from the hook, and the electrical conductors within the housing and the hook mate with each other. The electrical conductor inside the hook is attached to electrical power so that electrical power is provided to the object that is suspended from the hook. |
| US09673574B2 |
Connector terminal, electric connector, and method of fabricating the connector terminal
A connector terminal includes a press-fit terminal and a shaft portion, the connector terminal being fabricated of a single metal sheet, the shaft portion having a lateral cross section having a size entirely covering therewith a lateral cross section of the press-fit terminal when viewed in an axial direction of the connector terminal, the shaft portion having surfaces extending in the axial direction at an entire circumference thereof, the lateral cross section of the shaft portion being identical in shape with a lateral cross section of a terminal space of a die used for fabricating a housing for the press-fit terminal, the press-fit terminal being fit into the terminal space when the housing is molded with resin. |
| US09673571B2 |
Shield unit
A shield unit includes: a braid having a contact portion arranged in contact with a cylinder of a shield shell; a holder inserted in the cylinder and attached to the cylinder in contact with the contact portion, the holder attached to the cylinder electrically connecting the shield shell to the braid; and a rotation unit provided between the cylinder and the holder, the rotation unit being configured to make the holder rotate in a circumferential direction of the cylinder and make the cylinder and the contact portion slide relatively to each other until completion of attaching the holder to the cylinder. |
| US09673568B2 |
Plug connector
A plug connector including a connecting member, a cable, and a shield case. The cable includes a signal transmission part connected to the connecting member. The shield case includes first and second shells and a first retainer. The first and second shells are combined together in a first direction so as to form a tube at least partially covering the connecting member and the signal transmission part. The first shell has an end face on one side of a second direction. The second direction is orthogonal to the first direction. The first retainer is a tube or half tube for retaining the cable. The first retainer is provided on the second shell so as to be located on the one side of the second direction relative to the end face of the first shell and in contact with at least a part of the end face of the first shell. |
| US09673567B1 |
Apparatus, system, and method for preventing electric shock during maintenance of telecommunication systems
The disclosed apparatus may include a lock that has a locking mechanism that secures an electronic module to a telecommunication system. The lock may also have an ejection handle coupled to the locking mechanism such that application of physical force to the ejection handle ejects the electronic module from the telecommunication system by undoing the locking mechanism. The disclosed apparatus may also include a cross-bar coupled to the lock and movable in conjunction with the ejection handle. The cross-bar may facilitate access to a row of power connectors arranged along a surface of the electronic module when the ejection handle is positioned in a first position. Additionally or alternatively, the cross-bar may block access to the row of power connectors arranged along the surface of the electronic module when the ejection handle is positioned in a second position. Various other apparatuses, systems, and methods are also disclosed. |
| US09673566B2 |
Electronic device
An electronic device including a first body, a first connecting assembly, a second body, and a second connecting assembly is provided. The first body has a recess, and the first connecting assembly is disposed at the first body and hidden in the recess. The second connecting assembly is disposed on the second body in protruding manner. The second connecting assembly is fit to be assembled in the recess and electrically connected to the first connecting assembly, such that the first and the second bodies are detachably assembled to each other. |
| US09673563B2 |
Connector
A connector (10A) is provided with a housing (20) including a tube (22) and a seal (80) to be fit in the tube (22) in a liquid-tight manner. A holder (60) has a peripheral wall (62) fit externally on the tube (22) and a rear wall (61) configured to prevent the seal (80) from coming out backward. A wire cover (50) is mounted on the housing (20) by being fit externally on the peripheral wall (62) when the wire cover (50) is arranged to cover wires (100) pulled out from the holder (60) and the peripheral wall (62) is disposed in a proper posture on the tube (22). However, the wire cover (50) interferes with the holder (60) and cannot be mounted on the housing (20) when the peripheral wall (62) is in an improper posture inclined with respect to the tube (22). |
| US09673558B2 |
Systems and methods for maintaining pressure on an elastomeric seal
Systems and methods for maintaining a desired compressive force on seals in an electrical junction such as a pothead connector for an ESP motor. In one embodiment, insulated conductors of a power cable extend into a housing of a connector. The insulated conductors pass through an upper insulator, a set of elastomeric boot seals, and a lower insulator. O-rings are positioned between the upper insulator and the housing of the pothead connector. The lower insulator is secured to the upper insulator by a set of bolts and springs that urge the lower insulator toward the upper insulator, compressing the boot seals. The bolts are threaded into the upper insulator and are tightened to compress the springs against the lower insulator. The compression of the boot seals between the insulators maintains a desired range of contact pressure against the seals despite changes in the seal dimensions. |
| US09673556B2 |
Perpendicular plug connector
A perpendicular plug connector has an insulative housing, multiple first conductive terminals, multiple second conductive terminals, a base, a reinforcing fastening element and a shell. The first conductive terminals and the base are mounted on the insulative housing. The reinforcing fastening element is mounted on and tightly abutting the base. The shell accommodates the insulative housing and the first conductive terminals. The reinforcing fastening element allows fasteners such as bolts and rivets to extend through and fasten the perpendicular plug connector securely on a circuit board and enhances structural strength of the base. |
| US09673553B1 |
Terminal position assurance locking mechanism and method for operating thereof
A locking mechanism for a terminal position assurance (TPA) device is placed in-line with the TPA itself. The locking mechanism includes a pre-locking head and a final locking head. The final locking head is shorter than and face in an opposite direction from the pre-locking head. The orientation and geometry of the locking mechanism ensures a secure engagement of the TPA with the electrical connector assembly. Further, according to at least one embodiment, at least two pre-lock mechanisms and only a single final-lock mechanism may be provided for the locking mechanism to ensure a secure engagement of the TPA with the connector assembly without a false-positive engagement. |
| US09673552B2 |
Electrical receptacle connector
An electrical receptacle connector includes a metallic shell, an insulated housing, a plurality of first receptacle terminals, and a plurality of second receptacle terminals. The insulated housing is received in the receiving cavity. The insulated housing includes a tongue portion and a plurality of first through holes formed on the tongue portion. The first receptacle terminals are held in the tongue portion. The second receptacle terminals are held in the tongue portion. The second receptacle terminals include a plurality of cut portions corresponding to the first through holes. |
| US09673550B2 |
Electrical connecting module
The invention relates to an electrical connecting module comprising: a module housing (101), which comprises a module receptacle (103, 119, 1209) with a first electrical connection terminal (105, 107); a module element (109, 1205) with a second electrical connection terminal (111, 113) and with a third electrical connection terminal (115, 117), wherein the module element (109, 1205) for electrically connecting the first connection terminal (105, 107) to the second connection terminal (111, 113) can be inserted (into the module receptacle (103, 119, 1209) and can be held in the module receptacle (103, 119, 1209) by means of a detachable latching connection; and a release device (125) for releasing the latching connection. |
| US09673547B2 |
Plated terminal for connector and terminal pair
The present invention aims to provide a plated terminal for connector which requires a smaller insertion force by reducing a friction coefficient and a terminal pair formed using such a plated terminal for connector. An alloy containing layer (1) made of tin and palladium and containing a tin-palladium alloy is formed on a surface of a terminal base material (2) made of copper or copper alloy. Here, the alloy containing layer (1) is preferably such that domain structures of a first metal phase (11) made of an alloy of tin and palladium are formed in a second metal phase (12) made of pure tin or an alloy having a higher ratio of tin to palladium than in the first metal phase (11). |
| US09673544B1 |
Short type metal female terminal and an LED light using the same
A short type metal female terminal includes a base on which weld legs are disposed to provide an electrical connection with a light board. The base has an entrance through which a male terminal can pass. Two main elastic plates are respectively disposed at a left side and a right side of the base. The main elastic plates bend downwards and inwards, then extend oppositely to a place below the entrance, and then bend upwards to pass through the entrance. Thus, contact points of the main elastic plates opposite to each other are formed and located above the entrance. The male terminal passes between said contact points to carry out the electrical connection. The above structure is simple, and the electrical connection is more reliable. |
| US09673543B2 |
Distribution block and din rail release mechanism
An electrical distribution block transfer electrical power from a primary conductor to one or more tap conductors. The distribution block includes a base, a conductor block, first and second sidewalls, and a lid. The conductor block and the first and second sidewalls are connected to the base and the lid is connected to the first and second sidewalls. The conductor block includes one or more apertures for receiving more primary conductors and one or more apertures for receiving tap conductors. |
| US09673542B1 |
Poke-in electrical connector having a contact with a base extending through an opening in a bottom of a housing
A poke-in electrical connector includes a housing having a cavity and a poke-in wire channel open to the cavity. The wire channel receives an electrical wire during a poke-in termination. The housing has a bottom with an opening. A poke-in electrical contact is received in the cavity and held by the housing. The poke-in electrical contact includes a base and an arm extending from the base. The base extends through the opening at the bottom for surface mounting to a circuit board. The base has a generally planar solder pad exposed at the bottom for soldering to the circuit board. The arm has a poke-in beam engaging the electrical wire when poked-in to the corresponding wire channel. The arm is movable to a clearance position to release the poke-in beam from the electrical wire to allow the electrical wire to be removed from the wire channel. |
| US09673539B2 |
Spring biased contact pin assembly
A spring biased contact pin assembly includes a barrel member having a barrel wall defining an elongate internal cavity with a lower end and an upper end. The assembly also includes a lower plunger member reciprocally mounted in the internal cavity proximate the lower end of the internal cavity. A spring member is positioned in the internal cavity between the lower plunger member and the upper end of the internal cavity. A high electrical resistance spacer member is positioned in the internal cavity in contact with the lower plunger member and the spring member. Spring force exerted through the spacer member urges the lower plunger member into electrical contact with the barrel wall. A method of transmitting electricity through an electrical contact assembly includes urging a plunger member against the wall of a barrel member in which it is reciprocally mounted with a high electrical resistance member. |
| US09673531B2 |
Antenna
An antenna is disclosed. The antenna includes a coupling portion, a ground connection portion corresponding to the coupling portion, and a radiation body. The a radiation body further includes a first antenna portion extending from a first end of the coupling portion in a direction, a second antenna portion extending from the first end in a direction opposite to that of the first antenna portion, and a third antenna portion extending from an end of the ground connection portion in a direction surrounding the first antenna portion, wherein two gaps are provided for separating the third antenna portion from the first antenna portion and the second antenna portion respectively. |
| US09673527B2 |
Folded patch antenna platform
Various systems and methods are provided for folded patch antennas. In one embodiment, among others, a folded patch antenna includes a patch disposed on an outer side of a flexible substrate and a ground plane disposed on an inner side of the flexible substrate opposite the patch. The flexible substrate is folded to form an enclosed cavity defined by the inner side of the flexible substrate. The ground plane may provide electromagnetic interference (EMI) shielding of the cavity. In another embodiment, among others, a folded patch antenna platform includes a flexible substrate, a folded patch antenna, and a transceiver mounted on the flexible substrate. The folded patch antenna includes a patch communicatively coupled to the transceiver and a ground plane, which are disposed on opposite sides of the flexible substrate. |
| US09673526B1 |
Dual-frequency stacked patch antenna
The invention is directed to a dual-frequency stacked patch antenna. In one embodiment, the antenna comprises a pair of electrically conductive, nested, tub-like structures and a feed surface. The edges of the tub-like structures and the feed surface define a surface that is adapted to be conformal to an application surface that defines a cavity in which the antenna is positioned. The edges of the tub-like structures and the edge of the feed surface define a pair of slots for receiving and/or transmitting two signals with different center frequencies. Located and extending throughout each of the slots is a slot modification structure comprised of inter-digitated fingers that provide capacitive loading and enhance the low observability of the antenna. |
| US09673519B2 |
Ground planes for reducing multipath reception by antennas
An antenna system for a global navigation satellite system reference base station is disclosed. The antenna system includes an antenna positioned above a high capacitive impedance surface (HCIS) ground plane. Over a specific range of the lateral dimension of the HCIS ground plane and the height of the antenna above the HCIS ground plane, a high level of multipath suppression and high sensitivity for low-elevated satellites can be simultaneously maintained. The HCIS ground plane can be fabricated as a flat conducting plate with an array of conducting elements such as pins, pins with expanded tips, or mushroom structures. Alternatively, the HCIS can be fabricated as a flat conducting plate with a concentric series of choke rings. The antenna system can provide a positioning accuracy of +/−1 mm, an order of magnitude improvement over previous designs. |
| US09673514B2 |
Dimensionally tolerant multiband conformal antenna arrays
Some embodiments relate to a multiband antenna array formed on a flexible substrate. Low frequency antenna elements may be formed using nanoink. High frequency elements may be provided on a prefabricated antenna chip. The antenna array may be heated in a low temperature oven to sinter the nanoink into a solid antenna element. In some embodiments, an adhesive insulation layer may be provided which allows the antenna array to be attached to any surface. In other embodiments, the antenna array may be embedded in a composite material. |
| US09673513B2 |
Radiator frame having antenna pattern embedded therein and electronic device including the same
A radiator frame includes: a main radiator including an antenna pattern part configured to transmit or receive a signal, an internal terminal part provided on one end of the antenna pattern part and configured to electrically connect the antenna pattern part and a circuit substrate, and an external terminal part provided on another end of the antenna pattern part and configured to be connected to an auxiliary radiator to improve radiation performance of the antenna pattern part; and a molded frame molded around the radiator, the molded frame allowing the internal terminal part to be exposed at a first surface of the molded frame, and allowing the external terminal part to be exposed at a second surface of the molded frame. |
| US09673508B2 |
Antenna device and electronic device having the same
An electronic device is provided. The electronic device includes a first antenna radiator operating in at least one frequency band, and at least one second antenna radiator disposed proximate to the first antenna radiator coupled to at least one radiation pattern of the first antenna radiator, and to operate as a parasitic resonator. |
| US09673506B2 |
Antenna device and manufacturing method thereof
Disclosed herein is an antenna device that includes an antenna coil having a planar coil pattern, a magnetic sheet that covers one main surface of the antenna coil, and a resin layer provided on the other main surface of the antenna coil and along the coil pattern. The resin layer is substantially the same planar shape as the planar coil pattern. |
| US09673503B1 |
Systems and methods for combining or dividing microwave power
A power combiner/divider includes a main conductor defining an axis; an input connector having a center conductor, adapted to be coupled to a signal source, electrically coupled to the main conductor and having an axis aligned with the main conductor axis, and having a second conductor electrically coupled to a ground conductor; a plurality of satellite conductors radially exterior of and spaced apart from the main conductor, the satellite conductors defining the general shape of a slotted hollow cylinder having a cylinder axis aligned with the main conductor axis; a plurality of output connectors having respective axes that are perpendicular to the main conductor axis, the output connectors being radially spaced apart relative to the main conductor, the output connectors having center conductors electrically coupled to respective satellite conductors and having respective second conductors electrically coupled to a second ground conductor; and a multiconductor transmission line, including the satellite conductors, defined between the input connector and the output connectors. Methods of manufacturing are also disclosed. |
| US09673502B2 |
High-frequency signal transmission line and electronic device
A dielectric element assembly includes a plurality of dielectric layers stacked on each other in a direction of lamination and extends in an x-axis direction. A signal line is provided in the dielectric element assembly and extends in the x-axis direction. A reference ground conductor is provided on a positive side in a z-axis direction relative to the signal line. An auxiliary ground conductor is provided on a negative side in the z-axis direction relative to the signal line. Via-hole conductors connect the reference ground conductor and the auxiliary ground conductor and are provided in the dielectric element assembly on the negative side relative to the center in a y-axis direction. A portion of the signal line in a section which includes the via-hole conductors is positioned on the positive side in the y-axis direction relative to another portion of the signal line in a section which does not include the via-hole conductors. |
| US09673497B2 |
High frequency filter having frequency stabilization
A temperature-compensated high frequency filter of coaxial construction comprises at least one resonator having an inner conductor and an outer conductor housing. A compensation device made of a second material has a second coefficient of thermal expansion. The compensation device comprises a wall section, which extends in an axial direction and is variable in length in this direction in the event of a temperature change. The wall section is part of the housing wall configured in the manner of an intermediate layer or an upper-most layer located adjacent to the housing cover. The wall section may extend in an axial direction or in a direction transversely thereto and be variable in length in this direction in the event of a temperature change. The wall section is an integral part of the housing cover or is connected to the housing cover, or forms the housing cover having convex outwardly directed curvature. |
| US09673494B2 |
Portable electronic device thermal management system
An electronic device having a heat source disposed in direct alignment with a battery for the device and a thermal management system in thermal contact with the heat source. The thermal management system may extend from at least a first surface of the battery to a second surface of the battery. The second surface of the battery may be adjacent a heat dissipation element. The thermal management system may further be in thermal contact with the heat dissipation element. Further a portion of the thermal management system extends along the first and second surfaces of the battery and has a sufficiently high anisotropic ratio to avoid the transfer of heat to the battery to the extent to inhibit the functioning of the battery. |
| US09673493B2 |
Battery temperature regulating device
A battery temperature regulating device a battery module, a temperature detection device, a battery temperature regulating device, and a battery pack case. The battery temperature regulating device includes a cooling heat exchanger configured to cool air that passes therethrough, a condensed water reservoir configured to store condensed water generated in the cooling heat exchanger, and an air blowing device configured to blow the air in the vicinity of the cooling heat exchanger and the condensed water reservoir and circulate the air within the battery pack case. The battery temperature regulating device is configured to cool the air that passes through the cooling heat exchanger, drive the air blowing device to execute the cooling of the battery module when the temperature of the battery module is higher than a predetermined temperature, and drive only the air blowing device regardless of the temperature of the battery module. |
| US09673491B2 |
Vehicle battery system
A vehicle battery system has a vehicle battery, a cooling device to cool the vehicle battery and which includes a heat sink in thermal contact with the battery cells to transfer heat from the battery cells to the heat sink. The heat sink has at least one cooling channel through which a coolant may flow and connection ends formed by delimitations of the at least one cooling channel. A coolant distributor is provided at and connected to at least one end of the heat sink at a receiving region which is adhesive bonded to the heat sink, the receiving region of the coolant distributor surrounding the connection ends of the heat sink, in which the end faces of the delimitations of the cooling channel form stops for the coolant distributor which abut contact surfaces of the coolant distributor. |
| US09673490B2 |
Method and system for cooling secondary battery
Provided are a method and system for rapidly cooling a lithium secondary battery. A conductive connector is connected to at least one of positive and negative electrode terminals of a lithium secondary battery, and the conductive connector is brought into contact with a coolant to cool battery cells. The coolant may be water or air and may flow a coolant tube formed of a synthetic resin. An end of the coolant tube is fixed to at least one of the positive and negative electrode terminals. Therefore, owing to a cooling means disposed at a side of the lithium secondary battery, the temperature of the lithium secondary battery can be prevented from increasing to a preset value due to abnormal heating, and thermal stability of the lithium secondary battery can be improved by rapid cooling. |
| US09673487B2 |
Battery with a monitoring circuit and for use in a motor vehicle
A battery includes at least one battery cell in a battery cell housing and includes a housing cover having a monitoring circuit. An electrode of the at least one battery cell is connected in an electrically conductive manner to the battery cell housing via a switching mechanism in the monitoring circuit. The monitoring circuit is configured to open the switching mechanism when a malfunction signal is detected. The switching mechanism is closed during normal operation. Separate contacts provide contact to the cell housing in a module assembly and the electrode is disconnectable from the battery cell housing. |
| US09673486B2 |
Preparation method of laminated cell
The present disclosure provides a preparation method of a laminated cell comprising: providing a laminated pack: the laminated pack comprises n laminated groups, the each laminated group comprises m electrode plate assemblies, a spacer is provided between the adjacent laminated groups, the electrode plate assemblies of all the laminated groups of the laminated pack and the spacers between the adjacent laminated groups are orderly positioned in a Z-shaped separator in a laminating direction, an upper part and a lower part of the separator adjacent to the each spacer are separated by the each spacer; forming a laminated cell: the separator is broken at an end of the each spacer positioned in the separator to allow the each spacer and the each laminated group to separate from each other, so as to obtain the corresponding laminated cell formed by the electrode plate assembly of the each laminated group and the corresponding separator. |
| US09673485B2 |
Anode of cable-type secondary battery and manufacturing method thereof
Provided is a method for manufacturing an anode of a cable-type secondary battery having a solid electrolyte layer, including preparing an aqueous solution of an anode active material, making an anode by immersing a core as a current collector having a horizontal cross section of a predetermined shape and extending longitudinally in the aqueous solution, then applying an electric current to form a porous shell of the anode active material on the surface of the core, and forming a solid electrolyte layer on the surface of the anode by passing the anode through a solid electrolyte solution. The anode has a high contact area to increase the mobility of lithium ions, thereby improving battery performance. Also, the anode is capable of relieving stress and pressure in the battery, such as volume expansion during charging and discharging, thereby preventing battery deformation and ensuring battery stability. |
| US09673483B2 |
Reactive sintering of ceramic lithium ion electrolyte membranes
Disclosed herein are methods for making a solid lithium ion electrolyte membrane, the methods comprising combining a first reactant chosen from amorphous, glassy, or low melting temperature solid reactants with a second reactant chosen from refractory oxides to form a mixture; heating the mixture to a first temperature to form a homogenized composite, wherein the first temperature is between a glass transition temperature of the first reactant and a crystallization onset temperature of the mixture; milling the homogenized composite to form homogenized particles; casting the homogenized particles to form a green body; and sintering the green body at a second temperature to form a solid membrane. Solid lithium ion electrolyte membranes manufactured according to these methods are also disclosed herein. |
| US09673479B2 |
Energy accumulator module
An energy storage module having a plurality of stacked flat cells. The energy storage module has an interconnection formed in such a way that the energy storage module can be connected mechanically, electrically and/or for exchanging coolant with at least one other energy storage module of the same kind. |
| US09673472B2 |
Redox desalination system for clean water production and energy storage
An energy storage system employing a reversible salination-desalination process includes an electrochemical desalination battery (EDB) unit including an anode and a cathode. The EDB unit runs a salination process while storing energy from a direct current power supply unit, and runs a desalination process while releasing energy to an electrical load. The energy storage system can store power from a variable output electrical power supply unit such as solar cells and wind turbines while running a salination process, and release energy, e.g., during peak energy demand hours while running a desalination process. Combined with a capacitive deionization (CD) unit, the energy storage system can generate fresh water by running desalination processes in the EDB unit and the CD unit while releasing stored energy from the EDB unit. The energy storage unit can function as a dual purpose device for energy storage (load shifting) and fresh water generation. |
| US09673470B2 |
Electrolyte layer having a patchwork-type nanoporous grain boundary and a method of preparation thereof
Gadolinium-doped cerium oxide slurries used to form a patchwork type surface structure with nanoporous grain boundary prepared by mixing gadolinium-doped cerium oxide and a polymer binder to form a first mixture; wet-atomizing the first mixture under a pressure of at least 100 MPa to obtain a second mixture; coating the second mixture to a substrate to form a coated substrate; and sintering the coated substrate. The patchwork type structure is a polygonal or honeycomb structure having a size of from 0.1 μm to 3 μm. |
| US09673469B2 |
High performance multilayer electrodes for use in reducing gases
Electrode materials systems for planar solid oxide fuel cells with high electrochemical performance including anode materials that provide exceptional long-term durability when used in reducing gases and cathode materials that provide exceptional long-term durability when used in oxygen-containing gases. The anode materials may comprise a cermet in which the metal component is a cobalt-nickel alloy. These anode materials provide exceptional long-term durability when used in reducing gases, e.g., in SOFCs with sulfur contaminated fuels. The cermet also may comprise a mixed-conducting ceria-based electrolyte material. The anode may have a bi-layer structure. A cerium oxide-based interfacial layer with mixed electronic and ionic conduction may be provided at the electrolyte/anode interface. |
| US09673468B2 |
Polymer electrolyte material, polymer electrolyte molded product using the polymer electrolyte material and method for manufacturing the polymer electrolyte molded product, membrane electrode composite, and solid polymer fuel cell
It is an object of the present invention to provide a polymer electrolyte material which has excellent proton conductivity even under the conditions of a low humidity or a low temperature and is excellent in mechanical strength and fuel barrier properties, and which moreover can achieve high output, high energy density and long-term durability in forming a polymer electrolyte fuel cell therefrom, and a polymer electrolyte form article using the same and a method for producing the same, a membrane electrode assembly and a polymer electrolyte fuel cell, each using the same.The present invention employs the following means. Namely, the polymer electrolyte material of the present invention is a polymer electrolyte material including a constituent unit (A1) containing an ionic group and a constituent unit (A2) substantially not containing an ionic group, wherein a phase separation structure is observed by a transmission electron microscope and a crystallization heat measured by differential scanning calorimetry is 0.1 J/g or more, or a phase separation structure is observed by a transmission electron microscope and the degree of crystallinity measured by wide angle X-ray diffraction is 0.5% or more. Also, the polymer electrolyte form article, the membrane electrode assembly and the polymer electrolyte fuel cell of the present invention are characterized by being composed of such polymer electrolyte materials. |
| US09673464B2 |
Derivation of control parameters of fuel cell systems for flexible fuel operation
A method of operating a fuel cell system includes characterizing the fuel or fuels being provided into the fuel cell system, characterizing the oxidizing gas or gases being provided into the fuel cell system, and calculating at least one of the steam:carbon ratio, fuel utilization and oxidizing gas utilization based on the step of characterization. |
| US09673461B2 |
Fuel cell
To prevent inflow of liquid water into a power generating portion even if the liquid water remains in a manifold, and to enable size reduction by making constant the contact or surface pressure. According to the present invention, in a fuel cell comprising a power generating section including an electrolyte membrane joined between an anode and a cathode, and a manifold to cause inflow and outflow of an hydrogen containing gas and an oxygen containing gas separately from each other to the anode and cathode; the manifold is formed with an inflow preventing portion to prevent inflow of a liquid water remaining in the manifold, into the power generating portion. |
| US09673459B2 |
Solid oxide fuel cell device
A single monolithic ceramic substrate has rectangular dimensions with thermal expansion dominant along the length. An inactive ceramic portion substantially surrounds a fuel cell active portion of scalable power. The active portion comprises a plurality of three-layer active structures, each including an electrolyte disposed between a first polarity electrode and a second polarity electrode, the electrolyte layers being co-fired with the inactive ceramic portion, and a first or second gas passage respectively associated with each first and second polarity electrode. The plurality of active structures are stacked in the thickness dimension with alternating polarity such that first polarity electrodes of adjacent active structures face each other with the associated first gas passage shared therebetween and second polarity electrodes of adjacent active structures face each other with the associated second gas passage shared therebetween. The power is scalable according to the number of active structures stacked to define the plurality. |
| US09673456B2 |
Non-PGM catalysts for ORR based on charge transfer organic complexes
A sacrificial support-based method, a mechanosynthesis-based method, and a combined sacrificial support/mechanosynthesis support based method that enables the production of supported or unsupported catalytic materials and/or the synthesis of catalytic materials from both soluble and insoluble transition metal and charge transfer salt materials. |
| US09673454B2 |
Sodium-ion secondary battery
With a small amount of a conductive additive, an electrode for a storage battery including an active material layer which is highly filled with an active material is provided. The use of the electrode enables fabrication of a storage battery having high capacity per unit volume of the electrode. By using graphene as a conductive additive in an electrode for a storage battery including a positive electrode active material, a network for electron conduction through graphene is formed. Consequently, the electrode can include an active material layer in which particles of an active material are electrically connected to each other by graphene. Therefore, graphene is used as a conductive additive in an electrode for a sodium-ion secondary battery including an active material with low electric conductivity, for example, an active material with a band gap of 3.0 eV or more. |
| US09673452B2 |
Graphene oxide as a sulfur immobilizer in high performance lithium/sulfur cells
The loss of sulfur cathode material as a result of polysulfide dissolution causes significant capacity fading in rechargeable lithium/sulfur cells. Embodiments of the invention use a chemical approach to immobilize sulfur and lithium polysulfides via the reactive functional groups on graphene oxide. This approach obtains a uniform and thin (˜tens of nanometers) sulfur coating on graphene oxide sheets by a chemical reaction-deposition strategy and a subsequent low temperature thermal treatment process. Strong interaction between graphene oxide and sulfur or polysulfides demonstrate lithium/sulfur cells with a high reversible capacity of 950-1400 mAh g−1, and stable cycling for more than 50 deep cycles at 0.1 C. |
| US09673448B2 |
Electrodes, lithium-ion batteries, and methods of making and using same
Described herein are improved composite anodes and lithium-ion batteries made therefrom. Further described are methods of making and using the improved anodes and batteries. In general, the anodes include a porous composite having a plurality of agglomerated nanocomposites. At least one of the plurality of agglomerated nanocomposites is formed from a dendritic particle, which is a three-dimensional, randomly-ordered assembly of nanoparticles of an electrically conducting material and a plurality of discrete non-porous nanoparticles of a non-carbon Group 4A element or mixture thereof disposed on a surface of the dendritic particle. At least one nanocomposite of the plurality of agglomerated nanocomposites has at least a portion of its dendritic particle in electrical communication with at least a portion of a dendritic particle of an adjacent nanocomposite in the plurality of agglomerated nanocomposites. |
| US09673445B2 |
Battery
A battery is provided. The battery includes a positive electrode including a positive electrode active material layer provided on a positive electrode current collector; a negative electrode; and a separator at least including a porous film, wherein the porous film has a porosity ε [%] and an air permeability t [sec/100 cc] which satisfy formulae of: t=a×Ln(ε)−4.02a+100 and −1.87×1010×S−4.96≦a≦−40 wherein S is the area density of the positive electrode active material layer [mg/cm2] and Ln is natural logarithm. |
| US09673439B2 |
Connecting structure for exteriorly connecting a battery cell and a load circuit by using two connecting graphite blocks
A connecting structure for exteriorly connecting a battery cell and a load circuit by using two graphite connecting graphite blocks, wherein the positive and negative electrode terminals of the battery cell are made of nickel, the battery cell is connected to the load circuit by the two connecting graphite blocks, respectively. The graphite is inexpensive and resistant to oxidation; whereas, the connecting graphite blocks and the nickel-plated metal made electrode terminals of the battery cell will dissolve in each other to form a carbon-nickel alloy after being brought into contact with one another, thus ensuring a smooth large-current discharge because of the reduction in resistance of external connection. |
| US09673436B2 |
Nonaqueous electrolyte secondary battery
The nonaqueous electrolyte secondary battery of the present invention has a positive electrode, a negative electrode, a separator interposed between the positive electrode and the negative electrode, and a nonaqueous electrolyte solution. The battery further has a porous heat-resistant layer provided between the separator and at least one of the positive electrode and the negative electrode, wherein the porous heat-resistant layer includes an inorganic filler and a binder. The inorganic filler included in the porous heat-resistant layer has a particle size distribution with two peaks, which are a first peak (P1) at a relatively small particle diameter and a second peak (P2) at a relatively large particle diameter. When the particle diameter of the first peak (P1) is D1 be and the particle diameter of the second peak (P2) is D2 being, the peak particle diameter ratio D1/D2 satisfies the condition 0.2≦D1/D2≦0.7. |
| US09673433B1 |
Deformable battery pack enclosure
An exemplary electrified vehicle assembly includes, among other things, a lower wall of a battery enclosure and an upper wall of the battery enclosure. The upper wall includes an upper wall deformation area that is configured to deform in response to a load applied to the battery enclosure prior to other areas of the upper wall. |
| US09673427B2 |
Battery pack
An embodiment of the present invention provides a battery pack comprising a plurality of battery cells; a protective circuit module coupled to at least two battery cells; and a case accommodating the battery cells and the protective circuit module, wherein the two battery cells are disposed on a surface of the case, and the protective circuit module is disposed between the two battery cells on the surface of the case. |
| US09673425B1 |
Method for manufacturing AMOLED backplane and structure thereof
The present invention provides a method for manufacturing an AMOLED backplane and a structure thereof. The method uses a solid phase crystallization process to crystallize and convert amorphous silicon into poly-silicon so as to prevent the issue of mura on a display device caused by excimer laser annealing and adopts a back channel etching structure to effectively reduce the number of masks used. The method for manufacturing the AMOLED backplane according to the present invention needs only seven masking operations and, compared to the prior art, saves two masking operations, thereby simplifying the manufacturing process, improving the manufacturing efficiency, and saving costs. |
| US09673424B2 |
Mask frame assembly, method of manufacturing the same, and method of manufacturing organic light-emitting display device
A method of manufacturing a mask frame assembly, the method including: forming a first through hole in a vicinity of a first deposition region of a first mask; forming a second through hole in a vicinity of a second deposition region of a second mask; forming a third through hole in a first portion of a supporting stick; forming a fourth through hole in a second portion of the supporting stick; aligning the first through hole with the third through hole; aligning the second through hole with the fourth through hole; inserting a fixing member in the aligned first and third through holes; and inserting the fixing member in the aligned second and fourth through holes, wherein the support stick couples the first mask and the second mask together via the fixing member. |
| US09673422B2 |
Display device
A display device includes a substrate and a reflection layer. The substrate includes a first emission region, a second emission region, a third emission region, and a non-emission region. The reflection layer overlaps the first emission region, the second emission region, and the non-emission region, and has an opening corresponding to the third emission region. The first emission region, the second emission region, and the third emission region emit different color light. |
| US09673416B2 |
Electro-optical apparatus, manufacturing method thereof, and electronic device
There is provided an electro-optical apparatus including an element substrate that includes a display region in which a plurality of light-emitting elements are arranged, and a peripheral region in which a terminal is disposed. The light-emitting element has a structure in which a reflective electrode, an optical adjustment layer, a first electrode, a light-emitting layer, and a second electrode are laminated, and the first electrode is electrically connected to a contact electrode. The terminal has a structure in which a first terminal layer that is formed by a first conductive film which is the same as the reflective electrode, a second terminal layer that is formed by a second conductive film which is the same as the contact electrode, and a third terminal layer that is formed by a third conductive film which is the same as the first electrode are laminated. |
| US09673406B2 |
Metal complexes with boron-nitrogen heterocycle containing ligands
Novel organic compounds comprising a boron-nitrogen heterocycle are provided. In particular, the compound contains an azaborine. The compounds may be used in organic light emitting devices to provide devices having improved photophysical and electronic properties. |
| US09673405B2 |
Organic electroluminescent device, display apparatus, and lighting apparatus
An organic electroluminescent device containing:a six-coordinate, ortho-metalated iridium complex represented by the formula (I): wherein V represents a trivalent linking group and is bound to L1 to L3 through covalent bonds;each of L1 to L3 is represented by the formula (II) andR1 represents a substituted aryl group having seven or more carbon atoms. |
| US09673401B2 |
Organic electroluminescent materials and devices
The present disclosure generally relates to novel compounds containing carbazole and triazine with different number of phenyl units attached to its core. In particular, the disclosure relates to compositions and/or devices comprising these compounds as hosts for PHOLEDs. |
| US09673400B2 |
Amine-based compound and organic light-emitting diode including the same
An amine-based compound is represented by Formula 1: An organic light-emitting diode includes a first electrode, a second electrode, and an organic layer between the first electrode and the second electrode. The organic layer includes an emission layer and the amine-based compound represented by Formula 1. The OLED including the amine-based compound represented by Formula 1 has good color purity, low driving voltage, high efficiency, high brightness, and/or a long lifetime. |
| US09673394B2 |
Conducting formulation
The invention relates to novel formulations comprising an organic semiconductor (OSC) and a conductive additive, to their use as conducting inks for the preparation of organic electronic (OE) devices, especially organic photovoltaic (OPV) cells, to methods for preparing OE devices using the novel formulations, and to OE devices and OPV cells prepared from such methods and formulations. |
| US09673393B2 |
Methods of forming memory arrays
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays. |
| US09673391B2 |
Resistance variable memory structure and method of forming the same
A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric. |
| US09673386B2 |
Structure and method to reduce shorting in STT-MRAM device
A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode. |
| US09673385B1 |
Seed layer for growth of <111> magnetic materials
A seed layer stack with a smooth top surface having a peak to peak roughness of about 0.5 nm over a range of 100 nm is formed by sputter depositing an X layer such as Mo on a Ni layer where the X layer has one or both of a larger bond energy and a greater atomic number than Ni. A (Ni/X)m laminate is formed and then an uppermost NiCr seed layer is deposited to enhance perpendicular magnetic anisotropy (PMA) in an overlying ferromagnetic layer. A <111> NiCr crystal structure promotes <111> texture in the ferromagnetic layer. X layers serve as a diffusion barrier to Ta migration from a bottom electrode and have good lattice matching with the adjoining Ni layer and uppermost NiCr layer. As a result of the smooth seed layer stack in a magnetic tunnel junction (MTJ), MTJ properties are improved and more reproducible. |
| US09673380B2 |
Temperature and field stable relaxor-PT piezoelectric single crystals
The application is directed to piezoelectric single crystals having shear piezoelectric coefficients with enhanced temperature and/or electric field stability. These piezoelectric single crystal may be used, among other things, for vibration sensors as well as low frequency, compact sonar transducers with improved and/or enhanced performance. |
| US09673378B2 |
Liquid-ejecting head, liquid-ejecting apparatus, piezoelectric element, and piezoelectric material
A liquid-ejecting head includes a pressure-generating chamber communicating with a nozzle opening, and a piezoelectric element. The piezoelectric element has piezoelectric layer contains a perovskite complex oxide containing Bi, La, Fe, and Mn and can undergo electric-field-induced phase transition. |
| US09673375B2 |
Power generator with an electrical component made from inertial mass and control circuit thereof
A force generator for introducing vibrational forces into a structure for vibration control of the structure includes an inertial mass, at least one actuator for generating a vibratory movement of the inertial mass relative to the structure, and a drive circuit constructed from components for driving the at least one actuator. At least part of the inertial mass is formed by one component of the drive circuit. |
| US09673362B2 |
Optical semiconductor element mounting package, and optical semiconductor device using the same
An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. |
| US09673360B2 |
Method for manufacturing light emitting device using strip-shaped first resin members
Provided is a method for manufacturing a light emitting device that can manufacture the light emitting device at low cost. The manufacturing method of a light emitting device includes: a mounting step of mounting a plurality of light emitting elements at predetermined intervals in one direction on a substrate; a first resin formation step of continuously forming a first resin layer in the one direction to directly cover the light emitting elements mounted; a trench formation step of forming a trench between the light emitting elements in a direction intersecting the one direction; and a second resin charging step of charging a second resin into the trench. |
| US09673358B2 |
Light emitting module
Disclosed is a light-emitting module capable of not only improving appearance quality but also maximizing light efficiency. The disclosed light-emitting module comprises: a circuit board; a light-emitting diode chip which is flip-bonded on the circuit board; and a housing which is positioned on the circuit board and surrounds the light-emitting diode chip, wherein the housing has a recess and reflective part having a curvature structure formed on an inner wall of the recess. |
| US09673357B2 |
Light emitting device package
An embodiment relates to a light-emitting device package. In an embodiment, the light-emitting device package includes a package body configured to include a top surface, a plate guide unit disposed on the top surface, and a cavity formed in the top surface, a light-emitting device disposed within the cavity, a plate disposed on the top surface of the package body and guided by the plate guide unit, and an adhesive member disposed between the top surface of the package body and the plate. The adhesive member includes a base layer made of a flexible material, a first adhesive tape disposed between the base layer and the top surface of the package body and bonded to the base layer and the top surface of the package body, and a second adhesive tape disposed between the base layer and the plate and bonded to the base layer and the plate. |
| US09673352B2 |
Semiconductor light emitting device
A light emitting device is provided. The light emitting device includes a substrate, an N type semiconductor layer formed on the substrate, an active layer, an electron-blocking layer, and a P type semiconductor layer formed on the electron-blocking layer. An N side electrode is formed on a first portion of the N type semiconductor layer, and the active layer is formed on a second portion of the N type semiconductor layer. The electron-blocking layer is a super lattice multi-layer structure formed on the active layer, the P type semiconductor layer is formed on the electron-blocking layer, and a P side electrode is formed on a portion of the P type semiconductor layer. |
| US09673350B2 |
Semiconductor component and process for fabricating a semiconductor component
A semi-conducting component including a semi-conducting layer of a first conductivity type including a plurality of semi-conducting zones of a second conductivity type opposite that of the semi-conducting layer, and an insulating layer. The component further includes a first bias mechanism configured to bias the semi-conducting layer and a second bias mechanism configured to bias a semi-conducting zone. The first bias mechanism includes a conducting layer in contact with the insulating layer and which includes passageways for each second bias mechanism with the spacing between the conducting layer and the second bias mechanism which is located facing the corresponding semi-conducting zone. |
| US09673348B2 |
Buffer layer deposition for thin-film solar cells
Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer or layers may be dispensed separately to the substrate web, rather than being mixed prior to their application. The web and/or the dispensed solutions may be heated by a plurality of heating elements. |
| US09673346B1 |
Optimally-angleable solar powered air systems
An optimally-angleable solar powered air system is a portable indoor solar heating unit that may stand upright or may be mounted to a door or window. The optimally-angleable solar powered air system has a frame having a solar panel mounted to a first side and a fan mounted to a second side of the frame. In use, the frame may stand inside a room at an angle facing the sun via a removable handle such that the solar panel is able to capture solar energy. The system may then convert solar energy into usable power to power the fan. The second side of the frame includes an air deflector which may direct airflow outwardly from the second side of the frame into the room. |
| US09673340B1 |
Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a first layer, a second layer, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the first layer. The second layer is between the first layer and the second insulating layer. The gate electrode is over the second insulating layer. There is a P-N junction between the first layer and the second layer. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate. The first layer, the first doped region, and the second doped region have a first type conductivity, which is opposite to a second type conductivity of the second layer. |
| US09673336B2 |
Method for manufacturing semiconductor device
A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor. |
| US09673335B2 |
Rectifier circuit including transistor whose channel formation region includes oxide semiconductor
In a rectifier circuit, by using a transistor whose off-state current is small as a so-called diode-connected MOS transistor included in the rectifier circuit, breakdown which is caused when a reverse bias is applied is prevented. Thus, an object is to provide a rectifier circuit whose reliability is increased and rectification efficiency is improved. A gate and a drain of a transistor are both connected to a terminal of the rectifier circuit to which an AC signal is input. In the transistor, an oxide semiconductor is used for a channel formation region and the off-state current at room temperature is less than or equal to 10−20 A/μm, which is equal to 10 zA/μm (z: zepto), when the source-drain voltage is 3.1 V. |
| US09673334B2 |
Low temperature poly silicon thin film transistors (LTPS TFTs) and TFT substrates
A LTPS TFT and a TFT substrate are disclosed. The LTPS TFT includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage. In this way, the feed through voltage may be reduced such that the TFT performance is enhanced. |
| US09673333B2 |
P-Si TFT and method for fabricating the same, array substrate and method for fabricating the same, and display device
A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions. |
| US09673328B2 |
Structure and method for providing line end extensions for fin-type active regions
A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region. |
| US09673323B2 |
Embedded JFETs for high voltage applications
A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. |
| US09673321B2 |
Pillar-shaped semiconductor device and method for producing the same
An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs. |
| US09673320B2 |
Transistor with improved avalanche breakdown behavior
A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer. |
| US09673318B1 |
Semiconductor device including a gate trench having a gate electrode located above a buried electrode
A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench. |
| US09673311B1 |
Electronic device including a multiple channel HEMT
An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer. |
| US09673308B2 |
Semiconductor device manufacturing method
According to the present invention, since the buffer layer is formed by multiple ion implantations of different acceleration energies and the non-diffusion region in which impurity do not diffuse is left between the buffer layer and the collector layer, the semiconductor device which can supply sufficient holes to the drift layer at the turn-off can be manufactured while the withstand voltage is ensured. |
| US09673304B1 |
Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer. |
| US09673302B2 |
Conversion of strain-inducing buffer to electrical insulator
Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator. |
| US09673299B2 |
Method for manufacturing split-gate power device
The present invention relates to the field of manufacturing technologies of semiconductor power devices, and more particularly to a method for manufacturing a split-gate power device. In the method for manufacturing a split-gate power device according to the present invention, lateral etching is added to form lateral recesses of a control gate groove below a first insulating film in a process of forming the control gate groove by etching, and therefore, after a first conductive film is deposited, the first conductive film can be directly etched by using the first insulating film as a mask to form control gates. The technical process of the present invention is simplified, reliable and easy to control, and can greatly improve the yield of the split-gate power device. The present invention is particularly suitable for the manufacture of 25V-200V semiconductor power devices. |
| US09673298B2 |
Integrated vertical trench MOS transistor
A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip. |
| US09673294B2 |
Bipolar transistor structure and a method of manufacturing a bipolar transistor structure
According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. |
| US09673291B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion. |
| US09673287B2 |
Reliable and robust electrical contact
In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact. |
| US09673283B2 |
Power module for supporting high current densities
A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2. |
| US09673282B2 |
Handle substrates of composite substrates for semiconductors, and composite substrates for semiconductors
A handle substrate of a composite substrate for a semiconductor is provided. The handle substrate is composed of polycrystalline alumina. The handle substrate includes an outer peripheral edge part with an average grain size of 20 to 55 μm and a central part with an average grain size of 10 to 50 μm. The average grain size of the outer peripheral edge part is 1.1 times or more and 3.0 times or less of that of the central part of the handle substrate. |
| US09673281B2 |
Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates. |
| US09673280B2 |
Cobalt silicidation process for substrates comprised with a silicon-germanium layer
A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions. |
| US09673279B2 |
Semiconductor device having multi-channel and method of forming the same
A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern. |
| US09673277B2 |
Methods and apparatus for forming horizontal gate all around device structures
A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure. |
| US09673274B2 |
Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench. |
| US09673272B2 |
Semiconductor device including capacitor and method of fabricating the same
A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode. |
| US09673271B2 |
Adaptive capacitors with reduced variation in value and in-line methods for making same
A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor. |
| US09673269B2 |
Integrated capacitor comprising an electrically insulating layer made of an amorphous perovskite-type material and manufacturing process
An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided. |
| US09673268B2 |
Integrated inductor for integrated circuit devices
A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. |
| US09673267B2 |
Organic light emitting diode display device having a capacitor with stacked storage electrodes and method for manufacturing the same
An organic light emitting diode display device is disclosed which includes: scan, data and power lines crossing one another and arranged to define a pixel region; a switching thin film transistor disposed at an intersection of the scan and data lines; an organic light emitting diode disposed in the pixel region; a driving thin film transistor disposed between the power line and the organic light emitting diode; and a storage capacitor disposed adjacently to the organic light emitting diode and configured to charge a data signal which is applied from the data line. The storage capacitor includes a plurality of sub storage capacitors in which a plurality of storage electrodes are stacked alternately with one another. |
| US09673263B2 |
Color filter forming substrate and organic EL display device
Provided is an organic EL display device capable of preventing or restraining color shift or color mixing in an image displayed in each of its pixels, this inconvenience being caused by the entry of light into the pixel from an organic EL element of a pixel adjacent to the pixel; and provided is a color filter forming substrate making it possible to produce such an organic EL display device. The color filter forming substrate is a substrate for an organic EL display device, in which: a pixel-dividing light-shielding region is arranged over one surface of a base material comprising a transparent substrate to make plural pixel regions into a region-divided form; and plural color-filter-forming coloring layers for multiple colors are arranged to the predetermined pixel regions in accordance with the respective colors, characterized in that a light-shielding layer is arranged in the pixel-dividing light-shielding region, and a surface of the light-shielding layer farthest from the one surface of the base material is positioned farther from the one surface of the base material than respective surfaces of the color-filter-forming coloring layers in the respective colors, these surfaces not being respective base material side surfaces of the coloring layers, are positioned. |
| US09673259B2 |
Organic photoelectronic device and image sensor
Example embodiments relate to an organic photoelectronic device that includes a first electrode, a light-absorption layer on the first electrode and including a first p-type light-absorption material and a first n-type light-absorption material, a light-absorption auxiliary layer on the light-absorption layer and including a second p-type light-absorption material or a second n-type light-absorption material that have a smaller full width at half maximum (FWHM) than the FWHM of the light absorption layer, a charge auxiliary layer on the light-absorption auxiliary layer, and a second electrode on the charge auxiliary layer, and an image sensor including the same. |
| US09673257B1 |
Vertical thin film transistors with surround gates
A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate. |
| US09673243B2 |
Photosensitive imaging devices and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. |
| US09673242B2 |
Image sensor with micro lens including a plurality of layers each of different thickness
An image sensor includes a color filter configured to pass a specific color of light; a micro lens formed under the color filter and configured with a plurality of layers in which an upper layer has a smaller area than a lower layer; and a photo device formed under the micro lens and configured to receive light passing through the micro lens and convert the received light into an electrical signal. |
| US09673237B2 |
Depth pixel included in three-dimensional image sensor, three-dimensional image sensor including the same and method of operating depth pixel included in three-dimensional image sensor
A depth pixel of a three-dimensional image sensor includes a first photo gate which is turned on/off in response to a first photo control signal, a first photo detection area configured to generate first charges based on a received light reflected from a subject when the first photo gate is turned on, a first transmission gate which is turned on/off in response to a first transmission control signal, a first floating diffusion area configured to accumulate the first charges generated from the first photo detection area when the first transmission gate is turned on, and a first compensation unit configured to generate second charges which are different from the first charges based on ambient light components included in the received light to supply the second charges to the first floating diffusion area. |
| US09673233B2 |
Array substrate, display panel and method for manufacturing array substrate
An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole. |
| US09673231B2 |
Array substrate having via-hole conductive layer and display device
Embodiments of the disclosure provide an array substrate having via-hole conductive layer and display device. The array substrate includes: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer. |
| US09673230B2 |
Pixel array
A pixel array includes a plurality of scan lines, a plurality of data lines, a first active device, a second active device, a first pixel electrode and a second pixel electrode. The first active device and the second active device are electrically connected to the corresponding scan line and data line respectively. The first pixel electrode is electrically connected to the first active device through a contact hole. The second pixel electrode is electrically connected to the second active device through the contact hole. |
| US09673225B2 |
Array substrate, fabrication method thereof and display device
Embodiments of the present invention provide an array substrate, a fabrication method thereof and a display device. The array substrate comprises a driver IC and pixel units, wherein each port of the driver IC is connected to a plurality of pixel units through a connecting structure, each connecting structure comprises a connecting line connected between a port of the driver IC and a plurality of pixel units, at least some of the connecting structures also comprise resistance regulating units for changing the total resistance values of the connecting structures, and the resistance regulating units are connected in series with the respective connecting lines; and/or the resistance regulating units are connected in parallel with parts of the respective connecting lines, so that the differences among resistance values of connecting structures can be reduced, and in turn the display effect of a display panel is improved. |
| US09673224B2 |
Semiconductor device
To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor. |
| US09673219B2 |
Vertical semiconductor device with thinned substrate
A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. |
| US09673216B1 |
Method of forming memory cell film
Disclosed herein are methods of forming memory cell films in 3D memory. An opening having a sidewall may be formed through a stack of alternating layers of silicon oxide and silicon nitride. Bird's beaks may be formed in the silicon nitride at interfaces with the silicon oxide. In one aspect, bird's beaks are formed using a wet SiN etch. In one aspect, bird's beaks are formed by oxidizing SiN. A dilute hydrofluoric acid (DHF) clean may be performed within the opening after forming the bird's beaks in the silicon nitride. A memory cell film may be formed in the opening after performing the DHF clean. The memory cell film is straight, or nearly straight, from top to bottom in a memory hole. The memory cell film is not as susceptible to parasitic charge trapping as a memory cell film having a wavy contour. Therefore, neighbor WL interference may be reduced. |
| US09673214B2 |
Semiconductor device
A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another. |
| US09673211B1 |
Integration of a memory transistor into high-k, metal gate CMOS process flow
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions. |
| US09673208B2 |
Method of forming memory array and logic devices
A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas. |
| US09673207B2 |
Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ΔMAX. |
| US09673205B2 |
Embedded nonvolatile memory and forming method thereof
A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. |
| US09673202B2 |
Structure and method for FinFET SRAM
Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure. |
| US09673200B2 |
Semiconductor device structure and method of manufacturing the same
A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure. |
| US09673198B2 |
Semiconductor devices having active regions at different levels
A semiconductor device has active regions with different conductivity types. A substrate has a PMOS region and an NMOS region. A first active region is in the PMOS region. A second active region is in the NMOS region. A semiconductor layer is on the first active region. A first gate electrode crosses the first active region and extends on the semiconductor layer. A second gate electrode is on the second active region. An upper end of the first active region extends to a level lower than an upper end of the second active region. A lower end of the first active region extends to a level lower than a lower end of the second active region. |
| US09673192B1 |
Semiconductor device including a resistor metallic layer and method of forming the same
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross member and a second cross member, and a first gain resistor including a first gain resistor metallic strip coupled to the first cross member. The semiconductor device also includes an amplifier over the substrate and coupled to the first gain resistor metallic strip. |
| US09673191B2 |
Efficient fabrication of BiCMOS devices
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region. |
| US09673188B2 |
Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor
A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. |
| US09673182B2 |
Package on package bonding structure and method for forming the same
A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound. |
| US09673181B2 |
Package on package (PoP) bonding structures
Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures. |
| US09673180B2 |
Array substrate of organic light-emitting diodes and method for packaging the same
An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic light-emitting diodes, to shorten the package process time, and to improve the substrate utilization and the production efficiency. The array substrate of organic light-emitting diodes includes a plurality of display panels disposed in an array of rows and columns, wherein at least two adjacent display panels are connected through a frame adhesive, and there is no cutting headroom between at least one side of the at least two adjacent display panels. |
| US09673178B2 |
Method of forming package structure with dummy pads for bonding
Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die. |
| US09673174B2 |
Through silicon via bonding structure
System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. |
| US09673173B1 |
Integrated circuit package with embedded passive structures
An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer. |
| US09673171B1 |
Integrated circuit packaging system with coreless substrate and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects. |
| US09673169B2 |
Method and apparatus for a wafer seal ring
A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers. |
| US09673168B2 |
Connection body
Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles. |
| US09673165B2 |
Component mounting apparatus
A component mounting apparatus includes a tape attaching unit, a component mounting unit and a component compression unit provided in this order. A time measuring unit measures time having passed after completion of predetermined work performed on all the substrates transferred to the tape attaching unit, the component mounting unit, and the component compression unit, respectively. When preparation for transferring the substrates to the tape attaching unit is not completed within a predetermined time after the start of measurement performed by the time measuring unit, the respective substrates, which wait in the tape attaching unit, the component mounting unit, and the component compression unit, are forcibly transferred to the downstream sides and predetermined work is performed on the respective substrates that are forcibly transferred to the component mounting unit and the component compression unit. |
| US09673162B2 |
High power semiconductor package subsystems
A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect. |
| US09673161B2 |
Bonded structures for package and substrate
The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. |
| US09673158B2 |
Formation of connectors without UBM
A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer. |
| US09673157B2 |
Processing of thick metal pads
In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing. |
| US09673156B2 |
Package structure
A package structure includes a first insulation layer, at least one first electronic component, and a first re-distribution layer. The first electronic component is embedded within the first insulation layer, and the first electronic component includes plural first conducting terminals disposed on a bottom surface of the first electronic component. At least part of the bottom surface of the first electronic component is exposed from a bottom surface of the first insulation layer. The first re-distribution layer is formed on the bottom surface of the first insulation layer and contacted with the corresponding first conducting terminals. |
| US09673155B2 |
Integrated tunable filter architecture
An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated. |
| US09673151B2 |
Semiconductor package having metal layer
A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another. |
| US09673146B2 |
Low temperature tungsten film deposition for small critical dimension contacts and interconnects
Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process. |
| US09673144B2 |
Semiconductor device with metal think film and via
A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line. |
| US09673143B2 |
Semiconductor device and manufacturing method of the same
The semiconductor device 1 includes an insulating substrate 2, a conductive part 3 that extends in a first direction, a conductive part 4 that is separated in a second direction and extends in the first direction, conductive parts 5 that are lined along the first direction between the part 3 and the part 4, high-side switches 11, 12 and 13, low-side switches 14, 15 and, signal terminals that are arrayed along the first direction, a power supply terminal 21 that is electrically connected to the part 3, a ground terminal 22 that is electrically connected to the part 4, and output terminals 23, 24 and 25 that are electrically connected respectively to the corresponding parts 5, arrayed along the first direction on the other end side of the substrate 2, and provided over a straight line L that passes through the part 4 and extends in the first direction. |
| US09673128B2 |
Power module and fabrication method for the same
A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module. |
| US09673127B2 |
Silicone-based thermal interface materials
Embodiments described herein relate to silicone-based thermal interface materials which include a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm−3/2. |
| US09673125B2 |
Interconnection structure
A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad. |
| US09673122B2 |
Micro lead frame structure having reinforcing portions and method
In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. |
| US09673121B2 |
Carrierless chip package for integrated circuit devices, and methods of making same
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds. |
| US09673119B2 |
System and method for bonding package lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill. |
| US09673117B2 |
Semiconductor module
A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece. |
| US09673116B2 |
On chip electrostatic discharge (ESD) event monitoring
An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure. |
| US09673114B1 |
Precision substrate material removal using miniature-column charged particle beam arrays
Methods, devices and systems for patterning of substrates using charged particle beams without photomasks and without a resist layer. Material can be removed from a substrate, as directed by a design layout database, localized to positions targeted by multiple, matched charged particle beams. Reducing the number of process steps, and eliminating lithography steps, in localized material removal has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material removal allows for controlled variation of removal rate and enables creation of 3D structures or profiles. Local gas injectors and detectors, and local photon injectors and detectors, are local to corresponding ones of the columns, and can be used to facilitate rapid, accurate, targeted substrate processing. |
| US09673112B2 |
Method of semiconductor fabrication with height control through active region profile
The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions. |
| US09673108B1 |
Fabrication of higher-K dielectrics
A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer. |
| US09673102B2 |
Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions. |
| US09673099B2 |
Method of fabricating integrated circuit devices
An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors. |
| US09673094B2 |
Semiconductor device having via hole coated in side surfaces with heat treated nitride metal and method to form the same
A semiconductor device having a via hole whose side surface is covered with nitride metal is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials. The via hole is filled with a back metal and in side surfaces thereof is covered with the nitride metal which is heat treated at a preset temperature for a preset period. Nitrogen atoms in the nitride metal diffuse into the nitride semiconductor materials in the insulating regions and compensate nitride vacancies therein. The interface between the nitride metal and the nitride semiconductor material is converted into an altered region that shows enough resistivity to suppress currents leaking from the via hole metal to the conductive region of the nitride semiconductor material. |
| US09673089B2 |
Interconnect structure with enhanced reliability
An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided. |
| US09673087B2 |
Interconnect structures incorporating air-gap spacers
A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. |
| US09673084B2 |
Isolation scheme for high voltage device
Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage. |
| US09673082B2 |
Method of fabricating semiconductor device isolation structure
A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation. |
| US09673077B2 |
Pedestal construction with low coefficient of thermal expansion top
A support assembly for use in semiconductor processing includes an application substrate, a heater layer disposed directly onto the application substrate, an insulation layer disposed onto the heater layer, and a second substrate disposed onto the insulation layer. The heater layer is directly disposed onto the application substrate by a layered process such that the heater layer is in direct contact with the application substrate. The application substrate defines a material having a relatively low coefficient of thermal expansion that is matched to a coefficient of thermal expansion of the heater layer. |
| US09673075B2 |
Wafer container with door guide and seal
A wafer container that reduces or alleviates one or more of the problems associated with excessive container wall deflection due to loading and excessive particulate generation, particularly as those problems are experienced with containers for 450 mm diameter and larger wafers. The container has an enclosure and door with interlocking features to enable transfer of tension load to the door to minimize deflection of container surfaces. The container may include a gasketing arrangement compatible with the interlock feature. The container may include a removable door guide that improves centering of the door during door installation, and that is made of low particle generating material to reduce particulates. |
| US09673073B2 |
Manufacturing method of semiconductor device, and semiconductor device
Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor. |
| US09673068B2 |
Apparatus and method for processing substrate with film having porous structure (porous film) formed on surface layer thereof
A method for processing a substrate with a porous film having a porous structure formed on a surface layer thereof includes the following a) and b) steps. The a) step is a step of mixing a first processing solution containing water with gas to generate droplets of the first processing solution and injecting the droplets of the first processing solution to the porous film. In addition, the b) step is a step of, after the a) step, mixing a second processing solution which is an organic solvent having higher volatility than the first processing solution with the gas to generate droplets of the second processing solution and injecting the droplets of the second processing solution to the porous film. |
| US09673058B1 |
Method for etching features in dielectric layers
A method for etching features in a silicon oxide containing etch layer disposed below a patterned mask in a chamber is provided. An etch gas comprising a tungsten containing gas is flowed into the chamber. The etch gas comprising the tungsten containing gas is formed into a plasma. The silicon oxide etch layer is exposed to the plasma formed from the etch gas comprising the tungsten containing gas. Features are etched in the silicon oxide etch layer while exposed to the plasma formed from the etch gas comprising the tungsten containing gas. |
| US09673055B2 |
Method for quadruple frequency FinFETs with single-fin removal
A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed. |
| US09673054B2 |
Array of gated devices and methods of forming an array of gated devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed. |
| US09673053B2 |
Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer. |
| US09673043B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, substrate processing system and recording medium
There is provided a technique including: (a) forming a thin film containing a predetermined element, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element, carbon and a halogen element having a chemical bond between the predetermined element and carbon to the substrate; (a-2) supplying an oxidizing gas to the substrate; and (a-3) supplying a catalytic gas to the substrate; (b) removing a first impurity from the thin film by thermally processing the thin film at a first temperature higher than a temperature of the substrate in (a); and (c) removing a second impurity different from the first impurity from the thin film by thermally processing the thin film at a second temperature equal to or higher than the first temperature after performing (b). |
| US09673042B2 |
Methods and apparatus for in-situ cleaning of copper surfaces and deposition and removal of self-assembled monolayers
A method of processing includes: providing a substrate having a contaminant material disposed on the copper surface to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber; providing hydrogen (H2) gas to the HWCVD chamber; heating one or more filaments disposed in the HWCVD chamber to a temperature sufficient to dissociate the hydrogen (H2) gas; exposing the substrate to the dissociated hydrogen (H2) gas to remove at least some of the contaminant material from the copper surface; cooling the one or more filaments to room temperature; exposing the substrate in the HWCVD chamber to one or more chemical precursors to deposit a self-assembled monolayer atop the copper surface; and depositing a second layer atop the substrate. |
| US09673041B2 |
Plasma assisted atomic layer deposition titanium oxide for patterning applications
The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction. |
| US09673040B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer. |
| US09673038B2 |
Gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors
A method for gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors is disclosed in various embodiments. According to one embodiment of the invention, a method is provided for processing a semiconductor substrate. The method includes providing a substrate containing a germanium-containing semiconductor or a compound semiconductor, and exposing the substrate to a process gas containing a sulfur-containing gas and a nitrogen-containing gas that passivates a surface of the germanium-containing semiconductor or the compound semiconductor with sulfur. According to another embodiment, the germanium-containing semiconductor or the compound semiconductor has an oxidized layer thereon and the exposing to the process gas removes the oxidized layer from the substrate. According to another embodiment, the substrate may be treated with hydrogen fluoride (HF) gas and ammonia (NH.sub.3) gas to remove the oxidized layer from the substrate before passivating the germanium-containing semiconductor or compound semiconductor with sulfur. |
| US09673035B2 |
Ion source, and mass analysis apparatus including same
According to one embodiment of the present invention, an ion source includes: an anode tube in which gas flowing in through one side is ionized and discharged to the other side and in which a slit is formed on the outer circumference thereof; a filament which emits thermal electrons toward the slit so as to ionize the gas; and a diffusion-preventing body arranged between the filament and the slit and having at least one hole through which the thermal electrons can pass so as to reduce the diffusion of the thermal electrons flowing into the anode tube. |
| US09673034B2 |
Mass spectrometer
A mass spectrometer is disclosed comprising a time of flight mass analyzer. The time of flight mass analyzer comprises an ion guide comprising a plurality of electrodes which are interconnected by a series of resistors forming a potential divider. Ions are confined radially within the ion guide by the application of a two-phase RF voltage to the electrodes. A single phase additional RF voltage is applied across the potential divider so that an inhomogeneous pseudo-potential force is maintained along the length of the ion guide. |
| US09673027B2 |
Test apparatus and plasma processing apparatus
A test apparatus for efficiently and accurately testing a high frequency voltage dependency of an impedance of a test object without damaging the test object. The test apparatus includes a high frequency power source unit, a reference waveform generator, a matching device, an oscilloscope, a control panel, and a main control unit. The test apparatus may boost a high frequency pulse output at a relatively low power from the high frequency power source unit to a voltage required for a high frequency withstand voltage test to be applied to a test object in a state where impedance matching is performed between the high frequency power source unit and the test by the matching device, that is, under a tuned state. Whether the waveform of the voltage applied to the test object is a defined waveform may be concisely monitored and observed by the oscilloscope. |
| US09673026B2 |
Edge ramping
Systems and methods for performing edge ramping are described. A system includes a base RF generator for generating a first RF signal. The first RF signal transitions from one state to another. The transition from one state to another of the first RF signal results in a change in plasma impedance. The system further includes a secondary RF generator for generating a second RF signal. The second RF signal transitions from one state to another to stabilize the change in the plasma impedance. The system includes a controller coupled to the secondary RF generator. The controller is used for providing parameter values to the secondary RF generator to perform edge ramping of the second RF signal when the second RF signal transitions from one state to another. |
| US09673019B2 |
Electron detection system
An electron detection system for detecting secondary electrons emitted from a sample irradiated by a Focused Ion Beam (FIB). The FIB emanates from a FIB column and travels along a beam axis within a beam region, which extends from the FIB column to the sample. The system comprises an electron detector configured for detecting the secondary electrons, and a deflecting field configured to deflect a trajectory of the secondary electrons, which were propagating towards the FIB column, to propel away from the beam axis and towards the electron detector. The deflecting field may be configured to divert the trajectory of secondary electrons while the secondary electrons are generally within the beam region. |
| US09673010B2 |
Relay
A relay according to one embodiment of the present invention includes a housing, a cylinder, a fixed contactor coupled to the housing, a movable contactor contactable with or separated from the fixed contactor, a coil assembly disposed in the housing to generate a magnetic field, a movable shaft coupled with the movable contactor at an upper portion thereof, a fixed core inserted into the cylinder, a moving core fixed to the movable shaft to move the movable shaft in a pressing manner, a wipe spring to supply elastic force to the movable shaft, and a return spring located between the fixed core and the moving core. The moving core includes a cylindrical protrusion extending toward the fixed core and surrounding the movable shaft. |
| US09673009B2 |
Direct current relay
Disclosed embodiments relate to a direct current relay. In some embodiments, a direct current relay is capable of reducing noise by attenuating an impact generated between a fixed core and a moving core during an ‘ON’ operation, and by attenuating an impact generated between a shaft and a middle plate during an ‘OFF’ operation. |
| US09673006B2 |
Exhaust diffuser for a gas-insulated high voltage circuit breaker
A gas exhaust diffuser for a circuit breaker, comprising a first casing extending longitudinally along a principal axis with an open end to allow gas to enter and a closed end, and a second casing coaxial to the first casing, extending along the principal axis, with at least one outlet to allow gas to escape, the closed end of the first casing being arranged in the second casing and the first casing having at least two radial openings near its closed end to provide a fluid communication between the first and second casing. A plurality of incurved elements are positioned radially in the second casing at the at least one radial opening to create a rotation of an entering exhaust flow in a plan perpendicular to the principal axis, thereby generating a substantially helicoidally-shaped exhaust flow path in the second casing. |
| US09673005B2 |
Switchgear
The invention provides a switchgear that is capable of increasing a degree of freedom of a position of a moving arcing contact in a circuit breaker, does not require dimension management of components and a mechanism for adjusting a position of the moving arcing contact, and is capable of simplifying fabrication of components and assembly of devices and reducing cost. The switchgear according to the invention includes: a circuit breaker that is configured of a fixed arcing contact installed at a fixed-side conductor and a moving arcing contact installed at a moving electrode that opens and closes with respect to the fixed arcing contact; a linear motor that generates drive force for operating the moving arcing contact; a position detecting device that detects a position of a moving element of the linear motor; a contact detecting device that detects a contact state between the fixed arcing contact and the moving arcing contact; and a control device that sets a moving range of the moving arcing contact by controlling a voltage and a phase to be supplied to the linear motor based on the contact state between the fixed arcing contact and the moving arcing contact, which is detected by the contact detecting device, and position information of the moving element of the linear motor, which is detected by the position detecting device. |
| US09673004B1 |
Electrical switching apparatus, and arc chamber assembly and associated circuit protection method
An arc chamber assembly is for an electrical switching apparatus. The electrical switching apparatus includes a stationary contact and a movable contact structured to move into and out of engagement with the stationary contact in order to close and open the electrical switching apparatus, respectively. The arc chamber assembly comprises a plurality of splitter plates; a current loop member coupled to the plurality of splitter plates and being structured to extend from the stationary contact; an element coupled to the current loop member; and a number of permanent magnets each coupled to the element. The current loop member and the number of permanent magnets are structured to draw an electrical arc into the plurality of splitter plates. |
| US09673000B2 |
Multifunction key and electronic device with multifunction key
A multifunction key includes a key member, a conductive member, and a circuit baseboard. A portion of the key member extends out from a shell of an electronic device; the conductive member is fixed on a bottom of the key member. The conductive member includes a first protrusion member and a second protrusion member. One surface of the circuit baseboard includes a conductive layer and a resistance layer respectively contacting the first and the second protrusion member. Another surface of the circuit baseboard includes a first and second conductive terminal respectively connected to the conductive layer and the resistance layer. The conductive layer, resistance layer, first and second conductive terminal, conductive member, and an internal circuit of the electronic device form a circuit loop. When the key member moves, a resistance value of the resistance layer within in the circuit loop is changed and produces a corresponding key command. |
| US09672997B2 |
Method for the initial adjustment of a control device for electronic equipment
A method for control device adjustment comprising applying a preload simultaneously to a plurality of shafts of a control device so as to take up initial assembly play, wherein the control device comprises an upper actuating element that is movable relative to a lower supporting mounting, a lower supporting mounting, a switch that is actuated by the upper actuating element, and an articulated structure that is interposed vertically between the upper actuating element and the lower mounting to keep the upper actuating element parallel to a horizontal plane during its vertical downward movement relative to a frame, and the at least one shaft. The method also comprises providing an adjustment stop fixed relative to the lower mounting and forming a stop surface that interacts with a facing portion of the shaft. |
| US09672996B2 |
Control device of the spring type particularly for a high-voltage or medium-voltage circuit breaker or switch
The control device possesses a rigid main part combining most of the functional elements of this type of control device. It is made up of two portions of a rotary shaft, having placed between them a cam and a support arm that are connected together by a pivot that is offset relative to the axis of rotation. A toothed wheel having an inner set of teeth is placed around the support arm that is provided with a rachet system. The toothed wheel has an outer set of teeth-driven by a motor, via an intermediate gearwheel. The pivot controls the compression of the actuator spring by the assembly rotating. The device is applicable to high and medium voltage circuit breakers and switches. |
| US09672993B2 |
Electricity storage device and electricity storage module
An electrical storage device includes a casing that has an opening, an electrode assembly that is placed inside the casing, a terminal plate that is electrically connected to the electrode assembly, and a holder that is provided to surround the terminal plate, the terminal plate having a step or a slope in an area in which the terminal plate comes in contact with the holder. |
| US09672989B2 |
Solid electrolytic capacitor assembly for use in a humid atmosphere
A capacitor assembly that is capable of exhibiting good properties under humid conditions. The ability to perform under such conditions is due in part to the use of an intrinsically conductive polymer in the solid electrolyte that contains repeating units having the following formula (I): wherein, R is (CH2)a—O—(CH2)b; a is from 0 to 10; b is from 1 to 18; Z is an anion; and X is a cation. Due to its unique structure, the polymer is not highly sensitive to moisture. Consequently, the resulting capacitor assembly may exhibit excellent electrical properties even when exposed to high humidity levels. |
| US09672985B2 |
Capacitor and method for manufacturing the same
A capacitor includes a capacitor element that is a wound element or an element other than the wound element, and that includes electrode bodies each of which is in an anode side and a cathode side, and separators that intervenes between the electrode bodies; a sealing member that seals an opening of a case member accommodating the capacitor element; at least one electrode protrusion that protrudes from one of the electrode bodies on an element end-face of the capacitor element, at least one of current collector plate that is connected to the electric protrusion; and at least one terminal member that is disposed in the sealing member, and is superposed on the current collector plate, a side face part of the terminal member being welded to a side face part of the current collector plate. |
| US09672983B2 |
Peel resistant multilayer wiring board with thin film capacitor and manufacturing method thereof
A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer. |
| US09672980B2 |
R-T-B-M-C sintered magnet and production method and an apparatus for manufacturing the R-T-B-M-C sintered magnet
The present invention discloses an R-T-B-M-C sintered magnet and a method for manufacturing the R-T-B-M-C sintered magnet from an R-T-B-M-C alloy powder including the lubricant. The present invention also discloses an apparatus for manufacturing the R-T-B-M-C sintered magnet from the R-T-B-M-C alloy powder including the lubricant. The apparatus includes an alloy powder feeding mechanism for distributing the R-T-B-M-C alloy powder including the lubricant, a filling mechanism including a mold for receiving the R-T-B-M-C alloy powder including the lubricant, a press mechanism for compressing the R-T-B-M-C alloy powder including the lubricant and a stacking mechanism for storing the mold including the R-T-B-M-C alloy powder including the lubricant. |
| US09672977B2 |
Transparent capacitive wireless powering system
A transparent capacitive powering system (200) is disclosed. The system comprises a pair of receiver electrodes (241, 242) connected to a load (250) through an inductor (260), wherein the inductor is coupled to the load to resonate the system; and a transparent infrastructure (220) having at least a first layer (130) of a non-conductive transparent material and a second layer (120) of a conductive transparent material coupled to each other, wherein the second layer is arranged to form a pair of transmitter electrodes (221, 222), wherein the pair of receiver electrodes are decoupled from the second layer, thereby forming a capacitive impedance between the pair of transmitter electrodes and the pair of receiver electrodes, wherein a power signal generated by a driver (210) is wirelessly transferred from the pair of transmitter electrodes to the pair of receiver electrodes to power the load when a frequency of the power signal substantially matches a series-resonance frequency of the first inductor and the capacitive impedance. |
| US09672976B2 |
Multi-mode wireless charging
A device may include a multiple inductive coils arranged concentrically for operating according multiple modes of wireless power transfer. The device may include multiple layers of magnetic shields to protect device components from the effects of the magnetic field used for power transfer. Construction and material of multiple layers of shields may be based on addressing individually the different parameters of the multiple modes of operation and based on the combined effect of the layers in each mode of operation. In some examples, the device may include first and second ferrite shields each having different magnetic properties. |
| US09672974B2 |
Magnetic component and power transfer device
A magnetic component includes a first winding and a second winding which is insulated from the first winding and magnetically couples with the first winding. The first winding forms a first coil unit by being wound. The second winding forms a second coil unit by being wound about the same axis as the first winding. The second winding forming the second coil unit is disposed in areas X and Z. The magnetic component has the first coil unit and the second coil unit at positions that satisfy Equations 1 and 3. |
| US09672972B2 |
Winding component
A winding component includes a core that surrounds an outer circumference of a coil and end surfaces of flanges to form a closed magnetic circuit, in which notches through which end portions of the coil are drawn outward are so formed in the flanges that each of the notches extends radially inward from an outer circumferential edge of the corresponding flange, a wall that surrounds each of the notches such that the wall stands axially outward on the flange, a thick portion in a winding part in correspondence with the notches and thicker than other portions of the winding part, and a lid formed of a sidewall between an outer circumferential surface of the wall and the core and covers the outer circumferential surface of the wall and a top plate at an axially outer end of the sidewall and covers an opening in the wall. |
| US09672965B2 |
Reactor
A reactor includes a laminated core formed by laminating soft-magnetic ribbons in a lamination direction. The laminated core has a gap formed across a magnetic path direction in the laminated core. The laminated core also has a flat facing surface that faces the gap and a pair of flat side surfaces that are respectively on opposite sides of the facing surface in the lamination direction. The laminated core further has a pair of first corner curved surfaces that are formed between the facing surface and the pair of side surfaces. Each of the first corner curved surfaces has a width in the lamination direction greater than the thickness of each of the soft-magnetic ribbons. For each of the first corner curved surfaces, a length of the first corner curved surface in the magnetic path direction is greater than the width of the first corner curved surface in the lamination direction. |
| US09672960B2 |
Exterior member and electric wire wiring structure
An exterior member which covers the circumference of an electric wire, which is wired between electrical components, along the electric wire, and is supported by a supporting body while one side in a circumferential direction is exposed, includes an exterior member body that is formed into a long cylindrical shape and which has a predetermined background color, and an identifying mark that is provided on the outer surface of the exterior member body and which has another predetermined color different from the background color. The exterior member body is formed with at least one bent part which is bent at a middle position in a longitudinal direction, and the identifying mark is provided to face the one side while the exterior member is supported by the supporting body. |
| US09672957B2 |
Shielded electrical cable
A shielded electrical cable (50) includes conductor sets (51a, 51b) spaced apart along a width of the cable and extending along a length of the cable. Each conductor set includes first and second insulated conductors (52a, 52b), one or two drain grounding wires (54) disposed between the first and second insulated conductors, first and second conductive shielding films (56a, 56b) disposed on opposite first and second sides of the conductor set, and an adhesive layer (59) bonding the first shielding film to the second shielding film. |
| US09672949B2 |
X-ray imaging system and image processing method
The X-ray imaging system of this invention includes: a detecting member which detects a salt and pepper noise region in the reconstructed image based on at least one characteristic value of the moire stripe image not including the object and/or the moire stripe image including the object; a masked-image generating member which generates a masked image for identifying the detected salt and pepper noise region; and an image processing member which masks or trims at least one of the reconstructed image and the moire stripe images with the generated masked image. |
| US09672946B2 |
Water supply tank using compressor steam to provide cooling water to a nuclear reactor, and structure inside the tank reducing internal cooling water circulation resulting from injection of the steam into the tank
A passive high-pressure safety injection system includes a compressor which generates high-temperature and high-pressure steam, a cooling water supply tank which supplies cooling water using the compressed steam, a nuclear reactor which receives the cooling water so that the nuclear reactor is maintained in a cooled state, and an internal circulation prevention structure which is provided in the cooling water supply tank and prevents the cooling water from circulating in the cooling water supply tank. |
| US09672945B2 |
Reactor shutdown trip algorithm
A controller for producing a nuclear reactor shutdown system trip signal in response to at least one detector signal. The controller includes a signal conditioning module receiving the at least one detector signal and outputting a measured flux signal. A rate module generates a rate signal from the measured flux signal. A comparator circuit compares the rate signal to a trip setpoint and generates a first trip signal. |
| US09672944B2 |
Method of determining nuclear fusion irradiation coordinates, device for determining nuclear fusion irradiation coordinates, and nuclear fusion device
An object of the present invention is to efficiently improve uniformity of energy lines to be irradiated. A method of determining nuclear fusion irradiation coordinates according to the present invention is a method of calculating irradiation coordinates when energy lines are irradiated onto a nuclear fusion target, and comprises an initial arrangement step S202 of virtually arranging electric charges Qi at initial coordinates of the number of irradiation coordinates NB on a spherical surface S0 set by using random numbers, a coordinate analysis step S203 of analyzing coordinates ri of the electric charges Qi in time series based on coulomb forces acting among the electric charges Qi by constraining the coordinates ri onto the spherical surface S0, potential evaluation steps S205 and S206 of determining a timing at which potential energies of the electric charges Qi were stabilized based on the coordinates ri, and an irradiation coordinate deriving step S207 of deriving coordinates ri at the timing at which potential energies were stabilized as irradiation coordinates of energy lines in a case where a nuclear fusion target is arranged at the center of the spherical surface S0. |
| US09672941B1 |
Memory element status detection
A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element. |
| US09672940B1 |
Non-volatile memory with fast read process
In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters. |
| US09672939B2 |
Memory devices, testing systems and methods
Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested. |
| US09672937B2 |
Semiconductor device
A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair. |
| US09672936B2 |
Driving circuits and the shift register circuits
A driving circuit and a shift register circuit are disclosed. The driving circuit includes a plurality of cascaded multi-stages shift register circuits. Each of the shift register circuit includes a transmission door latch circuit and a signal transmission circuit. The transmission door latch circuit includes a transmission door, first clock signals triggering the transmission door such that transmission signals of two stages ahead are transmitted to the signal transmission circuit via the transmission door to generate transmission signals for the current stage. Second clock signals control the transmission signals of the current stage to pass through the signal transmission circuit to generate gate driving signals for the current stage. In this way, the driving circuit is feasible for CMOS manufacturing process, and owns the advantages such as low power consumption and high noise tolerance. |
| US09672935B2 |
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node. |
| US09672933B2 |
Threshold based multi-level cell programming for a non-volatile memory device
A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage. |
| US09672932B2 |
Nonvolatile memory device and memory system including the same
A nonvolatile memory device includes a memory cell array and a voltage generator. The memory cell array includes a plurality of planes, and each plane receives one of a first ground selection voltage and a second ground selection voltage. The voltage generator is configured to provide selectively one of the first ground selection voltage and the second ground selection voltage independently to each of the planes based on a result of an erase verification operation on each of the plurality of planes. |
| US09672928B2 |
Method and apparatus for estimating read levels of nonvolatile memory and for programming pilot signals used for such estimation
A method, executed by a memory controller, for estimating read levels of a nonvolatile memory includes reading voltages stored by memory cells of a page space within the nonvolatile memory to which pilot signals of a predetermined symbol are programmed. The number of memory cells are identified whose voltages, read from the page space, are less-than/greater-than a read-voltage applied in reading the voltages stored by the memory cells. A voltage to be applied for reading data stored in the page space is estimated based upon the identified number of memory cells. |
| US09672927B2 |
Semiconductor storage device
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. |
| US09672924B2 |
Nonvolatile memory device and operating method thereof
An operating method of a nonvolatile memory device includes receiving a read command from a memory controller; determining a read mode based on the received read command, controlling a precharge time and an offset of a precharge control signal according to the determination result, and precharging a sensing bit line among bit lines to a precharge voltage based on the controlled precharge control signal. The sensing bit line is a bit line being precharged according to the determined read mode among the bit lines. |
| US09672921B2 |
Device and method for storing data in a plurality of multi-level cell memory chips
A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips. |
| US09672920B2 |
Electronic device, non-volatile memorty device, and programming method
This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage. |
| US09672912B2 |
Semiconductor integrated circuit device with reduced power consumption
A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor. |
| US09672905B1 |
Optimize data protection layouts based on distributed flash wear leveling
A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided. |
| US09672904B1 |
6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write
A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in terms of area, dynamic power, leakage power and performance over the prior art in the industry. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per mux. |
| US09672902B1 |
Bit-cell voltage control system
In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage. |
| US09672898B1 |
Read column select negative boost driver circuit, system, and method
Embodiments include a read column select negative boost driver of a memory device. The negative boost driver may include a negative boost element coupled to a P-type metal-oxide-semiconductor (PMOS) pass gate, and configured to negatively boost a read column select signal below a negative power supply level VSS dependent on a boost control signal. The negative boost driver may further include an N-type metal-oxide-semiconductor (NMOS) boost control transistor coupled to the negative boost element and to a read column select inverter, and configured to tri-state the read column select inverter dependent on the boost control signal. |
| US09672897B1 |
Method and apparatus for memory speed characterization
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator. |
| US09672891B2 |
Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module
A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB. |
| US09672889B2 |
Semiconductor memory device and refresh control method thereof
A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command. |
| US09672883B1 |
Semiconductor circuit, serialization/deserialization circuit, and data processing system relating to clock signals
A semiconductor circuit may include a control circuit configured to generate a second start signal and a plurality of serialization control signals by synchronizing a first start signal with first and second clock signals. |
| US09672880B2 |
Radiation upset detection
A radiation upset detector is provided. The radiation upset detector includes at least one radiation sensitive memory initialized with at least one respective known-signature word; and at least one radiation hardened logic circuitry communicatively coupled to the at radiation sensitive memory to check the known-signature word at at least a kHz rate to detects errors. Responsive to detecting an error in the known-signature word in the radiation sensitive memory, the radiation hardened logic circuitry sends an action command. At least one of: a memory size of the memory; a number of circuits in the logic circuitry; a clock rate for the checking the known-signature word; and at least one corruption threshold is selected based on system reliability requirements of the protected system including at least one of: an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection. |
| US09672877B2 |
Interfaces and die packages, and apparatuses including the same
A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal. The interface device further includes an input multiplexer configured to multiplex the first data and the second data to provide an input data. |
| US09672873B2 |
Semiconductor device
A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors. |
| US09672868B2 |
Systems and methods for seamless media creation
Systems and methods for nonlinear media playback using a linear media player are described. In one implementation, a video tree representing a branching video presentation is provided, and a dynamic playlist is provided to a linear video player. A controller component interacts with the linear video player through a standard interface of the linear video player. During playback of a video content segment in the dynamic playlist by the linear video player, an indication of a user interaction with the playing video content segment is received by the controller component and from the linear video player via the standard interface, and the dynamic playlist is modified based on video content segments in a branch of the video tree. In another implementation, an uncompressed media file is selected and combined with a preceding and/or following media file. The combined files are compressed and a portion of the compressed file corresponding to the original media file is extracted. |
| US09672867B2 |
Automated creation and maintenance of video-based documentation
An approach for creation and maintenance of video-based training documentation. Universal identifiers are created and associated with user interface elements for delimiting videos and audios. Test scripts are created based on matching the universal identifiers to task instructions. Videos are created based on test scripts where the universal identifiers are marked on the videos. Audios are created based on the universal identifiers and the task instructions, where the universal identifiers are marked on the audios. The audios and the videos are combined based on synchronizing the universal identifiers. |
| US09672865B2 |
Systems and methods for temporal visualization of media asset content
Methods and systems described herein provide for visualizing content across different time segments of a media asset. Information about content within a particular time segment of a media asset is retrieved. This content information is generated by processing user-generated messages corresponding to the particular time segment. Content descriptors are generated based on the received content information corresponding to the particular time segment. A timeline is generated, independently of presenting a media asset, wherein the timeline visually associates content descriptors with their corresponding time segments of the media asset. When these content descriptors are selected by a user, the user-generated messages corresponding to the content descriptor at the corresponding time segment are displayed to the user. |
| US09672862B2 |
Method of writing servo information on a storage medium and arrangement for writing servo information on a storage medium
According to embodiments of the present invention, a method of writing servo information on a storage medium is provided. The method includes applying heat to a servo portion of a storage medium, and applying a magnetic field to the servo portion that is heated to write servo information on the servo portion. According to further embodiments of the present invention, an arrangement for writing servo information on a storage medium and a method of forming a storage medium are also provided. |
| US09672861B2 |
Optical recording medium
There is provided an optical recording medium including: three reproduction layers, wherein reflectance R1, R2, and R3 of the three reproduction layers on a side of a surface irradiated with reproduction light is equal to or greater than 5%, and wherein any absolute value of a difference delta R between two selected from the reflectance R1, R2, and R3 is equal to or less than 7%. |
| US09672858B2 |
Magnetic recording medium manufacturing method
According to one embodiment, there is provided a magnetic recording medium manufacturing method including forming a bonding layer on a substrate, forming a holding layer containing silicon on the bonding layer, forming a single-particle layer on the holding layer using particles containing metal fusible on the bonding layer, etching SiO2 in the holding layer using an etching solution containing HF and H2O2, filling the holding layer with the particles until the particles are brought into contact with the bonding layer, bonding the particles and the bonding layer together by heating, and forming a magnetic recording layer on the single-particle layer. |
| US09672852B2 |
Tape head assembly for linear tape open
A tape head assembly includes a set of data readers configured to simultaneously read data from a set of adjacent data tracks of a tape storage medium, each data track having a width; wherein the width of each data reader of the set along a lateral extension of the tape head assembly is equal to or less than the width of a data track wherein the lateral extension of the tape head assembly is orthogonal to a longitudinal extension of the tape storage medium when arranged in a tape drive containing the tape head assembly spanning at least the set of data tracks during reading; and a servo reader arrangement containing at least one servo reader arranged laterally offset from one of the data readers by less than the width of a data track. |
| US09672850B2 |
Systems and methods for synchronization hand shaking in a storage device
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window. |
| US09672848B2 |
Multipiece near field transducers (NFTS)
Devices having air bearing surfaces (ABS), the devices including a near field transducer (NFT) that includes a disc configured to convert photons incident thereon into plasmons; and a peg configured to couple plasmons coupled from the disc into an adjacent magnetic storage medium, wherein at least one of a portion of the peg, a portion of the disc, or a portion of both the peg and the disc include a multilayer structure including at least two layers including at least one layer of a first material and at least one layer of a second material, wherein the first material and the second material are not the same and wherein the first and the second materials independently include aluminum (Al), antimony (Sb), bismuth (Bi), boron (B), barium (Ba), calcium (Ca), cerium (Ce), chromium (Cr), cobalt (Co), copper (Cu), erbium (Er), gadolinium (Gd), gallium (Ga), germanium (Ge), gold (Au), hafnium (Hf), indium (In), iridium (Ir), iron (Fe), lanthanum (La), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), niobium (Nb), osmium (Os), palladium (Pd), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), scandium (Sc), silicon (Si), silver (Ag), strontium (Sr), tantalum (Ta), thorium (Th), tin (Sn), titanium (Ti), vanadium (V), tungsten (W), ytterbium (Yb), yttrium (Y), zirconium (Zr), or combinations thereof. |
| US09672847B2 |
Micrometer scale components
Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile. |
| US09672846B1 |
STO bias control for MAMR head reliability
The MAMR head comprises a main pole, a spin torque oscillator (STO) positioned over the main pole, and write coils coupled to the main pole. The STO generates a high frequency magnetic field on a magnetic medium. The controller is configured to supply the STO with first bias current at a first bias current level, and further supply the STO with second bias current at a second bias current level. The controller is further configured to time the second bias current to coincide with an electrical current overshoot in the write coils. |
| US09672844B2 |
Portable turntable device, system, and method
A turntable device, comprising: a spindle and two arms. The two arms may comprise: a housing; one or more buttons; a spindle engagement portion; a stylus cartridge; a power supply; one or more wireless communication devices; a linear actuator; a motor; and a vertical solenoid. The spindle may receive a phonographic record, and the spindle engagement portion may engage with the spindle, such that the arms are entirely supported via said spindle and only the spindle. |
| US09672843B2 |
Apparatus and method for improving an audio signal in the spectral domain
Method of improving audio signal in the spectral domain starts by receiving audio signal that includes signals from sources including speech source and music source. Audio signal is tuned for output by sound output device. Portions of audio signal are analyzed in a spectral domain to determine whether adjustments are required. Analyzing portions of audio signal includes determining whether anomaly is present in frequency band of audio signal in spectral domain by using at least one metric. Metrics include band energy ratios, spectral centroid, spectral tilt, spectral flux, spectral variance, absolute thresholds, and relative thresholds. Audio signal is adjusted to improve audio signal in spectral domain when audio signal is determined to require adjustments. Adjusting audio signal includes adjusting values of the metric in frequency band that is determined to include anomaly to correspond to clustering of metric values for audio signal in spectral domain. Other embodiments are also described. |
| US09672839B1 |
Reconstructing audio signals with multiple decorrelation techniques and differentially coded parameters
A method performed in an audio decoder for decoding M encoded audio channels representing N audio channels is disclosed. The method includes receiving a bitstream containing the M encoded audio channels and a set of spatial parameters, decoding the M encoded audio channels, and extracting the set of spatial parameters from the bitstream. The method also includes analyzing the M audio channels to detect a location of a transient, decorrelating the M audio channels, and deriving N audio channels from the M audio channels and the set of spatial parameters. A first decorrelation technique is applied to a first subset of each audio channel and a second decorrelation technique is applied to a second subset of each audio channel. The first decorrelation technique represents a first mode of operation of a decorrelator, and the second decorrelation technique represents a second mode of operation of the decorrelator. |
| US09672835B2 |
Method and apparatus for classifying audio signals into fast signals and slow signals
Low bit rate audio coding such as BWE algorithm often encounters conflict goal of achieving high time resolution and high frequency resolution at the same time. In order to achieve best possible quality, input signal can be first classified into fast signal and slow signal. This invention focuses on classifying signal into fast signal and slow signal, based on at least one of the following parameters or a combination of the following parameters: spectral sharpness, temporal sharpness, pitch correlation (pitch gain), and/or spectral envelope variation. This classification information can help to choose different BWE algorithms, different coding algorithms, and different post-processing algorithms respectively for fast signal and slow signal. |
| US09672834B2 |
Dynamic range compression with low distortion for use in hearing aids and audio systems
Dynamic range compression in the hearing aids is provided for restoring normal loudness of low level sounds without making the high level sounds uncomfortably loud. An apparatus along with a method using sliding-band compression is disclosed for significantly reducing the temporal and spectral distortions generally associated with the currently used single and multiband compression techniques. It; uses a frequency-dependent gain function calculated on the basis of auditory critical bandwidth based short-time power spectrum and the specified hearing thresholds, compression ratios, and attack and release times. It is realized using FFT-based analysis-synthesis and can be integrated with other FFT-based signal processing in hearing aids and audio systems. |
| US09672827B1 |
Real-time conversation model generation
A conversation model is generated based on a conversation between a plurality of participants. Conversation text associated with the conversation is retrieved. A plurality of conversation model components are identified within the conversation text. A correlation score is determined for each pair of conversation model components representing a measure of relatedness between the pair of conversation model components. Extrapolated conversation model components are identified based on the plurality of conversation model components and the determined correlation scores. The conversation model components, the additional conversation model components, and the correlation scores are then stored as a conversation model. |
| US09672825B2 |
Speech analytics system and methodology with accurate statistics
The present invention relates to implementing new ways of automatically and robustly evaluating agent performance, customer satisfaction, campaign and competitor analysis in a call-center and it is comprising; analysis consumer server, call pre-processing module, speech-to-text module, emotion recognition module, gender identification module and fraud detection module. |
| US09672823B2 |
Methods and vehicles for processing voice input and use of tone/mood in voice input to select vehicle response
Methods, systems and cloud processing are provided for coordinating and processing user input provided to vehicles during use. One example is for processing voice inputs at a vehicle to identify a mood of a user and then modifying or customizing the vehicle response based on the detected mood, physical characteristic and/or physiological characteristic of the user. One example includes a vehicle having an on-board computer for processing voice input. The vehicle having a microphone interfaced with the on-board computer and memory for storing a sample of audio data received from the microphone. The audio data is a voice input directed to the vehicle. A processor of the on-board computer is configured to process the sample of audio data to identify markers in frequency and/or magnitude. The markers are used to define an audio signature for the voice input, and the audio signature is used to identify a voice profile. The voice profile is used to identify a vehicle response for the voice input, and the voice profile is associated with tone of voice used in the voice input. The vehicle response acts to direct a vehicle system function to take an action based on the voice input and the vehicle response is adjusted based on the tone of voice. The tones of voice are associated to inferred moods of the user which include one or more of a normal mood, a frustrated mood, an agitated mood, an upset mood, a hurried mood, an urgency mood, a rushed mood, a stressed mood, a calm mood, a passive mood, a sleepy mood, a happy mood, or an excited mood, or combinations of two or more thereof. The action to be taken is based on the voice input and is one of a command to input a setting of the vehicle, a command requesting information, a request to access data, a request to communicate, or a combination thereof. |
| US09672822B2 |
Interaction with a portion of a content item through a virtual assistant
Techniques for interacting with a portion of a content item through a virtual assistant are described herein. The techniques may include identifying a portion of a content item that is relevant to user input and causing an action to be performed related to the portion of the content item. The action may include, for example, displaying the portion of the content item on a smart device in a displayable format that is adapted to a display characteristic of the smart device, performing a task for a user that satisfies the user input, and so on. |
| US09672815B2 |
Method and system for real-time keyword spotting for speech analytics
A system and method are presented for real-time speech analytics in the speech analytics field. Real time audio is fed along with a keyword model, into a recognition engine. The recognition engine computes the probability of the audio stream data matching keywords in the keyword model. The probability is compared to a threshold where the system determines if the probability is indicative of whether or not the keyword has been spotted. Empirical metrics are computed and any false alarms are identified and rejected. The keyword may be reported as found when it is deemed not to be a false alarm and passes the threshold for detection. |
| US09672810B2 |
Optimizations to decoding of WFST models for automatic speech recognition
A method in a computing device for decoding a weighted finite state transducer (WFST) for automatic speech recognition is described. The method includes sorting a set of one or more WFST arcs based on their arc weight in ascending order. The method further includes iterating through each arc in the sorted set of arcs according to the ascending order until the score of the generated token corresponding to an arc exceeds a score threshold. The method further includes discarding any remaining arcs in the set of arcs that have yet to be considered. |
| US09672809B2 |
Speech processing device and method
A speech processing device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: obtaining input speech, detecting a vowel segment contained in the input speech, estimating an accent segment contained in the input speech, calculating a first vowel segment length containing the accent segment and a second vowel segment length excluding the accent segment, and controlling at least one of the first vowel segment length and the second vowel segment length. |
| US09672806B2 |
Apparatus and method for determining a measure for a perceived level of reverberation, audio processor and method for processing a signal
An apparatus for determining a measure for a perceived level of reverberation in a mix signal consisting of a direct signal component and a reverberation signal component, has a loudness model processor having a perceptual filter stage for filtering the dry signal component the reverberation signal component or the mix signal, wherein the perceptual filter stage is configured for modeling an auditory perception mechanism of an entity to obtain a filtered direct signal, a filtered reverberation signal or a filtered mix signal. The apparatus furthermore has a loudness estimator for estimating a first loudness measure using the filtered direct signal and for estimating a second loudness measure using the filtered reverberation signal or the filtered mix signal, where the filtered mix signal is derived from a superposition of the direct signal component and the reverberation signal component. The apparatus furthermore has a combiner for combining the first and the second loudness measures to obtain a measure for the perceived level of reverberation. |
| US09672803B2 |
Adaptive active noise cancellation
A number of variations may include a method including obtaining data indicating a driver intent from a vehicle and using an ANC system to cancel noise in an appropriately reactive manner. |
| US09672799B1 |
Music practice feedback system, method, and recording medium
A music practice feedback method, system, and non-transitory computer readable medium including a displaying device configured to display sheet music, a collecting device configured to collect information related to a playing of the sheet music by a plurality of players, and a display changing device configured to change a display of the sheet music based on said collected information. |
| US09672797B2 |
Support assembly and keyboard apparatus
A support assembly includes a support rotatably disposed with respect to a frame; a jack support portion connected to the support; a jack having a recessed portion in a lower portion of the jack, the jack having the jack support portion inside the recessed portion and being rotatably disposed to the support; and an acting portion fixed to the jack and receiving a downward action. The recessed portion has an open end with a width larger than a width of the jack support portion. The recessed portion may have an open end with a width larger than a width of the jack support portion. |
| US09672796B2 |
Electronic device including flexible display
An electronic device includes a flexible display, a sensing unit configured to obtain bending information including at least one of a bending degree, the number of times of bending, a bending maintaining duration, and a bending speed of the display, and a controller configured to additionally display a second image on the display when the display is bent in a state in which a first image is displayed, and complementarily change transparency of the first image and that of the second image to reflect the bending information obtained by the sensing unit. |
| US09672795B2 |
Wet ink texture engine for reduced lag digital inking
A wet ink texture engine and associated method. The wet ink texture engine may run in the context of any application on any device, service, or general endpoint capable of receiving ink input. For example, the wet ink texture engine may be used in the context of a note application that receives input in the form of writing or drawing. The wet ink texture engine reduces, minimizes, or eliminates lag between receiving the input and displaying the input to improve inking experience for the user. |
| US09672793B2 |
Map display device and map display method
An object of the present invention is to provide a map display device and a map display method for displaying a plurality of map drawing pictures so as to improve convenience for a user. The map display device according to the present invention includes an input/display unit that receives input of user operation and displaying a first drawing object related to map information in a first drawing picture and a second drawing object related to map information in a second drawing picture; and a controller for controlling an overlapping state between the first drawing picture and a partial area of the second drawing picture in accordance with input of user operation received by the input/display unit and outputting, to the input/display unit, a picture in which the second drawing object masks the first drawing object in such an overlapped portion. |
| US09672792B2 |
Display device and driving method thereof
The present invention provides a display device with reduced power consumption and that reduces changes in luminance, and perceptibility of flicker, and a driving method thereof. A display device according to an exemplary embodiment comprises: a display panel configured to display a still image and a motion picture; a signal controller configured to control signals for driving the display panel; and a graphics processing unit configured to transmit input image data to the signal controller, wherein the signal controller comprises a frame memory configured to store the input image data, and the display panel is driven at a first frequency when the motion picture is displayed and the display panel is driven at a second frequency that is lower than the first frequency when the still image is displayed. |
| US09672791B2 |
Actuation of device for viewing of first content frames presented on a display between second content frames
In one aspect, a device includes a processor, at least one lens accessible to the processor, and a memory accessible to the processor. The memory bears instructions executable by the processor to receive synchronization information from another device, and based on the synchronization information, actuate the at least one lens to permit visible light to pass therethrough at times at which first frames of first content are presented and not at times that second frames different from the first frames for second content different from the first content are presented. |
| US09672790B2 |
Earphone system for mobile device and method for operating the same
An apparatus and method are provided. The apparatus includes a display and a controller operatively coupled with the display. The controller is configured to determine whether the apparatus is coupled with an output device external to the apparatus, and to adjust a brightness of the display based at least in part on a determination that the apparatus is coupled with the output device. |
| US09672789B2 |
Color conversion device, image forming device, and color conversion method
A color conversion device includes color conversion sections, an obtaining section and a reconversion section. The color conversion sections perform color conversion in parallel to convert colors of pixels contained in image data of a predetermined number of rows. The predetermined number is two or more. For the color conversion, at least one color conversion section uses certain color conversion information, and the other color conversion section uses other color conversion information having an information amount less than that of the certain color conversion information. The obtaining section obtains attribute information indicating an attribute of each of the pixels. When the attribute information is predetermined attribute information, the reconversion section converts a pixel color-converted with the other color conversion information using a pixel color-converted with the certain color conversion information in a predetermined pixel area contained in the image data. |
| US09672788B2 |
Reducing visual crowding, increasing attention and improving visual span
Methods, systems, and apparatuses, including computer programs encoded on computer readable media, for modifying displayed text in a gaze-contingent way to reduce crowding, thus increasing the observer's visual span, and thus increasing the observer's reading rate. The trick is to introduce only a few differences between characters (not enough to produce a pattern) of text so as to reduce crowding. For example, differences between characters near the left and right extremes of the observer's estimated visual span can be altered to reduce crowding. |
| US09672785B2 |
Dual data driving mode liquid crystal display
Disclosed is a display device having a display panel in which a plurality of gate lines and a plurality of data lines cross each other to define a plurality of pixels that may include a timing control unit that outputs a first data control signal and an image data; a first data driving unit on a first side of the display panel that generates a first data signal from the image data according to the first data control signal, outputs the first data signal to one of the plurality of data lines from the first side, and generates a second data control signal from the first data control signal; and a second data driving unit on a second side of the display panel that generates a second data signal from the first data signal according to the second data control signal, the second data signal substantially synchronized with the first data signal, and outputs the second data signal to the one of the plurality of data lines from the second side. |
| US09672784B2 |
CMOS gate driving circuit
The present invention provides a CMOS gate driving circuit, comprising a plurality of shift register units which are cascade connected, and the shift register unit of the nth stage comprises: a forward-backward scan module, a latch module (200) electrically coupled to the forward-backward scan module and an output module (400) electrically coupled to the latch module; the forward-backward scan module comprises: a first module (100) and a second module (300), and the first module (100) is a transmission module in forward scan and a pull-down module in backward scan; the second module (300) is a pull-down module in forward scan and a transmission module in backward scan; both the first module (100) and the second module (300) comprise a NAND gate, which can achieve forward-backward scan for ensuring the stability of the GOA function and the smooth output of the scan voltage signal to raise the stage transfer efficiency and to effectively reduce the sequence delay of the stage transfer; meanwhile, the multiple functions of the circuit module can be achieved, and the frame width of the screen can be decreased and the power consumption can be lowered. |
| US09672778B2 |
Method of driving display panel and display apparatus for performing the same
A method of driving a display panel includes steps of generating a plurality of load signals, of which at least one load signal has a different timing from the rest of the load signals, generating data voltages synchronized to low periods of the load signals and outputting the data voltages to data lines. Accordingly, the data voltages synchronized to each of the load signals can be outputted to each of the data lines. A color coordinate problem occurring when applying a RGBW type may be solved by setting a charging time of a white sub-pixel different from the rest of the sub-pixels. Thus, display quality of a display apparatus including the display panel may be improved. |
| US09672777B2 |
Liquid crystal display panel and driving method thereof
A liquid crystal display (LCD) panel and a driving method thereof are provided. The LCD panel includes display pixels each including RGBW display sub-pixels. The method includes: receiving an image data for representing a to-be-displayed image including image pixels; calculating RGBW image sub-pixel data corresponding to the image pixels according to the image data; using a first predetermined number of image pixels as a repeat unit and generating RGBW display sub-pixel data corresponding to a second predetermined number of display pixels by using each repeat unit in a pixel sharing manner, the first predetermined number being greater than the second predetermined number; and using the RGBW display sub-pixel data to drive RGBW display sub-pixels of corresponding display pixels. Accordingly, the edge blur phenomenon can be effectively improved by the image pixel sharing. |
| US09672773B2 |
Method for adjusting gamma voltages of OLED display device
A method for adjusting a gamma voltage of an OLED display device, including; acquiring a test picture pre-stored in the OLED display device, and extracting a first piece of data information on the test picture; comparing the first piece of data information with a pre-stored second piece of data information on the test picture before the OLED display device is aged, analyzing a comparison result, and obtaining the aging coefficient of the OLED display device; acquiring a set of gamma voltage values corresponding to the aging coefficient, outputting the set of gamma voltage values to a gamma integrated circuit of the OLED display device, and completing the adjustment of the gamma voltage. |
| US09672767B2 |
Organic light emitting display device
An organic light emitting display device includes: a display panel including a red sub-pixel, a green sub-pixel, a first blue sub-pixel, and a second blue sub-pixel connected to scan lines and data lines; a scan driver configured to drive the plurality of scan lines; a data driver configured to output a data output signal in response to a data signal; a de-multiplexer circuit configured to sequentially provide the data output signal to a first data line, a second data line, a third data line, and a fourth data line, respectively to the red sub-pixel, the green sub-pixel, the first blue sub-pixel, and the second blue sub-pixel, in response to selection signals; and a timing controller configured to provide the data signal to the data driver, control the scan driver, and output the selection signals in response to an image signal and a control signal. |
| US09672764B2 |
Liquid crystal display device
A liquid crystal display device where the luminance control unit determines a coefficient KU, where KU<1, as the coefficient and repeatedly multiplies each of the luminance set values by the coefficient KU until the first integrated value is within the range of the first threshold value in a case where the first integrated value is larger than the range of the first threshold value, and the luminance control unit determines a coefficient KL, where KL>1, as the coefficient and repeatedly multiplies each of the luminance set values by the coefficient KL until the first integrated value is within the range of the first threshold value in a case where the first integrated value is smaller than the range of the first threshold value. |
| US09672762B2 |
Current slope control method and appartus for power driver circuit application
A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor. |
| US09672757B2 |
Multi-mode software and method for a welding training system
A welding training system includes a welding training software having three or more modes. The three or more modes include a live-arc mode, a simulation mode, a virtual reality mode, an augmented reality mode, or some combination thereof. The live-arc mode is configured to enable training using a live welding arc, the simulation mode is configured to enable training using a welding simulation, the virtual reality mode is configured to enable training using a virtual reality simulation, and the augmented reality mode is configured to enable training using an augmented reality simulation. |
| US09672756B2 |
System and method for toy visual programming
A method for programmatic robot control including, at a user device: displaying a set of icons and receiving a program for a robot, wherein receiving a program for a robot includes receiving a selection of a state icon associated with a state; associating a transition with the state; and creating a relationship between the transition and an event. The method functions to provide a user with an environment for creating a program to control the robot, and can additionally function to control the robot. |
| US09672755B2 |
System and method for rewarding a child for behaving well while dining
Systems and methods for rewarding a child for behaving well while dining. One embodiment includes the steps of: generating indications proportional to the weight of food on a plate, calculating the rate of removing the food from the plate (Rr), and comparing Rr with a predetermined max eating rate (Rm). When Rr |
| US09672754B2 |
Methods and systems for interactive goal setting and recommender using events having combined activity and location information
A method for generating recommendations for achieving goals is described. The method includes receiving a goal for a user account. The goal is associated with an activity that is trackable via a monitoring device. The method further includes receiving tracking data associated with the monitoring device. At least part of the tracking data is associated to the activity. The method includes receiving geo-location data associated with the monitoring device. The geo-location data is correlated to the tracking data. The method includes analyzing the received tracking data and geo-location data to characterize a current performance metric for the activity and generating a recommendation for the user account. The recommendation identifies the current performance metric and a suggested action and location for increasing the current performance metric to achieve the goal. |
| US09672753B2 |
System and method for dynamic online test content generation
An online test platform facilitates automatic scrolling of test materials in a web browser while maintaining a text prompt associated with the test materials. The platform also facilitates development, delivery, and management of educational tests with interactive participation by students, teachers, proctors, and administrators even when some or all of them are remotely located. The platform may include administrator interfaces, test proctor interfaces, and test taker (e.g. student) interfaces to allow each participant to view, navigate, and interact with aspects of the online test platform that are intended to meet their needs. |
| US09672751B1 |
Three dimensional aid for teaching and illustrating exemplary thinking and problem solving
The invention provides a three-dimensional apparatus for problem solving, learning and presentation for modeling, teaching and illustrating exemplary problem solving or thinking. Some embodiments provide a puzzle-like form. Another preferred embodiment of the present invention provides for the building of a problem or topic or situation specific or custom learning or problem solving or investigatory or presentation aid. Embodiments of the invention may also incorporate or use electronic, digital, electro-mechanical, mechanical, electric or other devices, processors, controllers, or mechanisms, or input or output to or from such or similar elements, and wired or wireless or other networks or interfaces. |
| US09672747B2 |
Common operating environment for aircraft operations
A common operating environment (COE) display system for vehicle operations, such as for air transport provides coordination of logistics information with dispatch or a controller. An operational plan, such as a flight plan or other operational plan describing vehicle deployment is stored, and a map visualization system displays a map region. An in-vehicle display depicts the operational plan, providing displays of current and projected operational conditions of the vehicle within different time phases of the operational plan. Transfer of updates of the operational plan is performed without replacing substantial portions of the stored data for the operational plan, allowing synchronization of the operational plan with a remotely located facility. The system permits a controller or dispatcher to screen share the in-vehicle display based on information previously stored, as updated by the updates, and permits review of the modified operational plan. |
| US09672746B2 |
Terrain awareness system with obstruction alerts
Current TAWS systems generally do not provide alerts based on structures or wire obstacles. Such structures and wire obstacles include transmission and electrical wires, and power lines, bridges, and buildings. The current system allows just such alerting. Such alerts are particularly useful for helicopter aircraft, which commonly fly at heights where such structures and obstacles are present near the normal flying altitude of the aircraft. Certain implementations of the system and method include a method of creating an obstacle for use in a terrain awareness warning system, including: receiving data about a first terminus of an obstacle; receiving data about a second terminus of the obstacle; constructing a virtual volume about the first and second termini and a volume therebetween; and storing the virtual volume, whereby a database may be constructed of virtual volumes for use in addition to terrain information to provide alerting on obstacles for an aircraft. |
| US09672744B2 |
Boundary detection system
Systems and methods provide for tracking objects around a vehicle, analyzing the potential threat of the tracked objects, and implementing a threat response based on the analysis in order to keep occupants of the vehicle safe. Embodiments include a boundary detection system comprising a memory configured to store threat identification information, and a sensor unit configured to sense the object outside the vehicle and obtain sensor information based on the sensed object. The boundary detection system further includes a processor in communication with the memory and sensor unit, the controller configured to receive the sensor information, and control a threat response based on the sensor information and the threat identification information. |
| US09672743B2 |
Vehicle traffic control system
A traffic control system for allowing vehicles to travel unattended while maintaining their inter-vehicular distances without interfering with each other includes an onboard control apparatus mounted on the vehicles; and a traffic control apparatus which divides tracks for multiple vehicles into a plurality of sections and performs a blocking control to assign non-overlapping travelable sections to the multiple vehicles as a permitted travel section. The onboard control apparatus sets a travel permission request starting distance that is longer than a stoppable distance on the basis of the current speed of the vehicle and repeatedly transmits a travel permission request and current position information to the traffic control apparatus until the next travel permission is obtained when the remaining length of the permitted travel section has become shorter than the travel permission request starting distance in the advancing direction of the vehicle. |
| US09672740B2 |
Privacy protected public transit data mining method and system for effective passenger detouring
A method and system that provides detouring services to passengers and transportation operators. Transportation operators send data indicating prior uses of the operator to the passengers' mobile device and the system on the mobile device compiles the data to form travel patterns of the passenger. The travel patterns are assigned a probability indicating the frequency the travel pattern is used by the passenger. When a disruption of a service of an operator occurs, a detouring service provides detour suggestions to the passengers and travel demand changes to the operators. In another approach, an in-station display displays suggested detour routes based on the top destinations of stranded passengers and the passenger's mobile phones are not used to display or perform detouring. |
| US09672739B2 |
Map data update device
For a new road set in a region where an existing road is not present in map data, a road associated information setting unit 13 determines and sets road associated information to be applied to a road link of a new road on the basis of movement history data relating to a plurality of moving bodies stored in a movement history storage unit 14. Accordingly, the road associated information on the new road is automatically set on the basis of the movement history data relating to the plurality of moving bodies, and hence a worker is no longer required to execute on-site investigation or manually generate road associated information. |
| US09672738B1 |
Designing preferred vehicle routes based on driving scores from other vehicles
Systems and methods are provided for designing a preferred route for a vehicle. The route designing system receives a request from the vehicle for a preferred route from a first geographical point to a second geographical point. The route designing system analyzes the request and obtains driving scores associated with drivers of other vehicles. The route designing unit may identify a set of preferred and non-preferred vehicles based on the driving scores. The route designing system then determines a preferred route based, at least in part, on the driving scores associated with drivers of the other vehicles. The preferred route is designed to minimize the likelihood of proximity to non-preferred vehicles and maximize the likelihood of proximity to preferred vehicles. |
| US09672737B2 |
Dynamic multi-lane capacity optimization in a mixed vehicle environment
In the example embodiments as described herein there is at least a method and apparatus to perform operations including monitoring probe data of car and truck traffic on at least one road segment including more than one lane; based on the monitoring, determining that an occurrence of a traffic jam ahead of the car and truck traffic on the at least one road segment is probable or occurring; and in response to the determining, selectively notifying at least one of a car and truck of the traffic of required or prohibited changes to at least one of their position and speed on the at least one road segment to prevent an occurrence of a traffic jam on the at least one road segment. |
| US09672733B2 |
Heavy vehicle traffic flow optimization
There is provided a method for heavy vehicle traffic flow optimization. The method includes determining location information and destination information of qualifying heavy vehicles. The method further includes modifying one or more traffic signal sequences to optimize a traffic flow of the qualifying heavy vehicles responsive to the location information and the destination information. Each of the qualifying heavy vehicles has a respective associated weight greater than a predetermined weight threshold. |
| US09672732B1 |
Integrated accessible pedestrian system
An integrated pedestrian access system comprising of wireless push buttons adapted to transmit and receive wireless signals and receivers connected to pedestrian crosswalk signal systems, wherein said one or more receivers are configured to communicate with the wireless push buttons through wireless signals, communicate among the receivers, determine whether source device from which a request for registering a pedestrian signal is received through the said communication is the wireless push button or the receivers, determine status of pedestrian signal based on signals received from the pedestrian signal system, register request for pedestrian crosswalk signal if walk signal of the pedestrian signal is not on in the desired direction as per the status of pedestrian signal and provide acknowledgement corresponding to the status of pedestrian signal through the said source device. |
| US09672731B2 |
System, a processing unit, a method and a computer program product for monitoring sensors
The invention relates to a sensor monitoring system comprising at least one sensor (101, 102, 103) and a processing unit (150), wherein the sensor is arranged to transmit during a plurality of successive time periods data items to the processing unit and the processing unit is arranged to receive the data items from the said at least one sensor, the processing unit being further arranged for: determining for at least some time periods from the said plurality of successive time periods a number of corresponding data items; comparing between the at least some time periods the number of the corresponding data items; deducing for the at least some time periods a parameter associated with a variation in the number of data items per said some time periods. The invention further relates to a processing unit, and a method and a computer program for sensor monitoring. |
| US09672730B2 |
Method and apparatus for diagnosis of a communication channel
An apparatus for diagnosis of a communication channel, wherein a communication signal serves for data transmission and is a frequency-modulated signal. The apparatus includes a receiving circuit, which serves for receiving the frequency-modulated signal. The receiving circuit includes a monitoring unit, which serves for determining a signal parameter of the frequency-modulated signal. The receiving circuit also includes a demodulator, which serves to demodulate the frequency-modulated signal. The receiving circuit also includes a signal processing unit, which is connected with the demodulator and with the monitoring unit, wherein the signal processing unit, at least at times, serves for evaluating the signal parameter of the frequency-modulated signal determined by means the monitoring unit and, at least at times, for evaluating the demodulated signal. |
| US09672728B2 |
Smart hazard detector drills
Systems and methods for initiating a drill by receiving an indication to start a drill. Initiating the drill also includes verifying that a remote device used to initiate the drill is within proximity of a device used to propagate the drill. Once proximity is verified, the drill is conducted. |
| US09672722B2 |
Alarm system monitor sensor for multimedia terminal adapter
The methods, systems, and apparatuses described in this disclosure enable the identification of an alarm condition and the termination of a connection between an MTA and one or more telephony devices. An alarm condition can be identified at an MTA through the monitoring of feedback received from an alarm interface, and the MTA can respond to the identification of the alarm condition by terminating a connection to a telephony device for which communications are not routed through a corresponding alarm interface. An interface between the MTA and alarm interface may route communications to and from a telephony network through a first pair of wires and may receive feedback from the alarm interface through a second pair of wires. |
| US09672717B1 |
Contextual communication of events
An electronic system is described that receives data collected by a monitoring system, where the monitoring system includes a notification device that is tunable between different states that discreetly convey contextual alerts based on prior association of the states with contextual alerts. The system analyzes the monitoring system data against one or more event profiles that define events relating to the property or one or more users of the property. Based on the analysis of the monitoring system data, a particular event is identified. Information that specifies contextual alerts to be provided by the monitoring system that each correspond to an event defined by the one or more event profiles is accessed. A particular contextual alert that corresponds to the particular event is identified. The system causes output of the particular contextual alert at the notification device included in the monitoring system by changing a state of the notification device. |
| US09672713B2 |
Methods and apparatus to detect and warn proximate entities of interest
Systems and methods to detect and warn proximate entities of interest are described herein. An example method includes sending an interrogation signal generated by a vehicle within a first area, detecting the interrogation signal from the first area, in response to detection of the interrogation signal from the first area, receiving a first responsive signal from a first transponder in the first area, and determining a directional resolution of the first responsive signal. |
| US09672708B2 |
Battery operated device and tag for a battery operated tool
A device tag including a housing that includes a first connector structure constructed and arranged to engage with a battery operated device and a second connector structure constructed and arranged to slidingly engage with a battery such that the device tag is provided between the battery operated device and the battery. The device tag also includes an electrical connector carried by the housing and constructed and arranged to provide an electrical connection between the battery operated device and the battery. The device tag further includes an electronic device carried by the housing and constructed and arranged to transmit electrical signals. |
| US09672707B2 |
Virtual enhancement of security monitoring
Methods, systems, and apparatus, including computer programs encoded on storage devices, for monitoring, security, and surveillance of a property. In one aspect, a system includes a virtual reality headset, a plurality of cameras, a plurality of sensors that includes a first sensor, a control unit, wherein the control unit includes a network interface, a processor, a storage device that includes instructions to perform operations that comprise receiving data from the first sensor that is indicative of an alarm event, determining a location of the first sensor, identifying a set of one or more cameras from the plurality of cameras that are associated with the first sensor, selecting a particular camera from the identified set of one or more cameras; and transmitting one or more instructions to the particular camera that command the particular camera to stream a live video feed to a user interface of the virtual reality headset. |
| US09672705B2 |
Systems and methods of intrusion detection
Systems and methods of the disclosed embodiments provide a sensor to detect a side from which a door or window is being opened, and a controller communicatively coupled to the sensor to determine the side from which the door or window is being opened, and to generate a security exception based on the determination of the side from which the door or window is being opened. |
| US09672703B2 |
Multistage tactile sound device
A tactile sound device in proximate contact with a user, comprising a multistage arrangement of vibrotactile materials to impart visceral sensations to a user. The device imparts a physical sensation via a multistage arrangement of vibrotactile materials embodied in a wearable or seated configuration, in response to a wired or wireless signal input. |
| US09672698B2 |
Second chance lottery skill wagering interleaved game system
A lottery skill wagering interleaved game system. Responsive to a scanned code provided by an entertainment game module, a random number generation result is generated based on the scanned code. At least one of a virtual credit (VC) amount and a Quanta amount is determined based on the random number generation result. The determined amount of at least one of VC and Quanta is recorded in a player profile of a player associated with the entertainment game module and the scanned code. The skill wagering interleaved game interleaves a gambling game with an interactive entertainment game. The determined amount of at least one of VC and Quanta for the player are used within an interactive entertainment game session of the player. |
| US09672696B2 |
Gaming system and method incorporating winning enhancements
A computer implemented method is provided for integrating winning enhancements with a video game performed by a video gaming computer device comprising: selecting on a random basis a first set of chance elements, that determine a first gaming outcome; retrieving one or more rules for generating and displaying video gaming output based on the first set of chance elements, the video gaming output including a first set of gaming elements organized in a first array; displaying the first set of gaming elements; selecting on a random basis a second set of chance elements that determine a second gaming outcome; retrieving one or more rules for generating and displaying video gaming output based on the second set of chance elements as a second set of gaming elements that produce winning enhancements, the second set of gaming elements being organized in a second array; and displaying the winning enhancements in way that simulates the second set of gaming elements interacting physically with the first set of gaming elements. In another aspect, the second set of gaming elements interact with the first set of gaming elements via a grid overlay. A gaming device, gaming computer system, and gaming computer program that incorporates the wining enhancements is also provided. |
| US09672695B2 |
Gaming machine conducting indication effect
A gaming machine stores a plurality of notification patterns of the backlight unit displayable at least in the symbol rearrangement regions of the reel unit including the regions where the symbols are rearranged, a notification pattern being assigned to each of the notification patterns. The gaming machine randomly determines the symbols to be rearranged on the reel unit. The gaming machine determines a combination formed by the determined symbols. The gaming machine selects a notification pattern based on the determined combination. The gaming machine executes a selected notification pattern by the backlight unit, at a notification timing which is before the rearrangement of the symbols on the reel unit. |
| US09672694B2 |
Shared progressive with certificates gaming system and method
Disclosed is a progressive system for paying out a primary progressive prize and a secondary progressive prize. The system includes a progressive controller, a plurality of game devices each configured to execute a game of chance and a network interconnecting the progressive controller and the game devices. A funding module is executable by the progressive controller to maintain primary and secondary award pools. In accordance with one or more embodiments, the game devices may award shares of the secondary progressive pool to players. When the primary progressive is triggered, share holders may redeem their shares for a value determined by the system. In some embodiments, winners of shares may monitor the value of their pending certificates through various outlets such as social media sites. |
| US09672690B2 |
Credit and enabling system for virtual constructs in a hybrid game
Systems and methods in accordance with embodiments of the invention operate a controlled entity hybrid game. A controlled entity hybrid game includes a real world engine constructed to provide a randomly generated payout of real world credits from at least one wager in a gambling game, an entertainment software engine constructed to execute an entertainment game providing outcomes based upon a player's skillful execution of the entertainment game; and a game world engine constructed to manage the entertainment software engine and communicate, to the gambling game, a gameplay gambling event occurrence based upon a player's instruction of a controlled entity to consume an element of the entertainment game that triggers a wager in the gambling game, and change the element on the basis of the randomly generated payout and an entertainment game variable. |
| US09672685B2 |
Wagering game with altered probabilities based on reel strip configurations
A casino wagering game machine includes an electronic display device, electronic input device(s), and controller(s). The controller(s) detect, via at least one of the electronic input device(s), a physical item associated with a monetary value that establishes a credit balance. The controller(s) initiate the casino wagering game responsive to an input indicative of a wager covered by the credit balance and randomly select two or more adjacent reels of a plurality of reels to include one or more sets of adjacent identical symbols. The controller(s) spin and stop the reels with the adjacent identical symbols in each set represented as a single meta-symbol while the reels are spinning, award an award based on any winning outcomes displayed on the stopped reels, adding the award to the credit balance, and receive, via at least one of the electronic input device(s), a cashout input that initiates a payment from the credit balance. |
| US09672675B1 |
Lock-unlock system for vehicle
A lock-unlock system for a vehicle includes a mobile terminal and an in-vehicle device. The mobile terminal includes a unit to return a first response signal responding to a first request signal, and a unit to return a second response signal responding to a second request signal in response to receiving power supplied by electromagnetic induction induced by the second request signal. The in-vehicle device includes a unit to transmit the first request signal, to execute first verification control for verifying an identification code in the first response signal; a unit to transmit the second request signal, to execute second verification control for verifying an identification code in the second response signal; and a unit to indicate switching from the first verification control to the second verification control if a condition for the switching is satisfied after the first verification control has been started, to the user. |
| US09672670B2 |
Control system for providing cloud based commands for controlling operation of a moveable barrier
A control system for providing Cloud based commands to a garage door includes one or more Cloud servers for receiving commands from at least one mobile web enabled user device. A load balancer is used for receiving communication from a server for distributing commands from at least one web enabled device to the Cloud. A server based garage door opener is used for receiving commands and controlling operation of a garage door from the server. The status of the garage door is determined by measuring a distance of the garage door to the garage floor using a distance measuring device such that distance measuring information is communicated to the server for determining the open or closed status of the garage door before movement. |
| US09672669B1 |
Key fob case
The key fob case is a case that is adapted for use in with an automobile key fobs. The key fob case is a rigid case with a lid. When not in use, the automobile key fob is placed inside the key fob case to prevent inadvertent operation of the buttons on the automobile key fob. The key fob case is closed with the lid, which is a hinged transparent cover that fits the rigid case. The key fob case also has a switched light for use in darkness. The key fob case comprises a container, a cover, a hinge, and a light. |
| US09672662B2 |
Method for creating a surgical resection plan for treating a pathological deformity of a bone
The invention relates to a method for creating a surgical resection plan for treating a pathological deformity of a bone. |
| US09672661B2 |
Damage detection and repair system and method using enhanced geolocation
A damage detection and repair system is provided for performing a damage detection and repair preparation process, and includes an image-capturing device having at least one camera lens, a first positional sensor, and an orientation sensor. At least three second positional sensors are provided for the object to detect a corresponding three-dimensional (3D) position of the object relative to the image-capturing device. A location determination module determines a positional information of the damage of the object based on signals received from the first positional sensor, the orientation sensor, and the second positional sensors. A 3D generation module generates a 3D digital mockup model for illustrating the damage of the object and associated parts needed for repairing the damage. |
| US09672658B2 |
Portable globe creation for a geographical information system
Portable globes may be provided for viewing regions of interest in a Geographical Information System (GIS). A method for providing a portable globe for a GIS may include determining one or more selected regions corresponding to a geographical region of a master globe. The method may further include organizing geospatial data from the master globe based on the selected region and creating the portable globe based on the geospatial data. The portable globe may be smaller in data size than the master globe. The method may include transmitting the portable globe to a local device that may render the selected region at a higher resolution than the remainder of the portable globe in the GIS. A system for providing a portable globe may include a selection module, a fusion module and a transmitter. A system for updating a portable globe may include a packet bundler and a globe cutter. |
| US09672656B1 |
Variable level-of-detail map rendering
To render features on a digital map, a position and orientation of a virtual camera relative to a plane of the digital map is determined. The plane is tilted so that a plane of a viewport of the digital map is not parallel to the plane of the digital map, where the viewport delimiting a view of the digital map. Map features are selected for inclusion in the view of the digital map in accordance with the determined position and orientation of the virtual camera. A level-of-detail (LOD) is determined for each of the map features in accordance with a distance between the virtual camera and the map feature. The map features are rendered, using a rendering engine, in accordance with the determined LODs. |
| US09672655B2 |
System and method for modeling a biopsy specimen
The present disclosure provides, in certain embodiments, a system and method for generating a 3D model of a biopsy specimen. The 3D model may greatly enhance the capability to identify insufficient margins surrounding neoplastic tissue obtained through an excisional biopsy, and improve communication from a pathologist back to a surgeon and/or patient. The model provides a 3D representation of the neoplastic tissue within the specimen, thereby allowing the surgeon (or other medical personnel) to rotate and orient the model at any desired angle to identify insufficient margins and relate the location of the insufficient margins to the removal site to more accurately identify the location at which additional tissue needs to be excised. By identifying the exact location at which additional tissue needs to be excised, the surgeon is able to minimize the amount of additional tissue removed from the patient in order to achieve sufficient margins. |
| US09672654B2 |
Method and apparatus for accelerating ray tracing
Provided is a method of accelerating ray tracing. The method includes extracting characteristics of an input ray at a ray scanner, determining a ray with characteristics similar to that of the input ray based on comparing characteristics of the input ray with characteristics of rays used in previous renderings, and conducting a set up for ray tracing of the input ray based on a ray tracing of the determined ray. |
| US09672651B2 |
Four-dimensional reconstruction of regions exhibiting multiple phases of periodic motion
A method for four dimensional reconstruction of regions exhibiting multiple phases of periodic motion includes the operation of building one or more 3-D reconstructions using a set of 2-D projections. The method further includes the operation of deriving one or more 3-D model segments from each of the one or more 3-D reconstructions, wherein a plurality of 3-D model segments are formed thereby, and wherein each of the one or more 3-D model segments is derived from a single one of the one or more 3-D model segments. The plurality of derived 3-D model segments forms a 4-D reconstruction of the region of interest. |
| US09672649B2 |
System and method for enabling mirror video chat using a wearable display device
A method of exchanging audio-visual communication information between users includes detecting using an image capturing device associated with a wearable communication device, a mirror or image reflecting surface disposed in an environment of a first user, detecting a boundary of the mirror or image reflecting surface in response to the mirror being detected in the environment of the first user, selecting a portion of a first image displayed on the mirror or image reflecting surface within the boundary of the mirror or image reflecting surface, and displaying the portion of the first image as an overlay on a second image to a second user. A corresponding system and computer-readable device are also disclosed. |
| US09672648B2 |
Augmented reality aided navigation
In a computer-implemented method for augmented reality aided navigation to at least one physical device indicia corresponding to the at least one physical device supporting virtualization infrastructure is observed. Based on the observed indicia, navigational cues correlating to a location of the at least one physical device is generated. Navigational cues are displayed such that augmented reality aided navigation is provided to the at least one physical device. |
| US09672647B2 |
Image effect extraction
Techniques are disclosed for facilitating the sharing of digital imaging effects from an image originator to an image recipient. A digital imaging effect is the result of a processing technique that is applied to a digital image in a way that produces a particular visual effect. The processing techniques that underlie digital imaging effects such as these can be defined by parameters that establish how the individual pixels comprising the image are manipulated to achieve the desired visual effect. In certain embodiments such defining parameters can be incorporated into a digital image file that thus contains not only data defining the image itself, but also parameters that define one or more effects that may have been applied to the image. This advantageously allows a recipient of the digital image file to not only view the image, but also to use the incorporated parameters to apply the effect to other images. |
| US09672646B2 |
System and method for image editing using visual rewind operation
Systems, methods, and computer-readable storage media for performing a visual rewind operation in an image editing application may include capturing, compressing, and storing image data and interaction logs and correlations between them. The stored information may be used in a visual rewind operation, during which a sequence of frames (e.g., an animation) depicting changes in an image during image editing operations is displayed in reverse order. In response to navigating to a point in the animation, data representing the image state at that point may be reconstructed from the stored data and stored as a modified image or a variation thereof. The methods may be employed in an image editing application to provide a partial undo operation, image editing variation previewing, and/or visually-driven editing script creation. The methods may be implemented as stand-alone applications or as program instructions implementing components of a graphics application, executable by a CPU and/or GPU. |
| US09672638B2 |
Spectral X-ray computed tomography reconstruction using a vectorial total variation
An apparatus and method of reconstructing a computed tomography (CT) image using multiple datasets of projective measurements, wherein the method of image reconstruction favors spatial correlations among the images respectively reconstructed from each of the corresponding multiple datasets. The multiple data sets each contain projective measurements of the same object taken in close temporal proximity, but taken with different detector type or configurations (e.g., different spectral components in spectral CT or different detector types in hybrid 3rd- and 4th-generation CT scanners). Reconstructed images minimizing a vectorial total variation norm satisfies the criteria of favoring images exhibiting spatial correlations among the reconstructed images and favoring a sparse gradient-magnitude image (i.e., edge enhancing image) for each reconstructed image. |
| US09672637B2 |
Instrument for vehicle
This instrument for the vehicle includes: a display unit; a light source; and a control unit, wherein in response to an input of an dramatized-display instruction signal, the control unit causes an dramatized display that is different from the predetermined display to be displayed in the first display region, causes the second display region to turn dark, and causes the light source to be lit with a predetermined brightness when the configured brightness is greater than the predetermined brightness. |
| US09672636B2 |
Texture masking for video quality measurement
A particular implementation decomposes an image into a structure component and a texture component. An edge strength map is calculated for the structure component, and a texture strength map is calculated for the texture component. Using the edge strength and the texture strength, texture masking weights are calculated. The stronger the texture strength is, or the weaker the edge strength is, the more distortion can be tolerated by human eyes, and thus, the smaller the texture masking weight is. The local distortions are then weighted by the texture masking weights to generate an overall distortion level or an overall quality metric. |
| US09672635B2 |
Method for analyzing related images, image processing system, vehicle comprising such system and computer program product
A method for analyzing related images corresponding system and vehicle including such system as well as a computer program product for executing the method. The method comprises obtaining at least a first and a second image, defining a pixel patch in the first image for which a correlation shall be calculated, calculating matching cost values between each pixel of the pixel patch in the first image and its corresponding pixel in each of a plurality of pixel patches in the second image, wherein the pixel patches in the second image differ in position in the second image and include the pixel patch with a target position, aggregating the matching cost values of those corresponding pixels of all patches in the second image which match best to generate an aggregation window associated with the target position, and producing a signal including information on the target position. |
| US09672634B2 |
System and a method for tracking objects
A method for video object tracking using stereoscopic images with depth maps. The method comprises calculating a first axis histogram for each depth map and applying: a first object detection method to track objects based on at least one of: the contents of the images and the depth maps; and a second object detection method to track objects based on the contents of the histograms of the depth maps. The locations of tracked objects are determined based on comparison of the results of the first object detection method and the second object detection method. |
| US09672632B2 |
Device and method for camera driven background subtraction
A device, system, and method performs a camera driven background subtraction. The method being performed at an electronic device includes receiving information corresponding to an image-capturing device that is capturing an image. The method includes automatically selecting one of a plurality of image analysis mechanisms based upon the information. The method includes receiving the captured image captured by the image-capturing device. The method includes performing an image analysis using the selected image analysis mechanism on the captured image to determine a foreground and a background in the captured image. |
| US09672631B2 |
Medical image reporting system and method
This invention relates generally to medical imaging and, in particular, to a method and system for reconstructing a model path through a branched tubular organ. Novel methodologies and systems segment and define accurate endoluminal surfaces in airway trees, including small peripheral bronchi. An automatic algorithm is described that searches the entire lung volume for airway branches and poses airway-tree segmentation as a global graph-theoretic optimization problem. A suite of interactive segmentation tools for cleaning and extending critical areas of the automatically segmented result is disclosed. A model path is reconstructed through the airway tree. |
| US09672630B2 |
Contour line measurement apparatus and robot system
A contour line measurement apparatus includes an edge line extraction unit for setting a picture processing region and extracting an edge line from an object picture in each of the regions, an edge point generation unit for generating edge points which are intersections of the edge lines and epipolar lines, a corresponding point selection unit for selecting, from the plurality of edge points, a pair of edge points corresponding to the same portion of the reference contour line, and a three dimensional point calculation unit for calculating a three dimensional point on the contour line of the object on the basis of lines of sight of cameras which pass the pair of edge points. |
| US09672628B2 |
Method for partitioning area, and inspection device
An area partitioning method for partitioning an image into a foreground and a background includes a foreground designation step of causing a user to designate a part of pixels in an area that should be the foreground in the image as a foreground designating pixel, an estimation step of estimating a foreground color distribution and a background color distribution based on a color of the foreground designating pixel designated by the user, and an area partition step of partitioning the image into a foreground area and a background area with the estimated foreground color distribution and the estimated background color distribution as a condition. The estimation step includes dividing the color distribution of the image into a plurality of clusters, and selecting at least one cluster having a large relationship with the foreground designating pixel designated by the user in the plurality of clusters as the foreground color distribution. |
| US09672624B2 |
Method for calibrating absolute misalignment between linear array image sensor and attitude control sensor
Provided is a method for estimating and calibrating an absolute misalignment between an attitude control sensor of a satellite or a flight vehicle imaging and transmitting ground images having high resolution and an imaging payload. |
| US09672623B2 |
Image calibration
A digital image is captured. The captured digital image includes a calibration pattern. The calibration pattern includes displayed information about the calibration pattern. The displayed information is read to obtain calibration information about the captured digital image. A new image is generated. The calibration information is stored with the new image. |
| US09672622B2 |
Image fusion with automated compensation for brain deformation
A system can include a model to represent a volumetric deformation of a brain corresponding to brain tissue that has been displaced by at least one of disease, surgery or anatomical changes. A fusion engine can perform a coarse and/or fine fusion to align a first image of the brain with respect to a second image of the brain after a region of the brain has been displaced and to employ the deformation model to adjust one or more points on a displacement vector extending through a displaced region of the brain to compensate for spatial deformations that occur between the first and second image of the brain. |
| US09672620B2 |
Reconstruction with object detection for images captured from a capsule camera
A method of processing images captured using a capsule camera is disclosed. According to one embodiment, two images designated as a reference image and a float image are received, where the float image corresponds to a captured capsule image and the reference image corresponds to a previously composite image or another captured capsule image prior to the float image. Automatic segmentation is applied to the float image and the reference image to detect any non-GI (non-gastrointestinal) region. The non-GI regions are excluded in match measure between the reference image and a deformed float image during the registration process. The two images are stitched together by rendering the two images at the common coordinate. In another embodiment, large area of non-GI regions are removed directly from the input image, and remaining portions are stitched together to form a new image without performing image registration. |
| US09672617B2 |
Methods and systems for producing an implant
A computer implemented method for determining the 3-dimensional shape of an implant to be implanted into a subject includes obtaining a computer readable image including a defective portion and a non-defective portion of tissue in the subject, superimposing on the image a shape to span the defective portion, and determining the 3-dimensional shape of the implant based on the shape that spans the defective portion. |
| US09672616B2 |
Processing imaging data to obtain tissue type information
Methods and apparatus for obtaining probability density functions representing expected distributions of values of a parameter associated with an imaging modality are disclosed. The probability density functions are derived using data obtained from reference tissue volumes using the same imaging modality and at least one other type of imaging modality. The probability density functions are used to analyze data obtained from a volume of tissue of a patient in order to classify the tissue according to tissue type. Methods and apparatus are also disclosed in which deviations from a mean of an arctangent of ratios of first and second metabolite intensities in voxels are used to identify tissue types. |
| US09672614B2 |
Multi-structure atlas and/or use thereof
An image data processor (106) includes a structural image data processor (114) that employs a multi-structure atlas to segment a region of interest from structural image data that includes tissue of interest and that segments the tissue of interests from the region of interest. The image data processor further includes functional image data processor (116) that identifies the tissue of interest in functional image data based on the segmented tissue of interest. An image data processor includes a multi-structure atlas generator (104) that generates a multi-structure atlas. The multi-structure atlas physically maps structure to tissue of interest such that locate the structure in structural image data based on the multi-structure atlas localizes the tissue of interest to the region of interest. |
| US09672613B2 |
Dose- and time-optimized monitoring of bolus values
A method and a system for monitoring a bolus value are disclosed. The method includes contrast-agent-assisted test recording of a time series of test images of a region under examination, wherein one bolus value is determined in each of the respective test images, together with the change in the bolus values between at least two test images. The method includes regulating the time interval between the recordings of individual test images as a function of the change in the bolus values, thereby enabling the temporal resolution for determining the bolus value to be selected in such a way that it corresponds to the change in the bolus values. In this way the temporal resolution in the monitoring of bolus values is improved with a view to avoiding both too high and too low a recording rate for the test images. |
| US09672612B2 |
Image processing device, image processing method, and image processing program for classification of region of interest from intraluminal images based on initial region feature and expansion region feature
An image processing device classifies a region of interest included in an image into multiple classification items. The image processing device has: an initial region detector that detects at least part of the region of interest and sets the part as an initial region; an expansion region detector that detects an expansion region by expanding the initial region; and a region determining unit that calculates feature data of the initial region and the expansion region, and determines, based on the feature data, to which of the multiple classification items the region of interest belongs. |
| US09672611B2 |
Pattern analysis method of a semiconductor device
A pattern analysis method of a semiconductor device includes extracting a contour image of material layer patterns formed on a wafer, calculating an individual density value (DV) representing an area difference between the contour image and a target layout image, scoring the material layer patterns on the wafer using the individual DV, identifying a failure pattern among the scored material layer patterns, calculating coordinates of the identified failure pattern and displaying the coordinates on a critical dimension-scanning electron microscopy (CD-SEM) image, inputting a reference DV in the computer and automatically sorting the material layer patterns into material layer patterns having a hotspot and material layer patterns not having a hotspot, and reviewing the sorted material layer patterns having the hotspot. |
| US09672610B2 |
Image processing apparatus, image processing method, and computer-readable recording medium
An image processing apparatus processes an image obtained by capturing inside of a lumen of a living body. The image processing apparatus includes: a contour edge region extracting unit configured to extract a contour edge region of an examination target from the image; an examination region setting unit configured to set an examination region in the image so as not to include the contour edge region; and an abnormal structure identifying unit configured to identify whether a microstructure of a surface of the examination target is abnormal, based on texture information of the examination region. |
| US09672607B2 |
Identification and registration of multi-marker jig
Registering coordinate systems on an image is carried out by positioning a calibration jig having at least two collinear marker quadruples that are opaque to an imaging modality. Collinear quadruples are detected on an image of the jig and respective image cross ratios of the collinear quadruples are computed. Candidate lines are established by associating at least one collinear marker quadruple and at least one collinear image quadruple that have matching cross ratios. Respective registrations of the calibration jig with the image are performed using pairs of the candidate lines. One of the registrations is selected, wherein the selected registration has a residual that is smaller than a predetermined value. |
| US09672604B2 |
Convolutional color correction
A computing device may obtain an input image. The input image may have a white point represented by chrominance values that define white color in the input image. Possibly based on colors of the input image, the computing device may generate a two-dimensional chrominance histogram of the input image. The computing device may convolve the two-dimensional chrominance histogram with a filter to create a two-dimensional heat map. Entries in the two-dimensional heat map may represent respective estimates of how close respective tints corresponding to the respective entries are to the white point of the input image. The computing device may select an entry in the two-dimensional heat map that represents a particular value that is within a threshold of a maximum value in the heat map, and based on the selected entry, tint the input image to form an output image. |
| US09672603B2 |
Image processing apparatus, image processing method, display apparatus, and control method for display apparatus for generating and displaying a combined image of a high-dynamic-range image and a low-dynamic-range image
An image processing apparatus according to the present invention includes: a generating unit configured to generate a combined image in which a graphic image is combined on a non-combined image; and an outputting unit configured to output the combined image, wherein when generating a combined image in which a graphic image with a narrower dynamic range than the non-combined image is combined on the non-combined image, the generating unit generates a combined image in which brightness of at least one region among a region of the graphic image and a region of a periphery thereof is limited to a first threshold or lower. |
| US09672602B2 |
Projection image correcting apparatus, method for correcting image to be projected, and program
A projection image correcting apparatus for correcting, according to a three-dimensional shape of a projection surface, an original image to be projected, includes a projecting unit configured to project a pattern image on the projection surface, by controlling an image projecting device; a capturing unit configured to obtain a captured image of the projection surface on which the pattern image is projected, by controlling an image capturing device; a feature point extracting unit configured to extract feature points in the captured image corresponding to feature points in the pattern image; and a three-dimensional coordinates measuring unit configured to measure, by triangulation using the extracted feature points, three-dimensional coordinates of a plurality of measuring points on the projection surface corresponding to the feature points; and a reliability calculating unit configured to calculate reliabilities of the measuring points. |
| US09672601B2 |
System, method and computer-accessible medium for restoring an image taken through a window
Systems, methods and computer-accessible mediums for modifying an image(s) can be provided. For example, first image information for the image(s) can be received. Second image information can be generated by separating the first image information into at least two overlapping images. The image(s) can be modified using a prediction procedure based on the second image information. |
| US09672598B2 |
Color moire reducing method, color moire reducing apparatus, and image processing apparatus
Provided are a color moire reducing method, a color moire reducing apparatus, and an image processing apparatus. The color moire reducing method includes calculating a plurality of local color mean values around a pixel in a selected region of a current image, calculating difference values between the local color mean values and a maximum difference value from among the difference values, and setting a moire correction weight to the pixel on the basis of the maximum difference value. |
| US09672595B2 |
Ultrasonic image processing apparatus
There is provided an ultrasound image processing apparatus which displays an ultrasonic image with a higher resolution. For each pixel of interest on a previous frame, a pattern matching process is applied between the previous frame and a current frame, to calculate, for each pixel of interest, a mapping address to the current frame as a movement destination or a two-dimensional movement vector. The mapping address includes an integer value and a fractional value. The current frame is re-constructed into a high-density frame including a plurality of interpolation lines based on an original group of pixels of the current frame and an additional group of pixels defined by a pixel value and the mapping address of each pixel of interest on the previous frame. In generation of the mapping address, a sub-pixel process is applied. |
| US09672594B2 |
Multiple pixel pitch super resolution
A camera system for producing super resolution images is disclosed. The camera system may include a target scene, a first detector configured to capture a first image of the target scene, and a second detector configured to capture a second image of the target scene. The first detector may include a first pitch, and the second detector may include a second pitch different from the first pitch. |
| US09672593B2 |
Lens distortion correction using a neurosynaptic system
Embodiments of the invention provide a system and circuit for image distortion correction. The system includes neurosynaptic core circuits that: receive a set of inputs comprising image dimensions and pixel distortion coefficients for one or more image frames via one or more input core circuits, map each distorted pixel to zero or more undistorted pixels by processing the set of inputs corresponding to each pixel of the one or more image frames by the one or more input core circuits, and route corresponding pixel intensity values of each distorted pixel to output undistorted pixels for each image frame via one or more output core circuits. |
| US09672592B2 |
Tiling-display system and method thereof
A tiling-display system includes an image source device, a splitter unit, a plurality of control units, and a plurality of display devices. The splitter unit receives a source image from the image source device and outputs a plurality of replication images. Each of the source image and the replication images has a first image size. The control units receive the replication images and generate sub-images according to groups of setting parameters. Each of the groups of setting parameter includes a scale, a shift and a rotation angle. The shifts of the group of the setting parameters are different from each other, and each of the plurality of sub-images has a second image size and the corresponding rotation angle. The display devices receive and display the sub-images from the control units. The display devices are arranged according to the rotation angle and display a tiled image. |
| US09672591B2 |
Collage display of image projects
Techniques are described for displaying projects of images as “collages”. Collages differ from conventional thumbnail displays of projects in that collages display an entire project as if the project were a single image. Consequently, collages better convey the characteristics of projects as a whole, while de-emphasizing the distinctiveness of individual images within the projects. When displayed as collages, side-by-side comparisons may be readily performed between projects as a whole. For example, a single display may include collages for multiple projects, thereby allowing viewers to quickly tell how the projects differ in a variety of ways, including but not limited to size of shoot or density of shoot, dominant color, mood, time of day, bracketed shots or bursts, location and subject matter. The content of the collage for a project is based on the individual images that belong to the project. However, details of the individual images on which the project image is based may not be readily discernible from the collage. In addition, not all individual images that belong to a project may be used in a collage. Techniques for selecting which individual images of a project to include in the project are also described. |
| US09672590B2 |
Image interpolation method and device based on autoregressive model
An image interpolation method and device based on an autoregressive model. The method first, interpolating a low-resolution image up to a target scale to obtain an interpolated image M; determining a local area W in the image M to be interpolated, establishing two autoregressive models for each pixel point in the local area W except for the edge pixel points, and determining an initial objective function F0 according to the autoregressive models; down sampling the local area W except for the edge pixel points to the same size as the low-resolution image to obtain a local area W′, subtracting a corresponding area in the low-resolution image from W′ one pixel value by one pixel value, and adding the result to the initial objective function F0 to obtain an objective function F; performing iteration on the objective function F to obtain a pixel point value of a center block of W. |
| US09672584B2 |
Systems and methods of partial frame buffer updating
Aspects include a pixel source that produces data for a rendered surface divided into regions. A mapping identifies memory segments storing pixel data for each region of the surface. The mapping can identify memory segments storing pixel data from a prior rendered surface, for regions that were unchanged during rendering the rendering. Such changed/unchanged status is tracked on a region by region basis. A counter can be maintained for each memory segments to track how many surfaces use pixel data stored therein. A pool of free memory segments can be maintained. Reading a surface, such as to display a rendered surface by a display controller, includes identifying and reading the mapping to identify each memory segment storing pixel data for regions of the surface, reading such, and updating the counters for the memory segments that were read. |
| US09672583B2 |
GPU accelerated address translation for graphics virtualization
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics memory therein; an address translation service integrated with the graphics processor unit; a hypervisor to manage one or more guest machines; wherein the hypervisor is to configure a lookup table within the graphics memory of the graphics processor unit; and further wherein the address translation service of the graphics processor unit is to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory. Such a graphics processor unit may be implemented separate from a system, for example, embodied within a silicon integrated circuit. |
| US09672581B2 |
Multimodal biometric profiling
Multimodal biometric profiling may include receiving a cover image and a biometric template for a person. An indication of a security requirement related to biometric profiling for the person may be received. A threshold value may be determined based on the indicated security requirement. The threshold value may be used to limit a number of biometric template bits of the biometric template that are embedded in a predetermined bit position of a cover image pixel of the cover image based on cover image intensity associated with the predetermined bit position. |
| US09672579B1 |
Apparatus and method providing computer-implemented environment for improved educator effectiveness
A method provides a computer-implemented environment for improved educator effectiveness. The method includes a server serving, receiving, and storing web pages over a wide area network connected to client computers of administrators or teachers of a school, so the administrators or teachers can create, use or view processes and observation workflows to conduct performance reviews of teachers in the school. |
| US09672578B2 |
Catalog-based software license reconciliation
A software reconciliation engine utilizes a software rule-based catalog to produce accurate license reconciliation across a wide range of software configurations. A software offering may comprise software installables and corresponding constraints. Installed software and active hardware is discovered by a scanner, stored in an installed software database and active hardware database respectively and is mapped against entitled software offerings to determine whether the installed software is entitled to be installed on the hardware. The installed software has a base product attribute, a used-in-count attribute and a parent-child attribute that are used by the reconciliation engine to compare against the constraints to determine entitlement and report compliance. |
| US09672577B2 |
Estimating component power usage from aggregate power usage
A method for estimating component power usage using aggregate power usage data are provided in the illustrative embodiments. A power estimation model is received, the model correlating a factor of the component with an aggregate power consumption of a set of components during a period, the component being a member of the set of components, the component being a hardware device operating in the data processing environment and consuming electrical power, the factor being a characteristic of the component related to the consumption of the electrical power in the component. A value of the factor at a determined time is received. The value of the factor is applied to the power estimation model to generate an estimate of electrical power consumed by the component. The estimate is output as the estimated power usage of the component when the factor attains the value. |
| US09672571B2 |
System and method to provide vehicle telematics based data on a map display
A system and method are disclosed herein to determine an insurance premium discount based on telematics data. The system includes a computer memory and a processor in communication with the computer memory. The computer memory stores data indicative telematics data received from a sensor within a vehicle, including at least one of geo-position information of the vehicle and vehicle kinematics data. The processor is configured to identify safety events and associated safety event locations based on the telematics data. The processor is further configured to display to the driver indications of the safety events on a map display along with indications of safety events associated with other drivers. |
| US09672566B2 |
System and method for processing securities trading instructions and communicating order status via a messaging interface
A system allowing traders, etc. to use instant messaging (IM) (or other non-FIX based) communications to input trading instructions directly into a broker's Order Management System (OMS) for managing/executing trades. Accordingly, trading instructions may be provided electronically directly from a buy-side trader, and directly to a sell-side broker's/brokerage's OMS, without the need for the sell-side broker to manually re-key the order into the sell-side firm's OMS. Further, trading instructions are provided in electronic format directly to the broker's OMS without the need for the buy-side trader to have an expensive FIX based OMS or associated FIX connection, which is also expensive, thereby allowing relatively smaller investment houses/buy-side organizations to enjoy the benefits of electronic delivery of trading instructions directly to brokers' OMS. |
| US09672557B2 |
System and method for improved parallel search on bipartite graphs using dynamic vertex-to-processor mapping
One embodiment of the present invention provides a system for dynamically assigning vertices to processors to generate a recommendation for a customer. During operation, the system receives graph data with customer and product vertices and purchase edges. The system traverses the graph from a customer vertex to a set of product vertices. The system divides the set of product vertices among a set of processors. Subsequently, the system determines a set of product frontier vertices for each processor. The system traverses the graph from the set of product frontier vertices to a set of customer vertices. The system divides the set of customer vertices among a set of processors. Then, the system determines a set of customer frontier vertices for each processor. The system traverses the graph from the set of customer frontier vertices to a set of recommendable product vertices. The system generates one or more product recommendations for the customer. |
| US09672556B2 |
Systems and methods for programatically classifying text using topic classification
Systems and methods for programmatically classifying text are discussed herein. Some embodiments may provide for a system including circuitry configured to programmatically classify a block of text. For example, the circuitry may be configured to identify topics associated with the block of text and identify one or more categories for each of the topics. The circuitry may be further configured to determine unique categories across the one or more categories for each of the topics. For each unique category, an actual category frequency may be determined based on a number of times each of the topics in the block of text is associated with the unique category. The circuitry may be further configured to associate a unique category with the block of text based on the actual category frequency for each the unique category and one or more other actual category frequencies for one or more other unique categories. |
| US09672552B2 |
Methods of augmenting search engines for ecommerce information retrieval
Queries against search engines like the Google Search Appliance, Elastic Search and other readily available search engines to provide meaningful content for the purpose of supporting eCommerce websites. In particular, methods that provide for an intelligent abstraction to know when and how to generate a set of queries, the set of queries including one or more queries that are relevant to the searchable content are disclosed. In addition, the methods also can determine if a query against the search engine is even required and may redirect the use to other dynamic or static content outside the search index utilized by the search engine to satisfy the queries. |
| US09672540B2 |
Web page ad slot identification
Systems and methods of identifying ad elements of web pages via a computer network are provided. A script configured to identify an ad slot on a web page can be obtained by at least one data processing system having an ad slot evaluation module. The script can be executed to obtain advertisement parameters of the ad slot and web page parameters of the ad slot and generate a unique identifier of the ad slot. The generated unique identifier is associated with a URL identifier of the web page. The data processing system evaluates at least one database to determine one of a presence and an absence of the historical ad slot data. The data processing system provides content for display in the ad slot of the web page based at least in part on a result of the evaluation of the database. |
| US09672530B2 |
Supporting voting-based campaigns in search
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, receiving a search query from a user; determining that a voting user interface (VUI) is to be provided based on the search query, the VUI enabling the user to submit one or more votes in a vote-based campaign; receiving search results that are responsive to the search query; and transmitting instructions to display the search results and the VUI. |
| US09672524B2 |
Computer-guided corporate governance with document generation and execution
A system for organizing, managing, and reporting data relating to a corporate entity, comprising; at least one database configured to store a document record relating to a corporate action, the document record further comprising a core record reflecting human-readable information for incorporation into the generated document and stored with the document record, the document record further comprising a set of tags stored with the document record; a business logic module, coupled to the at least one database; and at least one document template stored in the at least one database and comprising instructions for generating, at the business logic module, a document based on the core record with an initial set of tags, wherein a first tag of the set of tags is in a text format and associates a human-readable document type with the document record, thereby providing namespaced tagging and retrieval of document records. |
| US09672519B2 |
Mobile device software radio for securely passing financial information between a customer and a financial services firm
A computing device having a software radio (e.g., a mobile device where the software radio is substantially defined in software) transmits first information related to a financial transaction over the first radio network to the financial institution, and transmits second information related to the financial transaction over the second radio network to the financial institution. A server of the financial institution receives the first information and the second information to carry out the financial transaction. |
| US09672515B2 |
Method and system for secure payments over a computer network
A method of conducting a financial transaction by a purchaser over a communications network is provided where the purchaser does not transmit his or her “real” payment card information over the network but instead secure payment application software is provided which allows for the transmission of a pseudo account number that is cryptographically processed for purposes of responding to an authorization request based on the real account number. |
| US09672512B1 |
Processor routing number for mobile communication service provider billing
A method of billing a payment transaction to a mobile communication service account. The method comprises receiving a request for mobile communication service provider billing approval from a payment processor, wherein the request comprises one of a phone number associated with a mobile communication service account or an equipment identification of a mobile communication device associated with the mobile communication service account, wherein the request comprises a processor routing number, wherein the processor routing number is consistent in format with one of a block of credit card numbers maintained by a mobile communication service provider, and wherein the processor routing number is used by different mobile communication devices associated with different mobile communication service accounts to complete payments. The method further comprises identifying the service account based on one of the phone number or the equipment identification of the mobile communication device, and charging to the mobile communication service account. |
| US09672511B2 |
Location dependent communications between mobile devices and transaction terminals to order mobile device payment accounts
A mobile device having: a position determination device configured to determine a location of the mobile device; a transceiver configured to communicate with a transaction terminal via near field communication; a communication device configured to communicate with at least one server over internet; a memory storing a plurality of data items and a set of instructions of a mobile application; and at least one microprocessor coupled with the memory to execution the instructions of the mobile application. The mobile application is configured to: communicate the location of the mobile device, using the communication device, to the at least one server over internet; determine, via communications with the at least one server based on the location of the mobile device, an order of data items; and communicate, using the transceiver via near field communication, with the transaction terminal in accordance with the order of the data items. |
| US09672507B2 |
Multifunction point of sale system
A point of sale system capable of operating in an indicia-reading mode or a verification mode is disclosed. In the indicia-reading mode, the point of sale system configures its illumination, imaging, and processing to read indicia as part of a normal checkout process. If triggered by a user or by an event, the point of sale system may operate in a verification mode. In the verification mode, the point of sale system enables the necessary illumination, imaging, and processing to verify an item. This verification includes illuminating the item in a way that causes a noticeable response from a security mark (or marks) on the item. An image of the response may be captured and processed to authenticate/verify the item. The point of sale system may then respond to the verification and/or may store the image/results as a record of the verification. |
| US09672503B2 |
Bandwidth metering in large-scale networks
Methods and apparatus for bandwidth metering in large-scale networks are disclosed. Metadata for a network transmission involving a virtualized resource at a host of a provider network, including endpoint address information and a traffic metric, is determined at a metering component. The metadata is aggregated at another metering component and provided to a traffic classification node. The traffic classification node generates a categorized usage record for the network transmission, based at least in part on network topology information associated with the provider network. The categorized usage record is used to determine a billing amount for the network transmission. |
| US09672502B2 |
Network-as-a-service product director
A device may receive order information that may identify a network service to be provided, via a service provider network, to a service location associated with a customer. The device may determine context information associated with providing the network service. The context information may be determined based on the order information and may include information associated with a virtual network function (VNF) that is to provide the network service to the service location. The device may determine provisioning details associated with the network service. The device may generate a service request that includes the context information and the provisioning details. The device may identify a cloud resource that is to host the VNF. The device may provide the service request to the cloud resource to cause the VNF to be created and inserted into the service provider network. |
| US09672499B2 |
Data analytic and security mechanism for implementing a hot wallet service
Some embodiments include a hot wallet service system including: a manager server configured to receive a cryptocurrency transaction request identifying at least a hot wallet accountholder identifier and to determine a first set of authentication servers to authenticate the cryptocurrency transaction request; the authentication servers, each configured to independently authenticate the cryptocurrency transaction request by verifying a requester of the cryptocurrency transaction request against an accountholder profile associated with the hot wallet accountholder identifier; wherein the authentication servers are configured to approve, independently from each other, the cryptocurrency transaction request by cryptographically signing approval messages to send to an aggregation server using respective private authentication keys stored respectively in the authentication servers when the requester is verified; and the aggregation server configured to aggregate cryptographic signatures of the cryptocurrency transaction request from the authentication servers to publish the cryptocurrency transaction request into a cryptocurrency network. |
| US09672498B2 |
Methods, systems, and computer readable media for managing periodic aircraft maintenance planning plans
Methods, systems, and computer readable media for managing periodic aircraft maintenance planning are provided. In some aspects, a method occurs at a maintenance platform server including a processor. The method includes providing one or more maintenance related object (MO), wherein each of the one or more MO represents one or more maintenance related task that includes criteria graphically depicted at an interface. In another aspect, the method further includes manipulating the criteria of the one or more maintenance related task represented by the one or more MO at the interface. |
| US09672494B2 |
Light-weight lifecycle management of enqueue locks
In an example embodiment, a request for an enqueue lock for a first piece of data is received from a client application. At an enqueue server separate from an application server instance, a light-weight enqueue session is then created, including generating a light-weight enqueue session identification for the light-weight enqueue session. An enqueue lock for the first piece of data is stored in the light-weight enqueue session. The light-weight enqueue session identification is then sent to the client application. In response to a detection that a session between the client application and the application server instance has been terminated, all enqueue locks in the light-weight enqueue session are deleted and the light-weight enqueue session is deleted. |
| US09672490B2 |
Procurement system
A procurement system may include a first interface configured to receive a query from a user, a command module configured to parameterize the query, an intelligent search and match engine configured to compare the parameterized query with stored queries in a historical knowledge base and, in the event the parameterized query does not match a stored query within the historical knowledge base, search for a match in a plurality of knowledge models, and a response solution engine configured to receive a system response ID from the intelligent search and match engine, the response solution engine being configured to initiate a system action by interacting with sub-system and related databases to generate a system response. |
| US09672489B1 |
Inventory validator with notification manager
A validator for an inventory management system is provided. The validator comprises at least one validation module, wherein the at least one validation module validates at least a portion of inventory information in the inventory management system by comparing the portion of inventory information to equivalent information in an information source that is one of a group of information sources comprising at least one of: a domain name system for converting a name of an alphanumerically labeled network component into an IP address, an automated monitoring system for monitoring a status of equipment for which the inventory management system maintains inventory information, a backup system capable of recording errors that occur in a data backup procedure, and a photograph system that maintains photographs of equipment for which the inventory management system maintains inventory information. |
| US09672488B1 |
Assessment construction tool
An assessment construction tool is provided for developing and executing assessments of various operational aspects of a business entity. Both application-level and project-level assessments may be constructed, and the assessments include a mechanism for applying scores associated with answers derived from conducting the assessment to multiple assessment process categories of the business entity. |
| US09672486B1 |
Inspection tool
Disclosed is a web-based tool for facilitating the inspection process for evaluating inspection items relating to assets at a site. A website is used to interface with the hand held devices used by inspectors in the field and create consistency in the way questions are posed, and recorded for inspection items. Unique identifiers are associated with each item so that they can be tracked. Also, a wireless camera arrangement is implemented where any photographs taken of a condition of a particular inspection item will automatically be incorporated into the form open regarding that item. |
| US09672484B2 |
Systems and methods for interfacing between a sales management system and a project planning system
The present disclosure facilitates interfacing between a sales management system and a project planning system. In some embodiments, the system includes an interface and schedule engine, both executing on a server. The interface can parse a sales order from the sales management system into products and project tasks within the products. The products can also include at least one of a labor product, a parts product, and an agreements product. The schedule engine can generate schedule tasks corresponding to the project tasks, determine a performance order of the schedule tasks, and combine the schedule tasks into schedule phases based on the performance order. The schedule engine can determine a performance order of the schedule phases and combine the schedule phases into a schedule component based on the performance order. The interface can transmit the schedule component to the project planning system for execution. |
| US09672483B2 |
Method of providing activity notification and device thereof
A method of providing an activity notification is provided. The method includes registering, by the device, information about the activity notification according to a request for registering the activity notification, and transmitting, by the device, the registered information about the activity notification to a management device, wherein the management device performs a process of providing the activity notification. |
| US09672479B2 |
System, method and apparatus for power management
A system, method and apparatus provide management of power to meet demand of consumers that consume the power. An interface is configured to receive a pricing signal that indicates a price for the power. Wherein the interface is configured to control an appliance coupled to the interface to shift adjusting power consumption sooner in time than the appliance is predetermined to shift its power consumption. |
| US09672476B1 |
Contextual text adaptation
Contextual adaptation of documents automatically replaces words for synonyms that appear within context or topic whey they are being used. A machine learned topic modeling, trained by a set of documents representative of a target user is executed to determine topics of an input document, and to determine words in the document to replace based on determining the relevance of the words to the topics in the documents. An output document is generated based on the input document with the replaced words. |
| US09672467B2 |
Systems and methods for creating and implementing an artificially intelligent agent or system
A system and associated methods for creating and implementing an artificially intelligent agent or system are disclosed. In at least one embodiment, a target personality is implemented in memory on an at least one computing device and configured for responding to an at least one conversational input received from an at least one communicating entity. An at least one conversational personality is configured for conversing with the target personality as needed in order to provide the target personality with appropriate knowledge and responses. For each conversational input received by the target personality, it is first processed to derive an at least one core meaning associated therewith. An appropriate raw response is determined then formatted before being transmitted to the communicating entity. Thus, the target personality is capable of carrying on a conversation, even if some responses provided by the target personality are obtained from the at least one conversational personality. |
| US09672466B2 |
Methods and systems of four-valued genomic sequencing and macromolecular analysis
A four-valued logic system for genomic sequencing and macromolecular analysis using a semantic network having object nodes and relationships between the object nodes. The object nodes are each represented by two vectors with true, false, defined, or undefined values in corresponding bits in the two vectors. Conditionals or quantifying variables are tested during successive recursive steps in a predicate calculus using the four-valued logic system. |
| US09672464B2 |
Method and apparatus for efficient implementation of common neuron models
Certain aspects of the present disclosure support efficient implementation of common neuron models. In an aspect, a first memory layout can be allocated for parameters and state variables of instances of a first neuron model, and a second memory layout different from the first memory layout can be allocated for parameters and state variables of instances of a second neuron model having a different complexity than the first neuron model. |
| US09672463B2 |
People counting method and apparatus
An apparatus configured to count people in a target area includes a wireless transceiver and a controller. The wireless transceiver is configured to radiate an impulse electromagnetic wave to the target area and receive a reflection signal from the target area, and the controller is configured to obtain a signal strength of the reflection signal over a reception time period during which the reflection signal is received and count people according to the signal strength, considering that the signal strength is weakened in proportion to the reception time period. |
| US09672462B2 |
Smart surface-mounted hybrid sensor system, method, and apparatus for counting
A counting system includes a counting apparatus, which includes a plurality of multi-sensor detectors configured to detect physical contact data and vertical range data corresponding to one or more steps across the multi-sensor detectors, and first circuitry configured to determine physical contact vectors and coordinate data from the physical contact data and the vertical range data. The counting system also includes at least one server including second circuitry configured to receive the physical contact vectors and the coordinate data from the counting apparatus, determine footprint patterns and body patterns based on the physical contact vectors and the coordinate data, and estimate a number of beings passing over the counting apparatus based on the footprint patterns and the body patterns. |
| US09672461B2 |
Smart card with display and production method thereof
The invention relates to the technical field of smart cards with displays. Such a card comprises, embedded in a transparent core, a multi-component module supporting the display. The card comprises: at least one layer of ink printed on the surface of the transparent core, except in a zone facing the display, said at least one layer being opaque in at least one region; and a transparent film covering the at least one ink layer. The card is characterized in that the at least one layer is formed by a first opaque ink layer printed on the surface of the transparent core, except in a zone facing the display and a second ink layer forming a graphic design allowing customization printed on the first ink layer. |
| US09672460B2 |
Configuring signal devices in thermal processing systems
In some aspects, consumables for a material processing head can include a body that is substantially axially symmetric about a central longitudinal axis; and a ring-shaped data tag attached to the body, the data tag having a central axis that is substantially coaxial to the central longitudinal axis of the body, the data tag having a conductive coil formed around the central axis of the data tag. |
| US09672457B2 |
Image forming apparatus capable of changing cut position on long medium and control method thereof
An image forming apparatus, provided with an image forming part that performs an image formation on each of individual medium pieces that are attached to a long base sheet with specified gaps wherein a long medium is configured with the long base sheet and the medium pieces, a length of the gaps being defined as a gap length, a carrying part that carries the long medium to the image forming part in a medium carrying direction, a cutting part that cuts the long medium that is being carried by the carrying part, and a cut position determining part that determines a cut position where the long medium is cut by the cutting part, the cut position being located at one of the gaps, wherein the cut position determining part changes the cut position according to the gap length. |
| US09672455B2 |
Image reading apparatus that outputs one or more files in which is stored generated image data
When acquired information contains setting information indicating to output first format file, a first output process is executed, wherein a reading process is performed and an inquiry is executed as to whether to continue reading. Every time when receiving an instruction to continue reading, a reading process is performed and the inquiry is executed. A first format file, in which is stored image data that has been generated until when an instruction not to continue reading is received, is outputted. When the acquired information contains setting information to output second format file, a second output process is executed, wherein a reading process is performed, and one or more second format files, whose number is equal to a number of sets of image data generated through the reading process, is outputted such that each set of image data is stored in a corresponding second format file. |
| US09672452B2 |
Image forming apparatus
An image forming apparatus which can reduce the required number of line buffers and random number generation circuits when performing a magnification changing process in a band process. The CPU 51 determines a range of a random number value (random number value rnd) which is generated by a random number generator, based on the scanning width (band process width d) and the length in a sub-scanning direction of an area (sub-scanning length ay). The CPU 51 receives a random number (random number value rnd), which is in the above range, and performs image processing in which a pixel is inserted or deleted at the position determined by the received random number (random number value rnd). |
| US09672447B2 |
Segmentation based image transform
The present invention relates to a method for changing the appearance of an original image comprising N>1 classes of image elements, the method comprising the step of: for each pixel and for at least one subset of the original image: calculating N probability values, each probability value defining a probability for the pixel of belonging to a corresponding one of the N classes of image elements, transforming a color of the pixel by using predetermined color transforms for each of the N classes of image elements and the N probability values for the pixel. |
| US09672446B1 |
Object detection for an autonomous vehicle
An object detection system for an autonomous vehicle processes sensor data, including one or more images, obtained for a road segment on which the autonomous vehicle is being driven. The object detection system compares the images to three-dimensional (3D) environment data for the road segment to determine pixels in the images that correspond to objects not previously identified in the 3D environment data. The object detection system then analyzes the pixels to classify the objects not previously identified in the 3D environment data. |
| US09672444B2 |
Method for producing denture parts or for tooth restoration using electronic dental representations
A method and apparatus related to forming prosthetic dental items or tooth restorations. A defective tooth, prosthetic dental item, or a dentition is scanned. A first electronic data set from a three-dimensional scan of a defective tooth, defective prosthetic dental item, or the dentition is generated, and one or more correspondence points or structure in the first electronic data set are assigned to one or more corresponding points or structures in a second electronic data set. The second electronic data set represents a tooth model. To generate a patient specific tooth model, the tooth model is adjusted such that a function which describes one or more distances between the one or more correspondence points or structures in the first electronic data set and the one or more corresponding points or structures in the second electronic data set is minimized. |
| US09672437B2 |
Legibility enhancement for a logo, text or other region of interest in video
A video processing system enhances quality of an overlay image, such as a logo, text, game scores, or other areas forming a region of interest (ROI) in a video stream. The system separately enhances the video quality of the ROI, particularly when screen size is reduced. The data enhancement can be accomplished at decoding with metadata provided with the video data for decoding so that the ROI that can be separately enhanced from the video. In improve legibility, the ROI enhancer can increase contrast, brightness, hue, saturation, and bit density of the ROI. The ROI enhancer can operate down to a pixel-by-pixel level. The ROI enhancer may use stored reference picture templates to enhance a current ROI based on a comparison. When the ROI includes text, a minimum reduction size for the ROI relative to the remaining video can be identified so that the ROI is not reduced below human perceptibility. |