Document Document Title
US09674014B2 Method and apparatus for high speed chip-to-chip communications
Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.
US09674012B2 Decision feedback equalizer and control method thereof
A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.
US09674010B2 Updating a filter of an equalizer
In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter.
US09674009B2 Receiver with offset calibration
An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.
US09674008B2 Body-biased slicer design for predictive decision feedback equalizers
A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
US09674006B2 Systems and methods to switch radio frequency signals for greater isolation
In semiconductor switches, the isolation can be limited by the capacitive coupling between the switch input and the switch output. Ultra-high isolation can be achieved by adding a coupled transmission line to the semiconductor switch. The coupled transmission line introduces inductive coupling, which cancels at least a part of the capacitive coupling between the switch input and the switch output.
US09673992B2 Method for operating a network as well as a local network and network component
The invention relates to a method for operating a network as well as a local network comprising network components and to network components, in particular of a home network, where a functional command is generated, which is configured to execute an assigned function in a network station, wherein a user identification, which is derived from the collected user data, is assigned to the functional command, the assigned user identification is evaluated in the network station in response to executing the functional command and the functional command is executed when, in response to the evaluation of the corresponding user identification, it is established that the functional command is approved in connection with the assigned user identification.
US09673986B2 Methods and systems for increasing the security of private keys
A method for increasing the security of private keys is provided that includes generating transaction data at a device operated by a user and processing the transaction data. Moreover, the method includes determining whether the user permits using a private key that is associated with the user and with a public-private key pair of the user. The private key is stored in a computer system different from the device. Furthermore, the method includes authenticating the user when the user permits using the private key, applying the private key to other data after successfully authenticating the user, and transmitting the other data to the device. The method also includes conducting a transaction with the transaction data.
US09673981B1 Verification of authenticity and responsiveness of biometric evidence and/or other evidence
Authenticity and responsiveness of evidence (e.g., biometric evidence) may be validated without regard for whether there is direct control over a sensor that acquired the evidence. In some implementations, only a data block containing evidence that is (1) appended with a server-generated challenge (e.g., a nonce) and (2) signed or encrypted by the sensor may validate that the evidence is responsive to a current request and belongs to a current session. In some implementations, trust may be established and/or enhanced due to one or more security features (e.g., anti-spoofing, anti-tampering, and/or other security features) being collocated with the sensor at the actual sampling site.
US09673979B1 Hierarchical, deterministic, one-time login tokens
Methods, systems and articles of manufacture for hierarchical, deterministic, one-time login tokens are provided herein. A method includes generating a plurality of items of key information comprising a first item of key information and a second item of key information that is derived from the first item of key information; attributing a distinct authorization level to the plurality of items of key information to create a modified version of the first item of key information and a modified version of the second item of key information; providing the modified version of the first item of key information to a first cryptographic device to be used in an authentication request associated with a second cryptographic device; and providing the modified version of the second item of key information to the second cryptographic device to be used in an authentication request with the first cryptographic device.
US09673968B2 Multi-wire open-drain link with data symbol transition based clocking
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.
US09673967B2 Synchronisation using pilots and data
A method for estimating a time offset of a transmitted signal which comprises pilot symbols and data symbols, the method comprising: receiving the transmitted signal to produce a received signal; and processing an optimizing function of the received signal at a finite number of possible time offsets to produce an estimator of the time offset.
US09673963B1 Multi-protocols and multi-data rates communications
Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.
US09673955B2 Mobile station
An objective is to appropriately select a “timing reference cell” and a “Pathloss reference cell” for an Scell in an sTAG. A mobile station UE according to the present invention includes a second management unit 11B configured to use a “UL Cell” managed in association with a “DL only Cell” where to perform a downlink communication only, as a Pcell or an Scell in a pTAG.
US09673951B2 Method of transmitting and receiving channel quality indicator information in wireless access system and device supporting same
The present invention relates to a method of transmitting and receiving channel quality indicator (CQI) information that relates to a channel aging effect in an environment where a time-varying channel characteristic is maximized, and a device supporting same. According to an embodiment of the present invention, a method of reporting multi-channel quality indicator (CQI) information by a terminal in a wireless access system that supports an environment where a time-varying channel characteristic is maximized may include receiving a first reference signal, obtaining information on a first CQI by using the first reference signal, receiving a second reference signal, obtaining information on a second CQI by using the second reference signal, reporting the information on the first CQI, and reporting the information on the second CQI.
US09673948B2 Hybrid pilot design for low latency communication
Methods, systems, and devices are described for wireless communication at a UE. A base station may select a hybrid pilot configuration including a relatively sparse periodic pilot and a dense pilot embedded in one or more symbols of a low latency burst. A user equipment (UE) may generate a long term statistical average channel estimate based on the periodic pilot and an instantaneous channel estimate (e.g., for demodulation) based on the dense pilot embedded in the low latency burst. The UE may refine the instantaneous channel estimate by converting a control channel embedded with the burst. In some instances, the base station may embed the dense pilots in the first symbol of a burst and transmit subsequent low latency symbols with a reduced density pilot (or without pilot tones).
US09673947B2 Methods for transmitting and receiving control channel, base station, and user equipment
The present invention provides methods for transmitting and receiving a control channel, a base station, and a user equipment. The method for transmitting a control channel includes: determining m PRB pairs used for transmitting a control channel to be transmitted; when a distributed transmission mode is used for transmission, determining an aggregation level L of the control channel to be transmitted; determining, according to the aggregation level L, a first control channel candidate at the aggregation level L; and placing, on physical resources to which the first control channel candidate is mapped, control information of the control channel to be transmitted, and transmitting the control information. The present invention improves multiplexing efficiency of control channels of different modes.
US09673941B2 Frequency-domain high-speed bus signal integrity compliance model
Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
US09673938B2 Method for configuring table of network apparatus in LTE TDD system and network apparatus using the same
The disclosure is directed to a method and apparatus for configuring a table of a network apparatus in a Long Term Evolution (LTE) time division duplexing (TDD) communication system. In one of the exemplary embodiments, the method would include identifying, from UL HARQ reference configurations and DL HARQ reference configurations, valid combinations that are compatible with an eIMTA relay; obtaining, for each of the valid combinations of the UL HARQ reference configurations and the DL HARQ reference configurations, a set of valid UL-DL subframe configuration that is compatible with the eIMTA relay; and obtaining, for each of the valid combinations of the UL HARQ reference configurations and the DL HARQ reference configurations, a set of valid SubframeConfigurationTDD that is compatible with the eIMTA relay.
US09673936B2 Method and system for providing error correction to low-latency streaming video
Disclosed is a method for providing error correction to a video stream transmitted from a server to a client device, wherein the server is connected to an intermediate module over a bandwidth-limited network and the intermediate module is connected to the client device over a lossy network. The method includes intercepting data transmitted from the bandwidth-limited network to the lossy network by the intermediate module, identifying the video stream for error correction from the intercepted data at the intermediate module, generating error correction data for the video stream by the intermediate module and transmitting a modified stream that includes the video stream and the error correction data over the lossy network to the client device by the intermediate module.
US09673933B2 Method and apparatus for transmitting and receiving packet in a communication system
A method for transmitting a packet in a communication system is provided. The method includes dividing a data stream into data payloads of a predetermined size and adding a common header to each of the data payloads, to generate a source payload, adding a first Forward Error Correction (FEC) payload Identifier (ID) to the source payload and applying an FEC code thereto, to generate an FEC source packet for a source payload, adding a second FEC payload ID to at least one parity payload and applying an FEC code thereto, to generate an FEC parity packet for the at least one parity payload, and transmitting the FEC source packet and the FEC parity packet.
US09673929B2 Optical transmission apparatus and optical transmission system
An optical transmission apparatus including: an attenuator that attenuates a power of a first optical signal generated in a first modulation method to a first target level and attenuates a power of a second optical signal generated in a second modulation method, a modulation level in the second modulation method being lower than the modulation level in the first modulation method, to a second target level, the second target level being lower than the first target level; and a transmitter that sends a WDM signal including the first optical signal and the second optical signal that have been attenuated by the attenuator.
US09673928B2 Method, system and apparatus of time-division-duplex (TDD) uplink-downlink (UL-DL) configuration management
Some demonstrative embodiments include devices, systems and/or methods of Time-Division Duplexing (TDD) Uplink-Downlink (UL-DL) configuration management. For example, a node may communicate a message including a cell identifier identifying a first cell controlled by the node, and a TDD configuration update to update at least one other node, which controls at least one second cell, with a TDD UL-DL configuration allocated by the node for communication within the first cell.
US09673922B2 Method and system for user speed estimation in wireless networks
A method for estimating the speed of a user equipment connected to a base station of a wireless network, the method comprising the following steps: —performing signal strength measurements (S) of a radio signal transmitted between the user equipment and the base station; —performing a spectral analysis (11) of the signal strength measurements; —determining the frequency of a local maximum in the power spectrum of the signal strength measurements; —estimating (12), from previously established reference data, the speed of the user equipment that corresponds to the determined frequency, the reference data associating a given user equipment speed with a certain determined frequency.
US09673921B1 Wireless fidelity (Wi-Fi) clear channel assesment (CCA) detection and transmission decision making in a portable device
Described herein are technologies related to an implementation of Wi-Fi CCA detection and transmission decision making using a histogram data block. For example, the histogram data block facilitates threshold values that are used for the transmission decision making to avoid Wi-Fi signal retransmission and/or collision.
US09673916B2 Electronic device with over-the-air wireless self-testing capabilities
An electronic device may be provided with wireless circuitry. The wireless circuitry may include antennas. The antennas may include phased antenna arrays for handling millimeter wave signals. Antennas may be located in antenna signal paths. The antenna signal paths may include adjustable components such as adjustable filters, adjustable gain amplifiers, and adjustable phase shifters. Circuitry may be incorporated into an electronic device to facilitate wireless self-testing operations. Wireless self-testing may involve use of one antenna to transmit an over-the-air antenna test signal that is received by another antenna. The circuitry that facilitates the wireless self-testing operations may include couplers, adjustable switches for temporarily shorting antenna signal paths together, mixers for mixing down radio-frequency signals to allow digitization with analog-to-digital converters, and other circuitry for supporting self-testing operations.
US09673915B2 Systems and methods for enhancing spectral efficiency in a communication network
A method for calibrating rates at which data is transmitted in a communication system. There is a short transmission utilizing a first set of communication parameters comprising first and second communication parameters. The first set of communication parameters are different from the second set of communication parameters used to create stable communication between the transmitter and receiver. The second set of communication parameters comprise first and second communication parameters. Then determining that there are substantially no errors associated with reception of the short transmission by the receiver. Then transmitting a long transmission utilizing a third set of communication parameters comprising first and second communication parameters. The first communication parameter of the third set is equal to the first communication parameter of the first set. The second communication parameter of the third set is equal to the second communication parameter of the second set.
US09673913B2 Circuit arrangement with interference protection
A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.
US09673911B2 Tracking nonlinear cross-phase modulation noise and linewidth induced jitter in coherent optical fiber communication links
An optical receiver may include a digital signal processor to receive an input sample that includes transmitted data, transmitted by an optical transmitter, and nonlinear distortion. The digital signal processor may process the input sample to generate an estimated data value. The estimated data value may be an estimate of the transmitted data. The digital signal processor may remove the estimated data value from the input sample to generate a noise sample. The digital signal processor may determine a nonlinear distortion value based on the input sample, the estimated data value, and the noise sample. The nonlinear distortion value may be an estimate of the nonlinear distortion included in the input sample. The digital signal processor may remove the nonlinear distortion value from the input sample to generate an output sample, and may output the output sample.
US09673909B2 Optical receiver module providing semiconductor optical amplifier
An optical receiver module that provides a semiconductor optical amplifier (SOA) is disclosed. The optical receiver module provides the SOA in another housing and a photodiode (PD) enclosed in another housing. The housing for the SOA and the other housing for the PD are fixed as interposing a coupling unit therebetween, which is rigidly fixed to those housings. The coupling unit has a bore that passes light output from a facet of the SOA and received by the PD. A feature of the coupling unit is that a width or diameter of the bore of the coupling unit is smaller than widths of respective housings along a direction perpendicular to the optical axis of the light.
US09673907B1 Constellation shaping of modulation formats for optical communication systems
Methods and systems for constellation shaping of modulation formats in optical communication systems may involve enabling an optical transport network to activate/deactivate constellation shaping on a per channel basis for a given optical path using universal programmable transceivers. Then, constellation shaping may be activated to increase the reach of optical channels by improving signal-to-noise ratio over the optical path.
US09673902B2 Visible light communication system
A visible light communication system is provided. The communication system includes at least one of a FFD and a visible light communication light source, and a RFD, wherein the visible light communication light source is configured to carry data information in a visible light signal and send the visible light signal; the RFD is in communication with the FFD and/or in communication with the visible light communication light source, and is configured to receive the visible light signal and demodulate the received visible light signal to recover data information; and the FFD is configured to achieve at least one of the following functions: the function of the visible light communication light source, the function of the RFD, and a function for forwarding the received visible light signal. In the present invention, the technical problem that visible light resources cannot be used fully because there is no network structure used for the visible light communications in the conventional art is solved, thereby achieving the technical effect of improving the utilization rate of the visible light.
US09673901B2 USPL-FSO lasercom point-to-point and point-to-multipoint optical wireless communication
Enhancements in optical beam propagation performance can be realized through the utilization of ultra-short pulse laser (USPL) sources for laser transmit platforms, which are can be used throughout the telecommunication network infrastructure fabric. One or more of the described and illustrated features of USPL free space-optical (USPL-FSO) laser communications can be used in improving optical propagation through the atmosphere, for example by mitigating optical attenuation and scintillation effects, thereby enhancing effective system availability as well as link budget considerations, as evidenced through experimental studies and theoretical calculations between USPL and fog related atmospheric events.
US09673899B2 In-band OSNR measurement on polarization-multiplexed signals
There is provided a system and a method for determining an in-band noise parameter representative of the optical noise contribution (such as OSNR) on a polarization-multiplexed optical Signal-Under-Test (SUT) comprising two polarized phase-modulated data-carrying contributions and an optical noise contribution. For each of a multiplicity of distinct polarization-analyzer conditions, the SUT is analyzed to provide at least one polarization-analyzed component of the SUT and the polarization-analyzed component is detected with an electronic bandwidth at least ten times smaller than the symbol rate of the SUT to obtain a corresponding acquired electrical signal; for each acquired electrical signal, a value of a statistical parameter is determined from the ac component of the acquired electrical signal, thereby providing a set of statistical-parameter values corresponding to the multiplicity of distinct polarization-analyzer conditions; and, from the set of statistical-parameter values, the in-band noise parameter is mathematically determined.
US09673893B2 Safety-enhanced laser array
When an unsafe port with a loss of signal is detected, a transceiver may enable one laser in a group of lasers associated with the unsafe port and may disable the remaining lasers. Then, the transceiver may instruct a transmitter associated with the one laser to transmit an optical signal on the unsafe port using a reduced transmit power that is less than a threshold value associated with the Class 1 conditions and at a different time than enabled lasers in other groups of lasers. Alternatively, for a safe port on which valid communication is received, the transceiver may enable lasers in a group of lasers associated with the safe port. Then, the transceiver may instruct transmitters associated with the lasers in this group of lasers to transmit optical signals on the safe port using a normal transmit power for the lasers that is greater than the threshold value.
US09673890B2 Using modulation-transcendent RF sampled digital data over an IP connection
The apparatus and methodologies used herein leverages RoIP to generically transport either conventional modulation (e.g., AM, FM, phase or pulse) or complex modulation (e.g., GMSK, CDMA, TDMA, OFDM, etc.) in real time or near real time across an internet protocol link, such as Gigabit Ethernet (GBE). The purpose of the invention is a method of creating a live, virtual, modulation transcendent link by using an internet protocol (IP) link to extend the natural range of a connection between an RF signal source (e.g. transmitter) and an RF receiving device (e.g. receiver). This methodology is referred to herein as radio frequency over internet protocol (RFoIP).
US09673889B2 Satellite operating system, architecture, testing and radio communication system
A cubesat communication system implementing addressable data packet for transmitting information collected by the cubesat to one or more receive-only ground stations. The cubesat may transmit information to the receive-only ground stations according to a scheduler. The receive-only ground stations may receive information from the cubesat without sending any commands to the cubesat to prompt transmission and re-transmit to a central common station using a bent pipe streaming protocol. Information between the cubesat and the ground station may be transmitted via a connectionless, datagram network protocol.
US09673885B2 Push-based relay selection for device-to-device communication
Techniques are described for wireless communication. One method includes estimating a pathloss from each of a plurality of relay candidates to a first communication device to generate a first capacity estimate for the first communication device for each of the plurality of relay candidates; receiving at the first communication device, from a second communication device, a second capacity estimate for the second communication device for each of the plurality of relay candidates; and selecting a relay from the plurality of relay candidates for relaying communications between the first communication device and the second communication device based at least in part on each first capacity estimate for the first communication device and each second capacity estimate for the second communication device.
US09673883B2 Method and apparatus for implementing channel measurement
A method and an apparatus for implementing channel measurement are disclosed in the present invention. The method includes: determining an antenna port subset, which is required to be measured, for a UE according to current state information of the user equipment UE; and informing the UE to perform channel measurement for the subset of antenna ports that is required to be measured and feed back channel state information. Through the present invention, when the state information of the UE meets a certain condition, the UE measures only the reference signals of a part of antenna ports, and feeds back channel state information for this part of antenna ports. Therefore, the overhead generated by the feedback of the UE to the channel state information is reduced.
US09673877B1 Radiofrequency processor
A multiple input, multiple function, multiple output (MIMFMO) radiofrequency (RF) processor including a MIMFMO RF processor element. The MIMFMO RF processor element is configured to receive multiple RF input signals, perform multiple RF operations on the multiple RF input signals, and output processed RF output signals to multiple output circuits.
US09673871B2 Wireless mobile device
A wireless mobile device using a battery as an antenna is provided. The wireless mobile device includes a battery, a system circuit, a RF choke and a DC blocker. The battery has a positive terminal and a negative terminal. The system circuit has a voltage terminal and a RF terminal. The RF choke is connected between the positive terminal of the battery and the voltage terminal of the system circuit. The DC blocker is connected between the positive terminal of the battery and the RF terminal of the system circuit.
US09673866B2 Communication system and communication device
A communication system includes a first communication device that operates using a battery as a main power source and a second communication device that communicates with the first communication device. The second communication device includes a second high-speed data communication unit including a second data communication antenna and a second short-range communication unit including a second magnetic-field antenna for short-range communication. The first communication device includes a first short-range communication unit including a first magnetic-field antenna and a first high-speed data communication unit including a first data communication antenna. When an electromotive voltage of the battery lowers, switches are turned OFF and electric power from a power conversion circuit including a rectifying circuit and a DC-to-DC converter is supplied to a communication controller.
US09673864B2 Wireless hierarchical heterogeneous pico-net for ski control systems
A wireless hierarchical heterogonous pico-net providing communication between smart-phone based analysis and control application and multiplicity of sensors and actuators embedded in the ski equipment is described. The topology of this pico-net comprises two layers of hierarch, where the first layer is configured as a Bluetooth wireless network using a Round-Robin scheduling method and consisting of a single master and up-to seven slaves, and the second layer of the hierarchy is configured as a sub-nets consisting of multiplicity of sensors and actuators and communicating internally using ANT personal area network (PAN) wireless interface, or via a digital wire interface. Such network topology provides deterministic latency of a hierarchy a single-hop Bluetooth network, irrespective of the numbers of sensors and actuators embedded within each sub-net of the second layer of hierarchy. The network latency is upper-bounded by the number of slaves in the first layer of hierarch, Furthermore, the Round-Robin scheduling method is supplemented with the gating-off the slave RF transmission when the slave has no data to send, or when the difference between current sensor samples and the previous sensor sample is smaller then predefined threshold. Such discontinued transmission lowers slave power consumption system interference.
US09673861B2 Cancelling crosstalk
Cancelling crosstalk between at least one transmitter chain and a receiver chain in a wireless communication node makes use of a single feedback path from the transmitter chain that is shared between processing of transmit signals (x) in the transmitter chain and reception signals (s) received in the receiver chain. Information in the shared feedback is used in a crosstalk model to cancel crosstalk in the reception signals.
US09673860B2 Method and apparatus for fast and accurate acquisition of crosstalk coefficients
In accordance with an embodiment, the method includes inserting a plurality of crosstalk probing signals within the wired multi-carrier communication system for probing the crosstalk from respective ones of the plurality of disturber lines into the victim line, carrying out crosstalk measurements over the victim line, and estimating the crosstalk coefficients from the crosstalk measurements. The method further includes organizing the plurality of disturber lines into subsets of disturber lines, and individually assigning disjoint groups of carriers to the respective subsets of disturber lines. The insertion of the plurality of crosstalk probing signals is confined within the respectively assigned groups of carriers. The subsets of disturber lines and/or the groups of carriers used for a second or subsequent iteration are tailored based on crosstalk characteristics observed for the respective disturber lines during a pervious iteration.
US09673850B2 Radio communication devices and methods for controlling a radio communication device
A radio communication device is described comprising: a receiver configured to receive radio signals on a radio channel; a noise level determination circuit configured to determine a noise level of the radio signals; an interference determination circuit configured to determine interference information indicating an amount of interference of the radio signals with other signals; an equalizer configured to determine a softbit based on the radio signals and based on the noise level; and a scaling circuit configured to scale based on the determined interference information at least one of the noise level or the softbit.
US09673845B2 Mixing stage, modulator circuit and a current control circuit
A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.
US09673841B2 Error-correcting code
A method is provided to transmit an error-correcting code. The method includes receiving a source packet, advancing a sliding encoder window after receiving the source packet, and generating coded packets by, when the padded packet is encoded for a first time, encoding the source packet alone, and, when the source packet is encoded for a number of times after the first time, encoding the source packet with older source packets in the sliding window.
US09673837B2 Increasing capacity in wireless communications
Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination (400) of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding (421, 423) is performed on slots as they are received over the air, and techniques are described for signaling (431, 432) acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes (1015) in the system.
US09673836B1 System level testing of entropy encoding
An aspect includes receiving a symbol translation table (STT) that includes input symbols and their corresponding codewords. An entropy encoding descriptor (EED) that specifies how many of the codewords have each of the different lengths is also received. Contents of one or both of the STT and the EED are modified to generate a test case and an entropy encoding test is executed. The executing includes performing a lossless data compression process based on contents of an input data string that includes one or more of the input symbols, and on contents of the STT and the EED; or performing a data expansion process based on contents of an input data string that includes one or more of the codewords, and on contents of the STT and the EED. A result of the entropy encoding test is compared to an expected result.
US09673834B2 Successive approximation method with a nonlinear characteristic
A circuit with a successive approximation analog-to-digital converter utilizes a feedback path and is operated for example in accordance with the successive approximation method. The feedback path is configured to translate a digital signal in accordance with a prescribed function and to furthermore convert the translated digital signal into an analog feedback signal. For example, the prescribed function can be an exponential function. As such, it can be possible to convert an input signal into an output signal by means of a nonlinear characteristic.
US09673832B2 Successive approximation analog-to-digital converter and accuracy improving method thereof
A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.
US09673831B1 Passive switch having low leakage current
In an analog-to-digital converter (ADC) having storage capacitors, passive top-plate switch circuitry has at least one diode-configured transistor connected between a first transistor and the top-plate node of the storage capacitors to provide a diode-voltage drop that ensures that the voltage at the node between two transistors is different from the top-plate node voltage in order to reduce GIDL/GISL leakage current through the first transistor that could adversely affect the ADC's digital output value. A corresponding capacitor is connected across each diode-configured device to reduce the amount of charge needed to achieve intermediate-node, steady-state voltages when the switch circuitry is off. In an n-type implementation, a reverse-diode-biased isolation device is connected between the top-plate node and the at least one diode-configured device to prevent the top-plate node from seeing the large dynamic junction capacitance of the at least one diode-configured device.
US09673825B2 Circuitry and layouts for XOR and XNOR logic
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.
US09673823B2 Semiconductor device and method of driving semiconductor device
A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.
US09673821B1 Wide operating level shifters
Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.
US09673814B2 Semiconductor devices and semiconductor systems including the same
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.
US09673813B2 Power control circuit
A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.
US09673812B2 Gate driver and power module equipped with same
A gate driver that drives a field-effect transistor on the basis of an input signal includes a comparator that compares an applied voltage applied between the drain and the source of a field-effect transistor to a reference voltage for detecting noise occurring between the drain and the source of the field-effect transistor, and a gate voltage switching circuit that, if the field-effect transistor is off, switches the voltage applied between the gate and the source of the field-effect transistor from a first voltage to a second voltage when the output of the comparator transitions from a state indicating that the applied voltage between the drain and the source is less than the reference voltage to a state indicating that the applied voltage between the drain and the source is equal to or greater than the reference voltage.
US09673808B1 Power on-reset circuit
A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.
US09673807B2 Gate voltage control apparatus configured to control a gate voltage of a switching device
A gate voltage control apparatus is configured to perform first to third processes when turning off the gate type switching device. In the first process, the gate voltage is decreased to a value lower than a threshold value so as to increase a voltage between main terminals. In the second process, the gate voltage is controlled at a value higher than the threshold voltage after timing on which the voltage between the main terminals makes a peak value during the first process. In the third process, the gate voltage is decreased to a value equal to or lower than a threshold voltage while the voltage between the main terminals remains at a value lower than the peak value and higher than the on voltage during the second process.
US09673806B2 Gate driver and display device including the same
A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.
US09673804B2 Circuit arrangement of electronic circuit breakers of a power generation device
The invention relates to a circuit arrangement with an electronic power switch, a capacitor and a plate-shaped direct current laminate. The direct current laminate includes two metal plates insulated from one another for carrying current and multiple connection elements arranged so to electrically connect the metal plates to the capacitor. The capacitor is electrically connected by the connection elements to the direct current laminate, and the capacitor is on one side of the direct current laminate. This circuit arrangement has a significantly reduced space requirement and simultaneously improved scalability. This is achieved because the direct current laminate additionally has multiple connection elements arranged so to connect the direct current laminate to the electronic power switch of the circuit arrangement. The electronic power switch is electrically connected by the connection elements to the direct current laminate and is arranged on the opposing side of the direct current laminate.
US09673801B2 Three-lead electronic switch system adapted to replace a mechanical switch
This disclosure provides example methods, devices, and systems for a three-lead electronic switch system adapted to replace a mechanical switch. A device is disclosed that includes a sensor, a current limiting circuit, an output switching circuit comprising a first switching device and a second switching device, and a three lead interface circuit in communication with the output switching circuit and the current limiting circuit. The device includes an electronic switching circuit in communication with the sensor, the current limiting circuit, and the output switching circuit. The electronic switching circuit is configured to drive the first and second switching devices in complementary conduction states responsive to determining the output of the sensor relative to a threshold voltage. The output switching circuit includes a first terminal, a second terminal, and a return terminal that are configured to provide power to the electronic switching circuit while providing an indication of the conduction states.
US09673795B2 Integrated circuit associated with clock generator, and associated control method
An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.
US09673790B2 Circuits and methods of synchronizing differential ring-type oscillators
A circuit includes a first differential ring-type oscillator, a second differential ring-type oscillator, and a coupling structure. The coupling structure capacitively couples the first and second differential ring-type oscillators. A method of synchronizing the first and second differential ring-type oscillators is also disclosed.
US09673786B2 Flip-flop with reduced retention voltage
A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
US09673785B2 Packaged MEMS device comprising adjustable ventilation opening
A packaged MEMS device and a method of calibrating a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device comprises a carrier, a MEMS device disposed on the substrate, a signal processing device disposed on the carrier, a validation circuit disposed on the carrier; and an encapsulation disposed on the carrier, wherein the encapsulation encapsulates the MEMS device, the signal processing device and the memory element.
US09673781B2 Radio-frequency-to-baseband function-reuse receiver with shared amplifiers for common-mode and differential-mode amplification
According to another aspect of the present disclosure, a radio-frequency-to-baseband-function-reuse receiver with shared amplifiers for common-mode and differential-mode amplification is provided. The receiver includes two set networks connected in parallel. The set networks includes a first and a second input capacitors, a first and a second output capacitors, a first transconductance amplifier having an input terminal, a second transconductance amplifier having an input terminal, a first switch, and a second switch. The first and the second input capacitors connect to a first node. The first and the second output capacitors connect to a second node. The first transconductance amplifier connects between the first input capacitor and the first output capacitor. The second transconductance amplifier connects between the second input capacitor and the second output capacitor. The first switch connects between the input terminal of the first transconductance amplifier and the second node. The second switch connects between the input terminal of the second transconductance amplifier and the second node.
US09673779B2 Electroacoustic transducer having reduced losses due to transverse emission and improved performance due to suppression of transverse modes
An electroacoustic transducer has reduced loss due to acoustic waves emitted in the transverse direction. For this purpose, a transducer comprises a central excitation area, inner edge areas flanking the central excitation area, outer edge areas flanking the inner edge areas, and areas of the busbar flanking the outer edge areas. The longitudinal speed of the areas can be set so that the excitation profile of a piston mode is obtained.
US09673776B2 Wide band directional coupler
A wide band directional coupler comprises a first transmission line, a second transmission line and at least one inductor, wherein the first transmission line and the second transmission line are adjacent each other, and the inductor connects to the second transmission. As a RF signal passes through the first transmission line, the second transmission line will couple with the RF signal in the first transmission line to generate a coupling signal. The inductor is connected to the second transmission line to improve the coupling factor and/or the insertion loss of the wide band directional coupler at high frequency band.
US09673775B2 Circuit substrate and branch circuit including high pass filter and low pass filter with mounting portions on substrate body
A circuit substrate includes a substrate body, an input signal line conductor with which the substrate body is provided and included in an input path, a first mounting portion provided on a main surface of the substrate body, included in a first output path and on which a high-pass filter including a lumped-parameter element is mounted, at least one first output signal line conductor with which the substrate body is provided and included in the first output path, and a second mounting portion provided on the main surface of the substrate body, included in a second output path and on which a low-pass filter including a lumped-parameter element is mounted. The first output signal line conductor provided farthest upstream in a signal propagation direction is connected to the input signal line conductor via a first lumped-parameter element mounted on the main surface of the substrate body.
US09673773B2 Signal interconnect with high pass filter
A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.
US09673769B2 Variable gain circuit and tuner system provided with same
A variable gain transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner. A variable gain circuit may include the variable gain transconductance amplifier.
US09673764B2 Amplifier circuit, radio frequency receiver and mobile telecommunications device
An amplifier circuit, comprises a first amplifier stage contributing to a power of an amplified signal and a second amplifier stage contributing to the power of the amplified signal. The first amplifier stage and the second amplifier stage share a transistor.
US09673760B2 Power amplification device and control method of power amplification device
A power amplification device (1) according to an exemplary embodiment of the invention includes a Doherty amplifier (10) that is adjusted to operate at a set frequency, a frequency comparator (11) that compares a supplied frequency being a frequency of an input signal RF_IN to the Doherty amplifier (10) with the set frequency, and a protection circuit (12) that sets an operating state of the Doherty amplifier (10) to inactive when the supplied frequency and the set frequency are different. It is thereby possible to protect the Doherty amplifier (10) when the input signal RF_IN with a frequency different from the set frequency is supplied.
US09673759B1 Off-chip distributed drain biasing of high power distributed amplifier monolithic microwave integrated circuit (MMIC) chips
Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.
US09673758B2 Differential amplifier circuit
A differential amplification circuit may include a differential amplification unit including a first input transistor and a second input transistor, and suitable for differentially amplifying input signals inputted through the first and second input transistors; a first input control section suitable for turning off the first input transistor when the differential amplification circuit is disabled and transferring a first input signal to the first input transistor when the differential amplification circuit is enabled; and a second input control section suitable for turning off the second input transistor when the differential amplification circuit is disabled and transferring a second input signal to the second input transistor when the differential amplification circuit is enabled.
US09673750B2 Mounting structures for photovoltaic cells
Mounting systems for PV modules and assemblies of modules, including apparatus and methods of use. The disclosed systems generally involve mounting a flexible photovoltaic module in a slight arch, bending it with a large radius around one axis of the module.
US09673748B2 Motor control device and motor control method
A motor control circuit controls an operation of a motor based on an input voltage and a control parameter. A voltage-abnormality detection unit detects abnormality of the input voltage by comparing the input voltage with an allowable voltage range. A memory stores therein a plurality of allowable voltage range candidates made to correspond to a plurality of reference voltages and a plurality of control parameter candidates made to correspond to the plurality of reference voltages. A reference-voltage acquisition unit acquires reference voltage information specifying one of the plurality of reference voltages. A selector selects one of the plurality of allowable voltage range candidates from the plurality of allowable voltage range candidates, corresponding to the one reference voltage, as the allowable voltage range and one of the plurality of control parameter candidates from the plurality of control parameter candidates, corresponding to the one reference voltage, as the control parameter based on the reference voltage information.
US09673741B2 System for supplying electrical power to a load and corresponding power supply method
This system for supplying electrical power to a load includes an asynchronous generator including a cage rotor intended to be driven by motor means and a rectifier adapted to rectify the voltage delivered by the generator. The rectifier is a rectifier employing unidirectional electronic components. The power supply system further includes a reactive power source for magnetizing the asynchronous generator.
US09673737B2 Clamp with ceramic electrode
A holding apparatus (100) for electrostatically holding a component (1), in particular a silicon wafer, includes at least one base body (10, 10A, 10B) which is composed of a first plate (11A) and a second plate (12), the first plate (11A) being arranged on an upper side (10A) of the base body (10, 10A, 10B) and the second plate are made of an electrically insulating material, a plurality of projecting, upper burls (13A) which are arranged on the upper side (10A) of the base body (10, 10A, 10B) and form a support surface for the component (1), and a first electrode which is arranged to receive a clamping voltage, wherein the first plate (11A) is made of an electrically conductive, silicon-including ceramic and forms the first electrode. A method for producing the holding apparatus (100) is also described.
US09673734B2 Apparatus for delay angle compensation of flying start function
An apparatus for delay angle compensation for flying start function in a medium-voltage inverter is disclosed. The apparatus generates generate a phase angle (θ) by converting a three-phase voltage of an inverter output terminal to dq-axis voltages (Vd, Vq), and calculate a compensation phase angle by a predetermined delay time. In addition, the apparatus generates an initial angle for the flying start by aggregating the compensation phase angle with the phase angle (θ). The apparatus may drive a high-voltage motor more stably, because an error between a command voltage phase angle and an actual output voltage phase angle may be reduced, when electric power of the medium voltage inverter is restored after a trip or an instantaneous blackout occurs.
US09673718B2 Voltage conversion method and voltage converter
In accordance with an embodiment, a method in a voltage converter includes, in each of successive drive cycles, switching on for an on-period a first electronic switch connected in series with a primary winding of a transformer. Before first electronic switch is switched on, the transformer is pre-magnetized for a pre-magnetizing period, where there is a first delay time between an end of the pre-magnetizing period and a beginning of the on-period.
US09673713B2 Gate drive power supply for multilevel converter
A neutral point clamped, multilevel level converter including a DC voltage link having a positive rail and a negative rail; a phase leg coupled to an AC node, the phase leg having a first switch and a second switch in series between the negative rail and the AC node, the phase leg having a third switch and a fourth switch in series between the positive rail and the AC node; and a gate drive power supply having a charge pump section, the charge pump section generating a first gate drive voltage for the first switch and a second gate drive voltage for the second switch.
US09673709B1 Buck converter electronic driver with enhanced iTHD
Methods, devices, techniques, systems, and integrated circuits are disclosed for variably controlling a switch on time for a driver, which may enhance iTHD. In one example, a device includes an input voltage sensor configured to detect an input voltage, and a variable switch on time generator, operatively connected to the input voltage sensor to receive a signal indicative of the input voltage. The variable switch on time generator is configured to determine a variable switch on time based at least in part on the detected input voltage, and output the determined variable switch on time for controlling switch on timing of a driver switch.
US09673704B2 Inductive load control circuit, a braking system for a vehicle and a method of measuring current in an inductive load control circuit
A method and circuit for controlling current through an inductive load such as an electromagnetic valve of a vehicle anti-lock braking system includes first and second driver stages, controlled by PWM (pulse width modulation) signals, for providing, respectively, an actuation path for valve current in an “on” phase and a recirculation path for valve current in an “off” phase. A peak value of current flowing in the actuation path at the end of an “on” phase is compared with a peak value of current flowing in the recirculation path at the start of the “off” phase in order to detect any malfunction of the circuit. An embodiment of the invention has the advantage of being able to detect any malfunction at very low and very high PWM duty cycles.
US09673700B2 Amplifier circuit and methods of operation thereof
A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.
US09673698B2 Voltage regulator with multiple output ranges
The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X−1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin−X(Vin−Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.
US09673692B2 Application of normally closed power semiconductor devices
A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter.
US09673682B2 Hybrid vertical energy storage system
A hybrid vertical energy storage system is invented wherein the components responsible for the conversion, storage and production of energy are used as the weighted component of a gravitationally aided energy storage device. The present invention allows gravity to operate mechanical devices which may help move a volume of fluid in order to compress a gas and store potential energy. The present invention utilizes the attributes of pumped hydro by using gravity assisted fluid transfer, and also combines Compressed Air Energy Storage (CAES) functionality by powering hydraulic pumps and motors to transfer fluid from one vessel to another vessel. This feature allows conventional, inexpensive, market proven components to make the capture, conversion, storage and production of energy more effective and affordable while eliminating the placement issues associated with such large scale pumped hydro and CAES systems while extending battery service life. Ideally, combining the positive attributes of some or all of the existing technologies into one energy storage system would provide a real and meaningful improvement, especially if the improvement reduced or eliminated economic, environmental and operational flaws associated with the individual technologies. This invention also provides a method of combining the output of individual, combined attribute energy storage systems to provide user definable and expandable electrical energy production. The vertical aspect of the invention allows operational attribute that separates and makes independent the capture and storage of energy being placed into the energy storage system and the hydro-pneumatic production of energy exiting the system.
US09673677B2 Mounting arrangement for an electric motor and a drive unit incorporating same
The present invention provides a mounting arrangement for an electric motor in a drive unit, and a drive unit incorporating such a mounting arrangement. The arrangement includes a motor casing with at least one connecting flange having an opening for receiving a connecting element. The flange is configured for fastening the motor casing to a drive unit housing via the connecting element. At least one alignment member is provided on the flange for engagement with a complementary member on the drive unit housing to align the motor casing with respect to the drive unit. The at least one alignment member is provided on or in a peripheral edge of said connecting flange.
US09673676B2 Single rotor type motor and manufacturng method thereof
A single rotor type motor includes: a stator including a plurality of stator cores that are split and radially arranged, a bobbin made of an insulating material and wrapped on an outer surface of each of the stator cores, coils wound on an outer surface of the bobbin, an upper fixing plate disposed on the upper surfaces of the stator cores and on which the stator cores are radially arranged, and a lower fixing plate that is disposed on the lower surfaces of the stator cores and is coupled with the upper fixing plate; and a single rotor disposed with a certain gap from any one surface of an inner surface of the stator and an outer surface thereof. The plurality of wiring units for electrically connecting between the coils wound around each of the stator cores are formed integrally on the upper surface of the upper fixing plate.
US09673674B2 Stator and rotary electric machine
In a stator having a stator core and three phase windings, slots are formed in the stator core. The phase winding are accommodated in layers, from one side to the other side in the corresponding slot along a radial direction of the stator core. The phase windings are arranged in a star-delta composite connection structure. The phase winding in each phase is comprised of conductors accommodated in a first slot and a second slot adjacently arranged in the stator core so that the conductor in the n-th layer is electrically connected to the conductor in the (n+1)-th layer, ascending order, per slot. Because each winding has the same length and no difference in electric potential occurs between the star connection and the delta connection, this structure suppress generation of operation noise and a circulating current through the stator core and prevents loss due to the circulating current.
US09673671B2 Permanent magnet rotor
A permanent magnet rotor for a motor, the permanent magnet rotor including an iron core and a permanent magnet. The iron core includes an annular ring having a central axial bore and a plurality of magnetic induction blocks protruding outward from an outer side of the annular ring. Between two adjacent magnetic induction blocks form a radial recess for mounting the permanent magnets. The magnetic induction blocks at both sides of an opening of the radial recess protrude with a hook block. The section of an outer side surface of the magnetic induction blocks is a circular-arc line and the outer side surface employs a point with a distance deviating from the center of the central axial bore as a center of circle.
US09673669B2 Brushless motor and rotor
A brushless motor includes a rotor. The rotor includes a first rotor core, a second rotor core and a field magnet. The first rotor core includes a plurality of first magnetic pole portions arranged in a circumferential direction. The second rotor core includes a plurality of second magnetic pole portions arranged in the circumferential direction. The field magnet is arranged between the first rotor core and the second rotor core in an axial direction. When the field magnet is magnetized in the axial direction, the first magnetic pole portions function as first magnetic poles and the second magnetic pole portions function as second magnetic poles.
US09673664B2 Wireless power reception apparatus, wireless power transmission apparatus, and wireless power transmission and reception system
A power transmission apparatus includes a power transmission unit and a power supply unit. A wireless power reception apparatus includes a power reception unit capable of wirelessly receiving electric power from the power transmission unit, and a control unit performing control for positional alignment between the power reception unit and the power transmission unit and for reception of electric power after the positional alignment. The magnitude of electric power received by the power reception unit from the power transmission unit is used for positional alignment between the power reception unit and the power transmission unit. The control unit sets a parameter of a power transmission and reception path so that a power receivable range that can be received by the power reception unit at any time while positional alignment is done is wider than that when electric power is received after the positional alignment.
US09673663B2 Semiconductor integrated circuit with shutoff control for plural power domains
A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.
US09673661B2 Transfer switch with monitor on load side
A transfer switch selectively couples at least two power sources to a load. The load may be a home, business, or vehicle. A current transformer is coupled to the output of the transfer switch and generates a load measurement signal that is proportional to the current or power output from the transfer switch. A controller receives the load measurement signal and a switch setting describing the operation of the switch. The controller generates data for a status message for display based on the load measurement signal and the switch setting. The status message may describe the power consumption of the load or indicate when an error has occurred.
US09673658B2 Non-contact capacitive coupling type power charging apparatus and non-contact capacitive coupling type battery apparatus
A non-contact type power charging apparatus and a non-contact type battery apparatus may transmit power to each of a plurality of battery cells in a capacitive coupling scheme. The non-contact type power charging apparatus may include a power transmitting apparatus transmitting power in a capacitive coupling scheme, and a power receiving apparatus receiving the power transmitted from the power transmitting apparatus to charge each of a plurality of battery cells with the power. The non-contact type battery apparatus may include a plurality of power receiving electrodes each receiving power transmitted in a capacitive coupling scheme, and a plurality of battery cells each charged with the power transmitted to the plurality of power receiving electrodes.
US09673657B2 Battery charging apparatus and approach
Various methods, apparatuses and systems are directed to battery-charging applications. As may be consistent with one or more embodiments discussed herein, a charging current for charging a battery is modulated, and the frequency of the modulated charging current is set based upon an impedance of the battery. Temperature of the battery is estimated based upon the impedance exhibited by the battery, while the battery is charged with the modulated charging current. In various implementations, the battery charging rate is controlled based on the estimated temperature.
US09673656B2 Charge and discharge control circuit and battery device
Provided is a highly safe battery device in which the accuracy of an overcurrent detection current value and a short-circuit current value is improved and current consumption is reduced. A short-circuit and overcurrent detecting circuit includes: a reference voltage circuit configured to output a reference voltage generated when a constant current flows through an impedance element and a transistor having a resistance value that is changed depending on a voltage of a secondary battery; a first comparator circuit configured to compare a voltage of an overcurrent detecting terminal with the reference voltage; and a second comparator circuit configured to compare a voltage based on the voltage of the overcurrent detecting terminal with the reference voltage.
US09673654B2 Multi-stage quick charging system
A multi-stage quick charging system is proposed. The system uses an intermediate power battery as voltage supporting point so that a converter having a fraction of the output voltage may control the entire power flow towards or from the battery of a vehicle or an electrical power device. The intermediate battery comprises several stages in series, associated with respective small chargers allowing a management of the charge balancing of the stages of the intermediate battery, since the chargers may be controlled in order to separately vary the contribution of each stage.
US09673653B2 Control of power flow in battery cells of a vehicle
A vehicle includes a high voltage traction battery for providing propulsion energy to the vehicle. A battery control module controls the operation of the battery, and also commands cell balancing out of or between cells of the battery to maintain a relative equilibrium of charge across a plurality of the cells. The battery control module is in communication with an interactive display in the vehicle or a communication device outside of the vehicle. A user can define a time period in which the vehicle is to enter a hibernation mode. During the hibernation mode, the battery control module inhibits cell balancing in the battery. Upon expiration of the user-defined time period, the battery control module enables cell balancing.
US09673649B2 Charger for lithium ion battery
A lithium ion battery and a charger thereof are provided. The lithium ion battery comprises a shell (1), a locating seat (2), an end cover (3), a battery cell (4), a positive contact (51), a positive plate (52), a negative plate (53), a positive connecting plate (61) and a negative connecting plate (62). The shell (1) is a one-step-molding cylinder with an upper opening. The positive contact (51) extends out from a contact extending hole (11) of the shell (1). A lower end face of the end cover (3) is tightly pressed on the negative plate (53) and the locating seat (2), where the end cover (3) is detachably connected with the upper opening of the shell (1). A cover edge of the end cover (3) cooperates with an end face of the upper opening of the shell (1). The lithium ion battery is conveniently detachable with the charger thereof.
US09673642B2 Discharge control device, discharge control method and computer readable medium
A discharge control device for controlling discharge in an energy storage device disposed in an electric apparatus, wherein the discharge control device includes a first determination unit adapted to determine whether or not an electric apparatus's status is being outside a predetermined first range and a discharge controller adapted to start discharge in the energy storage device, when the first determination unit determines that the status of the electric apparatus is being outside the first range.
US09673641B2 Voltage detecting device
A voltage detecting device includes a plurality of voltage detecting circuits provided for battery modules of a battery, the battery being formed by connecting, in series with each other, the battery modules each formed by connecting battery cells in series with each other, the plurality of voltage detecting circuits being configured to detect voltage of each of the battery cells; a plurality of voltage detecting lines connecting the battery cells to the voltage detecting circuits; and a control device controlling charge and discharge of the battery cells on a basis of detection information obtained from the voltage detecting circuits, a voltage detecting line having a lowest potential being connected to one of the voltage detecting circuits and a voltage detecting line having a highest potential being connected to the other of the voltage detecting circuits, being adjacent and connected to each other via a first capacitor.
US09673640B2 Battery system monitoring apparatus and electric storage device including the same for balancing a plurality of battery cells by discharging them based on voltage dependent turn-on resistance adapting of the balancing switch
A battery system monitoring apparatus for monitoring a cell group having a plurality of battery cells, and includes a cell controller IC which monitors and controls the states of the plurality of battery cells. A battery controller controls the cell controller IC and a plurality of voltage detection lines measure the voltage across the terminals of the battery cell. The voltage detection lines connect positive and negative electrodes of the battery cell, respectively, to a plurality of voltage input terminals of the cell controller IC. A power line connects the positive electrode of the battery cell having the highest potential among the plurality of battery cells to a power supply terminal of the cell controller IC and a ground line which connects the negative electrode of the battery cell having the lowest potential among the plurality of battery cells to a ground terminal of the cell controller IC.
US09673639B2 Rechargeable battery system including controller and battery backs in daisy chain communication path
A rechargeable battery management unit (controller) controls a plurality of battery packs. A communication path connects the rechargeable battery management unit and the plurality of battery packs in a daisy chain for packet communication and representing a ring topology. The rechargeable battery management unit sends a fixed-length packet divided into segments so as to flow in one direction on the management data communication path, the number of segments being equal to or more than the number of battery packs. Each of the plurality of battery packs stores data related to the battery pack in a segment assigned to the battery pack in the fixed-length packet received from a battery pack preceding in the management data communication path and sends the fixed-length packet to a succeeding battery pack.
US09673632B1 Fluid plane in computer data center
A method for providing power to a computer data center includes distributing a fluid through a single common domain throughout the computer data center building; converting the fluid into electrical energy at a plurality of electric power generation units that are distributed through the computer data center and connected to receive fluid from the common domain; and providing electrical power from the plurality of power generation units to corresponding electrical loads distributed throughout the computer data center building.
US09673628B2 Control of a microgrid
A microgrid having a plurality of electrical phases A, B & C. The microgrid includes an energy storage connected to a first phase A and a second phase B. The microgrid also includes a first single-phase distributed generator (DG) connected to the first phase and configured for injecting power into the first phase. The microgrid also includes a second single-phase DG connected to the second phase and configured for injecting power into the second phase. The microgrid also includes a first single-phase load connected to the first phase. The microgrid also includes a second single-phase load connected to the second phase. The microgrid also includes a control system configured for controlling the microgrid such that power is redistributed from the second phase to the first phase via the energy storage.
US09673625B2 Uninterruptible power supply apparatus
An uninterruptible power supply apparatus includes a power supply unit converting AC power to generate a DC voltage to be supplied to a loading device. The uninterruptible power supply apparatus further includes a first battery unit connected to the power supply unit to receive a DC current therefrom, and stores first DC power generated from the DC voltage. The first battery unit generates a DC voltage to be supplied to the loading device from the first DC power. The uninterruptible power supply apparatus includes a second battery unit connected in parallel to the power supply unit and stores second DC power, and generates, from the second DC power stored in the second battery unit, a DC voltage to be supplied to the loading device. The uninterruptible power supply apparatus further includes a controller for controlling operation of the power supply unit, the first battery unit and the second battery unit.
US09673620B2 Energy supply network; method and aircraft or spacecraft
An energy supply network, especially for an aircraft or spacecraft, including a first coupling device, the first coupling device being configured to couple the energy supply network to an external energy source, a first high voltage direct current, HVDC, segment, the first HVDC segment being coupled to the first coupling device and a second HVDC segment, the second HVDC segment being coupled to the first coupling device. Also provided is a corresponding method and an aircraft or spacecraft incorporating such an energy supply network.
US09673616B2 Power converter, display device including power converter, system including display device, and method of driving display device
A power converter includes a voltage conversion unit that provides a first driving voltage at a first output electrode by converting a power supply voltage in response to a first control signal, the voltage conversion unit being configured to provide a second driving voltage at a second output electrode by converting the power supply voltage after a short detection period, the voltage conversion unit being configured to shut down in response to a third control signal, and a short detection unit that generates the third control signal by comparing a magnitude of a voltage of the second output electrode with a magnitude of a reference voltage during the short detection period.
US09673612B2 Reverse battery protection for battery-powered devices
Reverse battery protection circuits for devices powered by batteries coupled in parallel can include both P-channel and N-channel MOSFETs. Each positive battery terminal connector of a battery-powered device can be coupled to a gate of an N-channel MOSFET or to both a gate of an N-channel MOSFET and a gate of a P-channel MOSFET. In some embodiments, each negative battery terminal connector of the device can be connected to a gate of a P-channel MOSFET. In the event of a reverse battery connection, one or more of the protection circuit's P-channel and N-channel MOSFETS can switch to a non-conductive state to isolate the device's load from an incorrectly installed battery and prevent the incorrectly installed battery and/or other parallel-coupled battery from prematurely discharging. Methods of protecting a load from a reverse battery connection are also provided, as are other aspects.
US09673610B2 Apparatus and method for controlling adaptive reclosing based on transient stability
An apparatus and method for controlling adaptive reclosing based on transient stability of a power transmission line are disclosed. The apparatus includes a power angle calculation unit, an integral square error (ISE) second-order differential calculation unit, a stability determination unit, and a disconnection signal generation unit. The power angle calculation unit acquires the instantaneous value of a power angle based on voltage and phase angle measurement signals. The ISE second-order differential calculation unit acquires the instantaneous value of the second-order differential of the ISE of the power angle. The stability determination unit determines whether a system is stable or unstable based on the transitions in the instantaneous value of the second-order differential of the ISE. The disconnection signal generation unit generates a first disconnection signal and a second disconnection signal adapted to open or reclose the circuit breaker at the leader end and the circuit breaker at the follower end.
US09673609B2 Self-test of over-current fault detection
A system for testing over-current fault detection includes a first switch to connect a voltage to a load and a capacitor; a first monitor circuit that monitors a current from the first switch to the load; a second monitor circuit that monitors a voltage across the capacitor; and a microcontroller configured to control a state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. The microcontroller detects an over-current fault condition based upon input from the first monitor circuit and detects a short-circuit fault condition based upon input from the second monitor circuit during test of the first monitor circuit.
US09673604B2 Coaxial cable terminator assembly having a substrate with inner and outer termination connections carried by a cap
A coaxial cable terminator assembly includes an electrically insulative substrate carried by a non-conductive cap in a receiving area thereof. The substrate carries outer and inner termination connections and an electrically resistive connector that electrically connects the outer termination connection to the inner termination connection. Outer and inner contacts are electrically connected to the outer and inner termination connections, respectively. The outer and inner contacts are for electrically contacting coaxial outer and inner conductors, respectively, of the end of a coaxial cable for terminating the end of the coaxial cable, and the cap is for frictionally and non-conductively engaging the coaxial cable, when the end of the coaxial cable is inserted into the receiving area.
US09673598B2 Cover assembly for an electrical box
A cover assembly for an electrical box, such as a fire-rated poke through, includes a frame defining an opening, the frame including a first frame location and a second frame location, the first frame location being substantially opposite the second frame location, a cover movable between a closed position over the opening and an open position away from the opening, the cover having a perimeter including a proximal end and a distal end, the proximal end being substantially opposite the distal end, and a hinge attaching the cover to the rear frame portion, the hinge having two substantially parallel pivot axes, at least one of which is movable towards and away from the other, one pivot axis located at the first frame location and the other pivot axis located at the proximal end of the cover. This construction provides a cover assembly for an electrical box that allows ready access to utility interfaces within the box, while preventing unwanted fluid and debris from damaging the junction box or utility interfaces below the cover assembly.
US09673595B2 Withdrawable contactor trucks with integral motorized levering-in, related switchgear, kits and methods
Withdrawable contactor trucks for a circuit breaker have a cradle with a motorized drive system comprising an electric motor in the cradle. The motorized drive system is configured to move the contactor truck in a controlled path between a withdrawn position and a levering-in position in a switchgear compartment.
US09673591B2 Wavelength locking multimode diode lasers with fiber Bragg grating in large mode area core
According to another aspect of the present disclosed technology, a diode laser assembly, includes an optical fiber having a cladding and a large mode area (LMA) core, wherein the LMA core comprises a fiber Bragg grating disposed within the LMA core, a plurality of diode lasers configured to emit light, optics configured to receive the light and to couple the light into the LMA core, and one or more features in the optical fiber to couple higher order modes of the light leaving substantially single mode light to propagate in the LMA core wherein a portion of the single mode light propagating in the LMA core is reflected by the fiber Bragg grating and is coupled back through the optics into the plurality of diode lasers to lock the wavelength of light emitted from each diode laser of the plurality.
US09673588B1 Techniques and apparatus for managing lasing gas concentrations
Techniques and architecture are disclosed for managing alkali vapor concentration in a lasing gas at non-condensing levels. In some instances, the disclosed techniques/architecture can be used to control and/or stabilize the concentration of alkali vapor in a lasing gas volume to any desired fraction of its saturation value under dynamically changing thermal loads. In some such instances, the concentration of alkali vapor in a given lasing gas volume can be maintained at a value which is sufficiently far from the saturation point to prevent or otherwise reduce condensation of the alkali vapor, for example, upon accelerating the lasing gas through a pressure drop into an optical pumping cavity of an alkali vapor laser system (e.g., such as a diode-pumped alkali laser, or DPAL, system). In some instances, the disclosed techniques/architecture can be used to establish a temperature gradient and/or an alkali vapor concentration gradient in the flowing lasing gas volume.
US09673587B2 Automatic-robotic-cable-connector-assembly method
An automatic-robotic-system-for-cable assembly is provided. The system is configured to detect the inner-wire placement. The detected inter-wire is conveyed toward a connector's relevant pad. In addition the robotic system is configured to associate the inner wire to the connector's relevant pad.
US09673585B2 Rotary connector having a cable in a wiring space between a rotary body and a housing
Movable end portions of cables and are fixed to a movable lead block, and fixed end portions of the cables are fixed to a fixed lead block. The movable lead block is mounted so as to be inserted into a cylindrical portion of a rotary body in a direction along a rotation center line, and the fixed lead block is mounted so as to be inserted into a lead block attachment portion of a lower housing in the direction along the rotation center line. The movable end portions and the fixed end portions of the cables are positioned at the same heights as those of the cables in a wiring space.
US09673582B2 Modular housing and track assemblies for tubular lamps
A lighting system for LED lights, including a plurality of discrete extruded elements interconectable to create various housing, support and light modifiers to be used in luminaire assemblies.
US09673580B2 Electrical connector with improved contacts
An electrical connector (100) includes an insulative housing (1), a plurality of terminals (2) received in the insulative housing, and a shell (3). The insulative housing includes a base portion (11) and a tongue plate (12) extending from the base portion forwardly. The tongue plate includes a mating face (13) and a supporting face (14) opposite to the mating face. The terminals (22) include a pair of signal terminals defined in the supporting face, a grounding terminal, and a power terminal. The pair of signal terminals are defined between the grounding terminal and the power terminal. Each of the signal terminals, the grounding terminal, and the power terminal has a thickness greater than 0.2 mm. The power terminal is made of nickel and copper.
US09673578B1 Cable-mounted electrical connector
An electrical connector includes an outer contact extending along a longitudinal axis between a front end and a rear end. The outer contact has a terminating segment that extends to the rear end and is configured to engage and be surrounded by a conductive layer of a cable to electrically connect the outer contact to the cable. The terminating segment is cylindrical and defines a chamber therethrough that is configured to receive one or more wires of the cable therein. The terminating segment has a crosshatch pattern along an outer surface thereof. The crosshatch pattern includes multiple grooves extending parallel to one another and multiple cross-grooves extending parallel to one another. The cross-grooves intersect the grooves to define multiple raised panels along the outer surface.
US09673576B2 Support for various types of items
A system for managing electric devices, including a first panel having at least one hole and having a first conductive surface, a second panel integral and substantially parallel to the first panel and having a second conductive surface. The first panel is overlapped to the second panel. The system is configured in such a way that the second conductive surface has at least one portion not covered by the first panel and accessible through the, or each, hole. The first conductive surface and the second conductive surface are connected to an electric circuit in such a way that the first conductive surface has a first predetermined polarity, and the second conductive surface has a second predetermined polarity, opposite to the first predetermined polarity.
US09673569B2 Electrical connector with central grounding plate
An electrical connector comprises a housing assembly and an outer shell surrounding the housing assembly, the housing assembly comprises a first terminal module and a second terminal module; the first terminal module comprises a first body and a group of first terminals fixed to the first body, the first body has a first tongue; the second terminal module comprises a second body and a group of second terminals fixed to the second body, the second body has a second tongue; the first body and the second body oppose each other and are fixed together by at least one engagement column in the first tongue that is locked to at least one locking hole in the second tongue.
US09673562B2 Sealed plug connector
The invention concerns a plug connector for a high current device, intended to be placed in particular in the engine compartment of a motor vehicle. A device such as a printed circuit board housed in the plug connector is connected to a cable via at least one rigid conductive metal bar (bus bar). A ring is interposed between the rigid conductive metal bar and a terminal electrically connected to the cable. A bolt holds the terminal, the ring and the bus bar clamped together. To ensure the seal of the plug connector at the bolt, a first ring seal is placed between the ring and an unthreaded zone of the shank of the bolt, and a second seal is placed between the ring and the plug connector.
US09673561B2 Connector and structure for fixing connector to wiring harness
It is aimed to prevent a tape from being displaced in the case of taping a connector. In the case of fixing a connector to a wiring harness (WH) by winding a tape, upper-surface side ribs (9) extending in a direction substantially perpendicular to a winding direction of a tape (T) are formed to project on opposite end parts of the upper surface of a connector housing (1). In the case of taping, a winding width is set to be wider than the upper-surface side ribs (9). Since this causes opposite end parts of the upper-surface side ribs (9) in an extending direction to serve as parts for catching the tape (T), a situation where the tape (T) is displaced in the extending direction of the upper-surface side ribs (9) can be prevented.
US09673559B1 Electrical connector assembly having a multi-piece backshell
A backshell includes an upper shell, a lower shell and a fastener coupled to the upper shell and coupled to the lower shell to hold the upper shell and the lower shell together and resist separation of the upper shell from the lower shell. The upper shell defines a portion of a cavity of the backshell and includes a top wall and an upper shell side wall extending from the top wall to a bottom of the upper shell. The lower shell defines another portion of the cavity of the backshell. The lower shell includes a bottom wall and a lower shell side wall extending from the bottom wall to a top of the lower shell. The top of the lower shell generally mates with the bottom of the upper shell at a mating plane. The fastener extends along a longitudinal axis generally parallel to the mating plane.
US09673554B2 Aircraft rotor fitted with a connector device for connecting electrical power between a hub and blades of the rotor
The invention provides a rotary-wing aircraft rotor fitted with a connector device for connecting electrical power between a hub (1) and blades (2) of said rotor. For each of the blades (2), a wired connection (4) provides an electrical connection between the hub (1) and the blade (2). A guide path (13, 14, 15, 16, 17) holds the wired connection (4) in shape and guides it under tension to move over itself, accompanying the pivoting movement of the blade root (3).
US09673548B2 Contact connection structure
A contact connection structure includes a first terminal including a first contact portion including an indent and a second terminal including a second contact portion including a contact face that makes contact with the indent. The indent includes a first arc face having the first curvature center extending on a first line, the contact face includes a second arc face having a curvature different from the curvature of the first arc face, the second curvature center of the second arc face extending on a second line perpendicular to the first line. The first arc face and the second arc face make contact with each other by an elliptic region. The direction of one of the first line and the second line is the direction of the long axis of the elliptic region, and the direction of the other line is a direction of the short axis of the elliptic region.
US09673545B2 Printed wiring board and connector connecting the wiring board
A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The flexible printed wiring board (1) further includes reinforcement layers (31, 32) that are disposed at the other surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component, and that are formed separately from the wirings (9, 11).
US09673538B2 Connector
An electrical connector has a connector housing, a conductive contact, and a housing cover. The connector housing has a plurality of wire receiving passageways, and a plurality of elastic wire holders. The conductive contact has a plurality of wire insulation cutting blades electrically connected together, each cutting blade having a tapered tip. The housing cover is connected to the conductive contact, and together with the conductive contact, is positioned on the connector housing such that when a plurality of conductive wires are positioned in the plurality of wire receiving passageways, after the housing cover has been positioned on the connector housing, the conductive contact has pierced through an outer insulation sheath of the conductive wires and is in contact with a conductive core thereof.
US09673537B2 Wire compression connector
A compression connector for connecting two wires is disclosed. The compression connector is made of either a single bifurcated connector body or two individual connector components that are slidably coupled and then crimped. As the compression connector is crimped, structural features on the connector components are pushed into a locked state in the two component embodiment. Bifurcated embodiments allow for more than one crimping act on the compression connectors resulting in a more reliable compression connection. The compression connector that results is much more resistant to failure compared to known C-shaped compression connectors.
US09673536B2 Omnidirectional antennas, antenna systems and methods of making omnidirectional antennas
An antenna generally includes at least two feeds and at least one open side defined between the at least two feeds. A feed point is between and/or connected to the at least two feeds. The antenna also includes shorting legs for mechanical support and electrically coupling to a ground plane.
US09673535B2 Telecommunication antenna reflector for high-frequency applications in a geostationary space environment
An antenna reflector compatible with applications at high frequencies between 12 and 75 GHz and suitable for a paraboloidal or ellipsoidal geostationary space environment comprising a reflective face to focus electromagnetic radiation, comprises a superposition of at least one layer comprising a fiber composite material, the at least one layer of fiber composite material comprising angular sectors arranged around a center, each defined by a first central angle and oriented in a radial direction the median of the central angle, each of the angular sectors comprising the fiber composite material comprising first and second fibers oriented different first and second respective directions, the first direction forming a second angle with the radial direction of the angular sector. The angular sectors comprise three concentric areas: a central area, a peripheral area and an intermediate area situated between the central area and the peripheral area, the intermediate area forming a rim.
US09673533B2 Slotted waveguide antenna for near-field focalization of electromagnetic radiation
A radial slot antenna comprising a radial waveguide, which includes an upper plate, having a centroid and an edge region and provided with a plurality of radiating apertures, formed as slots in the upper plate, which develop around the centroid. The radiating apertures are arranged to form first and second radiating regions, which are distinct and radially separated by a dwell region without radiating apertures and wherein, in the first and second radiating regions, radially adjacent radiating apertures are separated from one another by a radial distance, the dwell region having a radial width greater than the radial distances of the radiating apertures in the first and second radiating regions. The slot antenna further comprises a signal feeder for supplying am electromagnetic field to assume, in the first and second radiating regions, opposite phases, so that the electromagnetic field emitted by the slot antenna can be expressed via Bessel functions.
US09673532B2 Antenna
The present invention relates to an antenna, which includes a feeding part and a radiating part. By using the feeding part and the radiating part that are perpendicular to each other and use dielectric substrates, not only a volume of a normal radiation antenna is reduced, but also a substrate integrated waveguide directly radiates energy outwards, thereby improving operating bandwidth of the antenna.
US09673530B2 Portable wireless mesh device having improved antenna system
A wireless mesh network comprising a plurality of mobile mesh devices coupled as nodes in a mesh network topology is provided herein. Generally speaking, each mobile mesh device may be a portable, self-contained unit, which does not require network or power wiring to communicate network traffic between the nodes. According to one embodiment, the mobile mesh device may include a plurality of dipole antennas, which are enclosed within the mobile mesh device and configured to forward network traffic. At least one of the dipole antennas may be a frequency adjustable end-fed dipole antenna comprising a channel selection pin, which can be adjusted up or down along the dipole axis to change a resonant frequency of the dipole antenna. A method for setting or adjusting a resonant frequency of a frequency adjustable end-fed dipole antenna is also provided herein.
US09673529B2 ISM band antenna structure for security system
An antenna (10) is provided including a generally rectangular ground element (20) having a first end and a second end. The ground element (20) includes at least one hole (30, 30′) for mounting the antenna to a support structure. A generally rectangular radiating element (12) having a third end and a fourth end if parallel to the ground element (20) and separated from the ground element (20) by a space. A bend connects the first end of the ground element (20) to the third end of the radiating element (12). A coaxial cable includes a center conductor coupled to the radiating element (12) at a feed point and an outer conductor coupled to the ground element (20). The coaxial cable acts as a feed line that couples the antenna (10) to an external transmitter or receiver.
US09673523B2 Systems and methods for interference geolocation and mitigation using a phased array receiving antenna
A method for mitigating interference using a phased array receiving antenna is provided. The method includes perturbing a first communications beam and a second communications beam received at the phased array receiving antenna to generate a first composite beam and a second composite beam, cross-correlating the first composite beam and the second composite beam, receiving communications data using the first composite beam and the second composite beam, and determining a direction of a received interference signal based on the cross-correlation of the first composite beam and the second composite beam.
US09673522B2 Systems and methods for reconfigurable faceted reflector antennas
Systems and methods are disclosed herein for a reconfigurable faceted reflector for producing a plurality of antenna patterns. The reconfigurable reflector includes a backing structure, a plurality of adjusting mechanisms mounted to the backing structure, and a plurality of reflector facets. Each of the plurality of reflector facets is coupled to a respective one of the plurality of adjusting mechanisms for adjusting the position of the reflector facet with which it is coupled. The reflector facets are arranged to produce a first antenna pattern of the plurality of antenna patterns. By adjusting the plurality of adjusting mechanisms, the position of each of the reflector facets coupled to the respective one of the plurality of adjusting mechanisms is adjusted so that the reflector facets are arranged to produce a second antenna pattern of the plurality of antenna patterns.
US09673520B2 Multi-band wireless terminals with multiple antennas along an end portion, and related multi-band antenna systems
An antenna system may include a backplate that includes an end portion. The antenna system may also include first and second antennas spaced apart from each other along the end portion of the backplate. The antenna system may additionally include a parasitic element between the first and second antennas along the end portion of the backplate.
US09673516B2 High temperature transponders
The present invention provides, in alternative embodiments, high temperature transponders that can withstand high temperature shocks and can maintain their physical and electrical characteristics following high temperature exposure, and methods of making said transponders.
US09673515B2 Wireless conformal antenna system and method of operation
A conformal antenna system comprising one or more proximate antenna elements for very reliable localized reception and transmission of radiowave energy and power particularly in frequency controlled VHF, UHF and microwave spectrum is described. The system incorporates effective angle or proximity dependent interference mitigation for conventional transmitters/receivers or master controlled constellations of wireless devices, and is suitable for temporary or permanent installation and use in a variety of outdoor and in-building locations. The antenna elements are configured and optimized for close proximity but unobtrusive positioning near the point of use on stages, in concert halls, movie studios, houses-of-worship, and convention centers, and are configured to be relatively unaffected by people or furniture in very close proximity. Methods for manufacturing and using close proximity antennas are disclosed, as are systems and methods for the generation and control of signals thereto.
US09673512B2 Antenna assembly and wireless communication device employing same
An antenna assembly includes a first radiating portion, a second radiating portion, a third radiating portion, and a switch circuit. The switch circuit is electrically connected between the second radiating portion and the third radiating portion. The switch circuit includes a plurality of branch circuit with different impedances. The first radiating portion and the second radiating portion are electrically coupled and configured to operate at a first frequency band; the first radiating portion, the third radiating portion, the switch circuit, and the second radiating portion are electrically coupled and configured to operate at a second frequency band; the switch circuit is configured to adjust a resonance mode of the antenna assembly by switching to different impedances. A wireless communication device employing the antenna assembly is also provided.
US09673511B2 Exciting dual frequency bands from an antenna component with a dual branch coupling feed
An antenna element forms a ring slot antenna comprising a first slot and second slot. The antenna element is located on a first surface of a conductive chassis that encases a body or a volume for wireless communication signals to be received or transmitted. A coupling component is located on an opposite side of the conductive chassis and behind the antenna element. The coupling component facilitates a coupling between a communication component and the antenna element as a function of the orientation and geometric shape of the coupling component to facilitate different resonant frequencies via the first and second slots of the antenna element.
US09673510B2 Antenna structure and wireless communication device using the same
An antenna structure includes a first frame, a feed end, at least one ground end, a first radiator, a first extending section, a second extending section, a coupling section, and a second radiator. The first radiator is coupled to the feed end and is parallel to the first frame. The first extending section is coupled between the feed end and first frame. The second extending section is coupled between the feed end and the first frame. The coupling section is coupled to the first frame. The second radiator is coupled between the at least one ground end and the first frame.
US09673509B2 Antenna module for portable terminal and portable terminal comprising same
Provided are an antenna module for a portable terminal and a portable terminal including the same, wherein a slot is formed on a base sheet on which an NFC antenna and a wireless charging antenna are stacked, thereby minimizing a height difference between the NFC antenna and the wireless charging antenna. The provided antenna module for a portable terminal enables the NFC antenna and the wireless charging antenna to be stacked on an upper side of the base sheet having the slot, wherein opposite ends of the wireless charging antenna pass under a lower end of the NFC antenna while passing through the slot of the base sheet, and are connected to a power supply terminal of a portable terminal.
US09673507B2 Chassis-excited antenna apparatus and methods
A chassis-excited antenna apparatus, and methods of tuning and utilizing the same. In one embodiment, a distributed loop antenna configuration is used within a handheld mobile device (e.g., cellular telephone). The antenna comprises two radiating elements: one configured to operate in a high-frequency band, and the other in a low-frequency band. The two antenna elements are disposed on different side surfaces of the metal chassis of the portable device; e.g., on the opposing sides of the device enclosure. Each antenna component comprises a radiator and an insulating cover. The radiator is coupled to a device feed via a feed conductor and a ground point. A portion of the feed conductor is disposed with the radiator to facilitate forming of the coupled loop resonator structure.
US09673499B2 Notch filter with arrow-shaped embedded open-circuited stub
A notch filter includes a dielectric substrate; and a microstrip transmission line provided on the dielectric substrate and having an arrow-shaped embedded open-circuited stub.
US09673498B2 High frequency filter
In a high frequency filter, a multilayer structure includes a plurality of insulator layers, a first transmission line transmits an input signal, and a second transmission line is electromagnetic coupled with the first transmission line on the same insulator layer and transmits an output signal. A conductor layer defines capacitors with the first transmission line and the second transmission line with the insulator layer in between. A dielectric constant of the insulator layer that comes in contact with the first transmission line and the second transmission line is higher than a dielectric constant of an insulator layer other than the insulator layer.
US09673496B2 Signal transmission line
A signal transmission line is disclosed. The signal transmission line includes a dielectric substrate, a signal line formed on a first surface of the dielectric substrate, a first conductive layer formed on a second surface of the dielectric substrate, and a first stub formed on the first surface of the dielectric substrate, the first stub being electrically connected with the signal line. The first stub includes a plurality of straight areas each extending from a different position of the signal line, a conductor part extending in parallel with the signal line, the conductor part being electrically connected with straight areas, a projection part connected with the conductor part, the projection part extending from the conductor part, and an opening provided between the conductor part and the signal line.
US09673495B2 Battery module assembly having coolant flow channel
Disclosed herein is a battery module assembly including unit modules, each of which includes unit cells mounted to a cartridge in a state of being electrically connected to each other via bus bars, the battery module assembly including two or more sub-modules, each of which includes two or more unit modules vertically stacked from a ground to form a coolant flow channel at an interface therebetween, the unit modules being arranged in a lateral direction in a state of being spaced apart from each other to provide the coolant flow channel, and a module case, in which the sub-modules are received and fixed, the module case having a coolant inlet port, through which a coolant is introduced into the module case, and a cool outlet port, through which the coolant is discharged out of the module case, wherein the coolant flow channel is configured to have a structure in which a vertical sectional area of the coolant flow channel decreases toward the coolant outlet port.
US09673489B2 Battery pack
A battery pack includes at least one battery cell, a protection circuit module electrically connected to the at least one battery cell, and a frame including the at least one battery cell and the protection circuit module. The battery pack also includes a label adjacent to the at least one battery cell, protection circuit module, and frame. The label includes a noise preventing portion in a direction different from a lengthwise direction of the frame.
US09673481B2 Thin film solid state lithium ion secondary battery and method of manufacturing the same
In one embodiment, a thin film solid state lithium ion secondary battery is able to be charged and discharged in the air and manufactured stably at a favorable yield. The thin film solid state lithium ion secondary battery has an electric insulating substrate formed from an organic resin, an inorganic insulating film provided on the substrate face, a cathode-side current collector film, a cathode active material film, a solid electrolyte film, an anode potential formation layer, and an anode-side current collector film. The cathode-side current collector film and/or the anode-side current collector film is formed on the inorganic insulating film face. The anode potential formation layer is a layer formed from the same material as that of the cathode active material film or a material different from that of the cathode active material film and is a layer provided for forming anode potential at the time of discharge.
US09673480B2 Binder for an electrode of an electrochemical system, electrode comprising this binder, and electrochemical system comprising this electrode
Binder for an electrode of an electrochemical system having a non-aqueous electrolyte, said binder comprising a first polymer which has functional groups capable of reacting with a crosslinking agent and is crosslinked with said crosslinking agent, the crosslinked first polymer forming a three-dimensional network in which a second polymer chosen from fluoropolymers is imprisoned.
US09673474B2 Battery cell stack and redox flow battery
Provided is a battery cell stack in which the electrical resistance between a current collector plate and an end bipolar plate is unlikely to increase when charging and discharging are repeated. A battery cell stack includes a current collector plate electrically connected to each of a pair of end bipolar plates located at both ends in the stacking direction. In the battery cell stack, two members in contact with each other between the current collector plate and the end bipolar plate are made of materials such that, when an accelerated test satisfying the following conditions 1 to 3 is performed, the electrical resistance value between the current collector plate and the end bipolar plate after the accelerated test is 1.05 times or less the electrical resistance value between the current collector plate and the end bipolar plate before the accelerated test: Condition 1 is that a cycle includes applying pressure over one minute to achieve a predetermined pressure, maintaining the predetermined pressure for one minute, and bringing the predetermined pressure back to the atmospheric pressure over one minute; Condition 2 is that the predetermined pressure is set to be the atmospheric pressure +0.1 MPa; and Condition 3 is that the number of cycles is set to 18.
US09673463B2 Control arrangement and method in fuel cell system
A control arrangement in a fuel cell system for producing electricity with fuel cells, the fuel cell system including means for recirculating fuel through the anode sides of the fuel cells, and at least one system controller in a control processor for controlling the operation of the fuel cell system. The control arrangement includes means for performing a substantially asynchronous chemical reaction rates calculation process of at least one of fuel composition and fuel flow rate to accomplish information in a substantially iterative process on at least recirculation ratio of the fuel recirculation through anodes and means for generating, in a substantially synchronous process with the system controller process, fuel utilization (FU) information and Carbon formation information by utilizing the latest available recirculation ratio information provided by said asynchronous process.
US09673462B2 Fuel cell-vehicle communications systems and methods
A method for operating a fuel cell system includes electrically coupling a fuel cell stack to an energy storage device and an electrical demand by a load device. A controller is coupled to the fuel cell stack, the energy storage device, and the load device via a communications connection. The controller obtains information relative to an operation of at least one of the fuel cell stack and the energy storage device and the controller controls an operation of the load device based on the information.
US09673460B2 Fuel cell system, use of a fuel cell system and aircraft with a fuel cell system
A fuel cell system includes a fuel cell having a housing that encases the fuel cell, a supply line for a fuel cell fuel, and an exhaust gas line for fuel-cell exhaust gas. In this arrangement the supply line extends in the exhaust gas line, and the exhaust gas line encases the supply line while forming a space. Any leakage in the supply line thus results in the fuel being flushed out by means of the exhaust gases flowing in the exhaust gas line so that higher system reliability and a reduction in costs can be achieved.
US09673457B2 Interconnect and end plate design for fuel cell stack
Various embodiments include interconnects and/or end plates having features for reducing stress in a fuel cell stack. In embodiments, an interconnect/end plate may have a window seal area that is recessed relative to the flow field to indirectly reduce stress induced by an interface seal. Other features may include a thicker protective coating and/or larger uncoated area of an end plate, providing a recessed portion on an end plate for an interface seal, and/or recessing the fuel hole region of an interconnect relative to the flow field to reduce stress on the fuel cell. Further embodiments include providing intermittent seal support to minimize asymmetric seal loading and/or a non-circular seal configuration to reduce stress around the fuel hole of a fuel cell.
US09673455B2 Lithium-ion secondary battery
A lithium-ion secondary battery has an electrode sheet having a current collecting foil formed thereon with a mixture layer containing powdered mixture particles. On the current collecting foil, there are provided a binder coated section on which a binder layer is formed having patterned markings; and a binder non-coated section on which a binder layer is not formed. The mixture particles contain at least an electrode active material and a binder. The mixture layer is formed on the binder coated section and the binder non-coated section.
US09673451B2 Lithium ion secondary battery and method for manufacturing the same
A lithium ion secondary battery includes a positive electrode, a negative electrode, and an electrolyte provided between the positive electrode and the negative electrode. The positive electrode includes a positive electrode current collector and a positive electrode active material layer over the positive electrode current collector. The positive electrode active material layer includes a plurality of lithium-containing composite oxides each of which is expressed by LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) that is a general formula. The lithium-containing composite oxide is a flat single crystal particle in which the length in the b-axis direction is shorter than each of the lengths in the a-axis direction and the c-axis direction. The lithium-containing composite oxide is provided over the positive electrode current collector so that the b-axis of the single crystal particle intersects with the surface of the positive electrode current collector.
US09673450B2 Lithium ion battery
A lithium ion battery that has a spinel cathode and a nonaqueous electrolyte comprising a fluorinated acyclic carboxylic acid ester and/or a fluorinated acyclic carbonate solvent is described. The lithium ion battery operates at a high voltage (i.e. up to about 5 V) and has improved cycling performance at high temperature.
US09673447B2 Method of operating a lithium-ion cell having a high-capacity cathode
A method of operating a lithium-ion cell comprising (a) a cathode comprising a carbon or graphitic material having a surface area to capture and store lithium thereon; (b) an anode comprising an anode active material; (c) a porous separator disposed between the two electrodes; (d) an electrolyte in ionic contact with the two electrodes; and (e) a lithium source disposed in at least one of the two electrodes to obtain an open circuit voltage (OCV) from 0.5 volts to 2.8 volts when the cell is made; wherein the method comprises: (A) electrochemically forming the cell from the OCV to either a first lower voltage limit (LVL) or a first upper voltage limit (UVL), wherein the first LVL is no lower than 0.1 volts and the first UVL is no higher than 4.6 volts; and (B) cycling the cell between a second LVL and a second UVL.
US09673446B2 Lithium ion secondary battery containing a negative electrode material layer containing Si and O as constituent elements
A lithium ion secondary battery containing a negative electrode active material containing Si and O as constituent elements and exhibiting excellent charge-discharge cycle characteristics. The lithium ion secondary battery has a positive electrode having a positive electrode material mixture layer, a negative electrode, a separator and a nonaqueous electrolyte containing at least an electrolyte salt and an organic solvent, where the negative electrode has a negative electrode material mixture layer containing a negative electrode active material containing Si and O as constituent elements (the atomic ratio x of O to Si is 0.5≦x≦1.5). The nonaqueous electrolyte contains the electrolyte salt at a concentration exceeding a concentration at which conductivity in the nonaqueous electrolyte containing the electrolyte salt and the organic solvent is maximized, and the conductivity at 25° C. is 6.5 to 16 mS/cm.
US09673441B2 Connection pole for an accumulator, pole shaft of an accumulator, and accumulator
A connection pole for an accumulator, wherein the connection pole includes an inner hollow region configured to receive a pole shaft of the accumulator. The connection pole includes ribs on its inner wall in the inner hollow region, wherein the ribs run in the longitudinal direction of the connection pole and one or more or all of the ribs are integrally formed with the connection pole from the material of the connection pole and protrude from the inner side of the connection pole such that the ribs form a gap between the pole shaft and the inner surface of the connection pole.
US09673435B2 Nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery 100 according to the present invention is provided with an electrode assembly 80 having a structure in which a positive electrode 10 and a negative electrode 20 are stacked with a separator 30 interposed therebetween. A porous filler layer 32 is formed between the positive electrode 10 and the separator 30. The filler layer 32 contains a filler made of an inorganic material and contains a binder. The relationship T>D holds where T is the average thickness of the filler layer 32 and D is the average particle diameter of a positive electrode active material 15 present in the positive electrode 10 facing the filler layer 32, and a pressure applied to the electrode assembly 80 in the stacking direction is set to at least 0.1 MPa.
US09673432B2 Battery case and electric skateboard using same
A battery case includes a bottom plate part and two side plate parts extending oppositely from the bottom plate part, wherein each of the side plate parts has at least one opening, in which an elastic element is arranged. An electric skateboard includes a bearing deck, wheels mounted on both ends of the bearing deck, an electric motor mounted under the bearing deck, and said battery case which is mounted under the bearing deck. The side plate parts of the battery case have openings in which elastic elements are arranged. Therefore, when pressure is exerted by the bearing deck to the battery case, the opening of the battery case is able to squeeze the elastic element so that the battery case can undergo an elastic deformation easily.
US09673431B2 Battery having a brick architecture including cells arranged in series or in parallel
Battery comprising several cells disposed in several modules (112) linked together in series, characterized in that it comprises at least one brick (120) comprising a lower terminal and an upper terminal, between which are arranged two cells (111) and at least three switches (113), so as to be able to dispose the two cells (111) in series or in parallel between the two terminals and in that the battery comprises a control circuit (127) for the switches (113) of the said at least one brick.
US09673428B2 Non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery is provided, including a battery element having a positive electrode, a negative electrode and a separator; an exterior member for the battery element including: a first layer; a second layer; a bending part for partitioning the first layer and the second layer from each other; a sealing part which is formed by a peripheral part of the first layer in contact with a peripheral part of the second layer and which seals the battery element; a thick-walled part that is a portion of the sealing part and includes at least a part of the bending part, wherein the thick-walled part has a greater thickness in a thickness direction of the battery element than a thickness of a portion of the sealing part other than the thick-walled part, and wherein the thickness direction of the battery element corresponds to a stacking direction of the battery element.
US09673421B2 OLED display and manufacturing method thereof
An organic light-emitting diode (OLED) display and a manufacturing method thereof are provided. The OLED display includes a plurality of sub-pixel units each including a first region and a second region. The first region includes a first electrode, a first organic material functional layer and a second electrode disposed in order on a base substrate. The second region includes a third electrode, a second organic material functional layer and a fourth electrode disposed in order on the base substrate. The first electrode and the third electrode each include an opaque metal layer, and the second electrode and the fourth electrode are translucent metal electrodes. The first electrode, the first organic material functional layer and the second electrode constitute a first micro-cavity, the third electrode, the second organic material functional layer and the fourth electrode constitute a second micro-cavity, and the first micro-cavity and the second micro-cavity have different micro-cavity effects.
US09673420B2 Organic electroluminescent device, illumination apparatus, and illumination system
An organic electroluminescent device includes a first electrode, an insulating layer, an organic light emitting layer, a second electrode, and a light transmissive part. The first electrode has an upper face. The insulating layer is provided on the upper face. The insulating layer includes first to fifth insulating parts. The organic light emitting layer is provided on the upper face in between the insulating parts. The second electrode is provided on the organic light emitting layer. The light transmissive part overlaps the first region of the first electrode when projected onto the plane. The light transmissive part makes a phase of a first light permeating the first region to be different from a phase of a second light permeating the second region of the first electrode.
US09673419B2 Display device and manufacturing method thereof
Provide is a display device that prevents adverse effects on pixel circuits, resulting from a process related to a sealing film, and a manufacturing method of the display device. A display device includes pixel circuits on a substrate and a sealing film having a multilayer structure on the pixel circuits. The sealing film includes a first layer being formed in contact with the pixel circuits and being made of a silicon-containing inorganic material. The first layer is a mixed film containing at least one component changing seamlessly in a stacking direction.
US09673418B2 Display device
Provided is a display device including a display panel configured to display an image, and a window panel located on the display panel, the window panel having a display area for transmitting an image displayed on the display panel, and a non-display area surrounding the display area, wherein the window panel includes a window substrate, and a print layer on a lower surface of the window substrate in the non-display area, and including a silicon-based polymer or a fluorine-based polymer.
US09673415B2 Blue light organic light-emitting diode and display including same
The present disclosure provides a blue light organic light-emitting diode, which includes a first electrode layer; a first hole injection layer disposed on the first electrode layer; a second hole injection layer disposed on first hole injection layer; a hole transport layer disposed on the second hole injection layer; a blue light emitting material layer disposed on the hole transport layer; an electron transport layer disposed on the blue light emitting material layer; and a second electrode layer disposed on the electron transport layer, wherein the second hole injection layer has a thickness of 85 nm˜105 nm. The present disclosure further provides a display including the device. The blue light organic light-emitting diode of the present disclosure can control blue light energy components having a wavelength less than 435 nm within 0.2%, which reduces the harm of the blue light in the wave band to human eyes to a great extent.
US09673414B2 Organic light-emitting diode and method for preparing the same
An organic light-emitting diode and a method for preparing the same are disclosed. The organic light-emitting diode at least comprises a luminescent layer between an anode and a cathode, and the organic light-emitting diode further comprises at least two electron transport layers set between the luminescent layer and the cathode and an N-type doped layer set between every two adjacent electron transport layers. For the organic light-emitting diode of the invention, an electron transport material and an N-type dopant are sequentially evaporated in turn, and the electron injection and transportation capacity is improved by forming an N-type doping-like effect from interface dope effect and the diffusion of an N-type dopant, so that carrier concentration can be balanced, exciton utilization can be improved, and the photoelectric properties of the OLED device can be improved.
US09673412B2 System and method for matching electrode resistances in OLED light panels
Provided are an OLED device and a method of manufacturing the OLED device that may provide improved luminance uniformity. The disclosed OLED may have a first electrode that has a first sheet resistance Rs, and a second electrode that has a second sheet resistance, wherein the second sheet resistance may be in the range of 0.3 Rs-1.3 Rs. In addition, the disclosed OLED may have a plurality of equal potential difference between points on a first electrode and a second electrode. The equal potential difference may be provided by a gradient resistance formed on at least one of the electrodes.
US09673410B2 Deposition apparatus, method thereof and method for forming quantum-dot layer using the same
A deposition apparatus includes a first nozzle configured to spray a first deposition material toward a substrate and a second nozzle configured to spray a second deposition material, a first deposition source configured to supply the first deposition material to the first nozzle and a second deposition source configured to supply the second deposition material to the second nozzle. The deposition apparatus further includes a barrier member disposed between the first nozzle and the second nozzle and is configured to block the first deposition material evaporated through the first nozzle from being mixed with the second deposition material evaporated through the second nozzle and a vacuum chamber configured to surround the first and second nozzles, the first and second deposition sources and the barrier member.
US09673409B2 Phosphorescent tetradentate metal complexes having modified emission spectra
Multidentate metal complexes useful as phosphorescent emitters in display and lighting applications having the following structures:
US09673408B2 Luminescent diazabenzimidazole carbene metal complexes
The present invention relates to metal-carbene complexes of the general formula (I), where variable M is Ir or Pt and that are characterized by variable R being a group of formula (a). The complexes are used in organic electronic devices, especially OLEDs (Organic Light-Emitting Diodes), illuminating elements, stationary visual display units and in material layers as emitter, charge transport material and/or charge or exiton blocker.
US09673403B2 Heterocyclic compound and organic light emitting device using the same
The present specification provides a heterocyclic compound, and an organic light emitting device including: a first electrode, a second electrode, and organic material layers formed of one or more layers including a light emitting layer disposed between the first electrode and the second electrode, in which one or more layers of the organic material layers include the heterocyclic compound or a compound in which a heat-curable or photo-curable functional group is introduced into the heterocyclic compound.
US09673399B2 Floating evaporative assembly of aligned carbon nanotubes
High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (FETs) that incorporate the films as conducting channel materials. The single-walled carbon nanotubes are deposited from a thin layer of organic solvent containing solubilized single-walled carbon nanotubes that is continuously supplied to the surface of an aqueous medium, inducing evaporative self-assembly upon contacting a solid substrate.
US09673398B2 Difluorothienothiophene based conjugated polymers
A polymer having a monomer repeat unit comprising wherein Ar is an aryl group.
US09673395B2 Apparatus and method for forming organic thin film and manufacturing method of organic thin film device using the same
Provided is an organic thin film forming apparatus, an organic thin film forming method, and a method of manufacturing an organic thin film device using the same, in which an organic light-emitting layer (photoactive layer) and/or an electron transport layer can be formed on a substrate when an organic light emitting diode (OLED) or an organic solar cell is manufactured. The organic thin film forming apparatus includes: a solution spray unit for spraying a solution on a substrate; and a hot gas spray unit for spraying a hot gas onto fine liquid droplets that have been sprayed from the solution spray unit and that are in flight, to thereby evaporate a solvent contained in the fine liquid droplets.
US09673392B2 Phase change material switch and method of making the same
A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element.
US09673389B2 Memory device
According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.
US09673388B2 Integrated circuit structures with spin torque transfer magnetic random access memory and methods for fabricating the same
A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.
US09673383B2 Multilayer ceramic electronic component and method of manufacturing the same
There is provided a multilayer ceramic electronic component including: a ceramic body in which internal electrodes containing a first electrode material and dielectric layers are alternately disposed; external electrodes provided on outer surfaces of the ceramic body and containing a second electrode material; and diffusion parts each disposed to be connected to one end of the internal electrode and the external electrode and containing the first electrode material and the second electrode material mixed with each other, wherein the diffusion part includes an internal diffusion portion disposed within the ceramic body and an external diffusion portion protruding outside of the ceramic body.
US09673379B2 Piezoelectric material, piezoelectric element, and electronic device
A piezoelectric material that does not contain lead and has excellent piezoelectric constant and mechanical quality factor in a device driving temperature range (−30° C. to 50° C.) is provided. A piezoelectric material includes a main component containing a perovskite metal oxide represented by following general formula (1), and a first auxiliary component containing Mn, wherein an amount of the contained Mn is 0.002 moles or more and 0.015 moles or less relative to 1 mole of the metal oxide. (Ba1-yBiy)a(Ti1-x-zZrxFez)O3  (1) (where 0.010≦x≦0.060, 0.001≦y≦0.015, 0.001≦z≦0.015, 0.950≦y/z≦1.050, and 0.986≦a≦1.020).
US09673374B2 Cost-effective single crystal multi-stake actuator and method of manufacture
This invention pertains to piezoelectric actuators made of single crystal active elements which not only exhibit uniform and superior displacement in the axial direction but also of lower cost to produce than full single crystal ring or tube actuators. Said multi-stake actuator is made up of multiple longitudinal (d33) or transverse (d3i or d32) mode piezoelectric single crystal active elements, bonded together by epoxy with the aid of shaped edge- and top and bottom washer-stiffeners which are configured to suit various application needs.
US09673372B2 Actuator device and manufacturing method for actuator device
An actuator device and a manufacturing method for the actuator device with which an outer electrode electrically connected to an inner electrode can be reliably formed even when using a film made of an electrostrictive material. An actuator device includes a plurality of stacked electrostrictive films each of which is made of an electrostrictive material and includes inner electrodes formed on one surface or both surfaces of the film. Lead electrodes are formed to be led out respectively from the inner electrodes toward the outside of the electrostrictive film 31. At least one cut portion is formed in each of the lead electrodes, and conductive ink is applied to the cut portion. The conductive ink reaches, from the cut portions, the lead electrodes formed on the electrostrictive film.
US09673371B2 Anisotropically elongated thermoelectric material, process for preparing the same, and device comprising the material
An anisotropically elongated thermoelectric nanocomposite includes a thermoelectric material.
US09673368B2 Light emitting device having first and second electrodes on one side of a light emitting structure
A light emitting device having an enhanced surface property and an electrical property is provided. The light emitting device includes a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode disposed on one side of the light emitting structure and electrically connected to the first semiconductor layer, a second electrode disposed on one side of the light emitting structure and electrically connected to the second semiconductor layer, and an ohmic contact including a first layer disposed between the second electrode and the second semiconductor layer and having aluminum (Al), a second layer including at least one MxAly alloy formed by a reaction with Al included in the first layer, and a third layer disposed on the second layer and having gold (Au) is provided.
US09673367B2 Substrate for mounting chip and chip package
A chip mounting substrate including a plurality of conductive portions to apply an electrode voltage to a mounted chip having electrode portions, at least one insulation portion configured to electrically isolate conductive portions, a cavity depressed inward of the conductive portions and providing a space in which the chip is mounted and bumps formed on surfaces of the conductive portions having the cavity and bonded to the electrode portions. In the case of a metal substrate, a tight bonding is enabled between the chip and the substrate by bonding a plating layer formed on the electrode portions of the chip using bumps formed on the metal substrate.
US09673365B2 Optoelectronic component and electronic device having an optoelectronic component
An electronic device includes a printed circuit board having a cutout, wherein an optoelectronic component including a housing having an outer surface, the housing has a chip receptacle space at a top side, an optoelectronic semiconductor chip is arranged in the chip receptacle space, the housing has a first soldering contact surface and a second soldering contact surface, the first soldering contact surface and the second soldering contact surface face in the same spatial direction as the outer surface, and the first soldering contact surface and the second soldering contact surface are set back relative to the outer surface, is arranged in the cutout.
US09673356B2 Packaging device and packaging method
The present invention discloses a packaging device and a packaging method and relates to a field of manufacturing technique of a display panel. The packaging device is used to package a display panel, the display panel comprising a first substrate and a second substrate that are arranged opposed to each other and are able to be packaged by a sealing material, the packaging device comprising a first adsorption part and a second adsorption part that are able to attract each other through a magnetic force, one of the first adsorption part and the second adsorption part configured to be detachably arranged on the outside of the first substrate, and the other of the first adsorption part and the second adsorption part configured to be detachably arranged on the outside of the second substrate.
US09673355B2 Light emitting diode having electrode pads
A light-emitting diode includes at least two light emitting cells disposed on a substrate and spaced apart from each other, wherein each of the at least two light emitting cells includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. Each of the at least two light emitting cells includes a cathode disposed on the first conductivity-type semiconductor layer, an anode disposed on the second conductivity-type semiconductor layer, and the cathode of a first light emitting cell of the at least two light emitting cells is electrically connected in series to the anode of a second light emitting cell of the at least two light emitting cells adjacent to the first light emitting cell by an interconnecting section.
US09673354B2 Light emitting device
Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer, a first electrode electrically connected with the first conductive semiconductor layer, a mirror layer under the light emitting structure, a window semiconductor layer between the mirror layer and the light emitting structure, a reflective layer under the mirror layer, a conductive contact layer between the reflective layer and the window semiconductor layer and in contact with the second conductive semiconductor layer, and a conductive support substrate under the reflective layer. The window semiconductor layer includes a C-doped P-based semiconductor doped with a higher dopant concentration. The conductive contact layer includes material different from that of the mirror layer with a thickness thinner than that of the window semiconductor layer.
US09673351B2 Method of manufacturing semiconductor chips
A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.
US09673343B2 Transducer to convert optical energy to electrical energy
A transducer to convert optical energy to electrical energy. The transducer or photo-transducer has a base layer which has a group of connecting elements formed therein at separations which are increasing with the distance away from an emitter layer formed atop the base layer. The connecting elements separate and electrically connect the base layer into base segments, the base segments having increasing thicknesses with the distance away from the emitter layer. The photo-transducer generates an output voltage that is greater than the input light photovoltage. The photo-transducer output voltage is proportional to the number of connecting elements formed in the base layer.
US09673342B2 Textured silicon substrate and method
A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.
US09673341B2 Photovoltaic devices with fine-line metallization and methods for manufacture
A method for use in forming a photovoltaic device includes forming a doped semiconductor layer on a surface of a semiconductor substrate and forming a metal film on the doped semiconductor layer. A patterned etched resist is formed on the metal film and a dielectric layer is formed on the doped semiconductor layer and the etched resist. A laser having a wavelength absorbable by the patterned etch resist is applied through the dielectric layer to the patterned etch resist to remove the patterned etch resist.
US09673337B2 Semiconductor device
An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
US09673332B2 Circuit substrate manufacturing method
A method of manufacturing a circuit substrate comprising a semiconductor element disposed on a transparent substrate, includes: forming an island-shaped oxide semiconductor layer on the transparent substrate; forming a patterned etch-stop layer made of an insulating material so as to cover at least a center portion of the island-shaped oxide semiconductor layer; depositing a conductive layer over an entire surface of the transparent substrate including a region over the patterned etch-stop layer; forming a patterned resist on the conductive layer; and etching the conductive layer using the patterned resist as a mask to form a patterned conductive layer from the conductive layer, wherein the patterned conductive layer includes a source electrode, a source wiring line, and a drain electrode, and continuing to etch the island-shaped oxide semiconductor thereunder using the patterned conductive layer and the patterned etch-stop layer as a mask to form a cutout in the island-shaped oxide semiconductor layer.
US09673331B2 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
US09673327B2 Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
US09673316B1 Vertical semiconductor device having frontside interconnections
A semiconductor device including a VDMOS device formed therein includes a terminal, or contact, to the drain region of the VDMOS device from the frontside of the device. In one or more implementations, a semiconductor device includes a semiconductor substrate having a first surface and a second surface and a vertical diffused metal-oxide-semiconductor device formed within the semiconductor substrate. The vertical diffused metal-oxide-semiconductor device includes at least one source region formed proximate to the first surface and at least one drain region formed proximate to the second surface. A through-substrate via is formed within the semiconductor substrate, and the through-substrate via electrically connected to the drain region. The through-substrate via provides an electrical interconnection to the drain region from the first surface.
US09673315B2 Semiconductor device, inverter circuit, driving device, vehicle, and elevator
A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than ½ of the first area density.
US09673310B2 Direct drive LED driver and offline charge pump and method therefor
In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is “pumped” from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.
US09673303B2 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a fabrication method thereof. The semiconductor device may include a fin-shaped active pattern and a gate electrode provided on a substrate, first and second spacers provided on a sidewall of the gate electrode, impurity regions provided at both sides of the gate electrode, a contact plug electrically connected to one of the impurity regions, and a third spacer enclosing the contact plug and having a top surface positioned at substantially the same level as a top surface of the contact plug.
US09673301B1 Methods of forming spacers on FinFET devices
One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.
US09673300B2 Semiconductor devices including a gate core and a fin active core and methods of fabricating the same
Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.
US09673297B2 Vertical power MOSFET and methods of forming the same
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.
US09673295B2 Contact resistance optimization via EPI growth engineering
A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.
US09673292B2 Semiconductor device having modified profile metal gate
A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
US09673290B2 Self-aligned source and drain regions for semiconductor devices
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
US09673289B2 Dual oxide trench gate power MOSFET using oxide filled trench
A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.
US09673286B2 Group III-V transistor with semiconductor field plate
There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer.
US09673276B2 Semiconductor device and method of fabricating the same
A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.
US09673275B2 Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits
Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).
US09673273B2 High breakdown n-type buried layer
A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.
US09673270B2 Metal insulator metal capacitor and method for making the same
A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes.
US09673266B2 OLED pixel structure and method for manufacturing the same, OLED display panel and OLED display device
Embodiments of the present disclosure relate to an OLED pixel structure and a method for manufacturing the same, an OLED display panel having the OLED pixel structure, and an OLED display device having the OLED display panel. An OLED pixel structure comprises a plurality of sub-pixel units. Each of said sub-pixel units comprises: a first electrode, an organic material functional layer and a second electrode arranged in that order on said substrate plate; and an intermediate layer arranged between said substrate plate and said first electrode; wherein, a surface of said intermediate layer away from said substrate plate has a recess of arc shape; and said first electrode is located within said recess such that said first electrode, said organic material functional layer and said second electrode each has an arc shape corresponding to the arc shape of said recess. With these technical solutions according to the present disclosure, these problems of the narrow angle of view, and of different strengths and colors of the light as being viewed from different viewing angles, can be alleviated.
US09673262B2 COA substrate, display device and method for manufacturing COA substrate
The present disclosure provides a COA substrate, a display device and a method for manufacturing the COA substrate. The COA substrate includes a base substrate, a TFT array arranged on the base substrate, a protective layer covering the TFT array, and a color filter including a color pixel and a white pixel, wherein the white pixel is made of a photoresist material.
US09673258B2 Organic pixels including organic photodiode, manufacturing methods thereof, and apparatuses including the same
Provided is an organic pixel, which includes a semiconductor substrate including a pixel circuit, an interconnection layer having a first contact and a first electrode formed on a semiconductor substrate, and an organic photo-diode formed on the interconnection layer. For example, the organic photo-diode includes an insulation layer formed on the first electrode, a second electrode and a photo-electric conversion region formed between the first contact, the insulation layer and the second electrode. The photo-electric conversion region includes an electron donating organic material and an electron accepting organic material. The organic photo-diode may further include a second contact electrically connected to the first contact. The horizontal distance between the second contacts and the insulation layer may be less than or equal to a few micrometers, for example, 10 micrometers.
US09673256B2 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
US09673255B2 Resistive memory device and fabrication methods
A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
US09673254B2 Light emitting device
Disclosed is a light emitting device comprising a plurality of light emitting cells, and a bridge electrode electrically connecting two adjacent light emitting cells, and the plurality of light emitting cells comprise a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode on the first conductive semiconductor layer and a second electrode on the second conductive semiconductor layer, wherein the bridge electrode has a part thicker than the first electrode and the second electrode.
US09673251B2 Solid-state imaging device, method for manufacturing solid-state imaging device, and imaging apparatus
A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.
US09673250B2 Shallow trench textured regions and associated methods
Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
US09673249B2 Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device
A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.
US09673246B2 Dual metal for a backside package of backside illuminated image sensor
A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer.
US09673245B2 Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.
US09673240B2 Low cross-talk for small pixel barrier detectors
Methods and structures of barrier detectors are described. The structure may include an absorber that is at least partially reticulated. The at least partially reticulated absorber may also include an integrated electricity conductivity structure. The structure may include at least two contact regions isolated from one another. The structure may further include a barrier layer disposed between the absorber and at least two contact regions.
US09673239B1 Image sensor device and method
A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.
US09673236B2 Pixel array of an image sensor and image sensor
A pixel array of an image sensor includes a substrate, a chromatic pixel including a first photodiode formed in the substrate and a color filter formed over the first photodiode, and an achromatic pixel including a second photodiode formed in the substrate, the second photodiode having a nano pillar pattern at a surface region of the substrate.
US09673234B2 Semiconductor device
A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The semiconductor device includes first to third transistors with different device structures over one substrate. A semiconductor layer of the first transistor is an oxide semiconductor film with a stacked-layer structure, and a semiconductor layer of each of the second and third transistors is an oxide semiconductor film with a single-layer structure. Each of the first and second transistors includes a back gate electrode connected to its gate electrode.
US09673226B2 Thin film transistor array substrate, display panel and display device
A thin film transistor array substrate for a display device generally includes: a substrate; a plurality of gate lines and a plurality of data lines arranged on the substrate intersecting with and insulated from each other; and a plurality of pixel elements arranged in areas defined by the gate lines and the data lines. At least one of the pixel elements includes: a switch element; an insulation layer located on the switch element; and a pixel electrode located at the insulation layer. The insulation layers of the pixel elements define a plurality of vias. The pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through a common via defined by the insulation layers of the two adjacent pixel elements. The two adjacent pixel elements are disposed along extensions of the plurality of the gate lines.
US09673223B2 Electroluminescence display device
Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
US09673222B2 Fin isolation structures facilitating different fin isolation schemes
Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.
US09673217B1 Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
US09673213B1 Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof
A method of manufacturing a structure includes forming an in-process alternating stack including insulating layers and spacer material layers over a substrate, forming two sets of stepped surfaces by dividing the in-process alternating stack into a first alternating stack and a second alternating stack, the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack, each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers while leaving intact portions of the insulating layers in the second alternating stack, and forming a contact via structure through the second alternating stack to contact a peripheral semiconductor device under the second stack.
US09673212B2 Semiconductor device and method of manufacturing the same
A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.
US09673210B1 Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof
A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.
US09673209B2 Memory device and method for fabricating the same
A device comprises a nanowire over a substrate, wherein the nanowire comprises a first drain/source region over the substrate, a channel region over the first drain/source region and a second drain/source region over the channel region, a high-k dielectric layer and a control gate layer surrounding a lower portion of the channel region and a tunneling layer and a ring-shaped floating gate layer surrounding an upper portion of the channel region.
US09673196B2 Field effect transistors with varying threshold voltages
A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
US09673194B2 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.
US09673189B2 ESD unit
An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.
US09673187B2 High speed interface protection apparatus
The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.
US09673179B1 Discrete electronic device embedded in chip module
The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
US09673177B1 Selectively soluble standoffs for chip joining
A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.
US09673176B2 Metal to metal bonding for stacked (3D) integrated circuits
The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
US09673175B1 Heat spreader for package-on-package (PoP) type packages
A package-on-package (PoP) device has a first package and an interposer heat spreader. The first package includes a die and a substrate. The substrate has die contact pads, top contact pads, bottom contact pads, and interconnects between the die contact pads, the top contact pads, and the bottom contact pads. The die is electrically connected to the die contact pads. The top contact pads are adapted to be electrically connected to a second package to form the PoP device. The heat spreader has a central section thermo-conductively connected to the die. The heat spreader includes at least one arm connected to the central section and extending out past an edge of the first package. The heat spreader also has openings for electrical interconnects between the first package and the second package.
US09673172B2 Integrated electronic device including an interposer structure and a method for fabricating the same
An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device (1) includes two or more active components (30a, 30b), possibly fabricated by different semiconductor technologies, and an interposer structure (10) adapted for carrying the two or more active components such that at least one of the active components is carried on a top surface of the interposer structure. The integrated circuit device also includes at least one metal cap (40), furnished on the top surface of the interposer structure and encapsulating at least one of the active components. Some variants of the integrated circuit device of the invention are suited for operation under extreme conditions.
US09673170B2 Batch process for connecting chips to a carrier
Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.
US09673164B2 Semiconductor package and system with an isolation structure to reduce electromagnetic coupling
A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling is presented. The semiconductor device has a substrate on which a first circuit and a second circuit with inputs and outputs are formed proximate to each other. An isolation structure of electrically conductive material is located between components of the first and second circuits, the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. The isolation structure may be positioned on or over exterior surfaces of the semiconductor device housing or inside the housing. In one embodiment, the isolation structure includes a first leg extending transverse to the surface of the substrate and a first cross member connected to and projecting from the first leg over the substrate.
US09673154B2 Semiconductor device
A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.
US09673150B2 EMI/RFI shielding for semiconductor device packages
An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.
US09673149B2 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.
US09673145B2 Semiconductor integrated circuit layout structure
A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.
US09673139B2 Semiconductor device
A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.
US09673137B2 Electronic device having a lead with selectively modified electrical properties
A die package having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a first lead having a first metal core with a first core diameter, and a dielectric layer surrounding the first metal core, the dielectric layer having a first dielectric thickness that varies along its length and/or the dielectric layer having an outer metal layer at least partially surrounding the dielectric layer, for selectively modifying the electrical characteristics of the lead.
US09673136B2 Housing arrangement, method of producing a housing and method of producing an electronic assembly
A housing arrangement includes a plurality of interconnected housings for electronic components, each housing including a leadframe section of a leadframe, wherein the leadframe section is formed from an electrically conductive material and has a receiving region that receives the electronic component and/or a contact region that contacts the electronic component, a molding material into which the leadframe section is embedded and which has at least one receiving opening in which the receiving region and/or the contact region are exposed, and at least one stress reduction opening formed in the molding material and free of the receiving region and/or the contact region, wherein the housings connect to one another via the leadframe and the molding material, the stress reduction openings are formed at transitions from in each case one of the housings to another of the housings.
US09673135B2 Semiconductor device having mirror-symmetric terminals and methods of forming the same
A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device.
US09673134B2 Semiconductor component and method of manufacture
A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.
US09673133B2 Semiconductor devices having through-electrodes
Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.
US09673131B2 Integrated circuit package assemblies including a glass solder mask layer
Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.
US09673130B2 Semiconductor device having a cooler
A cooler 20 of a semiconductor device includes an inlet portion 27 and an outlet portion 28 for a cooling liquid, an inlet path 24, an outlet path 25, and a cooling flow path 26. The inlet path 24 and the outlet path 25 have asymmetrical planar shapes. A connection portion 271 between the inlet path 24 and the inlet portion 27 is opposed to the cooling flow path 26 of a part immediately below plural circuit substrates 13 arranged on the cooler 20. A connection portion 281 between the outlet path 25 and the outlet portion 28 is opposed to the cooling flow path 26 of a part immediately below plural circuit substrates 13 arranged on the cooler 20.
US09673129B2 Semiconductor device
In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.
US09673126B2 Multi-functional semiconductor refrigerating and warming dual-purpose box and manufacturing method
A multi-functional semiconductor refrigerating and warming dual-purpose box includes a box body, a refrigerating and heating unit, a composite condenser unit, and a liquid delivering pump. The box body includes two independent rooms, a bottom machine room, an upper working room, and a lower working room. The refrigerating and heating unit includes an upper room semiconductor refrigerating and heating unit and a lower room semiconductor refrigerating and heating unit, the upper room semiconductor refrigerating and heating unit comprising an external heat exchanger of the upper room, a first semiconductor chilling plate, and an internal heat exchanger of the upper room. The composite condenser unit and the liquid delivering pump are connected to the external heat exchanger of the upper room and the external heat exchanger of the lower room through pipes. A manufacturing method of a multi-functional semiconductor refrigerating and warming dual-purpose box is also provided.
US09673123B2 Electronic device module and method of manufacturing the same
The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal.
US09673113B2 Method and system for real-time polishing recipe control
Systems and methods are provided for controlling a polishing process in real-time. First and second characteristics are identified in first and second data sets, respectively, with each data set corresponding to a real-time wafer polishing data. A time delta is computed between the times at which the first and second characteristics occur within their respective data sets, and polishing parameters are then updated in real-time based on the computed time delta.
US09673111B2 Methods for extreme ultraviolet mask defect mitigation by multi-patterning
Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.
US09673105B2 CMOS devices with Schottky source and drain regions
A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.
US09673101B2 Minimize middle-of-line contact line shorts
Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
US09673096B2 Method for processing a semiconductor substrate and a method for processing a semiconductor wafer
According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.
US09673093B2 Semiconductor device and method of making wafer level chip scale package
A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.
US09673090B2 Seed layers for metallic interconnects
One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) at least one of the PVD seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, (iii) the PVD seed layers have no substantial overhangs sealing or pinching-off the top corners of the at least one opening, (iv) the combined thickness of the seed layers over the field is sufficient to enable uniform electroplating across the substrate, and (v) the combined seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening.
US09673085B2 Method for manufacturing SOI wafer
The present invention provides a method for manufacturing an SOI wafer including a step of forming an insulator film on an entire surface of a bond wafer before bonding, bringing a bonded wafer before delaminating the bond wafer at an ion implanted layer into contact with a liquid that enables dissolving the insulator film while protecting the insulator film on a back surface on the opposite side of a bonding surface of the bond wafer, or exposing the bonded wafer to a gas that enables dissolving the insulator film, and thus etching the insulator film placed between the bond wafer and a base wafer from an outer peripheral end of the bonded wafer toward a center of the bonded wafer.
US09673081B2 Isolated through silicon via and isolated deep silicon via having total or partial isolation
Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.
US09673080B2 Semiconductor piece manufacturing method
A semiconductor piece manufacturing method includes: a process of forming a fine groove on a front surface side including a first groove portion having a width that is gradually narrowed from a front surface of a semiconductor substrate W toward a rear surface thereof; a process of attaching a dicing tape having an adhesive layer on the front surface after the fine groove on the front surface side is formed; a process of forming a groove on a rear surface side having a width greater than the width of the fine groove on the front surface side along the fine groove on the front surface side from a rear surface side of the substrate by a rotating dicing blade; and a process of separating the dicing tape from the front surface after the groove on the rear surface side is formed.
US09673069B2 High frequency filter for improved RF bias signal stability
A plasma-assisted etch process for the manufacture of semiconductor or MEMS devices employs an RF source to generate a plasma that is terminated through an electrode. The termination is designed as a “short” at the frequency of the RF source to minimize voltage fluctuations on the electrode due to the RF source energy. The electrode voltage potential can then be accurately controlled with a bias source, resulting in improved control of etch depth of a semiconductor substrate disposed on the electrode.
US09673062B1 Plasma processing method
To provide a plasma processing device, a plasma processing method and a method of manufacturing electronic devices capable of performing high-speed processing as well as using the plasma stably. In an inductively-coupled plasma torch unit, a coil, a first ceramic block and a second ceramic block are arranged in parallel, and a long chamber has an annular shape. Plasma generated in the chamber is ejected from an opening in the chamber toward a substrate. The substrate is processed by moving the long chamber and the substrate mounting table relatively in a direction perpendicular to a longitudinal direction of the opening. A discharge suppression gas is introduced into a space between the inductively-coupled plasma torch unit and the substrate inside the chamber through a discharge suppression gas supply hole, thereby generating long plasma stably.
US09673061B2 Method for thermal process in packaging assembly of semiconductor
A method for thermal process in packaging assembly of semiconductor is disclosed. The high-pressure overheated vapor is injected into the process chamber. The overheated vapor becomes saturated vapor in atmosphere (1 ATM) immediately and generates condensed liquid film onto all the surface of semiconductor work and also the chamber walls as condensation phenomenon occurs. The process temperature of vapor condensation is very close to and never exceeds the boiling point of perfluorinated compounds (PFC). Therefore, the latent heat of the saturated vapor is transferred to semiconductor work through the surface of liquid film evenly and uniformly.
US09673059B2 Method for increasing pattern density in self-aligned patterning integration schemes
Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme comprising: providing a substrate having a patterned layer comprising a first mandrel and an underlying layer; performing a first conformal spacer deposition creating a first conformal layer; performing a first spacer reactive ion etch (RIE) process on the first conformal layer, creating a first spacer pattern; performing a first mandrel pull process removing the first mandrel; performing a second conformal spacer deposition creating a second conformal layer; performing a second RIE process creating a second spacer pattern, the first spacer pattern acting as a second mandrel; performing a second mandrel pull process removing the first spacer pattern; and transferring the second spacer pattern into the underlying layer; where the integration targets include patterning uniformity, pulldown of structures, slimming of structures, and gouging of the underlying layer.
US09673056B2 Method to improve finFET cut overlay
A patterned photoresist having an overlay tolerance of (x+y)/2 is formed over preselected hard mask portions or semiconductor fin portions, wherein x is a width of a semiconductor fin and y is a distance between a neighboring pair of semiconductor fins. Hard mask portions or semiconductor fin portions not protected by the patterned photoresist are then removed by an isotropic etching process. The patterned photoresist is removed. In some embodiments, the remaining hard mask portions are employed as fin forming etch masks.
US09673051B1 High density patterned material on integrated circuits
An integrated circuit comprises a plurality of strips of material over a substrate, the plurality of strips including strips S(i), each strip S(i) for i going from 3 to n having a first segment and a second segment separated by a gap from the first segment. The integrated circuit comprises a plurality of landing areas, the plurality of landing areas including landing areas A(i), each landing area A(i) for i going from 3 to n−2 connecting a first segment of strip S(i) in the plurality of strips with a second segment of strip S(i+2) in the plurality of strips, and disposed within the gap between the first and second segments in strip S(i+1). The strips S(i) have a first pitch in a direction orthogonal to the strips, and the landing areas A(i) have a second pitch twice the first pitch in the direction orthogonal to the strips of material.
US09673047B2 Solid phase epitaxy of 3C—SiC on Si(001)
A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.
US09673046B2 Gallium nitride substrate and manufacturing method of nitride semiconductor crystal
The invention provides a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a method for manufacturing an M-plane GaN substrate by forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonothermal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
US09673045B2 Integration of III-V devices on Si wafers
An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
US09673039B2 Devices comprising high-K dielectric layer and methods of forming same
Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
US09673033B2 Multi-reflection mass spectrometer
A multi-reflection mass spectrometer comprising two ion-optical mirrors, each mirror elongated generally along a drift direction (Y), each mirror opposing the other in an X direction and having a space therebetween, the X direction being orthogonal to Y; the mass spectrometer further comprising one or more compensation electrodes each electrode being located in or adjacent the space extending between the opposing mirrors; the compensation electrodes being configured and electrically biased in use so as to produce, in at least a portion of the space extending between the mirrors, an electrical potential offset which: (i) varies as a function of the distance along the drift length, and/or; (ii) has a different extent in the X direction as a function of the distance along the drift length. In a preferred embodiment the period of ion oscillation between the mirrors is not substantially constant along the whole of the drift length.
US09673032B1 Sample sprayer with adjustable conduit and related methods
A sample sprayer includes a first conduit for conducting a liquid sample, a second conduit surrounding the first conduit to define an annular passage for conducting a gas, a sprayer tip in which a fluid interaction region receives the liquid sample and the gas. The sprayer tip is configured to produce a sample spray by contact between the liquid sample and the gas in the fluid interaction region and emit the sample spray from the orifice. An adjustable positioning device is configured to translate the first conduit along the longitudinal axis in response to adjustment of the positioning device, wherein an axial position of the first conduit is adjustable relative to the orifice.
US09673031B2 Conversion of ion arrival times or ion intensities into multiple intensities or arrival times in a mass spectrometer
A mass spectrometer is disclosed comprising a Time of Flight mass analyzer comprising an ion detector comprising an Analog to Digital Converter. Signals from the Analog to Digital Converter are digitized and the arrival time and intensity of ions are determined. The arrival time T0 and intensity S0 of each ion arrival event is converted into two separate intensities S(n),S(n+i) which are stored in neighboring time bins T(n), T(n+1).
US09673030B2 Computer readable storage mediums, methods and systems for normalizing chemical profiles in biological or medical samples detected by mass spectrometry
Described herein are computer-readable storage mediums, methods and systems useful for analyzing samples via mass spectrometry. Aspects described herein include methods for normalizing mass spectrometry data that include providing a reference set of mass spectrometry data obtained from a first external standard sample having one or more isotopic standards, wherein the reference set of mass spectrometry data comprises one or more m/z intensity ratios. Methods described herein are useful for reducing errors based on instrument response and ionization efficiencies and improve reproducibility of data from instrument to instrument and from day to day.
US09673025B2 Electrostatic chuck including embedded faraday cage for RF delivery and associated methods for operation, monitoring, and control
A ceramic layer is attached to a top surface of a base plate using a bond layer. The ceramic layer has a top surface configured to support a substrate. At least one clamp electrode is positioned within an upper region of the ceramic layer. A primary radiofrequency (RF) power delivery electrode is positioned within the ceramic layer at a location vertically below the at least one clamp electrode such that a region of the ceramic layer between the primary RF power delivery electrode and the at least one clamp electrode is substantially free of other electrically conductive material. A plurality of RF power delivery connection modules is distributed in a substantially uniform manner about a perimeter of the ceramic layer. Each of the RF power delivery connection modules is configured to form an electrical connection from the base plate to the primary RF power delivery electrode at its respective location.
US09673024B2 Particle-optical systems and arrangements and particle-optical components for such systems and arrangements
A particle-optical arrangement comprises a charged-particle source for generating a beam of charged particles; a multi-aperture plate arranged in a beam path of the beam of charged particles, wherein the multi-aperture plate has a plurality of apertures formed therein in a predetermined first array pattern, wherein a plurality of charged-particle beamlets is formed from the beam of charged particles downstream of the multi-aperture plate, and wherein a plurality of beam spots is formed in an image plane of the apparatus by the plurality of beamlets, the plurality of beam spots being arranged in a second array pattern; and a particle-optical element for manipulating the beam of charged particles and/or the plurality of beamlets; wherein the first array pattern has a first pattern regularity in a first direction, and the second array pattern has a second pattern regularity in a second direction electron-optically corresponding to the first direction, and wherein the second regularity is higher than the first regularity.
US09673023B2 System for discharging an area that is scanned by an electron beam
A method and a system for imaging an object, the system may include electron optics that may be configured to scan a first area of the object with at least one electron beam; wherein the electron optics may include a first electrode; and light optics that may be configured to illuminate at least one target of (a) the first electrode and (b) the object, thereby causing an emission of electrons between the first electrode and the object.
US09673021B2 Positioning control device
An object of the invention is to provide a positioning apparatus and a positioning control device that may perform precise positioning by suppressing relative displacement of a movable point and positioning target objects. In a positioning apparatus including a movable stage, a stage position detector that detects a position of the movable stage, a control device that performs positioning of the movable stage, a positioning target object for positioning of the movable stage, and at least one or more sensors in a structure of the positioning target object or the movable stage, the control device includes an amount of relative displacement estimation unit that estimates an amount of relative displacement of the movable stage and the positioning target object using information of the sensor and information of the stage position detector, and a unit that controls the position of the stage using information calculated by the amount of relative displacement estimation unit.
US09673020B2 Charged particle beam device, method for adjusting charged particle beam device, and method for inspecting or observing sample
A charged particle beam device capable of observing a sample in an air atmosphere or gas atmosphere has a thin film for separating the atmospheric pressure space from the decompressed space. A vacuum evacuation pump evacuates a first housing; and a detector detects a charged particle beam (obtained by irradiation of the sample) in the first housing. A thin film is provided to separate the inside of the first housing and the inside of a second housing at least along part of the interface between the first and second housings. An opening part is formed in the thin film so that its opening area on a charged particle irradiation unit's side is larger than its opening area on the sample side; and the thin film which covers the sample side of the opening part transmits or allows through the primary charged particle beam and the charged particle beam.
US09673018B2 Charged particle beam writing apparatus and charged particle beam writing method
A charged particle beam writing apparatus includes a limiting aperture member at the downstream side of the emission source, arranged such that its height position can be selectively adjusted, according to condition, to be one of the n-th height position (n being an integer of 1 or more) based on the n-th condition depending on at least one of the height position of the emission source and an emission current value, and the (n+m)th height position (m being an integer of 1 or more) based on the (n+m)th condition depending on at least one of the height position of the emission source and the emission current value, and a shaping aperture member at the downstream side of the electron lens and the limiting aperture member to shape the charged particle beam by letting a part of the charged particle beam pass through a second opening.
US09673015B2 Partially grounded depressed collector
A depressed beam collector and an RF source comprising a depressed beam collector. The RF source may include, e.g., a multi-beam klystron, a single beam klystron, or other RF sources having an electron gun. The beam collector collects spent electrons from the electron gun and comprises a grounded portion configured to collect a portion of electrons entering the collector and a biased portion configured to collect another portion of the electrons entering the collector and having a depressed energy.
US09673013B2 Electrical switching apparatus, and interface assembly and display apparatus therefor
An interface assembly is for an electrical switching apparatus. The electrical switching apparatus includes a housing, a first handle partially extending through the housing, separable contacts located within the housing, an operating mechanism to open and close the separable contacts, a main printed circuit board located within the housing, and a number of electrical rating settings associated with the main printed circuit board. Each of the electrical rating settings has a magnitude. The interface assembly includes: a base assembly comprising a base, the base being disposed on the housing, the base having a mounting surface; and a second handle coupled to the mounting surface, the second handle and the first handle being structured to drive each other. The mounting surface has at least one port. The magnitude of a corresponding one of the electrical rating settings is visible through the at least one port.
US09673008B2 Electromagnetic switch
An electromagnetic switch includes a contact housing case; a plurality of contact mechanisms each having a fixed contact and a movable contact contacting to and separating from the fixed contact, and disposed in parallel inside the contact housing case; a movable contact holding portion holding the movable contacts of the plurality of contact mechanisms; and an electromagnet unit having a movable plunger moving the movable contact holding portion.
US09673002B2 Double seesaw switch
A double seesaw switch has two seesaw switches arranged side-by-side inside a case. Each of the two seesaw switches has a central terminal arranged on a bottom surface inside the case, a pair of fixed contacts separately arranged, a moving contact supported pivotably with respect to the central terminal and has a contact portion for contacting one of the fixed contacts, an operation body supported rotatably with respect to the case, and pivots the moving contact by moving on the moving contact in correspondence with a rotation movement of the operation body, and a biasing part biasing the operation body towards a neutral position. The biasing part is a leaf spring piece formed in a U shape from a portion of a ceiling surface of the case, and to press against the operation body in a power storing state of a leading end portion compressed.
US09672999B1 Mechanical keyboard button structure
The invention discloses a mechanical keyboard button structure including a base plate, a circuit board, a mechanical switch and a keycap, wherein the base plate, the circuit board, the mechanical switch and the keycap are connected in order from bottom to top; the mechanism switch is used for guiding the keycap to move up and down and converting a pressure of the keycap into a switch signal to transmit to the circuit board to communicate a circuit; the mechanical switch includes a supporting plate and a switch spindle arranged on the supporting plate and further includes a pair of scissors, the upper portion of the pair of scissors is fixed with the bottom surface of the keycap, while the lower portion is fixed with the supporting plate, and the switch spindle passes through the pair of scissors and supports against the bottom surface of the keycap. According to the invention, the mechanical axle structure is combined with the scissor structure, so that the button is supported more stably, the service life is long, and the corner has both better hand feeling and function; second, the structure can be used for the keyboard with a shorter stroke, so that the keyboard is thinner and lighter and is more widely applied in the market; at last the whole circuit does not need to be replaced when the trigger circuit below a single key is damaged, and the single button can be repaired and replaced.
US09672994B2 Device for operating multiple functions in a motor vehicle
A device for operating multiple functions includes an operating element and a base. The base has side bearings with guide slots, hinge joints with pivot pins, and an actuator. The operating element is mounted in the guide slots to pivotably be mounted to the side bearings about an axis of rotation to thereby be movable between positions. At least one of the positions is assigned to a switching function. The operating element is mounted to the base on a centered bearing between the side bearings. The operating element is supported on the pivot pins. Upon the operating element being actuated to trigger a switching function, the actuator produces a haptic feedback by generating an actuating force on the operating element which causes the pivot pins to pivot in a direction parallel to the axis of rotation thereby causing the operating element to axially displace along this same direction.
US09672991B2 Purified carbon nanotubes
The present invention relates to a method of preparing purified carbon nanotubes (CNTs) comprising mixing starting CNTs with an organic solvent in the presence of sonication; substantially removing the organic solvent to obtain a CNT composition; and heating the CNT composition at 200° C. or higher to obtain the purified carbon nanotubes. The present invention further relates to the purified CNTs and cohesive CNT assemblies prepared from the method described herein, and articles (e.g. capacitor, energy storage device or capacitive deionization device) comprising the purified CNTs.
US09672990B2 Organic dyes incorporating the oxadiazole moiety for efficient dye-sensitized solar cells
An oxadiazole dye for use as an organic photosensitizer. The oxadiazole dye comprising donor-π-spacer-acceptor type molecules in which at least one of an oxadiazole group acts as a π-conjugated bridge (spacer), a naphthyl unit acts as an electron-donating unit, a carboxyl group act as an electron acceptor group, and a cyano group acts as an anchor group. An optional thiophene group acts as part of the π-conjugated bridge (spacer). The dye for use as organic photosensitizers in a dye-sensitized solar cell. The dye for use in photodynamic therapies. Computational DFT and time dependent DFT (TD-DFT) modeling techniques showing Light Harvesting Efficiency (LHE), Free Energy for Electron Injection (ΔGinject), Excitation Energies, and Frontier Molecular Orbitals (FMOs) indicate that the series of dye comprise a more negative ΔGinject and a higher LHE value; resulting in a higher incident photon to current efficiency (IPCE).
US09672988B2 High-voltage pulse discharge capacitor and manufacturing method thereof
A high-voltage pulse discharge capacitor of an elongated structure comprises a capacitor body. The capacitor body comprises several high-voltage capacitor parallel units and a high-voltage capacitor core pack. The several high-voltage capacitor parallel units are mutually connected in parallel. The high-voltage capacitor parallel units connected in parallel are then connected as a whole with the high-voltage capacitor core pack in parallel. The high-voltage capacitor parallel unit comprises two capacitor core packs. The two capacitor core packs are mutually connected in parallel. The capacitor core packs connected in parallel are wrapped with a PP film and purple copper foil at an outer side integrally. The purple copper foil is connected to axial faces located at a head and a tail of a combination integral of the two capacitor core packs. Using a preceding parallel connection mode enables the capacitor to provide greater current when discharging electricity, reduces heat generated by internal resistance when the capacitor discharges the electricity, and prolongs a service life of the capacitor.
US09672982B2 Production method for a figure-of-eight-shaped laminated coil
There is provided a production method for a laminated coil, the production method including: a process of producing a coil part of one axis by stacking a flat coil in an axial direction, a process of bending the flat coil of a connection portion in an extended state thereof in a length direction to allow for the division of a first coil part and a second coil part, wherein the connection portion connecting two coil parts is produced by bending the flat coil of the connection portion, and a process of finally spreading the bent connection portion, such that the first coil part and the second coil part may be disposed to be parallel in the same direction on the same plane.
US09672970B2 Inductor bridge and electronic device
An inductor bridge is configured to bridge-connect a first circuit and a second circuit to each other, and includes a flexible flat plate base body, a first connector at a first end portion of the base body and connected to the first circuit, a second connector at a second end portion of the base body and connected to the second circuit, and an inductor section in the base body between the first connector and the second connector. The inductor section includes conductor patterns including a plurality of layers. The inductor bridge further includes a bending portion between the inductor section and the first connector, and a slot at an inner side of the bending portion that reduces a thickness of the base body.
US09672966B2 Bobbin, winding apparatus and coil
A bobbin has a winding core and multiple partitioning walls, so that multiple winding areas are formed in an axial direction. A groove is formed in each of the partitioning walls, so that a wire rod strides over the partitioning wall bypassing through the groove when a winding process for one of the winding areas is finished and a winding process for a neighboring winding area will be started. The groove has a first and a second guide wall surfaces, which are opposed to each other in a circumferential direction. Each of the first and the second guide wall surfaces is inclined in the axial direction such that each of the first and the second guide wall surfaces comes closer to a circumferential winding-end side in the axial direction to a stride-end side.
US09672964B2 High field strength varistor material
The present invention relates to a varistor material for a surge arrester with target switching field strength ranging from 250 to 400 V/mm comprising ZnO forming a ZnO phase and Bi expressed as Bi2O3 forming an intergranular bismuth oxide phase, said varistor material further comprising a spinel phase, characterized in that the amount of a pyrochlore phase comprised in the varistor material is such, that the ratio of the pyrochlore phase to the spinel phase is less than 0.15:1.
US09672963B2 Ceramic electronic component and method of manufacturing the same
A ceramic electronic component includes a rectangular or substantially rectangular parallelepiped shaped laminate in which a ceramic layer and an internal electrode are alternately laminated and an external electrode provided on a portion of a surface of the laminate and electrically connected to the internal electrode. The external electrode includes an inner external electrode covering a portion of the surface of the laminate and including a mixture of a resin component and a metal component and an outer external electrode covering the inner external electrode and including a metal component. The inner external electrode includes, as a metal component, a first metal component of which a portion forms an alloy with the internal electrode so as to connect the internal electrode and the inner external electrode to each other, and a second metal component higher in melting point than the first metal component, of which a portion forms an alloy with the first metal component so as to connect the inner external electrode and the outer external electrode to each other. A concentration of a metal in a surface layer of the inner external electrode is not lower than about 17%.
US09672962B2 Bushing of an electrical conductor
A bushing of an electrical conductor through a wall which separates two regions from one another, wherein the conductor extends through a passage in the wall, at a distance from said wall, characterized in that a sleeve, which is electrically insulated from the passage and is hermetically sealed, preferably extends approximately coaxially through the passage, and in that the electrical conductor extends through the sleeve and is incorporated in the sleeve in a hermetically sealed, preferably integral, manner.
US09672961B2 Bus bar module accommodating part structure
A synthetic resin plate (1) includes a plurality of accommodating parts (2) which accommodate at least one of bus bars, terminals, and electric wires which are connected to the terminals, hinges (7) which make first accommodating parts and second accommodating parts of the accommodating parts (2) connected and relatively movable, and projecting parts which are provided on the top surfaces of peripheral wall parts of the first accommodating parts, and which abut against parts of the second accommodating parts to restrict the movable ranges in the movable directions of the second accommodating parts relative to the first accommodating pans.
US09672958B2 Electrical cable with shielded conductors
An electrical cable includes at least one conductor assembly. Each conductor assembly includes at least one inner conductor that extends along a length, an insulator, and a shield layer. The insulator engages and surrounds a surface of the at least one inner conductor. The insulator is composed of a dielectric material. The shield layer engages and surrounds an outer perimeter of the insulator. The shield layer is formed of a conductive plastic material to provide electrical shielding for the at least one inner conductor and flexibility.
US09672956B2 High-frequency signal line and manufacturing method thereof
A high-frequency signal line includes a linear signal line and a first ground conductor provided at a dielectric body to extend along the dielectric body. The first ground conductor includes a first main surface and a second main surface opposed to each other in a direction of lamination. A strip-shaped protrusion extending along the signal line is provided on the second main surface of the first ground conductor.
US09672955B2 Clamp and wire harness having clamp
A clamp includes a base plate that is locked to an adhesive sheet which covers and holds an electric wire, a shaft that projects from the base plate and is inserted through an attaching hole which is bored through the adhesive sheet, an engaging portion that is formed at the distal end of the shaft, is inserted through the attaching hole and is engaged with an engaging hole of an attached body, and fixing pieces that project from the base plate to have an interval between projecting ends of the fixing pieces which is larger than the maximum opening width of the attaching hole, and hold and fix the fringe of the attaching hole with the base plate.
US09672942B2 Data decoding method of non-volatile memory device and apparatus for performing the method
A method of decoding data of a non-volatile memory device is provided. The method includes a first decoding operation of reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation of reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation, and performing decoding using the first soft decision; and a third decoding operation of changing from the first hard decision read level to a second hard decision read level when the decoding fails in the second decoding operation, reading second hard decision data using the second hard decision read level, and performing decoding either using the second hard decision data or using both the second hard decision data and the first soft decision data.
US09672934B2 Temperature compensation management in solid-state memory
Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.
US09672930B2 Low power operation for flash memory system
The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.
US09672929B2 Semiconductor memory in which source line voltage is applied during a read operation
A semiconductor memory device includes a memory cell, a word line electrically connected to a gate of the memory cell, and a source line electrically connected to a first end of the memory cell. During a read operation of the memory cell, a first voltage is applied to the source line in a first operation to determine whether or not a threshold voltage of the memory cell is above a first threshold value, a second voltage is applied to the source line in a second operation to determine whether or not the threshold voltage of the memory cell is above a second threshold value, and a third voltage is applied to the source line in a third operation to determine whether or not the threshold voltage of the memory cell is above a third threshold value.
US09672926B2 Apparatus and method of programming and verification for a nonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage
US09672925B2 Storage in charge-trap memory structures using additional electrically-charged regions
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
US09672923B1 Low power high speed program method for multi-time programmable memory device
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.
US09672916B2 Operation modes for an inverted NAND architecture
Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
US09672913B1 Semiconductor memory device and operating method thereof
There are provided a semiconductor memory device and an operating method thereof. The method of operating a semiconductor memory device may include receiving an erase and write (E/W) cycle mode select command and an operation command. The method may include selecting one E/W cycle mode information among a plurality of E/W cycle mode information stored according to the E/W cycle mode select command and storing the selected one E/W cycle mode information. The method may include performing a general operation of a memory cell array according to the one E/W cycle mode information stored and the operation command.
US09672910B2 Memory architecture for storing data in a plurality of memory chips
A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.
US09672909B2 Memory cell retention enhancement through erase state modification
A method of controlling a resistive memory cell is provided. A resistance threshold value is defined for the memory cell, wherein a circuit identifies the cell as erased if a detected resistance of the cell is above the resistance threshold and identifies the cell as programmed if the detected resistance is below the resistance threshold value. A filament is formed across an electrolyte switching region of the cell by applying an electrical charge, wherein the cell having the formed filament has a first resistance. The cell is then erased to an erased state having a second resistance greater than the first resistance. The cell is then programmed to a quasi-erased state having a third resistance between the first and second resistances, and above the resistance threshold value such that the cell is identified by the circuit as erased. The cell may then be maintained in the quasi-erased state.
US09672908B2 Apparatuses and methods of reading memory cells based on response to a test pulse
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.
US09672906B2 Phase change memory with inter-granular switching
A memory device comprising a conglomerate material interposed between a first electrode and a second electrode is provided. The conglomerate material includes nanocrystalline grains embedded in an amorphous matrix. During operations, phase change reactions occur at the inter-grain boundaries in the conglomerate material so as to reduce the operation power.
US09672900B2 Semiconductor memory device for stably reading and writing data
In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.
US09672896B2 Semiconductor memory device and semiconductor system having the same
A semiconductor memory device may include: a data alignment signal generation unit suitable for generating an alignment signal corresponding to an input speed of data; a data alignment unit suitable for aligning the data in response to the alignment signal to output aligned data; and a state data storage unit suitable for storing the aligned data in response to a control signal which is activated at a given time.
US09672894B2 Device and method of controlling refresh operation for dynamic random access memory (DRAM)
A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address.
US09672892B2 Memory device and memory system including the same
A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.
US09672890B2 Semiconductor memory apparatus
A semiconductor memory apparatus includes a plurality of cell arrays; and a use information storage block configured to determine whether a data write operation has already been performed for the plurality of cell arrays, and generate a plurality of control signals, wherein the semiconductor memory apparatus is configured to control a refresh operation for the plurality of cell arrays according to the plurality of control signals.
US09672888B2 Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.
US09672886B2 Fast and low-power sense amplifier and writing circuit for high-speed MRAM
A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.
US09672884B1 Semiconductor devices and semiconductor systems including the same
A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.
US09672882B1 Conditional reference voltage calibration of a memory system in data transmisson
A method and apparatus for memory subsystem calibration in which periodic calibrations of a data strobe delay and reference voltage are scheduled. After a first calibration, a reference score is determined based on a parameter of an eye opening. On a next scheduled calibration thereafter, the data strobe delay is calibrated at the most recent value of the reference voltage. A score is then determined, and compared to the reference score. If the score is within a specified range of the reference score, then no calibration of the reference voltage is performed on the current cycle. Otherwise, the reference voltage is calibrated as well.
US09672875B2 Methods and apparatuses for providing a program voltage responsive to a voltage determination
Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
US09672872B2 Semiconductor device having multiport memory
A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.
US09672870B1 Sealed bulkhead electrical feed-through X-Y positioning control
An electrical feed-through, such as a PCB connector, involves a connector part that includes a housing from which first and second positioning flanges extend from opposing ends. A data storage device includes an enclosure base with which the electrical feed-through is coupled, where the base comprises an annular recessed surface surrounding an aperture that is encompassed by the electrical feed-through, and first and second recessed positioning surfaces extending in directions outward from respective longitudinal ends of the annular recessed surface, where each of the recessed positioning surfaces has a corresponding wall extending vertically therefrom. When assembled, each positioning flange of the electrical feed-through mechanically mates with a corresponding recessed positioning surface of the base, such that the position of the electrical feed-through is constrained by the walls of each recessed positioning surface.
US09672866B2 Automated looping video creation
Automated looping video creation techniques are described. In one or more implementations, a digital medium environment is configured to create a looping video that supports repeated playback that appears generally seamless to a user by one or more computing devices. Frames of a video are segmented into foreground and background regions by the one or more computing devices. Similarity of the foreground regions is determined of the segmented frames, one to another, by the one or more computing devices to use as a transition in the looping video. The looping video is synthesized as a subset of the video by the one or more computing devices as having the transition based on the determined similarity of first and second said frames.
US09672860B2 Recording/reproducing apparatus
According to an embodiment, a recording/reproducing apparatus includes a diffraction grating and a light-receiving element. The diffraction grating divides return light from the guide layer in accordance with areas. The areas include a first area and a second area that does not overlap the first area. The light-receiving element includes (i) a first detecting cell group which receives a zero-order beam to which astigmatism is imparted, (ii) a second detecting cell group which receives at least one of a positive and negative first-order beam, which passes the first area and made astigmatic, and (iii) a third detecting cell group which receives at least one of a positive and negative first-order beam, which passes the second area and made astigmatic.
US09672856B1 Perpendicular magnetic recording media with lateral exchange control layer
A magnetic media having a lateral exchange control layer formed on a magnetic oxide layer of a magnetic recording layer. A cap layer is formed over the lateral exchange control layer. The lateral exchange control layer can be an alloy comprising Co and one or more of W, Ru, Hf, Ta, Nb and Fe. The lateral exchange control layer has the highest magnetic saturation moment among all the recording layers, and increases spacing between magnetic grains (e.g. increased non-magnetic boundary width), thereby reducing lateral exchange sigma. The presence of lateral exchange control increases signal to noise ratio and reduces bit error rate and increases areal density.
US09672849B2 Multiple reader stacks disposed in close proximity
In accordance with one embodiment, a multi-reader can be manufactured so as to be able to read from multiple regions of a storage device contemporaneously during operation. Such a device can be configured, for example, by forming a first wall; forming a second wall; and utilizing the first wall and the second wall to form two adjacent reader stacks.
US09672837B2 Non-uniform parameter quantization for advanced coupling
The present disclosure provides methods, devices and computer program products for non-uniform quantization of parameters relating to parametric spatial coding of audio signals. The disclosure further relates to a method and apparatus for reconstructing an audio object in an audio decoding system taking the non-uniformly quantized parameters into account. According to the disclosure, such an approach renders it possible to reduce bit consumption without substantially reducing the quality of the reconstructed audio object.
US09672832B2 Audio encoder, audio encoding method and program
There is provided an audio encoder comprising a determination part determining, based on frequency spectra of audio signals of a plurality of channels, a mixing ratio as a ratio, relative to a frequency spectrum after mixing for each channel of the plurality of channels, of the frequency spectrum for another channel, a mixing part mixing the frequency spectra of the plurality of channels for each channel based on the mixing ratio determined by the determination part, and an encoding part encoding the frequency spectra of the plurality of channels after mixing by the mixing part.
US09672831B2 Quality of experience for communication sessions
A computer-implemented method, computer program product, and computing system is provided for managing quality of experience for communication sessions. In an implementation, a method may include determining a language spoken on a communication session. The method may also include selecting a codec for the communication session based upon, at least in part, the language spoken on the communication session. The method may further include transacting the communication session using the selected codec for the communication session.
US09672830B2 Voice signal encoding and decoding method, device, and codec system
A voice signal encoding and decoding method, device, and codec system are provided. The coding method includes: encoding an input voice signal to obtain a broadband code stream, where the broadband code stream includes a core layer bit stream and an extension enhancement layer bit stream (101); compressing the core layer bit stream to obtain a compressed code stream (102); and packing the compressed code stream and the extension enhancement layer bit stream to obtain a packed code stream (103). The core layer bit stream is compressed, and the compressed code stream and the extension enhancement layer bit stream are packed, thereby reducing transmission bandwidth occupied by the input voice signal. Since the broadband voice encoding is performed on the input voice signal, a broadband voice code stream is transmitted by using narrowband transmission bandwidth, thereby improving the cost performance of voice signal transmission.
US09672829B2 Extracting and displaying key points of a video conference
Embodiments of the present invention disclose a method, system, and computer program product for speech summarization. A computer receives audio and video components from a video conference. The computer determines which participant is speaking based on comparing images of the participants with template images of speaking and non-speaking faces. The computer determines the voiceprint of the speaking participant by applying a Hidden Markov Model to a brief recording of the voice waveform of the participant and associates the determined voiceprint with the face of the speaking participant. The computer recognizes and transcribes the content of statements made by the speaker, determines the key points, and displays them over the face of the participant in the video conference.
US09672826B2 System and method for efficient unified messaging system support for speech-to-text service
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for communicating information about transcription progress from a unified messaging (UM) server to a UM client. In one embodiment, the transcription progress describes speech to text transcription of speech messages such as voicemail. The UM server authenticates and establishes a session with a UM client, then receives a get message list request from a UM client as of a first time, responds to the get message list request with a view of a state of messages and available transcriptions for transcribable messages in a list of messages associated with the get message list call at the first time, and, at a second time subsequent to the first time, transmits to the UM client a notification that provides an indication of progress for at least one transcription not yet complete in the list of messages. The messages can include video.
US09672824B2 Query rewrite corrections
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for natural language processing. One of the methods includes receiving a first voice query; generating a first recognition output; receiving a second voice query; determining from a recognition of the second voice query that the second voice query triggers a correction request; using the first recognition output and the second recognition to determine a plurality of candidate corrections; scoring each candidate correction; and generating a corrected recognition output for a particular candidate correction having a score that satisfies a threshold value.
US09672821B2 Robust speech recognition in the presence of echo and noise using multiple signals for discrimination
Systems and methods for speech recognition system having a speech processor that is trained to recognize speech by considering (1) a raw microphone signal that includes an echo signal and (2) different types of echo information signals from an echo cancellation system (and optionally different types of ambient noise suppression signals from a noise suppressor). The different types of echo information signals may include those used for echo cancelation and those having echo information. The speech recognition system may convert the raw microphone signal and different types of echo information signals (and optional noise suppression signals) into spectral features in the form of a vector, and a concatenator to combine the feature vectors into a total vector (for a period of time) that is used to train the speech processor, and during use of the speech processor to recognize speech.
US09672820B2 Simultaneous speech processing apparatus and method
According to one embodiment, a simultaneous speech processing apparatus includes an acquisition unit, a speech recognition unit, a detection unit and an output unit. The acquisition unit acquires a speech signal. The speech recognition unit generates a decided character string and at least one candidate character string. The detection unit detects a first character string as a processing piece character string if the first character string included in the decided character string exists commonly in one or more combined character strings on dividing the one or more combined character strings by a boundary indicating a morphological position serving as a start position of a processing piece in natural language processing. The output unit outputs the processing piece character string.
US09672818B2 Updating population language models based on changes made by user clusters
Technology for improving the predictive accuracy of input word recognition on a device by dynamically updating the lexicon of recognized words based on the word choices made by similar users. The technology collects users' vocabulary choices (e.g., words that each user uses, or adds to or removes from a word recognition dictionary), associates users who make similar choices, aggregates related vocabulary choices, filters the words, and sends words identified as likely choices for that user to the user's device. Clusters may include, for example, users in a particular location (e.g., sets of people who use words such as “Puyallup,” “Gloucester,” or “Waiheke”), users with a particular professional or hobby vocabulary, or application-specific vocabulary (e.g., word choices in map searches or email messages).
US09672813B2 Systems and methods for configuring matching rules related to voice input commands
Systems, devices and methods are provided for configuring matching rules related to voice input commands. For example, a first mapping relation between one or more first original terms in a preset term database and one or more first identification terms is established; the first mapping relation is stored in a first mapping relation table; one or more first voice input commands are configured for the first identification terms or one or more first statements including the first identification terms; and a second mapping relation between the first identification terms or the first statements and the first voice input commands is stored into a second mapping relation table.
US09672812B1 Qualifying trigger expressions in speech-based systems
A speech-based audio device may be configured to detect a user-uttered trigger expression and to respond by interpreting subsequent words or phrases as commands. In order to distinguish between utterance of the trigger expression by the user and generation of the trigger expression by the device itself, output signals used as speaker inputs are analyzed to detect whether the trigger expression has been generated by the speaker. If a detected trigger expression has been generated by the speaker, it is disqualified. Disqualified trigger expressions are not acted upon the by the audio device.
US09672811B2 Combining auditory attention cues with phoneme posterior scores for phone/vowel/syllable boundary detection
Phoneme boundaries may be determined from a signal corresponding to recorded audio by extracting auditory attention features from the signal and extracting phoneme posteriors from the signal. The auditory attention features and phoneme posteriors may then be combined to detect boundaries in the signal.
US09672804B2 Hearing aid compatible audio device with acoustic noise cancellation
A portable audio device, which includes active noise cancellation circuitry, a hearing aid compliant magnetic radiator, and a speaker/earpiece, is surrounded by ambient acoustic noise. The active noise cancellation circuitry provides an anti-noise signal at an input of the speaker to control/reduce the ambient acoustic noise outside of the device. In addition, the active noise cancellation circuitry provides an inverse anti-noise signal to an input of the magnetic radiator. The magnetic fields produced by the speaker driven by the anti-noise signal and the magnetic radiator driven by the inverse anti-noise signal cancel each other out through phase cancellation such that a hearing aid using a telecoil coupled to the audio device does not produce significant audio waves based on either of these signals. Other embodiments are also described.
US09672798B1 Systems and methods for providing decorative drum shell wraps
A drum shell wrap is disclosed that includes at least two layers of an acrylic film and a plurality of layers of polyethylene terephthalate (PET).
US09672781B2 Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.
US09672780B2 Over drive data generator and display driver including the same
A data generator includes an over drive data generator and a buffer. The over drive data generator generates an over drive data based on a previous display data and a current display data. The buffer provides the previous display data to the over drive data generator. The buffer stores the current display data and the over drive data. The buffer outputs the current display data and the over drive data. The data generator may increase the speed of driving the load connected to a display driver using the over drive voltage corresponding to the over drive data. If the speed of driving the load connected to the display driver is increased, the operational speed of the display device may be increased.
US09672779B2 Liquid crystal display device, backlight module, and drive circuit for backlight source thereof
Disclosed is a liquid crystal display device, a backlight module, and a backlight drive circuit. The backlight drive circuit comprises a booster circuit, a light-emitting unit, a circuit for automatic adjustment of current, and a controller. The current flowing through an LED will be altered by the circuit for automatic adjustment of current when extending an adjustable range of the controller, so as to reach the adjustable range of the controller.
US09672775B2 Method and circuit for synchronizing input and output synchronization signals, backlight driver of liquid crystal display device using the same and method for driving the backlight driver
Disclosed are method and circuit for synchronizing input and output synchronization signals, which can synchronize an output synchronization signal based on frequency change of an input synchronization signal and limit input and output periods, thereby preventing flickering, a backlight driver of a liquid crystal display device using the same, and a method for driving the backlight driver. The method for synchronizing input and output synchronization signals, includes generating an output synchronization signal whose output period is set based on a comparison result between an input period of an input synchronization signal and a previous output period of the output synchronization signal, and limiting the output period of the output synchronization signal within a predefined limit range from the previous output period.
US09672774B2 Electronic display device and backlight adjustment method thereof
The present disclosure provides an electronic display device including a backlight module, a light sensor, a storage device, an embedded controller, and a processing unit. The light sensor detects ambient light surrounding the electronic display device. The embedded controller controls intensity of the backlight module according to the ambient light and a brightness table of the storage device. The processing unit performs a basic input/output system to draw a brightness curve diagram according to the brightness table for users to adjust the curve of the brightness curve diagram during a boot process of the electronic display device and update the brightness table in the storage device according to the adjusted brightness curve diagram in response to a storing signal.
US09672770B2 Pixel circuit and driving method thereof, display device
A pixel circuit is disclosed, comprising: a driving module, an energy storage module, an electroluminescence module, a data voltage write module and a threshold compensation module, the threshold compensation module being connected with a compensation voltage input end, a first end of the energy storage module and at least one control signal input end, adapted to compensate the voltage of the first end of the energy storage module as a sum of the startup threshold of the driving module and the compensation voltage accessed by the compensation voltage input end in response to the control signal accessed by the connected control signal input end.
US09672768B2 Luminance-chrominance calibration production line of LED display module
A luminance-chrominance calibration production line includes: a rail; multiple stations disposed along the rail and including multiple first darkroom stations; multiple image acquisition apparatuses respectively disposed in the first darkroom stations and for capturing different color images sequentially displayed by a to-be-calibrated LED display module loaded on the rail to acquire color image data; and a rail computer system for controlling a transport movement on the rail and controlling the to-be-calibrated LED display module to display the different color images, and being signally connected to the image acquisition apparatuses to obtain the color image data. By using multiple image acquisition apparatuses to collect various color image information of LED display module in pipelined manner, calibration efficiency is improved, data collection is accurate, data collection error caused by using different image acquisition apparatuses to calibrate different LED display modules is avoided and calibration manpower is reduced.
US09672766B2 Methods for driving electro-optic displays
A bistable electro-optic display having a plurality of pixels each of which is capable of displaying at least three optical states, including two extreme optical states, is driven by the method comprising a first drive scheme capable of effecting transitions between all of the gray levels which can be displayed by the pixels; and a second drive scheme which contains only transitions ending at one of the extreme optical states of the pixels.
US09672765B2 Sub-pixel layout compensation
Devices and methods for reducing or eliminating sub-pixel layout artifacts on an electronic display are provided. One such device may include an electronic display to display image data, a processor to generate the image data, and sub-pixel layout compensation circuitry that modifies the image data to reduce or eliminate a sub-pixel layout artifact of the electronic display by modifying pixels of the image data on a sub-pixel-by-sub-pixel basis. The sub-pixel layout compensation circuitry may adjust a sub-pixel of a first color in a first pixel based at least in part on a first gradient between the sub-pixel of the first color of the first pixel and a sub-pixel of the first color of a second pixel.
US09672763B2 Pixel array and driving method thereof, display panel and display device
The present invention provides a pixel array including multiple pixel units, each of which includes two rows of sub-pixels, and each row of sub-pixels includes four sub-pixels of different colors, wherein in each pixel unit, colors of the first two sub-pixels in the previous row are the same as those of the last two sub-pixels in the next row, colors of the last two sub-pixels in the previous row are the same as those of the first two sub-pixels in the next row, and in the same row, any two adjacent sub-pixels form one pixel block. The present invention further provides a driving method of the above-mentioned pixel array, a display panel including the pixel array and a display device including the display panel.
US09672758B2 Kit for replicating an implantable prosthetic device
A kit for replicating an implantable prosthetic devices includes a model implant, a geometric tool, and an insert. The model implant may include a first curved surface, and the first curved surface may include a first cutout formed. The geometric tool may include a second curved surface having a second cutout. The geometric configuration of the second cutout may be substantially identical to the geometric configuration of the first cutout of the model implant. The insert may be configured to be engaged with both the first cutout and the second cutout.
US09672749B1 System and method for updating ILS category and decision height
A system and method is provided for updating an aircraft flight management system with approach and landing information received from a NOTAM transmission. The system and method receives an updated ILS category, updates the ILS category and updates the associated decision height/altitude. In addition, the system and method generates a notification of the NOTAM update and disregards user attempts to select an ILS category and/or decision height that is inconsistent with the NOTAM update.
US09672748B2 Deep stall aircraft landing
An aircraft defining an upright orientation and an inverted orientation, a ground station; and a control system for remotely controlling the flight of the aircraft. The ground station has an auto-land function that causes the aircraft to invert, stall, and controllably land in the inverted orientation to protect a payload and a rudder extending down from the aircraft. In the upright orientation, the ground station depicts the view from a first aircraft camera. When switching to the inverted orientation: (1) the ground station depicts the view from a second aircraft camera, (2) the aircraft switches the colors of red and green wing lights, extends the ailerons to act as inverted flaps, and (3) the control system adapts a ground station controller for the inverted orientation. The aircraft landing gear is an expanded polypropylene pad located above the wing when the aircraft is in the upright orientation.
US09672745B2 Awareness enhancing display for aircraft
Systems, methods and computer-storage media are provided for enhancing awareness in an aircraft using a touch-screen instrument panel. In one aspect, a warning is displayed peripherally in the panel in a way that attracts attention without interfering with the use of the panel for other purposes. In another aspect, a crew member is directed by highlighting through menus to a screen that enables the problem causing the warning to be corrected. In another aspect, parameters (e.g., temperatures, pressures) are displayed along with oriented graphical representations of system components. In yet another aspect, aircraft parameters are displayed in a historical context so that the user has a time-line context for a value at issue.
US09672736B2 Site map interface for vehicular application
A system and method for transferring data between an object detection system and a collision processing circuit is provided. The object detection system includes sensors configured to provide coverage of and detect movement within a predetermined area. The object detection system further includes a path predicting circuit and a plotting circuit operable to predict and plot the location of detected objects. The system further includes a map definition of the predetermined area, a grid system plotted onto the predetermined area, and environmental information relating to the predetermined area, and a series of overlays. Each overlay is plotted with the grid system and the predicted location of the detected objects. The object detection system transmits the map definition and series of overlays to the collision processing circuit so as to determine a probability of a collision.
US09672735B2 Traffic classification based on spatial neighbor model
Systems, methods, and apparatuses are described for estimating traffic conditions on road segments when no real time traffic data is available. A computing device may access a road topology comprising links from a geographic database. One of the links is selected from road topology. The computing device identifies a subset of the road topology having neighboring links that have an influential conditional probability on the selected link. In one example, the subset of the neighboring links includes parent links for the selected link, child links for the selected link, and parents of child links of the selected link. The computing device generates a traffic estimation model for the selected link using the subset of road topology and historical traffic data for the neighboring links.
US09672734B1 Traffic aware lane determination for human driver and autonomous vehicle driving system
A system, method, and computer program product for determining lane information in a road segment to drive a first vehicle to minimize travel time. According to an embodiment, navigation data of the first vehicle and at least one other vehicle in a road segment is sent to a computer server system via their respective clique leaders through a communication network. The lane information may include whether a change of lane is required, a lane to avoid, an optimum lane, and rank order of drivable lanes according to increasing order of travel time for the first vehicle to minimize travel time. The determined lane information is sent to the appropriate user device through its clique leader. The user device presents the lane information to a human driver and/or autonomous vehicle driving system of the first vehicle appropriately.
US09672729B2 Relevance determination of sensor event
Relevance determination of sensor event is disclosed. An apparatus obtains a sensor event created on the basis of sensor data generated by one or more sensors, determines relevance of the sensor event, and if the relevance of the sensor event fulfills a predetermined relevance condition, outputs, with the output interface, the sensor event according to its determined relevance.
US09672726B2 Hand hygiene compliance monitoring system
A hand hygiene compliance monitoring system includes a method and computer program product for performing sanitation compliance monitoring including receiving sanitation compliance data. The sanitation compliance data includes a zone identifier corresponding to a first device in a zone and an entity identifier corresponding to a second device attached to a mobile entity in the zone. The zone is defined by an area over which the first device and the second device communicate via one-way or two-way communication. It is determined whether the entity is compliant with a sanitation protocol associated with the zone, and a database is updated with results of the determining.
US09672725B2 Proximity-based reminders
A proximity-based reminder system includes one or more proximity detectors for determining whether a distance between two or more paired electronic devices satisfies various criteria. Data transmissions across a wide area network (WAN) are used to determine whether a distance between paired devices satisfies a first proximity condition. Transmissions across a local area network (LAN) are used to determine whether the distance between the paired devices satisfies a second proximity condition. When the first and second proximity conditions are satisfied, the proximity-based reminder system issues a reminder alert notification to one or more of the paired devices.
US09672724B2 Automatic configuration of alarm aggregations
According to another embodiment, a system for generating alarm aggregation rules is provided. The system includes a memory and at least one processor coupled to the memory. The at least one processor is configured to receive information descriptive of a set of devices, each device within the set having one or more devices within the set that are associated with the device and each device of the set being capable of entering at least one anomalous state; identify at least one type of alarm aggregation rule that applies to at least one device within the set based on one or more anomalous states that the at least one device is capable of entering; and store an association between an alarm aggregation rule of the at least one type and the set of devices.
US09672716B2 Swim-A-Sure system and device
An interactive life system for increasing the safety of person in water having a base station configured to communicate with a remote node; the base station having a first controller having a first microcontroller; and a transceiver means; wherein the base station further includes an alert for alerting a monitor, a pager; a NOAA weather receiver; wherein the remote node comprises a second controller, a second transceiver, a GPS, a buoy, a panic button, a pressure transducer, a visual indicator, a vibrating motor, and a mount; wherein the second controller comprises a second microcontroller; wherein the panic button communicates with the base station; wherein the visual indicator includes light; wherein the vibrating motor includes a mechanical indicator; and where the monitee can wear the device on the wrist.
US09672715B2 Notifications on a user device based on activity detected by an activity monitoring device
A mobile device is provided, including: a synchronization module configured to receive, at the mobile device, activity data from an activity monitoring device via a wireless connection; an activity data processing module configured to process the activity data to determine an activity metric for a user; a notification generator configured to compare the activity metric against a predefined threshold, the predefined threshold being mapped to a notification message, determine, based on the comparison, that the activity metric has reached or exceeds the predefined threshold, and access an electronic calendar associated with the user to obtain electronic calendar data; a display; and, a notification presenter configured to display the notification message on the mobile device via the display responsive to determining that the activity metric has reached or exceeded the predefined threshold, a timing of the display of the notification message being determined based on the electronic calendar data.
US09672711B2 System and method for integrated product protection
A method of preventing the theft of packaged products from a building, in which the method includes the steps of incorporating an electronic device into the packaging material for the packaged product, and configuring the electronic device to activate an alarm if the packaged product is removed from the building prior to deactivation of the electronic device. In a particular embodiment, the method further includes configuring the electronic device to impair the function or appearance of the packaged product if the packaged product is removed from the building prior to deactivation of the electronic device.
US09672710B2 Item movement tracking with three-dimensional (3D) proximity exclusions
A proximity exclusion is configured for at least one item in a commercial environment that precludes movement of the at least one item into a defined prohibited region within a structure associated with the commercial environment. Movement of the at least one item is detected within the structure associated with the commercial environment. A determination is made as to whether the movement of the at least one item results in the at least one item being located within the defined prohibited region within the structure associated with the commercial environment. In response to determining that the movement of the at least one item results in the at least one item being located within the defined prohibited region, a proximity exclusion alert is generated indicating that the at least one item is located within the prohibited region.
US09672709B2 Device and its use for deterring wearing and returning of merchandise
Provided is a device for deterring purchase-wear-return of merchandise, particularly women's dresses, by a consumer.
US09672701B2 Tactile imaging system
One embodiment of the present invention provides a tactile imaging system. The tactical imaging system includes: a receptive field tactile control unit; and a connecting module configured to connect the tactile imaging system with a host system. In addition, the receptive field tactile control unit includes: a monitoring module configured to monitor a property of a human skin; and a tactile stimulation providing module configured to provide a tactile stimulation.
US09672700B2 Task lighting system with alarm and dimming features
A temporary task lighting system used on job sites has an alarm mode. The system may be used to provide an alarm indication using the light units of the system. The alarm indication may be cycling the lights through on and off conditions or full on and dimmed conditions. Different systems and methods may be used to activate the alarm. The alarm activation may come from a typical fire alarm switch, a button on the power supply, a button on a central control computer, or a signal from an emergency response system such as a 911 system. The disclosure also provides central control for remote drivers and ballasts. The central control allows different zones of low voltage lighting systems or different zones of low voltage lights to set up, identified, and individually controlled from a central interface.
US09672689B2 Gaming system with movable ultrasonic transducer
An electronic gaming machine (EMG) includes a locating sensor generating an electronic signal based on a player's location in a sensing space. The EGM also includes a movable connector controllable by an electronic control signal. The electronic control signal controls an amount of movement of the movable connector. The EGM also includes an ultrasonic emitter configured to emit an ultrasonic field when the ultrasonic emitter is activated. The ultrasonic emitter coupled to the movable connector to allow the ultrasonic emitter to move. The EGM also includes one or more processors coupled to the locating sensor, the ultrasonic emitter and the movable connector. The processors configured to: identify a location of a player feature based on the electronic signal generated by the locating sensor; and control the movable connector and the ultrasonic emitter based on the identified location.
US09672687B2 Processing of a mobile device game-playing transaction based on the mobile device location
An exemplary method comprises receiving information associated with a game-playing transaction conducted between a user device and a game-playing terminal, wherein the game-playing transaction is associated with a request for playing a game; determining a location of the user device associated with the game; determining the user device is located in an approved location associated with the game; and processing the game-playing transaction based on determining the user device is located in the approved location associated with the game. The game-playing transaction is conducted on a first communication interface, and the information associated with the game-playing transaction is received on a second communication interface.
US09672680B2 Coin separating device
A coin separating device has a conveying device for conveying coins along a conveying section in a conveying direction from an input container, a checking device arranged on the conveying section for checking a coin conveyed along the conveying section and for providing a check result signal, a coin collecting device for collecting coins and a coin bridge device that is arranged between the coin collecting device and the conveying device and is realized to receive the check result signal and, in dependence on the check result signal, either to take over a conveyed coin from the conveying device by means of a movably arranged slide and supply it to the coin collecting device by means of the slide or not to take over a conveyed object from the conveying device such that the conveyed object passes from the conveying device to a return means of the coin separating device.
US09672678B2 Method and system of using image capturing device for counterfeit article detection
A device, system, and method of detecting counterfeit articles are provided. The method includes receiving article identifying information associated with a test article, using the article identifying information to retrieve an authentic article image associated with the test article from an image storage database, scanning the test article to capture one or more images of the test article under different wavelength illuminations, and displaying the one or more test article images and the authentic article image to allow comparison of the test article and the associated authentic article. Additionally, multiple wavelength emitting elements may be located within an image-capturing device, to provide alternate illuminations of the test article, allowing alternating capture of images highlighting different security features for providing a superimposed image. A system of counterfeit article detection is also provided.
US09672677B2 Method and apparatus for detecting magnetic signal of paper money
A method and an apparatus for detecting a magnetic signal of paper money. By using detecting a magnetic track and repairing an abnormal magnetic track, the detection method solves the phenomenon of the abnormal magnetic track, and greatly improves the recognition accuracy rate and the receiving rate of a paper money recognition apparatus. The detection method comprises: S1: acquiring original data of a paper money magnetic signal; S2: performing abnormal magnetic track detection on the original data to obtain a detection result; S3: if the detection result is an abnormal magnetic track, performing step S4 and step S5, otherwise, performing step S6; S4: repairing the original data according to a preset repair rule to obtain repaired data; S5: comparing the repaired data with a preset standard value to obtain a recognition result; and S6: comparing the original data with the preset standard value to obtain a recognition result.
US09672674B2 Systems and methods for secure lock systems with redundant access control
Systems and methods for providing secure locks having redundant access channels are disclosed. In some embodiments of the invention, the smart lock has a hardware processor, a power source, a cylinder, a button that forms a rose knob, and a rose protector. The rose knob and rose protector protect and conceal the hardware processor, the power source, and the cylinder. The rose protector forms an annular groove that slidably interlocks with the rose knob. The rose knob has a plurality of redundant access channels for receiving authentication information. The redundant access channels may include a biometric scanner for receiving biometric information, a passcode keypad for entering a token, or a wireless transceiver for receiving a token from a mobile device and transmitting a response to the mobile device. When the user cannot open the lock through the first redundant access channel, the smart lock is configured to allow access through a second access channel.
US09672673B1 Electronic locker lock system
In a system of locks, typically lockers for temporary use, but also including long-term lockers and locks in office furniture, each electronic lock has an access terminal for entry of a user's code. The electronic locks each have a processor and a programmable memory to receive inputs for setting and resetting access codes for the lock. The system includes a smartphone or other hand-held computer device, with a program for control of lock access. When locks of the system are to be set as to permitted access, or operating parameters of locks are to be adjusted, or for downloading information from the lock, information is entered into the smartphone and downloaded to a portable electronic data key. The data key is then touched to contacts of each lock to be affected, whereby the locks are set or the locks provide audit data to the smartphones.
US09672672B2 Keyless padlock, system and method of use
A keyless padlock having a padlock body, a shackle, a locking mechanism located in the body and associated with the shackle to lock the shackle to the body in a locked condition and to release at least a part of the shackle in an unlocked condition, the locking mechanism including a signal receiver, at least one control assembly and at least one actuator, the locking mechanism being unlocked upon verification of a signal including an unlock code transmitted by a mobile computing device.
US09672671B2 Relay attack prevention for passive entry/passive start systems
A keyfob is disclosed for use in detecting an attack on a vehicle. The keyfob includes a microcontroller, a wake receiver and an accelerometer. The wake receiver is configured to measure received signal strength and save the measured value in received signal strength indicator (RSSI). The accelerometer is used to generate acceleration data. The microcontroller detects an attack based on the RSSI and the acceleration data.
US09672667B2 System for processing fleet vehicle operation information
In one embodiment, a system for presenting fleet vehicle operation information in standardized forms includes a telematics module and a data standardizing module. The telematics module receives measurements related to operation of multiple vehicles in a fleet. The data standardizing module, using a first technique, estimates a first value for a parameter for at least one vehicle of the multiple vehicles based at least on the measurements. Further, the data standardizing module, using a second technique, estimates a second value for the parameter for at least one vehicle of the multiple vehicles based at least on the measurements. The second technique including using some measurement to estimate the second value different from the measurements used to estimate the first value according to the first technique. The data standardizing module outputs one or both of the first value and the second value for presentation to a user.
US09672665B1 Vehicle diagnostics
Computing systems for vehicle diagnostics are provided. In accordance with some aspects, a computing system may receive, from a vehicle (e.g., from a computing device installed in and/or at the vehicle), a diagnostic code generated by an on-board diagnostic (OBD) system of the vehicle. The computing system may determine an issue with the vehicle based on the diagnostic code and may determine, based on the issue, a remedial action for addressing the issue and a timeframe for performing the remedial action. The computing system may store data identifying the issue, the remedial action, and the timeframe in a record associated with the vehicle.
US09672664B2 Systems and methods for monitoring protection devices of an industrial machine
A system includes a machinery protection monitoring system. The machinery protection monitoring system includes a memory configured to store a plurality of alarm escalation rules associated with an operational protection function of an industrial machine, and a processor communicatively coupled to the memory and configured to utilize the plurality of alarm escalation rules. The processor is also configured to receive an indication that the operational protection of the industrial machine is at least partially suspended, compare the measurement of the one or more operational parameters to at least one of the plurality of alarm escalation rules, and generate an alarm signal based at least in part on whether the at least one of the plurality of alarm escalation rules is satisfied. The alarm signal includes an indication of an adverse operational condition of the machinery protection monitoring system.
US09672660B2 Offloading augmented reality processing
A system and method for offloading augmented reality processing is described. A first sensor of a server generates a first set of sensor data corresponding to a location and an orientation of a display device. The server receives a request from the display device to offload a combination of at least one of a tracking process and a rendering process from the display device. The server generates offloaded processed data based on a combination of at least one of the first set of sensor data and a second set of sensor data. The second set of sensor data is generated by a second sensor at the display device. The server streams the offloaded processed data to the display device.
US09672653B2 Stereo viewpoint graphics processing subsystem and method of sharing geometry data between stereo images in screen-spaced processing
A stereo viewpoint graphics processing subsystem and a method of sharing geometry data between stereo images in screen-space processing. One embodiment of the stereo viewpoint graphics processing subsystem configured to render a scene includes: (1) stereo frame buffers configured to contain respective pixel-wise rendered scene data for stereo images, and (2) a sharing decision circuit operable to determine when to share geometric data between the stereo frame buffers for carrying out screen-space effect processes to render the scene in the stereo images.
US09672652B2 Method for processing a computer-animated scene and corresponding device
The invention is related to a method for processing a computer-animated scene, the computer-animated scene being represented with at least an animation graph, at least an animation graph comprising a plurality of nodes connected by paths, the paths being representative of dependencies between the nodes, at least an event being associated with each node, a first information representative of the type of each event being associated with each node. As to optimize the parallelization of the nodes, the method comprises a step of classifying the nodes in at least a first batch and at least a second batch according to the first information associated with each node, at least a first batch comprising nodes to be evaluated in parallel and at least a second batch comprising nodes to be evaluated sequentially.
US09672650B2 Image processing apparatus, image processing method, and storage medium
An image processing apparatus includes: a digital processing unit that performs digital processing on accepted one or at least two images, thereby acquiring one or at least two processed images; a physical property information acquiring unit that acquires physical property information, which is information relating to a physical property that has been lost compared with one or more physical properties of a target contained in the images, in the one or at least two processed images; a physical property processing unit that performs physical property processing, which is processing for adding a physical property corresponding to the physical property information, using the one or at least two processed images; and an output unit that outputs a processed image subjected to the physical property processing. Accordingly, it is possible to reproduce lost physical properties of a target expressed in an image, to the fullest extent possible.
US09672645B2 Method to display a graph containing nodes and edges in a two-dimensional grid
A graph display system that represents graph nodes as grid cells in a two-dimensional grid. Graph edges are represented by placing the edge's nodes in adjacent grid cells, thus eliminating the entanglement of edges that are typically drawn as lines between scattered nodes. Relatedness of two nodes sharing an edge is indicated by the edge's weight. The display system prioritizes placement of higher weight edges such that more related information is grouped together in nearby grid cells. Any graph with n nodes and e edges can be displayed and browsed.
US09672643B2 Image processing LSI and image processing program
When graphics computations are to be performed to calculate the display data of a figure to be drawn within a frame that is formed of a plurality of lines in accordance with input vector data, the present invention reduces the storage capacity of a RAM to which a work area for storing intermediate data is allocated. When the graphics computations are to be performed, the frame in which the figure is to be displayed is segmented into a plurality of drawing areas for each of the lines. As regards the work area for storing the intermediate data, the same work area is allocated to all the drawing areas. The graphics computations for calculating the intermediate data of the individual drawing areas are sequentially performed by repeatedly using the same work area.
US09672642B2 Apparatus and method of performing tile binning of bezier curve
An apparatus and method for tile binning with respect to a Bezier curve. The apparatus may include a curve identification unit to identify a Bezier curve included in input data, a bounding box generation unit to generate a plurality of bounding boxes corresponding to the Bezier curve, and a tile binning unit to perform tile binning with respect to the Bezier curve based on the plurality of bounding boxes.
US09672640B2 Method for interactive manual matching and real-time projection calculation in imaging
Methods and systems are proposed herein for performing manual matching of generated digitally reconstructed radiographs with acquired verification images efficiently without intensive processing and/or memory consumption or hardware requirements. According to one aspect of the claimed subject matter, a system is provided that includes a computing workstation, communicatively coupled to both a data storage device and an image acquisition device. Real time images acquired by the image acquisition device are presented to the user along with one or more digitally reconstructed radiographs (DRRs)—generated using dynamically selected rendering techniques—from previously acquired image data. The user is able to verify the DRRs as a match to the real time image, or, alternately, to dynamically generate additional DRRs more suitable by actuating a portion of the generated DRR. Based on the user actuation, a new DRR is generated and presented to the user for verification.
US09672633B2 Image coding method, image decoding method, image coding apparatus, and image decoding apparatus
According to an embodiment, an image coding method is for coding an image including a luminance component and color difference components. The method includes acquiring a reference image; and generating a predicted image by interpolating the luminance component and the color difference components in the reference image according to a motion vector. If a size of a block, which is designated as a unit of the interpolation, is equal to or smaller than a predetermined first threshold value, the generating includes inhibiting a bi-directional prediction, and performing only a uni-directional prediction to generate the predicted image according to the motion vector.
US09672625B2 Method and apparatus to automatically implement a selection procedure on image data to generate a selected image data set
In a method and apparatus to automatically generate a selected image data set from an entirety of medical measurement data of an examination subject, the entirety of the measurement data of the examination subject is received as input data, and at least a portion of the measurement data is automatically analyzed with regard to a number of specific, topologically representative content feature parameter values of the examination subject selected measurement data from the entirety is made, with the selected data associated with defined, specific, topologically representative content feature parameter values. The selected measurement data are assembled into a selected image data set, as output data.
US09672621B2 Methods and systems for hair transplantation using time constrained image processing
Methods and systems are described for hair transplantation and other surgical procedures on a body surface. Specifically, methods and systems for computer-implemented and/or robotic hair transplantation and other surgical procedures, using time constrained image processing techniques are described. In various examples, multiple images of a body surface may be divided into overlapping sub regions for comparison. In various other cases, a percentage of an image of a body surface to be processed may be adjusted based on a time constraint. In some implementations, the output of one of these methods may be used as input for the other method.
US09672619B2 Image processing device, information storage device, and image processing method
An image sequence acquisition section acquires an image sequence including a plurality of images. A processing section performs an image summarization process that acquires a summary image sequence based on first and second deletion determination processes that delete some of the images included in the acquired image sequence. The processing section sets an attention image sequence including one at least one attention image included in the plurality of images, selects a first reference image from the attention image sequence, selects a first determination target image from the plurality of images, and performs the first deletion determination process that determines whether the first determination target image can be deleted based on first deformation information that represents deformation between the first reference image and the first determination target image. The processing section sets a partial image sequence from the image sequence, a plurality of images that have been determined to be allowed to remain by the first deletion determination process being consecutively arranged in the partial image sequence. The processing section selects a second reference image and a second determination target image from the partial image sequence, and performs the second deletion determination process that determines whether the second determination target image can be deleted based on second deformation information that represents deformation between the second reference image and the second determination target image.
US09672618B1 System and process for dyslexia screening and management
A Dyslexia screening and management system and process for individual user, community and group in general are described. An electronic media based tests for reading, writing, drawing, spelling and listening skills, family drawing, and letter writing test, which uses text, audio, video, and gaze movement to detect a set of symptoms of having dyslexia is described. Multi-modal, language-independent screening test modules have been developed, which gives indications of further dyslexia diagnosis tool. The multimedia retrieval framework is presented to accelerate and ease the process of testing dyslexia at the global level, and to identify and auto assess potential dyslexic patterns and to accumulate huge collection of multimedia test data for in-depth clinical dyslexia pattern analysis.
US09672605B2 Image processing device and image processing method
To increase the processing speed when median processing in the time direction is performed on color images, pixel values of each channel (R, G and B values) are extracted from multiple temporally consecutive frame images; subsequently, identifiers (index numbers) corresponding to frame images from which the pixel values are extracted are assigned to the pixel values; subsequently, a sorting process is performed on a set of pixel values of one channel (G values) to obtain an identifier assigned to a median value thereof; subsequently, a pixel value to which an identifier identical with that assigned to the median value is assigned is selected as a median value of each channel; and subsequently, a median image is generated on the basis of the median value of each channel obtained for each pixel.
US09672597B2 Method for reducing noise in sequences of fluoroscopic images
A method for reducing noise in flouroscopic images by detection of the traits in the curvelet domain, matching of the detected traits and time-domain filtering adapted to the type of coefficients associated with a trait. The method uses the discrete curvelet transforms of the images from a sequence. The denoised coefficients are detected, then transmitted to a step for locally matching the traits, the matched data subsequently undergo a step for time-domain filtering allowing the movement of the objects to be preserved in the image and a step for a 2D IDCT (Inverse Discrete Curvelet Transform) in order to produce the final image.
US09672596B2 Image processing apparatus to generate a reduced image of an endoscopic image
A filtering unit applies a filter for suppressing a high-frequency component to a second image generated by performing image processing including at least enlargement processing on a first image captured by using an endoscope. An image reducing unit generates a third image by performing reduction processing on the second image to which the filter has been applied. A filter setting unit sets a characteristic of a filter based on information on a maximum frequency component that can be reproduced in at least the first image and information on a maximum frequency component that should be reproduced in the third image.
US09672588B1 Approaches for customizing map views
A computing device can present a map of a geographic region. The computing device can determine that a user operating the computing device has performed a particular action. The particular action can be, for example, a particular gesture. The computing device can determine that a distance between the user's face and the display screen of the computing device is within a threshold distance. If the user's face is within a threshold distance of the display screen, the map can be displayed in a dynamic view mode. While in the dynamic view mode, the map for the geographic region includes at least one additional map label for a feature that is located in the geographic region and navigation of the rendered map is disabled.
US09672586B2 Image synthesis method with DSP and GPU
This patent application focuses on partitioning the computation to perform the image processing on the DSP, communicate the results to the GPU in an optimized manner, and use the GPU to render 3D information to the display. This invention solves the problem of seamlessly merging live streams from plural automotive cameras into a 3D display that can be rotated to see different view points. This purpose is achieved by partitioning the computation task between a digital signal processor (DSP) for image processing and a graphics processing unit (GPU) for rendering and display. This invention also includes meta data structures for communication of results from the DSP to the GPU.
US09672576B2 System and method for enabling effective work force management of a smart grid
A system and a method are provided for enabling effective work force management of a smart grid. The method includes receiving a first Session Initiation Protocol (SIP) message comprising a state of an electrical component on an electrical grid; and notifying a third party of the state of the electrical component by sending a second SIP message.
US09672573B2 Graphical user interface for facilitating allocation of variable compensation
Described above is a system for allocating variable compensation to a group of individuals. The system displays objective financial statistics associated with individuals, and subjective factors to be set by a user, where the system can convert subjective factors set by the user into a value. The user can then select base and variable compensation values for each individual. Other details are described herein.
US09672570B1 Telematics based on handset movement within a moving vehicle
At least a system for providing telematics data associated with a vehicle being driven by a driver is described. The vehicular telematics data may be obtained by tracking the movements of a wireless communications device of a driver of the vehicle. The telematics data may provide, among other things, speed, acceleration, deceleration, times of operation, duration of operation, mileage driven per day, and day of the week the vehicle has been used. At least a system for determining risk behavior of a driver is also described. While a vehicle is being driven, data is obtained related to the position and movement of a wireless communications device. The data may indicate the type of behavior exhibited by the driver while the vehicle is being driven.
US09672565B2 High speed processing of financial information using FPGA devices
Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.
US09672562B1 Price determination in an auction system
An apparatus for computing a bid price for a plurality of items includes an input portion, a processing portion, and an output portion. The input portion is adapted to electronically receive a bid for an online auction listing for a plurality of items, the bid including a limit price and an initial bid price for each of the plurality of items, and a total bid price for an entirety of the plurality of items. The processing portion is adapted to electronically compute a bid price for each of the plurality of items, such that a sum of the computed bid prices for the plurality of items is substantially equal to the total bid price. The output portion is adapted to electronically transmit the computed bid prices for the plurality of items to an online auction portion, the online auction portion accepting the bid in accordance with the computed bid prices.
US09672561B1 Fail-safe ordering
An action submitted via a network may be fulfilled despite the network, or a website accessible via the network, experiencing an error that prevents processing of the action when the action is received. In one example, the user that submitted the action may receive a confirmation page indicating that the action has been received. Transaction data may be retrieved based at least in part on the action and/or the user that submitted the action. Once the transaction data is stored in a queue, the transaction data may be processed either automatically or manually. Subsequently, the action may be fulfilled without the user needing to resubmit the action. Alternatively, the action may be optimistically fulfilled prior to the action being processed.
US09672560B2 Distributed order orchestration system that transforms sales products to fulfillment products
A distributed order orchestration system provides a plurality of representations of a product, such as a sales-centric representation of a product and a fulfillment-centric representation of a product. The distributed order orchestration system captures an order associated with the product, and creates a sales order based on the sales-centric representation of the product. The distributed order orchestration system then transform the sales order into a fulfillment order, where the fulfillment order is based on the fulfillment-centric representation of the product. As part of the transformation, product information that is associated with the sales order is transformed into product information that is associated with the fulfillment order, using one or more product transformation rules.
US09672559B2 Methods and systems for a digital interface for displaying retail search results
A user interface for displaying retail search results is disclosed. The system and methods allow users to search for a plurality of retail items while simultaneously viewing a plurality of search results for each of the plurality of retail items. This interface allows users to easily compare the search results for each retail item, and to purchase a plurality of retail items simultaneously. In one example of the present disclosure, users may enter a plurality of retail items into a shopping list. The system may then display multiple results for each item on the shopping list in a carousel-like user interface, so users may view a plurality of results for a plurality of items simultaneously.
US09672554B2 Methods and systems for deriving a score with which item listings are ordered when presented in search results
Methods and systems for analyzing, ordering and presenting item listings are described. In one example embodiment, a search query is processed to identify item listings satisfying the search query. Then, for each item listing that satisfies the search query, a ranking score is derived and assigned to the item listing. The ranking score is based in part on a relevance score, a listing quality score and a business rules score (or, adjustment factor). Finally, the item listings are ordered, based on their corresponding ranking score, and presented in order in a search results page.
US09672553B2 Searchable texture index
Electronic content that has a tactile dimension when presented on a tactile-enabled computing device may be referred to as tactile-enabled content. A tactile-enabled device is a device that is capable of presenting tactile-enabled content in a manner that permits a user to experience tactile quality of electronic content. In one example embodiment, a system is provided for generating content that has a tactile dimension when presented on a tactile-enabled device.
US09672550B2 Fulfillment of orders for items using 3D manufacturing on demand
Methods and systems can be provided for providing items manufactured on demand to users. A user request for an item can be received. The item can have 3D manufacturing instructions associated therewith. A delivery method for the item can be determined. A manufacturing apparatus can be selected to manufacture the item based on the 3D manufacturing instructions. Instructions can be sent to the manufacturing apparatus to manufacture the item based on the 3D manufacturing instructions. Delivery instructions can be provided for delivering the item according to the delivery method.
US09672549B2 System and method for providing customer service help
Systems, methods, and computer-readable storage media for providing customer service help. The system first receives, from a user device, contact information associated with the user device, wherein the contact information is received via a customer service terminal having a user interface configured to wirelessly receive data from the user device when the user device is within a distance of the customer service terminal. In response to receiving the contact information, the system then identifies a customer service representative associated with the customer service terminal. The system then sends the contact information to a remote device associated with the customer service representative. The customer service representative can then initiate a customer service communication between the user device and the remote device in order to provide customer service help to the user associated with the user device.
US09672548B2 Reputation management systems and methods
A method and system to manage user reputations is described. In some embodiments, a first picture is received from a first user and a second picture is received from a second user. The first picture and the second picture are associated with an in-person transaction related to an item. The method determines whether both the first picture and the second picture identify the item. The method further determines whether both the first picture and the second picture were taken at a similar geographic location. If the first picture and the second picture identify the item and were taken at a similar geographic location, transaction feedback is requested from the first user. A reputation score related to the second user is updated based on transaction feedback received from the first user.
US09672545B2 Optimizing license use for software license attribution
In one embodiment, a system for license management includes logic adapted for arranging entitlement slots under a plurality of licenses, each entitlement slot being configured for affording entitlement to use of an instance of a software application during a particular time frame, logic adapted for determining a license use signature from recorded license attribution information, logic adapted for receiving a notification of an instance not attributed to a license, and logic adapted for attributing the non-attributed instance to one of the plurality of licenses as a function of the license use signature, wherein each license has an entitlement value defining a maximum number of entitlement slots that may be attributed to that license during the time frame and any given instance of the software application may consume any number of the entitlement slots including zero entitlement slots.
US09672544B2 Method and system for providing accounting services
A computerized system and method for preparing at least one tax return, including, but not limited to: accepting tax information, by at least one accounting module, for the at least one tax return from at least one user; processing the tax information, at the at least accounting module, so that at least one third party tax software application can utilize the tax information to calculate the at least one tax return; and providing calculated results of the at least one tax return, from the at least one accounting module, to the at least one user; wherein third-party software is utilized to calculate the at least one tax return so that the at least one accounting module does not need to calculate the at least one tax return.
US09672543B1 System and method for device valuation
Described herein is a platform and method for providing a device valuation for an electronic device based on parameter values of the electronic device. The method may comprise obtaining a model information of the electronic device and identifying a base value of the electronic device. In some embodiments, a device specific performance evaluation may be executed on a hardware component contained with the electronic device. Upon execution of the performance evaluation, a set of parameter values may be generated using input collected with respect to the performance evaluation. A valuation of the electronic device may subsequently be generated based upon the base value and the set of parameter values.
US09672541B2 Visual tag editor
According to various embodiments, techniques and mechanisms described herein facilitate the editing of computer programming tags associated with a website. A user interface displaying a representation of a website may be presented on a display screen. The representation may include a plurality of webpage identifiers that each identifies a respective webpage associated with the website. The representation may also include a plurality of active tag indicators that are each associated with a respective one of the webpages. Each active tag indicator may identify a respective portion of computer programming code included in the respective webpage with which the active tag indicator is associated. User input indicating an editing action to be performed with respect to one or more of the computer programming code portions may be received, and a message identifying the editing action may be transmitted via a communications interface.
US09672538B1 Delivering personalized content based on geolocation information in a social graph with sharing activity of users of the open web
A system receives geographic information from devices to determine and deliver relevant advertisements or personalized content for consumers. This ties a user's real-world location, with virtual leads (e.g., advertisements). The system uses geographical information gathered by mobile devices and saves the geographical information to consumer profiles. For example, the system can use different wireless radios present on mobile devices to gather different types of geographical information. Some radios include cellular, Bluetooth, global positioning system (or GPS), Wi-Fi, near field communications (or NFC), and other radios.
US09672537B1 Dynamic content control in an information processing system based on cultural characteristics
A dynamic content controller is configured for communication with one or more data sources. The dynamic content controller comprises an analytics engine and a personalization engine coupled to the analytics engine. The analytics engine is configured to analyze cultural data collected from the one or more data sources during a current content browsing session. The personalization engine is configured to adapt content to be presented based at least in part on the analysis of the cultural data. The adaptation of the content to be presented is performed during the current content browsing session.
US09672536B2 Customized vCards
Methods and systems provide customized electronic cards, such as customized vCards. Each vCard can be customized, such as with respect to a particular recipient. Thus, desired specific information can be provided to the recipient and not provided to anyone else who receives a vCard from a user. In this manner, a unique communication between the user and the recipient can be defined. Different vCards, each containing some common information and some unique information, can be communicated to different recipients.
US09672534B2 Preparing content packages
Preparing a content package by determining a requesting user profile based on the requesting user identity. This includes calculating an inclusion value for a content file based on at least one factor. The factor may be a social networking factor. The social networking factor is based on a profile attribute linking the requesting user identity to at least one friend user identity and a content rating attribute linking the content file to the friend profile. Other factors are a content aging factor based on a content age value and a request length factor based on a content length value. The calculated inclusion value is compared to an inclusion condition. If the calculated inclusion value satisfies the inclusion condition, incorporating the content file into the content package.
US09672532B2 Monetizing downloadable files based on resolving custodianship thereof to referring publisher and presentation of monetized content in a modal overlay contemporaneously with download
The monetization of downloadable files associated with a custodial host site based on resolving custodianship to a referrer publisher with subsequent presentation of monetized content within a modal overlay is disclosed. A request from a client device has a resource identifier and a referrer publisher identifier. The request for the downloadable file is evaluated against one or more publisher and custodianship policy rules, which relate to a file extension of the downloadable file, a format of the resource identifier, a custodial domain on which the downloadable file is stored, and a referral domain as specified in the referrer publisher identifier. When custodianship is resolved, a modal overlay on which monetized content is incorporated is presented on the client device. The modal overlay is concurrently displayed with the transfer of the downloadable file to the client device.
US09672528B2 System and method for tracking and rewarding media and entertainment usage including substantially real time rewards
The present invention relates to systems and methods for rewarding entertainment consumers, and more specifically to a system and method for rewarding people for watching or otherwise engaging in various forms of media and entertainment (e.g. broadcast TV, on-demand TV, games, live entertainment, movies, and radio) to promote loyalty to or improve recognition of all entertainment, while collecting useful data about the media consumption habits as well as the rewards consumption patterns associated with those consumers.
US09672526B2 Systems and methods for tailoring marketing
The systems and methods may be used to recommend an item to a consumer. The methods may comprise determining, based on a collaborative filtering algorithm, a consumer relevance value associated with an item, and transmitting, based on the consumer relevance value, information associated with the item to a consumer. A collaborative filtering algorithm may receive as an input a transaction history associated with the consumer, a demographic of the consumer, a consumer profile, a type of transaction account, a transaction account associated with the consumer, a period of time that the consumer has held a transaction account, a size of wallet, and/or a share of wallet. The method may further comprise generating a ranked list of items based upon consumer relevance values, transmitting a ranked list of items to a consumer, and/or re-ranking a ranked list of items based upon a merchant goal.
US09672525B2 Identifying related information given content and/or presenting related information in association with content-related advertisements
The usefulness of content (target content), such as advertisements, may be increased by determining additional content and providing such additional content in association with the content. The target content may be text, a Web page, a URL, a search query, etc. The additional content might be related suggested queries (e.g. “Try a search for ——————”), news articles (or excerpts or summaries thereof), reviews (or excerpts or summaries thereof), advertisements, user group messages, etc.
US09672522B2 System and method for capturing and transferring information onto a gas cylinder using a QR code
The present invention generates and places a Quick Response (QR) matrix barcode on a Certificate of Analysis (COA) and/or label placed on a gas cylinder at a vendor's facility. The gas cylinder is then delivered to a customer. The customer can download onto his/her mobile device an Application from the vendor, by way of a communications network. Using the Application, the QR code can be scanned, decoded, and viewed by the customer. The customer can also download the decoded information into a database, or upload the same information to a third party's database. The information remains accurate, starting at the vendor's facility, arriving at the customer's facility and, finally, reaching the third party's facility. The information is securely transferred, without any possibility of making a mistake in the information transfer.
US09672521B1 Reformatting legacy system work orders with highlighted process compliance
A data system comprises a legacy system for storing work orders and process data; and a computer-based interface module for retrieving the work orders from the legacy system, reformatting the retrieved work orders to highlight words corresponding to process compliance and insert hyperlinks to process data referenced by the work orders, and presenting the reformatted work orders with the highlighted words and the hyperlinks.
US09672514B2 Systems and methods for conducting transactions and communications using a trusted third party
Systems and methods are provided for performing transactions and managing communications using a trusted third party. In one embodiment, a sender transfers an encrypted version of a file (such as a digitally encoded audio track, movie, document, or the like) to someone who wishes to receive it. The receiver computes a first hash of at least a portion of the encrypted data content, and sends the first hash to a third party configured to compare at least a portion of the first hash to at least a portion of a second hash. The receiver receives a file decryption key from the third party, and decrypts at least the portion of the received encrypted data content with the decryption key. In some cases, multiple hashes of the encrypted data content may be computed, each using a different portion of the encrypted data content.
US09672513B2 Cloud based payment method
A cloud based payment method for payment at a merchant's electronic cash register (202) comprising the steps of: —upfront: A. registering payment credentials (101) of a user; —at check-in of a store of a participating merchant: B1. launching a cloud payment application (211) on a mobile terminal (201) to establish connectivity with a cloud payment service (100); —and at check-out at an electronic cash register (202): C1. identifying (221, 222; 321, 323) the user with the cloud payment service (100) through an identification shared with the cloud payment service (100) via the electronic cash register (202) or via the cloud payment application (211); C2. communicating (222; 322) an amount payable from the electronic cash register (202) to the cloud payment service (100); C3. communicating (223; 324) the amount payable from the cloud payment service (100) to the cloud payment application (211); C4. receiving (224; 325) confirmation of the amount payable from the user; C5. obtaining (225; 326) payment authorization using the payment credentials (101); and C6. confirming (226; 327) payment from the cloud payment service (100) to the electronic cash register (202).
US09672508B2 Over the air update of payment transaction data stored in secure memory
A system, apparatus, and method for processing payment transactions that are conducted using a mobile device that includes a contactless element, such as an integrated circuit chip. The invention enables the updating, correction or synchronization of transaction data maintained by an Issuer with that stored on the device. This is accomplished by using a wireless (cellular) network as a data communication channel for data provided by an Issuer to the mobile device, and is particularly advantageous in circumstances in which the contactless element is not presently capable of communication with a device reader or point of sale terminal that uses a near field communications mechanism. Data transferred between the mobile device and Issuer may be encrypted and decrypted to provide additional security and protect the data from being accessed by other users or applications. If encryption keys are used for the encryption and decryption processes, they may be distributed by a key distribution server or other suitable entity to a mobile gateway which participates in the data encryption and decryption operations.
US09672506B2 Product identification apparatus with dictionary registration
A product identification apparatus includes a storage device which stores a dictionary including reference data of each of a plurality of products stored in association with identification information of the product, an imaging section which captures image data of a target product, and a processor which performs a dictionary registration process. The processor extracts reference data of the target product from the image data captured by the imaging section. The storage device adds the extracted reference data to previously stored reference data in association with the identification information of the target product. Alternatively, the storage device stores the extracted reference data in association with the identification information of the target product when no reference data is previously stored in association with the identification information of the target product.
US09672491B2 Virtual office environment
A system and method for monitoring remote employees, having a computer for a user to perform job related tasks, wherein the computer is enabled to record various data regarding the user's use of the computer, and a network to transmit the various data to a storage unit, to allow the data to be accessed by an employer.
US09672487B1 Systems and/or methods for providing enhanced control over and visibility into workflows where potentially sensitive data is processed by different operators, regardless of current workflow task owner
Certain example embodiments relate to systems and/or methods for providing enhanced control over potentially sensitive data sharable among and/or between different parties. For example, certain example embodiments provide views into computer-enabled workflows managed by external parties, including views into what sensitive data has been accessed, who has accessed it, etc., e.g., throughout the lifecycle of a product granted on the basis of an analysis of such data. A computer-enabled system for automatically assessing received sensitive data in accordance with one or more digitized rule sets also is provided in certain example embodiments, as are computer-mediated tools for helping to automatically, semi-automatically, and/or manually resolve issues detected in the assessments, e.g., via enhanced communication and collaboration, among and/or between parties to a transaction, as well as third-parties who indirectly are involved in the transaction. The data remains secure and traceable, e.g., in accordance with its provider's specifications.
US09672485B2 Supply chain network strategic design system
A system is provided that designs a supply chain network. The system identifies a service level agreement metric definition. The system further generates a grid including cells, where the grid is located over a representation of a geographical region. The system further computes a service level agreement metric for each cell of the grid using the service level agreement metric definition. The system further selects cells that have the largest service level agreement metrics and that have not been previously selected. The system further positions a supply chain network resource at a center of the selected cells. The system further computes a service level agreement based on the service level agreement metric of the selected cells.
US09672482B2 System and method for automatic objective reporting via wearable sensors
One embodiment of the present invention provides a system for automatically reporting progress in completing objectives and goals of a plan. During operation, the system receives data indicating user selection and/or configuration of a plan with one or more goals, objectives, and/or milestones. The system obtains data generated by sensors in a sensing device and/or a mobile device. The sensors generate physiological data or data from detecting activity or environment associated with the user. Next, the system analyzes the data to determine whether the user has completed an objective, milestone, or goal of the plan. If the system determines that the user has completed an objective, milestone, or goal of the plan, the system pushes an alert to the mobile device indicating that the user has completed the objective, milestone, or goal.
US09672480B2 Adaptive and dynamic data synchronization system for managing data and inventory
A system and method for adaptive and dynamic synchronization includes a data synchronization controller which enables synchronization of a plurality of different data types between a main computer and one or more remotely disposed computer elements. The controller includes an orchestrator which responds to requests for data synchronization for components in accordance with predetermined policies maintained by a policy management system. A synchronization interface is controlled by the orchestrator in accordance with the policies to select a synchronization engine to service requests for synchronization of different data types from the orchestrator. Synchronization may be handled for on demand and/or for on schedule requests for synchronization in the policy-based system and method.
US09672477B1 Exam scheduling with customer configured notifications
An exam scheduling device comprises a notification module configured to determine notifications for display to a scheduler in the process of scheduling an exam for a patient. The notifications presented to a particular scheduler may be selected based on one or more exam parameters associated with a patient, for example. Thus, only those notifications that are relevant to the exam parameters associated with a particular patient's exam are presented to the scheduler, and the scheduler is required to respond to only those notifications that a scheduling administrator has determined require a response.
US09672471B2 Systems, devices, and methods for detecting occlusions in a biological subject including spectral learning
Systems, devices, and methods are described for detecting an embolus, thrombus, or a deep vein thrombus in a biological subject.
US09672465B2 Solving vehicle routing problems using evolutionary computing techniques
According to one exemplary embodiment, a method for solving combinatorial optimization problems is provided. The method may include receiving a plurality of problem instance parameters associated with a graph. The method may also include determining a dynamic path change indicator exists. The method may then include initializing the graph based on the determining the dynamic path change indicator does not exist. The method may further include inserting a placeholder node and at least one placeholder node edge based on the determining the dynamic path change indicator exists. The method may also include reinitializing the graph with the inserted place holder node and the at least one placeholder node edge. The method may then include initializing the reinitialized graph. The method may further include executing a hybrid algorithm on the initialized graph or on the reinitialized graph, wherein the hybrid algorithm comprises an ant colony optimization algorithm and a genetic algorithm.
US09672458B2 Creation and management of dynamic quick response (QR) codes
In response to detecting a configured quick response (QR) code change event in a retail environment, a changed dynamic QR code is displayed that includes an encoded new unique value. The changed dynamic QR code is changed from a previously-displayed dynamic QR code and is changed based upon a set of contemporaneous data elements associated with an item displayed in the retail environment.
US09672454B2 Image processing apparatus for rendering plurality of objects by dividing plurality of objects into plurality of groups, and image processing method
An image processing apparatus for rendering objects group by group, which divides a plurality of objects in an application range of an original clip command into a first group and a second group, wherein the image processing apparatus applies, in the rendering of the first group, a clip process based on a first clip command corresponding to the original clip command to a part of the plurality of objects divided into the first group, and applies, in the rendering of the second group, a clip process based on a second clip command corresponding to the original clip command to a rest part of the plurality of objects divided into the second group.
US09672453B2 Data processing apparatus and print data generating method determining a dot arrangement pattern using a code table
A data processing apparatus includes a holding unit holding a code table, in which each of the codes in the table determines the dot arrangement pattern, a determining unit determining a predetermined number of first offset values which is power of 2, the first offset values denoting a number of pixels by which an arrangement of the codes is shifted in the code table, a table generating unit, in a case where a size of the code table is not power of 2 and the determining unit determines the first offset value wherein a quotient and a remainder when the predetermined number is divided by the size is 1 or more, determining a second offset value wherein the quotient is zero, as substitute for the determined first offset value, and to generate the code table to which an offset is made with the second offset value.
US09672451B2 Printing system including a printing apparatus and an information processing apparatus that is capable of communicating with the printing apparatus control apparatus, method of controlling the same, and storage medium
According to a print control apparatus and a method of controlling the same of the present invention, when the printing apparatus is in a power saving state, when an instruction for registering in the printing apparatus sheet information stored in a storage unit in association with a sheet feeder of the printing apparatus is received, the sheet information is registered in a list, and when the printing apparatus returns from the power saving state, control is performed so that sheet information registered in the list is transmitted to the printing apparatus.
US09672450B2 Image recording apparatus and control method therefor
An image recording apparatus according to this invention analyzes image data to be printed, and generates sequence information for defining the moving range of each scanning motion of a recording head and the conveyance amount of a recording medium. The apparatus divides a recording area defined by the generated sequence information into areas so that the processing amounts of a plurality of processing units capable of parallelly executing processes are equal to each other, distributes data of the divided areas to the processing units, and causes each of the processing units to generate recording image data. The apparatus performs recording by controlling driving and a scanning motion of the recording head and conveyance of the recording medium based on the recording image data obtained by the processing units.
US09672449B2 Apparatus, system, and method for calibration of a media processing device
A method, apparatus, and system for calibration of a media processing device are provided. The method may include providing a calibration sub-routine where the calibration sub-routine includes a plurality of calibration operations to be performed in sequence. The method may further include associating an audible note with each calibration operation and generating the audible note for each calibration operation as each respective calibration operation is performed, where the audible note is generated by a frequency of operation of a motor. The audible note associated with one calibration operation may be different from the audible note associated with another calibration operation.
US09672448B2 Pruning and label selection in Hidden Markov Model-based OCR
Systems and techniques are provided for pruning a node from a possible nodes list for Hidden Markov Model with label transition node pruning. The node may be a label transition node. A frame may be at a predicted segmentation point in decoding input with the Hidden Markov Model. The node may be scored at the frame. The node may be pruned from the possible nodes list for the frame when score for the node is greater than the sum of a best score among nodes on the possible nodes list for the frame and a beam threshold minus a penalty term. A possible nodes list may be generated for a subsequent frame using label selection. A second node may be pruned from the possible nodes list for the subsequent frame with early pruning.
US09672431B2 Object detection
In an example detection system for vehicles or other objects of interest, objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor may perform run-length encoding (RLE) to provide detected edges. The image may then be scanned from the bottom up to identify vertical clusters or “stacks” or RLEs. Vertical clusters with low vertical density may be eliminated as poor vehicle candidates. Vertical clusters not eliminated may then be processed with a histogram of gradients algorithm, and confirmed with a support vector machine algorithm. A range to the nearest object may also be calculated, and a warning provided if the object is too close.
US09672429B2 Boundary line recognizer device
This invention is provided with: a camera for capturing the image of a travel path; an edge point extraction unit for extracting edge points on the basis of the brightness of an image captured by the camera; a candidate line extraction unit for extracting, on the basis of the succession of the extracted edge points, a candidate line for a boundary line demarcating the travel path; a frequency calculation unit for calculating, on the basis of edge points belonging to the candidate line extracted by the candidate line extraction unit, the frequency distribution of the edge points for a parameter that specifies the width of the boundary line; a probability generation unit for calculating, on the basis of the frequency distribution calculated by the frequency calculation unit, the distribution for the probability that the candidate line at the parameter is the boundary line; and a boundary line recognition unit for recognizing the boundary line on the basis of the probability distribution calculated by the probability generation unit.
US09672426B2 Intelligent monitoring system
An intelligent monitoring system for care place is illustrated. The system includes a thermal camera capturing a thermal image of the care place; an image processing unit obtaining user's position and number of user according to region in which temperature is higher than a preset temperature in the thermal image; a temperature recording unit extracting and records user's temperature from the thermal image. When there is only one user, a abnormal event determining unit of the system determines whether an abnormal event occurs according to user's temperature changing rate. When there are several users, the abnormal event determining unit determines whether the abnormal event occurs according to both of the temperature changing rates of the users and an average temperature of the users. If the abnormal event occurs, the warning unit generates a warning signal.
US09672424B2 Generation of high resolution population density data sets through exploitation of high resolution overhead imagery data and low resolution population density data sets
Utilities (e.g., systems, methods, etc.) for automatically generating high resolution population density estimation data sets through manipulation of low resolution population density estimation data sets with high resolution overhead imagery data (e.g., such as overhead imagery data acquired by satellites, aircrafts, etc. of celestial bodies). Stated differently, the present utilities make use of high resolution overhead imagery data to determine how to distribute the population density of a large, low resolution cell (e.g., 1000m) among a plurality of smaller, high resolution cells (e.g., 100m) within the larger cell.
US09672421B2 Method and apparatus for recording reading behavior
A method and an apparatus for recording reading behavior are provided. A movement trajectory of a user's eye is tracked based on an eye-tracking procedure, so as to calculate reading time of a gazing part of an electronic document when it is detected that sight of an eye leaves the gazing part, or when it is detected that the eye keeps gazing the electronic document and reading of the gazing part is finished. And the reading time is recorded to a storage space corresponding to the gazing part.
US09672419B2 Detection of spurious information or defects on playing card backs
Methods and systems detect markings or flaws on the backs of playing cards. The method includes: providing ambient radiation at a gaming table and reflecting some of that radiation off a back surface of a playing card; capturing reflected radiation with a radiation sensor; the radiation sensor transmitting signals based on the reflected radiation captured by the radiation sensor; the transmitted signals providing data that contains image data of the back of the playing card; and displaying an image of the back of the playing card based on the image data. The transmitted signals provide image data of the back of the playing card and are also received by a processor that evaluates or compares that data. The system may be an installed casino system (with eye-in-the-sky technology), a portable box, or a component within a shuffling device or dealer shoe.
US09672418B2 Arabic sign language recognition using multi-sensor data fusion
Systems and methods for sign language recognition are described to include circuitry to detect and track at least one hand and at least one finger of the at least one hand from at least two different locations in a room, generate a 3-dimensional (3D) interaction space based on the at least two different locations, acquire 3D data related to the at least one detected and tracked hand and the at least one detected and tracked finger, extract 3D features associated with the at least one detected and tracked hand and the at least one detected and tracked finger, analyze a relevance metric related to the extracted 3D features, classify at least one pattern from each of the at least two different locations based on a fusion of data outputs by the circuitry, and generate a recognized sign language letter based on the fusion of the data outputs.
US09672415B2 Facial liveness detection in image biometrics
System and techniques for spoofing detection in image biometrics are described herein. A sequence of images may be obtained from a camera; a first plurality of images in the sequence of images including a representation of a user body part, and a second plurality of images in the sequence of images including a representation of an environment of the user. A marker may be created for the representation of the body part. A feature of the environment of the user present during the second plurality of images may be identified in the sequence of images using a third group of circuits. A correlation between the marker and the feature of the environment in the sequence of images may be quantified to produce a synchronicity metric of the degree to which the marker and the feature of the environment correlate.
US09672414B2 Enhancement of skin, including faces, in photographs
An image processing application performs improved face exposure correction on an input image. The image processing application receives an input image having a face and ascertains a median luminance associated with a face region corresponding to the face. The image processing application determines whether the median luminance is less than a threshold luminance. If the median luminance is less than the threshold luminance, the application computes weights based on a spatial distance parameter and a similarity parameter associated with the median chrominance of the face region. The image processing application then computes a corrected luminance using the weights and applies the corrected luminance to the input image. The image processing application can also perform improved face color correction by utilizing stylization-induced shifts in skin tone color to control how aggressively stylization is applied to an image.
US09672413B2 Setting operation area for input according to face position
Provided is an information processor which readily permits operation input to be made so as to point a position on a screen when an operation input is received from a user using a captured image obtained by imaging the user. The information processor acquires a captured image including a user's face, identifies the position of the user's face included in the acquired captured image, sets an operation area at a position on the captured image determined in accordance with the identified face position, detects a detection target within the operation area, and receives, as a user-pointed position, a position on the screen corresponding to a relative position of the detected detection target within the operation area.
US09672412B2 Real-time head pose tracking with online face template reconstruction
Provided are methods and apparatus for tracking a head pose with online face template reconstruction. The method comprises the steps of retrieving a plurality of frames of images of the user; comparing each of the retrieved frames with a predetermined face template to determine one or more head poses that are monitored successfully and obtain head pose information of the determined one or more head poses; and reconstructing, during the step of comparing, the face template from the obtained head pose information; wherein the reconstructed face template is compared with subsequently retrieved images such that the head poses of the user are tracked in time.
US09672409B2 Apparatus and computer-implemented method for fingerprint based authentication
A computer-implemented method of performing fingerprint based authentication from matching local features represented by binary features which can be matched in an efficient implementation in one or both of software and hardware by computing Hamming distances between the binary features. A local feature in a verification image is said to be matching with a local feature in an enrolment image if the Hamming distance between the binary features falls below a pre-determined threshold. The computer-implemented method retains information about the similarity of local features in the two images and utilities it in an efficient way with the objective of improving fingerprint recognition rates and enabling finger liveness detection. In an aspect a normalized feature similarity distribution is generated as part of the representation in recognition and liveness detection.
US09672407B2 Fingerprint sensing device with interposer structure
The invention relates to a fingerprint sensing device comprising: a sensing chip comprising an array of sensing elements being configured to be connected to readout circuitry for detecting a capacitive coupling between each of the sensing elements and a finger placed on a sensing surface of the sensing device. A surface of the sensing elements define a sensing plane. The sensing device further comprises a plurality of interposer structures arranged on the sensing chip extending above sensing plane, wherein the plurality of interposer structures have the same height above the sensing plane. A protective plate is attached to the sensing chip by means of an adhesive, and the protective plate rests on the interposer structures such that a distance between the protective plate and the sensing plane is defined by the height of the interposer structures.
US09672404B2 Active biometric authentication with zero privacy leakage
The invention provides a method for frequent verifications of the identity of a user performed during a long session of client-server communication by secure exchange of keys between the client and the server. A user is represented at the server by a set of random numbers that have nothing to do with his biometric data. The server initiates authentication requests by sending encoded randomly generated permutation to the client. On each request, the client creates a dynamic response key built by using the decoded permutation and biometric data of the user so that this biometric data cannot be retrieved from the key. The key also includes the correlation coefficient between the sound of the user's breathing and the distance between the most outer sides of the wings of his nose and the correlation coefficient between the area of the user's pupil and the brightness of his computer screen.
US09672401B2 Fingerprint sensing system and method
A fingerprint sensing system comprises a sensor array with a plurality of sensing structures and read-out circuitry connectable to each of the sensing structures, and power supply circuitry arranged to provide to the read-out circuitry a substantially constant supply voltage being a difference between a high potential and a low potential. The fingerprint sensing system is configured in such a way that the low potential and the high potential are variable while substantially maintaining the supply voltage, and the read-out circuitry is connectable to each of the sensing structures in such a way that a variation in the low potential and the high potential while substantially maintaining the supply voltage results in a change of the charge carried by a sensing structure connected to the read-out circuitry. The change in charge is indicative of a capacitive coupling between the sensing structure and the finger.
US09672400B2 Imaging and peripheral enhancements for mobile devices
An image enhancer device for use with an associated mobile electronic device having a digital camera. The image enhancer device includes an image manipulator coupled to a first region of a housing and configured to modify an optical path of the digital camera; an aimer having an aiming element configured to direct at least one aiming light beam towards an object of interest; an illuminator having an illumination element configured to direct at least one illumination light beam from the housing towards the object of interest; and electronics allowing for communication between the image enhancer device and the associated mobile electronic device. The image enhancer device forms a scan angle relative to a field of view of the digital camera of the mobile electronic device and allows for bar code imaging and/or native image processing with the digital camera of the associated mobile electronic device.
US09672395B2 Reader control system
An RFID reader control system and method is provided. A protocol for controlling an RFID reader and an RFID reader control unit of a mobile phone is defined. Messages, information, commands, responses, and notification are constructed and transmitted between the RFID reader and the RFID reader control unit.
US09672393B1 Phase controlled array for wirelessly powering implantable devices
A reader device includes an array of antenna coils configured to electromagnetically couple with devices implanted beneath or within skin of a human body. An implanted device can include a loop antenna or other means configured to couple with at least one antenna coil of the reader device to receive radio frequency energy from the reader device. The antenna coil array is configured to mount to the skin surface to improve the coupling between the implanted device and coils of the array. Further, the reader device is configured to select two or more antenna coils of the array and to operate the selected antenna coils to emit radio frequency power at respective amplitudes and relative phases to provide radio frequency power to the implanted device while increasing efficiency of the power transfer and reducing the exposure of the skin to radio frequency energy.
US09672390B2 IC card and command processing method for IC card
According to one embodiment, an IC card includes a communication unit, a controller, a data storage unit, a command processor, and a response unit. The controller performs data communication of the communication unit by using a logical channel. The command processor performs access to data specified by a command on a logical channel specified by the command. The response unit outputs a response message in response to the command, with the response message added with information indicating that the specified data is inaccessible because the data is used on an other logical channel, if the data specified by the command is inaccessible because the data is used on a channel other than the logical channel of the command.
US09672385B2 Method of improving FPGA security using authorization codes
A method for securely programming a population of authorized FPGAs includes defining the population of authorized FPGAs, generating an encrypted configuration bitstream for the population of authorized FPGAs, generating an individual Authorization Code for each FPGA in the population of authorized FPGAs, feeding the individual Authorization Codes into the FPGAs in the population of FPGAs, feeding the encrypted configuration bitstream into all of the FPGAs in the population of FPGAs, and in each FPGA using the Authorization Code to decrypt the encrypted configuration bitstream to program the FPGA.
US09672378B2 Collision avoidance in a distributed tokenization environment
A client receives sensitive data to be tokenized. The client queries a token table with a portion of the sensitive data to determine if the token table includes a token mapped to the value of the portion of the sensitive data. If the mapping table does not include a token mapped to the value of the portion of the sensitive data, a candidate token is generated. The client queries a central token management system to determine if the candidate token collides with a token generated by or stored at another client. In some embodiments, the candidate token includes a value from a unique set of values assigned by the central token management system to the client, guaranteeing that the candidate token does not cause a collision. The client then tokenizes the sensitive data with the candidate token and stores the candidate token in the token table.
US09672375B2 Security key entry using ancillary input device
A physical, non-human readable representation of a digital key may be in a physical key article. The key article may enable a person to generate a signal representing the digital key from a user interface device in communication with a computer by physical manipulation of the key article. Access to digital content via the computer may be unlocked in response to receiving the signal. In addition, a key may be represented by a pattern of unreadable errors in a computer-readable medium.
US09672372B2 Method for improving mean time to data loss (MTDL) in a fixed content distributed data storage
An archival storage cluster of preferably symmetric nodes includes a data protection management system that periodically organizes the then-available nodes into one or more protection sets, with each set comprising a set of n nodes, where “n” refers to a configurable “data protection level” (DPL). At the time of its creation, a given protection set is closed in the sense that each then available node is a member of one, and only one, protection set. When an object is to be stored within the archive, the data protection management system stores the object in a given node of a given protection set and then constrains the distribution of copies of that object to other nodes within the given protection set. As a consequence, all DPL copies of an object are all stored within the same protection set, and only that protection set. This scheme significantly improves MTDL for the cluster as a whole, as the data can only be lost if multiple failures occur within nodes of a given protection set. This is far more unlikely than failures occurring across any random distribution of nodes within the cluster.
US09672368B2 Providing selective control of information shared from a first device to a second device
A system and method for providing selective control of information shared from a first device to a second device. The system includes a connection detector to detect a short-range communication between the first device and the second device; a security setter to set or acquire a security setting; a disconnect detector to detect whether the short-range communication between the first device and the second device is terminated; and a wiper to perform data management of information shared via the short-range communication between the first device and the second device based on the security setting.
US09672367B2 Method and apparatus for inputting data
Embodiments of the present invention provide a method and an apparatus for inputting data. The present invention relates to the communications field and aims to improve security of input information. The method includes: acquiring, by a virtual machine manager, input data; performing, by the virtual machine manager, encryption processing on the input data according to an encryption rule of a security connection to obtain encrypted data; and sending, by the virtual machine manager, the encrypted data to the server. The present invention is applicable to a data input scenario.
US09672364B2 Differentially private linear queries on histograms
The privacy of linear queries on histograms is protected. A database containing private data is queried. Base decomposition is performed to recursively compute an orthonormal basis for the database space. Using correlated (or Gaussian) noise and/or least squares estimation, an answer having differential privacy is generated and provided in response to the query. In some implementations, the differential privacy is ε-differential privacy (pure differential privacy) or is (ε,δ)-differential privacy (i.e., approximate differential privacy). In some implementations, the data in the database may be dense. Such implementations may use correlated noise without using least squares estimation. In other implementations, the data in the database may be sparse. Such implementations may use least squares estimation with or without using correlated noise.
US09672357B2 System and method to mitigate malware
Particular embodiments described herein provide for an electronic device that can be configured to receive script data, determine a checksum tree for the script data, compare each checksum of the checksum tree to one or more subtree checksums, and assign one or more classifications to the script data. In one example, the checksum tree is an abstract syntax tree.