| Document | Document Title |
|---|---|
| US09674380B2 |
Image processing apparatus and image processing system
An image processing apparatus includes a communication unit, a display unit, an input unit, and an image processing unit. The communication unit receives information related to at least one processing condition for image processing stored in and specified with a terminal device. The display unit displays a screen in which the at least one processing condition received by the communication unit is displayed. The input unit, when a user wishes to change the at least one processing condition displayed in the display unit, allows the user to input a different processing condition to which the user wishes to change the displayed processing condition. The image processing unit performs the image processing. |
| US09674373B2 |
Identification of timestamps for a partial CDR when failover occurs in an offline charging system
Systems and methods that generate a partial Charging Data Record (CDR) when charging transfers from a primary charging function to a secondary charging function due to a failure. In one embodiment, the system receives an interim accounting request for a session from a secondary charging function after charging was transferred from the primary charging function. The system then opens a new partial CDR for the session based on the interim accounting request. The system receives a prior partial CDR for the session from the primary charging function, parses the prior partial CDR to identify a CDR timestamp, and records a start time in the new partial CDR based on the CDR timestamp. The system parses the interim accounting request to identify an accounting timestamp for the session, records an end time in the new partial CDR based on the accounting timestamp, and closes the new partial CDR. |
| US09674372B2 |
Real time, machine-based routing table creation and enhancement for toll-free telecommunications
Methods and systems for the population and pre-population of toll-free call routing tables based on prior activities such as a crowd-sourced routing table provide for provisioning a toll-free texting services. |
| US09674365B2 |
Method for carrying out an audio conference, audio conference device, and method for switching between encoders
A method and an audio conference device for carrying out an audio conference are disclosed, whereby classification information associated with a respective audio date flow is recorded for supplied audio data flows. According to a result of an evaluation of the classification information, the audio data flows are associated with at least three groups which are homogeneous with regard to the results. The individual audio data flows are processed uniformly in each group in terms of the signals thereof, and said audio data flows processed in this way are superimposed in order to form audio conference data flows to be transmitted to the communication terminals. |
| US09674363B1 |
Establishing a social connection with a business during a conversation
Associating callers of a contact center with their social media identity may provide mutual benefits to the caller and contact center. For example, a business operating a contact center can receive information about their current and potential customers and customers can receive additional information, incentives, or other perks by allowing access to their social media profile. When a caller initially calls a contact center, they are prompted, and possibly incentivized, to provide a social media identity. The social media identity may or may not have an affinity with an organization on the social media website. If not, the caller is provided with the opportunity to establish the affinity. If the caller does establish the affinity, the call may be identified as having a positive sentiment or negative sentiment if the caller does not do so. The call, or future calls, with the caller may then be processed accordingly. |
| US09674359B2 |
Call center telephone system, privacy call method, and non-transitory computer readable medium storing privacy call program
When a two-way call connection state, which is between a customer terminal connected to an outside line-side of a private branch exchange and an operator terminal, is switched to a three-way call connection state, which is among the outside line, the operator terminal, and a supervisor terminal, using conference, in order to send advice or the like to an operator from a supervisor, a transmission line of the outside line, a first transmission line of the operator terminal, a reception line of the operator terminal, a transmission line and a reception line of the supervisor terminal are connected to one of the conference trunks, which has been captured from among the available conference trunks, and a second transmission line of the operator terminal is connected to a reception line of the outside line. |
| US09674356B2 |
Dynamic recommendation of routing rules for contact center use
A machine learning system and method for contact center use. Activities associated with a plurality of contact centers are monitored and a knowledge base is updated based on the monitored activities. An outcome for a particular contact center may be predicted based on monitored interactions for the particular contact center, and based on information in the knowledge base. An output is then generated based on the predicted outcome. |
| US09674354B2 |
Systems and methods for use in marketing
A method for scheduling outbound communications to sales leads based, at least partly, on a model of customer behavior derived from (i) customer data gathered from a plurality of customers that initiated contact with an electronic communications interface, and (ii) time data recording for each of the customers a time or time period at which the customer interacted with the electronic communications interface. The model predicts, for one or more time periods and segments of a population, a likelihood of successfully engaging with a person from the segment of the population. The scheduling includes prioritizing the outbound communications to the sales leads during one or more defined time periods. |
| US09674351B1 |
Remote voice recognition
According to one or more aspects of the present disclosure operations related to performing captioning may include receiving, from a first user device, first audio data. The operations may further include directing the first audio data to a remotely located call-assistant device and receiving, from the call-assistant device, second audio data that is related to the first audio data and that is derived from speech of a call assistant. The operations may also include accessing, with a captioning software application, voice profile data of the call assistant and generating caption data that includes a transcription of the second audio data. The operations may also include generating, based on the transcription, screen data related to the captioning software application, in which the screen data includes the transcription. In addition, the operations may include directing the screen data to the call-assistant device and directing the caption data to the first user device. |
| US09674350B2 |
Telecommunication fraud prevention system and method
Embodiments of the invention include a system and a method for monitoring telephone calls on a plurality of inbound and outbound voice channels made to and originating from a private branch exchange (PBX) network to detect fraudulent activity. Audio data on two or more of the voice channels is monitored and detected. The detection comprises processing binary data streams on at least one inbound voice channel and at least one outbound voice channel, and modifying the bit sequence of the binary data stream of the at least one inbound voice channel by introducing a watermark therein. The streams are compared for determining whether the watermark is present in at least one outbound channel. If the watermark is found, the at least one outbound voice channel is blocked. |
| US09674347B1 |
Communication device
The mobile phone comprising a voice communication implementer, a stereo audio data output implementer, and a mobile phone updating implementer which updates a mobile phone battery controller, a mobile phone camera unit controller, a mobile phone microphone controller, a mobile phone speaker controller, or a mobile phone vibrator controller. |
| US09674343B2 |
System and method for instantiation of services at a location based on a policy
A request to instantiate a first service is received. The first service is subject to policy constraints including a location. It is determined that a first set of resources at the location is required for instantiation of the first service. The first set of resources is reallocated to the first service from a second service. The first service is instantiated at the location utilizing the first set of resources reallocated. |
| US09674342B2 |
Cable damage detection
A system for monitoring connection status of a cable in a network comprising a detector operationally connected to the cable, a metal line test module, and a processor for receiving from the detector one or more connection status reports about connection of the cable to a network node, and configured to cause, upon a connection status report threshold being reached, a test of the cable by the metal line test module to confirm the connection status of the cable. Related apparatus and methods are also disclosed. |
| US09674341B1 |
Transcribing audio communication sessions
A computer-implemented method to provide transcriptions of an audio communication session is disclosed. The method may include receiving audio data at a first device from a second device over a first wireless network connection of a first wireless network type and providing the audio data to a speaker of the first device for output of the audio data. The method may further include encoding the audio data at the first device based on a second wireless network type and transmitting the encoded audio data from the first device over a second wireless network of the second wireless network type. |
| US09674336B2 |
Portable processing unit add on for mobile devices
The present disclosure provides a portable processing unit add-on computing device for mobile devices. In one embodiment, the portable processing unit add-on comprises one or more processors, memory and means for remotely displaying and receiving input for its user interface. The portable processing unit add-on interacts with the mobile device in order to allow the mobile device's user to access the portable processing unit's functionality. The portable processing unit typically, but not necessarily, includes a desktop-grade processor, such as one based on the Intel™ x86 architecture, and runs a desktop-grade operating system such as Microsoft Windows™ or Ubuntu Linux™. |
| US09674335B2 |
Multi-configuration input device
A multi-configuration input device is described. In one or more examples, an input device comprises a connection portion configured to be secured to a mobile computing device using a magnetic connection, an input portion having one or more sensors configured to generate inputs responsive to user interaction, a support portion rotationally secured to the input portion and the connection portion and effective to assume a cover configuration in which the support portion and the input portion are positioned to cover a display device of the mobile computing device, and further effective to assume a stand configuration in which the support portion and the input portion are position at an acute angle with respect to one another, and an operating system selection key operable to select from a plurality of operating systems. |
| US09674334B2 |
Method for transmission of alarm messages to subscriber terminals in radio communications system
Alarm messages are transmitted to subscriber terminals of a radio communication system by signalling the alarm presence through a control channel to the subscriber terminals by at least one base station of the radiocommunication system using at least one system information item. Upon reception of the system information item by the subscriber terminals, the subscriber terminals transmit at least one respective recorded alarm signal. |
| US09674331B2 |
Transmitting data from an automated assistant to an accessory
An accessory is configured to receive a request. The accessory transmits information associated with the request to a portable device. An automated assistant application executed by the portable device can interpret the request and provide a report. The portable device can transmit the report to the accessory. The report may include one or more results determined by the automated assistant. |
| US09674330B2 |
Method of improving sound quality of mobile communication terminal under receiver mode
A mobile communication terminal is disclosed. The mobile communication terminal has Receiver Mode and hands-free mode and switchable between the modes. The terminal includes a first sound generator, which works under Receiver Mode and used for receiving and playing voice signal; a second sound generator, which works under Receiver Mode and Hands-free Mode and used for receiving and playing voice signal; when the mobile communication terminal works under Receiver Mode, the first sound generator and the second sound generator receive and play voice signal at the same time. A method of improving sound quality of the mobile communication terminal is also provided. |
| US09674326B2 |
Arrangement with a handset device, an interface unit and a hearing device
A handset device and an interface unit used to transmit at least one of a command signal and an audio signal to a hearing device by way of a wireless connection are disclosed. The handset device has an audio output and is configured to transmit a power signal configured to power the interface unit to the interface unit by way of a wired connection connecting the audio output of the handset device with an audio input of the interface unit. The handset device is also configured to transmit the command signal and/or the audio signal to the interface unit by way of the wired connection. In certain embodiments, the audio signal and at least one of the command signal and the power signal have pre-assigned and non-overlapping frequency ranges. |
| US09674324B1 |
Phone case with finger slots
The phone case with finger slots is a case that supports an electronic device, such as a smart phone. The case is further defined with a rear surface that includes at least one finger slot integrated therein. The at least one finger slot of the rear surface of the case includes a groove that is recessed below the rear surface of the case. The at least one finger slot includes an elastic member that spans across the groove. A finger opening is provided on a side surface of the case. In use, a finger is adapted to be inserted into the finger opening such that the elastic member stretches upwardly in order to form a contoured fitting over the finger. The case is also further defined with a top surface, and an electronic device is adapted to be inserted into a cavity provided through the top surface of the housing. |
| US09674319B2 |
Detection method in network system and related apparatus
A detection method, used in a network system, for detecting an online state of a server, includes a host generating a discover packet according to a media access control address of a network interface card of the server and transmitting the discover packet to the network system; and the host capturing the server internet protocol address in at least one offer packet when receiving the at least one offer packet corresponding to the discover packet, and storing the server internet protocol address in a detection result file. |
| US09674318B2 |
TCP processing for devices
A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream. |
| US09674315B2 |
Methods for dynamically binding header field identifiers in a network control protocol
Header field identifiers can be dynamically bound to header fields in software defined networks via signaling between software defined network (SDN) controllers and switches. Dynamically establishing header binding definitions may allow new header fields to be recognized and manipulated (e.g., matched, modified, etc.) by SDN switches without having to update the corresponding standard. To achieve this, an SDN controller sends a binding request to an SDN switch to propose that a header field identifier be dynamically associated with a header field type. If the SDN switch acknowledges the binding request, then the header field identifier is used to identify the header field type in messages (e.g., control messages, etc.) transmitted to the SDN switch. |
| US09674314B2 |
Method for operating a mobile wireless network
A method of operating a mobile wireless network is described to ensure proper function of protocol entities during the transmission of data units between two wireless stations of the mobile wireless network. In this case, user data is assembled by a first convergence protocol layer of the first wireless station into at least one first data unit, particularly a packet data unit, before transmission to a second convergence protocol layer of a second wireless station, particularly on the same protocol level, with the user data being supplied to the first convergence protocol layer by at least one user in a network layer. At least one protocol entity of the first convergence protocol layer is configured as a function of a configuration request received by the second wireless station, in order to form the at least one first data unit from the data received from the at least one user and to transmit it through a carrier to a link control layer. |
| US09674313B2 |
Adaptive payload management
Embodiments of the invention relate to payload storage format for storing data in support of an aggregation function. As an input is subject to aggregation, the input is evaluated to ascertain a payload format for the aggregation. It is understood that there is more than one payload format. An evaluation of the aggregation key is a factor in the initial payload format. If the key is an addition to an existing aggregation, the evaluation considers changing the format of the payload to address processing and/or memory efficiency for the aggregation. The evaluation and the format change takes place dynamically so that the aggregation may continue. |
| US09674308B2 |
Managing search session data
There is provided a method of synchronizing a first browsing session and a second browsing session for a user, the first browsing session having been executed on a first electronic device. The method comprises receiving, by a server via a communication network, a request for the second browsing session from one of the first electronic device and a second electronic device at a point of time after initiation of the first browsing session; responsive to the user being a subscriber of a synchronization feature, causing by the server via the communication network the second browsing session to be displayed on the one of the first electronic device and the second electronic device, the second browsing session including a server-side history associated with user interactions within the first browsing session performed prior to said receiving. |
| US09674307B1 |
Running mobile applications in a distributed client-server model using selective delegation of hardware and software contexts to the client
The configuration describes the methods to transform the execution of an Android app running locally on an Android device to a client-server model of execution where the app executes on a modified version of Android on a server. Unlike a traditional client-server model where the application executes within the server environment, the Android app on the server requires delegation of some functionality to client environment. The proposed configuration also describes the methods for delegating the execution of selected components of Android stack to the Client Device. The client may be a browser or any web connected device. |
| US09674303B1 |
Methods and systems for efficient data transmission in a data center by reducing transport layer processing
Methods and systems for network communications are disclosed. The target device receives a request for a network connection from an initiator device, the request indicating a desire to bypass transport communication layer processing. The target device accepts the request and sends a response to the initiator device indicating an agreement to bypass the transport layer processing. The target device then receives a frame from the initiator device and processes the frame by bypassing the transport communication layer processing. |
| US09674302B1 |
Computing resource transition notification and pending state
A computing resource associated with a user is scheduled to undergo a transition. Prior to the scheduled transition, the computing resource is placed in a pending state. The user is notified that the computing resource is scheduled to undergo the transition. In response to an input received from the user, the computing resource is allowed to undergo the transition when the input indicates that the transition can proceed. |
| US09674296B2 |
Preventing race condition from causing stale data items in cache
A data cache server may process requests from a data cache client to put, get, and delete data items into or from the data cache server. Each data item may be based on data in a data store. In response to each request to put a data item into the data cache server, the data cache server may determine whether any of the data in the data store on which the data item is based has or may have changed; put the data item into the data cache memory if none of the data in the data store on which the data item is based has been determined to have or maybe to have changed, and not put the data item into the data cache memory if data in the data store on which the data item is based has been determined to have or maybe to have changed. |
| US09674295B2 |
Methods for establishing and using a transaction-specific, browser-specific debit card
A system and method providing a collection of associated servers in a data center connected to the Internet. The servers, each being related to a service, deliver a client to a user, encapsulating the related services to common standard Internet browser software. The system and method provide a window to the Internet. The associated servers perform browsing for a user, stripping out viruses and malware and delivering safe content. The content enables a user to view and interact with the content on its computer, but not processing that content on the user's computer; the content is not stored on any local storage at the user's computer. The system and method for the delivery of services is tightly integrated into the Internet browsing experience and provides the end-user with anonymity, privacy, fraud protection, and multiple-client sharing of meta-information pertaining to the browsing experience. |
| US09674289B2 |
Method and apparatus for optimising telecommunication services
A method of optimizing telecommunication services for a plurality of end users of a plurality of service sessions, each service session having a priority level, the method comprising the steps of: receiving compliance measure indicating that the service experience of at least one end user is compliant, for a snapshot, with expectations of the at least one end user within a telecommunication service providing a plurality of service sessions to a plurality of end users; determining if the received compliance measure is less than a predetermined threshold; and if the received compliance measure is determined to be less than a predetermined threshold, throttling at least one of the plurality of service sessions, that has not been throttled and has the lowest priority level, to optimize telecommunication services. |
| US09674288B2 |
Controller capable of reducing communication cycle time
A controller (node) divides all nodes connected to a network into several network groups, and gives the division network groups network identification numbers for identifying them. A token frame contains a network identification number. This network identification number enables data to be shared among all the nodes connected to the network while a token for each network group is circulated only in the network group. |
| US09674286B2 |
Collaboration system and method
A participant computing device in a collaboration system, the participant computing device comprising a processing structure; and a memory including computer program code, wherein the memory and the computer program code are configured, with the processing structure, to cause the processing structure to share user defined content displayed on a desktop associated with the participant computing device with other participant computing devices. |
| US09674281B2 |
Circle-mesh overlay network construction and maintain method
A method of constructing and maintaining a circle-mesh overlay network is disclosed. The method of constructing a circle-mesh overlay network includes: (a) determining a reference member number of a circle overlay by using a total number of participating peers; (b) creating a new circle overlay and adding member peers from among the participating peers to the new circle overlay in consideration of the reference member number; and (c) forming a circle-mesh overlay network by way of interconnection between the new circle overlay and a different circle overlay. |
| US09674280B1 |
Social file storage
The present disclosure provides for determining whether object accesses that occur in a file system qualify as relevant events, and displaying information about relevant events in a social file storage interface. A social file storage interface can provide a news feed of recent relevant events, a subscription list that displays information about relevant events performed by colleagues, and an access map that displays a visual representation of relevant events and relevant objects in the file system. An object access qualifies as a relevant event if an attribute of the object access satisfies relevance criteria defined by a user. If a user is not authorized to access an object, a relevant event pertaining to that object will not be displayed to the user in the social file storage interface. An object can also be accessed and opened from within the social file storage interface. |
| US09674278B1 |
Geographic data management server
Aspects of the present disclosure relate to a tile management server. The management server receives, from a client device, a request for geographic data, the request having a management server request format. The management server selects a first geographic server, out of multiple geographic servers, for processing the request. The management server translates the request from the management server request format into a first geographic server request format. The first geographic server request format is for communicating with the first geographic server. A second geographic server from among the plurality of geographic servers communicates using a second geographic server request format different from the first geographic server request format. The management server transmits, to the first geographic server, the request translated into the first geographic server request format in order to cause the first geographic server to provide the geographic data to the client device. |
| US09674277B1 |
Systems and methods for request isolation protection
Systems and methods for request isolation protection at a first server. The first server receives a resource request from a client device. The first server may receive multiple requests from the same client device or other client devices. The first server caches the multiple requests so that only one resource request is made to a second server storing the resource. The first server detects when the client device cancels the request to the resource. In response, the first server cancels the request made to the second server if there are no other requests made to the resource. If there are other requests remaining, then the first server does not cancel the request to the second server. |
| US09674274B2 |
Internationalization with virtual staging and versioning
One embodiment of the present invention sets forth a technique for providing a variation of digital content that is based on a client-specified context token. Localized digital assets, e.g., graphics resources, video resource, audio resources, and text string resources, are stored as a collection of records and are dynamically linked to a assemble a software system based on the client-specified context token to generate the variation of digital content. The client receives the assembled variation of the digital content including the localized digital assets specified by the client-provided context. |
| US09674273B2 |
Method for providing composed services in a peer-to-peer network
A method for providing a service containing facilities in a peer-to-peer network comprising peer devices is provided. The peer devices may be associated with groups, each group being defined by a pre-determined facility. The pre-determined facility may be executed by each peer device associated with a respective group, and a selected peer device of a group executes the respective facility. A sequence of facilities and specifications to be executed is publicized in the peer-to-peer network, on the peer devices executing the respective facility by a peer device requesting the combined service, and the selection of the selected peer devices is carried out according to the publicized sequence and the publicized specifications. |
| US09674271B2 |
Platform for sharing collected information with third-party applications
A method for storing information items from a client device to a remote server is performed at the client device having memory and one or more processors, the remote server being communicatively coupled to the client device. The client device renders an information item and an information storing option associated with the information item using a first application at the client device. Upon detecting a user selection of the information storing option, the client device invokes a second application, which may or may not run on the client device, to upload data associated with the information item rendered on the client device to the remote server and then resumes the rendition of the information item using the first application at the client device. |
| US09674269B2 |
Client device and associated methodology of accessing networked services
A system makes it possible to use services offered by a plurality of servers different from one another is realized with the use of a common API. The system includes a plurality of service-offering servers, a client that uses services offered by the plurality of service-offering servers, and an interchange server that performs intermediary processing when the client uses a service. The client performs communication with the interchange server while using a common API when using any service among a plurality of services offered by the plurality of service-offering servers. The interchange server uses a unique API, which is unique to the service-offering server that offers the service selected by the client, to execute a processing sequence that is unique to the service-offering server. The client may use any service among services offered by the plurality of service-offering servers with the use of a common API without any need to use a unique API, which is unique to each of the plurality of service-offering servers. |
| US09674267B2 |
Methods and apparatus for hiding latency in network multiplayer games
Aspects of the present disclosure describe methods and apparatuses that hide latency during an interaction between an attacking client device platform and a defending client device platform in a multiplayer game played over a network. The attacking client device platform predicts a successful attack will be made and delivers a hit event to the defending client device platform. In order to provide additional time to wait for a hit reply from the defending client device platform the attacking client device platform initiates an altered animation mode that lengthens the run-time of the animation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09674266B2 |
Method for adaptive streaming, local storing and post-storing quality increase of a content file
A method includes monitoring a bandwidth currently available for streaming of a segment file pertaining to the selected content asset from a server to the client. A selected content asset is registered by receiving a user-originating request identifying the selected content asset. An adequate segment quality level to be requested is selected based on the currently available bandwidth. A segment to be requested is adaptively selected contingent upon the local availability or quality level of file segments. The segment is requested from the content providing server in the specified adaptively selected adequate segment quality level. The requested segment is received in a current segment quality level corresponding to the adaptively selected adequate quality level, stored locally associated with information regarding its quality level. Received file segments pertaining to the content file are rendered in a manner as specified by a received manifest file pertaining to the content file. |
| US09674259B1 |
Semantic processing of content for product identification
This disclosure describes systems, methods, and computer-readable media related to semantic processing of content for product identification. Content may be received from a user device. The content may be processed based at least in part on one or more content filters. At least a portion of the processed content may be analyzed with named-entity recognition to identify one or more product references. A confidence score associated with each of the one or more product references may be calculated. Data associated with the one or more product references may be obtained. The data associated with the one or more product references may be transmitted for presentation on the user device. |
| US09674258B2 |
System and method for context specific website optimization
A system for optimizing a website for different contexts includes an intermediary component configured to connect to clients and servers via network connections, means for analyzing a HTTP request from a client and determining specific context of the HTTP request, means for configuring optimization settings of selected website properties for the specific context of the HTTP request, and means for applying the configured context-specific optimization settings to redirected HTTP requests and HTTP responses. The intermediary component includes a traffic management system (TMS) and a traffic processing system (TPS). The TMS manages HTTP requests originating from the clients and targeting the servers and HTTP responses targeting the clients and redirects the HTTP requests to the intermediary component. The TPS receives the redirected HTTP requests and the HTTP responses, detects the context and applies relevant optimization techniques for the specific context to the redirected HTTP requests and the HTTP responses. |
| US09674255B1 |
Systems, devices and methods for presenting content
Media devices may stream a wide variety of content for presentation. Described herein are systems, devices, and methods for improving the presentation of the content. The media device may execute a pipeline architecture comprising a sequential execution of a plurality of threads. The threads may include a decryption thread, a decoding thread, and a rendering thread. The media device may include buffer queues between the threads, which enable continuous content presentation when one or more of the threads fail to communicate with another thread. The media device may pause the presentation of content by suspending the execution of the rendering thread. In one implementation, the media device replaces a stale frame that is displayed after performing a seek function with a black frame. In another example, to maintain content presentation, the media device drops video frames if an audio video lag event occurs. |
| US09674254B2 |
System and method for using a streaming protocol
An initialization vector (IV) is employed to decrypt a block of a stream that has been encrypted with Cypher Block Chaining (CBC) encryption, without requiring decryption of previous blocks within the stream. For example, a listener who accesses a distribution point to retrieve encrypted content authenticates himself to an application server that regulates access to encrypted content on the distribution point, and responsively receives a key. The listener then requests access to a reference point within the encrypted content stream somewhere after its beginning (e.g., using preview clips). The distribution point relates the reference point to a corresponding block of the encrypted stream, and identifies an IV previously used for encryption of that block. The distribution point provides the associated encrypted block of content and the IV to the listener to enable mid-stream rendering of the encrypted content, without requiring the listener to decrypt previous blocks within the encrypted stream. |
| US09674252B2 |
System and method for efficient delivery of repetitive multimedia content
A system and method for off-loading the serving of repetitive content by a streaming server are presented. The method includes establishing a plurality of unicast transport-layer sockets with a plurality of end-user devices; receiving a plurality of requests for a multimedia content from the plurality of end-user devices, wherein the plurality of requests are session-layer requests; determining if the received plurality of requests are for a repetitive content; and upon determination that the received plurality of requests are for the repetitive content: opening a single socket with a streaming application of at least one streaming server; retrieving a single copy of the requested multimedia content from the streaming application over the single socket; and streaming the retrieved single copy to the plurality of end-user devices through their respective plurality of unicast transport-layer sockets. |
| US09674247B1 |
Generating manifest files for digital media items
A media player generates a first manifest file for a digital media item as the digital media item is downloaded and/or processed. The first manifest file is used to seek to locations within a buffered portion of the digital media item. When a seek request to a location in an unbuffered portion is received, the media player downloads a second manifest file from a server. The second manifest file is used to seek for subsequent seek requests. |
| US09674246B2 |
Data routing optimization
Certain examples accommodate data routing optimizations. An example method includes receiving, by a first playback device, data to be directed to at least a second playback device. The method further includes transmitting non-audio data to the second playback device via a third playback device and transmitting audio data to the second playback device directly. |
| US09674241B2 |
System and method for maintaining associations within a social network for a user
A system and method for maintaining associations within a social network for a user are provided. A device proximate a user device is identified. It is determined whether the identified device is associated with an entity having a pre-established association with a user of the user device within the social network. The user is associated with the entity within the social network if the identified device is not associated with an entity having a pre-established association with the user if a determination is made that the user is to be associated with the entity. The user-entity association is maintained within the social network based upon whether the entity and the user device remain proximate. |
| US09674239B2 |
System and method for interactive remote movie watching, scheduling, and social connection
Disclosed is a media sharing system that provides shared experiencing of licensed media content such as movies. The system includes a web server that communicates with multiple client devices over the internet whereby a user's multiple social contacts can participate in a synchronized stream of licensed media content such as movies. The system is able to schedule the multi-user experiencing of the licensed media content and further synchronize the streaming of the licensed content so the participating users receiving the media streams in a substantially synchronized manner. The system still further provides for social content interaction amongst the multiple recipients so that the multiple users can interact in a time-contextual manner consistent with the substantially synchronized receipt of the licensed media content. |
| US09674237B2 |
Focus coordination in geographically dispersed systems
A method, system, and computer program product for focus coordination in geographically dispersed systems are provided in the illustrative embodiments. A shifting of focus to a first object present in a first view is detected at a first data processing system in a first location in the geographically dispersed plurality of data processing systems. Metadata of the first view is identified, the metadata being usable to identify a second object in a second view at a second data processing system in a second location in the geographically dispersed plurality of data processing systems, the second object corresponding to the object in the view. A focus information package is constructed, wherein the focus information package includes an attribute of the first object and the metadata of the first view. The focus information package is sent to the second data processing system. |
| US09674232B1 |
Enterprise conferencing with dual mixing
A method and computer readable medium for providing Enterprise conferencing is provided. In an exemplary embodiment of the invention, a first SIP INVITE message is exchanged between a Media Gateway of the Enterprise and a first Media Server of a Conferencing Service Provider. Then, an Application Server of the Conferencing Service Provider establishes conference call resources at the Conferencing Service Provider. A first RTP session is established between the Media Gateway and the first Media Server, and then a PROMPT AND COLLECT message is sent from the Application Server to the first Media Server to gather data from the caller for establishing the Enterprise conferencing. After receipt of the data by the Application Server, an SIP INFO message is sent from the Application Server to a second Media Server of the Conferencing Service Provider, selecting the second Media Server to host the call. |
| US09674229B2 |
Method and apparatus for continuing the exchange of a media data stream beyond termination of a corresponding session initiation protocol dialogue
A method of operating a first communication device (3) for receiving a media data stream (64) from at least one second communication device (5) in a telecommunications system. The first communication device (3) exchanging with the at least one second communication device (5) Session Initiation Protocol, SIP, messages (60, 62, 63, 64, 67, 70) during a SIP dialogue. The SIP messages (67, 70) including a late media indicator (68, 71) that includes an indication that the media stream (64) continues (72) after the SIP dialogue has terminated, or an indication (75) of support of receiving media stream after the SIP dialogue has terminated. The SIP dialogue controls the media data stream (64, 72). The first communication device (3) receives the media data stream (64, 72) from the second communication device (5). The first communication device (3) continues to receive the media data stream (72) after the SIP dialogue has ended. |
| US09674227B2 |
Communicating status regarding application of compliance policy updates
A set of compliance policy updates are received. The compliance policy updates are sent to workloads for application. A status of the application of the compliance policies to the workloads is received from the workloads and output. |
| US09674222B1 |
Method and system for detecting network compromise
A method and system are described for detecting unauthorized access to one or more of a plurality of networked victim computers in a victim cloud. The networked victim computers connect to one or more DNS servers. The system includes one or more decoy bot computers, which are operated as victim computers in the victim cloud. The system also includes one or more decoy control computers, which are operated as control computers that communicate with victim computers in the victim cloud. Threats are identified by analyzing data traffic communicated with the decoy bot computers and decoy control computers for information suspected of having being sent from a victim's computer without proper authorization, and by monitoring whether behavior of a DNS server deviates from expected behaviors. |
| US09674217B2 |
Method and system for mitigation of distributed denial of service (DDOS) attacks
A system and method for mitigating the effects of malicious internet traffic, including DDOS attacks and email bombs, by utilizing a DNS Traffic Analyzer and Firewall to analyze network traffic intended for a DNS server and preventing some network traffic from accessing the DNS server. |
| US09674216B2 |
Testing integrity of property data of a device using a testing device
The embodiments relate to a method and a test system for testing integrity of property data of a device using a testing device within a network, the devices and their respective property data within the network, such as all the measurement or control device distributed inside an industrial automation system, being taken into account in order to simplify testing of a large number of devices. The various property data are tested for an identity and are labelled, and calculations, which are carried out by the testing device for testing purposes, are initiated on the basis of the labelling. By taking other devices in the system into account, security requirements may be fulfilled during testing and the computational effort for the testing device may also be reduced. |
| US09674214B2 |
Social network profile data removal
A computer-implemented method includes receiving a request to remove data that is associated with a protected social entity. The data maintained on one or more social networks is scanned, where scanning includes identifying data that is associated with one or more social entities. One or more characteristics of the identified data are determined, and a reference to the identified data that indicates the characteristic, is generated for each of the one or more characteristics. A match between the one or more generated references and one or more stored references is identified, where the one or more stored references each reference one or more characteristics associated with the protected social entity, and where the one or more stored references are stored in one or more social risk databases. A request to the one or more social networks to remove the identified data associated with the one or more generated references is submitted. |
| US09674211B2 |
Cloud service usage risk assessment using darknet intelligence
A method of assessing a risk level of an enterprise using cloud-based services from one or more cloud service providers includes assessing provider risk scores associated with the one or more cloud service providers and in view of darknet intelligence data; assessing cloud service usage behavior and pattern of the enterprise; and generating a risk score for the enterprise based on the provider risk scores and on the cloud service usage behavior and pattern of the enterprise. The risk score is indicative of the risk of the enterprise relating to the use of the cloud-based services from the one or more cloud service providers. |
| US09674205B2 |
Identity and trustworthiness verification using online and offline components
Methods and systems for verifying the identity and trustworthiness of a user of an online system are disclosed. In one embodiment, the method comprises receiving online and offline identity information for a user and comparing them to a user profile information provided by the user. Furthermore, the user's online activity in a third party online system and the user's offline activity are received. Based on the online activity and the offline activity a trustworthiness score may be calculated. |
| US09674199B2 |
Secured device access in a device automation system
A secured device access method is implemented in a web-based device automation system whereby the configuration of an automation application for specific devices in a user's automation environment and the installation of the automation application define the security scope for the automation application. Once the automation application is configured and installed, the automation application is only allowed access to the authorized devices in the user's automation environment and the automation application may not access other devices in the user's environment that have not been authorized. |
| US09674188B2 |
Techniques for authentication via a mobile device
Techniques for authentication via a mobile device are provided. A mobile device is pre-registered for website authentication services. A user encounters a website displaying an embedded code as an image alongside a normal login process for that website. The image is identified by the mobile device, encrypted and signed by the mobile device and sent to a proxy. The proxy authenticates the code and associates it with the website. Credentials for the user are provided to the website to automatically authenticate the user for access to the website bypassing the normal login process associated with the website. |
| US09674185B2 |
Authentication using individual's inherent expression as secondary signature
A method and system are provided. The method includes training for one or more secondary signatures of a user. The method further includes identifying one or more inherent expressions of the user as the one or more secondary signatures. The method also includes authenticating the user using a primary signature and at least one of the one or more secondary signatures. The one or more inherent expressions are unintended expressions performed by the user in relation to the user providing the primary signature. |
| US09674183B2 |
System and method for hardware-based trust control management
A trust control management method for security, operable on a computer system generates a unique Trust ID value by combining user-defined values with hardware-specific values associated with the user's computer system and storing the Trust ID value in a memory register physically associated with the hardware of the computer system. A Trust Control Suite (TCS) operable with a server OS/hypervisor maintains a database of user-defined values and hardware-specific values for computer systems clustered in a trusted computing pool. An attestation procedure is performed by the trust control server combining the user-defined values with the hardware-specific values from its database and comparing it to the user-stored Trust ID value stored in the memory register associated with a user's computer system. Depending on whether it is a match or mismatch, the TCS can determine if it is a trusted computer or not, and can take appropriate alerts and policy actions. |
| US09674180B2 |
Using identity/resource profile and directory enablers to support identity management
Embodiments of the present invention provide methods, system and machine-readable media for dynamically providing identity management or other services. According to one embodiment, dynamically providing services can comprise receiving a request related to an unknown principal. A service to which the principal is known can be selected. Once a service to which the principal is known has been located, an identity management result can be obtained from the selected service. The method can further comprise determining based on the identity management result whether the principal is authorized to access a requested resource. In response to determining the principal is authorized, the requested resource can be accessed. |
| US09674177B1 |
Dynamic knowledge-based user authentication without need for presentation of predetermined credential
A personal computing device, server or other type of processing device authenticates a user attempting to access a protected resource by verifying user knowledge of one or more extracted characteristics of stored information indicative of an internal operating state of that resource. The one or more extracted characteristics are characteristics that would likely be known to the user if that user had made one or more previous authenticated accesses to the protected resource. For example, the extracted characteristics may be indicative of a manner in which the user had utilized the protected resource during the one or more previous authenticated accesses to the protected resource. The processing device receives input from the user regarding the one or more extracted characteristics, and grants or denies access to the protected resource based at least in part on the input received from the user. |
| US09674175B2 |
Proxy server-based network site account management
Disclosed are various embodiments for network site account management using a proxy server. A request for a secured resource on a network site is generated based at least in part on stored account information in response to receiving an initial request for the secured resource from a client. The request is sent to the network site. The secured resource is sent to the client in response to receiving the secured resource from the network site. |
| US09674161B2 |
Data exchange in the internet of things
A device is configured to store a hash value and an encrypted hash value. The device may broadcast a boot label including the encrypted hash value. The device may receive an administrator label from an administrative device based on the boot label. The administrator label may include a decrypted hash value. The device may determine the decrypted hash value matches the hash value. The device may receive access information from the administrative device based on the decrypted hash value matching the hash value. The access information may associate authorization information and an access level. The access level may be associated with particular data that is permitted to be read from the device. The device may selectively provide the particular data to a control device based on the access information. |
| US09674160B2 |
Methods for anti-fraud masking of a universal resource indentifier (“URI”)
Methods may display a URI of a resource. Methods may determine the presence of a non-public data element in the URI. Methods may generate a random number in response to the determination of the presence of the non-public data element. Methods may compute a resultant number based on the exclusive or of the random number and the non-public data element. Methods may substitute the resultant number for the non-public data element in the URI. Methods may transmit the URI and the random number to a server. Methods may receive a resource from the server, in response to the transmission of the URI and the random number to the server. Methods may compute the non-public data element using the random number and the resultant number. Methods may substitute the non-public data element for the resultant number in the URI. Methods may re-determine the URI of the resource. |
| US09674157B2 |
Secure network communication
A client device configured to intercept an outgoing packet. The outgoing packet includes a destination network address. The client device is further configured to use an encryption key to encrypt the outgoing packet to generate an encrypted packet, scatter the encryption key into the encrypted packet according to pattern logic defined by a unique identifier of a routing server, and send the encrypted packet containing the scattered encryption key to the routing server. The routing server is configured to receive the encrypted packet containing the scattered encryption key, extract the encryption key from the encrypted packet using the pattern logic defined by the unique identifier, use the encryption key to decrypt the encrypted packet to obtain the outgoing packet including the destination network address, and send the outgoing packet to the destination network address. |
| US09674156B2 |
Event-triggered release through third party of pre-encrypted digital data from data owner to data assignee
A future proof method and system for securely transferring digital data from a data owner to a data assignee through a third party involving securely registering the data owner possessing the digital data with the third party and securely predefining to the third party a trigger event associated with a data assignee, registering the data assignee with the third party, receiving encrypted digital data and an encrypted trigger event associated with the data assignee transmitted from the data owner to the third party, and securely transferring and releasing the digital data to the at least one data assignee by the third party upon validation by the third party of the occurrence of the trigger event in such a manner that digital data can be used by data assignee on data assignee system. |
| US09674155B2 |
Encrypting segmented data in a distributed computing system
A method begins by a dispersed storage (DS) processing module segmenting a data partition into a plurality of data segments. For a data segment of the plurality of data segments, the method continues with the DS processing module dividing the data segment into a set of data sub-segments and generating a set of sub keys for the set of data sub-segments based on a master key. The method continues with the DS processing module encrypting the set of data sub-segments using the set of sub keys to produce a set of encrypted data sub-segments and aggregating the set of encrypted data sub-segments into encrypted data. The method continues with the DS processing module generating a masked key based on the encrypted data and the master key and combining the encrypted data and the masked key to produce an encrypted data segment. |
| US09674153B2 |
Secure data processing
A secure data processing apparatus and method are disclosed. The secure data processing apparatus is operable to securely process user data provided by a user and includes a trusted domain having a trusted bus; a trusted domain controller coupling the trusted bus with an untrusted bus of an untrusted domain, the trusted domain controller being operable to ensure that encrypted incoming user data received over the untrusted bus is decrypted and provided over the trusted bus as the incoming user data and to ensure that outgoing user data is encrypted and provided over the untrusted bus as encrypted outgoing data. The trusted domain controller that only encrypted data is provided in the untrusted domain reducing the chance of the data being compromised. The trusted domain controller ensures that access to the unencrypted data within the trusted domain can be avoided. Confidentiality of the data can be assured without performance shortfalls. |
| US09674146B2 |
Network security module for Ethernet-receiving industrial control devices
A high-speed security device for network connected industrial controls provides hybrid processing in tandem hardware and software security components. The software security component establishes state-less data identifying each packet that requires high-speed processing and loads a data table in the hardware component. The hardware component may then allow packets matching data of the data table to bypass the software component while passing other non-matching packets to the software component for more sophisticated state analysis. |
| US09674140B1 |
Multiplexing sessions in telecommunications equipment using interactive connectivity establishment
A data processing method comprising generating, by each Interactive Connectivity Establishment (ICE) endpoint of a plurality of ICE endpoints, a username comprising an identifier, wherein the plurality of ICE endpoints are accessible through a single Internet Protocol (IP) address and port number pair; sending, by each ICE endpoint, at least the username to a server for use in establishing a session between a specific ICE endpoint of the plurality of ICE endpoints and a client device; receiving, at a proxy associated with the plurality of ICE endpoints, a datagram from the client device for the specific ICE endpoint, wherein the datagram comprises the username; in response to attributes of the datagram not matching an entry in a table of the proxy, extracting the identifier from the username; forwarding, by the proxy, the datagram to the specific ICE endpoint based on the identifier. |
| US09674134B2 |
Crowdsourcing user-provided identifiers and associating them with brand identities
A system and method for crowdsourcing user-provided brand identifiers and distributing content based on crowd-sourced identifiers is provided. Different user-provided brand identifiers are extracted from messages provided by users of a social network. The identifiers are aggregated into two or more aggregate identity groups. When a brand identifier associated with a user request for content is determined to be in at least one of the aggregate identity groups, content items comprising one or more other brand identifiers of the at least one aggregate identity group are provided to the user. |
| US09674128B1 |
Analyzing distributed group discussions
Techniques are described for analyzing user-supplied information, including in at least some situations to predict future aspects of additional related information that will be supplied by users. The user-supplied information that is analyzed may, for example, include distributed group discussions that involve numerous users and occur via user comments made to one or more social networking sites and/or other computer-accessible sites. The analysis of user-supplied information may, for example, include determining particular topics that are of interest for a specified category during one or more periods of time, quantifying an amount of user interest in particular topics and the category during the period of time, predicting future amounts of user interest in the particular topics and the category during one or more future period of times, and taking one or more further actions based on the predicted information. |
| US09674127B2 |
Selective message republishing to subscriber subsets in a publish-subscribe model
According to one exemplary embodiment, a method for selectively resending a first message in a publish-subscribe message distribution model is provided. The method may include receiving the first message having a first message ID associated with the first message. The method may include sending the first message to a plurality of subscribers. The method may include receiving a rolled back first message. The method may include determining if the first message ID matches a second message ID associated with a second message. The method may include creating a first subscriber list associated with the first message. The method may include storing the first message in a data structure. The method may include appending a second subscriber list associated with the second message with a subscriber. The method may include sending the second message to the first subscriber or the first message to the first subscriber. |
| US09674125B2 |
Method and system for achieving communications in a manner accounting for one or more user preferences or contexts
A method and system for selectively communicating information are disclosed herein. In at least one embodiment, the method includes receiving at a server first information portions regarding one or more preferences, instructions, user profile details, or operational history details. The method also includes receiving an initial version of a message including additional information from a mobile device associated with a user, and determining based upon the first information portions that the additional information should be modified. The method further includes generating a first modified version of the message by modifying the additional information, and sending, for receipt by a further mobile device associated with a further user, the first modified version. Accordingly, in at least some embodiments, the first modified version of the message can include additional relevant content suited for each given recipient, based on (for example) preference, profile, or history information. |
| US09674121B2 |
Dynamic invites with automatically adjusting displays
Methods, devices, systems, and non-transitory processor-readable storage media for providing a collaboration tool for soliciting responses from users, including operations for receiving at a computing device a request from a user, transmitting to a plurality of computing devices an invitation message that causes the plurality of computing devices to render a display that solicits a response to the request, receiving a response message related to the request from at least one of the plurality of computing devices, evaluating the received response message to determine whether the received response message fulfills the request, and transmitting to the plurality of computing devices a cancellation message in response to determining that the received response message fulfills the request, the cancellation message configured to cause the plurality of computing devices to perform operations to automatically clean-up the display that solicits the response to the request. |
| US09674120B2 |
Method and apparatus for generating a suggested message to be sent over a network
The present disclosure is a method and apparatus for generating a suggested message. In one embodiment, a method for generating a suggested message includes monitoring, by an application server, a first device operated by a first user, detecting, by the application server, a triggering event relevant to the first user, and automatically generating the suggested message in response to the triggering event, where the suggested message is addressed to a second user. |
| US09674115B2 |
Aggregation of physical layer information related to a network
An exemplary system includes a plurality of connector assemblies. Each of the connector assemblies includes a plurality of ports. Each of the connector assemblies is configured to read information stored on or in physical communication media that is connected to the ports of the respective connector assembly. An aggregation point is communicatively coupled to the plurality of connector assemblies. The aggregation point is configured to automatically discover the connector assemblies and cause each of the connector assemblies to send to the aggregation point at least some of the information read from the physical communication media that is connected to its ports. The aggregation point is configured to store at least some of the information sent by the connector assemblies to the aggregation point. The aggregation point can also be configured to provide at least some of the information it stores to at least one other device via the network. |
| US09674114B2 |
Modular decoupled crossbar for on-chip router
Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations. |
| US09674113B2 |
Data bridge
A data bridge controls packet transfers between network fabrics forming a closed network, such as a vehicular network and a home network. The data bridge includes two or more sets of modules, each of which communicates with a different network fabric. When a packet is to be delivered between network fabrics, a first set of modules, which is used to communicate with a first network fabric, decides whether to accept the packet or discard it. If the packet is accepted, it is delivered to a second set of modules, which is used for communicating with a second network fabric. The second set of modules makes a second, independent decision about whether the packet will be sent to the second network fabric. Each set of modules can base its decision on packet content type, and may discard any packet not to be delivered to the other network. |
| US09674111B2 |
Control mechanism for reliability and availability setting in virtual networks
A mechanism for improving a reliability of a virtual network and resources used. At a virtual network operator level, a request for providing resources for the virtual network is sent towards an infrastructure provider level. The request includes an indication regarding a required availability and reliability level which is to be achieved by the resources of the virtual network. At an infrastructure provider level the request is processed in order to determine the required availability and reliability level, and it is checked whether the required availability and reliability level is achievable for the resources to be provided for the virtual network. A result (confirmation or denial) of the check is sent back to the virtual network operator level. |
| US09674110B2 |
Resource release method, communication equipment, and network system
A method, a UE and a communications system for releasing resources are disclosed. When the UE is in a CELL_FACH state, a resource release indication is transmitted from a network equipment to the UE to instruct the UE to release HS-RACH resources on the UE. Upon receiving the resource release indication, the UE releases previously allocate HS-RACH resources on the UE. |
| US09674106B2 |
Methods and apparatus for secure remote connection
A method and system for establishing a helpdesk session between a subscriber device and a customer support representative (CSR) device following a request for a helpdesk session. The system issuing, on receipt of said request, a credential pair comprising subscriber credentials for a subscriber device and CSR credentials for a CSR device which is paired with the subscriber device. The subscriber credentials are transferred to the subscriber device and the CSR credentials are transferred to the CSR device. The subscriber and CSR credentials are then transferred to a core node for authentication. If the credentials are authentic the helpdesk session between the paired subscriber device and the CSR device is established. |
| US09674105B2 |
Applying a platform code level update to an operational node
Provided are a computer program product, system, and method for applying a platform code level update to update a source partition in a computing system. Computational resources in the computing system are allocated to a destination partition. A code load is applied to the destination partition to implement an updated platform code level comprising an update to the platform code level on the source partition while the source partition is operational and processing computing requests. Submission of new transactions to the source partition is blocked in response to applying the code load to the destination partition. An operational environment and system state at the source partition are migrated to the destination partition in response to blocking submission of new transactions to the source partition. Transactions are directed to the destination partition intended for the source partition in response to migrating the operational environment and system state to the destination partition. |
| US09674104B1 |
Adapting proportional integral controller enhanced algorithm for varying network conditions in a network environment
An example method for adapting Proportional Integral controller Enhanced (PIE) algorithm for varying network conditions is provided and includes estimating an average dequeue rate at which packets are dequeued from a queue of packets maintained in a buffer in a network element operating, estimating a current queuing latency for the queue of packets based on the average dequeue rate, determining a target delay based on the average dequeue rate, the target delay varying with the average dequeue rate according to a predetermined relationship, and calculating a current drop probability associated with a probability that packets arriving at the buffer will be dropped or marked, the current drop probability being calculated using at least the current queuing latency and the target delay. In some embodiments, a threshold for a number of bytes dequeued from the buffer is estimated based on network conditions. |
| US09674098B2 |
Credit flow control for ethernet
One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class. |
| US09674096B2 |
Rate adaptation
The present solution relates a method in a first communication node (301) for rate adaptation of communication between the first communication node (301) and at least one second communication node (302). The first communication node (301) and the at least one second communication node (302) being comprised in a communication network (300). The first communication node (301) receives a message from the second communication node (302). The message comprises a communication window size of the second communication node (302). The communication window size of the second communication node (302) is stored. Then, the first communication node (301) obtains the communication window size of the first communication node (301), i.e. its own communication window size. The first communication node (301) transmits a message to the second communication node (302). The message comprises the obtained communication window size of the first communication node (301). |
| US09674091B2 |
Congestion causation in a network interconnect
A method and system for detecting congestion in a network of nodes, abating the network congestion, and identifying the cause of the network congestion is provided. A congestion detection system may comprise a detection system, an abatement system, and a causation system. The detection system monitors the performance of network components such as the network interface controllers and tiles of routers to determine whether the network is congested such that a delay in delivering packets becomes unacceptable. Upon detecting that the network is congested, an abatement system abates the congestion by limiting the rate at which packets are injected into the network from the nodes. Upon detecting that the network is congested, a causation system may identify the job that is executing on a node that is the cause of the network congestion. |
| US09674084B2 |
Packet processing apparatus using packet processing units located at parallel packet flow paths and with different programmability
A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit. |
| US09674083B2 |
Path calculation order deciding method, program and calculating apparatus
A path calculation order determining method executed by a calculating apparatus for calculating a shortest path between a node pair in a network, using information on calculated shortest paths between other node pairs, the method including: a step storing calculated shortest path group information on shortest path groups each including calculated shortest paths from a starting node to one or more terminating nodes except the starting node, and topology information of the network, in a memory medium; and a calculation step of calculating shortest paths, starting from its starting node other than the starting node on the calculated shortest paths and having the most nodes that are located downstream therefrom, and terminating at nodes other than its starting node, using the calculated shortest path group information or the topology information for a path not included in the calculated shortest path group. |
| US09674080B2 |
Proxy for port to service instance mapping
A method for managing a chain of service appliances. A method for interoperating with a legacy service appliance which does not understand/interpret the service chain header format. The method specifies a proxy device which receives a data packet with chain header that contains a chain ID. The chain ID identifies a particular service chain of network services to be performed on the data packet by a plurality of service appliances. The method removes a chain header from the data packet. The method sends the data packet to the service appliance via a logical port that corresponds to the data packet's chain ID. The method includes receiving the data packet back from the service appliance via the logical port. Lastly, the method includes restoring the chain header in the data packet based upon the logical port through which the data packet is received. |
| US09674079B1 |
Distribution layer redundancy scheme for coupling geographically dispersed sites
In one embodiment, a plurality of first connections each couple a first distribution node of a first site to a respective access device. A second connection between the first distribution node and a first edge router is configured to not forward traffic associated with a first set of virtual local area networks (VLANs). It is determined whether the second distribution node is reachable from the first distribution node through the first edge router and a second edge router. The second distribution node is configured to forward traffic associated with the first set of VLANs to the second edge router. In response to a determination that the second distribution node is unreachable, the second connection is configured to forward traffic associated with the first set of VLANs. Traffic associated with the first set of one or more VLANs may be forwarded across the second connection to the first edge router. |
| US09674076B2 |
Set up of direct mapped routers located across independently managed compute and storage networks
Embodiments relate to setting up direct mapped routers located across independently managed compute and storage networks for enabling multiple modes of communication over the cross-coupled links between the networks. An aspect includes identifying a characteristic of a local entity based on a unique location identifier assigned to the local entity and learning a characteristic of a remote entity based on a location identifier received over a cross-coupled link between the local entity and the remote entity. A port on a local entity router is then correlated with the received location identifier of the remote entity. A route is then built in the direct mapped router table at a location pointed to by the location identifier of the remote entity. An optimistic failover route is established from a storage entity to a compute entity when a cross-coupled link between the storage entity and the compute entity is broken. |
| US09674073B2 |
Method and arrangement for route cost determination and selection with link cost interaction
This invention extends routing mechanisms that use link metrics for route selection so that: A link metric cross correlation vector is determined for all links, where each element in the vector corresponds to some other link, and reflects the change in the link metric value if a data flow would already use this other link. The invention further describes a specific embodiment where all cross-correlating links are adjacent to each other, i.e., they terminate or originate in a common node. A mechanism is described to create an extended routing graph. This extended graph permits the use of standard polynomial time algorithms that simultaneously construct the optimal route and find the optimal route metric (such as shortest-path algorithms) also for the adjacent link cross-correlating case. |
| US09674066B2 |
Method for parsing an information string to extract requested information related to a device coupled to a network in a multi-protocol remote monitoring system
A method, system, and computer program product for parsing an information string to extract requested information related to a remotely monitored device communicatively coupled to a network, including accessing the device using an HTTP protocol to obtain an information string associated with the device; determining, based on a type of the requested information, data extraction information for optimally extracting the requested information from the device; parsing the information string according to the data extraction information to identify substrings within the information string; and determining the requested information based on the information string, identified substrings, and the data extraction information. |
| US09674060B2 |
Dynamic and selective management of integration points using performance metrics
In one embodiment, a computer-implemented method for dynamic management of integration points includes connecting a set of applications to a communication interconnect fabric to form a set of connections, wherein each application in the set of applications is interconnected and each individual connection has a set of integration paths defined including a default path. The set of connections is monitored to determine whether a performance metric for a specific application in the set of applications is within a predefined tolerance. Responsive to a determination that the performance metric for the specific application in the set of applications is not within a predefined tolerance, a change may be instructed in availability of an integration component. |
| US09674059B2 |
Monitoring of availability data for system management environments
A method and system for monitoring availability data of a system management (SM) environment. In response to determining that a retrieved connection configuration establishes communication between a SM environment and a SM portal server that includes a central repository, availability data is collected from an availability module. The availability data pertains to availability of resources at endpoints of one or more terminal systems. The connection configuration is associated with the SM environment. Te SM environment is coupled to the SM portal server and the availability module. The SM environment includes the one or more terminal systems. |
| US09674058B2 |
Time series data processing device, time series data processing method, and computer-readable recording medium storing time series data processing program
A time series data processing device for processing time series data that is a sequence of data received from a system that is a processing target over time includes a time series data search processing unit that receives, for details of the time series data and occurrence time information, a time series data search condition including events of a plurality of the time series data and an interval condition that is a condition of time intervals of the events occurring, and changes the interval condition using an allowable time lag that is allowable time of a set time lag in a transmission source of the time series data to thereby reflect the set time lag in the time series data search condition; and a data monitoring unit that monitors the time series data received from the system that is the processing target, using the time series data search condition changed by the time series data search processing unit. |
| US09674056B2 |
Call routing and real-time monitoring
A method and system for providing call routing analytics. A virtual session initiation protocol switch is provided and hosted in an Internet cloud-based environment. The switch streams live call detail records to a computer system having a processor configured to process all of the subscriber's call records to monitor route performance for the subscriber. Real-time route performance data is transmitted to the subscriber for display at a subscriber computer. The subscriber can then alter a routing of at least a portion of the call utilizing the switch in response to the real-time route performance data to increase quality of signaling and business performance. |
| US09674052B2 |
Data packet stream fingerprint
Techniques for identifying stream fingerprints are provided. A stream of data packets may be received. In one aspect, a stream fingerprint may be determined based on the stream of data packets. An application associated with the stream may be determined based on the stream fingerprint. In another aspect, a stream may be partially matched while a fully matched stream fingerprint has not been determined. As additional packets are received, the stream may become fully matched. |
| US09674050B2 |
Handheld device for on-site datacenter management
In various exemplary embodiments, a system and associated method to provide management of a plurality of electronic elements in a datacenter is disclosed. The system includes a datacenter management system coupled to a wireless network to receive information regarding a spatial location of a handheld device within the datacenter. The datacenter management system provides information to the handheld device related to each of the plurality of electronic elements. The datacenter management system includes a management processor to process information related to each of the plurality of electronic elements and a database to store information related to each of the plurality of electronic elements. |
| US09674044B2 |
Transparent middlebox with graceful connection entry and exit
Methods for inserting a middlebox into a network connection include monitoring network state information in a connection between a client and a server. When the connection is idle, a connection entry is created for each device and is initialized using state information gathered by monitoring the network connection. Redirection of the network connection is activated between the client and the server such that the middlebox mediates the connection. Methods for removing a middlebox from a network connection include determining a degree of mismatch between a sequence number in a first connection between the middlebox and a client and a sequence number in a second connection between the middlebox and a server, delaying acknowledgment signals from the middlebox on a connection to decrease the degree of mismatch, and establishing a direct connection between the client and the server without mediation by the middlebox when the degree of mismatch is zero. |
| US09674043B2 |
Systems and methods for automatically clustering devices
A system including a parent device is provided. The parent device includes a power output configured to provide output power to an external device, a first network interface configured to exchange data with at least one external device, and at least one controller coupled to the power output and the first network interface. The controller is configured to determine an identifier of the parent device, transmit an identification message to a child device via the power output, the identification message including the identifier of the parent device, and receive a response to the identification message via the first network interface, the response including an identifier of the child device. |
| US09674040B2 |
Network topology discovery and obsolescence reporting
Implementations of the present disclosure involve an apparatus and/or method for a network topology discovery engine that detects one or more network elements and/or one or more connections between a plurality of network elements. The network topology discovery engine transmits a request for operational and connection information from at least one network element. In response, network topology information is received by the network topology discovery engine by one or more elements of the network that provide information on the topology and operational state of the telecommunications network. The received information may then be stored in a network topology database. This network topology database may be utilized by the network or a related component for information or maintenance of the telecommunications network, such as an obsolescence tracker to detect one or more network elements that could be replaced or upgraded. |
| US09674037B2 |
Centralized management of access points
Systems and methods are provided for centralized access, control, and management of APs. According to one embodiment, multiple APs of a private IP network are decoupled from potentially transient IP addresses by assigning a unique identifier to each of the multiple APs by an AC. An AC GUI is presented by the AC to an administrator through which (i) commands are provided by the administrator and (ii) the administrator is provided with access to a first AP of the multiple APs responsive to a command received from the administrator though the AC GUI and based upon the first AP's assigned unique identifier. The first AP is accessed, controlled or debugged by the AC based on the command. The access to the first AP enables a first AP GUI of the first AP through which the network administrator is provided with an ability to issue multiple commands to the first AP. |
| US09674033B2 |
High performance and grid computing with liveliness and deadlines fault tolerant data distributor quality of service
High performance computing (HPC) and grid computing processing for seismic and reservoir simulation are performed without impacting or losing processing time in case of failures. A Data Distribution Service (DDS) standard is implemented in High Performance Computing (HPC) and grid computing platforms, to avoid the shortcomings of current Message Passing Interface (MPI) communication between computing modules, and provide quality of service (QoS) for such applications. QoS properties of the processing can be controlled. Multiple data publishers or master nodes of a cluster have access to the same data source. Each of these publishers has an ownership strength quality of service, and the publisher with the highest ownership strength number is the designated publisher of the data to subscriber processor nodes of the cluster. If the designated data publisher prematurely terminates or crashes for some reason, then the publisher node with the next highest ownership strength measure is designated as data publisher and continues publishing data to subscribers. The QoS properties include ability to switch to a different designated publisher when the input data is being processed in real time, and a specified deadline time has passed during which data has not been published. |
| US09674031B2 |
Automated management of a distributed computing system
A system, method and computer program product are provided for managing a distributed computing system that features multiple hosts executing a distributed application. On each host a collector process collects application-level and/or system-level metrics and reports them to a data repository. A controller executes actor processes that compare the metrics, and/or trends in the metrics, to predetermined thresholds. If a threshold is met or passed, the corresponding actor or the controller initiates one or more remedy processes that take action intended to alleviate the condition detected by the actor. When a remedy is triggered, the controller takes a snapshot of the system to identify the current state, and saves information indicating how well the executed remedies corrected the situation. When a new snapshot matches an existing snapshot, the controller uses the saved information to determine which remedies to apply to the present occurrence of the mutual state. |
| US09674028B2 |
Device and method of simultaneous data transmission service over heterogeneous networks
A multi-network based-simultaneous data transmission service is performed by: transmitting, over one or more networks, two or more partial data divided from data to be transmitted in relation to a particular service; when a network switching of the one or more networks is required, identifying a type of the particular service; and performing the network switching at a network switching timing controlled based on the identified type of the particular service. |
| US09674026B1 |
Beam position monitor for energy recovered linac beams
A method of determining the beam position in an energy recovered linac (ERL). The method makes use of in phase and quadrature (I/Q) demodulation techniques to separate the pickup signal generated by the electromagnetic fields generated by the first and second pass beam in the energy recovered linac. The method includes using analog or digital based I/Q demodulation techniques in order to measure the relative amplitude of the signals from a position sensitive beam pickup such as a button, strip line or microstripline beam position monitor. |
| US09674024B2 |
Method for transmitting a signal with a preamble and corresponding devices, signal with corresponding preamble for synchronization of a receiver
The invention relates to a method of transmitting a signal comprising successive multi-carrier symbols with M subcarriers arranged in a frame, defined by a preamble comprising a first multi-carrier symbol: P 0 [ k ] = ∑ m = 0 M - 1 p m , 0 g [ k ] ⅇ j 2 π M m ( k - D 2 ) ⅇ j π m 2 and a second multi-carrier symbol: P 1 [ k ] = ∑ m = 0 M - 1 p m , 1 g [ mod ( k - N , M ) ] ⅇ j 2 π M m ( k - D 2 ) ⅇ j π ( m + 1 ) 2 . The pilot symbols pm,0 are such that: p m , 0 = { α m , m even 0 , m odd and p m , 1 = { p m , 0 ( - j ) , m even 0 , m odd with αm a real random variable. |
| US09674023B2 |
Systems for communicating using multiple frequency bands in a wireless network
Communication signals using a first and a second frequency band in a wireless network is described herein. The first frequency band may be associated with a first beamwidth while the second frequency band may be associated with a second beamwidth. An apparatus may include receiver circuitry arranged to receive first signals in a first frequency band associated with a first beamwidth and second signals in a second frequency band associated with a second beamwidth, the first signals comprising a frame synchronization parameter and the second signals comprising frame alignment signals. The apparatus may further include processor circuitry coupled to the receiver circuitry, the processor circuitry arranged to activate or deactivate the receiver circuitry to receive the frame alignment signals based on the frame synchronization parameter. Other embodiments may be described and/or claimed. |
| US09674017B2 |
Method and apparatus for spectrum spreading of a pulse-density modulated waveform
Methods and systems are provided for spreading spectral density of pulse streams during digital to analog conversion. An example spreading circuit may comprise an accumulator circuit, a bit generator circuit, a comparator circuit, and an inverter circuit. The accumulator circuit may be operable to receive a signal to be spread and generate an output based on the signal to be spread and at least one other input. The bit generator circuit may be operable to input into the accumulator circuit zero-sum sequences. The comparator circuit may be operable to provide a stream of pulses based on the output of the accumulator circuit. The inverter circuit may be operable to invert output of the comparator circuit, wherein output of the inverter circuit is input into the accumulator circuit. |
| US09674007B1 |
Automatic multiple input multiple output (MIMO) transmitter order detection
Systems and methods are disclosed herein to provide automatic identification of radio frequency (RF) transmitter chains during the testing of wireless data communication devices and systems, including Multiple Input Multiple Output (MIMO) devices and systems utilizing beamforming. In accordance with one or more embodiments, a signal analysis function is disclosed that identifies the ordinal index of each MIMO RF transmitter chain associated with a Device Under Test (DUT) using the Cyclic Shift Delay (CSD) imposed on the transmitted MIMO signal. Such a system may offer improved capabilities such as automated detection of mis-cabled test setups, automated recovery from mis-cabling, and automated adaptation of transmitted test signals to counteract the effects of mis-cabling. |
| US09674000B2 |
Method product the controlling a codec negotiation of a gateway, a computer program product for executing the method, and a communication system for controlling the codec negotiation
A method of controlling a codec negotiation of a gateway (1) providing a codec capability offer, e.g. OLC according to the standard H.245, for establishing a data connection (1A, NA, 5T, 12T) to a communication device (10), comprises the gateway (1) providing a DSP resource (5A, 5B) for encoding (C1E) and/or decoding (C1D) of data to be transmitted using a codec which is negotiated between the gateway (1) and the communication device (10), and controlling the gateway (1) to limit (4B1, 4B2, CA2, CA14) a selection of codecs available at the gateway (1) from at least two codecs reserving different amounts of the DSP resource (5A, 5B) respectively, to be included in the codec capability offer to a codec which reserves the least amount of the DSP resource (5A, 5B) such that the communication device (10) is forced (CA4, CA15) to select the codec which reserves the least amount of the DSP resource (5A, 5B). |
| US09673999B2 |
Member device of stacked switches system
A member device of a stacked switches system sends a first received unicast packet via an inter-group stack port which belongs to an aggregated stack link group on a forwarding path towards a different stack group when the first received unicast packet is to be egressed by another member device in the different stack group. The member device is further to send a second received unicast packet via an intra-group stack port on a forwarding path towards another member device in a same stack group when the second received unicast packet which is to be egressed by the another member device in the same stack group. The member device is further to send a third received unicast packet via a data port on the member device which associates with a egress port identification of the third received unicast packet when the third received unicast packet is to be egressed by the member device. |
| US09673998B2 |
Differential cache for representational state transfer (REST) API
System and method of differential cache control. Different parts of a representation are controlled by different cache expiration times. A differential control scheme may adopt a hierarchical control structure in which a subordinate level control policy can override its superordinate level control policies. Different parts of the representation can be updated to a cache separately. Differential cache control can be implemented by programming a cache control directive in HTTP/1.1. Respective cache expiration time and their control scopes can be specified in a response header and/or response document provided by a server. |
| US09673997B2 |
Managing a system between a telecommunications system and a server
A call is managed between a network and a telecommunications system (10) including a gateway (13), one or more interface devices (14-16) each of which can be connected to the gateway, and one or more sensors (17A, 17B) of information relating to the respective environments of the interface devices. The sensor senses information relating to the respective environments of the interface devices. Then, as a function of the sensed information, an interface device is selected. Finally, the selected interface device is connected with the gateway to enable a call between the selected interface device and the network. |
| US09673996B1 |
Redirection of a streaming media session in an anticipated failover scenario
Disclosed herein is a method and system for providing streaming media to a client device. Specifically, in a streaming media session that is initially ongoing between a content server and a client device via a first proxy server: (i) the first proxy server may determine that an interruption in the streaming media session is going to occur and responsively (a) send a transfer request to the client device and (b) send session information to a second proxy server, the session information comprising information identifying the streaming media session and a progress indicator that indicates a current status of the streaming media session, and (ii) after the transfer request and the session information is sent, continuing the streaming media session via the second proxy server. The second proxy server uses the progress indicator as a basis to continue the streaming media session with the client device. |
| US09673995B2 |
Communication device and method for redundant message transmission in an industrial communication network
For redundant message transmission in an industrial communication network having an arbitrarily meshed network topology, mutually independent paths are ascertained for a communication link that is redundant at least in sections between two network nodes within the industrial communication network, where the mutually independent paths comprise separate network nodes of a single communication network, and messages with duplicate identifiers are interchanged between transmission and reception units of communication devices of the industrial communication network in accordance with forwarding rules that correspond to the ascertained paths. |
| US09673991B2 |
Distributed control scheme for remote control and monitoring of devices through a data network
A device automation system for providing automatic control of one or more devices in an environment includes a hub in communication with the one or more devices and with a data network where the hub is configured to issue commands to the devices and receive data from the devices; and a central server in communication with the hub through the data network where the central server is configured to install one or more automation applications in the hub or on the central server for handling events generated at the devices. Each of the automation applications responds to an event and issuing an action in response. The central server is configured to determine that a first set of the events is to be handled at the hub while a second set of events is to be handled at the central server. |
| US09673988B2 |
Systems and methods for certifying devices to communicate securely
A virtual private network (VPN) over a telecommunications network is created by sending a request from a first VPN device to a second VPN device for establishing a VPN between the first and second VPN devices. The request includes a first signed certificate having a verified VPN parameter for the first VPN device. A reply is received at the first VPN device from the second VPN device that includes a second signed certificate having a verified VPN parameter for the second VPN device. The VPN is established between the first and second VPN devices based on each verified VPN parameter for each of the first and second VPN devices. |
| US09673987B2 |
Computerized system and method for deployment of management tunnels
Methods and systems for deploying management tunnels between managed and managing devices are provided. According to one embodiment, the use of PKI-authenticated serial numbers within network devices manufactured by a particular manufacturer enables one-step provisioning of one or more managed devices. A managed device is provisioned with the serial number of a management device manufactured by the particular manufacturer. When the managed device is installed within a network, the management device is located by the managed device with the assistance of a locator server and the managed device initiates establishment of an encrypted management tunnel with the management device. Prior to allowing the management device to use the management tunnel to perform management functionality in relation to the managed device, credentials of the management device are verified by the managed device by comparing the PKI-authenticated unique identifier of the management device to that which is stored within the managed device. |
| US09673984B2 |
Session key cache to maintain session keys
Scalable session management is achieved by generating a cookie that includes an encrypted session key and encrypted cookie data. The cookie data is encrypted using the session key. The session key is then signed and encrypted using one or more public/private key pairs. The encrypted session key can be decrypted and verified using the same private/public key pair(s). Once verified, the decrypted session key can then be used to decrypt and verify the encrypted cookie data. A first server having the private/public key pair(s) may generate the cookie using a randomly generated session key. A second server having the same private/public key pair(s) may decrypt and verify the cookie even if the session key is not initially installed on the second server. A session key cache may be used to provide session key lookup to save public/private key operations on the servers. |
| US09673982B2 |
Efficient hardware trust verification in data communication systems that comprise network interface cards, central processing units, and data memory buffers
In a data communication network, Network Interface Cards (NICs) receive user data and interrupt Central Processing Units (CPUs) that then transfer buffer descriptors for the user data to Data Memory Buffers (DMBs). The DMBs receive the buffer descriptors from the CPUs and transfer the buffer descriptors to the NICs. The NICs receive the buffer descriptors and responsively transfer the user data to the DMBs. The DMBs buffer the user data. A master NIC transfers a CPU hardware-trust validation challenge to a master CPU. The master CPU hashes the validation data with its physically-embedded, hardware-trust code to generate and transfer a CPU hardware-trust validation result. The master NIC processes the CPU hardware-trust validation result to verify hardware-trust of the master CPU. |
| US09673977B1 |
Refreshing public parameters in lattice-based cryptographic protocols
In a general aspect, a parameter is refreshed in a lattice-based cryptography system. In some aspects, a first value of a public parameter is obtained. The first value of the public parameter may have been previously used in an execution of a lattice-based cryptography protocol. A second value of the public parameter is generated based on the first value of the public parameter and random information. The second value of the public parameter is used in an execution of the lattice-based cryptography protocol. |
| US09673974B2 |
Method, apparatus, and system for performing an establishment of a security context between user equipment and an access node by a base station
Embodiments of the present invention discloses a method, an apparatus, and a system for establishing a security context and relates to the communications field, so as to comprehensively protect UE data. The method includes: acquiring an encryption algorithm of an access node; acquiring a root key and deriving, according to the root key and the encryption algorithm, an encryption key of the access node; sending the encryption key and the encryption algorithm to the access node, so that the access node starts downlink encryption and uplink decryption; sending the encryption algorithm of the access node to the UE so as to negotiate the encryption algorithm with the UE; and instructing the access node to start downlink encryption and uplink decryption and instructing, during algorithm negotiation, the UE to start downlink decryption and uplink encryption. The present invention mainly applies to SCC security protection. |
| US09673973B1 |
Decentralized authoritative messaging
A secure chat client is described that allows users to exchange encrypted communications via secure chat rooms, as well as one-to-one communications. In particular, the secure chat client allows users to create, configure, and manage secure chat rooms. Furthermore, the secure chat client provides users with the ability to recover secure messages when they obtain a new device or otherwise lose communications. |
| US09673972B2 |
Phase interpolator
Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. |
| US09673971B2 |
Automatic clock calibration of a remote unit using phase drift
An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames. |
| US09673965B2 |
Calibrating a serial interconnection
A method for calibrating a serial interconnection system having a first node, a second node, calibration nodes that are electrically connected in series by the serial interconnection system, and connection nodes corresponding to the serially connected calibration nodes, the connection nodes electrically connected in series by the serial interconnection system, the calibration method involving: for each of the calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, measuring the phase difference of signals appearing at the first and second nodes; from the measured phase differences for the calibration nodes, computing phase corrections for each of the calibration nodes; and applying the phase corrections computed for each of the calibration nodes to the corresponding connection nodes. |
| US09673964B2 |
Active load modulation in near field communication
An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal. |
| US09673962B1 |
System and method for reducing false preamble detection in a communication receiver
An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet. |
| US09673961B2 |
Multi-lane N-factorial (N!) and other multi-wire communication systems
System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link. |
| US09673960B2 |
Full duplex reconfigurable antenna self-interference cancellation systems
Embodiments of full-duplex systems with reconfigurable antennas are described. In one embodiment, a full-duplex reconfigurable antenna transceiver includes a transmit chain, a receive chain, and a reconfigurable antenna having a plurality of reconfigurable modes. The transceiver may also include an antenna controller configured to set a mode of the reconfigurable antenna. According to other aspects, the transceiver may also include a signal processor configured to transmit a set of training symbols during a training interval. The antenna controller may be further configured to select a respective mode of the reconfigurable antenna for each training symbol in the set of training symbols. Additionally, the antenna controller may be configured to calculate a received Signal-of-Interest to Interferer Ratio (SIR) for each training symbol of the set of training symbols. In this context, a full-duplex system utilizing a reconfigurable antenna may achieve significant rate improvement compared to half-duplex systems. |
| US09673958B2 |
Information transmission network and node
This network comprising functional nodes connected in series by information transmission means, in which the information assumes the form of discrete messages propagating from node to node in the network, is characterized in that the information transmission means for transmitting information between the nodes are bidirectional so as to allow information to propagate in both directions of flow of the network, and each node includes at least one first and one second associated port, for information input/output, connected to adjacent nodes by corresponding information transmission means and the operation of which is controlled by communication automaton means, between an operating mode for the asynchronous reception of information from its adjacent nodes and an operating mode for the synchronous transmission of information to the nodes adjacent thereto, and in that the communication automaton means are suitable for triggering the activation of the communication of information from the node to its adjacent nodes following the beginning (71, SOF) of the reception of information from each of them. |
| US09673954B2 |
Radio communication device and constellation control method
A base station is provided for receiving an acknowledgement or negative acknowledgement (ACK/NACK) signal, including a transmitting unit configured to transmit a control signal using one or a plurality of CCE(s). The base station also includes a receiving unit configured to receive an ACK/NACK signal, the ACK/NACK signal being multiplied by an orthogonal sequence, by a sequence defined by a cyclic shift, and by either a first value or a second value, wherein the first value rotates a constellation of the ACK/NACK signal by 0 degrees and the second value rotates the constellation of the ACK/NACK signal by N degrees, which is different from 0 degrees. |
| US09673952B2 |
Method and apparatus for supporting user equipments on different system bandwidths
Techniques for supporting communication for different user equipments (UEs) on different system bandwidths are described. In one design, a base station transmits first control information to support communication for at least one first UE on a first system bandwidth and transmits second control information to support communication for at least one second UE on a second system bandwidth, which overlaps the first system bandwidth. The base station transmits data to the first and second UEs on the first and second system bandwidths, respectively. In one design, the base station receives third control information from the first UE(s) and fourth control information from the second UE(s) on a third system bandwidth. The base station receives data from the first UE(s) on the third system bandwidth and receives data from the second UE(s) on a fourth system bandwidth, which overlaps the third system bandwidth. |
| US09673946B2 |
Transmit beamforming sounding with traveling pilots
This document discusses, among other things, apparatus and methods for transmit beamforming sounding. An example method for communicating over a wireless network having multiple sub-carrier frequencies can include assigning a first pilot signal to a first sub-carrier frequency for transmission with a first symbol, transmitting the first symbol from a first wireless device, receiving the first symbol at a second wireless device, determining channel time and phase offset using the first pilot signal, and estimating transmit beamforming channel state information using the first pilot signal. |
| US09673945B2 |
Implicitly linking aperiodic channel state information (A-CSI) reports to CSI-reference signal (CSI-RS) resources
Certain aspects of the present disclosure provide techniques for implicitly linking aperiodic channel state information (A-CSI) reports to CSI-reference signal (CSI-RS) resources. In an aspect, the UE may be instructed to report on specific CSI-RS resource(s) via explicit signaling in the UE grant. Other aspects disclose techniques for implicit CSI-RS resource selection by the UE that require fewer signaling resources. Instead of explicitly signaling CSI-RS resources to the UE, the UE may implicitly select CSI-RS resource for CSI feedback reporting based on information known to the UE, e.g. a subframe on which a reporting request is received. This may reduce the impact of the additional signaling in the UE grant. |
| US09673944B2 |
Method for controlling packet access, network side device, terminal device and communication system
Embodiments of the present invention provide a method for controlling packet access, a network side device, a terminal device and a communication system. The method includes: generating an access trigger message, where the access trigger message carries a temporary mobile group identity TMGI allocated to a user equipment UE; and sending the access trigger message to packet trigger an access operation of the UE for the TMGI. In the embodiments of the present invention, the group identity TMGI already existing in an MBMS can be used as the group identity of packet triggering UE access, and the access trigger message carrying the TMGI can be correspondingly generated and sent so as to trigger an access operation of the UE belonging to the TMGI, thereby implementing the function of the packet triggering user access. |
| US09673940B2 |
Method for transmitting/receiving signal and device therefor
The present invention relates to a wireless communication system. More particularly, the present invention relates to a method and a device for a terminal to transmit an uplink signal according to a normal HARQ operation in a wireless communication system supporting a carrier merge, the method comprising the steps of: forming a first cell set with a FDD and a second serving cell set with a TDD; receiving a PHICH signal from a subframe #(n−m−p) of the first serving cell, or receiving a PDCCH signal from a subframe #(n−m) of the first serving cell; and transmitting a PUSCH signal from a subframe #n of the second serving cell, in correspondence to the PHICH signal or the PDCCH signal, wherein n is an integer greater than or equal to 0, m is an integer greater than or equal to 1, and p is an integer greater than or equal to 1. |
| US09673939B2 |
HARQ-ACK handling for unintended downlink sub-frames
Disclosed in some examples is a method for providing a HARQ response in an LTE network for a PUCCH format 1b. The method includes receiving one or more downlink assignments of a bundling window over a wireless downlink control channel; setting a reception status for each sub-frame of a downlink data channel in the bundling window based on whether the sub-frame on the downlink data channel was associated with a particular one of the received downlink assignments and based upon whether the sub-frame was successfully received; setting a reception status of sub-frames of the downlink data channel in the bundling window that did not have a corresponding downlink assignment to a predetermined value; and transmitting a response, the response based upon the reception statuses set by the response module. |
| US09673937B2 |
Adaptive network communication protocols
A computer-implemented method includes sending one or more network packets. Each of the one or more network packets includes a network packet header. The computer implemented method further includes receiving a negative acknowledgement list comprising the network packets not received. The computer-implemented method further includes, responsive to the receiving of a negative acknowledgment list: For each network packet of the negative acknowledgment list, transforming the network packet header into a modified packet header to yield a modified packet. The computer-implemented method further includes combining each modified packet into a modified packet list. The computer-implemented method further includes generating one or more repair packets. Each of the one or more repair packets further include a repair packet header and a portion of the modified packet list. The computer-implemented method further includes sending the one or more repair packets. A corresponding computer system and computer program product are also disclosed. |
| US09673934B2 |
Error correction on demand
Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block. |
| US09673927B2 |
Wireless communication apparatus, wireless communication system, and wireless communication method
A wireless communication apparatus, a wireless communication system, and a wireless communication method enabling any plurality of apparatuses to engage in time division multiplex communication for communicating a plurality of data even if not all apparatuses in the network are accurately synchronized, perform a time division multiplex connection method of an autonomous distributed network that performs a continuous receiving (scan) operation over a frame period so as to obtain a grasp of the wireless communication apparatuses located at the neighborhood at predetermined periods, that includes the steps of receiving beacon signals from other wireless communication apparatuses to obtain a grasp of the wireless communication apparatuses that they are communicable with, calculating the reception slot of the wireless communication apparatus from the received beacon information, setting its own reception slot so as not to collide with the set situation thereof, and forming network autonomously engaging in time division multiplex communication with other wireless communication apparatuses located at the neighborhood. |
| US09673923B2 |
Methods and apparatuses for emergency notifications to the hearing impaired
Described are systems and methods for communicating emergency alerts to a hearing-impaired user. Queries are performed to one or more emergency alert databases to develop emergency alert notifications. At least some of the emergency alert notifications are filtered responsive to user selected criteria to select one or more filtered emergency alerts. An attention desired indicator is transmitted to a hearing-impaired user device that subscribes to a hearing-impaired relay service supported by the server if the one or more filtered emergency alerts are present. The filtered emergency alerts are transmitted to the hearing-impaired user device in response to a emergency information query from that user device. |
| US09673919B2 |
Systems, methods, and devices for evaluating signal quality and range
Systems, methods, and devices for evaluating wireless signal quality between environmental sensing and control devices. A signal quality device includes a sensor module, one or more user control devices, one or more display devices, and a processing unit. The signal quality device is configured to generate a first signal following activation of at least one of the one or more user control devices, wirelessly transmit the first signal, receive a second signal in response to the first signal, and activate the one or more display devices to provide an indication of the signal quality of the first signal. A wireless environmental controller includes a processing unit and is configured to receive the first signal, determine the signal quality of the first signal, generate the second signal related to the signal quality of the first signal, and wirelessly transmit the second signal. |
| US09673914B2 |
Method and apparatus for spectral stitching using reference channel and a pilot tone
A system and method sequentially measure the amplitude and phase of an output signal of a device under test in each of two or more frequency ranges which together span the output signal spectrum, using a local oscillator (LO) signal whose frequency changes for each measurement. The measured phase of the output signal is adjusted for at least one of the frequency ranges to account for a change of phase in the LO signal from measurement of one frequency range to another frequency range, including applying to the measured phase a phase offset determined by measuring the phase of a pilot tone using the LO signal before and after the frequency of the LO signal changes from measurement of one frequency range to another. The phase-adjusted measurements of the output signal in the two or more frequency ranges are stitched together to determine the amplitude and phase of the output signal across the output signal spectrum. |
| US09673910B1 |
Single-chip transceiver with electronic dispersion compensation for coherent optical channels
A transceiver for fiber optic communications. |
| US09673908B2 |
Device and a method for generating an electrical signal with a suppressed frequency band
Disclosed herein is a notch filter and a method for generating an electrical signal with a suppressed frequency band. The filter generates an optical signal by modulating a modulation optical wave with an electrical signal to generate first and second sidebands. The first sideband or the second sideband has less power than the other. The filter then modifies the optical signal by equalizing the power of light within the first side band at a selected frequency band and light within the second side band at the selected frequency band. The filter then produces an antiphase relationship between the light within the first side band at the selected frequency band and the light within the second side band at the selected frequency band. The filter then detects the modified optical signal to generate a copy of the electrical signal with suppressed frequency components within the selected frequency band. |
| US09673903B2 |
Method and apparatus for receiving visible light signal
The disclosure relates to a method and an apparatus for receiving a visible light signal. The method includes the following steps: controlling use of a camera as a light signal receiver to capture a group of continuous images covering an emitter, where the emitter emits visible light signals; and obtaining, from the group of continuous images, a visible light signal that comes from the emitter. In the disclosure, because a camera is used to receive a visible light signal, a visible light communication function can be implemented in various devices or systems under a premise that no hardware is newly added or modified. |
| US09673897B2 |
Optical network test instrument including optical network unit identifier capture capability from downstream signals
A test instrument can be coupled to a test point in a passive optical network to measure optical signals transmitted between an optical line terminal and an optical network unit in the optical network. The test instrument can capture an identifier of the ONU from downstream signals sent from the OLT to the ONU. |
| US09673894B2 |
Characterization of linear crosstalk on multiplexed optical signals
There is provided a method of determining at least one linear-crosstalk-related parameter of an optical signal-under-test having, within an optical channel bandwidth, at least a data-carrying signal contribution and a wavelength-dependent linear-crosstalk contribution arising from a data-carrying signal contribution of an adjacent optical signal associated with an adjacent channel to the optical signal-under-test, the method comprising: acquiring at least one optical spectrum trace encompassing a quasi-continuum of closely-spaced wavelengths over a spectral range extending to at least part of both the signal under test and the adjacent optical signal; and estimating said linear-crosstalk contribution using at least spectral properties of said at least one optical spectrum trace; wherein one of said at least one linear-crosstalk-related parameter is the linear-crosstalk contribution and is determined from said estimating. |
| US09673888B2 |
Acquiring LEO satellites without compass
A method and apparatus for establishing a communication link between a user terminal and a first satellite associated with a first satellite service are disclosed. The user terminal determines a position of the user terminal based, at least in part, on location information provided by a satellite positioning system (SPS) receiver associated with the user terminal, determines a reference azimuth of the user terminal based, at least in part, on a position of a second satellite associated with a second satellite service that is different than the first satellite service, obtains ephemeris data for the first satellite, and aligns a directional antenna of the user terminal with the first satellite based, at least in part, on the position of the user terminal, the reference azimuth of the user terminal, and the received ephemeris data. |
| US09673886B2 |
Apparatus and methods for radio frequency signal boosters
Provided herein are apparatus and methods for radio frequency signal boosters for cellular and broadcast television signals with Wi-Fi signals transmission function. Cell phone, Wi-Fi, and broadcast television signals are boosted and retransmitted over a shared antenna or over more than one antenna. In certain implementations, a multi-band signal booster is configured to provide signal path gain to at least three signal paths: a first signal path configured to receive a first time division duplexed Wi-Fi signal, a second signal path configured to receive a first frequency division duplexed mobile or cellular signal, and a second signal path configured to receive a broadcast television signal. |
| US09673880B2 |
Pilot signal transmission method, channel estimation method, and apparatus and system
A pilot signal transmission method, a channel estimation method, and an apparatus are provided, and the method for a pilot signal transmission includes: transmitting a pilot signal 1 CPICH1 over a first antenna, and transmitting a pilot signal 2 CPICH2 over a second antenna; transmitting a pilot signal CPICHk1 over a k1th antenna; and when it is determined that a terminal of a first category in the MIMO system is scheduled, transmitting a pilot signal CPICHk2 over the k1th antenna. Interference caused by a pilot signal to a traditional terminal is better reduced, performance of the traditional terminal is ensured while the terminal of the first category properly works in the MIMO system, and power consumption for transmitting a pilot signal is effectively reduced. |
| US09673878B1 |
Systems and methods for performing precoding in multi-user systems
Systems and methods are provided for precoding a signal at a transmitter. A plurality of receiver devices is identified, and a first receiver device is selected from the plurality of receiver devices. The transmitter communicates with the first receiver device over a channel, and an estimate of the channel is determined. A precoding matrix is computed based on the estimate, such that when the transmitter transmits a signal that is precoded with the precoding matrix over the channel, interference from a second receiver device of the plurality of receiver devices over the channel is reduced. |
| US09673874B2 |
System and method for controlling selection of network devices for beamforming
According to one embodiment of the invention, a network device comprises a plurality of antenna elements, one or more hardware processors, and a memory communicatively coupled to the one or more hardware processors. The memory comprises selective beamforming grouping logic that, upon execution by the one or more processors, aggregates a plurality of beamforming-enabled client devices within a coverage area of the network device. Furthermore, the selective beamforming grouping logic further categorizes the plurality of beamforming-enabled client devices into a plurality of groups based on a data transfer rate level supported by each of the plurality of beamforming-enabled client devices, determines a subset of client devices within a first group of the plurality of groups associated with a lowest data transfer rate level, and applies transmit beamforming simultaneously or at least concurrently for each client device of the subset of client devices. |
| US09673869B2 |
Communication apparatus configured to perform non-contact communication with external device
In response to receiving process-request information from an external device after starting operation by second power, a communication controller is configured to perform: a first supplying process of controlling a second power supply to supply the second power to a first communication node; a first data communication process of performing data communication with the first communication node after starting the first supplying process, wherein the first data communication process includes receiving process-related information from the first communication node; a determining process of, after finishing the first data communication process, determining whether data communication with a second communication node is necessary, based on the process-request information and on the process-related information; and a second supplying process of controlling the second power supply to supply the second power to the second communication node, in response to determining in the determining process that data communication with the second communication node is necessary. |
| US09673868B2 |
Wireless door lock power transfer system having communications capabilities
A door frame has a first electromagnetic coil and a door lock has a second electromagnetic coil with a door bolt electromagnetically coupling together the first and second electromagnetic coils, thereby forming a transformer. Power is transferred from the door frame to door lock through the transformer. Communications from the door frame to the door lock may be provided by modulating electromagnetic energy to the first electromagnetic coil and demodulating the modulated electromagnetic energy received at the second electromagnetic coil. Communications from the door lock to the door frame may be provided by varying a load on the second electromagnetic coil and detecting the load change at the first electromagnetic coil. |
| US09673863B2 |
Methods and system for increasing data transmission rates across a three-phase power system
A method for providing information by optimizing the data rate to a vehicle over a three-phase power line utilized to provide power to the vehicle is described. The method includes assigning three separate frequency bands to three respective conductors extending between a ground power system and the vehicle, generating carrier signals in three separate frequency bands and modulating various data onto three carrier signals to generate three transmission signals for sending the various data from the ground power system to the vehicle at frequencies within respective ones of the three separate frequency bands. The frequencies for each of the three separate frequency bands do not overlap one another. The method also includes switching the three transmission signals onto respective conductors of the three-phase power line, demodulating the various data within the vehicle, and providing the various data to one or more vehicle systems. |
| US09673862B1 |
System and method of analyzing crosstalk without measuring aggressor signal
A measurement instrument and associated method: receive at a measurement instrument at least one victim signal from a device under test (DUT), the victim signal including crosstalk interference from one or more aggressor signals which are not received by the measurement instrument; extract from the victim signal an ideal data pattern for the received victim signal, where the ideal data pattern does not include intersymbol interference (ISI), a noise component, or crosstalk interference to the victim signal; ascertain from the received victim signal and the ideal data pattern the ISI for the victim signal; produce a difference signal as a difference between: (1) the received victim signal; and (2) a sum of the ideal data pattern and the ISI; and ascertain from the difference signal a sum of the noise component and the crosstalk interference from one or more aggressor signals which are not received by the measurement instrument. |
| US09673859B2 |
Radio frequency bitstream generator and combiner providing image rejection
A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering. |
| US09673858B2 |
Fast frequency-hopping schedule recovery
In one embodiment, a device determines a need to resynchronize a broadcast and unicast frequency-hopping schedules on its network interface. In response to the need, the device may solicit the broadcast schedule from one or more neighbor devices having the synchronized broadcast schedule, and then establishes the unicast schedule for the network interface using communication during the synchronized broadcast schedule. |
| US09673857B2 |
Frequency hopping sequence generation
Techniques for frequency-hopping sequence-generation are described herein. In one example, a sequence of pseudo random numbers may be used to generate a scrambling sequence. The scrambling sequence may be used to map an unscrambled sequence of channels into a scrambled sequence of channels. Channel-repeats may be detected in the scrambled sequence of channels and resolved. Channel whitening may be performed to reduce channel overuse resulting from the channel-repeat resolutions. The scrambled sequence of channels may be provided to a radio to enable the radio to tune to the channels indicated by the scrambled sequence of channels. |
| US09673855B2 |
Adaptive transmission methods for multiple user wireless networks
An exemplary wireless communication network that includes a base that communicates with remote units located in a cell of the network. The base concatenates information symbols with a preamble corresponding to a destination remote unit. One or more remote units communicating with the base each concatenates information symbols with a preamble corresponding to that remote unit. An adaptive receiver system for a base unit rapidly adapts optimal despreading weights for reproducing information symbols transmitted from multiple remote units. A transmitter system for a base unit concatenates information symbols with a preamble associated with a remote unit in the cell. An adaptive receiver system for a remote unit in a communication network rapidly adapts optimal weights for reproducing a signal transmitted to it by a specific base unit in the network. |
| US09673853B2 |
Cascode power amplifier with voltage limiter
Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold. |
| US09673851B2 |
Retaining device for a mobile communication device
A retaining device for a mobile device having an accommodating module, into which the device can be inserted and on which a guide, support, and/or positioner for the device and a connector for electrically contacting the communication device are provided, and having a rotation module, on which the accommodating module is retained. The accommodating module can be rotated together with the rotation module about a first pivot axis from and to a first operating position and a second operating position. A housing is provided, in which the accommodating module and the rotation module are provided at least in some sections and on which the rotation module is retained. The accommodating module can be moved from an accommodating position, in which the device can be inserted into the accommodating module, to the first operating position and/or to the second operating position by rotating the accommodating module about a second pivot axis. |
| US09673849B1 |
Common mode extraction and tracking for data signaling
Systems, apparatuses, and methods for performing common mode extraction for data communication are disclosed. A circuit is configured to receive a single-ended data signal on a first input port and couple the data signal to a positive input terminal of a receiver component. The circuit is also configured to receive a differential clock signal on second and third input ports and generate a reference signal from the differential clock signal. In one embodiment, the reference signal is generated from an average of the differential clock signal. The circuit is configured to couple the reference signal to a negative input terminal of the receiver component. In one embodiment, the receiver component is an amplifier. |
| US09673847B1 |
Apparatus and methods for transceiver calibration
Apparatus and methods for transceiver calibration are provided. In certain configurations, a transceiver includes a transmit channel and an observation channel. The transmit channel includes a transmit mixer that up-converts a transmit signal by a first or transmit local oscillator frequency. The observation channel includes an observation mixer that down-converts an observed signal from the transmit channel by a second or observation local oscillator frequency that is offset from the first local oscillator frequency. By observing the transmit channel using a local oscillator frequency that is offset relative to the transmit channel's local oscillator frequency, the observation channel can observe transmit channel impairments substantially independently from observation channel impairments. |
| US09673842B2 |
Combining multiple desired signals into a single baseband signal
A transceiver for receiving multiple desired signals is described. The transceiver includes a first downconverter that receives a first received signal. The transceiver also includes a second downconverter that receives the first received signal. The transceiver further includes a first adder that receives an output of the first downconverter and a second received signal. The transceiver also includes a second adder that receives an output of the second downconverter. |
| US09673840B2 |
Turbo product codes for NAND flash
A method of encoding data in a data block includes generating a first XOR parity from an XOR of all data bits in the data block and an XOR of all row parities of all rows in the data block besides a last row, storing the first XOR parity in the last row, and generating a second XOR parity from an XOR of all column parities of all columns in the data block and an XOR of a parity of the last row. |
| US09673838B2 |
Parallel bit interleaver
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. |
| US09673826B2 |
Receiving device
According to one embodiment, a receiving device includes a first PLL circuit, a second PLL circuit, and a control circuit. The first PLL circuit includes a first VCO and extracts a first clock from a received first packet. The second PLL circuit includes a second VCO and outputs a second clock acquired by multiplying the received clock by N. The control circuit applies a control signal of the second VCO to a first line controlling the first VCO during a first time from start of reception of the first packet. |
| US09673822B2 |
Single wire interface
A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase. |
| US09673820B2 |
Low latency glitch-free chip interface
A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output. |
| US09673819B2 |
Metastability glitch detection
This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal. |
| US09673818B2 |
Semiconductor integrated circuit with data transmitting and receiving circuits
A data transmitting method used in a semiconductor device having a controller and a transmitter is described. A first write command is output by the controller and then a second write command is output by the controller. An interval time between the first write command and the second write command is calculated. The transmitter is activated by the controller and a first data is transmitted by the transmitter in accordance with the first write command, and then the transmitter is inactivated based on the interval time. Then the transmitter is activated when the transmitter is inactivated. Then, the second data is transmitted by the transmitter in accordance with the second write command. |
| US09673817B2 |
Mobile terminal and control method thereof
A method for operating a terminal according to an embodiment includes detecting an object that contacts the terminal, determining an operation of the terminal corresponding to the detected object, and performing the determined operation of the terminal. |
| US09673803B2 |
Semiconductor device, and on-vehicle electronic device and automobile each including semiconductor device
A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active. The temperature detector TD1 sets the temperature difference detection signal dt_ot to inactive when the temperature difference Tdif between the output transistor temperature Ttr and the ambient temperature becomes equal to or less than a reference temperature difference Tdref2, and sets the over temperature detection signal at_ot to inactive when the output transistor temperature Ttr becomes equal to or lower than a reference temperature Tref2. |
| US09673799B2 |
Sensing circuit with reduced bias clamp
A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner. |
| US09673797B2 |
Peak detector using charge pump and burst-mode transimpedance amplifier
A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor. |
| US09673791B2 |
Schmitt trigger circuit and power supply monitoring apparatus
A Schmitt trigger circuit according to an embodiment includes a voltage dividing circuit that divides an input voltage and outputs a divided voltage, and a basic Schmitt trigger circuit that includes a transistor as a current controlling element and controls current flowing through a light emitting diode (LED) included in an external photocoupler on the basis of the output voltage of the voltage dividing circuit proportional to the input voltage. The voltage dividing circuit has a positive temperature coefficient. |
| US09673788B2 |
Input buffer with selectable hysteresis and speed
A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage. |
| US09673783B2 |
Adaptive continuous-time filter adjustment device
A device includes a controller and an adaptive continuous-time filter that includes a control input and a first array of elements. The controller generates a digital word responsive to a time constant and compares a select bit of the digital word to a corresponding reference word to generate a control bit. The controller includes a duplicate array of elements, and applies the control bit to an adjustable element of the duplicate array of elements to modify the time constant. The controller provides the output word to the control input of the adaptive continuous-time filter to generate a filter response that accounts for effects of semiconductor process variation in the first array of elements. |
| US09673782B1 |
Center frequency and Q tuning of biquad filter by amplitude-limited oscillation-based calibration
Certain aspects of the present disclosure provide methods and apparatus for calibrating a tunable active filter. One example apparatus is a filter circuit that generally includes a tunable active filter comprising at least one amplifier and a first feedback path coupled between an input and an output of the at least one amplifier, the first feedback path comprising at least one switch; and an amplitude limiter coupled to the tunable active filter and comprising at least one transistor disposed in a second feedback path coupled between the input and the output of the at least one amplifier. |
| US09673771B2 |
Multilayer resonator and multilayer filter
A multilayer filter includes a plurality of mutually coupled resonant circuits provided within a multilayer body. Capacitor internal electrodes, inductor internal electrodes, and inductor via electrodes, ground via electrodes, and input-output via electrodes are arranged within the multilayer body. The ground via electrodes and the input-output via electrodes are provided on a dielectric layer on a mounting surface, or a second dielectric layer on a first dielectric layer provided on the mounting surface. The capacitor internal electrodes arranged towards the side of the mounting surface do not overlap the input-output electrodes when viewed in plan view. With this configuration, degradation in frequency characteristics of a resonant circuit is effectively prevented by controlling one of an inductive component and a capacitive component of the resonant circuit. |
| US09673770B2 |
Frequency domain multiband dynamics compressor with spectral balance compensation
A multiband dynamics compressor implements a solution for minimizing unwanted changes to the long-term frequency response. The solution essentially proposes undoing the multiband compression in a controlled manner using much slower smoothing times. In this regard, the compensation provided acts more like an equalizer than a compressor. What is applied is a very slowly time-varying, frequency-dependent post-gain (make-up gain) that attempts to restore the smoothed long-term level of each compressor band. |
| US09673767B2 |
MEMS microphone and method of operating the MEMS microphone
The present invention concerns a MEMS Microphone (1) comprising, a transducer element (2) for providing an electrical signal, a first part (3) for receiving the electrical signal from the transducer element (2) and for providing a processed signal, a second part (4) for receiving the processed signal from the first part (3) and for providing an output signal of the MEMS microphone (1), and a gain control unit (5) that is enabled to adjust a gain setting of the first part (3) and to adjust a gain setting of the second part (4). Further, another aspect of the present invention concerns a method of operating said MEMS microphone (1) comprising the step of adjusting a gain setting of the first part (3) and adjusting a gain setting of the second part (4). |
| US09673766B1 |
Class F amplifiers using resonant circuits in an output matching network
The embodiments described herein provide class F amplifiers and methods of operation. So implemented, the class F amplifiers can be used to provide high efficiency amplification for a variety of applications, including radio frequency (RF) applications. In general, the class F amplifiers are implemented with at least one transistor and an output matching network, where the output matching network includes a plurality of resonant circuits configured to facilitate class F amplifier operation. In addition to facilitating class F amplifier operation, the plurality of resonant circuits can also be implemented with other circuit elements to provide output impedance transformation in a way that facilitates efficient amplifier operation. |
| US09673765B2 |
Concurrent dual-band signal amplifier
A signal amplifier includes a band suppression filter configured to suppress a preset band among bands included in an input signal, a first common source-type amplifier connected between a supply terminal of a driving voltage and a ground terminal and configured to amplify a first input signal separated from an output signal of the band suppression filter in a common input node to provide a first amplified signal to a common output node, a second common source-type amplifier configured to amplify a second input signal separated from the output signal of the band suppression filter in the common input node to provide a second amplified signal to the common output node, and an output matcher configured to match levels of impedance between the common output node and an output terminal and to transfer a combined signal to the output terminal. |
| US09673762B2 |
Amplifier with adjustable ramp up/down gain for minimizing or eliminating pop noise
A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier. |
| US09673757B2 |
Modified tunneling field effect transistors and fabrication methods
Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided. |
| US09673755B1 |
Controlling a switched capacitor bank in a voltage controlled oscillator for wireless sensor devices
In some aspects, a wireless sensor device includes a voltage controlled oscillator. The voltage controlled oscillator includes a resonator circuit, a multiplexer and control logic. The resonator circuit includes a switched capacitor bank operable to tune the resonator circuit. The multiplexer is communicatively coupled to the switched capacitor bank to select combinations of capacitor bank elements based on input values representing digital capacitance levels. The multiplexer includes a first multi-bit input configured to receive a first set of values representing a first combination of the capacitor bank elements; a second multi-bit input configured to receive a second set of values representing a second combination of the capacitor bank elements; and a multi-bit output configured to communicate the first or second set of values to the switched capacitor bank. The control logic is configured to generate the first and second sets of values for each of the digital capacitance levels. |
| US09673753B1 |
Voltage-controlled oscillator with improved tuning curve linearization
In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear. |
| US09673752B2 |
Photovoltaic array skirt and mounting hardware
A photovoltaic array skirt assembly, where the array skirt has a double-groove structure which can accommodate both a splice and a photovoltaic module mounting device. The splice is mounted within the inner channel of the double-groove structure to connect adjacent array skirt sections, and can be locked into the double groove structure to prevent adjacent array skirt sections from uncoupling. One or more photovoltaic module mounting devices are also located in the groove structure, within the outer channel of the double-groove structure, each of which can be further secured in the array skirt with anti-rotation element. |
| US09673751B2 |
Rotating furling catenary solar concentrator
The present invention relates to a rotating solar concentrating device wherein reflective sheets hung in a catenary trough shape capable of solar concentration may be protectively furled and balanced and rotated about a vertical axis. The reflective sheets may be furled to protect them from damage from wind, rain, and dust. In some embodiments, rotating parts of the device may be hung from supports above. In some embodiments, a furling mechanism may initiate protective furling in response to damaging environmental factors. Some embodiments may concentrate light on a photovoltaic cell wherein the photovoltaic cell is cooled by immersion in a heat pipe. In some embodiments, reflective surfaces may be supported by cables that are tensioned by a hanging, rotating ballast. In some embodiments, the device may be employed in a ganged array. In some embodiments, the invention may harvest wind energy as a vertical axis wind turbine (VAWT). |
| US09673749B2 |
Power equipment and harmonic suppression method in power equipment
Provided is a power equipment which obtains a power saving effect according to the operation of an electric motor by providing a harmonic suppression function on the side of a power trunk line for supplying power to the electric motor without changing the electric motor side. The power equipment includes an electric motor (14) which is supplied with power from a power trunk line (12) connected to a power source transformer (11) to be operated. A harmonic generation unit (13) is provided in the power trunk line (12) and generates a harmonic voltage having a phase opposed to but the same degree as that of a harmonic voltage of a degree acting as a braking force on a rotor (14-2) in a rotational magnetic flux of harmonics generated between a stator (14-1) and the rotor when the electric motor (14) is operated. |
| US09673746B2 |
Motor driving circuit, motor device, and electric vehicle
A motor driving circuit has a supply line connected to a DC power source, an inverter whose input side is connected to the supply line and whose output side is connected to a motor, a power switch inserted in the supply line for switching the supply line between conducting and cut-off states, a voltage detector for detecting a voltage between the direct-current power source and the power switch, and an insulation resistance detector for first detecting, based on a result of detection by the voltage detector with the power switch in the cut-off state, an insulation resistance on the preceding-stage side of the power switch and subsequently detecting, based on a result of detection by the voltage detector with the power switch in the conducting state, an insulation resistance on the succeeding-stage side of the power switch. |
| US09673745B2 |
Servomotor control system including a buffer servomotor with a plurality of windings
A servomotor control system of the present invention includes: a multiple number of first servomotors for driving axes in a machine tool or others; a multiple number of converters for converting AC voltage into DC voltage; a multiple number of first inverters for converting DC voltage into AC voltage; second servomotors for rotating inertial bodies; a multiple number of second inverters for converting DC voltage into AC voltage; and a servomotor control unit for controlling the multiple first servomotors and the second servomotors, and is constructed such that the number of the second servomotors is less than that of the multiple second inverters, and at least one of the second servomotors includes a multiple number of independent windings, and at least part of the multiple second inverters are connected to the multiple independent windings provided for one of the second servomotors. |
| US09673744B2 |
Operating state circuit for inverter and method for setting operating states of an inverter
The invention relates to an operating state circuit for actuating an inverter (3), which supplies an n-phase electrical machine (5) with an n-phase supply voltage via phase connections (4a, 4b, 4c), wherein n≧1, comprising an evaluation device (6) which is connected to the phase connections (4a, 4b, 4c) of the inverter (3) and which is configured to detect output voltages of the inverter (3) to the phase connections (4a, 4b, 4c) and to determine a speed of the electrical machine (5) on the basis of the detected output voltages, and an actuating device (7) which is coupled to the evaluation device (6) and which is configured to switch to an idle state or an active short-circuit in dependence on the determined speed of the inverter (3). |
| US09673742B2 |
Controlling magnetic flux in an automotive electric machine
A method of compensating for magnetic flux resulting from variance from a first electric machine to a second electric machine. A magnetic flux change for the first machine is calculated as a function of a flux difference between the first machine and the second machine. Operation of the first machine is controlled using the magnetic flux change. |
| US09673739B2 |
Machine type identification
For identifying the machine type of an alternating current machine, a direct current is first applied to the stator for aligning the d-axis of the rotor and the magnetic field direction of the stator. Secondly, a direct current is applied to the stator at a current angle which causes the rotors of a permanent magnet machine and a synchronous reluctance machine to exert torque in different directions. The torque direction of the rotor is detected and the machine type is identified based on the torque direction information. The machine type is recognized as a permanent magnet machine or a synchronous reluctance machine depending on the torque direction. If no torque is detected, then the machine type is recognized as an induction machine. |
| US09673738B2 |
Multi-battery pack for power tools
A power tool including a motor, a first battery pack, a second battery pack, a first switching element coupled between the first battery pack and the motor, a second switching element coupled between the second battery pack and the motor, and controller coupled to the first switching element and the second switching element. The controller includes a first pulse-width modulation (PWM) output coupled to the first switching element and a first PWM signal to selectively close the first switching element. The controller further includes a second PWM output coupled to the second switching element and a second PWM signal to selectively close the second switching element. |
| US09673735B2 |
Power converter
A power converter includes first through sixth switching elements, first through tenth diodes, first through fourth capacitors, and a controller. The first through fourth capacitors are connected in parallel with the first through fourth switching elements, respectively. The seventh diode is connected in series with the first capacitor and is connected inversely in parallel with the first switching element. The eighth diode is connected in series with the second capacitor and is connected in parallel with the second switching element. The ninth diode is connected in series with the third capacitor and is connected inversely in parallel with the third switching element. The tenth diode is connected in series with the fourth capacitor and is connected in parallel with the fourth switching element. |
| US09673733B2 |
Control apparatus for photovoltaic inverter
There is provided a control apparatus for a photovoltaic inverter. The control apparatus includes a system voltage detector, a DC voltage detector that detects a DC voltage applied to the inverter, an output voltage deficiency detector that detects an output voltage deficiency of the inverter based on the system voltage and the DC voltage, an output-current detector, an output-current distortion detector that detects distortion of the output current based on a harmonic included in the output current, a MPPT controller, and an output-current distortion controller that performs control to set the DC voltage applied to the inverter to a voltage at a power point less than a maximum power point when the output voltage deficiency is detected and the distortion of the output current is detected. |
| US09673730B2 |
Double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and modulation method
Provided are a double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and a modulation method. The circuit includes a three-phase main inverter circuit and a three-phase double auxiliary resonant commutator circuit. An A-phase double auxiliary resonant commutator circuit, an A-phase main inverter circuit, a B-phase double auxiliary resonant commutator circuit, a B-phase main inverter circuit, a C-phase double auxiliary resonant commutator circuit and a C-phase main inverter circuit are connected in parallel in sequence and simultaneously connected with a DC power supply in parallel. The present invention can achieve the separation of the resonant current of the double auxiliary resonant commutator circuit from the load current at the moment of current commutation, thereby effectively reducing the current stress of the auxiliary switching tubes and the efficiency can be greatly increased particularly under light load condition. |
| US09673729B2 |
Power processing methods and apparatus for photovoltaic systems
High power output may be obtained from a photovoltaic (PV) system by controlling each photovoltaic cell of a solar array individually to operate at its maximum power point. Each cell may have associated power electronics and control circuitry that may be integrated together on a chip which may be advantageously implemented in CMOS, enabling reductions in cost and size. A perturb and observe algorithm may be used to find the maximum power point by measuring the power produced at different operating points, and modifying the operating point in the direction of increased power production. In one aspect, performance of a perturb and observe algorithm may be improved in the presence of noise. |
| US09673728B2 |
Converter arrangement with a capacitance
A converter arrangement can include a first rectifier having an AC input and a DC output with two DC output poles, a capacitance (C) connected between the DC output poles of the first rectifier, a second rectifier having an AC input with two AC input poles and a DC output with two DC output poles, wherein the DC output of the second rectifier is connected between the DC output poles of the first rectifier. A magnetic amplifier includes at least one control winding (L2) and at least one AC winding (L11, L12), wherein the at least one control winding is connected between the DC output poles of the first rectifier, and wherein the at least one AC winding (L2) of the magnetic amplifier is connected in series with the AC input of the second rectifier. |
| US09673727B2 |
Switching power supply control circuit and switching power supply
A jitter control circuit, which reduces conducted EMI noise by giving jitter (frequency diffusion) to the operating frequency for driving a switching element, determines an operating frequency fc (e.g., 40 kHz) at which reduction effects change from a feedback voltage that represents magnitude of a load. The jitter control circuit causes a, for example, 8-bit counter that generates a modulation frequency to operate with, for example, 8 bits when 40 kHz≦fc and 7 bits when fc<40 kHz. In this way, even when the range of the EMI noise measurement frequency is extended to the lower frequency side, for example, to 25 kHz, the maximum reduction effect is maintained in the entire frequency range. Thus, the maximum EMI noise reduction effect is obtained. |
| US09673725B2 |
Converter circuit with adjustable DC bus voltage
A method for controlling voltage of a DC bus in a converter circuit is provided. The method includes monitoring a duty cycle of a switch that connects a resistive circuit across the DC bus, the switch being closed when the DC bus voltage reaches an upper voltage value and opened when the DC bus voltage reaches a lower voltage value and altering the lower voltage value based upon the duty cycle of the switch. |
| US09673724B2 |
Matrix converter and method for generating an AC voltage in a second AC voltage grid from an AC voltage in a first AC voltage grid by means of a matrix converter
A matrix inverter is connected to a first and a second multi-phase A.C. voltage network. First inductive elements are connected to the first A.C. voltage network and second inductive elements are connected to the second A.C. voltage network. A switch matrix connects the ends of the first inductive elements, to the ends of the second inductive elements. The switch matrix has inverter units. A regulation arrangement is connected to control inputs of the inverter units. The matrix inverter has a first inverter unit, which is arranged between the ends of the first inductive circuit elements and earth potential. The matrix inverter has a second inverter unit, connected between the ends of the first inductive circuit elements and the ends of the second inductive circuit elements. The regulation arrangement insures that the electrical power flowing to the matrix inverter is equal to the electrical power flowing out of the matrix inverter. |
| US09673721B2 |
Switching synchronization for isolated electronics topologies
One or more first switches coupled to one of a primary transformer winding and a secondary transformer winding are controlled based on a first switch control reference clock signal. A reflected voltage across the other of the primary and secondary windings is sensed, and a second switch control reference clock signal is synchronized to the first switch control reference clock signal based on the reflected voltage. One or more second switches coupled to the other of the primary and secondary windings are controlled based on the second switch control reference clock signal. A digital isolator could instead be used to transfer a switch control reference signal across an isolation boundary. Switch control signals for controlling a set of switches on one side of the isolation boundary may be derived from a switch control reference signal that is synchronized with the transferred switch control reference clock signal. |
| US09673719B2 |
Dual Active Bridge with flyback mode
A dual active bridge (DAB) converter operates in a power conversion operation by controlling multiple bridge configured switches to charge a magnetization inductance from an input supply during a charge phase of a power cycle and to discharge the magnetization inductance into an output of the DAB during a discharge phase of the power cycle. The DAB converter includes an input converter connected to the input supply, an inductance connected to the input converter, a transformer comprising a primary and a secondary winding, and an output converter connected to the transformer. The input and output converters each include a first pair of switches forming a first circuit path, and a second pair of switches forming a second circuit path parallel to the first circuit path. The first and second circuit paths are both completed by a third circuit path including the inductance and the primary winding of the transformer. |
| US09673717B2 |
Electrical circuit for delivering power to consumer electronic devices
An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes an input terminal configured to receive an input power signal, an output terminal configured to provide an output power signal, and a plurality of voltage reduction circuit cells coupled between the input terminal and the output terminal. Each of the voltage reduction circuit cells includes a pair of flyback capacitors, a switching circuit, and a hold capacitor. The switching device is configured to operate the corresponding voltage reduction circuit cell at a charging phase and at a discharging phase. The plurality of voltage reduction circuit cells are configured to deliver the output power signal having a voltage level that is less than the voltage level of the input power signal. |
| US09673714B2 |
Power supply apparatus for an electrical appliance
A power supply apparatus includes a power supply circuit and a power-on circuit. The power-on circuit detects a remotely transmitted control signal and causes a transition of the power supply circuit to a turned on state. The power-on circuit includes a transducer configured to provide a power-on signal in response to the remote control signal. The transducer triggers transition to the turned on state through a switch driven by the power-on signal output from the transducer and arranged to supply a power supply circuit enable signal. A DC blocking capacitor is connected between an output of the transducer and a control terminal of the switch. |
| US09673707B2 |
Apparatus and methods for bypassing an inductor of a voltage converter
Apparatus and methods for bypassing an inductor of a voltage converter are provided. In one embodiment, a voltage converter includes an inductor and a bypass circuit that selectively bypasses the inductor based on a state of a bypass control signal. The inductor includes including a first end electrically connected to a first node and a second end electrically connected to a second node. The bypass circuit includes a first p-type field effect transistor and a second p-type field effect transistor electrically connected in series between the first node and the second node. The first p-type field effect transistor includes a body electrically connected to a first voltage, and the second p-type field effect transistor includes a body electrically connected to a second voltage greater than the first voltage. |
| US09673703B2 |
Bidirectional temperature communication between controller and converter for multiple phase buck converters
A converter arrangement, in particular a switched DC/DC converter arrangement, comprises a control die and a converter die. The control die comprises a control logic for generating a control signal and a control output for controlling the converter die by means of the control signal. The converter die comprises at least one converter that is designed for converting an input signal into an output signal in dependence on the control signal, wherein the control signal can be received at a control input. A single-line interface connects the control output to the control input. |
| US09673702B2 |
Negative current clocking
A switching mode power supply (SMPS) is capable of clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits. |
| US09673701B2 |
Slew rate enhancement for transient load step response
A power conversion circuit, such as a buck converter/regulator, includes a feedback loop operatively coupling the output voltage to the controller for the switching mechanism. The feedback loop includes an analog error amplifier that sources current to the controller when the output voltage falls below a predetermined reference voltage and sinks current from the controller when the output voltage rises above a predetermined reference voltage. The feedback loop further includes at least one of a sinking boost circuit that sinks additional current from the controller when the output voltage falls below a low voltage threshold or a sourcing boost circuit that sources additional current to the controller when the output voltage rises above a high voltage threshold. The boost circuits can include analog amplifiers, digital comparators, or a combination thereof. |
| US09673696B2 |
Ultra low-voltage circuit and method for nanopower boost regulator
At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry. |
| US09673694B2 |
Electromagnetic induction type power supply device
Disclosed is an electromagnetic induction type power supply device, which generates electric power through an electromagnetic induction method using a transformer from current flowing through a transmission line, can adjust an output thereof by detecting and feeding back the output, enables a transformer and a power converting unit to be added or removed as necessary. The electromagnetic induction type power supply device includes a transformer module including a plurality of transformers for outputting electric power by inducing, in an electromagnetic induction method, secondary current from primary current flowing through a transmission line; a power source module including a plurality of power converting units for converting the electric power output from the plurality of transformers to direct current power and outputting the converted power; and a power summing unit for summing the direct current power output from the plurality of transformers and providing the summed power to a load. |
| US09673690B2 |
Electromagnetic retarder rotor for a vehicle, retarder comprising such a rotor, and vehicle provided with such a retarder
An electromagnetic retarder rotor (1) for a vehicle, includes: an armature (2) having an inner surface (4); an end (5) having an inner surface that faces the inner surface (4) of the armature (2) and is at a distance therefrom, the end (5) being secured to the armature (2); a ring (13) for coaxial attachment to the armature (2); and an arm (15) defined between an upper edge and a lower edge and having a first end portion secured to the inner surface (7) of the end (5), on the lower edge, and a second end portion secured to the attachment ring (13), the upper edge of the arm (15) being at a distance from the inner surface of the armature (2) over the entire radial dimension of the arm (15). |
| US09673689B2 |
Rotating electric machine and power transmission device including rotors and electric power unit
Provided is a compound motor (14) comprising a magnet rotor (19) supported by bearings (B3, B4) in a rotatable manner, a winding rotor (20) supported by bearings (B5, B6) in a rotatable manner relative to the magnet rotor (19) at the inner side of the magnet rotor (19) and having rotor winding units (20b), and slip ring mechanisms (25). A space is formed in the inner circumference of the winding rotor (20). At least a part of the slip ring mechanisms (25) is arranged in the space of the inner circumference of the winding rotor (20). The bearings (B3 to B6) include bearings (B3, B6), the internal diameter of each is larger than the size of slip ring mechanisms (25) with respect to the radial direction. The bearings (B3, B6) are arranged outside the slip ring mechanisms (25) with respect to the radial direction. |
| US09673680B2 |
Electromechanical flywheels
An electromechanical flywheel machine includes a flywheel mass and a motor-generator having a rotor rotatable about a stationery inner stator having stator windings. |
| US09673679B2 |
Driving device
A driving device is provided with a gear unit and a plurality of motors. The gear unit includes a plurality of input shafts supported by a supporting member, and a driven member to which the plurality of input shafts is engaged. Each motor rotor is respectively attached to a corresponding one of the input shafts. Each motor stator is attached to a housing that is detachably attached to the supporting member. When the housing is attached to the supporting member, phase angles of the rotors of all of the motors are equal. |
| US09673675B2 |
Stator of an axial flow electric machine and the process for making it
Described is a stator for an axial flow electric machine comprising a toroidal core (2) made from ferromagnetic material and a plurality of windings (3) and teeth (4) angularly distributed on the core (2) in an alternating configuration. The teeth have, on at least one relative lateral surface, a shaped profile defining at least one gripping surface (12) such as to act in conjunction with a matrix of resin designed to stably press the teeth (4) on the core (2). |
| US09673673B2 |
Motor air flow cooling
In one possible embodiment, an aircraft electric motor cooling system is provided having an airflow path through a spinner which includes a first airflow path between an inner rotor and a stator, a second airflow path between an outer rotor the stator and a third airflow path along an outer surface of the outer rotor. |
| US09673672B2 |
Individual-segment rotor having retaining rings
The aim is to propose an individual-segment rotor that is simple to construct and suitable for series production. Therefore, an individual-segment rotor having a plurality of laminated core segments (2) arranged in a star shape and a permanent magnet (1) between each pair of adjacent laminated core segments (2) is provided, whereby the laminated core segments and the permanent magnets are arranged in a hollow cylindrical assembly. The laminated core segments each have a plurality of individual sheets, which are rigidly connected to one another. The hollow cylindrical assembly has a groove on each of two outer edges, into which groove a ring (11) is inserted in order to fasten the assembly. |
| US09673668B2 |
Compression band shim pack for stator core, related stator and generator
A shim pack to reduce vibration of a stator core is disclosed. The stator core may include a plurality of laminates coupled to a dovetail of a keybar and separated by a space block. The shim pack may include an elongated body extending from a first end including a dovetail slot configured to couple to the dovetail of the keybar to a second end extending radially at least substantially an entire length of an adjacent space block. A stator and related generator including the shim pack may also be provided. |
| US09673662B2 |
Battery disconnect safeguard
In embodiments, a mobile device includes a primary battery as a power source to power components of the mobile device, and includes a secondary battery as an additional power source to power the components of the mobile device. A sensor is implemented to detect an acceleration of the device that indicates an impending secondary battery disconnect event due to the mobile device falling. A battery controller is implemented to receive a sensor input of the detected acceleration from the sensor. The battery controller can then switch from the secondary battery to the primary battery as the power source based on the detected acceleration of the mobile device. The battery controller can switch back from the primary battery to the secondary battery as the power source based on the acceleration of the mobile device no longer being detected. |
| US09673655B2 |
Apparatus and methods of charging to safe cell voltage
This document discusses, among other things, a charge regulator configured to optimize charging of an energy storage device by measuring an internal voltage drop of the energy storage device using an open circuit voltage (OCV) across the terminals of the energy storage device during charging and a voltage across the terminals of the energy storage device during charging (CCV). |
| US09673652B2 |
Fast charging high energy storage capacitor system jump starter
A fast charging high energy storage capacitor system jump starter is described. The jump starter apparatus incorporates a method of using reserve energy from a depleted electrical system such as an automobile battery, combined with a fast charging high energy capacitor bank to enable the rapid and effective way to jump start a vehicle. |
| US09673648B2 |
Lithium-based battery pack for a hand held power tool
A method for conducting an operation including a power tool battery pack. The battery pack can include a housing, a first cell supported by the housing and having a voltage, and a second cell supported by the housing and having a voltage. The battery pack also can be connectable to a power tool and be operable to supply power to operate the power tool. The method can include discharging one of the first cell and the second cell until the voltage of the one of the first cell and the second cell is substantially equal to the voltage of the other of the first cell and the second cell. |
| US09673647B2 |
Charging apparatus for mobile device
A charging apparatus for a mobile device is provided. The apparatus includes a terminal casing and a charging mount. A pattern electrode part has concentric electrode patterns. A first magnet is provided underneath the pattern electrode part, and a second magnet having multiple magnet elements is disposed around the pattern electrode part. The charging mount has a pin terminal part which comes into contact with the pattern electrode part. A third magnet being magnetically coupled with the first magnet is provided underneath the pin terminal part. A fourth magnet being magnetically coupled with the second magnet is provided around the pin terminal part. |
| US09673644B2 |
Battery module having overcharge preventing device, and overcharge preventing device for battery module
The present invention relates to a battery module mounted with an overcharge preventing device, and an overcharge preventing device for a battery module. The battery module mounted with an overcharge preventing device of the present invention includes: a battery cell including a first battery cell and a second battery cell, which are spaced apart from each other; and an overcharge preventing device inserted and disposed between the first battery cell and the second battery cell, and configured to block power supplied to the battery cell when the battery cell is expanded according to overcharge, in which the overcharge preventing device is configured as one module separately from the battery cell, and is replaceably disposed between the first battery cell and the second battery cell, which are spaced apart from each other. |
| US09673637B2 |
Ultra-capacitor based energy storage in a battery form factor
An ultra-capacitor based energy source may replace rechargeable and conventional batteries. It may have the form factor of a conventional battery and may emulate the discharge characteristics of the replaced battery. |
| US09673636B2 |
Power reception control device and power reception control method for non-contact power transmission
A power reception control device provided in a power reception device of a non-contact power transmission system includes a power-reception-side control circuit that controls an operation of the power reception device, and a power supply control signal output terminal that supplies a power supply control signal to a charge control device, the power supply control signal controlling power supply to a battery. The power-reception-side control circuit controls a timing at which the power supply control signal (ICUTX) is output from the power supply control signal output terminal. The operation of the charge control device is compulsorily controlled using the power supply control signal (ICUTX). |
| US09673635B2 |
Self sustaining energy harvesting system
Systems (100) and methods (400) for powering an electrical load (322) in an environment. The methods involve using a battery (310) to simultaneously supply electrical energy to control electronics (308, 316) and a Super Capacitor (“SC”) storage element (314) immediately after a system has been disposed in the environment and turned on. In effect, the control electronics are caused to perform intended functions thereof nearly instantaneously after turning on the system. The SC storage element is charged from a first charge state in which approximately zero volts exist across terminals thereof to a second charge state in which greater than zero volts exists across the terminals. The SC storage element is then used to supply electrical energy to the electrical load of the system so as to cause the electrical load to perform intended functions thereof. |
| US09673624B2 |
Power supply device and power supply switching method
A power supply device (10) includes a plurality of constant current output circuits (14) that can supply power to a load (12). The constant current output circuit (14) includes a pulse generation unit (20) that generates a pulse voltage, and a communication unit (34) that transmits and receives drive information, between the constant current output circuit (14) and the other constant current output circuit (14). When an abnormality occurs in the constant current output circuit (14) supplying power to the load (12) and the constant current output circuit (14) supplying power to the load (12) is switched to the other constant current output circuit (14), the other constant current output circuit (14) drives the pulse generation unit (20) by using the drive information that has been received through the communication unit (34) from the power supply means having supplied power to the load. |
| US09673623B2 |
Sequentially operated modules
Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power. The system may use remote powering wherein few or all of the modules are powered from the same power source connected to the system in a single point. The power may be carried over dedicated wires or concurrently with the conductors carrying the activation signal. The payload may be a visual or an audible signaling device, and can be integrated within a module or external to it. The payload may be powered by a module or using a dedicated power source, and can involve randomness associated with its activation such as the delay, payload control or payload activation. |
| US09673619B2 |
Excess voltage protection apparatus and diagnostic method for multi-stage excess voltage protection apparatuses
The invention relates to a diagnostic method for multiple-stage excess voltage protection apparatuses that include at least one gas discharge distance between an input and a reference potential as a first stage, at least one diode path between an output and the reference potential as a second stage, and at least one decoupling inductance interposed between the input and the output. The diagnostic method is characterized in that a secondary voltage applied to a secondary inductance, which is actively connected, inductively, to the decoupling inductance, is measured and evaluated with a view to excess voltage events in the excess voltage protection apparatus. The invention also relates to a two-stage excess voltage protection apparatus. |
| US09673617B2 |
Pre-charge circuit for an electromechanical relay
A pre-charge circuit is provided for an electromechanical relay having a coil and relay contacts. The pre-charge circuit includes a semiconductor switch configured to be electrically connected across the relay contacts of the electromechanical relay. The pre-charge circuit includes a resistor configured to be electrically connected in series with the semiconductor switch between the coil and the relay contacts of the electromechanical relay. The pre-charge circuit includes a driver configured to be electrically connected between the coil of the electromechanical relay and the semiconductor switch such that the driver is configured to power operation of the semiconductor switch. The semiconductor switch is configured to pre-charge a capacitor of a load of the electromechanical relay with electrical current through the resistor for limiting in-rush electrical current supplied to the relay contacts of the electromechanical relay. |
| US09673615B2 |
Isolator circuit
An isolator circuit (25) for a unit of a safety system (10) includes a power control line (14) connectable to a first loop of a safety system and a power connection (16) connectable to a second loop of the safety system. A switch (26) is connected to the power control line (14), and the switch has a closed configuration and an open configuration. A controller (28) controls the configuration of the switch (26). If a voltage across the circuit (10) from the power connection (16) to the power control line (14) falls below a predetermined level, the controller (28) opens the switch (26), thereby causing a disconnection to occur in the first loop. |
| US09673613B2 |
Surge protection device
A surge protection device detects whether a surge voltage occurs at a power input port by using a first Zener diode and a second Zener diode. When the power input port receives a normal voltage, the surge protection device turns on a first transistor to transmit the normal voltage to a load. Otherwise, when the power input port receives the surge voltage, the surge protection device prohibits the first transistor from conducting so as to protect the load from being damaged by the surge voltage. The surge protection device protects the load by controlling conducting or not of the first transistor and is manufactured without a surge protection unit. Therefore, manufacturing cost of the surge protection can be decreased. |
| US09673608B2 |
Disconnection indicator of an active component of a device for protecting an electrical installation
A device for protecting an electrical installation including an insulating body electrically defining an internal housing, the protective device including, within the internal housing: an active component of a device for protecting an electrical installation; a disconnection system for disconnecting the active component moveable between a contact position corresponding to a connected state of the active component and an open position corresponding to a disconnected state of the active component; a disconnection indicator, where the disconnection indicator is secured in movement to the disconnection system and the disconnection indicator and the insulating body are arranged to have a first configuration, which corresponds to the contact position, and a second configuration, which corresponds to the open position, the relative positioning of the disconnection indicator with respect to the insulating body in the first configuration being visually distinct from the outside of the insulating body from the relative positioning of the disconnection indicator with respect to the insulating body in the second configuration. |
| US09673606B2 |
Pressurized electromechanical cable
An inventive pressurized cable is provided that simultaneously provides electrical connections and a supply of air, gas, or vacuum to an electromechanical device utilizing an existing connection on the device. The use of an existing cable connection for the supply of air or gas to provide positive pressure or a vacuum condition to an electromechanical enclosure allows for the use of standard electromechanical components without alteration and potential voiding of existing warranties. The present invention finds particular utility in the field of industrial automation where motors are subjected to coolant liquids and other types of contaminants that tend to infiltrate the motor seals, especially when the motor is shut down which causes a negative pressure inside the motor case that draws moisture in. Reactive gasses may be introduced with the inventive positive pressure cable that act to neutralize or condition harmful pollutants generated by the motor such as ozone. |
| US09673605B2 |
Boot seal
The boot seal may include an elastomeric body constrictively stretched over an end of a cable and a retainer to grip the cable. The retainer may be a body having a central opening to receive the cable and have a plurality of inclined tines extending radially inwardly from the body with the inclined tines having distal ends forming the central opening. The elastomeric body may have a first sleeve on an end of the boot seal for receiving the end of the cable. |
| US09673603B2 |
Divided conduit
A divided conduit containing a thermoplastic conduit and at least one strip-shaped film having a first longitudinal edge and a second longitudinal edge which are embedded into the inner surface of the conduit forming at least two flexible, longitudinal channels for enveloping cables or other elongated structures. |
| US09673600B2 |
Grommet
A grommet (10) is mounted on a burred part (54) formed on an inner periphery of a through hole (52) formed on a panel (50). The grommet (10) includes a small-diameter tubular portion (12), a large-diameter tubular portion (20) and a coupling (16) connecting the small-diameter tubular portion (12) and the large-diameter tubular portion (20). The small-diameter tubular portion (12) is held in close contact with an outer peripheral surface of the wire (60), and the a large-diameter tubular portion (20) is fit on an outer peripheral side of the burred part (54) of the panel (50). A rib (40) projects from an inner peripheral surface of the coupling (16) and covers at least a part of an inner peripheral surface side of the burred part (54) of the panel (50). |
| US09673597B2 |
Wall clamping junction box
An enclosure such as an electrical junction box has fixed clamping flanges exterior to the enclosure, screws rotatable relative to the enclosure and operative for drawing clamping brackets from an initial elevated position towards the clamping flanges for clamping the edges of an opening cut in drywall or the like, thereby to fasten the enclosure inside a wall or ceiling. The clamping brackets are initially retracted in the enclosure and rotation of the screws releases the brackets to an extended clamping position relative to the clamping flanges. |
| US09673596B2 |
Back box with mounting posts projecting from recessed portions in sidewalls
A weatherproof back box for receiving a fire alarm notification or other fire alarm device includes a back wall and sidewalls that project from the back wall and define a mouth. The sidewalls further include recessed portions that extend from the back wall toward the mouth, and end prior to the mouth. The back box further includes mounting posts, which are preferably less than 50% of the depth of the back box, that project from the recessed portions into the mouth. Additionally, these mounting posts receive fasteners for securing the fire alarm notification device in the mouth of the back box. |
| US09673593B2 |
Spark plug having firing pad
A spark plug has a firing pad attached to a center electrode or to a ground electrode. The firing pad is attached via laser welding and has a sparking surface with an overall fused area and an unfused area. In one or more embodiments, the overall fused area is located in part or more inboard of a peripheral edge of the firing pad. |
| US09673592B2 |
X-ray tube
An x-ray tube includes a vacuum housing. A cathode and an anode are disposed in the vacuum housing and insulated by at least one insulation element. Upon application of a high voltage, the cathode emits electrons that strike the anode as an electron beam. A voltage arrester device with an insulation path has a field strength that is higher than a field strength at the insulation element. If a voltage flashover occurs, the voltage is discharged via the voltage arrester device. |
| US09673590B2 |
Semiconductor stripe laser
A semiconductor stripe laser has a first semiconductor region having a first conductivity type and a second semiconductor region having a different, second conductivity type. An active zone for generating laser radiation is located between the semiconductor regions. A stripe waveguide is formed in the second semiconductor region and is arranged to guide waves in a one-dimensional manner and is arranged for a current density of at least 0.5 kA/cm2. A second electrical contact is located on the second semiconductor region and on an electrical contact structure for external electrical contacting. An electrical passivation layer is provided in certain places on the stripe waveguide. A thermal insulation apparatus is located between the second electrical contact and the active zone and/or on the stripe waveguide. |
| US09673586B2 |
Method of waterproofing coated electric wire attached connector terminal
A method of waterproofing a coated electric wire attached connector terminal which is formed of metal material and which includes a barrel part which is crimped to a conductor which is exposed from a sheath, a terminal part, a connecting plate which is formed between the barrel part and the terminal part, and connects the barrel part and the terminal part. The method includes an adhesive material applying step in which adhesive material is applied to the connecting plate, and a molded part molding step in which the coated electric wire attached connector terminal is placed in a metal mold to form an injection space around the connecting plate, the barrel part and the sheath and resin is injected into the injection space to cover the connecting plate, the barrel part and the sheath with a resin molded part. |
| US09673583B2 |
Photovoltaic mounting rail connector with drop-down connection to first photovoltaic module and slide-in connection to second photovoltaic module
A connector for attaching first and second photovoltaic modules to a mounting rail, with a lower body portion that rotates to lock into a mounting rail groove and an upper body portion with a hook that is lowered towards the lower body portion to grasp onto the first photovoltaic module and a key that receives the second photovoltaic module slidably-connected thereon. |
| US09673581B1 |
Electrical connector
An electrical connector comprising an insulating housing, a USB Type-C connector arranged in the insulating housing, a circuit board and a plurality of transferring terminals is disclosed. One side of the circuit board is connected with twenty-four connection terminals of the USB Type-C connector, other side of the circuit board is connected with the plurality of transferring terminals which are corresponding to USB Type-A standard. The circuit board is arranged with a connecting line, which is used to integrate signal transmitted through the twenty-four connection terminals of the USB Type-C connector into USB Type-A standard adopted outputting signal, and outputs the outputting signal through the plurality of transferring terminals. |
| US09673579B2 |
Portable USB charging hand controller with twist-on cover
The present invention discloses a portable remote controller, which comprises a remote controller body and a cover covering the remote controller body; hooks are arranged on the back of the cover, and slots to fit the hooks are arranged at corresponding positions in an upper rim of the remoter body; press buttons are arranged in a front of the cover. The portable remote controller with added USB charging function can not only fulfill the regular remoter control functions for intelligent living, but its USB interface is also able to charge almost all intelligent devices in the market, including almost all intelligent phones and tablets; thus when people are using intelligent devices in daily life, they will no longer worry about low batteries; also the cover is easy to remove and install, convenient to users. |
| US09673577B2 |
Power plug device and the manufacturing method thereof
This invention provides a power plug device and the manufacturing method thereof, the power plug device comprises a power-connected base; a cover is configured to the power-connected base, wherein the cover can cover the internal components of the power-connected base, such as at least one plug and a printed circuit board, a gap between the cover and a lid is filled with an insulating compound for preventing liquid ingress, and then the power plug device is sealed by using an ultrasonic welding. |
| US09673575B1 |
Electrically conductive wall hooks
The invention is an electrically conductive wall hook. The invention is a means to provide power to an object that is being stored in a hanging position. The invention is made up of two parts. The first part is a housing attached to an object to be stored that contains an opening. The second part is a hook attached to a wall. Both the housing and the hook contain electrical conductors. When the hook is fitted securely inside the opening of the housing, the object is suspended from the hook, and the electrical conductors within the housing and the hook mate with each other. The electrical conductor inside the hook is attached to electrical power so that electrical power is provided to the object that is suspended from the hook. |
| US09673574B2 |
Connector terminal, electric connector, and method of fabricating the connector terminal
A connector terminal includes a press-fit terminal and a shaft portion, the connector terminal being fabricated of a single metal sheet, the shaft portion having a lateral cross section having a size entirely covering therewith a lateral cross section of the press-fit terminal when viewed in an axial direction of the connector terminal, the shaft portion having surfaces extending in the axial direction at an entire circumference thereof, the lateral cross section of the shaft portion being identical in shape with a lateral cross section of a terminal space of a die used for fabricating a housing for the press-fit terminal, the press-fit terminal being fit into the terminal space when the housing is molded with resin. |
| US09673571B2 |
Shield unit
A shield unit includes: a braid having a contact portion arranged in contact with a cylinder of a shield shell; a holder inserted in the cylinder and attached to the cylinder in contact with the contact portion, the holder attached to the cylinder electrically connecting the shield shell to the braid; and a rotation unit provided between the cylinder and the holder, the rotation unit being configured to make the holder rotate in a circumferential direction of the cylinder and make the cylinder and the contact portion slide relatively to each other until completion of attaching the holder to the cylinder. |
| US09673568B2 |
Plug connector
A plug connector including a connecting member, a cable, and a shield case. The cable includes a signal transmission part connected to the connecting member. The shield case includes first and second shells and a first retainer. The first and second shells are combined together in a first direction so as to form a tube at least partially covering the connecting member and the signal transmission part. The first shell has an end face on one side of a second direction. The second direction is orthogonal to the first direction. The first retainer is a tube or half tube for retaining the cable. The first retainer is provided on the second shell so as to be located on the one side of the second direction relative to the end face of the first shell and in contact with at least a part of the end face of the first shell. |
| US09673567B1 |
Apparatus, system, and method for preventing electric shock during maintenance of telecommunication systems
The disclosed apparatus may include a lock that has a locking mechanism that secures an electronic module to a telecommunication system. The lock may also have an ejection handle coupled to the locking mechanism such that application of physical force to the ejection handle ejects the electronic module from the telecommunication system by undoing the locking mechanism. The disclosed apparatus may also include a cross-bar coupled to the lock and movable in conjunction with the ejection handle. The cross-bar may facilitate access to a row of power connectors arranged along a surface of the electronic module when the ejection handle is positioned in a first position. Additionally or alternatively, the cross-bar may block access to the row of power connectors arranged along the surface of the electronic module when the ejection handle is positioned in a second position. Various other apparatuses, systems, and methods are also disclosed. |
| US09673566B2 |
Electronic device
An electronic device including a first body, a first connecting assembly, a second body, and a second connecting assembly is provided. The first body has a recess, and the first connecting assembly is disposed at the first body and hidden in the recess. The second connecting assembly is disposed on the second body in protruding manner. The second connecting assembly is fit to be assembled in the recess and electrically connected to the first connecting assembly, such that the first and the second bodies are detachably assembled to each other. |
| US09673563B2 |
Connector
A connector (10A) is provided with a housing (20) including a tube (22) and a seal (80) to be fit in the tube (22) in a liquid-tight manner. A holder (60) has a peripheral wall (62) fit externally on the tube (22) and a rear wall (61) configured to prevent the seal (80) from coming out backward. A wire cover (50) is mounted on the housing (20) by being fit externally on the peripheral wall (62) when the wire cover (50) is arranged to cover wires (100) pulled out from the holder (60) and the peripheral wall (62) is disposed in a proper posture on the tube (22). However, the wire cover (50) interferes with the holder (60) and cannot be mounted on the housing (20) when the peripheral wall (62) is in an improper posture inclined with respect to the tube (22). |
| US09673558B2 |
Systems and methods for maintaining pressure on an elastomeric seal
Systems and methods for maintaining a desired compressive force on seals in an electrical junction such as a pothead connector for an ESP motor. In one embodiment, insulated conductors of a power cable extend into a housing of a connector. The insulated conductors pass through an upper insulator, a set of elastomeric boot seals, and a lower insulator. O-rings are positioned between the upper insulator and the housing of the pothead connector. The lower insulator is secured to the upper insulator by a set of bolts and springs that urge the lower insulator toward the upper insulator, compressing the boot seals. The bolts are threaded into the upper insulator and are tightened to compress the springs against the lower insulator. The compression of the boot seals between the insulators maintains a desired range of contact pressure against the seals despite changes in the seal dimensions. |
| US09673556B2 |
Perpendicular plug connector
A perpendicular plug connector has an insulative housing, multiple first conductive terminals, multiple second conductive terminals, a base, a reinforcing fastening element and a shell. The first conductive terminals and the base are mounted on the insulative housing. The reinforcing fastening element is mounted on and tightly abutting the base. The shell accommodates the insulative housing and the first conductive terminals. The reinforcing fastening element allows fasteners such as bolts and rivets to extend through and fasten the perpendicular plug connector securely on a circuit board and enhances structural strength of the base. |
| US09673553B1 |
Terminal position assurance locking mechanism and method for operating thereof
A locking mechanism for a terminal position assurance (TPA) device is placed in-line with the TPA itself. The locking mechanism includes a pre-locking head and a final locking head. The final locking head is shorter than and face in an opposite direction from the pre-locking head. The orientation and geometry of the locking mechanism ensures a secure engagement of the TPA with the electrical connector assembly. Further, according to at least one embodiment, at least two pre-lock mechanisms and only a single final-lock mechanism may be provided for the locking mechanism to ensure a secure engagement of the TPA with the connector assembly without a false-positive engagement. |
| US09673552B2 |
Electrical receptacle connector
An electrical receptacle connector includes a metallic shell, an insulated housing, a plurality of first receptacle terminals, and a plurality of second receptacle terminals. The insulated housing is received in the receiving cavity. The insulated housing includes a tongue portion and a plurality of first through holes formed on the tongue portion. The first receptacle terminals are held in the tongue portion. The second receptacle terminals are held in the tongue portion. The second receptacle terminals include a plurality of cut portions corresponding to the first through holes. |
| US09673550B2 |
Electrical connecting module
The invention relates to an electrical connecting module comprising: a module housing (101), which comprises a module receptacle (103, 119, 1209) with a first electrical connection terminal (105, 107); a module element (109, 1205) with a second electrical connection terminal (111, 113) and with a third electrical connection terminal (115, 117), wherein the module element (109, 1205) for electrically connecting the first connection terminal (105, 107) to the second connection terminal (111, 113) can be inserted (into the module receptacle (103, 119, 1209) and can be held in the module receptacle (103, 119, 1209) by means of a detachable latching connection; and a release device (125) for releasing the latching connection. |
| US09673547B2 |
Plated terminal for connector and terminal pair
The present invention aims to provide a plated terminal for connector which requires a smaller insertion force by reducing a friction coefficient and a terminal pair formed using such a plated terminal for connector. An alloy containing layer (1) made of tin and palladium and containing a tin-palladium alloy is formed on a surface of a terminal base material (2) made of copper or copper alloy. Here, the alloy containing layer (1) is preferably such that domain structures of a first metal phase (11) made of an alloy of tin and palladium are formed in a second metal phase (12) made of pure tin or an alloy having a higher ratio of tin to palladium than in the first metal phase (11). |
| US09673544B1 |
Short type metal female terminal and an LED light using the same
A short type metal female terminal includes a base on which weld legs are disposed to provide an electrical connection with a light board. The base has an entrance through which a male terminal can pass. Two main elastic plates are respectively disposed at a left side and a right side of the base. The main elastic plates bend downwards and inwards, then extend oppositely to a place below the entrance, and then bend upwards to pass through the entrance. Thus, contact points of the main elastic plates opposite to each other are formed and located above the entrance. The male terminal passes between said contact points to carry out the electrical connection. The above structure is simple, and the electrical connection is more reliable. |
| US09673543B2 |
Distribution block and din rail release mechanism
An electrical distribution block transfer electrical power from a primary conductor to one or more tap conductors. The distribution block includes a base, a conductor block, first and second sidewalls, and a lid. The conductor block and the first and second sidewalls are connected to the base and the lid is connected to the first and second sidewalls. The conductor block includes one or more apertures for receiving more primary conductors and one or more apertures for receiving tap conductors. |
| US09673542B1 |
Poke-in electrical connector having a contact with a base extending through an opening in a bottom of a housing
A poke-in electrical connector includes a housing having a cavity and a poke-in wire channel open to the cavity. The wire channel receives an electrical wire during a poke-in termination. The housing has a bottom with an opening. A poke-in electrical contact is received in the cavity and held by the housing. The poke-in electrical contact includes a base and an arm extending from the base. The base extends through the opening at the bottom for surface mounting to a circuit board. The base has a generally planar solder pad exposed at the bottom for soldering to the circuit board. The arm has a poke-in beam engaging the electrical wire when poked-in to the corresponding wire channel. The arm is movable to a clearance position to release the poke-in beam from the electrical wire to allow the electrical wire to be removed from the wire channel. |
| US09673539B2 |
Spring biased contact pin assembly
A spring biased contact pin assembly includes a barrel member having a barrel wall defining an elongate internal cavity with a lower end and an upper end. The assembly also includes a lower plunger member reciprocally mounted in the internal cavity proximate the lower end of the internal cavity. A spring member is positioned in the internal cavity between the lower plunger member and the upper end of the internal cavity. A high electrical resistance spacer member is positioned in the internal cavity in contact with the lower plunger member and the spring member. Spring force exerted through the spacer member urges the lower plunger member into electrical contact with the barrel wall. A method of transmitting electricity through an electrical contact assembly includes urging a plunger member against the wall of a barrel member in which it is reciprocally mounted with a high electrical resistance member. |
| US09673531B2 |
Antenna
An antenna is disclosed. The antenna includes a coupling portion, a ground connection portion corresponding to the coupling portion, and a radiation body. The a radiation body further includes a first antenna portion extending from a first end of the coupling portion in a direction, a second antenna portion extending from the first end in a direction opposite to that of the first antenna portion, and a third antenna portion extending from an end of the ground connection portion in a direction surrounding the first antenna portion, wherein two gaps are provided for separating the third antenna portion from the first antenna portion and the second antenna portion respectively. |
| US09673527B2 |
Folded patch antenna platform
Various systems and methods are provided for folded patch antennas. In one embodiment, among others, a folded patch antenna includes a patch disposed on an outer side of a flexible substrate and a ground plane disposed on an inner side of the flexible substrate opposite the patch. The flexible substrate is folded to form an enclosed cavity defined by the inner side of the flexible substrate. The ground plane may provide electromagnetic interference (EMI) shielding of the cavity. In another embodiment, among others, a folded patch antenna platform includes a flexible substrate, a folded patch antenna, and a transceiver mounted on the flexible substrate. The folded patch antenna includes a patch communicatively coupled to the transceiver and a ground plane, which are disposed on opposite sides of the flexible substrate. |
| US09673526B1 |
Dual-frequency stacked patch antenna
The invention is directed to a dual-frequency stacked patch antenna. In one embodiment, the antenna comprises a pair of electrically conductive, nested, tub-like structures and a feed surface. The edges of the tub-like structures and the feed surface define a surface that is adapted to be conformal to an application surface that defines a cavity in which the antenna is positioned. The edges of the tub-like structures and the edge of the feed surface define a pair of slots for receiving and/or transmitting two signals with different center frequencies. Located and extending throughout each of the slots is a slot modification structure comprised of inter-digitated fingers that provide capacitive loading and enhance the low observability of the antenna. |
| US09673519B2 |
Ground planes for reducing multipath reception by antennas
An antenna system for a global navigation satellite system reference base station is disclosed. The antenna system includes an antenna positioned above a high capacitive impedance surface (HCIS) ground plane. Over a specific range of the lateral dimension of the HCIS ground plane and the height of the antenna above the HCIS ground plane, a high level of multipath suppression and high sensitivity for low-elevated satellites can be simultaneously maintained. The HCIS ground plane can be fabricated as a flat conducting plate with an array of conducting elements such as pins, pins with expanded tips, or mushroom structures. Alternatively, the HCIS can be fabricated as a flat conducting plate with a concentric series of choke rings. The antenna system can provide a positioning accuracy of +/−1 mm, an order of magnitude improvement over previous designs. |
| US09673514B2 |
Dimensionally tolerant multiband conformal antenna arrays
Some embodiments relate to a multiband antenna array formed on a flexible substrate. Low frequency antenna elements may be formed using nanoink. High frequency elements may be provided on a prefabricated antenna chip. The antenna array may be heated in a low temperature oven to sinter the nanoink into a solid antenna element. In some embodiments, an adhesive insulation layer may be provided which allows the antenna array to be attached to any surface. In other embodiments, the antenna array may be embedded in a composite material. |
| US09673513B2 |
Radiator frame having antenna pattern embedded therein and electronic device including the same
A radiator frame includes: a main radiator including an antenna pattern part configured to transmit or receive a signal, an internal terminal part provided on one end of the antenna pattern part and configured to electrically connect the antenna pattern part and a circuit substrate, and an external terminal part provided on another end of the antenna pattern part and configured to be connected to an auxiliary radiator to improve radiation performance of the antenna pattern part; and a molded frame molded around the radiator, the molded frame allowing the internal terminal part to be exposed at a first surface of the molded frame, and allowing the external terminal part to be exposed at a second surface of the molded frame. |
| US09673508B2 |
Antenna device and electronic device having the same
An electronic device is provided. The electronic device includes a first antenna radiator operating in at least one frequency band, and at least one second antenna radiator disposed proximate to the first antenna radiator coupled to at least one radiation pattern of the first antenna radiator, and to operate as a parasitic resonator. |
| US09673506B2 |
Antenna device and manufacturing method thereof
Disclosed herein is an antenna device that includes an antenna coil having a planar coil pattern, a magnetic sheet that covers one main surface of the antenna coil, and a resin layer provided on the other main surface of the antenna coil and along the coil pattern. The resin layer is substantially the same planar shape as the planar coil pattern. |
| US09673503B1 |
Systems and methods for combining or dividing microwave power
A power combiner/divider includes a main conductor defining an axis; an input connector having a center conductor, adapted to be coupled to a signal source, electrically coupled to the main conductor and having an axis aligned with the main conductor axis, and having a second conductor electrically coupled to a ground conductor; a plurality of satellite conductors radially exterior of and spaced apart from the main conductor, the satellite conductors defining the general shape of a slotted hollow cylinder having a cylinder axis aligned with the main conductor axis; a plurality of output connectors having respective axes that are perpendicular to the main conductor axis, the output connectors being radially spaced apart relative to the main conductor, the output connectors having center conductors electrically coupled to respective satellite conductors and having respective second conductors electrically coupled to a second ground conductor; and a multiconductor transmission line, including the satellite conductors, defined between the input connector and the output connectors. Methods of manufacturing are also disclosed. |
| US09673502B2 |
High-frequency signal transmission line and electronic device
A dielectric element assembly includes a plurality of dielectric layers stacked on each other in a direction of lamination and extends in an x-axis direction. A signal line is provided in the dielectric element assembly and extends in the x-axis direction. A reference ground conductor is provided on a positive side in a z-axis direction relative to the signal line. An auxiliary ground conductor is provided on a negative side in the z-axis direction relative to the signal line. Via-hole conductors connect the reference ground conductor and the auxiliary ground conductor and are provided in the dielectric element assembly on the negative side relative to the center in a y-axis direction. A portion of the signal line in a section which includes the via-hole conductors is positioned on the positive side in the y-axis direction relative to another portion of the signal line in a section which does not include the via-hole conductors. |
| US09673497B2 |
High frequency filter having frequency stabilization
A temperature-compensated high frequency filter of coaxial construction comprises at least one resonator having an inner conductor and an outer conductor housing. A compensation device made of a second material has a second coefficient of thermal expansion. The compensation device comprises a wall section, which extends in an axial direction and is variable in length in this direction in the event of a temperature change. The wall section is part of the housing wall configured in the manner of an intermediate layer or an upper-most layer located adjacent to the housing cover. The wall section may extend in an axial direction or in a direction transversely thereto and be variable in length in this direction in the event of a temperature change. The wall section is an integral part of the housing cover or is connected to the housing cover, or forms the housing cover having convex outwardly directed curvature. |
| US09673494B2 |
Portable electronic device thermal management system
An electronic device having a heat source disposed in direct alignment with a battery for the device and a thermal management system in thermal contact with the heat source. The thermal management system may extend from at least a first surface of the battery to a second surface of the battery. The second surface of the battery may be adjacent a heat dissipation element. The thermal management system may further be in thermal contact with the heat dissipation element. Further a portion of the thermal management system extends along the first and second surfaces of the battery and has a sufficiently high anisotropic ratio to avoid the transfer of heat to the battery to the extent to inhibit the functioning of the battery. |
| US09673493B2 |
Battery temperature regulating device
A battery temperature regulating device a battery module, a temperature detection device, a battery temperature regulating device, and a battery pack case. The battery temperature regulating device includes a cooling heat exchanger configured to cool air that passes therethrough, a condensed water reservoir configured to store condensed water generated in the cooling heat exchanger, and an air blowing device configured to blow the air in the vicinity of the cooling heat exchanger and the condensed water reservoir and circulate the air within the battery pack case. The battery temperature regulating device is configured to cool the air that passes through the cooling heat exchanger, drive the air blowing device to execute the cooling of the battery module when the temperature of the battery module is higher than a predetermined temperature, and drive only the air blowing device regardless of the temperature of the battery module. |
| US09673491B2 |
Vehicle battery system
A vehicle battery system has a vehicle battery, a cooling device to cool the vehicle battery and which includes a heat sink in thermal contact with the battery cells to transfer heat from the battery cells to the heat sink. The heat sink has at least one cooling channel through which a coolant may flow and connection ends formed by delimitations of the at least one cooling channel. A coolant distributor is provided at and connected to at least one end of the heat sink at a receiving region which is adhesive bonded to the heat sink, the receiving region of the coolant distributor surrounding the connection ends of the heat sink, in which the end faces of the delimitations of the cooling channel form stops for the coolant distributor which abut contact surfaces of the coolant distributor. |
| US09673490B2 |
Method and system for cooling secondary battery
Provided are a method and system for rapidly cooling a lithium secondary battery. A conductive connector is connected to at least one of positive and negative electrode terminals of a lithium secondary battery, and the conductive connector is brought into contact with a coolant to cool battery cells. The coolant may be water or air and may flow a coolant tube formed of a synthetic resin. An end of the coolant tube is fixed to at least one of the positive and negative electrode terminals. Therefore, owing to a cooling means disposed at a side of the lithium secondary battery, the temperature of the lithium secondary battery can be prevented from increasing to a preset value due to abnormal heating, and thermal stability of the lithium secondary battery can be improved by rapid cooling. |
| US09673487B2 |
Battery with a monitoring circuit and for use in a motor vehicle
A battery includes at least one battery cell in a battery cell housing and includes a housing cover having a monitoring circuit. An electrode of the at least one battery cell is connected in an electrically conductive manner to the battery cell housing via a switching mechanism in the monitoring circuit. The monitoring circuit is configured to open the switching mechanism when a malfunction signal is detected. The switching mechanism is closed during normal operation. Separate contacts provide contact to the cell housing in a module assembly and the electrode is disconnectable from the battery cell housing. |
| US09673486B2 |
Preparation method of laminated cell
The present disclosure provides a preparation method of a laminated cell comprising: providing a laminated pack: the laminated pack comprises n laminated groups, the each laminated group comprises m electrode plate assemblies, a spacer is provided between the adjacent laminated groups, the electrode plate assemblies of all the laminated groups of the laminated pack and the spacers between the adjacent laminated groups are orderly positioned in a Z-shaped separator in a laminating direction, an upper part and a lower part of the separator adjacent to the each spacer are separated by the each spacer; forming a laminated cell: the separator is broken at an end of the each spacer positioned in the separator to allow the each spacer and the each laminated group to separate from each other, so as to obtain the corresponding laminated cell formed by the electrode plate assembly of the each laminated group and the corresponding separator. |
| US09673485B2 |
Anode of cable-type secondary battery and manufacturing method thereof
Provided is a method for manufacturing an anode of a cable-type secondary battery having a solid electrolyte layer, including preparing an aqueous solution of an anode active material, making an anode by immersing a core as a current collector having a horizontal cross section of a predetermined shape and extending longitudinally in the aqueous solution, then applying an electric current to form a porous shell of the anode active material on the surface of the core, and forming a solid electrolyte layer on the surface of the anode by passing the anode through a solid electrolyte solution. The anode has a high contact area to increase the mobility of lithium ions, thereby improving battery performance. Also, the anode is capable of relieving stress and pressure in the battery, such as volume expansion during charging and discharging, thereby preventing battery deformation and ensuring battery stability. |
| US09673483B2 |
Reactive sintering of ceramic lithium ion electrolyte membranes
Disclosed herein are methods for making a solid lithium ion electrolyte membrane, the methods comprising combining a first reactant chosen from amorphous, glassy, or low melting temperature solid reactants with a second reactant chosen from refractory oxides to form a mixture; heating the mixture to a first temperature to form a homogenized composite, wherein the first temperature is between a glass transition temperature of the first reactant and a crystallization onset temperature of the mixture; milling the homogenized composite to form homogenized particles; casting the homogenized particles to form a green body; and sintering the green body at a second temperature to form a solid membrane. Solid lithium ion electrolyte membranes manufactured according to these methods are also disclosed herein. |
| US09673479B2 |
Energy accumulator module
An energy storage module having a plurality of stacked flat cells. The energy storage module has an interconnection formed in such a way that the energy storage module can be connected mechanically, electrically and/or for exchanging coolant with at least one other energy storage module of the same kind. |
| US09673472B2 |
Redox desalination system for clean water production and energy storage
An energy storage system employing a reversible salination-desalination process includes an electrochemical desalination battery (EDB) unit including an anode and a cathode. The EDB unit runs a salination process while storing energy from a direct current power supply unit, and runs a desalination process while releasing energy to an electrical load. The energy storage system can store power from a variable output electrical power supply unit such as solar cells and wind turbines while running a salination process, and release energy, e.g., during peak energy demand hours while running a desalination process. Combined with a capacitive deionization (CD) unit, the energy storage system can generate fresh water by running desalination processes in the EDB unit and the CD unit while releasing stored energy from the EDB unit. The energy storage unit can function as a dual purpose device for energy storage (load shifting) and fresh water generation. |
| US09673470B2 |
Electrolyte layer having a patchwork-type nanoporous grain boundary and a method of preparation thereof
Gadolinium-doped cerium oxide slurries used to form a patchwork type surface structure with nanoporous grain boundary prepared by mixing gadolinium-doped cerium oxide and a polymer binder to form a first mixture; wet-atomizing the first mixture under a pressure of at least 100 MPa to obtain a second mixture; coating the second mixture to a substrate to form a coated substrate; and sintering the coated substrate. The patchwork type structure is a polygonal or honeycomb structure having a size of from 0.1 μm to 3 μm. |
| US09673469B2 |
High performance multilayer electrodes for use in reducing gases
Electrode materials systems for planar solid oxide fuel cells with high electrochemical performance including anode materials that provide exceptional long-term durability when used in reducing gases and cathode materials that provide exceptional long-term durability when used in oxygen-containing gases. The anode materials may comprise a cermet in which the metal component is a cobalt-nickel alloy. These anode materials provide exceptional long-term durability when used in reducing gases, e.g., in SOFCs with sulfur contaminated fuels. The cermet also may comprise a mixed-conducting ceria-based electrolyte material. The anode may have a bi-layer structure. A cerium oxide-based interfacial layer with mixed electronic and ionic conduction may be provided at the electrolyte/anode interface. |
| US09673468B2 |
Polymer electrolyte material, polymer electrolyte molded product using the polymer electrolyte material and method for manufacturing the polymer electrolyte molded product, membrane electrode composite, and solid polymer fuel cell
It is an object of the present invention to provide a polymer electrolyte material which has excellent proton conductivity even under the conditions of a low humidity or a low temperature and is excellent in mechanical strength and fuel barrier properties, and which moreover can achieve high output, high energy density and long-term durability in forming a polymer electrolyte fuel cell therefrom, and a polymer electrolyte form article using the same and a method for producing the same, a membrane electrode assembly and a polymer electrolyte fuel cell, each using the same.The present invention employs the following means. Namely, the polymer electrolyte material of the present invention is a polymer electrolyte material including a constituent unit (A1) containing an ionic group and a constituent unit (A2) substantially not containing an ionic group, wherein a phase separation structure is observed by a transmission electron microscope and a crystallization heat measured by differential scanning calorimetry is 0.1 J/g or more, or a phase separation structure is observed by a transmission electron microscope and the degree of crystallinity measured by wide angle X-ray diffraction is 0.5% or more. Also, the polymer electrolyte form article, the membrane electrode assembly and the polymer electrolyte fuel cell of the present invention are characterized by being composed of such polymer electrolyte materials. |
| US09673464B2 |
Derivation of control parameters of fuel cell systems for flexible fuel operation
A method of operating a fuel cell system includes characterizing the fuel or fuels being provided into the fuel cell system, characterizing the oxidizing gas or gases being provided into the fuel cell system, and calculating at least one of the steam:carbon ratio, fuel utilization and oxidizing gas utilization based on the step of characterization. |
| US09673461B2 |
Fuel cell
To prevent inflow of liquid water into a power generating portion even if the liquid water remains in a manifold, and to enable size reduction by making constant the contact or surface pressure. According to the present invention, in a fuel cell comprising a power generating section including an electrolyte membrane joined between an anode and a cathode, and a manifold to cause inflow and outflow of an hydrogen containing gas and an oxygen containing gas separately from each other to the anode and cathode; the manifold is formed with an inflow preventing portion to prevent inflow of a liquid water remaining in the manifold, into the power generating portion. |
| US09673459B2 |
Solid oxide fuel cell device
A single monolithic ceramic substrate has rectangular dimensions with thermal expansion dominant along the length. An inactive ceramic portion substantially surrounds a fuel cell active portion of scalable power. The active portion comprises a plurality of three-layer active structures, each including an electrolyte disposed between a first polarity electrode and a second polarity electrode, the electrolyte layers being co-fired with the inactive ceramic portion, and a first or second gas passage respectively associated with each first and second polarity electrode. The plurality of active structures are stacked in the thickness dimension with alternating polarity such that first polarity electrodes of adjacent active structures face each other with the associated first gas passage shared therebetween and second polarity electrodes of adjacent active structures face each other with the associated second gas passage shared therebetween. The power is scalable according to the number of active structures stacked to define the plurality. |
| US09673456B2 |
Non-PGM catalysts for ORR based on charge transfer organic complexes
A sacrificial support-based method, a mechanosynthesis-based method, and a combined sacrificial support/mechanosynthesis support based method that enables the production of supported or unsupported catalytic materials and/or the synthesis of catalytic materials from both soluble and insoluble transition metal and charge transfer salt materials. |
| US09673454B2 |
Sodium-ion secondary battery
With a small amount of a conductive additive, an electrode for a storage battery including an active material layer which is highly filled with an active material is provided. The use of the electrode enables fabrication of a storage battery having high capacity per unit volume of the electrode. By using graphene as a conductive additive in an electrode for a storage battery including a positive electrode active material, a network for electron conduction through graphene is formed. Consequently, the electrode can include an active material layer in which particles of an active material are electrically connected to each other by graphene. Therefore, graphene is used as a conductive additive in an electrode for a sodium-ion secondary battery including an active material with low electric conductivity, for example, an active material with a band gap of 3.0 eV or more. |
| US09673452B2 |
Graphene oxide as a sulfur immobilizer in high performance lithium/sulfur cells
The loss of sulfur cathode material as a result of polysulfide dissolution causes significant capacity fading in rechargeable lithium/sulfur cells. Embodiments of the invention use a chemical approach to immobilize sulfur and lithium polysulfides via the reactive functional groups on graphene oxide. This approach obtains a uniform and thin (˜tens of nanometers) sulfur coating on graphene oxide sheets by a chemical reaction-deposition strategy and a subsequent low temperature thermal treatment process. Strong interaction between graphene oxide and sulfur or polysulfides demonstrate lithium/sulfur cells with a high reversible capacity of 950-1400 mAh g−1, and stable cycling for more than 50 deep cycles at 0.1 C. |
| US09673448B2 |
Electrodes, lithium-ion batteries, and methods of making and using same
Described herein are improved composite anodes and lithium-ion batteries made therefrom. Further described are methods of making and using the improved anodes and batteries. In general, the anodes include a porous composite having a plurality of agglomerated nanocomposites. At least one of the plurality of agglomerated nanocomposites is formed from a dendritic particle, which is a three-dimensional, randomly-ordered assembly of nanoparticles of an electrically conducting material and a plurality of discrete non-porous nanoparticles of a non-carbon Group 4A element or mixture thereof disposed on a surface of the dendritic particle. At least one nanocomposite of the plurality of agglomerated nanocomposites has at least a portion of its dendritic particle in electrical communication with at least a portion of a dendritic particle of an adjacent nanocomposite in the plurality of agglomerated nanocomposites. |
| US09673445B2 |
Battery
A battery is provided. The battery includes a positive electrode including a positive electrode active material layer provided on a positive electrode current collector; a negative electrode; and a separator at least including a porous film, wherein the porous film has a porosity ε [%] and an air permeability t [sec/100 cc] which satisfy formulae of: t=a×Ln(ε)−4.02a+100 and −1.87×1010×S−4.96≦a≦−40 wherein S is the area density of the positive electrode active material layer [mg/cm2] and Ln is natural logarithm. |
| US09673439B2 |
Connecting structure for exteriorly connecting a battery cell and a load circuit by using two connecting graphite blocks
A connecting structure for exteriorly connecting a battery cell and a load circuit by using two graphite connecting graphite blocks, wherein the positive and negative electrode terminals of the battery cell are made of nickel, the battery cell is connected to the load circuit by the two connecting graphite blocks, respectively. The graphite is inexpensive and resistant to oxidation; whereas, the connecting graphite blocks and the nickel-plated metal made electrode terminals of the battery cell will dissolve in each other to form a carbon-nickel alloy after being brought into contact with one another, thus ensuring a smooth large-current discharge because of the reduction in resistance of external connection. |
| US09673436B2 |
Nonaqueous electrolyte secondary battery
The nonaqueous electrolyte secondary battery of the present invention has a positive electrode, a negative electrode, a separator interposed between the positive electrode and the negative electrode, and a nonaqueous electrolyte solution. The battery further has a porous heat-resistant layer provided between the separator and at least one of the positive electrode and the negative electrode, wherein the porous heat-resistant layer includes an inorganic filler and a binder. The inorganic filler included in the porous heat-resistant layer has a particle size distribution with two peaks, which are a first peak (P1) at a relatively small particle diameter and a second peak (P2) at a relatively large particle diameter. When the particle diameter of the first peak (P1) is D1 be and the particle diameter of the second peak (P2) is D2 being, the peak particle diameter ratio D1/D2 satisfies the condition 0.2≦D1/D2≦0.7. |
| US09673433B1 |
Deformable battery pack enclosure
An exemplary electrified vehicle assembly includes, among other things, a lower wall of a battery enclosure and an upper wall of the battery enclosure. The upper wall includes an upper wall deformation area that is configured to deform in response to a load applied to the battery enclosure prior to other areas of the upper wall. |
| US09673427B2 |
Battery pack
An embodiment of the present invention provides a battery pack comprising a plurality of battery cells; a protective circuit module coupled to at least two battery cells; and a case accommodating the battery cells and the protective circuit module, wherein the two battery cells are disposed on a surface of the case, and the protective circuit module is disposed between the two battery cells on the surface of the case. |
| US09673425B1 |
Method for manufacturing AMOLED backplane and structure thereof
The present invention provides a method for manufacturing an AMOLED backplane and a structure thereof. The method uses a solid phase crystallization process to crystallize and convert amorphous silicon into poly-silicon so as to prevent the issue of mura on a display device caused by excimer laser annealing and adopts a back channel etching structure to effectively reduce the number of masks used. The method for manufacturing the AMOLED backplane according to the present invention needs only seven masking operations and, compared to the prior art, saves two masking operations, thereby simplifying the manufacturing process, improving the manufacturing efficiency, and saving costs. |
| US09673424B2 |
Mask frame assembly, method of manufacturing the same, and method of manufacturing organic light-emitting display device
A method of manufacturing a mask frame assembly, the method including: forming a first through hole in a vicinity of a first deposition region of a first mask; forming a second through hole in a vicinity of a second deposition region of a second mask; forming a third through hole in a first portion of a supporting stick; forming a fourth through hole in a second portion of the supporting stick; aligning the first through hole with the third through hole; aligning the second through hole with the fourth through hole; inserting a fixing member in the aligned first and third through holes; and inserting the fixing member in the aligned second and fourth through holes, wherein the support stick couples the first mask and the second mask together via the fixing member. |
| US09673422B2 |
Display device
A display device includes a substrate and a reflection layer. The substrate includes a first emission region, a second emission region, a third emission region, and a non-emission region. The reflection layer overlaps the first emission region, the second emission region, and the non-emission region, and has an opening corresponding to the third emission region. The first emission region, the second emission region, and the third emission region emit different color light. |
| US09673416B2 |
Electro-optical apparatus, manufacturing method thereof, and electronic device
There is provided an electro-optical apparatus including an element substrate that includes a display region in which a plurality of light-emitting elements are arranged, and a peripheral region in which a terminal is disposed. The light-emitting element has a structure in which a reflective electrode, an optical adjustment layer, a first electrode, a light-emitting layer, and a second electrode are laminated, and the first electrode is electrically connected to a contact electrode. The terminal has a structure in which a first terminal layer that is formed by a first conductive film which is the same as the reflective electrode, a second terminal layer that is formed by a second conductive film which is the same as the contact electrode, and a third terminal layer that is formed by a third conductive film which is the same as the first electrode are laminated. |
| US09673406B2 |
Metal complexes with boron-nitrogen heterocycle containing ligands
Novel organic compounds comprising a boron-nitrogen heterocycle are provided. In particular, the compound contains an azaborine. The compounds may be used in organic light emitting devices to provide devices having improved photophysical and electronic properties. |
| US09673405B2 |
Organic electroluminescent device, display apparatus, and lighting apparatus
An organic electroluminescent device containing:a six-coordinate, ortho-metalated iridium complex represented by the formula (I): wherein V represents a trivalent linking group and is bound to L1 to L3 through covalent bonds;each of L1 to L3 is represented by the formula (II) andR1 represents a substituted aryl group having seven or more carbon atoms. |
| US09673401B2 |
Organic electroluminescent materials and devices
The present disclosure generally relates to novel compounds containing carbazole and triazine with different number of phenyl units attached to its core. In particular, the disclosure relates to compositions and/or devices comprising these compounds as hosts for PHOLEDs. |
| US09673400B2 |
Amine-based compound and organic light-emitting diode including the same
An amine-based compound is represented by Formula 1: An organic light-emitting diode includes a first electrode, a second electrode, and an organic layer between the first electrode and the second electrode. The organic layer includes an emission layer and the amine-based compound represented by Formula 1. The OLED including the amine-based compound represented by Formula 1 has good color purity, low driving voltage, high efficiency, high brightness, and/or a long lifetime. |
| US09673394B2 |
Conducting formulation
The invention relates to novel formulations comprising an organic semiconductor (OSC) and a conductive additive, to their use as conducting inks for the preparation of organic electronic (OE) devices, especially organic photovoltaic (OPV) cells, to methods for preparing OE devices using the novel formulations, and to OE devices and OPV cells prepared from such methods and formulations. |
| US09673393B2 |
Methods of forming memory arrays
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays. |
| US09673391B2 |
Resistance variable memory structure and method of forming the same
A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric. |
| US09673386B2 |
Structure and method to reduce shorting in STT-MRAM device
A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode. |
| US09673385B1 |
Seed layer for growth of <111> magnetic materials
A seed layer stack with a smooth top surface having a peak to peak roughness of about 0.5 nm over a range of 100 nm is formed by sputter depositing an X layer such as Mo on a Ni layer where the X layer has one or both of a larger bond energy and a greater atomic number than Ni. A (Ni/X)m laminate is formed and then an uppermost NiCr seed layer is deposited to enhance perpendicular magnetic anisotropy (PMA) in an overlying ferromagnetic layer. A <111> NiCr crystal structure promotes <111> texture in the ferromagnetic layer. X layers serve as a diffusion barrier to Ta migration from a bottom electrode and have good lattice matching with the adjoining Ni layer and uppermost NiCr layer. As a result of the smooth seed layer stack in a magnetic tunnel junction (MTJ), MTJ properties are improved and more reproducible. |
| US09673380B2 |
Temperature and field stable relaxor-PT piezoelectric single crystals
The application is directed to piezoelectric single crystals having shear piezoelectric coefficients with enhanced temperature and/or electric field stability. These piezoelectric single crystal may be used, among other things, for vibration sensors as well as low frequency, compact sonar transducers with improved and/or enhanced performance. |
| US09673378B2 |
Liquid-ejecting head, liquid-ejecting apparatus, piezoelectric element, and piezoelectric material
A liquid-ejecting head includes a pressure-generating chamber communicating with a nozzle opening, and a piezoelectric element. The piezoelectric element has piezoelectric layer contains a perovskite complex oxide containing Bi, La, Fe, and Mn and can undergo electric-field-induced phase transition. |
| US09673375B2 |
Power generator with an electrical component made from inertial mass and control circuit thereof
A force generator for introducing vibrational forces into a structure for vibration control of the structure includes an inertial mass, at least one actuator for generating a vibratory movement of the inertial mass relative to the structure, and a drive circuit constructed from components for driving the at least one actuator. At least part of the inertial mass is formed by one component of the drive circuit. |
| US09673362B2 |
Optical semiconductor element mounting package, and optical semiconductor device using the same
An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. |
| US09673360B2 |
Method for manufacturing light emitting device using strip-shaped first resin members
Provided is a method for manufacturing a light emitting device that can manufacture the light emitting device at low cost. The manufacturing method of a light emitting device includes: a mounting step of mounting a plurality of light emitting elements at predetermined intervals in one direction on a substrate; a first resin formation step of continuously forming a first resin layer in the one direction to directly cover the light emitting elements mounted; a trench formation step of forming a trench between the light emitting elements in a direction intersecting the one direction; and a second resin charging step of charging a second resin into the trench. |
| US09673358B2 |
Light emitting module
Disclosed is a light-emitting module capable of not only improving appearance quality but also maximizing light efficiency. The disclosed light-emitting module comprises: a circuit board; a light-emitting diode chip which is flip-bonded on the circuit board; and a housing which is positioned on the circuit board and surrounds the light-emitting diode chip, wherein the housing has a recess and reflective part having a curvature structure formed on an inner wall of the recess. |
| US09673357B2 |
Light emitting device package
An embodiment relates to a light-emitting device package. In an embodiment, the light-emitting device package includes a package body configured to include a top surface, a plate guide unit disposed on the top surface, and a cavity formed in the top surface, a light-emitting device disposed within the cavity, a plate disposed on the top surface of the package body and guided by the plate guide unit, and an adhesive member disposed between the top surface of the package body and the plate. The adhesive member includes a base layer made of a flexible material, a first adhesive tape disposed between the base layer and the top surface of the package body and bonded to the base layer and the top surface of the package body, and a second adhesive tape disposed between the base layer and the plate and bonded to the base layer and the plate. |
| US09673352B2 |
Semiconductor light emitting device
A light emitting device is provided. The light emitting device includes a substrate, an N type semiconductor layer formed on the substrate, an active layer, an electron-blocking layer, and a P type semiconductor layer formed on the electron-blocking layer. An N side electrode is formed on a first portion of the N type semiconductor layer, and the active layer is formed on a second portion of the N type semiconductor layer. The electron-blocking layer is a super lattice multi-layer structure formed on the active layer, the P type semiconductor layer is formed on the electron-blocking layer, and a P side electrode is formed on a portion of the P type semiconductor layer. |
| US09673350B2 |
Semiconductor component and process for fabricating a semiconductor component
A semi-conducting component including a semi-conducting layer of a first conductivity type including a plurality of semi-conducting zones of a second conductivity type opposite that of the semi-conducting layer, and an insulating layer. The component further includes a first bias mechanism configured to bias the semi-conducting layer and a second bias mechanism configured to bias a semi-conducting zone. The first bias mechanism includes a conducting layer in contact with the insulating layer and which includes passageways for each second bias mechanism with the spacing between the conducting layer and the second bias mechanism which is located facing the corresponding semi-conducting zone. |
| US09673348B2 |
Buffer layer deposition for thin-film solar cells
Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer or layers may be dispensed separately to the substrate web, rather than being mixed prior to their application. The web and/or the dispensed solutions may be heated by a plurality of heating elements. |
| US09673346B1 |
Optimally-angleable solar powered air systems
An optimally-angleable solar powered air system is a portable indoor solar heating unit that may stand upright or may be mounted to a door or window. The optimally-angleable solar powered air system has a frame having a solar panel mounted to a first side and a fan mounted to a second side of the frame. In use, the frame may stand inside a room at an angle facing the sun via a removable handle such that the solar panel is able to capture solar energy. The system may then convert solar energy into usable power to power the fan. The second side of the frame includes an air deflector which may direct airflow outwardly from the second side of the frame into the room. |
| US09673340B1 |
Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a first layer, a second layer, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the first layer. The second layer is between the first layer and the second insulating layer. The gate electrode is over the second insulating layer. There is a P-N junction between the first layer and the second layer. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate. The first layer, the first doped region, and the second doped region have a first type conductivity, which is opposite to a second type conductivity of the second layer. |
| US09673336B2 |
Method for manufacturing semiconductor device
A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor. |
| US09673335B2 |
Rectifier circuit including transistor whose channel formation region includes oxide semiconductor
In a rectifier circuit, by using a transistor whose off-state current is small as a so-called diode-connected MOS transistor included in the rectifier circuit, breakdown which is caused when a reverse bias is applied is prevented. Thus, an object is to provide a rectifier circuit whose reliability is increased and rectification efficiency is improved. A gate and a drain of a transistor are both connected to a terminal of the rectifier circuit to which an AC signal is input. In the transistor, an oxide semiconductor is used for a channel formation region and the off-state current at room temperature is less than or equal to 10−20 A/μm, which is equal to 10 zA/μm (z: zepto), when the source-drain voltage is 3.1 V. |
| US09673334B2 |
Low temperature poly silicon thin film transistors (LTPS TFTs) and TFT substrates
A LTPS TFT and a TFT substrate are disclosed. The LTPS TFT includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage. In this way, the feed through voltage may be reduced such that the TFT performance is enhanced. |
| US09673333B2 |
P-Si TFT and method for fabricating the same, array substrate and method for fabricating the same, and display device
A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions. |
| US09673328B2 |
Structure and method for providing line end extensions for fin-type active regions
A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region. |
| US09673323B2 |
Embedded JFETs for high voltage applications
A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. |
| US09673321B2 |
Pillar-shaped semiconductor device and method for producing the same
An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs. |
| US09673320B2 |
Transistor with improved avalanche breakdown behavior
A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer. |
| US09673318B1 |
Semiconductor device including a gate trench having a gate electrode located above a buried electrode
A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench. |
| US09673311B1 |
Electronic device including a multiple channel HEMT
An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer. |
| US09673308B2 |
Semiconductor device manufacturing method
According to the present invention, since the buffer layer is formed by multiple ion implantations of different acceleration energies and the non-diffusion region in which impurity do not diffuse is left between the buffer layer and the collector layer, the semiconductor device which can supply sufficient holes to the drift layer at the turn-off can be manufactured while the withstand voltage is ensured. |
| US09673304B1 |
Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer. |
| US09673302B2 |
Conversion of strain-inducing buffer to electrical insulator
Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator. |
| US09673299B2 |
Method for manufacturing split-gate power device
The present invention relates to the field of manufacturing technologies of semiconductor power devices, and more particularly to a method for manufacturing a split-gate power device. In the method for manufacturing a split-gate power device according to the present invention, lateral etching is added to form lateral recesses of a control gate groove below a first insulating film in a process of forming the control gate groove by etching, and therefore, after a first conductive film is deposited, the first conductive film can be directly etched by using the first insulating film as a mask to form control gates. The technical process of the present invention is simplified, reliable and easy to control, and can greatly improve the yield of the split-gate power device. The present invention is particularly suitable for the manufacture of 25V-200V semiconductor power devices. |
| US09673298B2 |
Integrated vertical trench MOS transistor
A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip. |
| US09673294B2 |
Bipolar transistor structure and a method of manufacturing a bipolar transistor structure
According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. |
| US09673291B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion. |
| US09673287B2 |
Reliable and robust electrical contact
In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact. |
| US09673283B2 |
Power module for supporting high current densities
A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2. |
| US09673282B2 |
Handle substrates of composite substrates for semiconductors, and composite substrates for semiconductors
A handle substrate of a composite substrate for a semiconductor is provided. The handle substrate is composed of polycrystalline alumina. The handle substrate includes an outer peripheral edge part with an average grain size of 20 to 55 μm and a central part with an average grain size of 10 to 50 μm. The average grain size of the outer peripheral edge part is 1.1 times or more and 3.0 times or less of that of the central part of the handle substrate. |
| US09673281B2 |
Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates. |
| US09673280B2 |
Cobalt silicidation process for substrates comprised with a silicon-germanium layer
A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions. |
| US09673279B2 |
Semiconductor device having multi-channel and method of forming the same
A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern. |
| US09673277B2 |
Methods and apparatus for forming horizontal gate all around device structures
A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure. |
| US09673274B2 |
Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench. |
| US09673272B2 |
Semiconductor device including capacitor and method of fabricating the same
A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode. |
| US09673271B2 |
Adaptive capacitors with reduced variation in value and in-line methods for making same
A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor. |
| US09673269B2 |
Integrated capacitor comprising an electrically insulating layer made of an amorphous perovskite-type material and manufacturing process
An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided. |
| US09673268B2 |
Integrated inductor for integrated circuit devices
A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. |
| US09673267B2 |
Organic light emitting diode display device having a capacitor with stacked storage electrodes and method for manufacturing the same
An organic light emitting diode display device is disclosed which includes: scan, data and power lines crossing one another and arranged to define a pixel region; a switching thin film transistor disposed at an intersection of the scan and data lines; an organic light emitting diode disposed in the pixel region; a driving thin film transistor disposed between the power line and the organic light emitting diode; and a storage capacitor disposed adjacently to the organic light emitting diode and configured to charge a data signal which is applied from the data line. The storage capacitor includes a plurality of sub storage capacitors in which a plurality of storage electrodes are stacked alternately with one another. |
| US09673263B2 |
Color filter forming substrate and organic EL display device
Provided is an organic EL display device capable of preventing or restraining color shift or color mixing in an image displayed in each of its pixels, this inconvenience being caused by the entry of light into the pixel from an organic EL element of a pixel adjacent to the pixel; and provided is a color filter forming substrate making it possible to produce such an organic EL display device. The color filter forming substrate is a substrate for an organic EL display device, in which: a pixel-dividing light-shielding region is arranged over one surface of a base material comprising a transparent substrate to make plural pixel regions into a region-divided form; and plural color-filter-forming coloring layers for multiple colors are arranged to the predetermined pixel regions in accordance with the respective colors, characterized in that a light-shielding layer is arranged in the pixel-dividing light-shielding region, and a surface of the light-shielding layer farthest from the one surface of the base material is positioned farther from the one surface of the base material than respective surfaces of the color-filter-forming coloring layers in the respective colors, these surfaces not being respective base material side surfaces of the coloring layers, are positioned. |
| US09673259B2 |
Organic photoelectronic device and image sensor
Example embodiments relate to an organic photoelectronic device that includes a first electrode, a light-absorption layer on the first electrode and including a first p-type light-absorption material and a first n-type light-absorption material, a light-absorption auxiliary layer on the light-absorption layer and including a second p-type light-absorption material or a second n-type light-absorption material that have a smaller full width at half maximum (FWHM) than the FWHM of the light absorption layer, a charge auxiliary layer on the light-absorption auxiliary layer, and a second electrode on the charge auxiliary layer, and an image sensor including the same. |
| US09673257B1 |
Vertical thin film transistors with surround gates
A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate. |
| US09673243B2 |
Photosensitive imaging devices and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. |
| US09673242B2 |
Image sensor with micro lens including a plurality of layers each of different thickness
An image sensor includes a color filter configured to pass a specific color of light; a micro lens formed under the color filter and configured with a plurality of layers in which an upper layer has a smaller area than a lower layer; and a photo device formed under the micro lens and configured to receive light passing through the micro lens and convert the received light into an electrical signal. |
| US09673237B2 |
Depth pixel included in three-dimensional image sensor, three-dimensional image sensor including the same and method of operating depth pixel included in three-dimensional image sensor
A depth pixel of a three-dimensional image sensor includes a first photo gate which is turned on/off in response to a first photo control signal, a first photo detection area configured to generate first charges based on a received light reflected from a subject when the first photo gate is turned on, a first transmission gate which is turned on/off in response to a first transmission control signal, a first floating diffusion area configured to accumulate the first charges generated from the first photo detection area when the first transmission gate is turned on, and a first compensation unit configured to generate second charges which are different from the first charges based on ambient light components included in the received light to supply the second charges to the first floating diffusion area. |
| US09673233B2 |
Array substrate, display panel and method for manufacturing array substrate
An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole. |
| US09673231B2 |
Array substrate having via-hole conductive layer and display device
Embodiments of the disclosure provide an array substrate having via-hole conductive layer and display device. The array substrate includes: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer. |
| US09673230B2 |
Pixel array
A pixel array includes a plurality of scan lines, a plurality of data lines, a first active device, a second active device, a first pixel electrode and a second pixel electrode. The first active device and the second active device are electrically connected to the corresponding scan line and data line respectively. The first pixel electrode is electrically connected to the first active device through a contact hole. The second pixel electrode is electrically connected to the second active device through the contact hole. |
| US09673225B2 |
Array substrate, fabrication method thereof and display device
Embodiments of the present invention provide an array substrate, a fabrication method thereof and a display device. The array substrate comprises a driver IC and pixel units, wherein each port of the driver IC is connected to a plurality of pixel units through a connecting structure, each connecting structure comprises a connecting line connected between a port of the driver IC and a plurality of pixel units, at least some of the connecting structures also comprise resistance regulating units for changing the total resistance values of the connecting structures, and the resistance regulating units are connected in series with the respective connecting lines; and/or the resistance regulating units are connected in parallel with parts of the respective connecting lines, so that the differences among resistance values of connecting structures can be reduced, and in turn the display effect of a display panel is improved. |
| US09673224B2 |
Semiconductor device
To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor. |
| US09673219B2 |
Vertical semiconductor device with thinned substrate
A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. |
| US09673216B1 |
Method of forming memory cell film
Disclosed herein are methods of forming memory cell films in 3D memory. An opening having a sidewall may be formed through a stack of alternating layers of silicon oxide and silicon nitride. Bird's beaks may be formed in the silicon nitride at interfaces with the silicon oxide. In one aspect, bird's beaks are formed using a wet SiN etch. In one aspect, bird's beaks are formed by oxidizing SiN. A dilute hydrofluoric acid (DHF) clean may be performed within the opening after forming the bird's beaks in the silicon nitride. A memory cell film may be formed in the opening after performing the DHF clean. The memory cell film is straight, or nearly straight, from top to bottom in a memory hole. The memory cell film is not as susceptible to parasitic charge trapping as a memory cell film having a wavy contour. Therefore, neighbor WL interference may be reduced. |
| US09673214B2 |
Semiconductor device
A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another. |
| US09673211B1 |
Integration of a memory transistor into high-k, metal gate CMOS process flow
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions. |
| US09673208B2 |
Method of forming memory array and logic devices
A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas. |
| US09673207B2 |
Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ΔMAX. |
| US09673205B2 |
Embedded nonvolatile memory and forming method thereof
A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. |
| US09673202B2 |
Structure and method for FinFET SRAM
Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure. |
| US09673200B2 |
Semiconductor device structure and method of manufacturing the same
A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure. |
| US09673198B2 |
Semiconductor devices having active regions at different levels
A semiconductor device has active regions with different conductivity types. A substrate has a PMOS region and an NMOS region. A first active region is in the PMOS region. A second active region is in the NMOS region. A semiconductor layer is on the first active region. A first gate electrode crosses the first active region and extends on the semiconductor layer. A second gate electrode is on the second active region. An upper end of the first active region extends to a level lower than an upper end of the second active region. A lower end of the first active region extends to a level lower than a lower end of the second active region. |
| US09673192B1 |
Semiconductor device including a resistor metallic layer and method of forming the same
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross member and a second cross member, and a first gain resistor including a first gain resistor metallic strip coupled to the first cross member. The semiconductor device also includes an amplifier over the substrate and coupled to the first gain resistor metallic strip. |
| US09673191B2 |
Efficient fabrication of BiCMOS devices
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region. |
| US09673188B2 |
Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor
A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region. |
| US09673182B2 |
Package on package bonding structure and method for forming the same
A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound. |
| US09673181B2 |
Package on package (PoP) bonding structures
Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures. |
| US09673180B2 |
Array substrate of organic light-emitting diodes and method for packaging the same
An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic light-emitting diodes, to shorten the package process time, and to improve the substrate utilization and the production efficiency. The array substrate of organic light-emitting diodes includes a plurality of display panels disposed in an array of rows and columns, wherein at least two adjacent display panels are connected through a frame adhesive, and there is no cutting headroom between at least one side of the at least two adjacent display panels. |
| US09673178B2 |
Method of forming package structure with dummy pads for bonding
Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die. |
| US09673174B2 |
Through silicon via bonding structure
System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. |
| US09673173B1 |
Integrated circuit package with embedded passive structures
An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer. |
| US09673171B1 |
Integrated circuit packaging system with coreless substrate and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects. |
| US09673169B2 |
Method and apparatus for a wafer seal ring
A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers. |
| US09673168B2 |
Connection body
Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles. |
| US09673165B2 |
Component mounting apparatus
A component mounting apparatus includes a tape attaching unit, a component mounting unit and a component compression unit provided in this order. A time measuring unit measures time having passed after completion of predetermined work performed on all the substrates transferred to the tape attaching unit, the component mounting unit, and the component compression unit, respectively. When preparation for transferring the substrates to the tape attaching unit is not completed within a predetermined time after the start of measurement performed by the time measuring unit, the respective substrates, which wait in the tape attaching unit, the component mounting unit, and the component compression unit, are forcibly transferred to the downstream sides and predetermined work is performed on the respective substrates that are forcibly transferred to the component mounting unit and the component compression unit. |
| US09673162B2 |
High power semiconductor package subsystems
A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect. |
| US09673161B2 |
Bonded structures for package and substrate
The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. |
| US09673158B2 |
Formation of connectors without UBM
A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer. |
| US09673157B2 |
Processing of thick metal pads
In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing. |
| US09673156B2 |
Package structure
A package structure includes a first insulation layer, at least one first electronic component, and a first re-distribution layer. The first electronic component is embedded within the first insulation layer, and the first electronic component includes plural first conducting terminals disposed on a bottom surface of the first electronic component. At least part of the bottom surface of the first electronic component is exposed from a bottom surface of the first insulation layer. The first re-distribution layer is formed on the bottom surface of the first insulation layer and contacted with the corresponding first conducting terminals. |
| US09673155B2 |
Integrated tunable filter architecture
An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated. |
| US09673151B2 |
Semiconductor package having metal layer
A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another. |
| US09673146B2 |
Low temperature tungsten film deposition for small critical dimension contacts and interconnects
Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process. |
| US09673144B2 |
Semiconductor device with metal think film and via
A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line. |
| US09673143B2 |
Semiconductor device and manufacturing method of the same
The semiconductor device 1 includes an insulating substrate 2, a conductive part 3 that extends in a first direction, a conductive part 4 that is separated in a second direction and extends in the first direction, conductive parts 5 that are lined along the first direction between the part 3 and the part 4, high-side switches 11, 12 and 13, low-side switches 14, 15 and, signal terminals that are arrayed along the first direction, a power supply terminal 21 that is electrically connected to the part 3, a ground terminal 22 that is electrically connected to the part 4, and output terminals 23, 24 and 25 that are electrically connected respectively to the corresponding parts 5, arrayed along the first direction on the other end side of the substrate 2, and provided over a straight line L that passes through the part 4 and extends in the first direction. |
| US09673128B2 |
Power module and fabrication method for the same
A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module. |
| US09673127B2 |
Silicone-based thermal interface materials
Embodiments described herein relate to silicone-based thermal interface materials which include a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm−3/2. |
| US09673125B2 |
Interconnection structure
A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad. |
| US09673122B2 |
Micro lead frame structure having reinforcing portions and method
In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. |
| US09673121B2 |
Carrierless chip package for integrated circuit devices, and methods of making same
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds. |
| US09673119B2 |
System and method for bonding package lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill. |
| US09673117B2 |
Semiconductor module
A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece. |
| US09673116B2 |
On chip electrostatic discharge (ESD) event monitoring
An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure. |
| US09673114B1 |
Precision substrate material removal using miniature-column charged particle beam arrays
Methods, devices and systems for patterning of substrates using charged particle beams without photomasks and without a resist layer. Material can be removed from a substrate, as directed by a design layout database, localized to positions targeted by multiple, matched charged particle beams. Reducing the number of process steps, and eliminating lithography steps, in localized material removal has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material removal allows for controlled variation of removal rate and enables creation of 3D structures or profiles. Local gas injectors and detectors, and local photon injectors and detectors, are local to corresponding ones of the columns, and can be used to facilitate rapid, accurate, targeted substrate processing. |
| US09673112B2 |
Method of semiconductor fabrication with height control through active region profile
The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions. |
| US09673108B1 |
Fabrication of higher-K dielectrics
A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer. |
| US09673102B2 |
Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions. |
| US09673099B2 |
Method of fabricating integrated circuit devices
An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors. |
| US09673094B2 |
Semiconductor device having via hole coated in side surfaces with heat treated nitride metal and method to form the same
A semiconductor device having a via hole whose side surface is covered with nitride metal is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials. The via hole is filled with a back metal and in side surfaces thereof is covered with the nitride metal which is heat treated at a preset temperature for a preset period. Nitrogen atoms in the nitride metal diffuse into the nitride semiconductor materials in the insulating regions and compensate nitride vacancies therein. The interface between the nitride metal and the nitride semiconductor material is converted into an altered region that shows enough resistivity to suppress currents leaking from the via hole metal to the conductive region of the nitride semiconductor material. |
| US09673089B2 |
Interconnect structure with enhanced reliability
An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided. |
| US09673087B2 |
Interconnect structures incorporating air-gap spacers
A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. |
| US09673084B2 |
Isolation scheme for high voltage device
Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage. |
| US09673082B2 |
Method of fabricating semiconductor device isolation structure
A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation. |
| US09673077B2 |
Pedestal construction with low coefficient of thermal expansion top
A support assembly for use in semiconductor processing includes an application substrate, a heater layer disposed directly onto the application substrate, an insulation layer disposed onto the heater layer, and a second substrate disposed onto the insulation layer. The heater layer is directly disposed onto the application substrate by a layered process such that the heater layer is in direct contact with the application substrate. The application substrate defines a material having a relatively low coefficient of thermal expansion that is matched to a coefficient of thermal expansion of the heater layer. |
| US09673075B2 |
Wafer container with door guide and seal
A wafer container that reduces or alleviates one or more of the problems associated with excessive container wall deflection due to loading and excessive particulate generation, particularly as those problems are experienced with containers for 450 mm diameter and larger wafers. The container has an enclosure and door with interlocking features to enable transfer of tension load to the door to minimize deflection of container surfaces. The container may include a gasketing arrangement compatible with the interlock feature. The container may include a removable door guide that improves centering of the door during door installation, and that is made of low particle generating material to reduce particulates. |
| US09673073B2 |
Manufacturing method of semiconductor device, and semiconductor device
Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor. |
| US09673068B2 |
Apparatus and method for processing substrate with film having porous structure (porous film) formed on surface layer thereof
A method for processing a substrate with a porous film having a porous structure formed on a surface layer thereof includes the following a) and b) steps. The a) step is a step of mixing a first processing solution containing water with gas to generate droplets of the first processing solution and injecting the droplets of the first processing solution to the porous film. In addition, the b) step is a step of, after the a) step, mixing a second processing solution which is an organic solvent having higher volatility than the first processing solution with the gas to generate droplets of the second processing solution and injecting the droplets of the second processing solution to the porous film. |
| US09673058B1 |
Method for etching features in dielectric layers
A method for etching features in a silicon oxide containing etch layer disposed below a patterned mask in a chamber is provided. An etch gas comprising a tungsten containing gas is flowed into the chamber. The etch gas comprising the tungsten containing gas is formed into a plasma. The silicon oxide etch layer is exposed to the plasma formed from the etch gas comprising the tungsten containing gas. Features are etched in the silicon oxide etch layer while exposed to the plasma formed from the etch gas comprising the tungsten containing gas. |
| US09673055B2 |
Method for quadruple frequency FinFETs with single-fin removal
A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed. |
| US09673054B2 |
Array of gated devices and methods of forming an array of gated devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed. |
| US09673053B2 |
Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer. |
| US09673043B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, substrate processing system and recording medium
There is provided a technique including: (a) forming a thin film containing a predetermined element, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element, carbon and a halogen element having a chemical bond between the predetermined element and carbon to the substrate; (a-2) supplying an oxidizing gas to the substrate; and (a-3) supplying a catalytic gas to the substrate; (b) removing a first impurity from the thin film by thermally processing the thin film at a first temperature higher than a temperature of the substrate in (a); and (c) removing a second impurity different from the first impurity from the thin film by thermally processing the thin film at a second temperature equal to or higher than the first temperature after performing (b). |
| US09673042B2 |
Methods and apparatus for in-situ cleaning of copper surfaces and deposition and removal of self-assembled monolayers
A method of processing includes: providing a substrate having a contaminant material disposed on the copper surface to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber; providing hydrogen (H2) gas to the HWCVD chamber; heating one or more filaments disposed in the HWCVD chamber to a temperature sufficient to dissociate the hydrogen (H2) gas; exposing the substrate to the dissociated hydrogen (H2) gas to remove at least some of the contaminant material from the copper surface; cooling the one or more filaments to room temperature; exposing the substrate in the HWCVD chamber to one or more chemical precursors to deposit a self-assembled monolayer atop the copper surface; and depositing a second layer atop the substrate. |
| US09673041B2 |
Plasma assisted atomic layer deposition titanium oxide for patterning applications
The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction. |
| US09673040B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer. |
| US09673038B2 |
Gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors
A method for gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors is disclosed in various embodiments. According to one embodiment of the invention, a method is provided for processing a semiconductor substrate. The method includes providing a substrate containing a germanium-containing semiconductor or a compound semiconductor, and exposing the substrate to a process gas containing a sulfur-containing gas and a nitrogen-containing gas that passivates a surface of the germanium-containing semiconductor or the compound semiconductor with sulfur. According to another embodiment, the germanium-containing semiconductor or the compound semiconductor has an oxidized layer thereon and the exposing to the process gas removes the oxidized layer from the substrate. According to another embodiment, the substrate may be treated with hydrogen fluoride (HF) gas and ammonia (NH.sub.3) gas to remove the oxidized layer from the substrate before passivating the germanium-containing semiconductor or compound semiconductor with sulfur. |
| US09673035B2 |
Ion source, and mass analysis apparatus including same
According to one embodiment of the present invention, an ion source includes: an anode tube in which gas flowing in through one side is ionized and discharged to the other side and in which a slit is formed on the outer circumference thereof; a filament which emits thermal electrons toward the slit so as to ionize the gas; and a diffusion-preventing body arranged between the filament and the slit and having at least one hole through which the thermal electrons can pass so as to reduce the diffusion of the thermal electrons flowing into the anode tube. |
| US09673034B2 |
Mass spectrometer
A mass spectrometer is disclosed comprising a time of flight mass analyzer. The time of flight mass analyzer comprises an ion guide comprising a plurality of electrodes which are interconnected by a series of resistors forming a potential divider. Ions are confined radially within the ion guide by the application of a two-phase RF voltage to the electrodes. A single phase additional RF voltage is applied across the potential divider so that an inhomogeneous pseudo-potential force is maintained along the length of the ion guide. |
| US09673027B2 |
Test apparatus and plasma processing apparatus
A test apparatus for efficiently and accurately testing a high frequency voltage dependency of an impedance of a test object without damaging the test object. The test apparatus includes a high frequency power source unit, a reference waveform generator, a matching device, an oscilloscope, a control panel, and a main control unit. The test apparatus may boost a high frequency pulse output at a relatively low power from the high frequency power source unit to a voltage required for a high frequency withstand voltage test to be applied to a test object in a state where impedance matching is performed between the high frequency power source unit and the test by the matching device, that is, under a tuned state. Whether the waveform of the voltage applied to the test object is a defined waveform may be concisely monitored and observed by the oscilloscope. |
| US09673026B2 |
Edge ramping
Systems and methods for performing edge ramping are described. A system includes a base RF generator for generating a first RF signal. The first RF signal transitions from one state to another. The transition from one state to another of the first RF signal results in a change in plasma impedance. The system further includes a secondary RF generator for generating a second RF signal. The second RF signal transitions from one state to another to stabilize the change in the plasma impedance. The system includes a controller coupled to the secondary RF generator. The controller is used for providing parameter values to the secondary RF generator to perform edge ramping of the second RF signal when the second RF signal transitions from one state to another. |
| US09673019B2 |
Electron detection system
An electron detection system for detecting secondary electrons emitted from a sample irradiated by a Focused Ion Beam (FIB). The FIB emanates from a FIB column and travels along a beam axis within a beam region, which extends from the FIB column to the sample. The system comprises an electron detector configured for detecting the secondary electrons, and a deflecting field configured to deflect a trajectory of the secondary electrons, which were propagating towards the FIB column, to propel away from the beam axis and towards the electron detector. The deflecting field may be configured to divert the trajectory of secondary electrons while the secondary electrons are generally within the beam region. |
| US09673010B2 |
Relay
A relay according to one embodiment of the present invention includes a housing, a cylinder, a fixed contactor coupled to the housing, a movable contactor contactable with or separated from the fixed contactor, a coil assembly disposed in the housing to generate a magnetic field, a movable shaft coupled with the movable contactor at an upper portion thereof, a fixed core inserted into the cylinder, a moving core fixed to the movable shaft to move the movable shaft in a pressing manner, a wipe spring to supply elastic force to the movable shaft, and a return spring located between the fixed core and the moving core. The moving core includes a cylindrical protrusion extending toward the fixed core and surrounding the movable shaft. |
| US09673009B2 |
Direct current relay
Disclosed embodiments relate to a direct current relay. In some embodiments, a direct current relay is capable of reducing noise by attenuating an impact generated between a fixed core and a moving core during an ‘ON’ operation, and by attenuating an impact generated between a shaft and a middle plate during an ‘OFF’ operation. |
| US09673006B2 |
Exhaust diffuser for a gas-insulated high voltage circuit breaker
A gas exhaust diffuser for a circuit breaker, comprising a first casing extending longitudinally along a principal axis with an open end to allow gas to enter and a closed end, and a second casing coaxial to the first casing, extending along the principal axis, with at least one outlet to allow gas to escape, the closed end of the first casing being arranged in the second casing and the first casing having at least two radial openings near its closed end to provide a fluid communication between the first and second casing. A plurality of incurved elements are positioned radially in the second casing at the at least one radial opening to create a rotation of an entering exhaust flow in a plan perpendicular to the principal axis, thereby generating a substantially helicoidally-shaped exhaust flow path in the second casing. |
| US09673005B2 |
Switchgear
The invention provides a switchgear that is capable of increasing a degree of freedom of a position of a moving arcing contact in a circuit breaker, does not require dimension management of components and a mechanism for adjusting a position of the moving arcing contact, and is capable of simplifying fabrication of components and assembly of devices and reducing cost. The switchgear according to the invention includes: a circuit breaker that is configured of a fixed arcing contact installed at a fixed-side conductor and a moving arcing contact installed at a moving electrode that opens and closes with respect to the fixed arcing contact; a linear motor that generates drive force for operating the moving arcing contact; a position detecting device that detects a position of a moving element of the linear motor; a contact detecting device that detects a contact state between the fixed arcing contact and the moving arcing contact; and a control device that sets a moving range of the moving arcing contact by controlling a voltage and a phase to be supplied to the linear motor based on the contact state between the fixed arcing contact and the moving arcing contact, which is detected by the contact detecting device, and position information of the moving element of the linear motor, which is detected by the position detecting device. |
| US09673004B1 |
Electrical switching apparatus, and arc chamber assembly and associated circuit protection method
An arc chamber assembly is for an electrical switching apparatus. The electrical switching apparatus includes a stationary contact and a movable contact structured to move into and out of engagement with the stationary contact in order to close and open the electrical switching apparatus, respectively. The arc chamber assembly comprises a plurality of splitter plates; a current loop member coupled to the plurality of splitter plates and being structured to extend from the stationary contact; an element coupled to the current loop member; and a number of permanent magnets each coupled to the element. The current loop member and the number of permanent magnets are structured to draw an electrical arc into the plurality of splitter plates. |
| US09673000B2 |
Multifunction key and electronic device with multifunction key
A multifunction key includes a key member, a conductive member, and a circuit baseboard. A portion of the key member extends out from a shell of an electronic device; the conductive member is fixed on a bottom of the key member. The conductive member includes a first protrusion member and a second protrusion member. One surface of the circuit baseboard includes a conductive layer and a resistance layer respectively contacting the first and the second protrusion member. Another surface of the circuit baseboard includes a first and second conductive terminal respectively connected to the conductive layer and the resistance layer. The conductive layer, resistance layer, first and second conductive terminal, conductive member, and an internal circuit of the electronic device form a circuit loop. When the key member moves, a resistance value of the resistance layer within in the circuit loop is changed and produces a corresponding key command. |
| US09672997B2 |
Method for the initial adjustment of a control device for electronic equipment
A method for control device adjustment comprising applying a preload simultaneously to a plurality of shafts of a control device so as to take up initial assembly play, wherein the control device comprises an upper actuating element that is movable relative to a lower supporting mounting, a lower supporting mounting, a switch that is actuated by the upper actuating element, and an articulated structure that is interposed vertically between the upper actuating element and the lower mounting to keep the upper actuating element parallel to a horizontal plane during its vertical downward movement relative to a frame, and the at least one shaft. The method also comprises providing an adjustment stop fixed relative to the lower mounting and forming a stop surface that interacts with a facing portion of the shaft. |
| US09672996B2 |
Control device of the spring type particularly for a high-voltage or medium-voltage circuit breaker or switch
The control device possesses a rigid main part combining most of the functional elements of this type of control device. It is made up of two portions of a rotary shaft, having placed between them a cam and a support arm that are connected together by a pivot that is offset relative to the axis of rotation. A toothed wheel having an inner set of teeth is placed around the support arm that is provided with a rachet system. The toothed wheel has an outer set of teeth-driven by a motor, via an intermediate gearwheel. The pivot controls the compression of the actuator spring by the assembly rotating. The device is applicable to high and medium voltage circuit breakers and switches. |
| US09672993B2 |
Electricity storage device and electricity storage module
An electrical storage device includes a casing that has an opening, an electrode assembly that is placed inside the casing, a terminal plate that is electrically connected to the electrode assembly, and a holder that is provided to surround the terminal plate, the terminal plate having a step or a slope in an area in which the terminal plate comes in contact with the holder. |
| US09672989B2 |
Solid electrolytic capacitor assembly for use in a humid atmosphere
A capacitor assembly that is capable of exhibiting good properties under humid conditions. The ability to perform under such conditions is due in part to the use of an intrinsically conductive polymer in the solid electrolyte that contains repeating units having the following formula (I): wherein, R is (CH2)a—O—(CH2)b; a is from 0 to 10; b is from 1 to 18; Z is an anion; and X is a cation. Due to its unique structure, the polymer is not highly sensitive to moisture. Consequently, the resulting capacitor assembly may exhibit excellent electrical properties even when exposed to high humidity levels. |
| US09672985B2 |
Capacitor and method for manufacturing the same
A capacitor includes a capacitor element that is a wound element or an element other than the wound element, and that includes electrode bodies each of which is in an anode side and a cathode side, and separators that intervenes between the electrode bodies; a sealing member that seals an opening of a case member accommodating the capacitor element; at least one electrode protrusion that protrudes from one of the electrode bodies on an element end-face of the capacitor element, at least one of current collector plate that is connected to the electric protrusion; and at least one terminal member that is disposed in the sealing member, and is superposed on the current collector plate, a side face part of the terminal member being welded to a side face part of the current collector plate. |
| US09672983B2 |
Peel resistant multilayer wiring board with thin film capacitor and manufacturing method thereof
A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer. |
| US09672980B2 |
R-T-B-M-C sintered magnet and production method and an apparatus for manufacturing the R-T-B-M-C sintered magnet
The present invention discloses an R-T-B-M-C sintered magnet and a method for manufacturing the R-T-B-M-C sintered magnet from an R-T-B-M-C alloy powder including the lubricant. The present invention also discloses an apparatus for manufacturing the R-T-B-M-C sintered magnet from the R-T-B-M-C alloy powder including the lubricant. The apparatus includes an alloy powder feeding mechanism for distributing the R-T-B-M-C alloy powder including the lubricant, a filling mechanism including a mold for receiving the R-T-B-M-C alloy powder including the lubricant, a press mechanism for compressing the R-T-B-M-C alloy powder including the lubricant and a stacking mechanism for storing the mold including the R-T-B-M-C alloy powder including the lubricant. |
| US09672977B2 |
Transparent capacitive wireless powering system
A transparent capacitive powering system (200) is disclosed. The system comprises a pair of receiver electrodes (241, 242) connected to a load (250) through an inductor (260), wherein the inductor is coupled to the load to resonate the system; and a transparent infrastructure (220) having at least a first layer (130) of a non-conductive transparent material and a second layer (120) of a conductive transparent material coupled to each other, wherein the second layer is arranged to form a pair of transmitter electrodes (221, 222), wherein the pair of receiver electrodes are decoupled from the second layer, thereby forming a capacitive impedance between the pair of transmitter electrodes and the pair of receiver electrodes, wherein a power signal generated by a driver (210) is wirelessly transferred from the pair of transmitter electrodes to the pair of receiver electrodes to power the load when a frequency of the power signal substantially matches a series-resonance frequency of the first inductor and the capacitive impedance. |
| US09672976B2 |
Multi-mode wireless charging
A device may include a multiple inductive coils arranged concentrically for operating according multiple modes of wireless power transfer. The device may include multiple layers of magnetic shields to protect device components from the effects of the magnetic field used for power transfer. Construction and material of multiple layers of shields may be based on addressing individually the different parameters of the multiple modes of operation and based on the combined effect of the layers in each mode of operation. In some examples, the device may include first and second ferrite shields each having different magnetic properties. |
| US09672974B2 |
Magnetic component and power transfer device
A magnetic component includes a first winding and a second winding which is insulated from the first winding and magnetically couples with the first winding. The first winding forms a first coil unit by being wound. The second winding forms a second coil unit by being wound about the same axis as the first winding. The second winding forming the second coil unit is disposed in areas X and Z. The magnetic component has the first coil unit and the second coil unit at positions that satisfy Equations 1 and 3. |
| US09672972B2 |
Winding component
A winding component includes a core that surrounds an outer circumference of a coil and end surfaces of flanges to form a closed magnetic circuit, in which notches through which end portions of the coil are drawn outward are so formed in the flanges that each of the notches extends radially inward from an outer circumferential edge of the corresponding flange, a wall that surrounds each of the notches such that the wall stands axially outward on the flange, a thick portion in a winding part in correspondence with the notches and thicker than other portions of the winding part, and a lid formed of a sidewall between an outer circumferential surface of the wall and the core and covers the outer circumferential surface of the wall and a top plate at an axially outer end of the sidewall and covers an opening in the wall. |
| US09672965B2 |
Reactor
A reactor includes a laminated core formed by laminating soft-magnetic ribbons in a lamination direction. The laminated core has a gap formed across a magnetic path direction in the laminated core. The laminated core also has a flat facing surface that faces the gap and a pair of flat side surfaces that are respectively on opposite sides of the facing surface in the lamination direction. The laminated core further has a pair of first corner curved surfaces that are formed between the facing surface and the pair of side surfaces. Each of the first corner curved surfaces has a width in the lamination direction greater than the thickness of each of the soft-magnetic ribbons. For each of the first corner curved surfaces, a length of the first corner curved surface in the magnetic path direction is greater than the width of the first corner curved surface in the lamination direction. |
| US09672960B2 |
Exterior member and electric wire wiring structure
An exterior member which covers the circumference of an electric wire, which is wired between electrical components, along the electric wire, and is supported by a supporting body while one side in a circumferential direction is exposed, includes an exterior member body that is formed into a long cylindrical shape and which has a predetermined background color, and an identifying mark that is provided on the outer surface of the exterior member body and which has another predetermined color different from the background color. The exterior member body is formed with at least one bent part which is bent at a middle position in a longitudinal direction, and the identifying mark is provided to face the one side while the exterior member is supported by the supporting body. |
| US09672957B2 |
Shielded electrical cable
A shielded electrical cable (50) includes conductor sets (51a, 51b) spaced apart along a width of the cable and extending along a length of the cable. Each conductor set includes first and second insulated conductors (52a, 52b), one or two drain grounding wires (54) disposed between the first and second insulated conductors, first and second conductive shielding films (56a, 56b) disposed on opposite first and second sides of the conductor set, and an adhesive layer (59) bonding the first shielding film to the second shielding film. |
| US09672949B2 |
X-ray imaging system and image processing method
The X-ray imaging system of this invention includes: a detecting member which detects a salt and pepper noise region in the reconstructed image based on at least one characteristic value of the moire stripe image not including the object and/or the moire stripe image including the object; a masked-image generating member which generates a masked image for identifying the detected salt and pepper noise region; and an image processing member which masks or trims at least one of the reconstructed image and the moire stripe images with the generated masked image. |
| US09672946B2 |
Water supply tank using compressor steam to provide cooling water to a nuclear reactor, and structure inside the tank reducing internal cooling water circulation resulting from injection of the steam into the tank
A passive high-pressure safety injection system includes a compressor which generates high-temperature and high-pressure steam, a cooling water supply tank which supplies cooling water using the compressed steam, a nuclear reactor which receives the cooling water so that the nuclear reactor is maintained in a cooled state, and an internal circulation prevention structure which is provided in the cooling water supply tank and prevents the cooling water from circulating in the cooling water supply tank. |
| US09672945B2 |
Reactor shutdown trip algorithm
A controller for producing a nuclear reactor shutdown system trip signal in response to at least one detector signal. The controller includes a signal conditioning module receiving the at least one detector signal and outputting a measured flux signal. A rate module generates a rate signal from the measured flux signal. A comparator circuit compares the rate signal to a trip setpoint and generates a first trip signal. |
| US09672944B2 |
Method of determining nuclear fusion irradiation coordinates, device for determining nuclear fusion irradiation coordinates, and nuclear fusion device
An object of the present invention is to efficiently improve uniformity of energy lines to be irradiated. A method of determining nuclear fusion irradiation coordinates according to the present invention is a method of calculating irradiation coordinates when energy lines are irradiated onto a nuclear fusion target, and comprises an initial arrangement step S202 of virtually arranging electric charges Qi at initial coordinates of the number of irradiation coordinates NB on a spherical surface S0 set by using random numbers, a coordinate analysis step S203 of analyzing coordinates ri of the electric charges Qi in time series based on coulomb forces acting among the electric charges Qi by constraining the coordinates ri onto the spherical surface S0, potential evaluation steps S205 and S206 of determining a timing at which potential energies of the electric charges Qi were stabilized based on the coordinates ri, and an irradiation coordinate deriving step S207 of deriving coordinates ri at the timing at which potential energies were stabilized as irradiation coordinates of energy lines in a case where a nuclear fusion target is arranged at the center of the spherical surface S0. |
| US09672941B1 |
Memory element status detection
A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element. |
| US09672940B1 |
Non-volatile memory with fast read process
In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters. |
| US09672939B2 |
Memory devices, testing systems and methods
Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested. |
| US09672937B2 |
Semiconductor device
A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair. |
| US09672936B2 |
Driving circuits and the shift register circuits
A driving circuit and a shift register circuit are disclosed. The driving circuit includes a plurality of cascaded multi-stages shift register circuits. Each of the shift register circuit includes a transmission door latch circuit and a signal transmission circuit. The transmission door latch circuit includes a transmission door, first clock signals triggering the transmission door such that transmission signals of two stages ahead are transmitted to the signal transmission circuit via the transmission door to generate transmission signals for the current stage. Second clock signals control the transmission signals of the current stage to pass through the signal transmission circuit to generate gate driving signals for the current stage. In this way, the driving circuit is feasible for CMOS manufacturing process, and owns the advantages such as low power consumption and high noise tolerance. |
| US09672935B2 |
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node. |
| US09672933B2 |
Threshold based multi-level cell programming for a non-volatile memory device
A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage. |
| US09672932B2 |
Nonvolatile memory device and memory system including the same
A nonvolatile memory device includes a memory cell array and a voltage generator. The memory cell array includes a plurality of planes, and each plane receives one of a first ground selection voltage and a second ground selection voltage. The voltage generator is configured to provide selectively one of the first ground selection voltage and the second ground selection voltage independently to each of the planes based on a result of an erase verification operation on each of the plurality of planes. |
| US09672928B2 |
Method and apparatus for estimating read levels of nonvolatile memory and for programming pilot signals used for such estimation
A method, executed by a memory controller, for estimating read levels of a nonvolatile memory includes reading voltages stored by memory cells of a page space within the nonvolatile memory to which pilot signals of a predetermined symbol are programmed. The number of memory cells are identified whose voltages, read from the page space, are less-than/greater-than a read-voltage applied in reading the voltages stored by the memory cells. A voltage to be applied for reading data stored in the page space is estimated based upon the identified number of memory cells. |
| US09672927B2 |
Semiconductor storage device
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. |
| US09672924B2 |
Nonvolatile memory device and operating method thereof
An operating method of a nonvolatile memory device includes receiving a read command from a memory controller; determining a read mode based on the received read command, controlling a precharge time and an offset of a precharge control signal according to the determination result, and precharging a sensing bit line among bit lines to a precharge voltage based on the controlled precharge control signal. The sensing bit line is a bit line being precharged according to the determined read mode among the bit lines. |
| US09672921B2 |
Device and method for storing data in a plurality of multi-level cell memory chips
A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips. |
| US09672920B2 |
Electronic device, non-volatile memorty device, and programming method
This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage. |
| US09672912B2 |
Semiconductor integrated circuit device with reduced power consumption
A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor. |
| US09672905B1 |
Optimize data protection layouts based on distributed flash wear leveling
A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided. |
| US09672904B1 |
6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write
A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in terms of area, dynamic power, leakage power and performance over the prior art in the industry. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per mux. |
| US09672902B1 |
Bit-cell voltage control system
In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage. |
| US09672898B1 |
Read column select negative boost driver circuit, system, and method
Embodiments include a read column select negative boost driver of a memory device. The negative boost driver may include a negative boost element coupled to a P-type metal-oxide-semiconductor (PMOS) pass gate, and configured to negatively boost a read column select signal below a negative power supply level VSS dependent on a boost control signal. The negative boost driver may further include an N-type metal-oxide-semiconductor (NMOS) boost control transistor coupled to the negative boost element and to a read column select inverter, and configured to tri-state the read column select inverter dependent on the boost control signal. |
| US09672897B1 |
Method and apparatus for memory speed characterization
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator. |
| US09672891B2 |
Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module
A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB. |