| Document | Document Title |
|---|---|
| US09647594B2 |
Flyback control mode-based controller and motor-controlling method thereof
A flyback control mode-based controller includes a power supply circuit, a position-checking circuit, a current-checking circuit, a control circuit, and a power output circuit. The power output circuit includes a controlled energy conversion unit. The energy conversion unit includes a control switch and an energy conversion circuit. The energy conversion circuit uses the capacitor C circuit, the inductor L circuit, or the LC circuit to connect parallelly or serially with an inductor in a motor winding L so as to form an oscillation circuit, such that periodic oscillations with attenuation are enabled by relying on the energy stored in the motor winding L. By applying the controller to motors having forward control mode or motors having flyback control mode, the current to be released by the motor during discharging can be repeated used, thereby achieving maximum energy conservation. |
| US09647589B2 |
Alternator with current measurement
An alternator is described that is configured to provide a current for powering one or more loads. The alternator includes an output port configured to output the current for powering the one or more loads, and one or more current sensors configured to measure a current level of at least a portion of the current being output via the output port to the one or more loads. The alternator further includes one or more communication ports configured to transmit information based on the current level measured by the one or more current sensors. |
| US09647588B2 |
Decay lock loop for time varying current regulation in electric motors
A system and method for a decay lock loop for time varying current regulation in electric motors determines if a predetermined electrical current regulation level for an electric motor has been obtained within a tuning control time window. A coarse control loop increases or decreases a fast current decay, in response to a determination that the predetermined electrical current regulation level has not been obtained within the tuning control time window, until the predetermined electrical current regulation level falls within the tuning control time window. A fine control loop increments or decrements an amount of fast current decay during a total decay time, in response to a determination that the predetermined electrical current regulation level has been obtained within the tuning control time window, until a predetermined timing of the predetermined electrical current regulation level has been obtained. |
| US09647586B2 |
Signal amplifier, phase detector, and motor drive controller
A signal amplifier for a phase detector, based on plural sensor signals having amplitude levels in accordance with a rotational position of a rotor of a motor to detect the rotational position thereof includes a first phase detector; a phase counter; a signal amplification factor operation circuit; a signal amplification factor controller; and a signal amplification unit. |
| US09647584B2 |
Motor drive controller and control method of motor drive controller
A motor drive controller includes: a control circuit unit configured to output a drive control signal for driving a motor in response to a command signal externally input to the control circuit unit; and a motor driving unit configured to output a drive signal to the motor based on the drive control signal output from the control circuit unit. The control circuit unit is provided with: a speed setting unit configured to generate a target rotation speed signal corresponding to a target rotation speed based on a command step determined in response to a step command signal and predetermined setting information when the step command signal is input as the command signal; and a drive control signal generating unit configured to generate and output the drive control signal based on the target rotation speed signal. |
| US09647583B2 |
Variable magnetization machine controller
A variable magnetization machine controller has a current command module, a magnetization module and a reducing current module. The current command module computes a vector current command in a dq axis based on a torque command. The magnetization module applies a magnetization control pulse to a d-axis current of the vector current command. Thus, the reducing current module applies a reducing current to a q-axis current of the vector current command based on the torque command and one of an estimated torque of the variable magnetization machine and a measured torque of the variable magnetization machine. |
| US09647578B2 |
Energy harvester
An energy harvester having a converter suitable for converting a variation of the energy to be harvested into a corresponding excess of electrical charges. There is a circuit for collecting the excess of electrical charges, the circuit is equipped with a controllable switch and a control device for the switch designed to control the switching of this switch to its closed position. The control device is suitable for exerting a force which stresses the electrical contacts towards one another. The force varies continually as a function of the quantity of electrical charges present on the first terminal and bringing the electrical contacts to bear on one another only when the excess of electrical charges exceeds a predetermined threshold, and/or for ionizing the electrically insulating medium to produce an electrical arc between the two electrical contacts only when the excess of electrical charges exceeds the predetermined threshold. |
| US09647576B2 |
Vibration type driving apparatus, two-dimensional driving apparatus, image-blur correction apparatus, interchangeable lens, image-pickup apparatus, and automatic stage
A vibration type driving apparatus including:a vibrator including an electro-mechanical energy conversion device; a driven body between the vibrator and a movable body and driven in a first direction by the vibrator; and a moving mechanism that allows the movable body to move in a second direction relative to the driven body, in which the second direction is a direction intersecting the first direction in a plane parallel to a plane where the vibrator and the driven body are in contact with each other. |
| US09647575B2 |
Power converter
A power converter fixes, in one cycle of an alternating-current voltage output command, a gate pulse signal to always output a direct-current input positive side terminal voltage value of an inverter circuit in a period X1 centering on a phase angle θ1 for higher potential, fixes a gate pulse signal to always output a direct-current input negative side terminal voltage value of the inverter circuit in a period X2 centering on a phase angle θ2 for lower potential, and outputs a gate pulse signal in which a ratio of a period Y1, which is obtained by excluding the periods X1 and X2 from a period between the phase angle θ1 and the phase angle θ2, and the first period X1, and a ratio of a period Y2, which is obtained by excluding the periods X1 and X2 from a period between the phase angle θ2 and a phase angle θ1+360 [deg]. |
| US09647574B2 |
Multi-stage power inverter
An inverter for converting an input direct current (DC) waveform from a DC source to an output alternating current (AC) waveform for delivery to an AC grid includes an input converter, an output converter, an input controller, and an output controller. The input controller is configured to control the operation of the input converter, and the output controller is configured to control the operation of the output controller. The input and output controllers are electrically isolated from each other and may be incapable of direct communications between each other. In some embodiments, the input and output controllers may communicate with each other via the input and output converters. |
| US09647573B2 |
Low-power power supply
A low-power power supply for an electronic circuit uses an existing current input and converts the current to a higher voltage sufficient for supplying an electronic circuit. The input current generates a defined input voltage, which input voltage is initially generated by voltage drop by the input current passing at least one diode in the open direction of the diode. The input voltage, through a transistor, charges a plurality of switched capacitor networks in a first mode of operation, and in a second mode of operation, the switched capacitor networks are coupled in series for multiplying the input voltage to second higher voltage that is supplied to a oscillating circuit. The oscillating circuit drives the input current via a transformer and half bridge driver to convert a low voltage current supply from a low voltage current into a low current and higher voltage useable for supplying a small electronic circuit. |
| US09647565B2 |
Method for driving a resonant converter, and corresponding converter and computer program product
A driving module of a resonant converter receives an enabling signal and a voltage across a switch of a secondary side, and generates a control signal for first and second switches of the secondary side. The driving module cyclically controls switches of a primary full-bridge switching stage and both switches of the secondary side. After a fixed time, the driving module turns off the low-side switch and turns on the high-side switch, waits for a rising edge of the enabling signal, waits for zero current in the secondary side switches, turns off the first switch via the control signal after a variable delay relative to the rising edge of the enabling signal, keeps the second switch on, waits for zero voltage across the first switch, switches back on the first switch via the control signal when the voltage measured across the first switch drops below a variable threshold. |
| US09647564B2 |
Power supply device
A power supply device according to the present invention includes: a filter capacitor coupled to a line to which an input voltage that is passed through a dimmer is supplied; a discharge switch coupled to the filter capacitor through the line; and a main switch receiving the input voltage and controlling power transmission. The power supply device performs input voltage control for shaping the input voltage with a predetermined pattern using the discharge switch. |
| US09647558B2 |
System and method for maintaining a constant output voltage ripple in a buck converter in discontinuous conduction mode
The system and method creates a substantially constant output voltage ripple in a buck converter in discontinuous conduction mode by varying the on-time of a pulse width modulator (PWM) signal driving the buck converter when the buck converter is operating in discontinuous conduction mode. A first signal is generated that is a function of the switching frequency of the buck converter. This signal is low-pass filtered and compared with a second signal that is a function of the switching frequency of the buck converter when operating in continuous conduction mode and with constant PWM on-time. The output signal generated by the comparator is a signal that is equal to the ratio of the first signal and the second signal. The on-time of a voltage controlled oscillator is controlled by the output signal, the oscillator signal causing the on-time of the PWM signal to vary in a controlled fashion. |
| US09647552B2 |
Constant on time switching converter with DC calibration
A reference compensating circuit used in a COT control circuit. The reference compensating circuit has an error amplifier, a first current sink, a resistor, a second current sink, a current source and a capacitor. The error amplifier amplifies the difference between a reference signal and a feedback signal and generates an error signal. Based on the error signal, the first current sink generates a current flowing out from a node of the reference compensating circuit. The resistor receives the reference signal at one terminal. The other terminal of the resistor is coupled to the node. The second current sink sinks a current from the node intermittently. The current source sources a current into the node. The capacitor is coupled between the node and a ground to provide a calibrated compensation reference signal to the COT control circuit. |
| US09647549B2 |
Current sense controller for a DC-to-DC converter
A DC-to-DC converter comprises a first switch, a second switch coupled to the first switch, an inductor, and a plurality of serially connected power transistors. The first switch is to couple an input voltage to a common node. The first and second switches to be turned on and off in a reciprocating manner so as to couple either the input voltage or ground to the common node. The inductor, connecting the common node to an output voltage node of the DC-to-DC converter, is configured to control a voltage at the output voltage node based on current flowing through the inductor. The plurality of power transistors are concurrently controlled by a first signal that is based on a value of a voltage at the common node and a supply voltage, the serially connected power transistors to control an amount of current flowing through the inductor. Moreover, the first signal is used to prevent a high voltage drop from overstressing the plurality of power transistors while the first switch is on. |
| US09647548B2 |
Method for operating a power converter circuit and power converter circuit
In accordance with an embodiment, a method includes converting power by a power converter circuit having a plurality of converter cells coupled to a supply circuit. Converting the power includes a plurality of successive activation sequences and, in each activation sequence, activating at least some of the plurality of converter cells at an activation frequency. The activation frequency is dependent on at least one of an output power and an output current of the power converter circuit. |
| US09647547B2 |
Voltage conversion device for stepping up voltage
The present invention is intended to discriminate between a battery voltage sensor and the input voltage sensor of a converter for abnormality, without stopping the step-up operation of the converter. A voltage conversion device is provided with a battery, a converter, a battery voltage sensor, a voltage sensor for detecting the input voltage of the converter, a current sensor for detecting a reactor current, and a control unit. The control unit determines the abnormality of the battery voltage sensor or the input voltage sensor on the basis of an estimated value of input voltage calculated based on the reactor current, the input voltage of the converter and a battery voltage, without stopping the step-up operation of the converter. |
| US09647545B2 |
Reduced sleep current in power converters
A low standby power DC-DC converter can be powered down during standby mode. The DC-DC converter can be periodically awakened between sleep cycles to check if the output voltage needs to be recharged (refreshed). The duration of the sleep cycles can be varied to accommodate for changing load conditions that would affect the output voltage. |
| US09647543B2 |
Methods and systems for improving light load efficiency for power stages of multi-phase voltage regulator circuits
Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes. |
| US09647542B2 |
Switched mode power supplies
A switched mode power supply, SMPS. The SMPS comprises a switch, one or more inductors, an output smoothing capacitor, and a controller. The controller is configured to determine a first energy difference that is an instantaneous energy in the inductor(s) minus an energy in the inductor(s) at a load current, and determine a second energy difference that is an energy in the output smoothing capacitor at a reference voltage minus an instantaneous energy in the output smoothing capacitor. The controller is further configured to turn the switch on and off with a clock rate and a variable duty cycle such that the switch is on from the start of each period of the clock until the first energy difference is substantially equal to the second energy difference, and such that the switch is otherwise off. |
| US09647540B2 |
Timing generator and timing signal generation method for power converter
A timing generator and a timing signal generation method for a power converter are provided. The timing generator includes an adjusting circuit and a timing generation unit. The adjusting circuit receives an error signal related to an output voltage of the power converter. The adjusting circuit generates an adjusting signal according to the error signal and a delay circuit. The timing generation unit generates a timing signal according to the error signal, the adjusting signal and a control signal. A width of the timing signal is changed with the error signal and the adjusting signal. Accordingly, the timing generator adjusts On-time/Off-time in response to a transient response. |
| US09647539B1 |
Charge pump based on a clock generator integrated chip
A charge pump includes chip, package substrate and circuit board. Chip includes transistor set including at least four transistors connected to first input end of input terminal set and two rows of odd number and even number second input ends of input terminal set. Except first transistor, the other transistors are arranged in two rows subject to odd number and even number and respectively electrically coupled to the two rows of at least three second input ends by traces. At least three second external pins of package substrate and at least three capacitors of circuit board are respectively arranged in two rows subject to odd number and even number, enabling first circuit with connected odd number second external pins and second circuit with connected even number second external pin to be kept apart without intersection. Traces in chip are arranged in staggered manner, reducing parasitic capacitance. |
| US09647536B2 |
High voltage generation using low voltage devices
A charge pump design suitable for generating high voltages employs multiple low voltage capacitors and low voltage transfer switches, with a limited number of high voltage devices. This is designed such that during a first clock phase, capacitors are each connected between an input voltage and ground and, during a second clock phase all the capacitors are connected in series to generate the required voltage. Both the switches (PMOS) and as well the capacitors are realized as low voltage devices. The ability to use low voltage devices can significantly reduce the area and also a reduction in current consumption relative to the usual high voltage charge pumps which uses high voltage devices. |
| US09647535B2 |
Compact structure of power-supply apparatus capable of minimizing electromagnetic noise
A power-supply apparatus is provided which includes a transformer, a primary semiconductor unit, a secondary semiconductor unit, and a secondary electronic device. Each of the primary semiconductor unit and the secondary semiconductor units has a plurality of semiconductor devices installed therein. The transformer, the primary semiconductor unit, the secondary semiconductor unit, and the secondary electronic device are electrically joined through connecting conductors. The transformer is laid on the primary semiconductor unit to make a first stack. Similarly, the secondary electronic device is laid on the secondary semiconductor unit. This permits the power-supply apparatus to be reduced in overall size thereof and minimizes adverse effects of electromagnetic noise to ensure the high efficiency in power supply operation. |
| US09647533B2 |
PFC circuits with very low THD
A boost chopper circuit is described that an alternating current (AC) power source; at least one inductor connected to said AC power source; a rectifier connected to said inductor and AC power source; at least one switch shorting our said rectifier; a series circuit connected in parallel with said switch of at least one diode and a capacitor; and a load connected in parallel with said capacitor. A control technique is employed that includes turning on and off the switch in order to keep the average current per pulse cycle proportional to the AC input voltage during the same pulse cycle. |
| US09647531B2 |
Soft-start switching power converter
A soft-start switching power converter includes a voltage converting circuit and a soft-start circuit. The voltage converting circuit includes a transformer, and a first switch which includes a first terminal connected to the transformer, a second terminal providing a trigger signal, and a control terminal receiving a control signal, and which is controlled to switch between conduction and nonconduction, such that the transformer generates a feedback voltage. The soft-start circuit receives the trigger signal, generates the control signal according to the trigger signal, and determines whether or not to clamp the control signal at a preset voltage level based on the trigger signal. |
| US09647529B2 |
Modular multi-stage inverter comprising surge arrester
Electric power is transferred between an AC voltage grid and a DC voltage grid in the high-voltage range. Phase modules have at least one common DC voltage connection and separate AC voltage connections. A phase module branch between the DC voltage connection and each AC voltage connection has a series circuit of two-pole sub-modules, each with an energy storage device and a power semiconductor circuit in parallel with the energy storage device. The power semiconductor circuit is driven to generate either the voltage drop across the energy storage device or else a zero voltage at the two sub-module connection terminals. A converter transformer has a primary side on an AC voltage grid and a secondary side connected to the AC voltage connections. Improved protection against overloading is provided by at least one surge arrester between the or one of the common DC voltage connections and the inverter neutral point. |
| US09647527B2 |
Power supply circuit and power factor correction circuit
A power supply circuit includes a switching element and a control section. The control section converts back electromotive force generated at the time of the operation of the switching element to optical energy and converts the optical energy to an electrical signal. Furthermore, the control section drives the switching element on the basis of the electrical signal obtained by converting the optical energy. Accordingly, unlike a case where surge energy is regenerated by resonance, there is no need to use a resonant element such as an inductor. As a result, circuit scale is reduced. |
| US09647520B2 |
Double stator switched reluctance rotating machine
A double stator switched reluctance rotating machine includes an annular rotor, an outer stator that is disposed outside the rotor, and an inner stator that is disposed inside the rotor, and has a structure in which the outer and inner stators are connected to each other in parallel. |
| US09647518B2 |
Method for manufacturing laminated iron core
In a method for manufacturing a laminated iron core from a thin sheet, the method includes coining the thin sheet from below to form a thinned bridge portion on an outer peripheral portion of an iron core piece, blanking the iron core piece from the thin sheet from above or below after forming the bridge portion, and laminating the iron core piece on another iron core piece to manufacture the laminated iron core. |
| US09647509B2 |
Cooler and motor-integrated power conversion apparatus
A surface of a plate (102) having a predetermined thickness is used as a cooling surface (101). A pair of cooling medium entrance and exit (111, 112) are provided on one end surface (102a). First and second cooling medium flow paths (131, 132), a cooling medium branch path (121) communicating with the cooling medium entrance (111) and used for dividing cooling medium to flow into the cooling medium flow paths (131, 132), and a cooling medium merging path (122) at which the cooling media flowing from the exits of the cooling medium flow paths (131, 132) merge, are formed on a surface opposite to the cooling surface (101). The cooling medium flowing clockwise through the first cooling medium flow path (131) passes through a cooling medium communicating flow path (123) formed so as to three-dimensionally cross the first cooling medium flow path (131), so that the cooling medium flowing counterclockwise through the second cooling medium flow path (132) and the cooling medium flowing through the first cooling medium flow path (131) flow into the cooling medium merging path (122). Thus, pressure loss is avoided, high cooling performance is obtained, and simplification of a cooling system including a cooling medium pipe and the like can be realized. |
| US09647506B2 |
Motor and method for manufacturing motor
A brush holder is held between a flange of a yoke housing and a gear housing of a speed reduction unit and fastened by a fastening screw. A link of the brush holder is located between a screw fastening portion of the flange and a screw fastening portion of the gear housing. A connector is linked to a holder main body by the link. The link includes a screw insertion hole and first and second bridges. A metal terminal, which electrically connects the holder main body and the connector, is embedded in each of the first and second bridges. |
| US09647503B2 |
Rotary motor and manufacturing method therefor
The present invention provides a rotary motor including at least a field magnet having field winding, and an armature having armature winding with an electrically insulating coating material applied thereto, and the coating material includes at least two layers of: a lower-layer coating material including a first low-viscosity resin liquid; and an upper-layer coating material including a second low-viscosity resin liquid with at least hollow glass beads and a thermoplastic resin added thereto. Thus, a rotary motor can be achieved which achieves a balance between an efficiency improvement and reliability. |
| US09647500B2 |
Rotor for rotating electric machine
A rotor includes a rotor core in which a plurality of magnet housing holes are arrayed in a circumferential direction and a plurality of magnets fixed and held in the magnet housing holes by a filler material. The rotor core includes: a q-axis core portion, an outer flux bather that is formed between the q-axis core portion and the magnet and is filled with the filler material; and a bridge portion formed between a stator-side core portion and the q-axis core portion. The bridge portion includes a large-width portion, a small-width portion and a medium-width portion that are sequentially disposed from the q-axis core portion side towards the stator-side core portion side in the circumferential direction. The large-width portion has the largest radial-direction width. The small-width portion has the smallest radial-direction width. The medium-width portion has a medium radial-direction width between the largest radial-direction width and the smallest radial-direction width. |
| US09647498B2 |
Electric machine
An electric machine, especially a transversal flux machine, the stator being composed of a stack of phase segments, each phase segment having at least one stator segment and one stator winding, especially a single winding, each stator segment having an annular stator bridge, on which pole shoes are premolded, which in particular extend in the radially inward direction, and/or which extend in the direction of the rotor and/or which are situated between the rotor and the annular stator bridge, the pole shoes having the same shape, in particular, the axial width of the pole shoe decreasing with increasing radial clearance, the associated profile being disposed between a first and a second profile, the first profile being a linear function of the radial clearance, the pole back associated with the first profile being a planar area, in particular, the second profile being a circular function, in particular a circular segment function, the pole back associated with the second profile being a cylindrical section area, in particular. |
| US09647494B2 |
Fast network formation using a battery-backed network backbone
In one embodiment, a device in a network detects a power outage event in the network. The device causes an unprotected node in the network to use a first routing topology that includes a power-protected backbone, in response to detecting the power outage event. The power-protected backbone includes one or more nodes that are protected against the power outage event and the unprotected node is not protected against the power outage event. The device routes data for the unprotected node using the first routing topology. The device causes the unprotected node to use a second routing topology that optimizes a path from the unprotected node to a root node of the network based on one or more performance criteria. |
| US09647492B2 |
Direct current uninterruptible power supply system and device
A DC uninterruptible power supply system includes plural uninterruptible power supply devices, each of which includes a power cord, a battery module, a voltage detecting circuit, a current detecting circuit, and a control unit. When the voltage detecting circuit detects that a voltage at the power cord is lower than a first preset value, the control unit controls the battery module to output electrical power to the power cord. When the current detecting circuit detects that current of another uninterruptible power supply device is smaller than a second preset value, the control unit controls a switch to permit current flow to the another uninterruptible power supply device. |
| US09647490B2 |
Household appliance circuit arrangement
An electric household appliance has a low-voltage capacitive power means (10) connected to an electrical power network (3) and is designed to generate a low-voltage (S2,V2). The low-voltage capacitive power means (10) comprise a capacitive dividing circuit (28) comprising a first (30) and second input terminal (31) connected to a first and second power line (3) at a first (V1) and second (VREF) predetermined potential respectively; a first output terminal (32) adapted to generate said low-voltage enabling signal (S2); first (37) and second charge-accumulating means (38) connected between said first and second input terminal; and at least one voltage limiter (40) connected parallel to said second charge-accumulating means (38) and designed to switch from a non-conducting to a conducting state when subjected to a voltage above a predetermined breakdown voltage (VZ). The first (37) and second charge-accumulating means (38) are designed so that the voltage (VC2) at the terminals of said second charge-accumulating means (38) is below the predetermined breakdown voltage (VZ). |
| US09647485B2 |
Portable device and wireless power charging system for portable device
A portable device is provided. The portable device includes a power receiving unit configured to receive a first energy or a second energy from a wireless power transmitter, the first energy being used to perform a communication function and a control function, the second energy being used to charge a battery, and the wireless power transmitter being configured to wirelessly transmit a power, a voltage generator configured to generate a wake-up voltage from the first energy, or to generate a voltage for charging the battery from the second energy, a controller configured to perform the communication function and the control function, the controller being activated by the wake-up voltage, and a communication unit configured to perform a communication with the wireless power transmitter based on a control of the controller. |
| US09647484B2 |
Wireless charging transceiver device and wireless charging control method
A wireless charging transceiver device includes an energy storage module, a coil, a switch module, a rectifier circuit, and a resonant circuit. The coil is used to induce an external magnetic field or receive an external charging signal, and is used to transmit a wireless charging signal. The switch module is used to be coupled between the energy storage module and the coil through a first or second electrical path. The rectifier circuit is coupled between the energy storage module and the switch module, and is sited in the first electrical path, and rectifying a first inducing current which is induced from the external magnetic field in a first mode. The resonant circuit is coupled between the energy storage module and the switch module, and is sited in the second electrical path. |
| US09647480B2 |
Wireless power receiver and power control method thereof
Disclosed is a wireless power receiver for transferring power received from a wireless power transmitter to a load. The wireless power receiver includes a reception coil to receive AC power from the wireless power transmitter; a rectifying unit to rectify the received AC power into DC power; and a charging management unit to control DC power applied to the load by comparing the DC power with a threshold value. |
| US09647479B2 |
Charging system including a battery pack that outputs a stop request signal and a charging apparatus that stops power conversion in receipt of the stop request signal
A charging control device includes a control unit and a monitoring unit. The control unit performs at least one of controlling charging to a rechargeable battery and monitoring a state of a rechargeable battery, while outputting a state signal which indicates an operation state of the control unit. The monitoring unit determines whether or not the operation state of the control unit is a predesignated specified operation state based on the state signal outputted from the control unit. |
| US09647477B2 |
Power supply equipment utilizing interchangeable tips to provide power and a data signal to electronic devices
Power supply equipment includes an adapter which converts power from a power source to DC power for powering an electronic device. The power supply equipment includes circuitry which produces a data signal for use by the electronic device to control power drawn by the electronic device. A cable, extends from the adapter. The power supply equipment further includes a tip which has an input side and an output side. The input side of the tip is detachable mateable to the cable. The output side of the tip is detachably mateable to the electronic device. The tip output side has a shape and size dependent on the shape and size of a power input opening of the electronic device. The tip provides the data signal, as well as the DC power, to the electronic device. Different tips may be used to provide appropriate data signals to different electronic devices. |
| US09647474B2 |
Protective case for mobile device with auxiliary battery and power control
A protective case for a mobile device is disclosed. The case includes an additional power source (i.e., a battery) that can supply electric current to the mobile device. A processing device within the protective case may be wirelessly connected to the mobile device, such as with a Bluetooth interface, and thereby control operational aspects of the battery case, including for example control over supplying power to the mobile device. The battery case may be part of a charging system or kit that includes a uniquely designed separate charger. In yet another aspect, the protective case may include unitary bumper flexible bumper co-molded to the body of the case and a male connector extending from a nested portion that is adapted to tilt outward from the case to facilitate insertion of the corresponding female port on the mobile device into the connector and into the case. The protective case may also include a stand in the form of dock or cradle to allow positioning and/or charging of the battery case and mobile device via external contact terminals correspondingly positioned on the outside of the case and in the cavity of the cradle. |
| US09647472B2 |
Method and circuitry to recover energy from discharge signals of a charging operation of a battery/cell
Circuitry and methods to “capture”, recover, store and/or use electrical energy output and/or generated by the battery/cell as discharge signals of a charging sequence/operation. Such electrical energy may then be “reused” by the charging circuitry or system and/or in the system powered by the battery/cell and/or external to the charging circuitry or battery/cell. The energy output and/or generated by the battery/cell in response to discharge signals of a charging sequence/operation may (1) supply energy to the associated system being powered by the battery, (2) supply charge current to the same battery/cell or another battery/cell, (3) supply charge to one or more cells in a multiple cell battery pack that are at a lower voltage than the other cells, (4) store the charge in a different charge storing device (e.g., a capacitor and/or second battery), and/or (5) heat a battery/cell to improve charging performance. |
| US09647471B2 |
Battery management system and method
A battery management system (BMS) monitors and reports on an operational state of a battery. In some embodiments the BMS can be part of a battery assembly. In at least one embodiment the BMS can monitor battery voltage, charge and discharge current, temperature and (via a measurement utilizing magnetism) chemical change in a battery. In some embodiments, a permanent magnet is placed within the battery and a magnetoresistance sensor on the battery management system circuit board is employed to measure the affected magnetic field from the chemical change within the battery as it moves from a discharged state to a charged state and back to a discharged state. This measurement provides for an accurate statement of the battery's present day state of charge and state of health. |
| US09647462B2 |
Hearing instrument comprising a rechargeable power source
A hearing instrument having an audio signal source for providing for audio signals; an audio signal processing unit for processing said audio signals; a unit to be worn at or in a user's ear or to be implanted in the user's head for stimulating the user's hearing according to the processed audio signals, and a rechargeable power source, in which the rechargeable power source is a wound capacitor comprising a capacitor foil arrangement which has at least a first electrically conducting layer, a second electrically conducting layer and a dielectric layer in-between and which is wound in a manner so as to form an induction coil for generating a current for charging of the capacitor when exposed to an external alternating electromagnetic field generated by a charging device. |
| US09647460B2 |
System for the inductive charging of an energy accumulator of a vehicle, and charging station
A system for the inductive charging of an energy accumulator of a vehicle, and a charging station, an electronic circuit being provided in the interior of a hood, the opening of which is situated at the bottom side of the hood. |
| US09647459B2 |
Distributed low voltage power systems
A distributed low voltage power system is disclosed herein. The system can include a power source generating line voltage power, and a first line voltage cable having a first line voltage end and a second line voltage end, where the first line voltage end is coupled to the power source. The system can also include a first power distribution module (PDM) comprising a first power transfer device and a first output channel. The system can further include a first LV cable having a first LV end and a second LV end, where the first LV end is coupled to the first output channel of the first PDM. The system can also include at least one first LV device operating on the first LV signal, where the second LV end of the first LV cable is coupled to the at least one first LV device. |
| US09647456B2 |
Power management circuit and a method for operating a power management circuit
A power management circuit and a method for operating a power management circuit are described. In one embodiment, a power management circuit includes power switching modules. Power is supplied to each of the power switching modules by at least one of multiple power sources. Each of the power switching modules includes a latch circuit configured to have a definite state at power-up of a corresponding power source and a logic circuit configured to control power supplied from the corresponding power source in response to the definite state of the latch circuit, where the logic circuit includes a cross-coupled circuit. Other embodiments are also described. |
| US09647455B2 |
EMI filter systems and methods for parallel modular converters
A system and method for providing power to a vehicle is disclosed. The system can include a plurality of parallel module converter for prioritizing and allocating each electrical load to one or more parallel module converter modules. The centralization of power distribution can enable the reduction of components. The system can enable fewer power controllers, filters, and other components to be used, saving weight and time. The system can enable the controllers, inverters, and filters, among other things, to be utilized at a higher level reducing unnecessary redundancy. The system can enable the use of a single input EMI filter, for example, reducing the number of filters in the system significantly. Methods for designing EMI filters for each electrical load are also disclosed. |
| US09647453B2 |
Dual supply memory
According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal. |
| US09647447B2 |
Protective device having a thin construction
The present invention is directed to an electrical wiring device that includes a circuit interrupter assembly coupled to a solenoid actuator and configured to move along an assembly axis in a direction normal to a major surface of the electrical isolation member to provide electrical continuity between the plurality of line terminals, the plurality of load terminals and the plurality of receptacle contact structures in a reset state and to interrupt the electrical continuity to effect a tripped state. The circuit interrupter assembly including at least one portion configured to pivot relative to the assembly axis to effect the reset state or the tripped state. |
| US09647446B2 |
Electrical switching apparatus including alternating current electronic trip circuit with arc fault detection circuit
An electrical switching apparatus includes a transductor circuit that senses a direct current between at least one input terminal and at least one output terminal and outputs an alternating current proportional to the direct current between the input terminal and the output terminal. The electrical switching apparatus also includes a current sensor configured to sense an alternating current component of the direct current. The electrical switching apparatus further includes an alternating current electronic trip circuit including an arc fault detection circuit configured to detect an arc fault based on the sensed alternating current component. The alternating current electronic trip circuit is also configured to control pairs of separable contacts to trip open based on the alternating current output from the transductor circuit or the detected arc fault. |
| US09647445B2 |
Over-current protection circuit and method
A determination is made as to when the current flowing through a transistor exceeds a predetermined threshold. When the current exceeds the predetermined threshold, the transistor is deactivated. The deactivating of the transistor is effective to limit the current that flows through the transistor. The limiting of the current is effective to prevent damage to the transistor in an over current condition. The transistor is maintained in a deactivated state until a time off circuit resets the DC-DC converter circuit. The maintaining of the transistor in the deactivated state until a time off circuit resets the DC-DC converter circuit is additionally effective to reduce the time on (Duty Cycle—D.C.) and frequency to further prevent damage to the transistor due to switching power losses. |
| US09647443B2 |
Semiconductor device
A fuse, a resistor, and a transistor, which serve as an abnormality history setting unit, are provided in series between external terminals. The transistor receives a specific abnormality detection signal on its base from an abnormality detection circuit. The specific abnormality detection signal becomes “H” level in order to bring the transistor into an on state when a specific abnormal phenomenon to be detected occurs out of plural types of abnormal phenomena. The abnormality history setting unit executes an abnormality history operation for turning on the transistor and allowing a current exceeding a disconnection level to flow through the fuse provided between the external terminals to disconnect the fuse. |
| US09647438B2 |
Sealing grommet assembly with integral wire channel
A sealing grommet assembly for use with a panel and a wire bundle includes first and second grommets, a cable guide, and an annular retainer. The first grommet defines a first conduit and a first set of sealing lips. The second grommet defines a second conduit and a second set of sealing lips. The cable guide is positioned within the first and second conduits, and receives and supports the wire bundle. The annular retainer is encapsulated by the first and second grommets, and has a first set of axially-projecting latch fingers that secures the first and second grommets to each other. The retainer also has a second set of axially-projecting latch fingers that secures the first and second grommets to the panel. The sealing lips form a seal against opposite sides of the panel when the sealing grommet assembly is secured to the panel via the annular retainer. |
| US09647435B2 |
Busbar system especially for long vertical paths
A busbar system for the transport of energy especially for long vertical paths is disclosed, wherein the busbar system includes multiple sections, the sections each include multiple busbars and a holding piece, and the busbars of the sections are held by the respective holding pieces and electrically connected to one another via a connection. |
| US09647434B2 |
Binding structure for band for wire harness
A binding structure for a band for a wire harness prevents displacement of a band fastening position. A band (10) has a belt-shaped band section (12) by which electrical wires (80) are bound. The band section (12) includes a winding portion (14) wound around an outer periphery of the electrical wires (80) bundled together in a manner that the winding portion (14) is shifted away from a binding start point in a forward direction along a lengthwise direction of the electrical wires, and a winding portion (15) intersecting with the winding portion (14) in the forward direction and wound around the outer periphery in a manner that the winding portion (15) is shifted toward the binding start point in a return direction opposite to the forward direction. |
| US09647432B2 |
Quick lock tube securing system using connector, locking element, and engaging portion
A connecting system for quickly securing a hollow tube to a structure or another hollow tube using a connector that has housing with a tapered interior edge that operably engages a tapered locking wedge received therein. When the tube is inserted into the tapered locking wedge, the locking wedge therein holds and locks the tube in place in the connector. A guide ring may be provided within the connector to facilitate proper alignment of the tube within the connector and provide excellent electrical conductivity throughout the entire tube connecting system. One or more roller bearings may be provided within the wedge to facilitate initial tube insertion and then compression locking of the tube by the wedge. The connector can include a variety of structure engaging portions to allow the connector to be operably secured to a variety of structures such as electrical junction boxes, electrical conduits, tubes, armored cables, metal clad cables, flexible metal cables and the like. |
| US09647427B2 |
Spark-gap of an electric arc generation device, and corresponding electric arc generation device
A spark-gap of the invention comprises: a first body supporting a first electrode mounting connected to a first electrode having a first electrode end, a second body supporting a second electrode mounting connected to a second electrode placed so as to face the first electrode end, and a connection arm connecting the first body to the second body. The first body and the second body have a generally cylindrical outer shape and are aligned along a common longitudinal axis. The first electrode end is offset, relative to the longitudinal axis, toward the side opposite the connection arm. The invention also relates to an electric arc generation device comprising such a spark-gap. |
| US09647422B1 |
Laser device
A laser device has a plurality of semiconductor lasers, a driving device that supplies a driving electric current to the semiconductor laser, a trigger generation circuit that sends a trigger signal to the driving device in order to output the driving electric current, and a wave-combining device that wave-combines laser light emitted from the semiconductor lasers at the combined-wave end, and at least any one of a signal transmitting time, an electric current transmitting time and a light transmitting time is adjusted so as to be the time set respectively for transmitting paths; wherein the signal transmitting time in which the trigger signal transmits over the signal path, the electric current transmitting time in which the laser light transmits over the electric current path, a light transmitting time in which the laser light transmits over the optical path. |
| US09647421B2 |
Semiconductor laser module and method of manufacturing the same
The semiconductor laser module 1 has a first substrate 10, a second substrate 20 provided on the first substrate 10, a semiconductor laser device 30 operable to emit a laser beam L having an optical axis along the Z-direction, a collimator lens 40 configured to collimate components of the laser beam L along a direction of a fast axis (Y-direction), and a lens fixture block 50 having a lens attachment surface 50A and a block fixation surface 50B that are perpendicular to the X-direction. An end 40A of the collimator lens 40 along the X-direction is fixed to the lens attachment surface 50A of the lens fixture block 50 with a lens fixation resin 42. The block fixation surface 50B of the lens fixture block 50 is fixed to a side surface 20A of the second substrate 20 along the X-direction with a block fixation resin 52. |
| US09647419B2 |
Active silicon optical bench
An integrated photonic module includes a semiconductor substrate configured to serve as an optical bench. Alternating layers of insulating and conducting materials are deposited on the substrate and patterned so as to define electrical connections. An optoelectronic chip is mounted on the substrate in contact with the electrical connections. A drive chip is mounted on the substrate so as to provide an electrical drive current to the optoelectronic chip via the electrical connections. |
| US09647417B2 |
Laser device and method
A laser beam combining and power scaling device and method. A first highly reflective mirror residing perpendicular to the first optical axis reflecting radiation emitted from the first laser head. A first Q-switch in alignment with the first optical axis interposed between the first highly reflective mirror and the first laser head. A second highly reflective mirror residing perpendicular to the second optical axis reflecting radiation emitted from the second laser head. The second Q-switch in alignment with the second optical axis is interposed between the second highly reflective mirror and the first laser head. A third optical axis is coincident with the first optical axis. A third highly reflective mirror residing perpendicular to the third optical axis in alignment therewith. The third optical axis may include a third diode pumped laser head and Q-switch. A beam splitter resides at the intersection of the axes. |
| US09647409B2 |
Ultra-wideband supercontinuum light source based on dual-band fiber laser
The present invention is applicable to the field of fiber laser technologies. In the present invention, two fiber lasers of different bands are used as seed sources to form a dual-band fiber laser that outputs beams of two bands simultaneously, and the dual-band fiber laser is used to pump the cascaded evolving assemblies. Specifically, when the laser beams of the two bands go through a first-stage evolving assembly, the laser of one band is evolved into a visible-to-near-infrared supercontinuum, while the laser of the other band is evolved into an ultra-short pulse; the visible-to-near-infrared supercontinuum and the ultra-short pulse are coupled and enter a second-stage evolving assembly; the ultra-short pulse is further evolved into a near-infrared-to-mid-infrared supercontinuum, in which the visible-to-near-infrared supercontinuum generated at the previous stage is transmitted in a low loss manner; and an ultra-wideband supercontinuum covering visible, near-infrared, and mid-infrared bands is finally output from cascaded fibers. |
| US09647408B2 |
System and method to produce tunable synthesized optical frequency
A control circuit for generating an optical output at a target frequency using a single-frequency laser is provided. The control circuit includes a micro-ring resonator configured to generate a frequency comb of a plurality of comb frequencies based on a source frequency, a carrier-envelope offset interferometer configured to determine a carrier-envelope offset frequency of the frequency comb, a tunable filter configured to select a subset of comb frequencies of the frequency comb based on the target frequency, and a spectrometer configured to resolve ambiguities in overlap between the subset of comb frequencies and the frequency comb, and refine the subset of comb frequencies to a single comb frequency for output. |
| US09647405B2 |
Method of machining a flat harness using a punching machine
A flat harness is machined by providing a punching machine that includes a first punching device and a second device, and forming different types of hole portions in the shape on the insulating portion of the flat harness in a die cutting process by using the first punching device and the second punching device. |
| US09647403B2 |
Electric motor/generator with easily replaceable brush holder and brushes
An electrical machine (1) with a machine housing (5) receiving an electrically excited rotor (2) and a stator (10) of the electrical machine (1) and with an electronics unit (18) fastened to the machine housing (5) and electrically connected to an exciter winding (3) of the rotor (2) via at least one sliding contact (11, 12) consisting of at least one slip ring (13, 14) assigned to the rotor (2) and at least one brush (15, 16) assigned to the electronics unit (18), the brush (15, 16) being arranged displaceably in a brush holder (20). In this case it is provided that the brush holder (20) is fastened exchangeably in a guiding recess (27) of the electronics unit (18). |
| US09647402B2 |
Power connector products with improved Schuko grounding socket
The present invention relates to a power connector provided with an improved Schuko grounding socket architecture. The Schuko grounding socket architecture includes a Schuko access portion, which includes Schuko contacts located beyond the top face panel. The Schuko contacts are configured in the form of a flat metallic surface substantially parallel to the top face panel to provide a sufficient surface area for physical contact with the flat grounding contact of the Schuko plug, thereby ensuring a good ground contact with the plug. Preferably, the Schuko contacts are in turn bent over to gain additional structural strength. |
| US09647401B2 |
Connector device including cable connector
A connector device includes first and second connectors including first and second housings. The second housing has a recess that receives the first housing. The first housing is connected to one end portion of a cable and has a first opening portion, which allows the other end portion of the cable to extend to the outside, on a peripheral wall at one side. An outer peripheral surface of the peripheral wall includes an inclined surface at the other side. The inclined surface is inclined so as to approach a bottom portion of the recess while extending in a direction from the one end portion toward the other end portion of the cable. The inclined surface is brought into contact with the recess so that the first connector is moved relative to the second connector in the direction from the one end portion toward the other end portion. |
| US09647399B2 |
Connector for electrical connection
Connector for electrical connection includes coupler, cable, switch mechanism, failure detector and transmitter. Coupler is removably inserted in and connected to reception side connector provided in machine which is equipped with storage battery. Cable includes two or more electric wires including power line configured to be electrically connected to reception side connector via coupler. Cable is connected to device that performs at least one of supplying power to machine and receiving power from machine. Switch mechanism opens and closes electrical circuit between coupler and power line. Failure detector detects occurrence of failure of coupler. Transmitter transmits detection result of failure detector to device through at least one first electric wire of the two or more electric wires. Switch mechanism opens and closes the electrical circuit in accordance with control signal transmitted through first electric wire. |
| US09647397B2 |
Prognosis of connector disconnection with canary-based short terminals
A system and method for determining that a male terminal and a female terminal are becoming disconnected in a connector as a result of the connector becoming loose or the terminals becoming corroded. The connector is a multi-terminal connector including a male terminal housing that houses a plurality of male terminals and a female terminal housing that houses a plurality of associated female terminals. One of the male terminals is a diagnostic terminal that is shorter than the other male terminals so that it is disconnected from its associated female terminal before the other male terminals when the terminal housing separate, which can be used to detect connector failure. |
| US09647395B2 |
Electrical connector assembly with improved ground terminals
An electrical connector for high-frequency transmission comprises an elongate insulative housing including a top wall and a bottom wall opposite to each other, and a pair of end walls respectively connecting two ends thereof, and a receiving cavity surrounded thereby; a terminal assembly received in the top wall and the bottom wall respectively, and stacked in an up-to-down direction; and a metal case enclosing the insulative housing; wherein the terminal assembly includes a signal terminal group, and a ground terminal group including a first contact portion and a second contact portion, wherein the first contact portion and the second contact portion are arranged in a front-to-back direction perpendicular to both the up-to-down direction and the elongate direction, and respectively protruding into the receiving cavity. |
| US09647388B1 |
Miniaturized HDMI plug with plug-in retention feature
A high-definition multimedia interface (HDMI) plug includes a plug body section including a rigid outer shell that includes a roof section, a floor section, and a front-facing side. A male HDMI connector shell is secured to the rigid outer shell. A retention clamp is disposed within the plug body section and the male HDMI connector shell. The retention clamp includes an anchor, a flexing arm, and a tooth disposed at an end of the flexing arm. The anchor is vertically stabilized by a first interior liner that physically couples an upward-facing surface of the anchor to the roof section, and a second interior liner that physically couples a downward-facing surface of the anchor to the floor section. |
| US09647386B2 |
Percutaneous connector and associated methods of use
In one embodiment, the present invention includes a percutaneous skin connector including a base and a cap. The base has a channel extending through it and a plurality of base magnets are positioned around the channel and exposed at a base surface. A skirt which allows tissue ingrowth extends from the base to further secure the base to the patient. The connector also includes a cap with a bore extending through it and a plurality of cap magnets positioned around the bore and exposed at a cap surface. The base magnets and cap magnets attract and align the cap surface to the base surface. The connector further includes a release mechanism adapted to at least partially separate the cap from the base when the cap is rotated relative to the base and out of alignment with the base. |
| US09647385B2 |
Magnetic connection device
A magnetic connection device including a first connector including a first housing and a plurality of first electrodes mounted on the first housing in a state of being partially exposed and having magnetic substances; and a second connector including a second housing, a plurality of second electrodes mounted on the second housing and having magnetic substances, and elastic members for elastically supporting the plurality of second electrodes, wherein an end portion of each of the plurality of second electrodes is located in the second housing due to an elasticity of the elastic members in a state where a magnetic attraction is not applied from the plurality of first electrodes, and protrudes out of the second housing to be electrically connected to each of the plurality of first electrodes when there is the magnetic attraction applied from the plurality of first electrodes. |
| US09647382B2 |
Connector terminal having a two-part waterproof case
A connector terminal includes a barrel part capable of attaching thereto a conductor exposed from an outer skin of an electric wire to cause to conduct and connect, and a terminal part caused to conduct to a mating terminal. The barrel part and an end of the electric wire are covered with a waterproof case made of resin to be made waterproof. The waterproof case is made of divided two case members, and is formed of the same material as the outer skin of the electric wire. |
| US09647381B2 |
Downhole electrical wet connector
A downhole electrical wet connector comprising a plug which is slidingly inserted into a socket, the socket comprising a series of wiper seals spaced apart by separation zones, each zone being individually supplied with dielectric fluid from a separate reservoir. A retractable insert is arranged in the socket and displaced by the plug during connection. The fluid pressure in each zone is individually regulated relative to ambient wellbore pressure and the pressure in adjacent zones and optionally equalized to minimize loss of fluid. |
| US09647380B2 |
Connector
A connector 1 connecting an inverter and a motor includes an inverter case 10 where the inverter is arranged, an inverter side terminal block 30 mounted on the inverter case 10, an inverter side terminal disposed on the inverter side terminal block 30, a motor case where the motor is arranged, a motor side terminal block 40 mounted on the motor case 20, a motor side terminal disposed on the motor side terminal block 40 and fit to the inverter side terminal 32 such that the inverter case 10 is opposite the motor side terminal block 40, and a second sealing member S2 arranged between the inverter case 10 and the motor side terminal block 40 to surround a connection portion of the inverter side terminal 32 and the motor side terminal 42 and configured to seal a space between the inverter case 10 and the motor side terminal block 40. |
| US09647378B1 |
Electrical connector
An electrical connector is provided including a connector body having an upper housing, a lower housing and a front housing. The upper housing has terminal channels configured to receive terminals therein. The upper housing, the lower housing and the front housing are molded as a single piece with front sacrificial links connecting the upper and front housings and with rear sacrificial links connecting the upper and lower housings. The lower housing is press mated to the upper housing whereby the rear sacrificial links break as the lower housing is closed and mated to the upper housing. The front housing is press mated to the upper housing whereby the front sacrificial links break as the front housing is closed and mated to the upper housing. |
| US09647374B2 |
Distribution tap security cover
A security cover for a distribution tap that is mounted over the top of the tap preventing access to the service drop ports on the tap. The security cover includes one or more walls, a lid allowing access through the security cover to the tap, a base plate attachable to the tap and notches in at least one wall for cable access. The lid and walls fit over and enclose the service drop ports of the tap. The lid is attachable to at least one of the walls via a z-hinge and a plunger lock is used to secure the lid to the walls. One side of the base plate is attachable to the walls and the opposite side of the base plate is attachable to the tap. The base plate is substantially open to the top surface of the tap and is attachable via the tap's existing mounting points. |
| US09647372B2 |
High-voltage finger protection
An electrical pin contact is disclosed. The electrical pin contact has a free end, a base spaced apart from the free end and connected to a plug type connector, and an electrically insulating contact protection member extending from the base to the free end. The contact protection member forms an outer face between the base and the free end. |
| US09647371B2 |
Multipole electric plug connector part
A multipole electrical plug-in connector part includes a connector housing, a protective cap, and a clamping body. The protective cap is lockable to the connector housing and has an inlet opening. The protective cap further has a fixing section. The fixing section and the connector housing are connected together. The clamping body has elastically resilient clamping surfaces and is connected to the fixing section. Electrical connecting lines extending through the inlet opening toward the fixing section are mechanically fixed in a force-fit manner between the clamping surfaces of the clamping body and inner wall sections of the connector housing. |
| US09647368B2 |
Terminals for electrical connectors
A female terminal for an electrical connector may generally include a socket with an opening for receiving a male terminal, a first pair of contacts, a second pair of contacts, a pair of crimping members, and positioning tabs. The socket may be defined by a pair of opposing sidewalls, a top, and a bottom, at least in examples where the socket is generally rectangular. The first and second pairs of contacts may be disposed along the pair of opposing sidewalls, projecting at least partially into the socket configured to contact and exert substantially the same normal force on a male terminal that is inserted into the socket. The pair of crimping members can be utilized to secure a wire to the female terminal, and the positioning tabs may be utilized to secure the female terminal within the electrical connector. |
| US09647367B1 |
Current restrictive spring-loaded electrical connection device
In the present invention, a connector pin assembly for a high voltage (hv) connector used to connect a high voltage (hv) power supply to a cathode assemble of an X-ray tube is provided. The pin connector assembly includes a conductive outer cylinder adapted to be connected to a hv power supply, a conductive inner cylinder located at least partially within the outer cylinder, a biasing member disposed within the inner cylinder, a conductive plunger slidably disposed within and engaged with the inner cylinder and the biasing member and a non-conductive member disposed within the inner cylinder, the non-conductive member operable to restrict a current flowing through the connector pin along a path from the outer cylinder through the inner cylinder to the plunger, without contacting the biasing member. |
| US09647365B2 |
Electric connector
The contact state of a signal transmission medium and contact members is enabled to be maintained well by a simple configuration. Medium pressing portions of an actuator, which is subjected to a moving operation so as to electrically connect contact portions of contact members, which are in a multipolar arrangement, and a signal transmission medium (FPC, FFC, or the like) to each other, are disposed at the same positions as the contact portions of the contact members in the direction of the multipolar arrangement. The medium pressing portions of the actuator at the positions directly opposed to the contact portions of the contact members are configured to press the signal transmission medium when the actuator is moved to a working position so that the contact pressures applied from the medium pressing portions of the actuator to the signal transmission medium are reliably applied to the contact portions of the contact members without being dispersed. |
| US09647363B2 |
Techniques and configurations to control movement and position of surface mounted electrical devices
Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed. |
| US09647359B2 |
Electronic device having a tray for accommodating cards
An electronic device that accommodates a plurality of cards is provided. The electronic device includes a first contact area connected to a first card among the plurality of cards and a second contact area selectively connected to one of a second card or a third card among the plurality of cards. |
| US09647355B1 |
Automobile start supply voltage detection alligator clip with pull-off function
The invention aims at providing an automobile start supply voltage detection alligator clip with a pull-off function, including: a positive alligator clip structure; a negative alligator clip structure; a male contact head; and a positive pull-off end and negative pull-off end arranged on the male contact head; the positive/negative alligator clip structure includes a positive/negative upper cover, positive/negative upper cover contact piece, positive/negative pull-off contact piece, positive/negative pull-off spring, positive/negative lower cover contact piece, positive/negative lower cover, and positive/negative upper and lower covers pressure spring; an internal positive/negative silica gel wire is sleeved in an external positive/negative silica gel wire by an internal silica gel wire sleeving process; and the positive/negative pull-off contact piece is connected to a positive/negative pull-off detection end by the internal positive/negative silica gel wire. The male contact head, positive pull-off detection end and negative pull-off detection end are wrapped together by encapsulation. |
| US09647354B1 |
Terminal block splitter connector
The invention relates to a terminal block splitter connector including an insulating housing, the first conductive metal component, the second conductive metal component, the first fixing component, the second fixing component, the first wire inlet group, the second wire inlet group, the first push button, and the second push button. The first and second push button match with the first and second conductive metal component for on-line and off-line control of the first and second conductive metal component. A conductive connection plate is installed on the bottom of the insulating housing for power connection of the first and second conductive metal component. The first and second pin group are respectively mounted on the bottom of the first and second conductive metal component. The first and second socket group are installed on the conductive connection plate and respectively correspond to the first and second pin group. |
| US09647353B2 |
Method and apparatus for forming interface between coaxial cable and connector
A method of forming a solder joint between a coaxial cable and a coaxial connector includes the steps of: positioning a solder element between an end of an outer conductor of the coaxial cable and a connector body of the connector, wherein the connector includes an insulator with a suction passage; lowering the connector body and insulator onto a mounting structure; melting the solder element to form a solder joint between the outer conductor and the connector body, the solder joint including a lower surface formed by contact with the insulator and/or the connector body; and applying suction to the melting solder element from a suction source to reduce the formation of bubbles within the solder joint, wherein a suction path between the suction source and the solder element includes the suction passage in the insulator. |
| US09647352B2 |
Electric wire with terminal
Provided is an electric wire with a terminal (1), in which a resin portion (4) molded by a die covers a conductor exposure portion of a terminal (3) to which a conductor is connected. At least groove portion (16) is provided at a part of the terminal (3) covered with the resin portion (4) so that the groove portion (16) prevents the resin portion (4) from separating from the terminal (3) in a removing direction of the die after the resin portion (4) is molded by the die. |
| US09647350B2 |
Ground clamp adapter
A ground clamp adapter for grounding electrical wire. The ground clamp adapter comprises a first section. The first section comprises a body having a platform extending laterally from the body. The platform having a lateral recess and a transverse recess orthogonally integrally formed in the platform. At least one bracket is adjustably coupled to the platform proximate one of the lateral recess and the transverse recess. The bracket and one of the lateral recess and the transverse recess are configured to clamp a grounding wire. A second section has a coupling portion configured to adjustably couple with the first section. The second section is configured to clamp onto a pipe shaped object to conduct electricity to ground. |
| US09647348B2 |
Method for preparing a wire to receive a contact element
A method is provided for preparing a wire for installation of a terminal. The method comprises removing an insulating layer from a conductor to expose a portion of a conductor. The method further includes attaching a conductive foil layer to a portion of the exposed portion of the conductor by applying pressure to the conductive foil layer. |
| US09647346B2 |
Omnidirectional antenna
An omnidirectional antenna is provided. The omnidirectional antenna includes a spiral antenna including a substrate, at least one upper antenna pattern formed on the substrate, and at least one lower antenna pattern formed under the substrate and connected to the upper antenna pattern; and a monopole antenna that supports the spiral antenna and that is connected to the spiral antenna. Therefore, by forming an omnidirectional antenna in a spiral antenna having an upper antenna pattern and a lower antenna pattern at an upper surface and a lower surface, respectively, of a substrate, three-dimensional current flow is available and thus omnidirectional radiation characteristics may be exhibited. |
| US09647345B2 |
Antenna system facilitating reduction of interfering signals
Described embodiments include an antenna system and method. The antenna system includes a surface scattering antenna that has an electromagnetic waveguide structure and a plurality of electromagnetic wave scattering elements. The plurality of electromagnetic wave scattering elements are distributed along the waveguide structure, have a respective activatable electromagnetic response to a guided propagating electromagnetic wave, and produce a controllable radiation pattern. A gain definition circuit defines a radiation pattern configured to acquire a possible interfering signal. The defined antenna radiation pattern has a field of view covering at least a portion of an undesired field of view of an associated antenna. An antenna controller establishes the defined radiation pattern in the surface scattering antenna by activating the respective electromagnetic response of selected electromagnetic wave scattering elements. A correction circuit reduces an influence of the received possible interfering signal in a contemporaneously received signal by the associated antenna. |
| US09647343B2 |
Process for assembling different categories of multi-element assemblies to predetermined tolerances and alignments using a reconifigurable assembling and alignment apparatus
Systems and methods for assembling different multi-element items with different specifications using a reconfigurable apparatus are provided. One embodiment includes a base plate, a back plate coupled to the base plate in a predetermined angle relationship. The exemplary back plate comprises a plurality of alignment pins adapted to engage with alignment locations of multiple element assembly items. The exemplary base plate and alignment mounting structures couple to end cap parts disposed on opposing ends of the multiple element assembly items holding the items together. A clamping mechanism maintains/releases pressure on the multiple element assembly items against the back plate. The back plate holds alignment pins in a first back plate location in a first orientation for one type of multiple element assembly items and hold the alignment pins in a second location when the back plate is in a second orientation for a different type of multiple element assembly items. |
| US09647337B1 |
Dual-band antenna with grounded patch and coupled feed
Methods and systems for radiating electromagnetic energy with a patch antenna structure are described. A device may include a radio frequency (RF) feed and an antenna structure coupled to the RF feed. The antenna structure may include a ground plane, first and second conductors, and first and second impedance matching components. The first conductor may include an inner surface defining and at least partially surrounding a slot. The first and second impedance matching components may be coupled between the RF feed and the ground plane. |
| US09647331B2 |
Configurable antenna assembly
An antenna assembly may include a first ground plane, a second ground plane that may be switched between grounding and non-grounding states, and first and second antenna layers. Each of the first and second antenna layers may include a plurality of pixels interconnected by a plurality of phase change material (PCM) switches. The PCM switches are configured to be selectively switched between phases to provide a plurality of antenna patterns within the first and second antenna layers. |
| US09647326B1 |
High-efficiency broadband antenna
A design for high-efficiency broadband antennas which includes a D-plate and an E-cylinder, electrically insulated from each other, the E-cylinder being above the D-plate, and both parts insulated from a ground plane. The E-cylinder and D-plate may be fed by distinct feed networks with adjustable impedance. |
| US09647324B2 |
System and method for reducing reflections from metallic surfaces onto aircraft antennas
An aircraft traffic system is provided that includes a primary antenna operable to generate interrogation signals and receive interrogation replies from other aircraft. The system additionally includes a secondary antenna configured as a tuned absorber having a matched impedance to at least partially absorb reflections of the interrogation signals or interrogation replies utilized by the primary antenna. |
| US09647323B2 |
Electronic device with antenna having ring-type structure
In one embodiment, an electronic device including an antenna with a ring-type structure is disclosed. The electronic device includes a metal bracket and the antenna. The antenna includes a first metal ring surrounding the metal bracket, where the first metal ring has at least two sections separated by at least one gap. At least one section may operate as a radiator through radio frequency (RF) feeding at least at one portion thereof. A second metal ring may be electrically connected, at least at one point thereof, to a ground of the electronic device or to the first metal ring. At least one section of the first metal ring may operate as a monopole antenna, as a PIFA antenna, or as a loop antenna, via suitable feeding. |
| US09647319B2 |
Window assembly with transparent layer and an antenna element
A window assembly includes an electrically conductive transparent layer and an antenna element disposed on a substrate. The transparent layer has an area defining a periphery with a plurality of edges. An outer region devoid of the transparent layer is defined adjacent the transparent layer along the periphery. The antenna element includes a first antenna segment and a second antenna segment. The first antenna segment is elongated and disposed in the outer region and spaced from the periphery and extends solely along one edge of the periphery. The second antenna segment extends integrally from the first antenna segment towards the transparent layer such that the second antenna segment crosses a periphery of the transparent layer. A feeding element is coupled to the first antenna segment to energize the antenna element and the transparent layer such that the antenna element and the transparent layer collectively transmit and/or receive radio frequency signals. |
| US09647306B2 |
RF filter comprising N coaxial resonators arranged in a specified interdigitation pattern
Devices and methods related to multiple-pole ceramic resonator filters. In some embodiments, a radio-frequency (RF) filter can include a first coaxial resonator in a first orientation and having an input tab on a first side of the filter, and an N-th coaxial resonator in the first orientation and having an output tab on the first side of the filter. The RF filter can further include second and (N−1)th coaxial resonators, each in a second orientation opposite the first orientation to form first and second interdigitations with the first and N-th resonators, respectively. The RF filter can further include at least two coaxial resonators in the first orientation and coupled between the second and (N−1)th resonators. The N resonators can be slot coupled between the first and N-th resonators. The first and second interdigitations can be configured to provide enhancement of the slot coupling between the first and N-th resonators. |
| US09647303B2 |
Energy storage system preventing self from overheating, a method for preventing energy storage system from overheating and a method for forming a heat dissipation coating on energy storage system
The present invention discloses an overheat prevention energy storage system preventing self from overheating, comprising a heat dissipating external surface, wherein at least a portion of the external surface is coated with at least one layer of heat dissipation coating of high emissivity. The present invention further discloses a method for preventing overheat of the energy storage system and a method for forming at least one layer of heat dissipation coating of high emissivity onto at least part of an external surface of the energy storage system or assemblies thereof. |
| US09647302B2 |
Battery thermal system with a stacking frame
A battery pack assembly. Each assembly includes a battery cell and a cooling fin assembly positioned in thermal communication with the battery cell for thermal cooling thereof. The cooling fin assembly includes a generally planar cooling fin defining a compliant structure and at least one foot defining a flat surface along an edge of the cooling fin. A heat sink and a frame structure contain the battery cells and the cooling fin assemblies such that upon placement of the cooling fin assemblies and the battery cells in the frame structure, a substantial entirety of the flat surfaces of the feet of the cooling fin assemblies are aligned to define a generally planar surface with which to thermally engage the heat sink. A vehicle propulsion system having a battery pack assembly and methods of assembling a battery pack assembly is also described. |
| US09647299B2 |
Small form factor betavoltaic battery for medical implants
A betavoltaic power source. The power source comprises a source of beta particles, one or more regions for collecting the beta particles and for generating electron hole pairs responsive thereto, and a secondary power source charged by a current developed by the electron hole pairs. |
| US09647298B2 |
Nonaqueous electrolyte battery and electrical apparatus
A nonaqueous electrolyte battery is provided. The nonaqueous electrolyte battery includes an anode; a cathode; a separator; an electrolytic solution including a solvent and an electrolyte salt; wherein the solvent includes a fluoro ethylene carbonate, wherein the nonaqueous electrolyte battery has a discharge capacity ratio of a discharge capacity B when discharging at a 5 C rate to a discharge capacity A when discharging at a 0.2 C rate ((B/A)×100%), and wherein the discharge capacity ratio is 80% or more. An electrical apparatus including a nonaqueous electrolyte battery is also provided. |
| US09647296B2 |
Magnesium borohydride and its derivatives as magnesium ion transfer media
An anhydrous electrolyte for a magnesium battery. The anhydrous electrolyte includes a magnesium salt having the formula Mg(BH4)2. The electrolyte also includes a solvent, the magnesium salt dissociating in the solvent. Various solvents including aprotic solvents and molten salts such as ionic liquids may be utilized. The magnesium salt dissociates in the solvent to Mg electroactive species BH4− and Mg2+. |
| US09647295B2 |
Lithium ion secondary battery and electrolyte additive for the same
Provided is an electrolyte additive for a lithium ion secondary battery including an organic lithium compound and a hyper-branched structure material. The electrolyte additive enhances the decomposition voltage of the electrolyte up to 5.5 V, and increases the heat endurable temperature by 10° C. or more. The safety of the battery is thus improved. |
| US09647294B2 |
Non-aqueous electrolytic solution, electrochemical element using same, and alkynyl compound used therefor
The present invention provides an excellent nonaqueous electrolytic solution capable of improving low-temperature and high-temperature cycle properties and load characteristics after high-temperature charging storage, an electrochemical element using it, and an alkynyl compound used for it.The nonaqueous electrolytic solution of the present invention comprises containing at least one alkynyl compound represented by the following general formula (I) in an amount of from 0.01 to 10% by mass in the nonaqueous electrolytic solution. R1(O)n—X1—R2 (I) (In the formula, X1 represents a group —C(═O)—, a group —C(═O)—C(═O)—, a group —S(═O)2—, a group —P(═O) (—R3)—, or a group —X3—S(═O)2O—. R1 represents an alkenyl group, a formyl group, an alkyl group, an acyl group, an arylcarbonyl, an alkanesulfonyl group, an alkynyloxysulfonyl group, an arylsulfonyl group, a dialkylphosphoryl group, an alkyl(alkoxy)phosphoryl group, or a dialkoxyphosphoryl group; R2 represents an alkynyl group or an alkynyloxy group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an alkoxy group, an alkenyloxy group, an alkynyloxy group, or an aryloxy group; n indicates 0 or 1. |
| US09647284B2 |
Integration of molten carbonate fuel cells in Fischer-Tropsch synthesis
In various aspects, systems and methods are provided for integration of molten carbonate fuel cells with a Fischer-Tropsch synthesis process. The molten carbonate fuel cells can be integrated with a Fischer-Tropsch synthesis process in various manners, including providing synthesis gas for use in producing hydrocarbonaceous carbons. Additionally, integration of molten carbonate fuel cells with a Fischer-Tropsch synthesis process can facilitate further processing of vent streams or secondary product streams generated during the synthesis process. |
| US09647279B2 |
Systems and methods for mitigating carbon corrosion in a fuel cell system
System and methods for reducing carbon corrosion in a fuel cell system are presented. Particularly, the disclosed systems and methods may be utilized in connection with preventing the formation of a propagating H2-Air interface within the fuel cell system. In certain embodiments, the disclosed systems and methods may utilize an electrochemical pump disposed in a cathode loop of the fuel cell system configured to remove oxygen that intrudes into the fuel cell system. In further embodiments, pumps may be included in an anode and a cathode loop of the fuel cell system that may allow for circulation of certain gases to prevent the formation of an H2-Air front with the system. |
| US09647269B2 |
Electrode active material and secondary battery
In a secondary battery utilizing redox by a radical site, charge-discharge is carried out in such a manner that a lithium ion moves between a positive electrode and a negative electrode (rocking chair-type). An anion in an amount necessary for electrode doping during charge-discharge is made unnecessary, thereby reducing the amount of an electrolytic solution. A secondary battery with a large energy density is achieved. Provided is an electrode active material including at least one polymer including a radical site capable of being converted into a first cation, and an anion site capable of being bonded with the first cation or a second cation. |
| US09647268B2 |
Battery containing rubeanic acid or derivative thereof as active material
Provided is a battery having a high charging/discharging capacity density as compared with a conventional one. The battery (1) is characterized by comprising a positive electrode (2), a negative electrode (3), and an electrolytic solution interposed between the positive electrode (2) and the negative electrode (3) and formed by dissolving an electrolytic solution in a solvent, wherein the positive electrode (2) includes rubeanic acid or a rubeanic acid derivative as an active material and the solvent includes an ionic liquid. In the battery (1), it is possible to neutralize, by anions present in the ions, positive charges generated when rubeanic acid or the rubeanic acid derivative is oxidized. Therefore, rubeanic acid or the rubeanic acid derivative can take three states from an oxidant to a reductant, so that a high charging/discharging capacity density can be obtained in comparison with a conventional one. |
| US09647267B2 |
Rechargeable copper-zinc cell
A rechargeable cell comprising h combination a bipolar electrode, a zinc electrolyte, a copper electrolyte and metal-ion impermeable, polymer electrochemical membrane separator, wherein the zinc electrolyte and the copper electrolyte are separated from each other by the bipolar electrode on one side and by the membrane separator on the other side. A battery comprising at least one said rechargeable cell. |
| US09647264B2 |
Nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery capable of achieving a high battery performance (e.g., high energy density and high power density) is provided. The nonaqueous electrolyte secondary battery is equipped with a positive electrode having a positive electrode current collector and a positive electrode active material layer that is formed on the positive electrode current collector and includes at least a positive electrode active material and a conductive material. The positive electrode active material includes a lithium-transition metal composite oxide. The conductive material includes a lithium phosphate compound coated, on at least part of the surface thereof, with a conductive carbon, and a proportion of the conductive material in the positive electrode active material layer is 10% by mass or less. |
| US09647260B2 |
Method of manufacturing anode for thermally activated reserve battery using thin metal foam and cup
Disclosed is a method of manufacturing an anode for a thermally activated reserve battery using a thin metal foam and a cup, which includes rolling a metal foam, coating the metal foam with a molten eutectic salt, impregnating the metal foam with lithium, and providing the metal foam with an electrode cup and a conductive separation membrane, and in which lithium having excellent capacity and output characteristics is employed in an anode for a thermal battery operating at high temperature. |
| US09647257B2 |
Battery pack
A battery pack is disclosed. In one aspect, the battery pack includes a plurality of battery cells and a monitoring portion including a plurality of lines respectively electrically connected to the battery cells. The lines include a positive current line, a negative current line, and at least one monitoring line. The battery pack further includes a connector including a plurality of connector pins formed therein, wherein the connector pins are respectively electrically connected to the lines of the monitoring portion, and a protective circuit module accommodating the connector therein. The connector pins have different lengths. |
| US09647255B2 |
Porous separation membrane, secondary battery using same, and method for manufacturing said secondary battery
Provides are a porous separator that prevents a short-circuit between two electrodes by using a porous nanofiber web where nanofibers have a core-shell structure, to thereby promote safety and thinning simultaneously. The porous separator includes: a porous nonwoven fabric playing a support role and having micropores; and a porous nanofiber web that is laminated on one side of the porous nonwoven fabric, and plays a role of an adhesive layer and an ion-containing layer when the porous nanofiber web is in close contact with an opposed electrode, wherein a portion of the porous nanofiber web is incorporated in a surface layer of the porous nonwoven fabric, to thus partially block pores of the porous nonwoven fabric and to thereby lower porosity of the porous nonwoven fabric. The porous nanofiber web has nanofibers obtained by spinning a mixture of a swellable polymer and a non-swellable polymer to have a core-shell structure. |
| US09647253B2 |
Methods of producing and using microporous membranes
A method of producing microporous membranes includes stretching a multi-layer layer extrudate having first and second layers, the first layer including a first polyolefin and a first diluent, and the second layer including a second polyolefin and a second diluent, the second polyolefin including polypropylene in an amount of 1.0 wt. % to 40.0 wt. %, the polypropylene having an Mw>0.9×106 and a ΔHm≧100.0 J/g; removing at least a portion of the diluents to produce a dried membrane having a first length and a first width; stretching the membrane by a first magnification factor of 1.1 to 1.5 and stretching the membrane by a second magnification factor of 1.1 to 1.3; and reducing the width. |
| US09647250B2 |
Energy storage arrangement
An energy storage arrangement for supplying electric power, in particular in a motor vehicle, includes at least a first energy storage module and a second energy storage module mounted on top of the first energy storage module. Each energy storage module has two end plates and a plurality of storage cells tensioned between the end plates. At least one end plate of the first energy storage module is secured by at least one first screw, and at least one end plate of the second energy storage module is secured by at least one second screw. An internal thread is formed in the screw head of the first screw, and the second screw is screwed into the screw head of the first screw. |
| US09647247B2 |
Encasement for a battery cell and for a battery system, process for producing said encasement, battery cell and battery system
An encasement (20) for a battery cell (2) and for a battery system (1) wherein said encasement is in the form of a sheet and comprises a core layer (22). This core layer (22) comprises carbon nanotubes. The invention further relates to a process for producing an encasement (20) which comprises initially coating a polymer substrate with an oxide material and applying carbon nanotubes to an oxide layer thus formed. |
| US09647246B2 |
Battery
A battery includes: a cylindrical battery case; and an electrode body disposed in the battery case, and including a positive plate, a negative plate, and a separator disposed between the positive plate and the negative plate. A spacer formed of a dense body and an electrolyte storage space storing an electrolyte are provided between the electrode body and the battery case on one end or both ends of the battery case in an axial direction of the electrode body. |
| US09647243B2 |
Display apparatus and method of manufacturing the same
A display apparatus includes a pixel part disposed in a display area of a base substrate, including a switching element connected to a signal line, a pixel electrode connected to the switching element and a common electrode that overlaps the pixel electrode, a plurality of fan-out lines disposed in a peripheral area of the base substrate that are connected to the signal line of the display area, a plurality of pads disposed in the peripheral area of the base substrate that are respectively connected to end portions of the fan-out lines, an organic layer that covers the switching element of the display area and that extends from the display area to a portion of the fan-out lines, and an electrode pattern that overlaps the fan-out lines in a boundary portion of the organic layer. |
| US09647241B2 |
Organic light emitting diode display having multi-layer stack structure
An organic light-emitting diode (OLED) display comprises, an anode electrode disposed over a substrate; a cathode electrode disposed opposite the anode electrode; a charge generation layer disposed between the anode electrode and the cathode electrode; a first stack disposed between the charge generation layer and the cathode electrode and configured to comprise a first organic light-emitting layer, a first common layer disposed over the first organic light-emitting layer, and a second common layer disposed under the first organic light-emitting layer; and a second stack disposed between the charge generation layer and the anode electrode, wherein at least one of the first common layer and the second common layer covers a sidewall of the charge generation layer. |
| US09647240B2 |
Light emitting apparatus
An illuminator includes a light-emitting element and a light extraction sheet which transmits light occurring from the light-emitting element. The light-emitting element includes a first electrode having a light transmitting property, a second electrode, and an emission layer between the first and second electrodes. The light extraction sheet includes a light-transmitting substrate having a first face and a second face, a first light extraction structure on the first face side of the light-transmitting substrate, and a second light extraction structure on the second face side of the light-transmitting substrate. The first light extraction structure includes a low-refractive index layer and a high-refractive index layer having a higher refractive index than the low-refractive index layer. The second light extraction structure is arranged so that light which is transmitted through the light-transmitting substrate and arrives at an incident angle of 60 to 80 degrees has an average transmittance of 20% or more. |
| US09647236B2 |
Packaging method of organic light emitting display panel, organic light emitting display panel and display device
A packaging method for an organic light emitting display panel, an organic light emitting display panel and a display device are disclosed. The packaging method includes: forming a water/oxygen blocking layer that covers a whole base substrate on the base substrate with an organic light emitting device and a peripheral bonding region formed thereon, etching the water/oxygen blocking layer on the base substrate, so as to at least remove the water/oxygen blocking layer on a connection terminal within the bonding region, and to retain the water/oxygen blocking layer on the organic light emitting device. With the packaging method, an organic light emitting display panel with a narrow frame can be realized. |
| US09647234B2 |
Organic light-emitting diode display and manufacturing method thereof
An organic light-emitting diode (OLED) display and a manufacturing method thereof are disclosed. One inventive aspect includes a first substrate, a second substrate, and a first insulation layer, a metal layer and a second insulation layer formed on the first insulation layer. The metal layer is formed on the first insulating layer and has a first through hole. The second insulation layer is formed on the metal layer and has a second through hole. |
| US09647228B2 |
Light-emitting element and light-emitting device
Provided are a light-emitting element capable of reducing power consumption by increasing its light extraction efficiency and a light-emitting device using the light-emitting element. A light-emitting element includes a composite material, which contains an organic compound having a high hole-transport property and an electron acceptor and in which the spin density measured by an electron spin resonance (ESR) method is less than or equal to 1×1019 spins/cm3, the spin density is less than or equal to 3×1019 spins/cm3 when the molar ratio of the electron acceptor to the organic compound is greater than or equal to 1, or the spin density is less than or equal to 5×1019 spins/cm3 when the molar ratio is greater than or equal to 2. |
| US09647226B2 |
Organic electroluminescent element
An organic electroluminescence device according of the invention includes an anode, a cathode, and at least a first emitting layer and a second emitting layer interposed between the anode and the cathode. The first emitting layer includes a first host material and a first dopant material. The second emitting layer includes a second host material, a third host material and a second dopant material. |
| US09647223B2 |
Single layer nanocomposite photoresponse device
A photoresponse device comprising a nanocomposite photoactive material is provided. The photoactive layer comprises a nanocomposite material of metal oxide nanoparticles dispersed within a photosensitizing organic semiconductor formed on a substrate. Methods of characterizing the nanocomposites are provided and demonstrate commercially relevant electrical and photodetection properties, particularly the ability to operate as a photodiode, photoconductor or photocapacitor. An economical process for preparing the nanocomposite and the photoresponse device is also provided as well as applications. |
| US09647218B2 |
Organic electroluminescent materials and devices
A compound having the structure of Formula 1, as well as, a first device and a formulation including the same are disclosed. In the structure of Formula 1: R5 is and (a) at least one of R1-R4 is or (b) R1 is In addition, R1, R2, R3, R4, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Z1, Z2, Z3, Z4, Z5, Z6, Z7, and Z8, are each independently selected from a variety of substituents, where adjacent A, B, Y, and Z groups are, optionally, joined to form a fused ring structure. Finally, X includes an acceptor group selected from —CmF2m+1, —SimF2m+1, —NCO, —NCS, —OCN, —SCN, —OCmF2m+1, and —SCmF2m+1. |
| US09647214B2 |
Organic electroluminescent element, compound for organic electroluminescent element, and light-emitting device, display device, and illumination device using said element
An organic electroluminescent element using a compound represented by the following general formula (I) emits dark blue light and has a high effect of inhibition of voltage during high-luminance driving: wherein R1 to R6; E1 and E2; X1 and X2; and A1 to A8 are as defined herein. |
| US09647209B2 |
Integrated phase change switch
Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer. |
| US09647204B2 |
Spin torque MRAM based on Co, Ir synthetic antiferromagnetic multilayer
Magnetic memory devices having an antiferromagnetic reference layer based on Co and Ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple Co-containing layers oriented in a stack, wherein adjacent Co-containing layers in the stack are separated by an Ir-containing layer such that the adjacent Co-containing layers in the stack are anti-parallel coupled by the Ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer. A method of writing data to a magnetic random access memory device having at least one of the present magnetic memory cells is also provided. |
| US09647200B1 |
Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material
Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material. |
| US09647195B2 |
Multi-frequency ultra wide bandwidth transducer
Piezoelectric micromachined ultrasonic transducer (pMUT) arrays and techniques for frequency shaping in pMUT arrays are described, for example to achieve both high frequency and low frequency operation in a same device. The ability to operate at both high and low frequencies may be tuned during use of the device to adaptively adjust for optimal resolution at a particular penetration depth of interest. In embodiments, various sizes of piezoelectric membranes are fabricated for tuning resonance frequency across the membranes. The variously sized piezoelectric membranes are lumped together by two or more separate electrode rails, enabling independent addressing between the two or more subgroups of sized transducer elements. Signal processing of the drive and/or response signals generated and/or received from each of the two or more electrode rails may achieve a variety of operative modes for the device, such as a near field mode, a far field mode, and an ultra wide bandwidth mode. |
| US09647194B1 |
Superconductive multi-chip module for high speed digital circuits
An electrical module having electrically interconnecting substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures. |
| US09647193B2 |
Thermoelectric conversion element and thermoelectric conversion device
[Object] To increase the degree of freedom in designing a system for taking out power from a temperature gradient in terms of a thermoelectric conversion element or a thermoelectric conversion device.[Means for Achieving Object] A thermal spin-wave spin current generating member made of a magneto-dielectric body is provided with an inverse spin Hall effect member, a temperature gradient is provided in the above-described thermal spin-wave spin current generating member in the direction of the thickness, and at the same time a magnetic field is applied to the above-described inverse spin Hall effect member in the direction perpendicular to the longitudinal direction and perpendicular to the direction of the above-described temperature gradient by means of a magnetic field applying means so that a thermal spin-wave spin current is converted to a voltage which is taken out in the above-described inverse spin Hall effect member. |
| US09647191B2 |
Method for thermal energy-to-electrical energy conversion
An improved method and apparatus for thermal-to-electric conversion involving relatively hot and cold juxtaposed surfaces separated by a small vacuum gap wherein the cold surface provides an array of single charge carrier converter elements along the surface and the hot surface transfers excitation energy to the opposing cold surface across the gap through Coulomb electrostatic coupling interaction. |
| US09647187B1 |
Multi-slice two-dimensional phased array assembly
A two-dimensional phased array beam former comprising at least first and second chips having each top and bottom surfaces, the bottom surface of the first chip being attached to the top surface of the second chip; the first and second chips having each an emitter side surface, the emitter side surfaces of the first and second chips facing a same direction and comprising each a plurality of emitters; wherein each of said first and second chips comprises at least one conductive post extending between said top and bottom surfaces; the at least one conductive post of the first chip being vertically aligned with and connected to the at least one conductive post of the second chip. |
| US09647181B2 |
Light emitting device with phosphors
Provided is a light emitting device in which with the general color rendering index Ra and the special color rendering index R9 maintained at high numeric values, the light emission efficiency is prevented from being reduced as much as possible, and the high color rendering and the high efficiency are achieved so as to be usable for general lighting usage. The device includes at least one light emitting element 6 emitting a light having a peak emission wavelength in a near-ultraviolet to blue region, and a phosphor layer 5 containing a green phosphor excited by a primary light emitted from the light emitting element 6 and emitting a light having a peak emission wavelength in a green region, a first red phosphor excited by the primary light and emitting a light having a peak emission wavelength in a red region, and a second red phosphor exited by the primary light and emitting a light having a peak emission wavelength different from that of the first red phosphor in the red region. |
| US09647178B2 |
Package structure of optical module having printed shielding layer and its method for packaging
A package structure of an optical module includes: a substrate having a frame defined with a light-emitting region and a light-admitting region; a light-emitting chip disposed at the light-emitting region of the substrate; a light-admitting chip disposed at the light-admitting region of the substrate; two encapsulants formed in the frame and enclosing the light-emitting chip and the light-admitting chip, respectively; and a shielding layer formed on the frame and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively. The optical module package structure uses an opaque glue to reduce costs and total thickness of the package structure. |
| US09647176B2 |
Reflective display devices
A technique of producing a control component for a reflective display device, comprising: forming an array of electronic switching devices; forming over said array of electronic switching devices an insulator region defining a controlled surface topography; and forming on the patterned surface of the insulator region by a conformal deposition technique a substantially planar array of reflective pixel conductors each independently controllable via a respective one of the array of electronic switching devices, wherein each pixel conductor exhibits specular reflection at a range of reflection angles relative to the plane of the array of pixel conductors for a given incident angle relative to the plane of the array of pixel conductors. |
| US09647170B2 |
Method for producing group III nitride semiconductor light-emitting device
The present techniques provide a method for producing a Group III nitride semiconductor light-emitting device, with suppression of an increase in polarity inversion defect density. The production method includes an n-type semiconductor layer formation step, a light-emitting layer formation step, and a p-type semiconductor layer formation step. The p-type semiconductor layer formation step includes a p-type cladding layer formation step. The p-type cladding layer formation step includes a first p-type semiconductor layer formation step for forming a p-type AlGaN layer, a first semiconductor layer growth intermission step after the first p-type semiconductor layer formation step, and a p-type InGaN layer formation step after the first semiconductor layer growth intermission step. In the first semiconductor layer growth intermission step, a mixture of nitrogen gas and hydrogen gas is supplied to the substrate. |
| US09647164B2 |
Single-band and dual-band infrared detectors
Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed. |
| US09647162B2 |
Electronic power cell memory back-up battery
An electronic power cell memory back-up battery is disclosed. The electronic power cell memory back-up battery utilizes stored light photons to produce usable energy, and can be used to replace batteries or other power sources in electronic devices. The electronic power cell memory back-up battery disclosed includes a light source and a photovoltaic device in optical communication with the light source. The photovoltaic device creates electrical power in response to receiving light from the light source. A portion of the electrical power generated by the photovoltaic device is used to power the light source. In some embodiments power input contacts are included for use in providing initial start-up power to the light source. In some embodiments the light source comprises a light-emitting device and a photoluminescent material optically coupled to the light-emitting device, where the photoluminescent material emits light in response to receiving light from the light-emitting device. |
| US09647161B2 |
Method of manufacturing a device comprising an integrated circuit and photovoltaic cells
According to one embodiment, the present invention relates to a method for manufacturing a photovoltaic device comprising a photovoltaic cell or a plurality of photovoltaic cells (PV cells) connected to an electronic integrated circuit having at least one electrical contact area. A stack comprising the PV cell(s) is produced separately from the electronic integrated circuit, the electronic integrated circuit is then transferred to said stack comprising the PV cell(s). During this transfer, connection areas carried by the PV cell(s) are brought into contact with matching connection areas carried by the electronic integrated circuit. |
| US09647160B2 |
Adhesives for attaching wire network to photovoltaic cells
Provided are novel methods of fabricating photovoltaic modules using pressure sensitive adhesives (PSA) to secure wire networks of interconnect assemblies to one or both surfaces of photovoltaic cells. A PSA having suitable characteristics is provided near the interface between the wire network and the cell's surface. It may be provided together as part of the interconnect assembly or as a separate component. The interconnect assembly may also include a liner, which may remain as a part of the module or may be removed later. The PSA may be distributed in a void-free manner by applying some heat and/or pressure. The PSA may then be cured by, for example, exposing it to UV radiation to increase its mechanical stability at high temperatures, in particular at a, for example the maximum, operating temperature of the photovoltaic module. For example, the modulus of the PSA may be substantially increased during this curing operation. |
| US09647154B2 |
Ordered superstructures of octapod-shaped nanocrystals, their process of fabrication and use thereof
This invention relates to the controlled realization of ordered superstructures of octapod-shaped colloidal nanocrystals, formed either in the liquid phase or on a solid substrate. These structures can be applied in many fields of technology. |
| US09647151B2 |
Checking the stoichiometry of I-III-VI layers for use in photovoltaic using improved electrolysis conditions
The invention relates to manufacturing a I-III-VI compound in the form of a thin film for use in photovoltaics, including the steps of: a) electrodepositing a thin-film structure, consisting of I and/or III elements, onto the surface of an electrode that forms a substrate (SUB); and b) incorporating at least one VI element into the structure so as to obtain the I-III-VI compound. According to the invention, the electrodeposition step comprises checking that the uniformity of the thickness of the thin film varies by no more than 3% over the entire surface of the substrate receiving the deposition. |
| US09647150B2 |
Monolithic integration of plenoptic lenses on photosensor substrates
A monolithic integration of a plenoptic structure on an image sensor is provided using material with low refractive index on the substrate of photosensors and arranging material with a high refractive index on the material with low refractive index to create the plenoptic microlenses. Plenoptic lenses are created directly on the substrate of photosensors. Photosensors with a high integration density are arranged at minimum distances to minimize inter-pixel interferences and on the integration density end having “deformed square” geometries on the vertices adjacent to a pixel of the same color, removing any photosensitive area from the vertices. The light efficiency is increased by structures of plenoptic microlenses at variable distances from the substrate, with more asymmetric profiles on the periphery, or pixels of different sizes and shapes towards the periphery of the sensor. Micro-objectives are produced by the creation of alternate layers of low and high refractive index. |
| US09647147B2 |
Solar battery cell and production method thereof
A solar battery cell, including semiconductor substrate, an insulating film formed on one face side of the semiconductor substrate, and an electrode electrically connected to the one face side of the semiconductor substrate, the electrode being embedded in a groove that is provided on the insulating film and provided so as to protrude from a surface of the insulating film by a same width as the groove. |
| US09647145B1 |
Method, apparatus, and system for increasing junction electric field of high current diode
Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin. |
| US09647144B2 |
Integrated magnetic field sensor and method for a measurement of the position of a ferromagnetic workpiece with an integrated magnetic field sensor
An integrated magnetic field sensor, having a semiconductor body with a surface and a rear surface, and a metal carrier, with a front and a rear, wherein the rear of the semiconductor body is connected to the front of the metal carrier in a non-positive manner, and a Hall sensor, embodied on the surface of the semiconductor body, with a main extension surface, and a magnet with a first magnetic pole embodied along a first surface, which first magnetic pole has a central axis embodied in a perpendicular manner on the first surface, wherein the metal carrier, the magnet and the semiconductor body are arranged in a common housing and precisely one or at least one Hall sensor is arranged in the housing. |
| US09647141B2 |
Thin film transistor and method of manufacturing the same
Embodiments of the present disclosure provide a thin film transistor (TFT) and a method of manufacturing the same, which enables to decrease the vertical resistance from the source and the drain to the polarity inversion region, so that the current from the source and the drain to the polarity inversion region may be increased, thereby improving the performances of the TFT. An active layer of the TFT is provided with a first groove and a second groove which neither pass through the active layer. A source and a drain of the TFT are formed at least partially in the first groove and the second groove, respectively. The source and the drain contact the active layer through the first groove and the second groove, respectively. |
| US09647140B2 |
Thin film transistor
A thin film transistor disposed on a substrate, includes a gate, a gate insulation layer, a first source/drain, a semiconductor layer and a second source/drain. The gate is disposed on the substrate. The gate insulation layer covers the gate and the substrate. The first source/drain is disposed on the gate insulation layer. The semiconductor layer is disposed above the gate, extends from the gate insulation layer to the first source/drain, and includes a first portion disposed on the first source/drain and a second portion connected to the first portion. An electrical conductivity of the first portion is higher than that of the second portion. The second source/drain covers and is in contact with the second portion. A manufacturing method of thin film transistor is further provided. |
| US09647137B2 |
Oxide semiconductor, thin film transistor, and display device
An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor. |
| US09647136B2 |
Thin film transistor, thin film transistor panel, and method for manufacturing the same
A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode. |
| US09647135B2 |
Tin based p-type oxide semiconductor and thin film transistor applications
This disclosure provides p-type metal oxide semiconductor thin films that display good thin film transistor (TFT) characteristics. The p-type metal oxide thin films include ternary or higher order tin-based (Sn-based) p-type oxides such as Sn (II)-M-O oxides where M is a metal. In some implementations, M is a metal selected from the d block or the p block of the periodic table. The oxides disclosed herein exhibit p-type conduction and wide bandgaps. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. In some implementations, the p-channel TFTs have low off-currents. |
| US09647131B2 |
Semiconductor device, power circuit, and manufacturing method of semiconductor device
The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer. |
| US09647129B2 |
Semiconductor device
To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion. |
| US09647126B2 |
Oxide for semiconductor layer in thin film transistor, thin film transistor, display device, and sputtering target
Provided is an oxide semiconductor configured to be used in a thin film transistor having high field-effect mobility; a small shift in threshold voltages against light and bias stress; excellent stress resistance. The oxide semiconductor has also excellent resistance to a wet-etchant for patterning of a source-drain electrode. The oxide semiconductor comprises In, Zn, Ga, Sn and O, and satisfies the requirements represented by expressions (1) to (4) shown below, wherein [In], [Zn], [Ga], and [Sn] represent content (in atomic %) of each of the elements relative to the total content of all the metal elements other than oxygen in the oxide. (1.67×[Zn]+1.67×[Ga])≧100 (1) {([Zn]/0.95)+([Sn]/0.40)+([In]/0.4)}≧100 (2) [In]≦40 (3) [Sn]≧5 (4) |
| US09647123B1 |
Self-aligned sigma extension regions for vertical transistors
A semiconductor structure including vertical transistors is provided in which a sigma shaped source/drain extension region is formed between a top faceted surface of a first region of an epitaxial semiconductor channel material and a bottom faceted surface of a second region of the epitaxial semiconductor channel material. The sigma shaped source/drain extension region is formed after formation of a functional gate structure on each side of an epitaxial semiconductor channel material by first removing a sacrificial bottom spacer layer of a bottom spacer material stack, performing a sigma etch on an exposed lower portion of the epitaxial semiconductor channel material to provide the first region of epitaxial semiconductor channel material and the second region of the epitaxial semiconductor channel material, and then epitaxially growing the sigma shaped source/drain extension region from the faceted surfaces of the first and second regions of epitaxial semiconductor channel material. |
| US09647122B2 |
Semiconductor device and method of forming the same
A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location. |
| US09647120B1 |
Vertical FET symmetric and asymmetric source/drain formation
A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions. |
| US09647117B2 |
Apparatus and method for forming semiconductor contacts
A method comprises forming a fin structure over a substrate, wherein the fin structure comprises a channel connected between a drain region and a source region, depositing a semiconductor layer in an amorphous state over the drain region and the source region at a first temperature and performing a solid phase epitaxial regrowth process on the semiconductor layer at a second temperature, wherein the second temperature is higher than the first temperature. |
| US09647111B2 |
Advanced forming method and structure of local mechanical strained transistor
Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer. |
| US09647108B2 |
Silicon carbide semiconductor device
A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer. |
| US09647107B1 |
Fabrication method for forming vertical transistor on hemispherical or polygonal patterned semiconductor substrate
A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface. |
| US09647106B2 |
Silicon carbide semiconductor device and method for manufacturing same
A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate interconnection. The silicon carbide substrate includes: a first impurity region; a second impurity region provided on the first impurity region; and a third impurity region provided on the second impurity region so as to be separated from the first impurity region. A trench has a side portion and a bottom portion, the side portion extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region. When viewed in across section, the interlayer insulating film extends from above the third impurity region to above the gate electrode so as to cover the corner portion. |
| US09647103B2 |
Semiconductor device with modulated field element isolated from gate electrode
The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance. |
| US09647099B2 |
Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base
A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base. |
| US09647097B2 |
Vertical tunnel field effect transistor (FET)
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET. |
| US09647094B2 |
Method of manufacturing a semiconductor heteroepitaxy structure
A method of manufacturing a semiconductor structure includes the steps of depositing a layer of semiconductor oxide on a base semiconductor layer, scavenging oxygen from the layer of semiconductor oxide and recrystallizing the oxygen scavenged layer of semiconductor oxide as a semiconductor heteroepitaxy layer. |
| US09647091B2 |
Annealed metal source drain overlapping the gate
A method of forming a field effect transistor is provided. The method of forming a field effect transistor may include forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered, depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region, and forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate. |
| US09647090B2 |
Surface passivation for germanium-based semiconductor structure
The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin. |
| US09647089B2 |
Thin film transistor substrate, display apparatus including the same, method of manufacturing thin film transistor substrate, and method of manufacturing display apparatus
Thin film transistor substrate includes: a substrate; a crystalline silicon layer on the substrate; and a capping layer covering the crystalline silicon layer and including a first portion having a first thickness and a second portion having a second thickness that is greater than the first thickness. |
| US09647087B2 |
Doped protection layer for contact formation
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening. |
| US09647086B2 |
Early PTS with buffer for channel doping control
A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers. |
| US09647081B2 |
Method for manufacturing silicon carbide semiconductor device
A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided. |
| US09647079B2 |
Thin film transistor array panel and manufacturing method thereof
Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor. |
| US09647076B2 |
Circuit including semiconductor device with multiple individually biased space-charge control electrodes
A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal. |
| US09647075B2 |
Segmented field plate structure
A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate. |
| US09647074B2 |
Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium layer is heat-treated
A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm−3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm−3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases. |
| US09647071B2 |
FINFET structures and methods of forming the same
FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer. |
| US09647070B2 |
Semiconductor devices with graded dopant regions
Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications. |
| US09647069B2 |
Drain extended field effect transistors and methods of formation thereof
In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. |
| US09647068B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region. The undoped channel region, base dopant region, and threshold voltage setting region are disposed within the semiconductor substrate layer. The undoped channel region is disposed between the source electrode and the drain electrode, and the base dopant region and the threshold voltage setting region extend beneath the source electrode and the drain electrode. The threshold voltage setting region is disposed between the undoped channel region and the base dopant region. |
| US09647063B2 |
Nanoscale chemical templating with oxygen reactive materials
A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing. |
| US09647058B2 |
Diode
A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q≦0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking. |
| US09647056B2 |
Semiconductor devices including a support for an electrode and methods of forming semiconductor devices including a support for an electrode
Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes. |
| US09647054B2 |
Inductor system and method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed. |
| US09647050B2 |
Flexible circuit film and display apparatus having the same
A flexible circuit film includes a first flexible film, a second flexible film facing the first flexible film, a plurality of wirings arranged between the first flexible film and the second flexible film and extending in a first direction, then bending to extend in a second direction crossing the first direction, and then bending a second time to extend in an opposing direction to the first direction, and a guide film including a material more rigid than the first and second flexible films and arranged on an ends of the first flexible film. The guide film includes a tear-preventing portion overlapping with a bending portion of a shortest one of the wirings while covering portions of an inner edge near inner corners of a U-shaped flexible circuit film. |
| US09647045B2 |
Transparent display substrates, transparent display devices and methods of manufacturing transparent display devices
A transparent display substrate, a transparent display device, and a method of manufacturing a transparent display device, the substrate including a base substrate including a pixel area and a transmission area; a pixel circuit on the pixel area of the base substrate; an insulation layer covering the pixel circuit on the base substrate; a pixel electrode selectively disposed on the pixel area of the base substrate, the pixel electrode being electrically connected to the pixel circuit at least partially through the insulation layer; and a transmitting layer structure selectively disposed on the transmission area of the base substrate, the transmitting layer structure including at least an inorganic material, the inorganic material consisting essentially of silicon oxynitride. |
| US09647040B2 |
Touch display device and manufacturing method thereof
The present invention discloses a touch display device and a manufacturing method thereof, the display device comprising: an OLED display layer disposed on a lower substrate; an upper substrate; an air layer formed between the upper substrate and the lower substrate; and a touch module, disposed above the OLED display layer, wherein the touch module comprises: a first sensing circuit layer and a second sensing circuit layer, further wherein the first sensing circuit layer and the second sensing circuit layer are spaced and the distance between them is more than 2 μm. The display device can reduce interference in detection circuit caused by coupling capacitance formed between the sensing circuit layers thereby improving accuracy of touch detection. |
| US09647039B1 |
Array substrate, display panel, display device, and fabrication method thereof
An array substrate includes a plurality of first pixel-unit columns and a plurality of second pixel-unit columns repeatedly alternating with each other along a first direction. The first pixel-unit column includes a plurality of first pixel-unit groups and a plurality of second pixel-unit groups repeatedly alternating with each other along a second direction. The second pixel-unit column includes a plurality of third pixel-unit groups and a plurality of fourth pixel-unit groups repeatedly alternating with each other along the second direction. Each of the first pixel-unit group, the second pixel-unit group, the third pixel-unit group, and the fourth pixel-unit group includes a plurality of sub-pixels arranged into a matrix. The first pixel-unit group and the second pixel-unit group have same quantities of rows and columns in one matrix. The third pixel-unit group and the fourth pixel-unit group have same quantities of rows and columns in one matrix. |
| US09647038B2 |
Solid-state imaging device and method of manufacturing the same
A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion. |
| US09647035B2 |
Non-volatile resistive random access memory crossbar devices with maximized memory element density and methods of forming the same
Non-volatile resistive random access memory crossbar devices and methods of fabricating the same are provided herein. In an embodiment, a non-volatile resistive random access memory crossbar device includes a crossbar array including a bitline and a wordline. A hardmask that includes dielectric material is disposed over the bitline. The hardmask and the bitline include a first sidewall. A memory element layer and a selector layer are disposed in overlying relationship on the first sidewall of the bitline and hardmask. The memory element layer and a selector layer are further disposed between the bitline and the wordline, to form a first memory element and selector pair. |
| US09647030B2 |
Horizontal magnetic memory device using in-plane current and electric field
Provided is a magnetic memory device for applying an in-plane current to a conductive wire adjacent to a free magnetic layer having an in-plane magnetic anisotropy to induce a flux reversal of the free magnetic layer and simultaneously applying a voltage to each magnetic tunnel junction cell selectively to reverse magnetization of the free magnetic layer selectively at each specific voltage. The magnetic memory device may implement high density integration by reducing a volume since a spin-hall spin-torque causing a flux reversal is generated at an interface of the conductive wire and the free magnetic layer, ensure thermal stability by enhancing perpendicular magnetic anisotropy of the magnetic layer, and reduce a critical current density by increasing an amount of spin current. In addition, by increasing tunnel magnetic resistance with a thick insulating body, the magnetic memory device may increase a reading rate without badly affecting the critical current density. |
| US09647025B2 |
Solid-state imaging device, method of manufacturing the same, and electronic apparatus
A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged. |
| US09647024B2 |
Solid state imaging device and electronic apparatus
A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit. |
| US09647023B2 |
Image pickup device and method of manufacturing the same
A P-type well is defined by an isolation region formed in a semiconductor substrate. A pixel region and a ground region are defined in the P-type well. In the pixel region, a pixel transistor region and a photodiode region having a photodiode formed therein are defined. An antireflection film is formed so as to cover at least the photodiode region and the ground region. A plug connected to the ground region is formed so as to extend through the antireflection film and the like. |
| US09647021B2 |
Semiconductor device manufacturing method
A first waveguide member is formed, as viewed from above, in an image pickup region and a peripheral region of a semiconductor substrate. A part of the first waveguide member, which part is disposed in the peripheral region, is removed. A flattening step is then performed to flatten a surface of the first waveguide member on the side opposite to the semiconductor substrate. |
| US09647018B2 |
Imaging device including an intermediate electrode between first and second pixel electrodes and in contact with a photoelectric conversion film
An imaging device includes a first pixel electrode, a second pixel electrode adjacent to the first pixel electrode, and a photoelectric conversion film continuously covering the first pixel electrode and the second pixel electrode, in which an insulating film is provided between the first pixel electrode and the photoelectric conversion film, and between the second pixel electrode and the photoelectric conversion film, and an intermediate electrode is provided in a position between the first pixel electrode and the second pixel electrode, the intermediate electrode being in contact with a surface of the photoelectric conversion film, the surface being on a side where the first and second pixel electrodes are arranged. |
| US09647016B2 |
CMOS image sensors including vertical transistor
Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate. |
| US09647015B2 |
Method for manufacturing array substrate and array substrate manufactured therefor
A method for manufacturing an array substrate is disclosed and includes steps of: sequentially forming a first metal layer, an insulating layer and a second metal layer on a glass substrate; forming a passivation layer on the second metal layer; performing a first etching process on the passivation layer to obtain a first groove and a second groove; performing a second etching process on the passivation layer to obtain a third groove; and forming a pixel electrode layer on the passivation layer. The method saves one photomask and a photolithography step, thereby reducing the cost and improving the efficiency. |
| US09647014B2 |
Complementary thin film transistor driving back plate and preparing method thereof, and display device
A complementary thin film transistor driving back plate and a preparing method thereof, and a display device are disclosed. The preparing method comprises: forming a lower electrode (102) on a base substrate (101); sequentially disposing a continuously grown dielectric layer (103), a semiconductor layer (104), and a diffusion protection layer (105); sequentially forming a no-photoresist region (107), an N-type thin film transistor preparation region (108), and a P-type thin film transistor preparation region (109); removing a photoresist layer (114) of the N-type thin film transistor preparation region (108); removing a diffusion protection layer (105) of the N-type thin film transistor preparation region (105); removing a photoresist layer (114) of the P-type thin film transistor preparation region (109); performing an oxidation treatment to the base substrate (101); disposing a passivation layer (111) on the base substrate (101); and forming an upper electrode (113) on the passivation layer (111). |
| US09647010B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor. |
| US09647008B2 |
Method of forming contact structure in array substrate
The present application discloses a method of fabricating an array substrate comprising forming a via extending through a first insulating layer and a second insulating layer, the via comprising a first sub-via in the first insulating layer and the second sub-via in a second insulating layer; mobilizing a portion of first insulating layer material surrounding the first sub-via; and distributing the mobilized portion of the first insulating layer material over a sidewall of the second sub-via. |
| US09647004B2 |
Display
A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate. |
| US09647003B2 |
Display device
A display device includes a display panel including gate lines and data lines, the gate lines and the data lines intersecting, and pixels defined at the intersections of the gate lines and data lines, a gate driver to sequentially output a gate driving signal to the gate lines, a data driver to sequentially output a data signal to channels, a switching controller to electrically connect one of the channels with two or more of the data lines, the switching controller including a switch for each of the channels, wherein the two or more data lines are adjacent, one is directly connected to the channel and the other is connected to the channel through the switch, and a timing controller to provide a selection signal to the switch which controls the connection between the other of the two or more data lines and the channel. |
| US09646994B2 |
Semiconductor devices and manufacturing methods thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET. |
| US09646989B1 |
Three-dimensional memory device
According to one embodiment, the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of the electrode layers. The plurality of second columnar parts extend in the stacking direction in the second stacked part, and include a plurality of second semiconductor bodies being different in length in the stacking direction. |
| US09646988B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces. |
| US09646987B2 |
Semiconductor memory device and production method thereof
A semiconductor memory device according to an embodiment comprises a memory cell array including a stacked body and a semiconductor film, the stacked body including first layers stacked in a third direction, the semiconductor film having a side surface facing the first layers, and the semiconductor film extending in the third direction. The stacked body has a first portion and a second portion, the first portion having a first end which is an end in a first direction, and the first portion having the semiconductor film disposed therein, and a second portion being positioned on a side of the first end of the first portion, and the second portion having disposed therein a connecting line that contacts one of the first layers and extends in the third direction. The second portion has a projecting portion that projects further in the second direction than the first portion. |
| US09646984B2 |
Non-volatile memory device
A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure. |
| US09646981B2 |
Passive devices for integration with three-dimensional memory devices
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices. |
| US09646980B2 |
Logic compatible flash memory cells
A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell. |
| US09646977B2 |
Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate. |
| US09646975B2 |
Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device. |
| US09646972B2 |
Methods of forming buried vertical capacitors and structures formed thereby
Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure. |
| US09646965B2 |
Monolithically integrated transistors for a buck converter using source down MOSFET
An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor. |
| US09646961B1 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one TS-short-related failure mode, and one metal-short-related failure mode. |
| US09646950B2 |
Corrosion-resistant copper bonds to aluminum
A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s. |
| US09646947B2 |
Integrated circuit with inductive bond wires
An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die. |
| US09646945B2 |
Semiconductor device having solder joint and method of forming the same
Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder. |
| US09646942B2 |
Mechanisms for controlling bump height variation
The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed. |
| US09646940B2 |
Gas barrier film and electronic device
The gas barrier film including, on a base, a first gas barrier layer which is formed by a physical vapor deposition method or a chemical vapor deposition method and contains Si and N; and a second gas barrier layer which is formed by coating a solution containing a polysilazane compound, wherein the second gas barrier layer is subjected to conversion treatment by being irradiated with a vacuum ultraviolet ray; and, when the composition of each layer is represented by SiOxNy, the distribution of the composition SiOxNy of the second gas barrier layer in a thickness direction satisfies a condition specified in the following (A): (A) the second gas barrier layer includes 50 nm or more of a region of 0.25≦x≦1.1 and 0.4≦y≦0.75 in the thickness direction. |
| US09646936B2 |
Intramodule radio frequency isolation
A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices. |
| US09646932B2 |
Method for forming interconnect structure that avoids via recess
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. |
| US09646930B2 |
Semiconductor device having through-substrate vias
A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device. |
| US09646924B2 |
Interposer, method for manufacturing interposer, and semiconductor device
Electrodes pads formed on device surfaces connect semiconductor chips to through electrodes of an intermediate substrate. A flow path is formed inside the intermediate substrate. A cooling medium flows through the flow path. Stoppers are attached to an inner surface of the flow path. The stoppers include metal abutment members, respectively. An end of each pipe abuts against the counterpart abutment member. Solder connects the pipes to the abutment members. |
| US09646919B2 |
Semiconductor package for a lateral device and related methods
A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package. |
| US09646916B1 |
Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical interconnect
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space. |
| US09646915B2 |
Heat dissipation device and semiconductor device
In a laminating direction of first to fifth ceramic sheets, a first slit and a second slit are positioned closer to a first mounting section and a second mounting section than a first communication hole, a second communication hole, a third communication hole and a fourth communication hole. Moreover, an overlapping section where each first slit and the first communication hole overlap, and an overlapping section where each second slit and the third communication hole overlap, are positioned in the vicinity of an area where the first mounting section and the second mounting section are disposed when viewed from the laminating direction of the first to fifth ceramic sheets. |
| US09646911B2 |
Composite substrate
A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure. |
| US09646910B2 |
Integrated heat spreader that maximizes heat transfer from a multi-chip package
In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components. |
| US09646909B2 |
Electrical switch and mounting assembly therefor
A mounting assembly is for an electrical switch, such as for example, a dimmer switch, which includes a heat sink. The mounting assembly includes a switching member, an insulator disposed between the switching member and the heat sink, and a separate cover member overlaying the switching member. The separate cover member is structured to secure the switching member and the insulator to the heat sink. The switching member includes a switch body and a conductive tab. The separate cover member secures the switching member to the heat sink, without requiring a separate fastener to be inserted through a hole in the conductive tab. The insulator electrically isolates the conductive tab from the heat sink. |
| US09646906B2 |
Semiconductor package with printed sensor
A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor precursors including an ink and a liquid carrier are additively printed directly on the die or package to provide precursors for electrodes and a sensing material between the sensor electrodes. Sintering or curing removes the liquid carrier such that an ink residue remains to provide the sensor electrodes and sensing material. The sensor electrodes electrically coupled to the pins or bond pads or the die includes a wireless coupling structure coupled to the bond pads and the method includes additively printing an ink then sintering or curing to form a complementary wireless coupling structure on the completed semiconductor package coupled to the sensor electrodes so that sensing signals sensed by the sensor are wirelessly transmitted to the bond pads after being received by the wireless coupling structure. |
| US09646905B2 |
Fingerprint sensor package and method for fabricating the same
The invention provides a fingerprint sensor package and a method for fabricating the same. The fingerprint sensor package includes a substrate. A first fingerprint sensor die is disposed on the substrate. A molding compound layer is disposed on the substrate, encapsulating the first fingerprint sensor die. Filler are dispersed in the molding compound layer. The diameter of the fillers is less than or about 20 μm. |
| US09646902B2 |
Paired edge alignment
Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs. |
| US09646900B2 |
Programmable addressable test chip
A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied. |
| US09646896B2 |
Lithographic overlay sampling
Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure. |
| US09646891B2 |
Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus including the same
Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process. |
| US09646888B2 |
Technique of reducing shallow trench isolation loss during fin formation in finFETs
A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate to form a fin-type structure and a groove; forming an isolation material layer in the regions between adjacent fins of the fin-type structure and in the groove; removing a portion of the isolation material layer that is located above the hard mask layer to form a shallow trench isolation; and forming a second mask layer over the hard mask layer, the second mask layer having an opening above the shallow trench isolation; performing ion implantation to the shallow trench isolation through the opening; removing the second mask layer and the hard mask layer; and removing a portion of the isolation material layer located in the regions between adjacent fins of the fin-type structure and a portion of the shallow trench isolation. |
| US09646884B2 |
Block level patterning process
The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses. |
| US09646882B2 |
High quality electrical contacts between integrated circuit chips
Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close undesirable opens or voids between contacts of the two integrated circuits. |
| US09646880B1 |
Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars
A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a dielectric material, removing the first vertically-oriented polysilicon pillar to form a first void in the dielectric material, and filling the first void with a conductive material to form a first via. |
| US09646874B1 |
Thermally-isolated silicon-based integrated circuits and related methods
Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit. |
| US09646872B2 |
Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included. The bottom surface of the SOI substrate is bonded to the patterned top surface of the first semiconductor device layer via the bonding surface. |
| US09646869B2 |
Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed. |
| US09646864B2 |
Substrate processing system and substrate transfer control method
A substrate processing system includes a plurality of processing chambers configured to perform a predetermined processing with respect to substrates, a transfer device configured to transfer the substrates to the processing chambers in a predetermined order, and a delivery unit configured to deliver the substrates between the delivery unit and the transfer device. The substrate processing system configured to sequentially process the substrates by repeating an operation in a predetermined transfer order. The substrate processing system includes a transfer order setting unit and a transfer control unit configured to switch the first transfer order to the second transfer order. |
| US09646860B2 |
Alignment systems and wafer bonding systems and methods
Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer. |
| US09646851B2 |
Embedded semiconductive chips in reconstituted wafers, and systems containing same
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. |
| US09646850B2 |
High-pressure anneal
A method of treating a semiconductor device is provided including the steps of loading the semiconductor device in a processing chamber, pressurizing the processing chamber by supplying a processing gas from a pressure chamber to the processing chamber, performing a thermal anneal of the semiconductor device in the processing chamber, and depressurizing the processing chamber by supplying the processing gas from the processing chamber to the pressure chamber. |
| US09646848B2 |
Etching method, etching apparatus and storage medium
A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times. |
| US09646846B2 |
Method for producing a multilevel microelectronic structure
A method for producing a multilevel microelectronic structure includes formation of a first layer, production of at least one second layer at least partially covering the first layer, and production of at least one microelectronic pattern on or in the second layer. The second layer is formed so as to generate a mechanical stress in it, the first layer forms, for the second layer, a support preventing relaxation of the stress. After the production of at least one microelectronic pattern, the method includes at least elimination of at least part of the first layer, thus making it possible to relax at least part of the mechanical stress on the second layer so that at least a portion of the second layer covering the eliminated part of the first layer moves, and fixing the moved portion of the second layer to a structure part that has remained fixed. |
| US09646844B2 |
Method for forming stair-step structures
A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times. |
| US09646840B2 |
Method for CMP of high-K metal gate structures
A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device and forming a dielectric layer on the substrate. The front-end device includes a first dummy gate in a first type metal gate transistor region, a second dummy gate in a second type metal gate transistor region, and a polysilicon gate in a polysilicon gate region. The method also includes removing a thickness of the first, second, and polysilicon gates and forming a protective layer on the polysilicon layer to protect the polysilicon layer during a CMP process, thereby improving the performance and yield of the semiconductor device. |
| US09646837B2 |
Ion implantation method and ion implantation apparatus
An ion implantation method includes transporting ions to a wafer as an ion beam, causing the wafer to undergo wafer mechanical slow scanning and also causing the ion beam to undergo beam fast scanning or causing the wafer to undergo wafer mechanical fast scanning in a direction perpendicular to a wafer slow scanning direction, irradiating the wafer with the ion beam by using the wafer slow scanning in the wafer slow scanning direction and the beam fast scanning of the ion beam or the wafer fast scanning of the wafer in the direction perpendicular to the wafer slow scanning direction, measuring a two-dimensional beam shape of the ion beam before ion implantation into the wafer, and defining an implantation and irradiation region of the ion beam by using the measured two-dimensional beam shape to thereby regulate the implantation and irradiation region. |
| US09646836B2 |
Semiconductor device manufacturing method
Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n−-type epitaxial layer, and formation of an n-type impurity region and p-type impurity region that form an n-type region and p-type region of a parallel p-n layer, are repeatedly carried out. Furthermore, an n−-type counter region is formed in the vicinity of the p-type impurity region in the uppermost n−-type epitaxial layer forming the parallel p-n layer. Next, an n−-type epitaxial layer is deposited on the n−-type epitaxial layer. Next, a MOS gate structure is formed in the n−-type epitaxial layer. At this time, when carrying out a p-type base region diffusion process, the n-type and p-type impurity regions are caused to diffuse, thereby forming the n-type region and p-type region of the parallel p-n layer. |
| US09646835B2 |
Wafer structure for electronic integrated circuit manufacturing
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. |
| US09646834B2 |
Method for manufacturing semiconductor device
There are prepared a semiconductor substrate having a first main surface and a second main surface, and an adhesive tape having a third main surface and a fourth main surface, the first main surface having a maximum diameter of not less than 100 mm. The semiconductor substrate fixed to the third main surface of the adhesive tape is placed in an accommodation chamber. The accommodation chamber is evacuated while maintaining a temperature of the adhesive tape at not less than 100° C. An electrode is formed on the second main surface after the step of reducing the temperature of the semiconductor substrate. The step of evacuating the accommodation chamber includes a step of evacuating the accommodation chamber while maintaining the temperature of the adhesive tape at not less than 100° C. with a space being provided between the fourth main surface of the adhesive tape and the substrate holding unit. |
| US09646831B2 |
Advanced excimer laser annealing for thin films
The present disclosure relates to a new generation of laser-crystallization approaches that can crystallize Si films for large displays at drastically increased effective crystallization rates. The particular scheme presented in this aspect of the disclosure is referred to as the advanced excimer-laser annealing (AELA) method, and it can be readily configured for manufacturing large OLED TVs using various available and proven technical components. As in ELA, it is mostly a partial-/near-complete-melting-regime-based crystallization approach that can, however, eventually achieve greater than one order of magnitude increase in the effective rate of crystallization than that of the conventional ELA technique utilizing the same laser source. |
| US09646829B2 |
Manufacturing method of semiconductor device
A method for manufacturing a highly reliable semiconductor device with less change in threshold voltage is provided. An insulating film from which oxygen can be released by heating is formed in contact with an oxide semiconductor layer, and light irradiation treatment is performed on a gate electrode or a metal layer formed in a region which overlaps with the gate electrode, so that oxygen is added into the oxide semiconductor layer in a region which overlaps with the gate electrode. Accordingly, oxygen vacancies or interface states in the oxide semiconductor layer in a region which overlaps with the gate electrode can be reduced. |
| US09646824B2 |
Method for manufacturing semiconductor device
To form a MOSFET over a silicon carbide substrate, when a heat treatment accompanied by nitration is carried out to reduce the interface state density in the vicinity of the boundary between a gate insulating film and a silicon carbide substrate, CV hysteresis occurs due to the relationship between the capacitance and gate voltage of the MOSFET, thereby reducing the reliability of a semiconductor device.To solve the above problem, a heat treatment accompanied by nitration is carried out on the insulating film formed over the silicon carbide substrate (step S7). Then, the insulating film is heated in an inert gas atmosphere (step S9). Thereafter, a field effect transistor having a gate insulating film which is composed of the insulating film is formed over the silicon carbide substrate. |
| US09646823B2 |
Semiconductor dielectric interface and gate stack
A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer. |
| US09646820B2 |
Methods for forming conductive titanium oxide thin films
The present disclosure relates to the deposition of conductive titanium oxide films by atomic layer deposition processes. Amorphous doped titanium oxide films are deposited by ALD processes comprising titanium oxide deposition cycles and dopant oxide deposition cycles and are subsequently annealed to produce a conductive crystalline anatase film. Doped titanium oxide films may also be deposited by first depositing a doped titanium nitride thin film by ALD processes comprising titanium nitride deposition cycles and dopant nitride deposition cycles and subsequently oxidizing the nitride film to form a doped titanium oxide film. The doped titanium oxide films may be used, for example, in capacitor structures. |
| US09646818B2 |
Method of forming planar carbon layer by applying plasma power to a combination of hydrocarbon precursor and hydrogen-containing precursor
Aspects of the disclosure pertain to methods of forming planar amorphous carbon layers on patterned substrates. Layers formed according to embodiments outlined herein have may improve manufacturing yield by making the top surface of an amorphous carbon layer more planar despite underlying topography or stoichiometric variations. The amorphous carbon layers may comprise carbon and hydrogen, may consist of carbon and hydrogen or may comprise or consist of carbon, hydrogen and nitrogen in embodiments. Methods described herein may comprise introducing a hydrogen-containing precursor at a relatively high ratio relative to a hydrocarbon into a substrate processing region and concurrently applying a local plasma power capacitively to the substrate processing region to form the planar layer. Alternatively an atomic flow ratio of hydrogen:carbon may begin low and increase discretely or smoothly during formation of the amorphous carbon layer. |
| US09646815B2 |
Integrated nanospray system
Integrated nanospray ionization package, comprising a nanospray emitter, a push button carriage with button element projecting through a bore in said package, an integral high voltage contact pin, a bore in said package for reversible protrusion of the nanospray emitter, a push-and-retract spring mechanism in which the range of forward motion of the emitter is not dependent on range of travel of the said button, and then upon actuation of said button element and spring element for retraction of said nanospray emitter, said nanospray emitter is pushed forward to establish electrical contact, and upon release of said button retracts and breaks the electrical contact. |
| US09646810B2 |
Method for improving mass spectrum reproducibility and quantitative analysis method using same
Methods are described for improving reproducibility of mass spectrum and quantitative analysis method using the same. More particularly, methods for improving reproducibility of a mass spectrum of a chemical compound, wherein temperatures of an ion generation reaction are controlled to be the same with each other, or wherein spectra of which temperature of ion generation reaction are the same with each other are selected from mass spectra of a chemical compound are described. In addition, methods for measuring an equilibrium constant of a proton transfer reaction between a matrix and an analyte at a certain temperature, for obtaining a calibration curve for quantitative analysis, and for quantitative analysis of an analyte by using mass spectra area described. |
| US09646809B2 |
Intaglio printing plate coating apparatus
There is described an intaglio printing plate coating apparatus (1) comprising a vacuum chamber (3) having an inner space (30) adapted to receive at least one intaglio printing plate (10) to be coated, a vacuum system (4) coupled to the vacuum chamber (3) adapted to create vacuum in the inner space (30) of the vacuum chamber (3), and a physical vapour deposition (PVD) system (5) adapted to perform deposition of wear-resistant coating material under vacuum onto an engraved surface (10a) of the intaglio printing plate (10), which physical vapour deposition system (5) includes at least one coating material target (51, 52) comprising a source of the wear-resistant coating material to be deposited onto the engraved surface (10a) of the intaglio printing plate (10). The vacuum chamber (3) is arranged so that the intaglio printing plate (10) to be coated sits substantially vertically in the inner space (30) of the vacuum chamber (3) with its engraved surface (10a) facing the at least one coating material target (51, 52). The intaglio printing plate coating apparatus (1) further comprises a movable carrier (6) located within the inner space (30) of the vacuum chamber (3) and adapted to support and cyclically move the intaglio printing plate (10) in front of and past the at least one coating material target (51, 52). |
| US09646807B2 |
Sealing groove methods for semiconductor equipment
In one embodiment, a surface having a sealing groove formed therein. The sealing groove is configured to accept an elastomeric seal. The sealing groove includes a first portion having a full dovetail profile and at least on a second portion having a half dovetail profile. |
| US09646806B2 |
Plasma electrode device and method for manufacturing the same
Provided are a plasma electrode device and a manufacturing method thereof. The plasma electrode device includes a first substrate including a first substrate main body having a first flow hole through which air flows and a first discharge electrode disposed on one surface of the first substrate main body and a second substrate disposed on one side of the first substrate, the second substrate including a second flow hole through which air flows and a second discharge electrode acting with the first substrate. The first substrate main body includes a ground electrode acting with the first or second discharge electrode to perform plasma discharge and a first insulator coupled to the ground electrode. |
| US09646802B2 |
Method and apparatus for electron beam lithography
Disclosed is an apparatus in a semiconductor lithography system. The apparatus comprises a multiplexer and a plurality of imaging elements. The plurality is configured into a shift chain and an output of the shift chain is coupled to a data input of the multiplexer. |
| US09646799B1 |
Apparatus for sealing arc-tube
Provided is an apparatus for sealing an arc-tube including a jig body including an electrode pin hole into which an end part of the electrode pin inserted into a bypass tube part of the arc-tube is inserted and a connection path connected with the electrode pin hole; and a pressurizing means inserted into the connection path to pressurize and fix the electrode pin positioned at the electrode pin hole. Therefore, the apparatus for sealing an arc-tube can more easily and stably fix the electrode pin during a sealing process. |
| US09646795B2 |
Low-frequency circuit breaker
An object is to obtain a low-frequency circuit breaker which has a simple configuration and a small size as a whole and is advantageous in view of costs. There is provided a low-frequency circuit breaker, in which a semiconductor switch and a mechanical switch are connected in parallel with each other. The semiconductor switch is configured by connecting a thyristor and a thyristor in anti-parallel with each other. These members are controlled by the circuit breaker control circuit. |
| US09646794B2 |
Mobile vehicle or equipment electrical circuit disabler
This invention is a way to disable a electrical circuit in a mobile vehicle or equipment. This invention works in conjunction with our previous Patent, EMERGENCY SHUTOFF SYSTEM FOR POWER MACHINERY, WIRELESS MONITORING SYSTEMS, AND EMERGENCY SHUTOFF METHODS. U.S. Pat. No. 7,012,519. This system allows a new vehicle or equipment to have a remote controller of the ignition circuit installed, without cutting or damaging the wire harness. This system will not void the manufacture warranty of engine module or computer system. This system will shorten the time required to install our “FOX-PAWS” shut down switch, thus saving the customer time and money. |
| US09646791B2 |
Circuit breaker device
A circuit breaker device is provided with a main contactor part that can switch between connection and disconnection of a battery and a circuit, and a circuit breaker (10a) that can disconnect the battery. The circuit breaker (10a) is provided with: a connector connection part (41b) having a pair of connector circuit terminals (41bp, 41bn) related to passing electricity through a coil for the main contactor part; a connector (43) that is attachable to and detachable from the connector connection part (41b) and has a connector shorting terminal (43a) that shorts the pair of connector circuit terminals (41bp, 41bn) upon attachment to the connector connection part (41b); and a claw part (44a) for restricting attachment of the connector (43) to the connector connection part (41b). |
| US09646790B2 |
Crossbar structure of electromagnetic contactor
A crossbar structure of an electromagnetic contactor is provided, specifically, a crossbar structure of an electromagnetic contactor in which consistent performance is attained by preventing a moving mount from being flipped. The electromagnetic contactor includes a crossbar configured to move up and down and a moving contact point disposed on an installation groove, which is formed on the crossbar in a vertical direction, and brought in contact with or separated from a fixed contact point. The installation groove includes an insertion part into which the moving contact point is inserted and assembled and an operating part closely formed enough to prevent the moving contact point from being flipped when the moving contact point moves up and down. |
| US09646782B2 |
Metallic button
A metallic button includes a metallic keycap and an annular buffer member. The metallic keycap has a peripheral side surface, and defines an annular receiving groove and a notch communicating with the annular receiving groove on the peripheral side surface. The annular receiving groove extends around the peripheral side surface. The buffer member is composed of flexible material, sleeved on the keycap, and partially received in the annular receiving groove and the notch. |
| US09646781B1 |
Push button encoders for exercise equipment
A push button encoder comprises a push button, a base that supports the push button, and a printed circuit board. Pushing the push button engages the printed circuit board and thereby causes the printed circuit board to output an electrical signal. A spring resiliently supports the printed circuit board with respect to the base such that the printed circuit board is movable with respect to the base when the push button is pushed. |
| US09646780B2 |
Keyswitch structure
The keyswitch structure uses two linkages form as V-shaped to support a keycap when the keycap is moved up and down. A first linkage and a second linkage are coupled with each other and also coupled with a support on a base respectively in a line contacting way, thereby forming a first axis, a second axis, and a third axis. The third axis is located between the first axis and the second axis. As the keycap is pressed to move downward, the keycap brings the two linkages and the support of the base to have relative rotation movement. Due to the geometric feature between the three axes, part of the linkages between the axes or the support of the base may be caused to slightly deform to provide a resilient restoring force that can move the keycap upward to a position not being pressed. |
| US09646779B2 |
Circuit breakers with polarity sensitive shunt trip mechanisms and methods of operating the same
A circuit breaker includes at least one set of breaker contacts and a contact actuating mechanism configured to open and close the at least one set of contacts. The circuit breaker further includes a polarity sensitive shunt trip mechanism mechanically coupled to the contact actuating mechanism and configured to lock the contact actuating mechanism responsive to a shunt trip voltage of a first polarity to prevent closing of the at least one set of contacts and to unlock the contact actuating mechanism responsive to a shunt trip voltage of a second polarity to enable closing of the at least one set of breaker contacts. |
| US09646778B2 |
Gas insulated switching apparatus and switch
An operating device for a disconnector includes a drive unit, a Geneva mechanism, and a wire. The drive unit includes a forwardly and reversely rotatable motor serving as a drive source for driving a movable contactor of the disconnector, a power source supplying power to the motor, and a first pulley connected to a rotary shaft of the motor, and is disposed apart from the disconnector. The Geneva mechanism includes a second pulley that rotates in the same direction as the first pulley with the rotation of the first pulley, and a driven wheel that is intermittently driven while the second pulley rotates and that is provided with a rotary shaft connected to the movable contactor, and is attached to the disconnector apart from the drive unit. Further, as a flexible rotational force transmission member, a wire is stretched between the second pulley and the first pulley. |
| US09646773B2 |
Electrolyte solution for capacitors, electric double layer capacitor, and lithium ion capacitor
The present invention provides a highly conductive, highly voltage-resistant, and stable liquid electrolyte solution for capacitors which does not coagulate and is free from precipitation of salts in a wide temperature range, particularly at low temperatures, shows excellent electrical characteristics, and has excellent long-term reliability. The present invention also provides an electric double-layer capacitor and a lithium ion capacitor produced using the electrolyte solution for capacitors. The present invention relates to an electrolyte solution for capacitors including: an organic solvent; and a quaternary ammonium salt or lithium salt dissolved in the organic solvent, the organic solvent containing acetonitrile and a chain alkyl sulfonic compound represented by the formula (1): wherein R1 and R2, which may be the same as or different from each other, each independently represent a straight or branched chain C1-C4 alkyl group. |
| US09646768B2 |
Chip component
A chip component includes: a ceramic body including a capacitance forming part in which first and second dielectric layers are alternately disposed; and external electrodes disposed on both end surfaces of the ceramic body, wherein the capacitance forming part includes first and second internal electrodes spaced apart from each other on the first dielectric layers and exposed to the end surfaces of the ceramic body to thereby be connected to the external electrodes; and floating electrodes disposed on the second dielectric layers and overlapped with portions of the first and second internal electrodes, the ceramic body includes protective parts disposed between upper and lower surfaces thereof and the capacitance forming part and having third dielectric layers on which first and second dummy electrodes exposed to the end surfaces of the ceramic body are disposed, and the protective parts include third dummy electrodes disposed between the first and second dummy electrodes. |
| US09646767B2 |
Ceramic electronic component and ceramic electronic apparatus including a split inner electrode
A ceramic electronic component includes a ceramic element, a first inner electrode, a second inner electrode, an outer electrode, and a first auxiliary electrode. The first auxiliary electrode extends to a first surface of the ceramic element. The first inner electrode extends along a first direction on the first surface. The first auxiliary electrode extends outward from the region where the first inner electrode is disposed in the first direction on the first surface. The outer electrode covers the first inner electrode and the first auxiliary electrode. |
| US09646765B2 |
Coil winding device and winding method thereof
The coil winding device includes a nozzle configured to feed a wire to wind the wire around the winding core to form a coil, a plurality of hook rods disposed in predetermined intervals around an end part of the winding core, the wire drawn out from an edge of the coil being configured to be hooked to each of the plurality of hook rods during a forming process of the coil, a winding core rotating mechanism configured to rotate the winding core together with the plurality of hook rods, a hook rod rotating mechanism configured to rotate the plurality of the hook rods, and a wire drawing-out mechanism configured to draw out the wire from the edge of the coil and hook the wire on the hook rods during the forming process of the coil. |
| US09646762B2 |
Low crosstalk magnetic devices
In one aspect there is an apparatus. The apparatus may include an electronic circuit that generates a first magnetic field from a current in the electronic circuit. The apparatus may further include a sensing circuit separated from the electronic circuit by a predetermined distance to sense the first magnetic field. A cage circuit may cancel a portion of the first magnetic field at the sensing circuit. The cage circuit may generate a cage current from the current in the electronic circuit and at least one of a phase shift or an amplitude shift applied to the current in the electronic circuit. The cage current may generate a second magnetic field causing cancellation of the portion of the magnetic field from the electronic circuit at the sensing circuit. |
| US09646757B2 |
Surge protective network signal processing circuit assembly
A surge protective network signal processing circuit assembly includes a network chip, a network connector and a processing circuit including a plurality of two-wire channels electrically connected in parallel between the network chip and the network connector and a plurality of signal coupling capacitors respectively mounted in the two-wire channels and electrically connected in parallel and grounded for discharging instantaneous high voltage surges. |
| US09646756B2 |
Powder magnetic core and method for producing the same
The present invention provides a powder magnetic core which has a low iron loss and an excellent constancy of magnetic permeability and is suitably used as a core for a reactor mounted on a vehicle. The powder magnetic core is a compact of a mixed powder containing an iron-based soft magnetic powder having an electrical insulating coating formed on its surface and a powder of a low magnetic permeability material having a heat-resistant temperature of 700° C. or higher than 700° C. and a relative magnetic permeability of not more than 1.0000004. The density of the compact is 6.7 Mg/m3 or more, and the low magnetic permeability material exists in the gap among the soft magnetic powder particles in the green compact. |
| US09646753B2 |
Apparatus with a circuit for actuating a magnetic actuator arrangement
An apparatus with a circuit arrangement having four actuatable switching elements and three output connections for actuating two magnetic actuator coils. A first switching element is connected between a first supply voltage connection for a high potential of a supply voltage source and a first output connection. A second switching element is connected between the first supply voltage connection and a second output connection. A third switching element is connected between a third output connection and a second supply voltage connection for low potential of the supply voltage source. A fourth switching element is connected between the second output connection and the second supply voltage connection. A magnetic actuator arrangement is electrically connected to the circuit arrangement via lines and includes two magnetic actuator coils and three actuator connections. |
| US09646752B2 |
Magnetic field distribution control apparatus
A magnetic field distribution control apparatus includes a rod portion, a coil disposed at one side of an upper surface of the rod portion, and a ferrite movably disposed within the coil and configured to produce a magnetic field. |
| US09646749B2 |
Grain-oriented electrical steel sheet
The present invention proposes a method that can reduce the noise generated by a transformer core and the like when formed by laminations of a grain-oriented electrical steel sheet in which core loss has been reduced by a magnetic domain refinement process. In this steel sheet, linear distortion extending with an orientation in which an angle formed with a direction perpendicular to the rolling direction of the steel sheet is an angle of 30° or less is periodic in the direction of rolling of the steel sheet, core loss (W17/50) is 0.720 W/kg or less, and magnetic flux density (B8) is 1.930 T. The volume of the closure domain arising in the distortion part is 1.00-3.00% of the total magnetic domain volume within the steel sheet. |
| US09646743B2 |
High voltage bushing cover
Bushing covers adapted to surround a bushing to protect the bushing and bushing connections from damage, which can be installed at distance using an insulated pole. |
| US09646742B2 |
Electricity transmission cooling system
A method for cooling high temperature superconducting (HTS) cable comprising receiving a first flow of coolant at a first section of HTS cable and permitting the first flow of coolant to flow therethrough. The method also includes receiving a second flow of coolant at a second section of HTS cable and permitting the second flow of coolant to flow therethrough. The first section of HTS cable and said second section of HTS cable are coupled via a cable joint, the cable joint electrically connecting the first and second sections of HTS cable. The cable joint is in fluid communication with at least one refrigeration module. The cable joint includes at least one conduit configured to permit a third flow of coolant between the cable joint and the at least one refrigeration module through a coolant line separate from the first and second sections of HTS cable. |
| US09646740B2 |
Electrical characteristics of shielded electrical cables
A shielded electrical cable includes one or more conductor sets extending along a length of the cable and being spaced apart from each other along a width of the cable. Each conductor set has one or more conductors having a size no greater than 24 AWG and each conductor set has an insertion loss of less than about −20 dB/meter over a frequency range of 0 to 20 GHz. First and second shielding films are disposed on opposite sides of the cable, the first and second films including cover portions and pinched portions arranged such that, in transverse cross section, the cover portions of the first and second films in combination substantially surround each conductor set, and the pinched portions of the first and second films in combination form pinched portions of the cable on each side of each conductor. |
| US09646738B2 |
System for isolating power conductors using folded insulated sheets
An improved electrical system may be provided by electrically isolating complex bus geometries by using one or more substantially flat and electrically insulating sheets. The sheet may have one or more fold lines which allow the sheet to fold in multiple directions and ways over varying configurations of power conductors. The sheet may fit within the constraints of preconfigured electrical system components without the need for redesigning such components. The sheet may have a dielectric strength per mil effective to isolate power conductors based on maximum charge and proximity of the power conductors. |
| US09646737B2 |
Bearing ring, electrically insulating coating and method for applying an electrically insulating coating
The invention discloses a bearing ring. The bearing ring, with a body, has an electrically insulating coating made up of a ceramic layer with pores and a plastic for filling the pores and coating the ceramic layer. According to the invention, the pores have a proportion between 10 and 50% in the ceramic layer. The invention furthermore defines an electrically insulating coating, made up of a ceramic layer with pores and a plastic for filling the pores and coating the ceramic layer. The invention further still discloses a method for applying an electrically insulating coating to a body of a bearing ring. |
| US09646736B2 |
Aromatic polycarbonate resin composition and molded article thereof
A resin composition which has high electrical conductivity and high stiffness, is suppressed in outgassing caused by a temperature rise and is excellent in heat stability during melt molding in the production process and a molded article thereof.The resin composition comprises (A) 65 to 85 parts by weight of an aromatic polycarbonate resin (component A), (B) 15 to 35 parts by weight of graphite having an average particle diameter of 5 to 60 μm (component B), and (C) 0.1 to 5 parts by weight of at least one compound (component C) selected from the group consisting of a polyester having a sulfonate group (component C-1) and a polyether ester having a sulfonate group (component C-2) based on 100 parts by weight of the total of the components A and B. |
| US09646731B2 |
X-ray radiation detector, CT system and related method
A direct-converting x-ray radiation detector is disclosed for detecting x-ray radiation, in particular for use in a CT system. In an embodiment, the detector includes a semiconductor material used for detecting the x-ray radiation; at least one collimator; and at least one radiation source, to irradiate the semiconductor material with additional radiation. In at least one embodiment, the at least one collimator includes at least one reflection layer on a side facing the semiconductor material, on which the additional radiation is reflected to the semiconductor material. In another embodiment, a CT system including the direct-converting x-ray radiation detector, and a method for detecting incident x-ray radiation via a direct-converting x-ray radiation detector, in particular for use in a CT system, are disclosed. |
| US09646728B2 |
Plasma welding apparatus for guide thimble and guide thimble end plug of nuclear fuel assembly
Disclosed is a plasma welding apparatus for a guide thimble and guide thimble end plug of a nuclear fuel assembly, which includes: a welding chamber (100) includes an end-plug inserting part (110) into which the end plug (10) is inserted, a guide-thimble inserting part (120) which is provided on the same axis as the end-plug inserting part (110) and into which the guide thimble (20) is inserted and fixed, a torch assembling part (130) to which a plasma welding torch (131) is assembled so as to make a right angle with the end-plug inserting part (110) and the guide-thimble inserting part (120), and argon inflow and outflow ports (141, 142) through which argon is supplied or discharged; an end-plug transfer unit (210) supplying the end plug (10) to the end-plug inserting part (110); and an guide-thimble transfer unit (220) transferring the guide thimble (20) to the guide-thimble inserting part (120). |
| US09646725B2 |
Method of operating a pressurized-water nuclear reactor allowing same to pass from a plutonium-equilibrium cycle to a uranium-equilibrium cycle and corresponding nuclear fuel assembly
A method is provided for operating a nuclear reactor. The method includes operating the nuclear reactor for at least one plutonium equilibrium cycle during which the core contains plutonium-equilibrium nuclear fuel assemblies; subsequently, operating the reactor for transition cycles, at least some of the plutonium-equilibrium nuclear fuel assemblies being progressively replaced with transition nuclear fuel assemblies and then with uranium-equilibrium nuclear fuel assemblies; and then operating the nuclear reactor for at least one uranium equilibrium cycle. |
| US09646721B1 |
Solid state drive bad block management
A system, computer program product, and computer-executable method of managing a solid state drive (SSD) in a data storage system, the system, computer program product, and computer-executable method including initializing the SSD to enable the SSD to request memory for bad block replacement, querying the SSD to determine a size of memory on the SSD reserved for dynamic over provisioning, and allocating a portion of the size of memory for bad block replacement. |
| US09646719B2 |
Memory device, method of generating log of command signals/address signals of memory device, and method of analyzing errors of memory device
A memory device includes first and second memory cell arrays, a first controller, and a second controller. The first controller controls the first memory cell array through first word line signals and first bit line signals to execute an operation corresponding to a command signal based on an address signal and a data signal. The second controller includes first and second mode registers. The second controller writes sampled values of the address signal and the command signal to the second memory cell array through access signals to form a log in response to stored values of the first and second mode registers or reads stored values of the second memory cell array as the data signal through the access signals. |
| US09646717B2 |
Memory device with internal measurement of functional parameters
A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation. |
| US09646714B2 |
Shift register, semiconductor device, display device, and electronic device
The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire. |
| US09646713B2 |
Memory cell and corresponding device
A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event. |
| US09646712B1 |
Implementing eFuse visual security of stored data using EDRAM
A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination. |
| US09646710B2 |
Semiconductor device with channel switching structure and method of making same
Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line. |
| US09646708B2 |
Input/output interface circuits and methods for memory devices
An input/output interface circuit is provided for a memory device. The input/output interface circuit receives a first control signal and a second control signal, and provides an output clock signal. The input/output interface circuit includes a plurality of circuit blocks coupled in series, the a plurality of circuit blocks including an input terminal coupled to the first control signal and the second control signal, and an output terminal providing the output clock signal, a plurality of power switch transistors, each power switch transistor including a control terminal and coupled between a corresponding one of the circuit blocks and a power supply terminal, and a plurality of switch control circuits, each switch control circuit coupled to the control terminal of a corresponding one of the power switch transistors. The switch control circuits are configured to activate the circuit blocks in a first predetermined order and deactivate the circuit blocks in a second predetermined order. |
| US09646704B2 |
Operating method for nonvolatile memory and operating method for storage device including the nonvolatile memory
An operation method of a storage device including a nonvolatile memory and a memory controller controlling the nonvolatile memory, includes transmitting a multi-program command to the nonvolatile memory by the memory controller; and programming memory cells connected to two or more word lines by the nonvolatile memory in response to the multi-program command. |
| US09646698B2 |
Semiconductor memory device tunnel insulating layers included in the plurality of memory cells having different thicknesses according to distances of the plurality of memory cells from the X-decoder
A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder. |
| US09646695B2 |
Content addressable memory and memory cell thereof
A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided. |
| US09646694B2 |
10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed. |
| US09646689B2 |
Refresh architecture and algorithm for non-volatile memories
Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level. |
| US09646686B2 |
Reconfigurable circuit including row address replacement circuit for replacing defective address
According to one embodiment, a reconfigurable circuit includes circuit blocks arranged with a matrix of A rows and B columns. Each of the circuit blocks includes M row conductive lines, N column conductive lines crossing the row conductive lines, output inverters each having input and output terminals, the input terminal of each output inverter connected to corresponding one of the row conductive lines, input inverters each having input and output terminals, the output terminal of each input inverter connected to corresponding one of the column conductive lines, and resistance change elements between the row conductive lines and the column conductive lines, each of the resistance change elements including a first terminal and a second terminal, the first terminal being connected to corresponding one of the row conductive lines, the second terminal being connected to corresponding one of the column conductive lines. |
| US09646685B2 |
Resistive memory device, resistive memory, and operating method of the resistive memory device
An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal. |
| US09646684B1 |
PCM memory with margin current addition and related methods
A differential PCM memory may include first and second PCM elements, and a sense amplifier circuit configured to sense a difference between first and second sense currents passing through the first and second PCM elements, respectively, during a sense operation. The differential PCM memory may include a first margin current branch coupled in parallel with the first PCM element and configured to selectively add a first margin current to the first sense current, and a second margin current branch coupled in parallel with the second PCM element and configured to selectively add a second margin current to the second sense current. |
| US09646678B2 |
Semiconductor integrated circuit device
Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows. |
| US09646673B2 |
Address detection circuit, memory system including the same
An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at least a threshold number of times in each period that the active command is activated M (1≦M≦N) number of times, based on the N number of addresses stored in the address storage unit. |
| US09646672B1 |
Memory device and method of refreshing the same
A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation. |
| US09646671B1 |
Systems and methods for managing write voltages in a cross-point memory array
Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased. |
| US09646670B2 |
Spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy
Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example, disclosed is a three-terminal magnetic tunnel junction (MTJ) storage element that is programmed via a combination of voltage-controlled magnetic anisotropy (VCMA) and spin-orbit torque (SOT) techniques. Also disclosed is a memory controller configured to program the three-terminal MTJ storage element via VCMA and SOT techniques. The disclosed devices improve efficiency over conventional devices by using less write energy, while having a design that is simpler and more scalable than conventional devices. The disclosed devices also have increased thermal stability without increasing required switching current, as critical switching current between states is essentially the same. |
| US09646669B2 |
Programming memory elements using two phase boost
Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using a two phase boost. The memory devices perform the two phase boosting to program anti-parallel data values during a first programming phase and to program parallel data values during a second programming phase that is subsequent to the first programming phase. The voltage boost is provided by a high percentage of memory elements in a memory device by simultaneously transitioning the source line of the memory elements from a reference voltage to a source voltage during the first programming phase to effectively double the activation voltage for gates of transistors in the memory elements to program anti-parallel data values. Methods are also described for programming memory elements using a two phase boost. |
| US09646664B2 |
Memory device and memory system including the same
A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column. |
| US09646663B2 |
Multi-bank memory with line tracking loop
In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks. |
| US09646661B2 |
Memory device with internal combination logic
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic. |
| US09646654B2 |
Synchronization of events and audio or video content during recording and playback of multimedia content items
A computer-implemented method for simultaneously recording a media recording and an event recording includes recording a media recording, recording an event recording simultaneously with the media recording, the event recording encoding a plurality of events, an event being related to one or more user interactions with an input device associated with the media recording and recording the event recording includes for each of a plurality of events of the event recording generating data characterizing the particular event and generating a corresponding time stamp for the particular event by polling a system time of a computer device at the time the particular event takes place, the method further includes providing the data characterizing the particular event and the corresponding time stamp for storage. |
| US09646652B2 |
Scene and activity identification in video summary generation based on motion detected in a video
Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are identified based on the identified events of interest. In one example, best scenes are identified based on the motion values associated with frames or portions of a frame of a video. Motion values are determined for each frame and portions of the video including frames with the most motion are identified as best scenes. Best scenes may also be identified based on the motion profile of a video. The motion profile of a video is a measure of global or local motion within frames throughout the video. For example, best scenes are identified from portion of the video including steady global motion. A video summary can be generated including one or more of the identified best scenes. |
| US09646645B2 |
Spindle motor with disk clamp centered on cover cap
The invention relates to the spindle motor for driving a hard disk drive, comprising: a stationary motor component (10, 12, 16, 18), a rotary motor component (14) rotatably mounted relative to the stationary motor component using a fluid dynamic bearing system, a bearing gap (20) disposed between the stationary motor component and the rotary motor component and filled with a bearing fluid, having at least one open end, at least one sealing gap (34) for sealing the open end, at least one cover cap (30) for covering the sealing gap, which is secured to the rotatable motor component, a disk clamp (44) for attachment of at least one magnetic storage disk (48) on the rotatable motor member and an electromagnetic drive system (40, 42) to drive the rotatable motor member. The disk clamp (44, 156) is centered on a peripheral surface of the cover cap (30, 118). |
| US09646642B2 |
Resist fortification for magnetic media patterning
A method and apparatus for forming magnetic media substrates is provided. A patterned resist layer is formed on a substrate having a magnetically susceptible layer. A conformal protective layer is formed over the patterned resist layer to prevent degradation of the pattern during subsequent processing. The substrate is subjected to an energy treatment wherein energetic species penetrate portions of the patterned resist and conformal protective layer according to the pattern formed in the patterned resist, impacting the magnetically susceptible layer and modifying a magnetic property thereof. The patterned resist and conformal protective layers are then removed, leaving a magnetic substrate having a pattern of magnetic properties with a topography that is substantially unchanged. |
| US09646641B2 |
Composition for magnetic recording medium and magnetic recording medium
The magnetic coating composition for a magnetic recording medium comprises: (A) a compound denoted by formula (1) having a weight average molecular weight of equal to or less than 20,000: (A1-R2—S)n-R1—(P1)m (1) wherein, in formula (1), R1 denotes an organic connecting group with a valence of (m+n); R2 denotes a single bond or divalent organic connecting group; A1 denotes a functional group selected from the group consisting of an acidic group, a basic group, and a hydroxyl group; m denotes an integer ranging from 1 to 8 and n denotes an integer ranging from 1 to 9, with m+n ranging from 3 to 10; each of n instances of A1 and R2 can be independently different or identical; P1 denotes a polymer backbone; and m instances of P1 can be identical or different; (B) binder; (C) ferromagnetic powder; and (D) solvent. |
| US09646639B2 |
Heat assisted magnetic recording writer having integrated polarization rotation waveguides
A heat assisted magnetic recording (HAMR) writer is described. The HAMR writer is coupled with a laser that provides energy having a first polarization state. The HAMR writer has an air-bearing surface (ABS) configured to reside in proximity to a media during use, a plurality of waveguides, a main pole and at least one coil. The main pole writes to the media and is energized by the coil(s). The waveguides receive the energy from the laser and direct the energy toward the ABS. The waveguides include an input waveguide and an output waveguide. The input waveguide is configured to carry light having the first polarization state. The output waveguide is configured to carry light having a second polarization state different from the first polarization state. The waveguides are optically coupled and configured to transfer the energy from the first polarization state to the second polarization state. |
| US09646638B1 |
Co-located gimbal-based DSA disk drive suspension with traces routed around slider pad
A suspension having a DSA structure on a gimbaled flexure includes a loadbeam and a flexure attached to the loadbeam. The flexure includes a metal layer with a pair of spring arms, a tongue including a slider mounting surface, and a pair of struts connecting the pair of spring arms to the tongue. The suspension further includes a pair of traces including one or more insulated conductors and being routed around opposite sides of the slider mounting surface, over the pair of struts to a set of terminal contacts on a distal portion of the tongue. The suspension also includes a motor mounted on the flexure, the motor having opposite lateral ends, the motor orientated laterally across the flexure such that the opposite lateral ends of the motor are on opposite lateral sides of the flexure. Electrical activation of the motor rotates the slider mounting surface relative to the loadbeam. |
| US09646637B1 |
Thin-film piezoelectric material element, head gimbal assembly and hard disk drive
A thin-film piezoelectric material element includes a laminated structure part having a lower electrode film, a piezoelectric material film laminated on the lower electrode film and an upper electrode film laminated on the piezoelectric material film. The thin-film piezoelectric material element includes a surface layer insulating film disposed on side surfaces of the laminated structure part and a top surface of the upper electrode film, and has a through hole formed on a top disposed part disposed on the top surface. The surface layer insulating film has a long-side disposed part disposed outside than the top disposed part, the long-side disposed part has a long-side width, along with the long-side direction, formed shorter than the through hole. |
| US09646635B2 |
Magnetoresistive sensor
Implementations disclosed herein allow a signal detected by a magnetoresistive (MR) sensor to be improved by providing for one or more alloyed layers that each includes a ferromagnetic material and a refractory material. The alloyed layers are provided adjacent to a shield element or between soft magnetic layers of the sensor stack. |
| US09646632B2 |
Time warp activation signal provider, audio signal encoder, method for providing a time warp activation signal, method for encoding an audio signal and computer programs
An audio encoder has a window function controller, a windower, a time warper with a final quality check functionality, a time/frequency converter, a TNS stage or a quantizer encoder, the window function controller, the time warper, the TNS stage or an additional noise filling analyzer are controlled by signal analysis results obtained by a time warp analyzer or a signal classifier. Furthermore, a decoder applies a noise filling operation using a manipulated noise filling estimate depending on a harmonic or speech characteristic of the audio signal. |
| US09646630B2 |
Voice recognition via wide range adaptive beam forming and multi-channel audio data
An apparatus, system, and computer readable media for data pre-processing and processing for voice recognition are described herein. The apparatus includes logic to pre-process multi-channel audio data and logic to resolve a source location. The apparatus also includes logic to perform wide range adaptive beam forming, and logic to perform full voice recognition. |
| US09646627B2 |
Speech processing device, method, and program for correction of reverberation
A speech processing device includes a distance acquisition unit configured to acquire a distance between a sound collection unit configured to record speech from a sound source and the sound source, a reverberation characteristic estimation unit configured to estimate a reverberation characteristic based on the distance acquired by the distance acquisition unit, a correction data generation unit configured to generate correction data indicating a contribution of a reverberation component from the reverberation characteristic estimated by the reverberation characteristic estimation unit; and a dereverberation unit configured to remove the reverberation component from the speech by correcting the amplitude of the speech based on the correction data. |
| US09646626B2 |
System and method for network bandwidth management for adjusting audio quality
Disclosed herein are systems, methods, and computer-readable storage devices for processing audio signals. An example system configured to practice the method receives audio at a device to be transmitted to a remote speech processing system. The system analyzes one of noise conditions, need for an enhanced speech quality, and network load to yield an analysis. Based on the analysis, the system determines to bypass user-defined options for enhancing audio for speech processing. Then, based on the analysis, the system can modify an audio transmission parameter used to transmit the audio from the device to the remote speech processing system. The audio transmission parameter can be one of an amount of coding, a chosen codec, an amount of coding, or a number of audio channels, for example. |
| US09646623B2 |
Mix buffers and command queues for audio blocks
The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example. |
| US09646621B2 |
Voice detector and a method for suppressing sub-bands in a voice detector
The present invention relates to a voice detector being responsive to an input signal being divided into sub-signals representing a frequency sub-band, comprising: means to calculate, for each sub-band, an SNR value snr[n] based on a corresponding sub-signal for each sub-band and a background signal for each sub-band. The voice detector further comprises: means to calculate a power SNR value for each sub-band, wherein at least one of said power SNR values is calculated based on a non-linear function, means to form a single value snr_sum based on the calculated power SNR values, and means to compare said single value snr_sum and a given threshold value vad_thr to make a voice activity decision vad_prim presented on an output port. The invention also relates to a voice activity detector, a node and a method for selectively suppressing sub-bands in a voice detector. |
| US09646618B2 |
Method and apparatus for compressing and decompressing a Higher Order Ambisonics representation for a sound field
The invention improves HOA sound field representation compression. The HOA representation is analyzed for the presence of dominant sound sources and their directions are estimated. Then the HOA representation is decomposed into a number of dominant directional signals and a residual component. This residual component is transformed into the discrete spatial domain in order to obtain general plane wave functions at uniform sampling directions, which are predicted from the dominant directional signals. Finally, the prediction error is transformed back to the HOA domain and represents the residual ambient HOA component for which an order reduction is performed, followed by perceptual encoding of the dominant directional signals and the residual component. |
| US09646615B2 |
Audio signal encoding employing interchannel and temporal redundancy reduction
A method of encoding a time-domain audio signal is presented. A device transforms the time-domain signal into a frequency-domain signal including a sequence of sample blocks, wherein each block includes a coefficient for each of multiple frequencies. The coefficients of each block are grouped into frequency bands. For each frequency band of each block, a scale factor is estimated for the band, and the energy of the band for the block is compared with the energy of the band of an adjacent sample block, wherein the blocks may be adjacent to each other in either or both of an interchannel and a temporal sense. If the ratio of the band energy for the first block to the band energy for the adjacent block is less than some value, the scale factor of the band for the first block is increased. The coefficients of the band for each block are quantized based on the resulting scale factor. The encoded audio signal is generated based on the quantized coefficients and the scale factors. |
| US09646614B2 |
Fast, language-independent method for user authentication by voice
A method and system for training a user authentication by voice signal are described. In one embodiment, a set of feature vectors are decomposed into speaker-specific recognition units. The speaker-specific recognition units are used to compute distribution values to train the voice signal. In addition, spectral feature vectors are decomposed into speaker-specific characteristic units which are compared to the speaker-specific distribution values. If the speaker-specific characteristic units are within a threshold limit of the speaker-specific distribution values, the speech signal is authenticated. |
| US09646605B2 |
False alarm reduction in speech recognition systems using contextual information
A system and method are presented for using spoken word verification to reduce false alarms by exploiting global and local contexts on a lexical level, a phoneme level, and on an acoustical level. The reduction of false alarms may occur through a process that determines whether a word has been detected or if it is a false alarm. Training examples are used to generate models of internal and external contexts which are compared to test word examples. The word may be accepted or rejected based on comparison results. Comparison may be performed either at the end of the process or at multiple steps of the process to determine whether the word is rejected. |
| US09646602B2 |
Method and apparatus for improving disordered voice
There is provided a method and an apparatus for processing a disordered voice. A method for processing a disordered voice according to an exemplary embodiment of the present invention includes: receiving a voice signal; recognizing the voice signal by phoneme; extracting multiple voice components from the voice signal; acquiring restored voice components by processing at least some disordered voice components of the multiple voice components by phoneme; and synthesizing a restored voice signal based on at least the restored voice components. |
| US09646601B1 |
Reduced latency text-to-speech system
In delivering text-to-speech (TTS) results to a user, the time between the user request and delivery of initial TTS results is reduced using one or more of various techniques. Caching of TTS results may be reconfigured to cache unit indices rather than full speech synthesis results. More powerful computing resources may be dedicated to early TTS processing. A user may be notified of TTS results prior to complete processing of a TTS request. Early TTS processing may be performed by a local device and then passed to a remote device. |
| US09646600B1 |
Text reading and vocalizing device
A text reading and vocalizing device having an elongate, handheld, manipulable body positional proximal a line of text, whereby movement of the body along the line of text positions a light scanner, distally disposed upon a second body part, to optically recognize text for audible indication of the text sounded by the body or relayed through a pair of headphones interconnected at a headphone jack, wherein text is readable and playable to a user, the text further translatable into an associated language when one of a plurality of language selection buttons, disposed upon the body, is depressed. |
| US09646599B2 |
Remoldable contour sensor holder
A sensor assembly for inspecting a part, the sensor assembly comprising a sensor for sensing a defect of the part and a remoldable housing for retaining and positioning the sensor in alignment with the defect of the part. The housing is formed of a moldable material and may be molded into a shape that conforms to a contour of the part when a stimulus is applied to the housing and may harden into the shape when the stimulus is removed from the housing. |
| US09646598B2 |
Audio device
An audio device connected to an electronic device is provided. The audio device connected to an electronic device includes an audio side connector comprising a microphone terminal that outputs a microphone signal to the electronic device, at least one audio terminal that receives an audio signal from the electronic device, an active noise cancelling (ANC) terminal, and a ground terminal, an ANC block that is driven by power input from the electronic device to remove noise around the audio device, an ANC power source unit that is provided in the electronic device and applies power input via the ANC terminal to the ANC block as drive power, and an on/off switch unit that controls the ANC power source unit, wherein the ANC terminal is included in any one of the areas of the microphone terminal, the audio terminal, and the ground terminal. |
| US09646597B1 |
Delivery sound masking and sound emission
An unmanned aerial vehicle (UAV) may emit masking sounds during operation of the UAV to mask other sounds generated by the UAV during operation. The UAV may be used to deliver items to a residence or other location associated with a customer. The UAV may emit sounds that mask the conventional sounds generated by the propellers and/or motors to cause the UAV to emit sounds that are pleasing to bystanders or do not annoy the bystanders. The UAV may emit sounds using speakers or other sound generating devices, such as fins, reeds, whistles, or other devices which may cause sound to be emitted from the UAV. Noise canceling algorithms may be used to cancel at least some of the conventional noise generated by operation of the UAV using inverted sounds, while additional sound may be emitted by the UAV, which may not be subject to noise cancelation. |
| US09646589B2 |
Joint and coordinated visual-sonic metaphors for interactive multi-channel data sonification to accompany data visualization
Data sonification arrangements for use with data visualization so as to provide parallel perceptual channels for representing complex numerical data to a user seeking to identify correlations within the data are presented. In an implementation, several varying data quantities are represented by time-varying graphics while several other varying data quantities are represented by time-varying sound, both presented to a user to observe correlations between sonic and visual events or trends. Sonification can be used to offload some information-carrying information capacity from a visualization system, while other information can be rendered via both sonification and visualization to provide affirming or orienting redundancy. In an implementation joint and coordinated visual-sonic metaphors are used for this or other purposes. For example, data sonification can include multiple data-modulated sound timbre classes, each rendered within a stereo sound field according to a spatial metaphor that is shared with the visualization. |
| US09646588B1 |
Cyber reality musical instrument and device
Systems and methods for creating and presenting sensory stimulating content in a cyber reality environment. One aspect of the disclosure allows a composer to associate audio content with one or more virtual triggers, and to define behavior characteristics which control the functioning of each virtual trigger. Another aspect of the disclosure provides a variety of user interfaces through which a performer can cause content to be presented to an audience. |
| US09646583B2 |
Remote hi-hat mouth controller
A wireless hi-hat cymbal controller is activated by a user's biting action. The controller includes a pressure sensor located in a mouthpiece and operably coupled to a wireless transceiver. An actuator operates in response to a wireless signal received from the controller when the pressure sensor detects that a user is biting down on the mouthpiece. |
| US09646581B2 |
Soundhole cover accessories
Soundhole cover accessories may act to prevent items from falling into the body of an instrument through its soundhole, such as guitar picks or the like. The accessories may include a body portion adapted to fit over the soundhole of the instrument and a mesh portion defined by a plurality of apertures that may be dimensioned so that items that may be used with the instrument (such as guitar picks) are substantially prevented from passing there through. The body portion may act as a base to which one or more adhesive fasteners may be attached. The body may be flexible or rigid, and may be placed over the soundhole and affixed into place by the adhesive fasteners. |
| US09646580B1 |
Decorative panel for guitar and manufacturing method thereof
A decorative panel for a guitar and a manufacturing method of the decorative panel. The decorative panel can be applied to a head, a body, a neck or a pick guard of the guitar to enhance an aesthetic sense of the guitar. The manufacturing process is simplified to reduce the manufacturing period thereby increasing productivity and reducing the failure rate of the guitar. The decorative panel for the guitar includes a base plate; and a binding disposed at the edge of the base plate in a band type by a binding line. The binding line is integrally formed such that one or more binding grooves formed on the periphery of the base plate are filled with epoxy resin paint. |
| US09646575B2 |
Remote desktop system evaluating method, medium and apparatus
A method includes extracting an input operation data group that includes multiple items of input operation data in a remote desktop system and a drawing processing data group that includes multiple items of drawing processing data, specifying a relative position between a coordinate that is included in one item of input operation data among the extracted input operation data group, and a coordinate of a drawing area that is included in one item of drawing processing data among the extracted drawing processing data group, specifying a coordinate that is assumed to be included in any item of input operation data which is included in the input operation data group, and associating different input operation data that is included in the input operation data group, with the different drawing processing data, based on the coordinates that are assumed and that are specified. |
| US09646572B2 |
Image processing apparatus
An image processing apparatus determines a transparency percentage of each of plural portions of a cabin image of a vehicle, causes the plural portions to be semi-transparent or to be transparent at the determined transparency percentages and displays the cabin image. Thus, the user can intuitively understand a positional relationship between the vehicle and a surrounding region and does not miss an obstacle in a course of traveling of the vehicle. |
| US09646566B2 |
Medical image display control apparatus and operation method of the same, and medium
Providing a parameter calculation unit that calculates parameters representing medical functional information for pixel positions of the medical image, wherein the upper and lower limit values of the parameter medically represent the same functional information and whose value changes cyclically between these values, an interpolation parameter calculation unit that obtains, for a pixel position for which the parameter is not calculated, a parameter by interpolation, the unit calculating a parameter obtained by the interpolation using a cyclic function in which the interpolation direction differs according to the difference between the parameters calculated for two pixel positions, a display color group storage unit that includes a color group in which the same color corresponds to the upper and lower limit values of the parameter and whose color changes with the magnitude of the parameter, and a mapping unit that maps the parameters based on the color group. |
| US09646560B2 |
Liquid crystal display device for improving crosstalk characteristics
A liquid crystal display (LCD) device includes a display including a plurality of pixels, a voltage compensation controller configured to control the plurality of pixels and determine whether to compensate a predetermined grayscale voltage to be applied to the plurality of pixels, and a voltage generator configured to provide the predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining not to compensate the predetermined grayscale voltage, and to compensate the predetermined grayscale voltage and provide the compensated predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining to compensate the predetermined grayscale voltage. |
| US09646559B2 |
Liquid crystal display device
A display device including a panel having a display area and first, second, third and fourth non-display areas formed at an outer portion of the display area, said first non-display area facing the second non-display area, and the third non-display area facing the fourth non-display area; a data driver disposed in the first non-display area, and configured to drive a plurality of data lines provided in a first direction in the display area; a gate driver disposed in the second non-display area and configured to drive a plurality of gate lines provided in a second direction vertical to the first direction in the display area; a timing controller configured to drive the data driver and the gate driver; and a plurality of link lines in the display area and extending from the gate driver and provided in parallel to the data lines respectively connected to the gate lines. |
| US09646553B2 |
Display device
A display device according to an exemplary embodiment of the inventive concept includes: a first insulation substrate; gate lines disposed on the first insulation substrate to transmit a gate signal; data lines crossing and insulated from the gate lines to transmit a data voltage; a first switching element and a second switching element which are connected to the corresponding gate and data lines; a dividing switching element connected to the corresponding gate lines, second switching element, and a reference voltage line; a first pixel electrode connected to the first switching element; and a second pixel electrode connected to the second switching element and the dividing switching element. A reference voltage applied to the dividing switching element from the reference voltage lines varies according to the polarities of the data voltage with respect to the common voltage. |
| US09646552B2 |
Display device with a source signal generating circuit
In RGB time division drives, there is capacitor coupling due to the effects of fluctuation in the drain lines, and thus, the image quality deteriorates (lateral smearing), so that the display brightness becomes different from the desired display brightness due to delay in the convergence of the fluctuation of the common potential, and thus, it is a goal to prevent the image quality from deteriorating (lateral smearing). In RGB time division drives, the order of time division is switched for each frame, or in the direction of the horizontal lines. |
| US09646551B2 |
Display control system, processor, controller, and display control method
A processor determines a drive scheme from among candidates of a plurality of drive schemes having differing schemes for supplying a signal to a signal line of a display panel. A controller stores a scheme drive information in which a drive scheme information and a signal control information in a drive scheme are associated. A controller receives a scheme information from a processor, and controls a signal supplied to a signal line of a display panel, the control being made based on a scheme information and a scheme drive information. |
| US09646548B2 |
Custom PSFs using clustered light sources
Light sources of a backlight are configured to customize the shape of light emitted from the clusters. The clusters are activated as a unit and modulated as to brightness, but of the customized shape. All clusters can have a similar customized PSF, or the customization of each cluster may be varied in real time. Real time changes of a clusters PSF may be based, for example, an image or a region of the image to be displayed using the clusters. |
| US09646542B2 |
Display device compensating IR-drop of supply voltage
A gate driver circuit includes a gate driver coupled to a gate line. The gate driver generates a gate signal for input to a plurality of pixels and controls a current of the gate signal based on an IR-drop of a supply voltage supplied to the pixels through a supply voltage distribution line. The gate driver decreases the current of the gate signal when the IR-drop increases, and increases the current of the first gate signal when the IR-drop decreases. A pulse width of an activation period of the gate signal decreases and luminance of the pixels increases when the current of the first row pixels decreases. |
| US09646541B2 |
Display device
A display device is disclosed. In one aspect, the display device includes a display panel including gate lines and pixels electrically connected to the gate lines, the pixels comprising a first pixel row and a second pixel row having a fewer number of pixels than the first pixel row. The display device also includes a gate driver including stages, each configured to output a gate signal to the respective gate line, the gate lines comprising first and second gate lines respectively connected to the first and second pixel rows, and the stages comprising first and second stages respectively connected to the first and second gate lines. An output transistor of each stage is configured to output the gate signal and the channel width of the output transistor of the first stage is greater than that of the output transistor of the second stage. |
| US09646538B2 |
Light emitting period setting method, driving method for display panel, driving method for backlight, light emitting period setting apparatus, semiconductor device, display panel and electronic apparatus
Disclosed herein is a light emitting period setting method for a display panel wherein the peak luminance level is varied through control of a total light emitting period length which is the sum total of period lengths of light emitting periods arranged in a one-field period, including a step of setting period lengths of N light emitting periods, which are arranged in a one-field period, in response to the total light emitting period length such that the period lengths of the light emitting periods continue to keep a fixed ratio thereamong, N being equal to or higher than 3. |
| US09646536B2 |
Pixel circuit for organic light emitting display and driving method thereof, organic light emitting display
A pixel circuit for an organic light emitting display includes first, second, third, fourth, fifth, and sixth MOS transistors, a first capacitor, and an organic light emitting diode. The gate electrode of the first MOS transistor receives a first scanning signal. The first electrode of the first MOS transistor receives a data signal. The gate electrode of the third MOS transistor receives a control signal. The gate electrode of the fourth MOS transistor receives the first scanning signal. The gate electrode of the fifth MOS transistor receives the control signal. The first electrode of the fifth MOS transistor receives a reference voltage. The gate electrode of the sixth MOS transistor receives a second scanning signal. The first electrode of the sixth MOS transistor receives the reference voltage. |
| US09646532B2 |
Display device, driving method for display device and electronic apparatus
A display device includes a pixel array unit that is formed by disposing pixel circuits that include a P-channel type drive transistor that drives a light-emitting unit, a sampling transistor that applies a signal voltage, a light emission control transistor that controls light emission and non-light emission of the light-emitting unit, a storage capacitor that is connected between a gate electrode and a source electrode of the drive transistor and an auxiliary capacitor, a first end of which is connected to the source electrode of the drive transistor, and a drive unit that, during threshold correction, applies a standard voltage that is used in threshold correction to the gate electrode of the drive transistor in a state in which the source electrode of the drive transistor has been set to a floating state, and subsequently applies a pulse signal to a second end of the auxiliary capacitor. |
| US09646531B2 |
Element substrate and light emitting device
A light emitting device and an element substrate which are capable of suppressing variations in luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. A gate potential of a driving transistor is connected to a first scan line or a second scan line, and the driving transistor operates in a saturation region. A current controlling transistor which operates in a linear region is connected in series to the driving transistor. A video signal which transmits a light emission or non-emission of a pixel is input to the gate of the current controlling transistor through a switching transistor. |
| US09646530B2 |
Organic light-emitting display apparatus having repair lines
An organic light-emitting display apparatus includes: a plurality of emitting pixels coupled to a plurality of scan lines extending in a row direction and a plurality of data lines extending in a column direction; a plurality of dummy pixels arranged in the row direction; a plurality of first repair lines extending in the column direction, that are coupled to the plurality of dummy pixels, and that are adapted to be coupled to the plurality of emitting pixels; a plurality of second repair lines extending in the column direction, and that are coupled to the plurality of dummy pixels; and a plurality of repair switching devices arranged in a matrix array and adapted to be coupled to the plurality of scan lines and the plurality of second repair lines and adapted to be coupled to the plurality of data lines. |
| US09646528B2 |
Image display device and method of displaying image
An image display device includes an image display unit including first pixels including sub-pixels of three or more colors in a first color gamut, and second pixels including sub-pixels of three or more colors in a second color gamut different from the first color gamut; a processing unit that determines an output of the sub-pixels of the first pixel based on a combined component of a first component and an out-of-color gamut component, and determines an output of the sub-pixels of the second pixel based on a third component by eliminating the out-of-color gamut component from a second component; and a determination unit that determines whether the input image signal corresponds to an edge of an image. When the input image signal corresponds to the edge of the image, the processing unit causes the out-of-color gamut component not to be reflected in an output of the first pixel. |
| US09646522B2 |
Enhanced information delivery using a transparent display
Information is delivered about a particular external environment using a transparent display. In one embodiment, a method includes determining a position of a mobile transparent display, determining an orientation of the display, retrieving information about the environment of the display using the determined position and orientation, and overlaying the retrieved information over a view on the transparent display. |
| US09646519B2 |
Paint stick and marker installation system
A paint stick and marker installation system for inserting a marker having shaft with a bottom end for inserting into the ground and an engagement portion of the shaft separated from the bottom end by an insertion portion of the shaft. The apparatus includes a magazine assembly configured to receive at least one marker. The magazine space has a push position in the magazine space for receiving the at least one marker. The apparatus further comprises a push assembly mounted on the magazine assembly. The push assembly is configured to engage the engagement portion of the shaft of the marker located in the push position and push the marker from the magazine assembly when the push assembly is actuated. A plurality of the markers are bonded together such that each of the markers can be removed from the rest of the plurality when inserting a marker into the ground. |
| US09646516B2 |
Masking and unmasking methods and devices
Devices and methods for masking and unmasking sensitive data, based on a standard cryptographic algorithm defining a ciphering algorithm, and a deciphering algorithm using more resources than the ciphering algorithm are described. The masking of sensitive data is done by applying the deciphering algorithm to the sensitive data to obtain masked sensitive data. The unmasking of the masked sensitive data is done by applying the ciphering algorithm to the masked sensitive data to obtain sensitive data in plain form. |
| US09646507B2 |
Rotorcraft collision avoidance system and related method
A method of operating a rotorcraft collision avoidance system is provided. The method includes determining a unique characteristic of a detected rotorcraft, determining the actual length of a first rotor based at least in part on the determined unique characteristic of the rotorcraft, locating a major axis of the first rotor of the rotorcraft from a perspective of a home unit, from the perspective of the home unit, determining an angular extent of the major axis of the first rotor, and determining the then current distance from the home unit to the rotorcraft based at least in part on the determined actual length of the first rotor and the corresponding angular extent. |
| US09646504B2 |
Flight deck displays to enable visual separation standard
Systems and methods that display information to enable a flight crew on a trailing aircraft to maintain separation behind a leading aircraft during an approach. Graphical designs are displayed on a navigation display or other display in the flight deck of the trailing aircraft to help the flight crew visually acquire the leading aircraft out the window and maintain at least a specified separation distance or spacing between the two aircraft even if visual contact is lost after the initial visual contact. A visual indication is provided on the display if that separation distance/spacing is attained. If for some reason the flight crew misses that visual indication and the trailing aircraft continues to get closer to the leading aircraft, another visual indication is provided, followed by an aural alert when a minimum safe spacing is reached. |
| US09646503B2 |
Cockpit display systems and methods for generating navigation displays including landing diversion symbology
Cockpit display systems and methods for generating navigation displays including landing diversion symbology are provided. In one embodiment, the cockpit display system includes a cockpit monitor and a controller coupled to the cockpit monitor. The controller is configured to assess the current feasibility of landing at one or more diversion airports in a range of an aircraft on which the cockpit display system is deployed. The controller is further configured to assign each diversion airport to one of a plurality of predetermined landing feasibility categories, and generate a horizontal navigation display on the cockpit monitor including symbology representative of the feasibility category assigned to one or more of the diversion airports. |
| US09646502B1 |
Universal unmanned aerial vehicle identification system
This disclosure is directed to an automated unmanned aerial vehicle (“UAV”) self-identification system, devices, and techniques pertaining to the automated identification of individual UAVs operating within an airspace via a mesh communication network, individual UAVs and a central authority representing nodes of the mesh network. The system may detect nearby UAVs present within a UAV's airspace. Nearby UAVs may self-identify or be identified via correlation with one or more features detected by the UAV. The UAV may validate identifying information using a dynamic validation policy. Data collected by the UAV may be stored in a local mesh database and distributed to individual nodes of the mesh network and merged into a common central mesh database for distribution to individual nodes of the mesh network. UAVs on the mesh network utilize local and central mesh database information for self-identification and to maintain a dynamic flight plan. |
| US09646500B2 |
Method for requesting transportation services
A method for safely and efficiently requesting transportation services through the use of mobile communications devices capable of geographic location is described. Individual and package transportation may be provided. New customers may be efficiently serviced, and the requester and transportation provider locations may be viewed in real time on the mobile devices. |
| US09646498B1 |
Systems and methods for live and replay utilization and tracking of vehicular movement and response
Systems and methods for live utilization and tracking of vehicular movement producing a fluid representation of the movement of vehicles and means to evaluate vehicle movement/activities relative to response requirements may be provided. Accordingly, real-time evaluations and/or corrections may be made based on this improved tracking of movement/activities. Replay analysis of movement/activities that have already occurred may be provided to evaluate and make adjustments for future responses and activities. Colors and other unique display items may be used to highlight different activities, movements and/or timing for completion within an online mapping application. Layering of different mapping displays also may be provided. |
| US09646495B2 |
Method and system for traffic flow reporting, forecasting, and planning
A street lighting and traffic control system and method employing sensor technologies. Conventional sensors and processors are linked together by a wireless mesh communications architecture that may also be interfaced through one or more gateways into one or more monitoring and control centers. Traffic flow reporting, control and forecasting using a street lighting and traffic control network that includes a series of street lighting fixtures. |
| US09646489B2 |
Remote control method and apparatus for home appliances
A remote control method and an apparatus for home appliances, wherein a remote controller performs situation recognition using sensors and automatically controls home appliances without a control message from a portable device when communication with the portable device is not possible, are provided. The remote control method is designed for a remote controller managing home appliances installed in a home. The remote control method includes receiving a remote control request from a portable device capable of remotely controlling one or more home appliances, performing, upon reception of the remote control request, situation recognition with respect to the home appliances, and controlling operations of the home appliances based on situation recognition results. |
| US09646487B2 |
Process control alarm auditing
Methods, apparatus, systems and articles of manufacture are disclosed to audit process control alarms. An example disclosed method includes identifying components in the process control system that correspond to alarms to be audited. The example method also includes if a query to request a status of a particular one of the alarms to be audited is not in a status update queue, generating a query associated with the audit report request to request the status of the particular one of the alarms from the corresponding component. Otherwise, if the query to request the status of a particular one of the alarms to be audited is in the status update queue, associating the audit report request to the query. The example method also includes transmitting, via a process control system bus, the queries to be designated as low priority. |
| US09646481B2 |
Alarm setting and interfacing with gesture contact interfacing controls
A device configured for capture of activity data for a user includes a housing, a sensor, a motor, a memory, and a processor. The sensor is disposed in the housing to track activity data of the user. The motor causes vibration of the housing. The memory stores an alarm setting that defines a time of day for triggering an alarm on the device. The processor activates the alarm upon reaching the time of day defined by the alarm setting, with the alarm causing the motor to produce the vibration of the housing. The sensor, which is interfaced with the processor, is configured to detect a current level of activity of the user. The processor is configured to automatically deactivate the alarm if the current level of activity qualifies for deactivating the alarm. The deactivating of the alarm causes the vibration of the device to be suspended. |
| US09646476B1 |
Gas-monitoring and fall detection device
The gas monitoring and fall detection device is a safety device intended to be worn by special duty personnel, such as maintenance people, who do not work in a set location and may inadvertently stray into dangerous situations. The gas monitoring and fall detection device monitors the working environment for dangerous gas levels and, when a dangerous gas level is detected, generates an alarm to the wearer and transmits an alarm to a supervisory station. The gas monitoring and fall detection device also contains an accelerometer to detect falls and a GPS module to provide the location of the wearer. The gas monitoring and fall detection device comprises a monitoring unit that is worn by the wearer and a supervisory station to receive the transmitted alarm information. |
| US09646473B2 |
Interchangeable personal security device
An apparatus for personal security is disclosed that includes a wearable accessory formed to receive an alerting device such that the alerting device is not visible while the accessory is worn. The apparatus includes an alerting device with an alerting element. The alerting device is interchangeable with a plurality of wearable accessories. One or more activation elements are disposed on the wearable accessory and formed to activate the alerting device wherein the alerting element sends an alert signal in response to receiving an activation signal from the one or more activation elements. In one embodiment, the alerting device is in wireless communication with a communication device and sends an alert signal to the communication device in response to receiving the activation signal. In another embodiment, the communication device notifies one or more predefined contacts that an alert signal was sent in response to receiving the alert signal. |
| US09646472B2 |
Tamper evident systems
The invention disclosed is a tamper detection element to locate against a first member to detect tampering. The element has a resilient deformable member able to deform because of tamper induced deformation, a contact sensing member disposed towards the resilient deformable member, a first electrically conductive portion adjacent or on the resilient deformable member, and a second electrically conductive portion on the contact sensing member. An electrical relationship can then be formed between the first and second electrically conductive portions, and the tamper induced deformation results in a change of impedance of the electrical relationship, the change therefore indicative of the tampering. |
| US09646469B2 |
Visual and touch interaction display
A sensory display for experiencing rigidity and local shape in the display is provided. Rigidity and local shape of cells in an array of cells forming the display is controlled by three independent and different control mechanisms. Cell rigidity controllers control the rigidity of the cells. A shape array controller controls the shape of the array of cells. Cell pinning controllers controls the height of the cells. A computer control interface could control the respective control functionalities of each of the controllers. The display experience could be further enhanced with audio, images or video. |
| US09646462B2 |
Method and apparatus for awarding at least one jackpot prize
At step 40 the parameters for the jackpot are initialized, including a storage criterion and an award criterion. At step 41 the current value of the jackpot prize pool is calculated. At step 42 the CPU 2 checks whether the storage criterion has been met. If so, the currently accumulated value of the jackpot prize pool is stored at step 43 in memory 6 as a pending jackpot, along with the award criterion that is associated with that pending jackpot. The jackpot parameters are then redefined and the accumulation of as new jackpot prize pool is ready to commence. A number of pending jackpots may be concurrently stored in memory 6, each with an associated stored award criterion. At step 46 the CPU 2 determines if any of the award criterions that are associated with the pending jackpots have been met and if so, the associated pending jackpot prize is awarded at step 47 in accordance with a jackpot prize distribution scheme. |
| US09646459B2 |
Incentive apparatus for gambling game systems
An incentive apparatus for a gambling game system aims to increase the odds thereof. The gambling game system includes a betting table and a plurality of game results. The betting table has payout odds marked thereon corresponding to different game results of the gambling game system. The incentive apparatus includes a dynamic raised odds calculation element, an electronic display board and a payout element. The dynamic raised odds calculation element randomly selects a specific number of the game results and generates dynamic raised odds for the selected game results respectively. The electronic display board has a plurality of display zones corresponding to the game results. The display zones immediately display the dynamic raised odds after betting of each round of game stops. The payout element pays out to players who win the round of the game according to the payout odds or the dynamic raised odds. |
| US09646458B2 |
Gaming system, gaming device and method having secondary symbols associated with primary symbols
A gaming system including a plurality of generated primary symbols and at least one generated secondary symbol. If any generated primary symbol is associated with any generated secondary symbol, the gaming system provides an award based on the generated primary symbol being associated with the generated secondary symbol. |
| US09646457B2 |
Gaming system and method for providing enhanced wagering opportunities
A gaming system including a central server linked to a plurality of gaming machines. In one embodiment, the gaming system provides players with one or more enhanced wagering opportunities. One enhanced wagering opportunity enables a player to continue playing one or more primary games at the maximum wager even if the player's continued play causes the gaming device's credit meter to fall below zero credits. In one such embodiment, after playing one or more maximum wager games which cause the credit meter to drop below zero, the player's player tracking account is utilized to cover any amount of credits the gaming device's credit meter is below zero. |
| US09646455B2 |
Integrating social networking and wagering systems
A wagering game system and its operations can include connecting, via a network communication interface of a gaming system, a device associated with a social networking venue to the gaming system. The operations can further include detecting, via the network communication interface, an indication of an electronic event associated with the gaming system and determining, via analysis of the indication of the electronic event by the gaming system, a value associated with the electronic event. The operations can further include activating a feature of the social networking venue according to the value associated with the electronic event. |
| US09646446B2 |
Game system
A game system includes: a bill identifying apparatus for identifying bills of different currencies and an amount of the bills and then outputting data representing the identified result; a player tracking device which is integrated with each of gaming machines, for converting data outputted from the bill identifying apparatus to credit data for executing a game, based on an exchange rate; and an information card device which is integrated with the player tracking device, the information card device causing an information card to store data equivalent to an amount awarded to a player in accordance with a game result of the gaming machines and sending out the credit data for executing the game to the gaming machines, based on the data equivalent to the amount read from the information card. |
| US09646436B1 |
Gesture controls for remote vehicle access systems
A method and apparatus for hands-free activation of vehicle functions such as accessing doors and windows, and establishing driver preferences such as seat positions is disclosed. A capacitive sensor is embedded in a non-metallic portion of the vehicle such as a tail light, window, or cladding on the vehicle. The capacitive sensor is in communication with a vehicle control unit, which can detect the proximity of a user or a specific gesture to activate a predetermined vehicle function. |
| US09646434B2 |
Method and system for controlling access to a restricted location
The present disclosure describes techniques for controlling access a restricted location (114) as well as a system (100) for doing so. According to various implementations, a potential entrant to the restricted location needs to transmit two values to an access authorization device (108) located at the perimeter (112) of the restricted location in order to gain access. In one implementation, the system provides an authentication code to a first device (116) (e.g., a smartphone) via wireless communication link (120) (e.g., over a cellular network) and displays a visual image (127) with an embedded access code at a display device (104). The second device (118), which is securely paired with the first device, captures the image and sends the image data to the first device. Using the authentication code and the access code, the first device derives the two values to gain access to the restricted location. |
| US09646429B2 |
Apparatus, methods and computer program product for thermal management of user equipment coupled to a vehicle
Apparatus, a method and a computer program product periodically determine one or more temperature thresholds and configuration settings attributable to one or more user equipment coupled to a vehicle. The one or more determined temperature thresholds and configuration settings are sent to the one or more user equipment in a thermal management scheme message. The one or more user equipment are adapted to adjust an operational threshold in response to the received thermal management scheme message. |
| US09646427B2 |
System for detecting the operational status of a vehicle using a handheld communication device
A system which utilizes the on-board capabilities of handheld communication devices, such as smartphones, tablet computers and the like, to detect the operational status of a vehicle, such as the engine being ON, the engine idling, the vehicle moving, etc. The detected operational state may be desirable for monitoring operation of the vehicle, such as fleet management systems, wherein the duration and location of idling are of particular interest. The detected operational state may also be useful for controlling functionality on the handheld communication device, such as disabling texting or other manually operated functions when the vehicle is in motion. |
| US09646424B2 |
Methods and processes for interactive display of three dimensional covariance
A system and method for displaying a three-dimensional surface along with ellipsoids representing covariances. In one embodiment, at a point on a three dimensional surface, an ellipsoid is formed having principal axes proportional to the eigenvalues of a covariance matrix. The ellipsoid and the three-dimensional surface are projected onto a two-dimensional plane for display on a two-dimensional screen to a user. The covariance matrix may be an estimated error covariance or a sample covariance. |
| US09646420B2 |
Display control method and information processing apparatus
An information processing apparatus includes circuitry configured to: control an imaging device to stop a first focus adjustment when a specific object is detected from a first image captured by the imaging device while the first focus adjustment is in execution, the first focus adjustment being performed at each first time interval by the imaging device, and control the imaging device to start a second focus adjustment when the specific object is not detected from a second image captured by the imaging device after the imaging device is controlled to stop the first focus adjustment. |
| US09646417B1 |
Augmented reality system for field training
A method and apparatus for displaying simulation objects. A simulation of a live environment is run while a training device is present in the live environment. A set of simulation objects in the simulation is identified from a number of simulation objects in the simulation using a position of the training device in which the set of simulation objects is visible to the training device in the live environment. Simulation data is generated for the set of simulation objects. The simulation data is sent to the training device in the live environment. |
| US09646414B2 |
Systems and methods for modeling 3D geological structures
Systems and methods for modeling a three-dimensional (3D) geological structure to improve maximum continuity interpolation. An integration method describes local anisotropic effects and introduces interpolation techniques to perform the interpolation between two points of interest along a direction of maximum continuity and across fault surfaces. |
| US09646413B2 |
System and method for remote shadow rendering in a 3D virtual environment
A method for rendering shadows in a 3D virtual environment includes generating a depth rasterization map corresponding to a plurality of objects in a three-dimensional virtual environment and a shadow interval map with reference to the depth map and a predetermined path of a light source in the environment that casts light onto at least one object in the plurality of objects that generates a shadow in the three-dimensional virtual environment with a server computing device. The method includes transmitting the shadow interval map from the server to a client and generating, with a processor in the client, a graphical depiction of the virtual environment including at least one shadow generated with reference to the shadow interval map, the at least one shadow corresponding to the light source and the plurality of objects in the virtual environment. |
| US09646412B1 |
Pre-sorted order independent transparency
In one embodiment, a computer-implemented method for rendering a three-dimensional computer-aided design model includes storing in a computer memory a subset of data fragments for a certain pixel location, receiving a next data fragment, and determining whether the next data fragment has a depth value indicating a position closer to a viewer than any one of the data fragments in the subset, in which case, the next data fragment replaces the data fragment in the subset having a depth value indicating a position farthest from the viewer. The subset is sorted according to respective depth values of each of the data fragments in the subset, and a blending process is performed to compute a pixel value representing a transparency characteristic of the three-dimensional computer-aided design model at the certain pixel location. |
| US09646409B2 |
Generation of a display data set with volume rendering
A display data set depicting a three-dimensional source data set of display parameters is generated through volume rendering. Integration distance is subdivided based on a fixed predetermined target sampling distance independent of a desired sampling distance. The number of subsections minus one correspond to integrations over different subsections with front and back values of the display parameter as a target sampling distance opacity. A contribution of the volume-rendering integral and a target sampling distance color coefficient are based on the target sampling distance opacity. Target sampling distance opacities and target sampling distance color coefficients are determined based on pre-integration tables for contributions of the volume-rendering integral. Third opacities are calculated and converted to the desired sampling distance from target sampling distance opacities and the ratio of desired sampling distance to target sampling distance. Third color coefficients are calculated, and the volume-rendering integral is determined from the contributions. |
| US09646407B2 |
Flexible display apparatus and flexible display apparatus controlling method
A flexible display apparatus and a method configured to display three-dimensional (3D) space is disclosed. The flexible display apparatus includes a display that is deformable and is configured to display three-dimensional (3D) image data, a sensor configured to sense deformation of the display, and a controller configured to display some of the 3D image data corresponding to the sensed deformation of the display. The method for controlling a flexible display apparatus with a display includes sensing deformation of a display, and displaying some three-dimensional (3D) image data corresponding to the deformation when the deformation is bending of the display. |
| US09646405B2 |
Image processing device, image processing method and program
According to an illustrative embodiment, an image processing device is provided. The image processing device includes a foreground selection processing circuit to select at least one foreground image that has been separated from a source image; a background selection circuit to select at least two display background images from at least one background image that has been separated from the source image; and a combination circuit to combine the at least one selected foreground image with the at least two display background images to generate a plurality of combined images, wherein at least one of the plurality of combined images does not appear in the source image. |
| US09646404B2 |
Information processing method, information processing device, and program that facilitates image processing operations on a mobile device
An information processing method for causing a computer to process an image, wherein the image processing method causes the computer to execute an acquisition step of acquiring the image, and an output step of outputting an output image by separating between an editing area that is a predetermined area where the image is editable on the image and a changing area other than the predetermined area on the image, wherein, in a case where an operation is done on the changing area, the editing area is moved, and in a case where an operation is done on the editing area, the editing area is not moved. |
| US09646403B2 |
Image processing apparatus, image processing method, and non-transitory computer-readable storage medium
An image processing apparatus inputs an image and then reads out, from a memory, to perform image processing for an image of a second region of the input image, an image of a region superimposed on the second region, and an image of a part of a first region adjacent to the second region, and controls a position of padding, wherein the padding results from image reduction of the first region, performed before the image processing for the image of the second region, so that the padding that results from the image reduction of the first region is not read out for the image processing for the image of the second region. |
| US09646398B2 |
Minimizing blur operations for creating a blur effect for an image
A processing device receives input representing a selection of one or more areas of an image and creates a blurred area for the one or more selected areas. The blurred area corresponds to a portion of the image that contains the one or more selected areas. The portion of the image has a size that is greater than an aggregate size of the one or more selected areas. The processing device replaces the one or more selected areas with the corresponding portion of the blurred area. |
| US09646394B2 |
Case data visualization application
A case data visualization application is provided that, when executed on a device, allows a user to visualize a chronology of events associated with a case, view a summary of one or more supporting details of an event, and drill-down to view specific case data of each supporting detail of an event. Thus, the case data visualization application provides a way of collecting, organizing, visualizing, and sharing data associated with a case. Furthermore, the case data visualization application allow a plurality of users to collaborate on the case, and synchronizes a plurality of supporting details created by a plurality of users that are associated with an event. |
| US09646390B2 |
Parallel image compression
Methods, apparatus, and computer readable media are provided for image compression. Edge elements of an image comprising pixels are established by analyzing pixel values associated with the pixels of the image. The edge elements are organized in an edge data structure having at least two dimensions. The edge data structure is compacted along a first dimension by arranging the established edge elements adjacent to each other along the first dimension in a compacted edge data structure. Compressed edges in a second dimension in the compacted edge data structure are determined by: determining edge elements to be joined along a second dimension in the compacted edge data structure based on pixel values of neighboring edge elements, along the second dimension, in the compacted edge data structure; and compressing the image by encoding formed edges, the edges being formed by joining the determined edge elements. |
| US09646387B2 |
Generation of event video frames for content
According to some aspects, methods and systems may include receiving, by a computing device, metadata identifying an event occurring in a video program, and determining an expected motion of objects in the identified event. The methods and systems may further include analyzing motion energy in the video program to identify video frames in which the event occurs, and storing information identifying the video frames in which the event occurs. |
| US09646385B2 |
System and a method for generating a depth map
A computer-implemented system for generating a depth map for a pair of stereoscopic images, the system comprising a lower level processing arrangement and a higher level processing arrangement. The lower level processing arrangement comprises a search range estimation module receiving a reliability map and configured to determine a range of considered disparities in a higher level of processing wherein a decision regarding such range is taken based on the reliability map. The higher level processing arrangement comprises a depth map generation with reliability module receiving output of an image sections matching module configured to output a depth map and a reliability map wherein the reliability map comprises data on reliability, with which a disparity value has been determined for each point of the pair of stereoscopic images. |
| US09646383B2 |
Image processing apparatus, image capturing apparatus, and display apparatus
An image processing apparatus includes an image processing intensity determination unit that determines an intensity of image processing and an image processing unit that performs the image processing to image information in accordance with the intensity determined by the image processing intensity determination unit. The image processing intensity determination unit determines the intensity of the image processing at a target pixel included in the image information on the basis of a depth value indicating a depth corresponding to the target pixel and a vertical position of the target pixel in the image information. |
| US09646381B2 |
State-of-posture estimation device and state-of-posture estimation method
This posture state estimation device is capable of estimating with high accuracy the posture state of an object. The posture state estimation device (100) is a device for estimating the posture state of an object having a plurality of sections connected by joints on the basis of image data that images the object, and has a section candidate extraction unit (140) for extracting a section candidate for a section from the image data, a complementary section candidate extraction unit (160) which estimates that a portion of an unextracted section for which a section candidate has not been extracted is being shadowed by an already extracted section for which a section candidate has been extracted in order to extract a section candidate of the unextracted section, and a posture state estimation unit (170) for estimating the posture state of the object on the basis of the extracted section candidate. |
| US09646380B2 |
Image-data processing device and image-data processing method
The application discloses an image data processing device for generating output image data which represents an output image including a first region image to be displayed in a first region and a second region image to be displayed in a second region adjacent to the first region. The image data processing device includes an extractor configured to extract a part of first image data representing a first image as first extraction data representing the first region image and a part of second image data representing a second image to be viewed and compared simultaneously with the first image as second extraction data representing the second region image. The extractor processes the first extraction data and the second extraction data to generate the output image data. |
| US09646379B1 |
Detection of selected defects in relatively noisy inspection data
Methods and systems for detection of selected defects in relatively noisy inspection data are provided. One method includes applying a spatial filter algorithm to inspection data acquired across an area on a substrate to determine a first portion of the inspection data that has a higher probability of being a selected type of defect than a second portion of the inspection data. The selected type of defect includes a non-point defect. The inspection data is generated by combining two or more raw inspection data corresponding to substantially the same locations on the substrate. The method also includes generating a two-dimensional map illustrating the first portion of the inspection data. The method further includes searching the two-dimensional map for an event that has spatial characteristics that approximately match spatial characteristics of the selected type of defect and determining if the event corresponds to a defect having the selected type. |
| US09646378B2 |
Information processing apparatus, information processing method, program, and measuring system
There is provided an imaging unit comprising at least one image sensor, a measuring instrument including at least one marker, a position computing unit, a determining unit, and an output controller, wherein the imaging unit is configured to acquire an image comprising a user and the marker, and provide the acquired image to the position computing unit, wherein the position computing unit is configured to compute a position of the marker with respect to the user based on the image provided by the imaging unit, and further provide the computed position to the determining unit, wherein the determining unit is configured to determine whether the computed position of the marker matches a retrieved measurement position, and further output the result of the determination to the output controller, and wherein the output controller is configured to provide an indication when the marker position matches the measurement position. |
| US09646377B2 |
Methods and systems for optical imaging or epithelial luminal organs by beam scanning thereof
Arrangements, apparatus, systems and systems are provided for obtaining data for at least one portion within at least one luminal or hollow sample. The arrangement, system or apparatus can be (insertable via at least one of a mouth or a nose of a patient. For example, a first optical arrangement can be configured to transceive at least one electromagnetic (e.g., visible) radiation to and from the portion. A second arrangement may be provided at least partially enclosing the first arrangement. Further, a third arrangement can be configured to be actuated so as to position the first arrangement at a predetermined location within the luminal or hollow sample. The first arrangement may be configured to compensate for at least one aberration (e.g., astigmatism) caused by the second arrangement and/or the third arrangement. The second arrangement can include at least one portion which enables a guiding arrangement to be inserted there through. Another arrangement can be provided which is configured to measure a pressure within the at least one portion. The data may include a position and/or an orientation of the first arrangement with respect to the luminal or hollow sample. |
| US09646376B2 |
System and method for reviewing and analyzing cytological specimens
Systems and methods of use to facilitate classification of cytological specimens are discussed. The system acquires or imports image data of a cytological specimen. The imported image data may include, or the system may otherwise perform an image analysis to identify one or more objects of interest in a respective specimen image dataset, including feature attributes for the identified objects. The system analyzes the feature attributes by predetermined criteria and/or optionally with user inputted criteria. The system includes an analysis tool that assists the user in identifying cytologically abnormal objects, if present in a particular specimen, by manipulating and viewing images of objects selected as a function of feature attributes. More generally, the analysis tool aides the user to find, extract, and display abnormal objects from within a large dataset of images and facilitates navigation through large amounts of image data and enables the efficient classification of the entire specimen. |
| US09646375B2 |
Method for setting a blood transfusion parameter
One variation of a method for setting a blood transfusion parameter for a patient includes identifying a blood transfusion bag in a photographic image; extracting a color feature from a region of the photographic image corresponding to the blood transfusion bag; estimating a blood component content within the blood transfusion bag based on the color feature; and triggering transfusion from the blood transfusion bag based on the blood component content within the blood transfusion bag and an estimated volemic status of the patient. |
| US09646370B2 |
Automatic detection method for defects of a display panel
An automatic detection method for defects of a display panel is disclosed, which comprises: acquiring a tag image, a mapped original image and a mapped tag image; dividing the mapped original image into a plurality of mapped original sub-images, and dividing the mapped tag image into a plurality of mapped tag sub-images; acquiring a normal area and a defective area of the mapped original sub-images; merging the mapped original sub-images to discriminate the normal area and the defective area of the mapped original sub-images; correcting the discriminated normal area and the discriminated defective area of the mapped original sub-images by using the mapped tag image and the tag image to acquire a defect location of the display panel. The automatic detection method for defects of the display panel can accurately acquire the location of the defect and the difference between the defective area and the normal area to quantify and discriminate the defects of the display panel. |
| US09646365B1 |
Variable temporal aperture
An system having an aperture configured to change state while recording one or more images during an image capture process, and a method for processing one or more recorded images by detecting at least a bokeh artifact within the one or more images and processing the images based at least in part on information obtained by analyzing the size and orientation of the bokeh artifact. |
| US09646363B2 |
Image processing apparatus and method for detecting object using equi-height mosaicking image, and vehicle operation assisting system employing same
Provided is an image processing device including: an area extraction unit extracting areas corresponding to size of a predetermined target object from an image; a mosaicking image creation unit connecting extracted areas to create a mosaicking image; and an object detection unit detecting an object from the mosaicking image. |
| US09646362B2 |
Algorithm for improved zooming in data visualization components
Example embodiments reduce the processing required to zoom on graphical data visualizations by transforming only graphic elements visible in the zooming viewport. In one example embodiment, a grid overlays the component image. Prior to zooming, grid elements covered by the zooming viewport are determined and only graphic objects bounded by those grid elements are transformed during zooming. |
| US09646361B2 |
Initialization independent approaches towards registration of 3D models with 2D projections
A method of registering a 3-dimensional (3D) model of a coronary artery tree with 2-dimensional (2D) images includes solving for matrices R, Pi, i=1, . . . , N, that minimize a cost function Σi=1N∥ΨiRX−IiPi∥2,1 subject to constraints that R∈conv(SO(3)), Pi∈[0,1]ni×m, and Pi1≦1, 1TPi=1, for i∈{1, N}, where N is a number of 2D images, R is a rotation matrix, conv(SO(3)) denotes a convex hull of the special orthogonal group in 3 dimensions, X denotes a 3D centerline model of a coronary artery tree, Ii denotes the ith 2D image, Ψi denotes a transformation between the 3D centerline model X and the ith 2D image Ii, 1 is an all-ones vector, Pi is a permutation matrix, and rounding a solution R to a nearest orthogonal matrix R* in SO(3), where R* aligns the 3D centerline model X of the coronary artery tree with 2D fluoroscopic images acquired during a percutaneous coronary intervention procedure. |
| US09646352B2 |
Parallel echo version of media content for comment creation and delivery
Methods, systems, and devices are described for associating comments with playback of media content. At an input device, a parallel echo version of media content being played on a second device is provided, and a selection is received of a portion of the parallel echo version of the media content. A comment associated with the selected portion of the parallel echo version of the media content is received, and the received comment is associated with a portion of the media content associated with the selected portion of the parallel echo version. At an output device, a parallel echo version of media content being played on a second device is provided, a current point in the parallel echo version of the media content is determined, and an indicator of a comment associated with a point in the media content corresponding to the current point in the parallel echo version is displayed. |
| US09646348B2 |
Informative graphical representation of individual net worth system, method and software
Net worth can be graphically represented as dollars versus time. A user can zoom in on a desired section of the graphical representation in order to better discern short term net worth trends. On the zoomed in image, time and or dollars may be truncated in order to show net worth trends more distinctly. The slope of the curve between two net worth points or at any single net worth can be computed and graphically displayed to a user so that the user can understand short term net worth trends an modify behavior to improve long term net worth trends. |
| US09646346B2 |
Methods, devices and systems for automatically triggering data collection events and collecting insurance rating data
The devices, methods, systems and computer-readable mediums of the present disclosure provide automatic data collection for insurance rating purposes. In particular, a battery powered Bluetooth device may be attached to a personal item of an insured individual. The Bluetooth device may automatically trigger a mobile telephone to begin storing data related to use of the personal item when the mobile telephone is proximate the Bluetooth device. The mobile telephone may periodically transmit the stored data to a remote server. |
| US09646344B2 |
System and method for chart based order entry
Systems and methods for chart-based order entry are described. According to one example method a chart is used to display historical market data corresponding to a tradeable object. An order entry interface is displayed in relation to the chart. The order entry interface includes a plurality of price objects for selecting price levels to be used for trade orders to buy or sell the tradeable object. According to one example method, the price levels corresponding to the price objects depend on a location of the interface in relation to the chart, and as the interface is moved in relation to the chart, the price levels are automatically updated. Upon selection of the price level on the interface, a trade order to buy or sell is submitted to a matching engine at an electronic exchange. |
| US09646343B2 |
Systems and methods for interactively disambiguating entities
The disclosure relates to entity disambiguation in an interactive fashion based upon attributes. Once disambiguated, a manner in which to review a future article based upon an initial set of attributes and an additional set of attributes and, when needed, generate a warning flag based upon the review is also described. The warning flag may result in a change in the relationship between the entity and an organization such as a bank that is considering engaging in a business relationship with a candidate client, and that may subsequently abandon that plan, or a bank that had previously extended credit to the entity, and that subsequently may be less inclined as a result of the information retrieved by the present invention. A previously accepted entity may also be flagged for credit or anti-money laundering consideration if and when the applicant's situation (e.g., financial situation, involvement in anti-money laundering) changes. |
| US09646342B2 |
Remote control for online banking
Disclosed is a system and associated method of using a customer's mobile device as an online banking remote control for another customer device. The system typically includes a processor, a memory, and an online banking module stored in the memory. The module is typically configured for (i) associating the mobile device with the customer's online banking account and (ii) binding the mobile device to another computing device. In addition, the module is typically configured for subsequently receiving a remote access command associated with the customer's online banking account and associated with the computing device from the mobile device. The remote access of the computing device to the customer's online banking account can then be modified based on the remote access command and determining that (i) the mobile device is associated with the customer's online banking account and (ii) the mobile device is bound to the computing device. |
| US09646341B2 |
Interactive multimedia showroom display for plumbing fixtures and products
An exemplary display system is disclosed, which includes a display wall having a plurality of slots; a plurality of removable shelves, each removable shelf insertable into a slot of the plurality of slots; a plurality of unique identifiers, each unique identifier coupled to a corresponding removable shelf; a fixed shelf having an embedded or attached sensor; and a user-interactive visual display. Various systems display plumbing fixtures. In exemplary embodiments, the unique identifiers are implemented using RFID tags. |
| US09646340B2 |
Avatar-based virtual dressing room
A method to help a user visualize how a wearable article will look on the user's body. Enacted on a computing system, the method includes receiving an image of the user's body from an image-capture component. Based on the image, a posable, three-dimensional, virtual avatar is constructed to substantially resemble the user. In this example method, data is obtained that identifies the wearable article as being selected for the user. This data includes a plurality of metrics that at least partly define the wearable article. Then, a virtualized form of the wearable article is attached to the avatar, which is provided to a display component for the user to review. |
| US09646338B1 |
Managing textual descriptions based on quality rating
A system and method for managing reconciled textual descriptions based on merchant quality rating are provided. Merchants providing items to an electronic marketplace submit merchant values corresponding to textual descriptions of attributes of the item. A merchant value analyzer component processes multiple merchant descriptions to select a set of textual descriptions based on a comparison of the textual descriptions and merchant quality ratings. Additionally, a merchant quality analyzer component calculates updated merchant quality ratings based on the submitted merchant values. |
| US09646336B2 |
Information processing system and information processing method
An information processing system constituted with one or more computers includes a first result storage part to store result values of operation amounts of a first device; a prediction part to generate prediction values of operation amounts of the first device during a period; a calculation part to calculate indicator values based on the prediction values; an extraction part to select a second device that substitutes the first device using the indicator values; a replacement information storage part to store correspondence information between a device before replacement and a device after replacement; an obtainment part to obtain operation amounts of the devices before and after replacement, respectively, assuming that the first device is replaced by the second device; and an output part to output information about the obtained operation amounts. |
| US09646332B2 |
Secure large volume feature license provisioning system
Disclosed is a manufacturing process and feature licensing system for provisioning personalized (device-unique) licenses to devices. The secure system uses a secure key wrapping mechanism to deliver the LSK to LPS. Another feature is that various network communication links are secured using standard security protocol. Application messages, license templates, licenses are digitally signed. The system is flexible, configured to allow multiple manufacturers and to allow various feature configurations via the use of License Template; scalable, as it is possible to use multiple LPS hosts to serve multiple programming stations; and available in that the delegation of license signing capability from CLS to LPS eliminates the dependency on unreliable Internet connections. Redundant LPS hosts provide high level of availability required for high volume license provisioning. The system is traceable: license and device association are replicated back to the CLS to provide full license request and generation traceability. |
| US09646328B1 |
Interactive point of purchase display for toys
Techniques are provided for an interactive point of purchase product display. The interactive point of purchase product display includes a product placement region, one or more products located in the product placement region, an input device configured to receive an input signal, a controller device, and a selection indicator device. The input device may receive data about a potential consumer or customer. The controller device is coupled to the input device and the one or more products and is configured to receive data from the input device responsive to the input signal, select a product in response to the receive input and generate a selection signal identifying the product resulting in the attention of a customer to be drawn to the product. |
| US09646318B2 |
Updating point of interest data using georeferenced transaction data
Georeferenced transaction data is harvested (“crowd-sourced”) from client devices and sent to a network-based map service. The map service performs cluster analysis on location data points in the harvested data, resulting in one or more clusters representing local densities of transaction occurrences. Data vectors including supplemental data are obtained from one or more vendors. Location data points included in the data vectors are compared to center coordinates of the one or more clusters and the closest matching cluster/vector pair provides a mapping to POI data in a POI database. The mapped POI data is updated with the supplemental data. In some implementations, transaction timestamps in the harvested data are used to estimate the business hours of a business POI. |
| US09646314B2 |
Systems and methods for providing a promotion for a combined product dispensed from a product dispenser
Embodiments of the invention can include systems and methods for providing a promotion for a combined product dispensed from a product dispenser. In one embodiment, a system can provide a promotion for a combined product dispensed from a product dispenser. The system can include a code generation module operable to receive data associated with a plurality of product recipes; and generate a machine readable item with a promotion identifier, and a combined recipe including the plurality of product recipes, wherein the machine readable item configures a product dispenser to promote and dispense the combined recipe. |
| US09646312B2 |
Anonymous player tracking
An enhanced method of Casino and hotel probable customer and customer demographic identification, game selection, advertising and customer service based on the identification. |
| US09646311B2 |
Electronic course evaluation
A method, apparatus, questionnaire, and system for evaluating student(s), teacher(s), and a course(s). A participant enters data into a device. A participant is a student or a teacher. The data reflect a response by the participant to at least one item that is presented to the participant. The at least one item relates to at least one session of the course. The at least one session is taught to the participant by a teacher. The data may include teacher data relating to the teacher(s), student data relating to the student(s), course data relating to the course(s), or combinations thereof. |
| US09646310B2 |
Printable, writeable article for tracking counterfeit and diverted products
A method includes printing a readable and writeable memory on an object, using a seed to generate an original value, writing the original value to the memory, and sending the object to a recipient. The method may also include receiving the object at the recipient, determining the seed from a characteristic of the object, generating an authentication value using the seed value, and comparing the authentication value and the original value. |
| US09646308B1 |
Tool for selling and purchasing vehicle history reports
Systems and methods for selling and purchasing vehicle history reports are described. In one embodiment, a method includes determining a set of vehicles in a dealer inventory, determining a subset of the vehicles in the dealer inventory for which the dealer has not purchased a vehicle history report, presenting a summary report to a dealer, the summary report including information about at least one of the vehicles in the subset of the vehicles, receiving a selection to purchase a vehicle history report for at least one of the vehicles in the summary report, and providing the vehicle history report corresponding to the selection to the dealer. |
| US09646303B2 |
Secure remote payment transaction processing using a secure element
Embodiments of the present invention are directed to methods, apparatuses, computer readable media and systems for securely processing remote transactions. One embodiment of the invention is directed to a method of processing a remote transaction initiated by a mobile device. The method comprises receiving, by a mobile payment application on a secure memory of the mobile device, transaction data from a transaction processor application on the mobile device. The method further comprises validating that the transaction processor application is authentic and in response to validating the transaction processor application, providing encrypted payment credentials to the transaction processor application. The transaction processor application further initiates a payment transaction with a transaction processor server computer using the encrypted payment credentials. |
| US09646302B2 |
Systems, methods, and computer program products for managing wallet activation
Systems, methods, and computer program products are provided for managing activation in a mobile wallet. A wallet activation request is received from a wallet client. The wallet activation request is transmitted to a central trusted service manager (TSM). One or more push messages including activation data are received from the TSM, and the push messages are transmitted to the wallet client, in response to a second request from the wallet client while the wallet client is in an active state. |
| US09646301B2 |
System and method for secure card with on-board verification
Systems and methods for secure cards with on-board verification are disclosed. In one embodiment, a transaction device associated with at least one transaction account may have a substrate comprising a display that displays an account identifier for the transaction account; a sensor that receives authentication information from a user; a processor that processes the authentication information to verify the authenticity of the user; and a communicator that communicates at least the account information, the communicator including at least one of a magnetic stripe, an electrical interface, and a wireless RF interface. The display may not display the account identifier until the user is authenticated, and the communicator may be inactive to communicate the account information until the user is authenticated. |
| US09646296B2 |
Mobile-to-mobile transactions
A mobile-to-mobile transaction method allows two mobile smartphones to engage in a private transaction between themselves. The two share the same transaction server using prearranged individual enrollments. These build a dynamic digital image of a colorgram with a selected shape that defines a colorgram matrix boundary. Authentication codes, merchant coupons, product advertisements, and browser uniform resource locator (URL) links for product information and ordering, one-time-password (OTP) seeds, initialization vectors, individual enrollment passwords, or password seeds are embedded and encrypted in each colorgram. The colorgram is sent to a first one of the mobile smartphones for its display to a collocated second one of the mobile smartphones. A transaction is authenticated between users based on a calculated expectation of what should be returned when it provides its own digital image of the colorgram displayed by the first mobile smartphone. |
| US09646293B2 |
In session charging notifications and recharging accounts
Various embodiments provide a subscription management service, which can be in-band or out-of-band, which allows users to extend their subscription or temporarily side-step payment limits on a subscription without disrupting the user's experience. The various embodiments can be operable in all on-demand services including, but not limited to, video services, voice services, video/voice services, text services, Web services, and the like. |
| US09646289B2 |
Powertag: manufacturing and support system method and apparatus for multi-computer solutions
A solutions-based computer system manufacturing process includes assembling computer and storage system components for creation of a given solution-based product as a function of a customer order or plan. The process further includes assigning a solution identifier to the solution-based product. The solution identifier includes a solution type and a unique identifier within the solution type. |
| US09646285B2 |
Method for manufacturing a group of packaging media
A method for manufacturing a group of packaging media includes generating a sequence of unique codes, marking a series of packaging media with said unique codes, wherein said sequence is maintained in said series, and creating two or more sub-series of packaging media from said series by registering a first unique code marked on a first packaging media, entering an ordered number, creating said sub-series based on said ordered number, registering a last unique code, calculating an expected number based on a difference between said first and last unique code, and accepting said sub-series if a difference between said expected number and said ordered number is within a pre-defined tolerance. |
| US09646284B1 |
Global inventory warehouse
Building and maintaining an accurate and up-to-date global inventory of hardware, software, and telecommunications assets deployed throughout an organization is described. A global inventory warehouse (GIW) receives an identification and physical location of these assets from multiple source systems. Some of these source systems contain information pertaining to the assets that has been manually entered into the source system by a human administrator. Other source systems, meanwhile, contain information that has been automatically collected by the source systems without human intervention. The GIW receives this information from the source systems and stores it within a GIW database. The GIW database may thus contain a global inventory of all or nearly all of the hardware, software, and telecommunications assets distributed throughout the organization. This database may also contain an identification of physical locations within the organization of all or substantially all of these assets. |
| US09646276B2 |
Dashboard for dynamic display of distributed transaction data
An interface is provided for a user to create a custom dashboard for providing application performance data. The dashboard may be created from one or more widgets, such as graphs, charts, and other display components, and each widget may be individually configured with parameters. The dashboard may be configured to display data for one or more particular transactions, transaction types, or transactions that meet specified criteria. Once created, the dashboard may be shared through a website URL, e-mail, or other method. |
| US09646274B2 |
System and method for accessing business process instances through mobile devices
A BPM system is described for modeling, management and execution of business processes. A process designer component is used to graphically design a business process, which includes a set of activities linked by transitions. The business process is stored and executed using one or more engines. A mobile device can be used to access the business process instance executing on the engine. The mobile work portal can be generated to render information for the process instance onto the mobile device. A process application programming interface can be used to access and manipulate the process instance from the mobile device. |
| US09646270B2 |
Systems and methods for identifying, categorizing, aggregating, and visualizing multi-dimensional data in an interactive environment
The disclosed principles provide on-demand systems and related methods for identifying, categorizing, calculating, formatting, aggregating, linking, and visualizing multi-dimensional data in an interactive simulation environment. Simulation results are customized for each end-user based on selection criteria provided by the end-user via interactive network-based dashboards. The disclosed principles may be deployed either as an on-demand or SaaS deployment, public or private, or on the user's own servers. Business data for any number of businesses, executives, employees and individuals may be provided by any data source including customers/subscribers. The disclosed system/service does not rely on data provided from end-users, such as personal contact databases, electronic rolodexes, career job sites, or business or social media networking websites. Instead, the disclosed principles provide an aggregation of data in any of a number of categories to end users for their use in identifying relationships between, for example, employers, customers, competitors, prospects, partners, vendors, business consultants, investors, mergers, executives, employees, clients, and individuals. |
| US09646269B1 |
System, method, and computer program for centralized guided testing
A system, method, and computer program product are provided for centralized guided testing. In use, at least one software testing project is identified. Additionally, data associated with the at least one software testing project is accessed from at least one of a plurality of knowledge repositories that are capable of being dynamically and constantly updated, the plurality of knowledge repositories including: at least one first repository including official testing methodology associated with a plurality of testing processes; at least one second repository including test project management information; at least one third repository including test knowledge information provided by users; and at least one fourth repository including historical testing project information and ongoing testing project information. Further, the data associated with the at least one software testing project is presented utilizing at least one user interface. |
| US09646267B1 |
Following an entity in a social network
Methods, systems, and computer programs are presented for managing the visibility of relationships within a social network. One method includes an operation for enabling a person to establish a first follow relationship from the person to an entity in the social network. However, the entity is disabled to establish a second follow relationship from the entity to the person until the first follow relationship from the person to the entity is established. Further, the establishment of the first follow relationship with a limited visibility is detected, and the establishment of the second follow relationship is also detected. The method further includes an operation for disabling a user in the social network to obtain visibility of the second follow relationship if the first follow relationship is invisible to the user. |
| US09646266B2 |
Feature type spectrum technique
Sensors are used to generate sample set data representing objects in a sample set. A computer system analyzes the sample set data to determine the frequencies with which features in a feature set are observed in the objects in the sample set. An example of such output is a bar chart representing the frequency of observation of features in the feature set in a particular object. The feature output may be used to identify one or more obscure (i.e., low frequency) features in the particular object. Machine learning may be used to learn associations between sample set data and features in the feature set. |
| US09646265B2 |
Model updating method, model updating device, and recording medium
A model updating method is provided. The model updating method that is executed by a computer includes calculating a score that indicates a degree of normality or abnormality of each of a plurality of pieces of data by using as a judgment model each of the pieces of data, predicting as a predicted condition whether each of the pieces of data is normal or abnormal according to score, judging whether or not the predicted condition is correct for each of the plurality of pieces of data, calculating the accuracy rate for the predicted conditions of a top specified number of pieces of data in order of decreasing abnormality as indicated by the score when the plurality of pieces of data are arranged in a specified order of score, and judging whether or not it is necessary to update the judgment model according to the accuracy rate. |
| US09646263B2 |
Identifying expanding hashtags in a message
A social networking system receives messages from users that include hashtags. The social networking system may use a natural language model to identify terms in the hashtag corresponding to words or phrases of the hashtag. The words or phrases may be used to modify a string of the hashtag. The social networking system may also generate computer models to determine likely membership of a message with various hashtags. Prior to generating the computer models, the social networking system may filter certain hashtags from eligibility for computer modeling, particularly hashtags that are not frequently used or that more typically appear as normal text in a message instead of as a hashtag. The social networking system may also calibrate the computer model outputs by comparing a test message output with outputs of a calibration group that includes positive and negative examples with respect to the computer model output. |
| US09646256B2 |
Automated end-to-end sales process of storage appliances of storage systems using predictive modeling
Techniques for generating end-to-end sales leads based on storage capacity forecast using predictive modeling are described herein. According to one embodiment, diagnostic data is received from a data collector that periodically collects the diagnostic data from a storage system having one or more storage units to store data objects. A capacity forecaster coupled to the data collector forecasts a full capacity date using predictive modeling based on the diagnostic data, where the full capacity date estimates a date in which the one or more storage units reach a full storage capacity. A context generator coupled to the capacity forecaster generates a context having information identifying the one or more storage units of the storage system and an operator operating the storage system, wherein the context is used to communicate with the operator for acquiring an additional storage unit to increase storage capacity prior to the full capacity date. |
| US09646255B2 |
Conversation branching for more efficient resolution
A method for conversation branching may include storing a plurality of messages communicated in an online conversation and generating a fingerprint for each message. The fingerprint for each message may be stored to a lookup table. The method may also include detecting a new message from one of the users and processing the new message to generate an artifact that correlates to the new message. The lookup table may be queried using the artifact to determine a similarity between the new message and each of the stored messages. One or more proposed reply messages to the new message may be generated for branching the online conversation to a new conversation point that corresponds to a selected one of the one or more proposed reply messages. The one or more proposed reply messages are based on one of the stored messages that has a closest similarity to the new message. |
| US09646252B2 |
Template clauses based SAT techniques
A CNF formula comprises at least one template clause representing a set of concrete clauses, each associated with a different temporal shift. The template clause is utilized by a SAT solver in determining satisfiability of the CNF formula. The template clause may be utilized to reduce amount of storage resources required for performing the satisfiability analysis. The template clause may in some cases increase feasibility of determining satisfiability. The template clause may in some cases reduce required time to determine satisfiability. The template clause may be utilized in incremental SAT solving to reuse deduced relations between literals that are applicable to additional cycles, such as invariants originating from a transition relation of a model. |
| US09646251B2 |
Detection of communication topic change
A computer processor determines a first span of a communication, wherein a span includes content associated with one or more dialog statements. If the content of the first span contains one or more topic change indicators which are identified by at least one detector of a learning model, the computer processor, in response, generates scores for each of the one or more indicators. The computer processor aggregates scores of the one or more indicators of the first span, which may be weighted, to produce an aggregate score. The computer processor compares the aggregate score to a threshold value, wherein the threshold value is determined during training of the learning model, and the computer processor, in response to the aggregate score crossing the threshold value, determines a topic change has occurred within the first span. |
| US09646250B1 |
Computer-implemented cognitive system for assessing subjective question-answers
A cognitive system that automatically assesses subjective answers may be provided. A cognitive engine executing on one or more processors may determine whether a statement parsed from a subjective answer by natural language processing technique is accurate or inaccurate, for each of the plurality of statements based on matching the statement with information associated with a domain of a question from a plurality of data sources, according to an accuracy threshold. An overall assessment of the answer may be automatically determined based on a number of statements determined to be accurate, a number of statements determined to be inaccurate, a number of duplicate statements in the answer relative to a total number of statements in the answer. A visual graphics representing accurate and inaccurate statements may be presented or displayed, allowing a user to interact with the visual graphics to modify the assessment. |
| US09646248B1 |
Mapping across domains to extract conceptual knowledge representation from neural systems
Described is system for extracting conceptual knowledge representation from neural system. The system extracts a first set of attributes to define a set of objects in a first domain. A first formal concept lattice is constructed comprising the set of objects and the first set of attributes from the first domain. A second set of attributes is extracted to define the set of objects in a second domain. A second formal concept lattice is constructed comprising the set of objects and the second set of attributes from the second domain. The first formal concept lattice is aligned with the second formal concept lattice to link the first set of attributes with the second set of attributes, wherein a combined lattice is generated. The combined lattice is used to relate the first domain to the second domain. |
| US09646247B2 |
Utilizing temporal indicators to weight semantic values
A mechanism is provided, in a data processing system comprising a processor and a memory configured to implement a question and answer system (QA), for utilizing temporal indicators to weight semantic values. A set of temporal characteristics is identified of a set of initial candidate answers. For each initial candidate answer in the set of initial candidate answers: a distance value is generated for each of the set of temporal characteristics of the set of initial candidate answers, a multiplier value is determined with which to weight an initial confidence score associated with the initial candidate answer using the distance value; a sentiment value is determined of the initial candidate answer, and a final weight value is determined using the multiplier value, the sentiment value, and the initial confidence score associated with the initial candidate answer. A set of temporally refined candidate answers is then provided using the determined final weight values. |
| US09646243B1 |
Convolutional neural networks using resistive processing unit array
Technical solutions are described for implementing a convolutional neural network (CNN) using resistive processing unit (RPU) array. An example method includes configuring an RPU array corresponding to a convolution layer in the CNN based on convolution kernels of the layer. The method further includes performing forward pass computations via the RPU array by transmitting voltage pulses corresponding to input data to the RPU array, and storing values corresponding to output currents from the RPU arrays as output maps. The method further includes performing backward pass computations via the RPU array by transmitting voltage pulses corresponding to error of the output maps, and storing the output currents from the RPU arrays as backward error maps. The method further includes performing update pass computations via the RPU array by transmitting voltage pulses corresponding to the input data of the convolution layer and the error of the output maps to the RPU array. |
| US09646237B2 |
Barcoded indicators for quality management
A barcoded indicator operative to provide a machine-readable indication of exceedance of at least one threshold by at least one product quality affecting parameter, the barcoded indicator including at least a first barcode and at least a second barcode, the at least a second barcode being in a second barcode unreadable state prior to exceedance of the at least one threshold and upon exceedance of the at least one threshold the at least a first barcode becoming unreadable and generally simultaneously the at least a second barcode becoming readable. |
| US09646236B1 |
Encoding and decoding data in two-dimensional symbology
Examples of techniques for encoding data in a 2D symbology are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented comprises assigning a first color representative of a 0-bit and a second color representative of a 1-bit. The method further comprises designating a starting cell pair and an ending cell pair. The method also comprises generating, by a processing device, the 2D symbology. The 2D symbology comprises a series of cells in a cell space starting with the starting cell pair and ending with the ending cell pair. Each cell between the starting cell pair and the ending cell pair corresponds to a bit of a binary string and has a common cell length. The cells corresponding to a 0-bit are colored the first color and the cells corresponding to a 1-bit are colored the second color. |
| US09646235B2 |
Method and apparatus for producing a 2D barcode encoded part by molding being identifiable using a smartphone
A method for producing a part by molding with an embedded 2D barcode defined in the surface of the part and the embedded 2D barcode subsequently being readable using a light source and a camera, the method including providing a mold with an array of individual areas of optical anisotropic surface structures, where at least a number of the individual optical anisotropic structures forms a two-dimensional barcode or data matrix; making a replica of the mold, the replica including the array having the property that the directional reflection coefficient of the individual areas of optical anisotropic surface structures is depending on the illumination angle and detection angle in a way that is not rotational symmetric around the axis normal to the surface of the replica, the array being readable by illumination and detection of reflection intensity of the illumination source under a non-normal angle to the surface of the replica. |
| US09646232B2 |
Rendering apparatus, rendering method, and computer readable medium storing rendering program
An object of the present invention is to provide an image processing apparatus capable of combining a group element so that a color intended by a user is output ultimately even in the case where flattening is performed on the way of the processing performed on the group. |
| US09646229B2 |
Method and system for bone segmentation and landmark detection for joint replacement surgery
A method and system for automatic bone segmentation and landmark detection for joint replacement surgery is disclosed. A 3D medical image of at least a target joint region of a patient is received. A plurality bone structures are automatically segmented in the target joint region of the 3D medical image and a plurality of landmarks associated with a joint replacement surgery are automatically detected in the target joint region of the 3D medical image. The boundaries of segmented bone structures can then be interactively refined based on user inputs. |
| US09646228B2 |
Role-based tracking and surveillance
A method for surveilling a monitored environment includes classifying an individual detected in the monitored environment according to a role fulfilled by the individual within the monitored environment, generating a trajectory that illustrates movements and locations of the individual within the monitored environment, and detecting when the trajectory indicates an event that is inconsistent with an expected pattern for the role. |
| US09646224B2 |
Image processing method, image processing device and automated optical inspection machine
The present disclosure relates to an image processing method, an image processing device, and an automated optical inspection machine. The method includes: an inspection area determining step for determining a rectangular inspection area in an inspected image; a definition threshold determining step for calculating an image definition threshold according to the gray values of pixels of a plurality of sample images in the inspection area; a product image definition determining step for calculating a product image definition according to the gray values of pixels of a product image in the inspection area; and a comparison step for comparing the product image definition with the image definition threshold; and a product image selecting step for selecting the current product image as an image to be inspected. |
| US09646212B2 |
Methods, devices and systems for detecting objects in a video
Methods, devices and systems for performing video content analysis to detect humans or other objects of interest a video image is disclosed. The detection of humans may be used to count a number of humans, to determine a location of each human and/or perform crowd analyses of monitored areas. |
| US09646211B2 |
System and method for crowd counting and tracking
A video analytic system includes a depth stream sensor, spatial analysis module, temporal analysis module, and analytics module. The spatial analysis module iteratively identifies objects of interest based on local maximum or minimum depth stream values within each frame, removes identified objects of interest, and repeats until all objects of interest have been identified. The temporal analysis module associates each object of interest in the current frame with an object of interest identified in a previous frame, wherein the temporal analysis module utilizes the association between current frame objects of interest and previous frame objects of interest to generate temporal features related to each object of interest. The analytics module detects events based on the received temporal features. |
| US09646209B2 |
Sensor and media event detection and tagging system
Enables detection and tagging of events using sensor data combined with data from servers such as social media sites. Sensors may measure values such as motion, temperature, humidity, wind, pressure, elevation, light, sound, or heart rate. Sensor data and event tags may be utilized to curate text, images, video, sound and post the results to social networks, for example in a dedicated feed. Event tags generated by the system may represent for example activity types, players, performance levels, or scoring results. The system may analyze social media postings to confirm or augment event tags. Users may filter and analyze saved events based on the assigned tags. The system may create highlight and fail reels filtered by metrics and by tags. |
| US09646208B2 |
Method for computerized grouping contact list, electronic device using the same and computer program product
A method for computerized grouping contacts, an electronic device using the same and a computer program product are provided. The method for computerized grouping the contacts includes the following steps. At least one image is provided. Contacts are determined in the image. An interpersonal relation information is updated according to the image and the determined contacts. A contact group is suggested according to the interpersonal relation information. |
| US09646206B2 |
Object identification and inventory management
A method/apparatus for identifying an object based on a pattern of structural features located in a region of interest wherein the pattern of features comprises at least one fingerprint feature. The region may be recognized and used to identify the object. A first feature vector may be extracted from a first image of the pattern and may be mapped to an object identifier. To authenticate the object, a second feature vector may be extracted from a second image taken of the same region later in time than the first image. The two feature vectors may be compared and differences between one or more feature vector values determined. A match correlation value may be calculated based on the difference(s). The differences may be dampened if associated with expected wear and tear. Thus the impact on the match correlation value of such differences may be reduced. The differences may be enhanced if associated with changes that are not explainable as wear and tear. Thus the impact on the match correlation value of such differences may be increased. |
| US09646204B2 |
Electronic device and method for outline correction
An electronic device and an image processing method in the electronic device are provided. The electronic device includes a display unit configured to display an image; and a controller configured to correct an outline according to a drawing input with a correction scheme on the image and to crop the image within the corrected outline according to the corrected outline. |
| US09646203B2 |
Method and apparatus for generating map data based on construction designs
A method, apparatus and computer program product are provided for generating map data based on construction designs. In the context of a method, the method includes receiving a construction design, performing optical character recognition to detect characters within the construction design, extracting design features within the construction design, and generating map data based on the detected characters, and the extracted design features. |
| US09646202B2 |
Image processing system for cluttered scenes and method of operation thereof
An image processing system and method of operation includes: a source image having source pixels; homogeneous blocks in the source image having a block color; a homogeneous region in the source image formed by merging the homogeneous blocks having the block color within a color threshold; a text background region having text pixels and background pixels in the homogeneous region with the text background region having a texture feature above a texture threshold and a region size above a region size threshold; and a binary text mask representing the text pixels and the background pixels for displaying on a device. |
| US09646197B2 |
Biometric identification and verification
In real biometric systems, false match rates and false non-match rates of 0% do not exist. There is always some probability that a purported match is false, and that a genuine match is not identified. The performance of biometric systems is often expressed in part in terms of their false match rate and false non-match rate, with the equal error rate being when the two are equal. There is a tradeoff between the FMR and FNMR in biometric systems which can be adjusted by changing a matching threshold. This matching threshold can be automatically, dynamically and/or user adjusted so that a biometric system of interest can achieve a desired FMR and FNMR. |
| US09646192B2 |
Fingerprint localization
A method, device and system for generating an enrollment template are provided. The enrollment template is generated by collecting a placement image representing a portion of a biometric object such as a fingerprint. The placement image is localized on the fingerprint by comparing the data in the placement image to data in a floor map representing a larger image of the fingerprint obtained by swiping or rolling the fingerprint over a sensing area of a partial placement sensor. As additional placement images are obtained more information is provided for the enrollment template. The additional placement images are also localized to one another utilizing the floor map. The enrollment template is generated based on a grouping of each placement image to its neighboring placement images. |
| US09646190B2 |
Two-dimensional code reading device
A two-dimensional code reading device which can prolong the lifetime of the auxiliary light is provided. A two-dimensional code reading device in the present invention includes an image reading unit to acquire an image of a two-dimensional code printed on a ticket medium, a specific pattern detector to detect a specific pattern to identify the two-dimensional code from the image of the two-dimensional code acquired by the image reading unit, a two-dimensional code decoder to read information recorded in the two-dimensional code detected by the specific pattern detector, an auxiliary light to irradiate light on the ticket medium and an auxiliary light controller to control turning on and off of the auxiliary light, wherein the auxiliary light controller turns on the auxiliary light when the specific pattern is detected by the specific pattern detector and the information recorded in the two-dimensional code cannot be read by the two-dimensional code decoder. |
| US09646188B1 |
Imaging module and reader for, and method of, expeditiously setting imaging parameters of an imager based on the imaging parameters previously set for a default imager
An imaging reader has near and far imagers for imaging targets to be read over a range of working distances. A default imager captures a minor portion of an image of the target, and rapidly determines its light intensity level. The exposure and/or gain values of the default imager are set to predetermined values based on the determined light intensity level. If the target is not decoded by the default imager, then the exposure and/or gain values of another imager are set to predetermined values based on the exposure and/or gain values that were previously set for the default imager. |
| US09646181B2 |
Card reader
A card reader may include a recording and reproducing means to perform reading of data or writing of data, a first cable configured to transmit a data signal outputted from the recording and reproducing means or a data signal inputted into the recording and reproducing means, a circuit board in a flat plate shape for controlling the card reader, a connector mounted on the circuit board and connected with one end side of the first cable, and a second cable connected with the circuit board and configured to transmit a control signal for controlling the card reader. A width of the second cable is wider than a width of the first cable, and the second cable is connected with the circuit board so as to cover a connected portion of the first cable with the connector. |
| US09646178B2 |
Secure data storage based on physically unclonable functions
Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data. |
| US09646173B2 |
Comment plug-in for third party system
In particular embodiments, one or more computing devices associated with a third-party system generate a web page comprising one or more references configured to cause a client device to send a request to a web site of a social-networking system to access a user comment, wherein the user comment is associated with content on a third-party web site hosted by the third-party system. The request comprises a first URL that references the web site of the social-networking system, and the first URL comprises a second URL that references the third-party web site and comprises a content identifier for the content, and the request is to cause the web site of the social-networking system to access the user comment in a data store of the social-networking system. The one or more computing devices associated with the third-party system may send the web page to the client device. |