| Document | Document Title |
|---|---|
| US09648233B2 |
System, device, and vehicle for recording panoramic images
The present invention relates to a system, a device, and vehicle for recording panoramic images. According to the present invention, panoramic images can be obtained using a plurality of optical cameras and light directing elements which are arranged based on a parabola. This allows a compact device to be obtained while ensuring that each camera records a partial image as if it were at substantially the same focus point as the other cameras. By arranging the plurality of cameras and light directing elements such that the respective focus points are slightly offset relative to each other, a slight overlap between adjacent field of views can be obtained to improve stitching of the partial images to from the panoramic image. |
| US09648232B2 |
Image processing apparatus, image capturing apparatus, control method and recording medium
An image processing apparatus generates a plurality of frequency range images by separating an image based on an obtained image signal into predetermined frequency ranges. The apparatus applies predetermined image processing to the plurality of frequency range images, and generates an image for saving based on the plurality of images. The apparatus generates an image for display based on some of the plurality of frequency range images to which the predetermined image processing has been applied. |
| US09648226B2 |
Image capture apparatus and control method thereof
An image capture apparatus and control method thereof that improve focus detection accuracy in scenes that have low luminance, contrast, and the like is disclosed. The image capture apparatus has a focus detection mode suited to scenes that have low luminance, contrast, and the like. In this focus detection mode, the focus detection is carried out on the basis of a frequency component extracted from an image signal to which a coefficient for correcting intensity differences between color components is not applied, or to which a coefficient having a lower difference among color components than the computed coefficient has been applied. |
| US09648225B1 |
Method, apparatus, system and software for focusing a camera
Methods, apparatuses, systems and software for focusing a camera are disclosed. The camera focusing system includes a distance measuring device, a video receiver that receives video/images, a graphics overlay unit, and a monitor. The distance measuring device includes an emitter that emits a radiation beam, a detector that detects reflected radiation, and logic that determines and processes distance information for subject(s) or object(s) in detection zones from the reflections. The graphics overlay unit receives video/image information from the video receiver and the distance information from the distance measuring device, and includes a video overlay and data processing unit that generates graphics indicating a field of detection and position for each detection zone and a direction and/or magnitude of a change in focus setting(s) to bring subjects or objects within each detection zone into focus. The monitor displays the video/image and the graphics overlaid thereon. |
| US09648224B2 |
Apparatus and method of processing image
Image processing apparatus and method of calculating distance information and size information of an object within an image frame are provided. The method of processing an image includes: sequentially moving a focus lens from infinity to a short distance; overlapping and storing frames including an object focused at each movement location of the focus lens; and displaying a synthesis frame that synthesizes the overlapped frames in one frame, and simultaneously, calculating relative distance information of objects focused at different locations of the focus lens based on an object focused at an arbitrary location of the focus lens, and displaying the relative distance information in the synthesis frame. |
| US09648222B2 |
Image capturing apparatus that controls supply of amperage when reading out pixel signals and method for controlling the same
An image capturing apparatus including a plurality of photoelectric conversion portions for each of a plurality of microlenses, the image capturing apparatus comprising: a readout unit configured to be driven using a first driving method in which a signal is read out from part of the plurality of photoelectric conversion portions, and a second driving method in which a signal is read out from a greater number of the photoelectric conversion portions than in the first driving method; and a supply unit configured to, in a case where a signal is read out using the first driving method, supply an amperage that is smaller than that in a case where a signal is read out using the second driving method, to the readout unit. |
| US09648220B2 |
Imaging apparatus, imaging apparatus body and image sound output method
A digital camera includes an optical system including a focus lens, a zoom lens and a diaphragm, an HDMI output terminal configured to output sound collected by a microphone unit and a picture imaged by a CCD image sensor to an external recorder, and a controller. The controller controls switching between a moving image priority mode and a still image priority mode in which the optical system is driven at a higher speed than a speed in a moving image priority mode. In addition, the controller allows change to a moving image imaging mode by an operation unit when detecting that output to the external recorder is possible in the HDMI output terminal. |
| US09648219B2 |
Web camera and operation method thereof
A web camera and an operation method thereof are provided. The web camera includes a photographic unit, an infrared (IR) transmitter, a network communication unit and a processing unit. The photographic unit captures an image. The network communication unit establishes a connection with a remote host via a communication network. The processing unit sends the image captured by the photographic unit to the remote host via the network communication unit. The processing unit receives a control command from the remote host via the network communication unit. The processing unit transmits an IR control code corresponding to the control command to a target device via the IR transmitter. The processing unit determines whether the target device responds to the IR control code based on the image. |
| US09648214B2 |
Module for plenoptic camera system
An apparatus including a substrate; a plurality of first image sensels supported by the substrate and arranged in rows and columns, wherein the substrate includes one or more apertures. |
| US09648200B2 |
Image processing system storing received image data in folder, image processing method, and storage medium
An image processing system includes a memory unit configured to store an address book to be used for setting a transmission destination of image data, a receiving unit configured to receive the image data, an acquisition unit configured to acquire a name that is registered in the address book in association with information of a transmission source of the image data received by the receiving unit, a setting unit configured to set a folder path for a plurality of hierarchies which includes a folder with the name acquired by the acquisition unit, and a storage unit configured to store the image data received by the receiving unit in a folder indicated by the folder path that is set by the setting unit. |
| US09648198B2 |
Image processing apparatus, image processing method, and non-transitory computer-readable storage medium that embed additional information in an image having a plurality of pixels and image information
An image processing apparatus for embedding additional information in an image having a plurality of pixels and image information. A generating unit generates (a) the additional information to be embedded and (b) a bookbinding type of a medium containing the image. A holding unit holds a plurality of quantization conditions for embedding the additional information, including a quantization threshold. A selection unit segments the image into a plurality of embedding regions, and selects a condition to use in quantization based on the image information. A quantization condition control unit controls at least one of the plurality of quantization conditions for a predetermined region of the image based on the bookbinding type generated. An error diffusion processing unit distributes an error to peripheral pixels of a target pixel. A separating unit separates the embedded additional information from the image. |
| US09648197B2 |
Salient point-based arrangements
A variety of methods and systems involving sensor-equipped portable devices, such as smartphones and tablet computers, are described. One particular embodiment decodes a digital watermark from imagery captured by the device and, by reference to watermark payload data, obtains salient point data corresponding to an object depicted in the imagery. Other embodiments obtain salient point data for an object through use of other technologies (e.g., NFC chips). The salient point data enables the device to interact with the object in a spatially-dependent manner. Many other features and arrangements are also detailed. |
| US09648193B2 |
Image reading apparatus for bound media
An image reading apparatus for bound media includes a placement table, on which a bound medium is placed, a first arm that is opposite to a bound portion of the bound medium, a second arm, a lifting unit that lifts up a turned medium of the bound medium, a second arm moving mechanism that moves the second arm, so that the turned medium lifted by the lifting unit is sandwiched between the first arm and the second arm, an arm moving mechanism that moves the first arm and the second arm, so that the turned medium turns over, a first imaging unit that performs imaging of a side of the turned medium opposite to the first arm, and a second imaging unit that performs imaging of the a side of the turned medium opposite to the second arm. |
| US09648183B2 |
Electric device
An electric device, including a chassis and an operation panel, is provided. The operation panel is disposed on a face of the chassis and has one end and the other end opposite from the one end. The operation panel includes a first capacitive touch switch configured to be responsive to a touch and a second capacitive touch switch configured to be responsive to a touch. The first capacitive touch switch has a first sensitivity for responding to the touch, and the second capacitive touch switch has a second sensitivity for responding to the touch. The second capacitive touch switch is arranged in a position closer to the one end of the operation panel than the first capacitive touch switch, and the second sensitivity of the second capacitive touch switch is lower than the first sensitivity of the first capacitive touch switch. |
| US09648176B2 |
Multifunctional document processing device retrieving information on behalf of mobile device
A method for operating a mobile device. The method includes receiving a software application for the multifunctional document processing device by the mobile device, establishing a local connection with the mobile device to a multifunctional document processing device, and generating with the software application a service request by the mobile device, wherein the service request includes service request data. The method further includes transmitting the service request with the software application to the multifunctional document processing device and receiving, by the software application of the mobile device, return data in response to the service request from the multifunctional document processing device. The mobile device does not provide a location of the mobile device to a service provider of the mobile device. |
| US09648170B2 |
System and method for providing call-back options
A system and method for providing call-back options is disclosed. The method comprises receiving a call in a call routing system, providing at least one call-back option for a caller to receive a call-back, re-allocating resources in the call routing system based at least in part on the at least one call-back: option, and calling the caller based on the at least one call-back option. The caller may specify a specific time, a relative time, or a time range when a call-back is preferred. The caller may also specify one or more telephone numbers in combination with the time preferences. The call-back may be initiated by a voice response unit (VRU) and additional call-back options may be presented to the customer who responds to the call-back. |
| US09648168B2 |
Method and apparatus for optimizing response time to events in queue
A system for optimizing response time to events or representations thereof waiting in a queue has a first server having access to the queue; a software application running on the first server; and a second server accessible from the first server, the second server containing rules governing the optimization. In a preferred embodiment, the software application at least periodically accesses the queue and parses certain ones of events or tokens in the queue and compares the parsed results against rules accessed from the second server in order to determine a measure of disposal time for each parsed event wherein if the determined measure is sufficiently low for one or more of the parsed events, those one or more events are modified to a reflect a higher priority state than originally assigned enabling faster treatment of those events resulting in relief from those events to the queue system load. |
| US09648167B2 |
Back office services of an intelligent automated agent for a contact center
A back office services of an intelligent automated agent for a contact center is provided. The back office services is configured to run on a processor coupled to a non-transitory storage device. The back office services includes: a customer profile module configured to access a profile of a customer from a customer profile database stored on the storage device, the profile of the customer including interaction data from interactions involving the customer and the contact center, and analysis results from analyzing the interaction data between the interactions involving the customer and the contact center; and a content analysis module configured to generate new analysis results by performing the analyzing of the interaction data between consecutive interactions of the interactions involving the customer and the contact center, and update the analysis results of the profile of the customer on the storage device to reflect the new analysis results. |
| US09648163B2 |
Generation of phone number lists and call filtering
An analyzer resource receives call information about outbound phone calls from multiple phone numbers to target phone numbers in a phone network. The analyzer resource analyzes the call information to detect likely unwanted call activity. Based on the analyzing, the analyzer resource produces a list of phone numbers from which one or more entities originate unwanted calls to the subscribers in the phone network. |
| US09648159B2 |
Single-PDP dual stack serial dialing method and system
A method and system for single-PDP dual-stack serial dialing is provided. A mobile terminal sets a single-PDP dual-stack serial dialing parameter according to a parameter setting command transmitted by a host; then the mobile terminal initiates a PDP activation request to a mobile communication network according to a first dialing instruction transmitted by the host and the configured single-PDP dual-stack serial dialing parameter, acquires activation response information fed back by the mobile communication network, generates dialing response information according to the activation response information, and feeds back the dialing response information to the host, wherein the dialing response information includes cause reference information. And after receiving the dialing response information, the host can acquire a specific condition of the current mobile network according to the cause reference information included in the dialing response information to determine a dialing mode. |
| US09648157B2 |
Mobile terminal and method of controlling information publication via a website in a mobile terminal
A mobile terminal and a method of a mobile terminal controlling information publication via a website are disclosed. According to one embodiment, a mobile terminal includes: a wireless communication unit for accessing a social networking service (SNS) website; a user input unit for receiving an input of information to be published at the accessed SNS website; a position location module for obtaining a current position of the mobile terminal; and a controller for: determining whether the obtained current position is located within a specific location area; preventing publication of the input information at the accessed SNS website if it is determined that the obtained current position is located within the specific location area; and allowing publication of the input information if it is determined that the obtained current position is not located within the specific location area. |
| US09648150B1 |
One piece conductive housing with incorporated antenna for use in an electronic device
The present application provides a housing for an electronic device having wireless communication capabilities including an antenna incorporated as part of the housing. The housing includes a one piece conductive housing having an outer edge. One or more windows are located entirely within the one piece conductive housing, where each of the one or more windows has a perimeter. At least a first window of the one or more windows is positioned within the one piece conductive housing proximate a portion of the outer edge of the one piece conductive housing. At least one drive signal is applied across the first window of the one or more windows, which is positioned proximate the outer edge of the one piece conductive housing, at a respective pair of points along the perimeter of the first window. |
| US09648149B2 |
Method and device for indicating PLCP header transmission mode
Disclosed are method and device for indicating a PLCP header transmission mode. A method for generating a physical layer convergence protocol (PLCP) of a data frame can comprise the following steps: demodulating PLCP header mode information based on a scrambling sequence of the received frame or information elements included in the received frame; and generating a data frame including the PLCP header generated based on the PCLP header mode information. The PLCP header mode information comprises at least one indication from a space time block coding mode indication, a guard interval mode indication, and a repetition mode indication. The invention is capable of improving data transmission efficiency by adaptively determining a transmission mode of a PCLP header to a channel situation. |
| US09648146B2 |
Information processing system
An information processing system includes a first server that performs processes in accordance with first operations included in a system of operations for the first server, a second server that performs processes in accordance with second operations included in a system of operations for the second server different from the system of operations for the first server, and a terminal apparatus that requires the first and second servers to perform the processes. The terminal apparatus includes a first requiring portion that requires the first server to perform a process in accordance with at least one of the first operations designated by a user and a converter that converts the at least one first operation into a command set and stores the command set in a storage, the command set including at least one command, which is a part of the process and is performed by the first and second servers. |
| US09648142B2 |
Systems and methods for identifying a returning web client
Methods and systems are provided for identifying unique devices and/or unique users of a web-based system within constraints of an external application. In some embodiments the process comprises receiving request information from a client device at an application server, using such information to form a device fingerprint, and attempting to match the newly-formed fingerprint with exactly one fingerprint stored in a database of previously-formed fingerprints. Some embodiments utilize a two-stage Locality-Sensitive Hash query technique. The client device fingerprint may be converted into a series of LSH values which may be used to find a matching fingerprint. A first stage may query input LSH values against LSH values in a data store, and a second stage may query LSH values temporarily held in volatile memory, thereby minimizing network traffic and reducing a total process time. |
| US09648138B1 |
Method and system for virtual server dormancy
A method for providing a dormant state for content management servers. Client devices are allowed to conduct transactions with servers when the servers are active. However, in a dormant state, the servers are not allowed to accept new transactions. Thus, by utilizing the dormant state, software upgrades can be made to one server at a time. Alternatively, all servers can be taken down for major upgrades, with the servers still operated in a read-only mode based on a file image from a point in time just prior to the shutdown. When the upgrade is completed, the servers can be returned to the active state. |
| US09648136B2 |
Smart packaging for mobile applications
A method of distributing content to an application from a server is disclosed. The method includes detecting in a file to be sent to the application from the server that the application is directed to request one or more resources to be downloaded to the application. A network latency associated with the downloading of the one or more resources is determined. A subset of the one or more resources is selectively packaged based at least in part on the network latency. The selectively packaged subset of the one or more resources is sent to the application. |
| US09648135B2 |
Method, device, client end and system for network resource management
The invention is applicable to network technologies and provides a method for network resource management, a server and a client end, which includes: receiving, an error report from a client end, wherein the error report includes a data source of a data fragment that does not pass the validation of the client; obtaining, a category of the data source; shielding, the data source when the data source belongs to a first category; and instructing, the data source to update network resources to which the data fragment belongs, when the data source belongs to a second category. The invention avoids the situation that the client end is unable to download a complete file due to an error of an original source of network resources, and improves the success rate of downloading. |
| US09648134B2 |
Object migration between cloud environments
Technologies are generally described for a system for migrating an application between cloud environments such as datacenters. In some examples, an application hosted at a source cloud may be moved from the source cloud to the destination cloud by migrating one or more objects at a time from the source to the destination cloud while maintaining the application up and running by intercepting and redirecting requests to a source or destination depending on where related objects reside. Example objects may be data structures, attributes and associated behaviors that encapsulate the application. Migration of the objects may be facilitated by enumerating and serializing the objects, and loading subsets of one or more serialized objects at the destination datacenter. An object migration module may keep track of objects in transit, and may direct requests for transferred objects to the destination cloud for maintaining continued access to the application. |
| US09648126B2 |
Efficient caching in content delivery networks based on popularity predictions
A method for caching objects at one or more cache servers of a content delivery network (CDN) includes: determining, by a processor, attributes of objects of a set of objects; calculating, by the processor, an efficiency metric for each object of the set of objects based on the attributes of each object, wherein the attributes of each object include an expected future popularity associated with the object; selecting, by the processor, a subset of objects from the set of objects for caching based on calculated efficiency metrics; and caching the subset of objects at the one or more cache servers. |
| US09648123B2 |
Distributing content elements among devices
Technologies are generally described for distributing displayed content elements among devices. In some examples, a system for moving and redistributing controls or other elements among web capable devices is presented using gateway managed redirection and injection of web page code. Injection capabilities of advertising gateways may be managed with a web application type interface for allowing a user to instruct the gateway to copy elements out of the web interface on one device and inject the elements into the interface on another device. Thus, transport of control or other elements may be enabled as suitable for various device capabilities. |
| US09648122B2 |
Mobile cache for dynamically composing user-specific information
A system and method for caching data in wireless application protocol (WAP) enabled services caches static data and facilitates dynamic creation of user-specific information to provide a customized output. The mobile cache generates the user-specific information in WML in real-time from cached information according to user-specified preferences. A change trigger triggers information delivery after a predetermined amount of cached information changes. The system may also include an image converter to ensure that image objects can be viewed easily on WAP-enabled devices having small display screens and a document converter to dynamically compose information from selected data based on XML-based content tagging. |
| US09648116B2 |
System and method for monitoring mobile device activity
A method and server for monitoring the physical activities of a mobile device is provided. The server receives descriptive data from a monitor, the descriptive data including a time, a monitor identifier and a device identifier. Additional descriptive data based on the monitor identifier is selected and a profile based on the descriptive data and the additional descriptive data is updated. The profile is further updated based on a time based activity. The additional descriptive data can include classifications and at least one keyword associated with each classification. Each keyword associated with each classification is selected based on a location of the monitor. The profile can be associated with at least one of the device identifier and the monitor identifier. The server can further maintain additional profiles and aggregate the maintained to form a macro profile. |
| US09648113B2 |
Location specific event broadcasting
Applications in a broadcast environment distribute events in real-time to a large number of receivers within specified geographic locations while efficiently sharing bandwidth resources with other applications using the same broadcast network. Applications need not be aware of the other applications sharing the resources, nor of the methods, protocols, and other mechanisms used to actually broadcast the data over the broadcast medium. Server-side applications that serve data, send notifications, or distribute events to specific locations within the network use a broadcast location manager. Client applications that receive such data, notifications, or events use a client location filter to obtain events that are relevant based on the location of the device. The broadcast location manager and client location filter work together to reliably and efficiently transmit data, notifications, and events to specific locations over the broadcast network for all applications involved. |
| US09648105B2 |
Unified snapshot storage management, using an enhanced storage manager and enhanced media agents
An illustrative approach to managing snapshots streamlines how and when snapshots are generated in a storage management system, such that fewer snapshots may be generated without diminishing the scope of data protection. A novel unified-snapshot storage policy may govern snapshots for any number of subclients. A unified-snapshot job based on the unified-snapshot storage policy enables the illustrative storage management system to automatically discover relevant components and generate at most one snapshot per target logical unit number (“LUN”) in a storage array. Each snapshot may comprise the data of any number of subclients and/or clients in the storage management system. Accordingly, one unified-snapshot job may yield a minimum but sufficient number of snapshots comprising data of all subclients associated with the governing unified-snapshot storage policy. An enhanced storage manager may manage the unified-snapshot jobs. One or more enhanced media agents and/or data agents may participate in the unified-snapshot jobs and in subsequent cataloguing of the snapshots. |
| US09648098B2 |
Predictive peer determination for peer-to-peer digital content download
Each computing device in a peer-to-peer network stores particular digital content. A computing device in the peer-to-peer network includes a peer prediction system that obtains an indication of digital content that has not been downloaded to the computing device but is predicted to be downloaded by the computing device in the future (e.g., in response to a user request for the digital content). The peer prediction system obtains a list of peer computing devices in the peer-to-peer network that have at least part of the digital content, and communicates with those peer computing devices to determine connectivity information for each of those peer computing devices. The computing device maintains a record of this connectivity information, and in response to a subsequent user request to download the digital content, uses the maintained record to determine which peer computing devices to access to obtain the digital content. |
| US09648097B2 |
Cloud-to-device messaging for application activation and reporting
A computer-implemented method and system for updating application data for a first instance of an application via C2DM is disclosed. An application server may receive a request from the first client computing device for updated application data via a network connection. The updated application data may correspond to a second instance of the application at a second client computing device. In response to determining the second instance of the application at the second client computing device supports push notifications, the system and method may generate a C2DM message including a user ID corresponding to the first client computing device and the request for updated application data. A server may then send the C2DM message to the second client computing device, wherein the C2DM message causes the second instance to wake up and generate the updated application data. The updated application data may be returned to the first client computing device. |
| US09648096B2 |
Distribution control system, distribution system, distribution control method, and computer-readable storage medium
A distribution control system is connected to a plurality of communication terminals that output image and/or sound data indicating at least either one of an image and sound and transmits the image and/or sound data to the communication terminals. The distribution control system includes a browser management unit is configured to start up a browser appropriate for the communication terminals; a browser configured to generate the image and/or sound data by rendering content data; a transmitter configured to transmit the image and/or sound data to the communication terminals; and a receiver configured to receive input information from the communication terminals. The transmitter is configured to transmit the image and/or sound data updated by the browser in accordance with the input information to the communication terminals. |
| US09648093B2 |
Application service provider delivery system
In one embodiment, a display engine and one or more data files are determined. They are then sent to a website provider's network. The display engine and data are used to provide ASP functionality without contacting the ASP network for every user request. So even if the ASP network is not available, the ASP functionality provided by the display engine and data is always accessible to the website provider. For example, the website provider's network may provide the ASP functionality by displaying data in one or more data files at a user's display device. This is performed without relying on the availability of the ASP network. |
| US09648089B2 |
Context-aware hypothesis-driven aggregation of crowd-sourced evidence for a subscription-based service
A method and system for providing an answer to a subscription-based query service. The method includes acquiring context information and evidence information from one or more electronic devices based on a query. One or more belief values are assigned based on the evidence information and the context information. The belief values are aggregated for determining a score for competing hypotheses using a probabilistic model. Sufficiency of hypotheses is determined based on statistical significance for potential answer information to the query. |
| US09648082B2 |
Functionality inoperable unless node registered at remote site
Systems and methods for providing registration at a remote site that may include, for example, a monitoring module that may communicate with a remote site. A registration protocol may be used by the monitoring module and the remote site in generating the messages communicated during the registration process. The monitoring module may gather and generate various identification information to be included in the registration protocol messages. The registration information provided by the monitoring module may be stored at the remote site in a database server having a database. A confirmation message may be communicated from the remote site to the monitoring module that may either acknowledge successful registration or report that an error occurred during the registration process. |
| US09648081B2 |
Network-attached memory
A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data. |
| US09648079B2 |
System and method for providing content to a requesting terminal
A system and method, responsive to receiving a request for content from a terminal, to respond to the terminal with instructions configured to set up a bi-directional communication channel at the terminal for communication between a server and the terminal and to subsequently load the requested content. The requested content comprises at least one referencing object and a plurality of referenced objects belonging to the content. The method and system will generate a modified referencing object by replacing, in the referencing object, links to referenced objects that are external links with modified links that point to a locally stored version of the same object and then to send the referenced objects to the terminal over the bi-directional communication channel. The modified referencing object will be sent to the terminal such that the modified links in the modified referencing object point to referenced objects previously sent to the terminal. |
| US09648076B2 |
Method and system for generating values for a request for caching of content items
A web browser (20) at a client (12) generates a request (26) for content from an origin server (18). A cache server (16) intercepts the request and examines the request to determine whether the request should be transformed. More specifically, the cache server compares transform criteria (40) to a uniform resource identifier portion (28) and a header portion (30) associated with the request. By transforming the request such that information in the header portion is included in the uniform resource identifier portion, the cache server can cache the content associated with the request using the uniform resource identifier portion of the request. |
| US09648073B2 |
Streaming control for real-time transport protocol
Dynamic control of transport protocols utilized in the streaming of media content based in part on the type of content, latency requirements, network conditions and/or device capabilities is described. The techniques provide a source device to dynamically switch between User Datagram Protocol (UDP) and Transmission Control Protocol (TCP) to stream media content to a sink device. For example, during a Wi-Fi peer-to-peer remote display session associated with real-time media content (e.g., live streaming sporting event, or gaming applications), the source device may utilize Real-time Transport Protocol (RTP) over UDP to transmit the media stream to the sink device. Conversely, when the media content is not latency critical, such as playback of stored media (e.g., movie), the source device may dynamically switch to RTP over TCP in order to provide reliable data transmission. |
| US09648070B2 |
Cloud queue access control
An example implementation may involve a computing system receiving, from a media playback system, a request to initiate playback of a cloud queue. The cloud queue may currently have a first access status that authorizes a first set of queue operations, which may include playback of the cloud queue. After receiving the request to initiate playback, the computing system may cause audio tracks of the cloud queue to be queued in a local queue of the media playback system such that the media playback system may playback audio tracks of the cloud queue via the local queue. The computing system may modify the access status of the cloud queue to a second access status. This second access status may authorize a second set of queue operations on the cloud queue. The computing system may cause access to the local queue to be restricted to the second set of queue operations. |
| US09648064B1 |
Method and system for stabilizing and streaming first person perspective video
It is possible to capture video information using one or more body mounted cameras, to transmit that information over a wireless communication channel, and to process that information, such as by using angular momentum information captured by gyroscopes, to obtain an image which is suitable for viewing in real time. This technology can be applied in a variety of contexts, such as sporting events, and can also be applied to information which is captured and stored for later use, either in addition to, or as an alternative to, streaming that information for real time viewing. |
| US09648063B1 |
Personalized content delivery using a dynamic network
Personalized content delivery using a dynamic network may include, using a processor, continually receiving, from each of a plurality of mobile devices, a location of the mobile device and a list specifying at least one RF device detected by the mobile device while at the location; and, estimating, using the processor, location information for the RF devices according to the locations and the lists. Using the processor, a determination may be made that a first RF device from the lists is proximate to a stationary presentation device. Responsive to the determining and using the processor, content may be provided to the stationary presentation device. The content may be selected, at least in part, according to the location information of the first RF device. |
| US09648060B2 |
Systems and methods for medical diagnostic collaboration
Certain examples provide systems and methods for medical diagnostic collaboration. An example system includes a conversation manager to facilitate a first conversation between a first device and a second device. The conversation manager manages a plurality of conversations based on respective conversation identifiers assigned to each of the plurality of conversations. The example system also includes a collaboration session manager to facilitate, via the first conversation, a collaboration session between the first and second devices, which allows a user of the first device and a user of the second device to view, share, and comment on a medical study. In addition, the example system includes a context manager to manage context information to describe a state of the medical study as it is displayed on the first device to synchronize a state of the medical study displayed on each of the first and second devices. |
| US09648056B1 |
Geographic content discovery
Disclosed are various embodiments for a geographic content discovery application. The geographic location of a client device is determined. Opportunities to obtain content are communicated to the client responsive to the client device being located in a defined geographic boundary. The content may be determined as a function of relevance, incentives associated with the geographic boundary, or nearby clients. |
| US09648055B2 |
Applications in a flexible registration framework
A processing device executing an application that is logged in to a user account recognized by a registration service receives information identifying a device that has not been bound to any user account, wherein the application supports a plurality of registration techniques. The processing device identifies a registration technique supported by the device that is to be used for registration of the device. The processing device performs at least one of sending information associated with the registration technique to the device or receiving the information associated with the registration technique. The processing device sends the information associated with the registration technique to the registration service, and then receives a message from the registration service, wherein the message indicates that the information satisfied a criterion of the registration technique and comprises a notification that the device is bound to the user account. |
| US09648053B2 |
On-demand registration for internet protocol multimedia subsystem (IMS) services
A device may receive service information associated with an internet protocol multimedia subsystem (IMS) service. The IMS service may be provided via an IMS network. The service information may include information that identifies a terminating device that is to receive the IMS service. The device may cause registration trigger information to be provided to the terminating device based on receiving the service information. The registration trigger information may be provided to the terminating device to cause the terminating device to register to the IMS network to allow the terminating device to receive the IMS service. |
| US09648046B2 |
Dynamic adjustment of authentication policy
A computer-implemented method for managing an authentication policy for a user on a network of an organization includes determining at least one social media attribute of the user, and a social media risk value is assigned based on the at least one social media attribute of the user. The method further includes determining at least one network activity risk attribute of the user, and a network activity risk score is assigned based on the at least one network activity risk attribute. A current risk assessment score of the user is calculated based on the social media risk value and the network activity risk value. An authentication policy for the user is determined based on the current risk assessment score. |
| US09648038B2 |
Propagation of viruses through an information technology network
Requests to send data from a first host within a network of hosts are monitored against a record of destination hosts that have been sent data in accordance with a predetermined policy. Destination host identities (not the record) are stored in a buffer. The buffer size is monitored to determine whether requests from the first host are pursuant to viral activity therein. |
| US09648036B2 |
Systems for network risk assessment including processing of user access rights associated with a network of devices
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for network risk assessment. One of the methods includes obtaining information describing network traffic between a plurality of network devices within a network. A network topology of the network is determined based on the information describing network traffic, with the network topology including nodes connected by an edge to one or more other nodes, and with each node being associated with one or more network devices. Indications of user access rights of users are associated to respective nodes included in the network topology. User interface data associated with the network topology is generated. |
| US09648034B2 |
Systems and methods for detecting and scoring anomalies
Systems and methods for detecting and scoring anomalies. In some embodiments, a method is provided, comprising acts of: determining whether the digital interaction is suspicious; in response to determining that the digital interaction is suspicious, deploying a security probe of a first type to collect first data from the digital interaction; analyzing first data collected from the digital interaction by the security probe of the first type to determine if the digital interaction continues to appear suspicious; and if the first data collected from the digital interaction by the security probe of the first type indicates that the digital interaction continues to appear suspicious, deploying a security probe of a second type to collect second data from the digital interaction. |
| US09648033B2 |
System for detecting the presence of rogue domain name service providers through passive monitoring
A method, system, computer program product embodied in a computer readable storage medium, and computer system are disclosed for identifying a rogue domain name service (DNS) server. Embodiments include passively monitoring traffic on a target network; and identifying a DNS resolution response in the traffic on the network. The DNS resolution response includes a mapping of a domain to an internet protocol (IP) address. The DNS resolution response is compared with a preconfigured list of known mappings of domains to IP addresses. Based on the results of the comparison, it can be determined whether the DNS resolution response is correct. In cases where the DNS resolution response is incorrect, the provider of the DNS resolution response is a rogue DNS server. |
| US09648026B2 |
Cryptographic method for securely exchanging messages and device and system for implementing this method
At least one embodiment refers to a method for securely exchanging messages between at least two devices, each of them storing a shared secret key. The method comprises: at each device: generating a random number, then sending it to the other devices; determining a first key by a first operation based onto said secret key and each random number; determining a second key based on said first key and said random numbers; at a sending device: determining a pseudo message on the basis of the message and said random numbers; calculating then sending a cryptogram on the basis of said pseudo message and said second key; and at the receiving device: decrypting said cryptogram by means of said second key; and retrieving said message from said pseudo message. |
| US09648014B2 |
Methods and apparatus for non-contact radio frequency detection and automatic establishment of corresponding communication channel
Methods and apparatus for establishing secure communications are disclosed. An identifier is received from a personal object such as a ring. This identifier is received, for example, through a non-contact near field communication. The identifier is recognized and associated to a mobile terminal device of a user, the mobile terminal device being separate from the object. Then, a secure communication channel is established with the mobile terminal device over another connection that preferably provides a secure communication channel. |
| US09648011B1 |
Tokenization-driven password generation
Applications usually require users to present passwords as a form of identification in order to access user accounts. To improve the security and convenience for accessing such accounts, tokenized passwords may be used in place of or in addition to traditional passwords. Client devices retrieve password rules from an application associated with the user account, and retrieve token tables based on the password rules. The client device receives information from the user for use as a password seed. Using the password seed as an input to the token tables, the client device generates a tokenized password. The tokenized password is transmitted to the application for association with the user account. The tokenized password is not saved at the client device but is re-generated each time the user accesses the account, improving the security of the token-driven password generation system. |
| US09648010B2 |
Relay device, non-transitory storage medium storing instructions executable by the relay device, and service performing system
A relay device communicates with a server and a client device and includes a storage and a controller. The controller is configured to: receive, from the server, service use information which is to be used for the client device to use a service; transmit the received service use information to the client device; receive, from the client device, transmission instructing information containing key information which identifies CA certificate data stored in the storage and used for the client device to verify server certificate data; and transmit, to the client device, the CA certificate data identified by the key information contained in the received transmission instructing information. The CA certificate data is stored in the storage. |
| US09648009B2 |
Efficient network layer for IPv6 protocol
An electronic device may include a network interface that may enable the electronic device to wirelessly couple the electronic device to other electronic devices. The electronic device may also include a processor that may determine at least one data path to the other electronic devices using a Routing Information Protocol—Next Generation (RIPng) routing mechanism. After identifying at least one data path to the other electronic devices, the processor may determine whether the identified data path(s) is secure using a Datagram Transport Layer Security (DTLS) protocol. If the identified data path(s) is determined to be secure, the processor may send Internet Protocol version 6 (IPv6) data packets to the other electronic devices via the secure data path(s). |
| US09648008B2 |
Terminal identification method, and method, system and apparatus of registering machine identification code
A terminal identification method, a machine identification code registration method and related system and apparatus are disclosed. After receiving a first request for which signature or certificate verification is to be performed from a terminal, a service network obtains a signature or certificate of a trusted party for a machine identification code identifier of the terminal from the first request, wherein the machine identification code identifier being an identifier allocated by the trusted party to the machine identification code of the terminal. The service network verifies the obtained signature or certificate, and if a verification result indicates legitimacy, identifies the terminal using the machine identification code identifier obtained from the signature or certificate. The present disclosure further provides a trusted party and a method of registering a machine identification code by the trusted party. The present scheme can efficiently realize terminal identification, occupy fewer resources and facilitate better privacy protection. |
| US09647997B2 |
USB interface for performing transport I/O
Systems and methods for implementing a Transport I/O system are described. Network encrypted content may be received by a device. The device may provide the network encrypted content to a secure processor, such as, for example, a smart card. The secure processor obtains a network control word that may be used to decrypt the network encrypted content. The secure processor may decrypt the network encrypted content to produce clear content. In embodiments, the secure processor may then use a local control word to generate locally encrypted content specific to the device. The device may then receive the locally encrypted content from the secure processor and proceed to decrypt the locally encrypted content using a shared local encryption key. The secure processor may connect to the device via a standard connection, such as via a USB 3.0 connector. |
| US09647993B2 |
Multi-repository key storage and selection
System for performing a cryptographic operation, comprising a client system and a server system; said server comprising a multi-repository manager, repositories of cryptographic keys, a processor and a memory; and said client comprising a processor and a memory; wherein said two memories store computer executable instructions that, when executed, cause the client and the server to perform a method comprising: the client sending a request of the cryptographic operation to the server; the multi-repository manager obtaining a set of references to cryptographic keys allowed to the request from the repositories of cryptographic keys; the multi-repository manager establishing a cryptographic key referenced in said set of references as the cryptographic key to be used; the multi-repository manager requesting performance of the cryptographic operation to the repository wherein the cryptographic key to be used is stored; the multi-repository manager obtaining the result of the cryptographic operation from the repository that has performed the cryptographic operation; and the server sending the result of the cryptographic operation to the client. |
| US09647986B2 |
Methods, systems, and computer readable media for providing diameter signaling router with firewall functionality
According to one aspect, the subject matter described herein includes a system for Diameter routing and firewall filtering. The system includes a Diameter signaling router comprising a network interface for receiving, from a first Diameter node, a first Diameter message having Diameter information. The Diameter signaling router also includes a firewall module for determining whether the first Diameter message satisfies a firewall policy. The firewall policy is based on at least a portion of the Diameter information in the first Diameter message. The Diameter signaling router further includes a routing module for forwarding at least a portion of the first Diameter message towards a second Diameter node in response to the first Diameter message satisfying the firewall policy. |
| US09647982B2 |
Peer tunneling for real-time communications
A system performs peer tunneling for real time communication (“RTC”). The system receives, by a tunneling server, a peer service request message from a first user equipment (“UE”) indicating a request for establishing a peer tunnel between the first UE and a second UE. The system determines whether tunneling service is available at the second UE. When tunneling service is available at the second UE, the system sends a first peer service response message back to the first UE including remote tunnel parameters corresponding to the second UE. When tunneling service is not available at the second UE, the system sends a second peer service response message back to the first UE indicating a failed tunnel creation. |
| US09647981B2 |
Network discovery and connection using device addresses not correlated to a device
To prevent tracking as it roams through a network of wireless access points (WAPs), a wireless device changes the MAC address. The device does this by randomizing some or all of the bits in the MAC address or selecting the MAC address from a group of MAC addresses assigned to the device by the device manufacturer. Furthermore, in order to further confuse tracking and make analytics not useful, a device can share MAC addresses with other devices, and check to make sure that a shared MAC address is not actively being used before selecting and using it. |
| US09647976B2 |
Method and device for implementing end-to-end hardware message passing
A method and device for implementing end-to-end Hardware Message Passing (HMP) are disclosed. The device includes: a message memory, a controller, a message input interface and a message output interface. The message memory is configured to temporarily store a message. The controller is configured to perform management on a message in the form of hardware, store a message obtained from the message input interface into the message memory, and read a message from the message memory and transmit the message to a message user via the message output interface. The message input interface is directly connected with a message creator and is configured to obtain a message created by the message creator under the control of the controller. The message output interface is directly connected to the message and is configured to provide a message to the message user under the control of the controller. The disclosure can improve the efficiency of message passing and reduce software management overhead. |
| US09647973B2 |
Applying actions to item sets within a constraint
Items of an item set may be stored by an item server (e.g., mail messages comprising a mailbox stored by a mail server) that supports the application of actions, but only within a constraint (e.g., a maximum duration or computational resources consumed by the action). The application of complex actions to large item sets may exceed the constraint if performed in one request. Moreover, the request may be made by a user interface of a user device, but the user interface may stall while interoperating with the item server to perform the action. Instead, a background process may issue a sequence of requests applying the action to respective batches of items within the constraint. This architecture may enable the user interface to remain responsive to the user while the action is performed, and even to be terminated without jeopardizing the completion of the action upon the item set. |
| US09647972B2 |
Message delivery in messaging networks
In response to receipt of a request message from a requester, a reply message is created. The reply message includes a message identifier of the request message copied from the received request message. The reply message is published to each of a group of replicated message queues. The reply message is identifiable by the requester using the copied message identifier of the request message on any one of the group of replicated message queues prior to being consumed by the requester. |
| US09647971B2 |
Automatic delivery selection for electronic content
Computer program products and methods for the secure delivery of a message in a communication system. The method includes identifying a best method for delivery of a message including considering preferences of a sender and a recipient and sending the message from the sender to the recipient using the identified method. |
| US09647970B2 |
Sorting electronic mail
Emails are received and parsed for a set of dates. A set of words surrounding the set of dates are identified and contextual information is correlated with the set of dates based on the set of words. It is then determined whether the dates are promotional expiration dates based on the contextual information. The emails that have promotional dates are placed in a list having a chronological order that is based on the promotional expiration dates. The current calendar date is checked and emails are excluded from the list in response to the current calendar date being chronologically after the promotional expiration date. The list is then displayed based on the exclusion of the email. |
| US09647968B2 |
Systems and methods for invoking chatbots in a channel based communication system
Disclosed systems and methods join a user to pre-existing primary communication channels based upon the information obtained from a user profile. Each channel hosts a different plurality of users and facilitates electronic communication between a corresponding enterprise data source and a remote user device associated with the user. The user is joined to one or more sub-channels associated within a primary channel. A message posted by the user is received and comprises a key identifying a sub-channel, an API token identifying the user, and a first communication. In response, an automated human interface module (bot), which includes a node graph to direct one or more states of a conversation, posts a responsive message including the key, the API token, and a second communication. The API token and key route the responsive message to the user device thereby initiating a secure conversation between the user device and an enterprise data source. |
| US09647960B2 |
Switched data transmission system allowing the cancellation of time dependent loops and usable in particular in avionics applications
This switched data transmission system, that may be used in particular in avionics applications, of the type comprising a plurality of electronic devices and equipment units adapted for transmitting discrete messages over a transmission network, and in which each of the equipment units is connected to a network switch, the switches being connected to each other by means of data transmission links so as to form a physical topology of a loop network, each message being associated with information regarding data flow priority in the network comprising of functional priority information, is characterized in that each message is also associated with information regarding topological priority of data flow in the network. |
| US09647958B2 |
Radio frequency signal router
A RF router for routing n input signals to m destinations, where the router comprises a backplane coupled to a plurality of RF input terminals, a plurality of RF output terminals, a plurality of splitters and a plurality of connectors. The backplane is also coupled to a controller and a plurality of connectors for receiving a plurality of switching matrices. The RF router comprises a plurality of u×v input switch matrices, a plurality of p×q intermediate switch matrices and a plurality of r×s output switch matrices, where at least one of the plurality of u×v input switch matrices, the plurality of p×q intermediate switch matrices and the plurality of r×s output switch matrices are redundant. |
| US09647957B2 |
Throttling usage of resources
A computing device provides a first server. The first server receives a primary request associated with a client. In response to receiving the primary request, the first server processes the primary request to generate a response message. As part of processing the primary request, the first server sends a secondary request to a second server after a delay period expires. The second server accesses a resource as part of processing of the secondary request. The duration of the delay period depends at least in part on a recent latency level of the client with regard to the resource. In this way, the first server throttles access to the resource. |
| US09647955B2 |
Systems, methods, and devices for dynamic resource monitoring and allocation in a cluster system
In an embodiment, the systems, methods, and devices disclosed herein comprise a computer resource monitoring and allocation system. In an embodiment, the resource monitoring and allocation system can be configured to allocate computer resources that are available on various nodes of a cluster to specific jobs and/or sub-jobs and/or tasks and/or processes. |
| US09647953B2 |
Credit-based flow control in lossless Ethernet networks
In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the processor or media access control (MAC) functionality of a network port. The logic is configured to negotiate a credit aging duration during initialization of a link between a receiving endpoint and a sending endpoint, the receiving and sending endpoints being connected in a network fabric. The link includes at least one virtual link. The logic is also configured to receive an amount of available flow credits from the receiving endpoint and transmit one or more packets to the receiving endpoint. The amount of available flow credits are used to determine a capacity to process packets at the receiving endpoint. The exchange of flow credits is performed on a per virtual link basis. Other systems, methods, and computer program products are presented according to more embodiments. |
| US09647951B2 |
Media stream rate reconstruction system and method
In a media delivery system over an Internet Protocol (IP) network, a device for network jitter reduction and rate reconstruction using a means for receiving streams with jitter, buffering the streams, and playing out/streaming each stream at an original rate of respective streams. |
| US09647947B2 |
Block mask register key processing by compiling data structures to traverse rules and creating a new rule set
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a routing appliance coupled to a network compiles data structures to process keys associated with a particular block mask register (BMR) of a plurality of BMRs. For each BMR of the plurality of BMRs, the processor identifies at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked. The processor also builds at least one data structure used to traverse a plurality of rules based on the identified at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked. |
| US09647944B2 |
Segment routing based wide area network orchestration in a network environment
An example method for segment routing based wide area network (WAN) orchestration in a network environment is provided and includes monitoring a segment routing (SR) enabled WAN environment in at least near real-time by a path computation element (PCE) located outside the WAN, receiving an event notification at the PCE, and performing traffic engineering using SR to reroute traffic off shortest paths. In one embodiment, where a current state of the WAN is not pre-computed, performing traffic engineering comprises optimizing routes to remove violation of any utilization policies, deploying the optimized routes in the WAN, re-optimizing routes for other parameters, and further deploying the re-optimized routes in the WAN. In another embodiment, performing traffic engineering comprises optimizing routes to remove violation of any utilization policies and for other parameters, and deploying the optimized routes in the WAN. In another embodiment, performing traffic engineering comprises deploying optimized routes in the WAN. |
| US09647936B2 |
Methods, systems, and computer readable media for routing diameter messages at a diameter signaling router
According to one aspect, the subject matter described herein includes a method for routing Diameter messages. The method includes steps occurring at a Diameter signaling router (DSR) comprising a plurality of Diameter message processors. The method includes receiving a Diameter request message. The method further includes generating a hop-by-hop identifier for identifying a first Diameter message processor of the plurality of Diameter message processors. The method further includes incorporating the hop-by-hop identifier into the Diameter request message. The method further includes routing the Diameter request message to a first Diameter node. |
| US09647935B2 |
Inter-layer quality of service preservation
A server device may store inter-layer quality of service (“QoS”) information, indicating a set of link layer QoS levels that are associated with a particular device, a set of network layer QoS levels that are associated with the set of link layer QoS levels, and a set of MPLS QoS levels that are associated with the set of link layer QoS levels. A network device may establish a set of bearers, that correspond to the set of link layer QoS levels, with a particular device; output information regarding the set of network layer QoS levels that are associated with the set of link layer QoS levels, to allow the particular device to select a bearer, of the set of bearers, via which to output traffic to the network device; receive, from the particular device, traffic via the bearer; and determine a particular MPLS QoS level associated with the received traffic. |
| US09647931B2 |
Systems, and methods for rerouting electronic communications
A system includes first and second apparatuses configured to communicate with a server apparatus; and a third apparatus configured to transmit data to the first apparatus and record number of transfer of the data in the system, the data including information on a destination of the data and the number of transfer, wherein the first apparatus is configured to set the destination to the second apparatus and update the number of transfer, when receiving the data and not being allowed to communicate with the server apparatus, and transmit an updated data including information on the set destination and the updated number of transfer, to the third apparatus, and the third apparatus is configured to transmit the updated data to the second apparatus based on the set destination when the updated number of transfer is equal to or smaller than the recorded number of transfer when receiving the updated data. |
| US09647930B2 |
Route determination in a multi-hop network using multiple routing metrics
The proposed technology provides a computationally efficient way to find suitable routes under consideration of multiple metrics. The considered multi-hop network is represented by a connected graph having nodes and links interconnecting the nodes. The method comprises the step (S1) of obtaining a value of a reference route between a source node and a destination node in the connected graph according a first routing metric. The method further comprises the step (S2) of modifying, based on the value of the reference route according to the first routing metric, the connected graph by modifying link cost, with respect to a second routing metric, of at least one link in the connected graph. The method also comprises the step (S3) of determining at least part of a route between the source node and the destination node in the modified connected graph, based on the modified link cost, according to the second routing metric. |
| US09647927B2 |
Computer-implemented K-shortest path finding method
A computer-implemented method includes a principal process including performing a computational procedure in which the or each vertex preceding a particular vertex receives a notification that a computational procedure has been completed for the preceding vertex; and calculates new path lengths for the particular vertex by adding the length value attributed to the edge from the preceding vertex to the particular vertex to each of the recorded k shortest path lengths from the first vertex to the preceding vertex. A record of the k shortest path lengths calculated for the particular vertex is maintained. After the new path lengths have been calculated for the or each of the preceding vertices, a notification that the computational procedure has been completed for the particular vertex is issued. The computational procedure is performed with the source vertex as the first vertex and each vertex on a path from the source vertex to the destination vertex as the particular vertex. |
| US09647922B2 |
Computer implemented methods and apparatus for trials onboarding
Disclosed are methods, apparatus, systems, and computer readable storage media for trials onboarding. A server may receive a request to generate a trial instance of an organization providing data and functionality for a period of time. Data on the request may also be stored. The trial instance may be selected from a template based on an access channel corresponding to the request. |
| US09647921B2 |
Statistics and failure detection in a network on a chip (NoC) network
Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC. |
| US09647911B1 |
Tracking network data propagation
This disclosure describes at least embodiments of a system for electronically generating data and then tracking propagation of the data across a network of devices using computational analysis of communication activity. The network of devices can include a network of one or more servers, end user computing devices, telecommunications infrastructure, and the like, or a subpart thereof. The system can electronically generate, using electronic hardware, generate data items having a variable quantity associated with them that depends at least on a predetermined quantity of those data items as specified by one or more devices in the network of devices, and which may vary based on the communication activities of one or more devices within the network of devices. An individual data item may include a data structure or representation and may be electronically transmitted within the network. |
| US09647910B2 |
Management server and control method of the management server for managing a service system virtually built using connected components
Methods and apparatuses for managing a service system virtually built are provided. A management server assigns identifiers that are unique to a service system to components used to build the service system, and records connections of the components and the time of building the service system. When detecting a change in the connections of the components, the management server records the changed connection and the time of the change, collects monitoring information and monitoring times from a data center, and records the monitoring information associated with the monitoring times. When receiving information designating a time from a terminal, the management server identifies and outputs the configuration of the service system and the monitoring information at the designated time based on the identifiers of the components associated with the designated time. |
| US09647909B2 |
Monitor a data center infrastructure
A method and apparatus for monitoring a data center infrastructure are described. In one embodiment, the method comprises collecting traffic data from the network, collecting storage I/O performance information, collecting central processing unit (CPU) and memory usage information, determining a virtual infrastructure of the network, compute and storage comprising virtual entities; and grouping the traffic data based at least on the virtual entities. |
| US09647908B2 |
Method, apparatus and system for determining software performance
A method, apparatus and system for determining software performance. After the software is published, performance parameters of operation systems of running the software and performance parameters of run software are acquired from various user terminals. The performance parameters of the operation system of running the software and the performance parameters of the run software is processed to acquire a performance parameter processing result according to a preset method for processing a performance parameter. Performance of the software is determined according to the performance parameter processing result. |
| US09647905B1 |
System and method for optimized management of statistics counters, supporting lock-free updates, and queries for any to-the-present time interval
A method and system for monitoring computer and networking performance. The method includes receiving a request for a tracked statistical item over a specified interval, calculating a result value for the request by adding accrued values recorded within specified interval with interpolated value between last value in the specified interval and most recent value outside the interval using available recorded data for the statistical item organized in ranges with varied granularity, and returning the result value to a requestor. |
| US09647903B2 |
Systems and methods for providing trusted service management services
Embodiments of the invention provide systems and methods for providing trusted service management services. According to one embodiment, a system can include a processor operable to execute computer-executable instructions to: generate a message generated based on a common messaging standard; transmit the message via a common gateway and corresponding interface; receiving, via the common gateway and corresponding interface, a response generated based on the common messaging standard; and process the response based on the common messaging standard. |
| US09647902B2 |
Virtualized network for virtualized guests as an independent overlay over a physical network
An independent overlay and a method for creating an independent overlay of a virtualized network for virtualized hosts over a physical network to allow access between a first virtualized guest and a second virtualized guest over the physical network. The independent overlay includes a physical network; a first virtualized host instantiating thereon a first guest; a second virtualized host instantiating thereon a second guest, wherein a first communication port and a second communication port are communicatively connected to constitute a distributed communication element that enables a virtualized network for communication between the first guest and the second guest via the first communication port and the second communication port, respectively; and a media access (MAC) discovery mechanism. |
| US09647901B2 |
Configuring a content delivery network (CDN)
In a content delivery network (CDN a method includes: receiving a request for a CDN service of a particular type, wherein a CDN service of said particular type defines a fixed number of configurable layers of request processing, sequentially from a first layer to a last layer; and processing said request, starting at said first layer, said processing being based on a modifiable runtime environment, said processing continuing conditionally through each of said layers in turn until either said request is terminated by one of said layers or said last layer processes said request. A layer may cause some of the processing of a request to be handled by another service. The CDN service may be selected from: delivery services, collector services, reducer services, rendezvous services, configuration services, and control services. |
| US09647897B2 |
Dynamic grouping of managed devices
A particular method includes generating, at a server configured to access inventory data associated with one or more managed devices, a graphical user interface (GUI) that is operable to define grouping criteria for one or more dynamic groups of managed devices. The method also includes receiving, at the server via the GUI, first grouping criteria and data identifying an action to be performed with respect to managed devices that satisfy the first grouping criteria. The first grouping criteria is based on at least second grouping criteria and a logical operator. The method further includes determining, at the server based on the inventory data, a group of managed devices that satisfy the first grouping criteria. The method includes initiating, by the server, transmission of a push notification regarding the action to each managed device in the group of managed devices. |
| US09647893B2 |
Method for identifying logical loops in ethernet networks
A method and system for identifying logical loops in an Ethernet network may determine a number of nodes N and a number of links L between nodes. A number of rings R, including a number of major rings and a number of sub-rings for the Ethernet network may be determined. Specific formulas for the values for L, R, and N may be evaluated to determine when the Ethernet network includes logical loops. |
| US09647890B1 |
Mesh network resiliency
Mesh network resiliency technology, in which a first routing configuration for nodes of a mesh network is determined, the first routing configuration being appropriate when a first power source of the mesh network is available. Routing data that indicates routing responsibilities within the first routing configuration is provided to first nodes of the mesh network. An interruption of the first power source for the mesh network is detected by nodes of the mesh network. In response to detecting the interruption, a second routing configuration for nodes of the mesh network is determined, the second routing configuration being appropriate when the first power source of the mesh network is unavailable. Routing data that indicates routing responsibilities within the second configuration is provided to second nodes of the mesh network, each of the second nodes including a second power source that is different than the first power source. |
| US09647888B2 |
Network addressable appliance interface device
The present disclosure relates to an interface device to control an appliance through a network. The interface device can be device-agnostic and can be incorporated into any suitable appliance. Upon initialization, the interface device can determine the capabilities of the attached appliance and send out update information that can be received by a controller. The controller can send commands designated to control the appliance, which are received by the interface device and translated into appropriate commands that are transmitted to the appliance. The interface device can turn the appliance into a network device, such as a home automation network device. |
| US09647881B2 |
Managing a network connection of a switch
Managing a network connection of a switch. Software configuration information relating to the network connection of the switch is obtained, wherein the information specifies at least one VLAN connecting to the switch and a plurality of uplinks to be shared. According to the software configuration information, the plurality of uplinks is assigned to the at least one VLAN to form a corresponding connection relationship, in which relationship, each VLAN corresponds uniquely to one uplink from the plurality of uplinks. The hardware connection between the at least one VLAN and the plurality of uplinks on the hardware layer of the switch is set according to the corresponding connection relationship. Shared links may be formed in the switch, which links have multiple uplinks with redundancy, all in active status. |
| US09647879B2 |
Network backup device and network system
Provided are a network backup device and a network system. The network backup device includes a first connector configured to connect with one or more ports of a first network equipment, a second connector configured to connect with one or more second network equipment, a third connector configured to connect with a third network equipment, a switching module configured to aggregate data transmitted from the second connector, transfer the aggregated data to the third connector, and distribute data transmitted from the third connector to the second connector, and a switch configured to, in response to a fault occurring in a port of the first network equipment, switch from a connection between the second connector and the faulty port of the first network equipment to a connection between the second connector and the switching module. |
| US09647872B2 |
Dynamic identification of other users to an online user
Informing a user of a large scale network dynamically of other network users includes determining dynamically an online context of the user. Other users presently within the online context of the user are identified and trait information is stored that is related essentially only to the user or to the other users in a users store associated with the online context. The user is informed dynamically of the other users based on the stored trait information, such as, for example, an age or other demographic identifier, or information indicative of an expertise, interest, preference, user type and/or other quality of the user or of the other individual. |
| US09647870B2 |
Relay apparatus, system, and computer-readable medium
A relay apparatus includes a storage, and request data reception and transmission units, first and second conversion units, and content identifier reception and transmission units. For each storage service, the storage stores a service identifier, access destination information, and a conversion routine for converting a content identifier and a specified condition for specifying content between a server format and a client apparatus format. The request data reception unit receives a service identifier and a specified condition from a client apparatus. The first conversion unit converts the specified condition into a server format. The request data transmission unit transmits the resulting specified condition according to the access destination information. The content identifier reception unit receives a content identifier from a server. The second conversion unit converts the received content identifier into the client apparatus format. The content identifier transmission unit transmits the resulting content identifier to the client apparatus. |
| US09647869B2 |
Method and system for hosting transient virtual worlds that can be created, hosted and terminated remotely and automatically
Embodiments of the invention relate to providing a method and system for presenting users with the ability to host a virtual world especially one that is capable of being used in a game based environment for teaching and learning, and more specifically to improving ease of customization, enabling on-demand-usage and facilitating content sharing for hosting private virtual locations on virtualized servers specifically so that multiple discreet virtual worlds can be hosted (automatically and remotely), started or removed on one or more servers simultaneously and independently of each other without affecting the other hosts. |
| US09647864B2 |
Method and apparatus for reception of control signaling
A method and apparatus provide reception of control signaling in a wireless communication network. A preamble transmission can be detected from a second device in a first set of at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol starting with a first OFDM symbol in a subframe received on a secondary serving cell operating on an unlicensed carrier, the first OFDM symbol having a first Cyclic Prefix (CP). A second OFDM symbol in the subframe can be determined such that the second OFDM symbol immediately follows the first set of OFDM symbols. Downlink Control Information (DCI) containing a Physical Downlink Shared Channel (PDSCH) resource assignment can be decoded in a second set of OFDM symbols beginning with the second OFDM symbol, the second set of OFDM symbols having a second CP. The duration of the first CP is larger than the duration of the second CP. |
| US09647860B2 |
Soft demapper, calculating system, and method for calibrating soft data of multimedia data stream
By determining a scaling factor for scaling signals according to a signal having low bit error rates, and by adjusting soft data using the scaling factor, when soft data are simulated using the Gaussian Model having obvious errors with respect to reality, impacts of signals having low bit error rates are effectively amplified so that impacts of signals having high bit error rates are effectively reduced on the contrary. As a result, the obvious errors introduced by using the Gaussian Model and a low broadcast quality of digital television signals caused by said obvious errors can be neutralized. |
| US09647858B2 |
Optimizing apparatus and method for a pulse shaping filter and a transmitter
Embodiments of the present invention provide an optimizing apparatus and method for a pulse shaping filter and a transmitter. The apparatus is configured to determine an initial peak-to-average power ratio threshold of the pulse shaping filter, and determine an initial filter coefficient of the pulse shaping filter according to the initial peak-to-average power ratio threshold; determine a constraint condition for optimizing the pulse shaping filter according to the initial peak-to-average power ratio threshold and the initial filter coefficient of the pulse shaping filter; wherein the constraint condition comprises a threshold constraint in a filter coefficient sign domain; and adjust the initial peak-to-average power ratio threshold and the initial filter coefficient of the pulse shaping filter in a case where the constraint condition is satisfied, until a predefined condition is satisfied, so as to obtain an optimized filter coefficient of the pulse shaping filter. |
| US09647855B2 |
Mobile phone payment with disabling feature
A method and system for payments for mobile phone payments with a disabling feature is disclosed. The method includes activating a mobile phone containing contactless payment systems, and having a timeout feature disable the contactless payment systems after a set period of time. |
| US09647853B2 |
Transmitting system, the device and the method for the remote bus
A transmitting system, the device and the method for the remote bus applies to control the remote device via network. The transmitting system comprises of a main computer and a bridge device. The main computer includes a first process unit, a storage unit, a first network port and an agent program. The first process unit dispatches the agent program, and sets up the address space and the connection channels according to the identify information. The bridge device couples to the main computer and the target device. The agent program divides the operation command and generates the first package. The main computer sends the first package to the bridge device via the first network port. The bridge device recovers the first package to the operation command, and drives the target device according to the operation command. |
| US09647848B2 |
Application charging method, device, and system
The present invention discloses an application charging method. The method includes receiving, by a CTF device, a charging rule of an application from a PCRF device, wherein the charging rule of the application carries an application identifier and charging rule parameters of the application, executing the charging rule of the application, and detecting, according to an application identifier, a flow of the application transmitted on one or more bearers, sending, by the CTF device according to charging rule parameters of the application, a charging session establishment request to a charging system and establishing a charging session of the application, collecting charging information about the detected flow of the application, and sending the collected charging information about the flow of the application to the charging system by using the charging session of the application. |
| US09647846B1 |
Systems and methods for verifying the authenticity of graphical images
The disclosed computer-implemented method for verifying the authenticity of graphical images may include (1) identifying a graphical image intended for presentation by a display and then, prior to facilitating presentation of the graphical image by the display, (2) identifying an original unique identifier of at least a portion of the graphical image encoded into the graphical image, (3) computing a subsequent unique identifier of the portion of the graphical image, and (4) determining, by comparing the subsequent unique identifier to the original unique identifier, whether the graphical image is authentic. Various other methods, systems, and computer-readable media are also disclosed. |
| US09647845B2 |
Key downloading method, management method, downloading management method, device and system
Disclosed is a key download and management method, comprising: a device end authenticating the validity of an RKS server by checking the digital signature of a public key of an operating certificate of the RKS server; the RKS server generating an authentication token (AT); after being encrypted with a device identity authentication public key of the device end, returning a ciphertext to the device end; after being decrypted by the device end with a device identity authentication private key thereof, encrypting the ciphertext with the public key of the operating certificate and then returning same to a key server; after being decrypted with a private key of the operating certificate, the key server contrasting whether the decrypted authentication token (AT) is the same as the generated authentication token (AT); and if so, indicating that the POS terminal of a device is valid, thereby realizing bidirectional identity authentication. |
| US09647844B2 |
Governed placement of data analytic results
Metadata respectively associated with one or more input data sets processed by one or more analytic applications is obtained. The metadata for each data set is indicative of at least one of trust and veracity associated with the data set. The one or more analytic applications generate analytic results based on the one or more input data sets. A governed placement is determined for at least the analytic results based on at least a portion of the obtained metadata. |
| US09647837B2 |
Securely filtering trust services records
Embodiments include method, systems, and computer program products for filtering trust services records. Embodiments include receiving a trust services record that includes a plurality of security components and that is usable to secure data that is stored in an untrusted location. It is determined whether the trust services record has been tampered with, including verifying each of the plurality of security components of the trust services record. The trust services record is filtered based on the determination of whether the trust services record has been tampered with. The filtering includes, when the trust services record is determined to have not been tampered with, allowing performance of at least one task with respect to the secured data; and, when the trust services record is determined to have been tampered with, disallowing performance of any task with respect to the secured data. |
| US09647834B2 |
Systems and methods with cryptography and tamper resistance software security
Provided is an arbitrary automation system for secure communications. The system includes a utility device configured for processing critical data associated with the arbitrary automation system, the critical data being structured in accordance with utility device access levels. A key management module (i) provides a data protection key (DPK) for protecting the critical data in accordance with each of the utility device access levels and (ii) generates a user key encryption key (UKEK) for encrypting the DPK based upon the device access levels. The system additionally includes a software module configured for masking an execution state of software within the utility device and the key management module via principles of evasion and resistance. |
| US09647833B2 |
System and method for identity-based key management
A system and method for identity (ID)-based key management are provided. The ID-based key management system includes an authentication server configured to authenticate a terminal through key exchange based on an ID and a password of a user of the terminal, set up a secure channel with the terminal, and provide a private key based on the ID of the user to the terminal through the secure channel, and a private-key generator configured to generate the private key corresponding to the ID of the terminal user according to a request of the authentication server. |
| US09647832B2 |
Efficient methods for protecting identity in authenticated transmissions
Systems and methods are provided for protecting identity in an authenticated data transmission. For example, a contactless transaction between a portable user device and an access device may be conducted without exposing the portable user device's public key in cleartext. In one embodiment, an access device may send an access device public key to a portable user device. The user device may return a blinded user device public key and encrypted user device data. The access device may determine a shared secret using the blinded user device public key and an access device private key. The access device may then decrypt the encrypted user device data using the shared secret. |
| US09647830B2 |
Wireless communication apparatus, integrated circuit and wireless communication method
A wireless communication apparatus has an analog control loop circuitry to generate an analog control signal which adjusts a phase of a voltage-controlled oscillation signal, an integrator to integrate the analog control signal, a phase adjuster to adjust a phase of the voltage-controlled oscillation signal, a digital control loop circuitry, in a first mode, to match a frequency of the voltage-controlled oscillation signal to a frequency of the received signal based on an output signal of the phase adjuster, and in a second mode, to generate a digital control signal which is opposite in phase to the analog control signal and has a frequency, a voltage-controlled oscillator to generate the voltage-controlled oscillation signal based on the analog and digital control signals, and a signal switch to supply the analog control signal to the integrator in the first mode and to the voltage-controlled oscillator in the second mode. |
| US09647825B2 |
Circuit and method for creating additional data transitions
When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply. |
| US09647823B2 |
Enhanced scheduling procedure for full duplex access point
Methods, systems, and devices are described for wireless communication at an access point (AP). A scheduling procedure for using a full duplex wireless local area network (WLAN) AP with legacy station (STA) compatibility (e.g., half duplex) may be implemented. For example, a system may include a full duplex AP and have half duplex STAs with two antennas each. The scheduling procedure may involve dynamic grouping of STAs into half duplex sets, for example, based at least in part on location information of the STAs. The STAs may be grouped such that the AP is able to transmit to one of the half duplex sets while concurrently receiving from another of the half-duplex sets. The AP may employ beamforming, via the STAs, to reduce interference between full duplex in-band communications. |
| US09647820B2 |
Neighbour cell quality measurement in a telecommunications system
The present invention relates to methods and arrangements for neighbor cell quality measurements using silent resource element (RE) grids, and as well to a silent RE grid. |
| US09647819B2 |
Mechanisms to facilitate a telecommunication system to make use of bands which are not-licensed to the telecommunication system
The present invention addresses a method, including configuring a remote device (UE) for measurements of at least one carrier in a first frequency band which is different from a second frequency band which is licensed used for communication by said remote device, receiving a measurement report from said remote device, and deciding on the usability of the at least one measured carrier in said first frequency band for communication by said remote device. Also, a method is proposed, including measuring at least one carrier in a first frequency band which is different from a second frequency band which is licensed used for communication by a remote device, and sending, to a network transceiver device, a measurement report of the measurements. Likewise, corresponding computer program products as well as correspondingly configured devices are addressed. |
| US09647818B2 |
Apparatus and method for single-tone device discovery in wireless communication networks
Embodiments of wireless communication devices and methods for device discovery is generally described herein. Some of these embodiments describe an apparatus having processing circuitry arranged to configure a single-tone discovery signal for transmission in a symbol in a transmission opportunity based on an assignment pattern. The assignment pattern may define frequency positions, for a set of transmission opportunities, at which the apparatus shall transmit discovery signals in the corresponding transmission opportunity. The apparatus may have physical layer circuitry arranged to transmit the single-tone discovery signal in the corresponding transmission opportunity. Other methods and apparatuses are also described. |
| US09647816B2 |
Wireless local area network communications with varying subcarrier spacings
An operation method of station in wireless local area network is provided. The operation method includes generating a legacy preamble, generating a high efficiency (HE) preamble including at least one HE-signal (HE-SIG) field, a HE-short training field (HE-STF), and at least one HE-long training field (HE-LTF), and generating a HE physical layer convergence procedure protocol data unit (HE-PPDU) including the legacy preamble and the HE preamble. Therefore, performance of WLAN can be enhanced. |
| US09647813B2 |
Communication apparatus and communication method
Disclosed is a transmission apparatus capable of properly performing cross carrier scheduling in ePDCCHs. In this apparatus, when communication is performed using a plurality of component carriers (CCs), configuration section 102 configures a first search space as a candidate to which control information for a first CC is assigned and a second search space as a candidate to which control information for a second CC other than the first CC among the plurality of CCs is assigned, within a same allocation unit group among a plurality of allocation unit groups included in a data-assignable region within the first CC, and transmission section 106 transmits control information mapped to the first search space and control information mapped to the second search space. |
| US09647812B2 |
Method and apparatus for receiving data in wireless communication system supporting cooperative transmission
The present invention relates to a wireless communication system. A method for receiving data by a user equipment (UE) in a cooperative multi-point (CoMP) wireless communication system includes receiving information indicating a transmission base station (BS) that actually transmits data among a plurality of BSs that participate in CoMP, receiving information about zero-power channel state information-reference signal (CSI-RS) of each of the plural BSs, and assuming that data is not mapped to a resource element of zero-power CSI-RS corresponding to the transmission BS and receiving the data through a physical downlink control channel (PDSCH). |
| US09647810B2 |
Method and system for mapping pilot signals in multi-stream transmissions
A base station is provided. The base station comprises a downlink transmit path comprising circuitry configured to transmit a plurality of reference signals in two or more subframes. Each subframe comprises one or more resource blocks. Each resource block comprises S OFDM symbols. Each of the S OFDM symbols comprises N subcarriers, and each subcarrier of each OFDM symbol comprises a resource element. The base station further comprises a reference signal allocator configured to allocate a first group of the plurality of reference signals to selected resource elements of a first subframe according to a reference signal pattern. The first group of the plurality of reference signals is for a first group of antenna ports. The reference signal allocator also configured to allocate a second group of the plurality of reference signals to selected resource elements of a second subframe according to the same reference signal pattern. The second group of the plurality of reference signals is for a second group of antenna ports different from the first group of antenna ports. |
| US09647809B2 |
Method for spreading a plurality of data symbols onto subcarriers of a carrier signal
A method for spreading a plurality of data symbols onto subcarriers of a carrier signal for a transmission in a transmission system provides a data vector, including the plurality of data symbols. The provided data vector is transformed, and based on the transformed data vector and a spreading matrix subsequent to the transform, a spread data vector is being created, having a length which corresponds to the number of the subcarriers. |
| US09647807B2 |
System and method for coordinating multiple wireless communications devices in a wireless communications network
A method for allocating radio resources by a coordinating wireless communications device in a wireless communications network including a plurality of wireless communications devices includes: obtaining a plurality of supported narrow-band channels in the wireless communications network; selecting a primary channel from the supported narrow-band channels and using the primary channel to communicate with the plurality of wireless communications devices; organizing the plurality of wireless communications devices into one or more communication groups; and assigning one of the one or more communication group a non-overlapping operating channel for multi-user multiple-input multiple-output (MU MIMO) communication with the coordinating wireless communications device. |
| US09647806B2 |
Method for configuring coordinated multipoint transmission
Provided is a method for configuring coordinated multipoint transmission (CoMP) of the present invention. The method includes: providing a transmission mode to support CoMP and, at a base station (eNB), configuring the transmission mode to support CoMP to a user terminal (UE) by radio resource control (RRC) signaling. According to the method of the present invention, it becomes possible to configure CoMP so that the LTE system can support the CoMP function. |
| US09647803B2 |
Cooperative communication system with adaptive packet retransmission strategy
The invention proposes a method for the transmission of data in a cooperative network comprising a source terminal (S), a destination terminal (D) and a relay terminal (R), comprising: in a first transmission (T1), the transmission of the data of a packet by the source terminal (S) to both the relay terminal (R) and the destination terminal (D); in the event of failure (N1) of the destination terminal (D) to successfully decode the data in the packet of the first transmission, and in the case of the data of the first transmission being successfully (O2) decoded by the relay terminal (R), the relay terminal transmits the data of the packet to the destination terminal in a second transmission (T2); in the event of failure (N3) of the destination terminal to successfully decode the data in the packet of the second transmission (T2), selection of the source terminal and/or relay terminal to retransmit the data of the packet to the destination terminal in a third transmission (T3), where the selection may be based on an assessment of the reliability of the transmission channel between the source terminal and the destination terminal and of the transmission channel between the relay terminal and the destination terminal. |
| US09647802B2 |
Systems and methods for mitigating effects of an unresponsive secure element
A method includes counting a number of successive information frame (I-frame) retransmissions due to a guard timer expiring. A contactless front-end (CLF) transmits the I-frame to a secure element (SE) over a single wire protocol (SWP) interface. The method also includes discontinuing I-frame retransmission when the count equals a retransmission threshold. The method further includes deactivating the SWP interface. |
| US09647800B2 |
Fulcrum network codes
Fulcrum network codes, which are a network coding framework, achieve three objectives: (i) to reduce the overhead per coded packet to almost 1 bit per source packet; (ii) to operate the network using only low field size operations at intermediate nodes, dramatically reducing complexity in the network; and (iii) to deliver an end-to-end performance that is close to that of a high field size network coding system for high-end receivers while simultaneously catering to low-end ones that can only decode in a lower field size. Sources may encode using a high field size expansion to increase the number of dimensions seen by the network using a linear mapping. Receivers can tradeoff computational effort with network delay, decoding in the high field size, the low field size, or a combination thereof. |
| US09647799B2 |
FEC coding identification
The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well. |
| US09647797B2 |
Collision detection using a multiple symbol noncoherent soft output detector
Systems and methods for detecting collisions in radio frequency tags in accordance with embodiments of the invention are disclosed. In one embodiment, a receiver system includes a receiver configured to receive and sample a phase modulated input signal, and a multiple symbol noncoherent soft output detector configured to receive the sampled input signal and to generate a soft metric indicative of the reliability of a detected symbol based upon observations over multiple symbols, a collision detector configured to calculate a decision metric from a set of soft metrics generated by the multiple symbol noncoherent soft output detector and detect a collision when the decision metric satisfies a predetermined criterion. |
| US09647793B2 |
Measuring device, measurement method, and transmission system
A measuring device includes an identifying unit configured to identify a design value of a central frequency of spectrum of an optical signal for each of sub-channels, the optical signal being formed in Nyquist pulse, the sub-channels forming a super-channel in wavelength division multiplexing communication; and a measurer configured to measure the power of the optical signal in a band for each of the sub-channels, the identified design value of the central frequency of the band being a central frequency of the band, the band being narrower than a frequency band of a corresponding one of the sub-channels. |
| US09647792B2 |
Spectral temporal connector for full-mesh networking
A spectral-temporal connector interconnects a large number of nodes in a full-mesh structure. Each node connects to the spectral-temporal connector through a dual link. Signals occupying multiple spectral bands carried by a link from a node are de-multiplexed into separate spectral bands individually directed to different connector modules. Each connector module has a set temporal rotators and a set of spectral multiplexers. A temporal rotator cyclically distributes segments of each signal at each inlet of the rotator to each outlet of the rotator. Each spectral multiplexer combines signals occupying different spectral bands at outlets of the set of temporal rotators onto a respective output link. Several arrangements for time-aligning all the nodes to the connector modules are disclosed. |
| US09647791B2 |
Wavelength configuration method and apparatus for multi-wavelength passive optical network, and multi-wavelength passive optical network system
The present application provides a wavelength configuration method for a multi-wavelength passive optical network, which includes: scanning, by an ONU, a downstream receiving wavelength, and receiving, downstream wavelength information of each downstream wavelength channel that is broadcast by an OLT separately through each downstream wavelength channel of a multi-wavelength PON system; establishing, by the ONU, a downstream receiving wavelength mapping table, where an entry of the downstream receiving wavelength mapping table includes downstream receiving wavelength information, drive current information of a downstream optical receiver and receiving optical physical parameter information of the ONU; selecting, by the ONU, one downstream wavelength from the downstream wavelength information broadcast by the OLT, and setting, according to the drive current information of the downstream optical receiver recorded in a related entry of the downstream receiving wavelength mapping table, an operating wavelength of the downstream optical receiver to the selected downstream wavelength. |
| US09647787B1 |
Activating interference signal rejection filter path based on detection of an interference signal in a wireless distribution system (WDS)
Embodiments of the disclosure relate to activating an interference signal rejection filter path based on detection of an interference signal in a wireless distribution system (WDS). In this regard, in one aspect, a filter path selection circuit is configured to activate an interference rejection filter path configured to suppress a predefined interference signal when the predefined interference signal is detected in a received radio frequency (RF) signal. In another aspect, the filter path selection circuit is configured to detect the predefined interference signal by comparing a measured power level of the predefined interference signal against a predefined power threshold. By activating the interference rejection filter path to suppress the predefined interference signal based on detection of the predefined interference signal, it is possible to dynamically respond to the predefined interference signal that may randomly appear in the WDS, thus providing an enhanced overall RF performance in the WDS. |
| US09647786B2 |
Determining bitloading profiles based on sNR measurements
With the introduction of orthogonal frequency division multiplexing (OFDM) technology in to communication channels in a cable network, cable modems that receive data downstream over subcarriers of the OFDM channel are grouped in to modulation tiers based on at least one metric. A profile is generated for each OFDM channel based on the measurements across cable modems and subcarriers related to the OFDM channel, including the metric values used to group the cable modems in to the modulation tiers. Included in an OFDM profile may be a scheme for allocating marginal cable modems in to the plurality of modulation tiers. The methods and systems for generating modulation and coding scheme profiles enable more efficient modulation by network elements. |
| US09647783B2 |
Automatic checking method for clock synchronization and specialized apparatus thereof
The invention relates to an automatic checking method for clock synchronization, comprising the following steps: (1) regularly acquiring clock signals sent by a Beidou signal source, a GPS signal source and an SNTP signal source; (2) performing subtraction to the clock signals of the Beidou signal source and the GPS signal source and evaluating the absolute value of the difference; at the same time, performing subtraction to the clock signals of the Beidou signal source and the SNTP signal source and then evaluating the absolute value of the difference and finally judging the results of the two differences; and (3) constantly repeating steps (1) and (2). The operations in the present invention can efficiently avoid the problems in the existing technology, guarantee the consistency and accuracy of system time, and guarantee the stable and safe operation of the system and the normal operation of other power grid businesses. |
| US09647782B2 |
Frame synchronization for data transmission over an optical network
We disclose an interface device configured to inter-convert CPRI data frames and Optical Transport Units (OTUs). The interface device acquires frame synchronization by temporarily storing data in a buffer bank such that translated sync characters are placed at respective predetermined locations within the buffer bank. Each translated sync character represents, in the corresponding OTU, a respective sync character of a CPRI hyperframe. The interface device is configured to distinguish translated sync characters from payload-data words of identical value based on predetermined alignment, in the buffer bank, of data temporarily stored therein for conversion into the CPRI data format. The interface device advantageously enables multiplexing of a plurality of CPRI links and aggregation and encapsulation of the multiplexed CPRI data into a stream of OTUs for transmission to the intended destination over an Optical Transport Network. |
| US09647780B2 |
Individualizing a content presentation
Embodiments provide an apparatus, a system, and a method. A method individualizing a presentation of content includes receiving data indicative of a physical orientation of a person relative to a display operable to present the content. The method also includes selecting a display parameter of the presented content in response to the received data indicative of a physical orientation of a person. The method further includes employing the selected display parameter in presenting the content. The method may include generating the data indicative of a physical orientation of a person relative to a display operable to present the content. The method may include receiving information indicative of a change in the physical orientation of the person proximate to the display; and changing the display parameter of the presented content in response to the received information indicative of a change in the physical orientation of the person proximate to the display. |
| US09647779B2 |
Systems, methods, and apparatus to identify media devices
Systems, methods, and apparatus to identify media devices are disclosed. An example method includes determining an internet protocol address of a requesting device of a received network communication. A first lookup is performed to identify a media access control address of the requesting device based on the internet protocol address. Data identifying the network communication is stored in association with the media access control address. |
| US09647775B1 |
Power amplification module
A power amplification module includes a first input terminal arranged to receive a first transmission signal in a first frequency band, a second input terminal arranged to receive a second transmission signal in a second frequency band higher than the first frequency band, a first amplification circuit that amplifies the first transmission signal, a second amplification circuit that amplifies the second transmission signal, a first filter circuit located between the first input terminal and the first amplification circuit, and a second filter circuit located between the second input terminal and the second amplification circuit. The first filter circuit is a low-pass filter that allows the first frequency band to pass therethrough and that attenuates a harmonic of the first transmission signal and the second transmission signal. The second filter circuit is a high-pass filter that allows the second frequency band to pass therethrough and that attenuates the first transmission signal. |
| US09647773B2 |
System and method for a subscriber powered network element
A system for powering a network element of a fiber optic wide area network is disclosed. When communication data is transferred between a central office (CO) and a subscriber terminal using a network element to convert optical to electrical (O-E) and electrical to optical (E-O) signals between a fiber from the central office and twisted wire pair, coaxial cable or Ethernet cable transmission lines from the subscriber terminal, techniques related to local powering of a network element or drop site by the subscriber terminal or subscriber premise remote powering device are provided. Certain advantages and/or benefits are achieved using the present invention, such as freedom from any requirement for additional meter installations or meter connection charges and does not require a separate power network. |
| US09647772B2 |
Signal decision circuit, optical receiver, and signal decision method
A signal decision circuit includes: a first decision circuit configured to identify a voltage level of an input signal using an average level of an amplitude of the input signal as a first threshold level; a detection circuit configured to detect an average of an amplitude absolute level based on the average level of the amplitude; a second decision circuit configured to identify a voltage level of the input signal using a second threshold level obtained by adding the average of the amplitude absolute level to the average level of the amplitude; and a third decision circuit configured to identify a voltage level of the input signal using a third threshold level obtained by subtracting the average of the amplitude absolute level from the average level of the amplitude. |
| US09647771B2 |
Wavelength optimization for underwater optical communications
Systems and methods for wavelength optimization for underwater optical communication can include a plurality of n lasers having different wavelengths λi for i=1 to n, a beam splitter and a corner retro-reflector. The plurality of n lasers can simultaneously illuminate the beam splitter along a coincident axis. The plurality of n lasers can be selectively blocked so that only one laser wavelength λi at a time impinges on the beam splitter. A portion passes through the beam splitter to establish a reference signal, while the remainder is reflected off the corner retro-reflector. A portion of return illumination passes through the beam splitter to establish a return signal. The process can be repeated for each of n lasers for i=1 to n. The λi wavelength where the normalized signal-to-noise differential between the reference signal and return signal is the minimum can be the optimum communication wavelength. |
| US09647769B2 |
Maximum likelihood decoding
In a coherent receiver of an optical communication system, a method of processing a detected symbol estimate to determine a most likely value of a corresponding transmitted data word, the transmitted data word comprising one or more data bits encoded in a transmitter using a predetermined constellation of at least two symbols. A set of two or more virtual constellation points are define in a decision region corresponding to a possible value of the data word. The detected symbol estimate is processed to find a most likely virtual constellation point given the detected symbol estimate. The most likely value of the corresponding transmitted data word is determined based on the most likely virtual constellation point. |
| US09647768B2 |
Monolithic optical receiver and a method for manufacturing same
A monolithic Receiver Optical Sub-Assembly (ROSA) device is provided and a method for producing the device. The device comprises: at least one antenna configured to receive optical signals; at least one rectifier configured to rectify electrical signals being electrical representation of the received optical signals and having frequencies within an optical band range; and at least one amplifier, coupled to the rectifier and configured to amplify rectified electrical signals; and wherein the ROSA is also characterized in being a single monolithic device. |
| US09647767B2 |
Estimation and compensation of local oscillator frequency offset and chromatic dispersion using pilot tones in spectral-shaping subcarrier modulation
A signal processing method including obtaining, using an optical receiver, a data signal that comprises one or more pairs of pilot tones and a plurality of subcarrier signals, identifying the one or more pairs of pilot tones, determining a local oscillator frequency offset estimation for the data signal using the one or more pairs of pilot tones, wherein the local oscillator frequency offset estimation indicates a frequency offset, and compensating the data signal in accordance with the local oscillator frequency offset estimation. A signal processing method including obtaining, using an optical receiver, a data signal that comprises one or more pairs of pilot tones and a plurality of subcarrier signals, identifying the one or more pairs of pilot tones, determining a chromatic dispersion estimation for the data signal using the one or more pairs of pilot tones, and compensating the data signal in accordance with the chromatic dispersion estimation. |
| US09647765B2 |
Method and apparatus for transmitting phase shift keyed optical signals
A burst-mode phase shift keying (PSK) communications apparatus according to an embodiment of the present invention enables practical, power-efficient, multi-rate communications between an optical transmitter and receiver. Embodiments may operate on differential PSK (DPSK) signals. An embodiment of the apparatus includes an average power limited optical transmitter that transmits at a selectable data rate with data transmitted in bursts, the data rate being a function of a burst-on duty cycle. DPSK symbols are transmitted in bursts, and the data rate may be varied by changing the ratio of the burst-on time to the burst-off time. This approach offers a number of advantages over conventional DPSK implementations, including near-optimum photon efficiency over a wide range of data rates, simplified multi-rate transceiver implementation, and relaxed transmit laser line-width requirements at low data rates. |
| US09647764B2 |
Adaptive compensation circuitry for suppression of distortions generated by the dispersion-slope of optical components
A distortion compensation circuit compensates for the distortions generated by the dispersion-slope of an optical component and the frequency chirp of an optical transmitter. The dispersion compensation circuitry can be utilized in the optical transmitter, the optical receiver and/or at some intermediate point in a fiber-optic network. One embodiment of the compensation circuit utilizes a primary electrical signal path that receives at least a portion of the input signal and a delay line; and a secondary signal path in parallel to the primary path that receives at least a portion of the input signal and including: an amplifier with an electrical current gain that is proportional to the dispersion-slope of the optical component, an optional RF attenuator, an optional delay line, a “squarer” circuit, and a “differentiator” circuit. Another embodiment of the disclosure performs simultaneous, and independent, compensation of second-order distortions generated by both the dispersion-slope of a first optical component and the dispersion of a second optical component. Other embodiments of the disclosure perform adaptive predistortion for compensation of distortions generated by the dispersion-slope of a first optical component and the dispersion of a second optical component to maintain optimum compensation even if the dispersion properties of the optical components change with time. |
| US09647760B2 |
Optimized dynamic bandwidth scheduler
A method allocating timeslots for transmission of data packets and REPORT messages in a communication network including plural logical links managed by a terminal, including: implemented at each cycle by the terminal receiving at least one REPORT message from at least one logical link, the REPORT message including an updated queue length expressed in timeslots of the logical link and, upon receiving the REPORT message, updating the image queue length, based on the updated queue length; allocating to logical links having non-zero image queue length at least one timeslot in a next cycle based on a theoretical transmission time for transmitting data packets or REPORT messages and based on a fraction of overhead associated with the transmission, until all timeslots of the next cycle are allocated or all image queue lengths are zero, and incrementing the theoretical transmission time of each logical link based on its required minimum bit rate. |
| US09647759B2 |
Efficient mapping of CPRI signals for sending over optical networks
A method for communication includes receiving in a first communication interface input frames, which include data symbols that were derived by encoding respective characters, and further include one or more synchronization symbols having no corresponding characters. The characters from the data symbols are recovered, and the recovered characters are transmitted to a second communication interface by mapping the characters into communication frames and discarding the synchronization symbols. The characters are extracted from the communication frames in the second communication interface by synchronizing to the input frames independently of the synchronization symbols. The input frames are reconstructed in the second communication interface, including the data symbols and the synchronization symbols, by re-encoding the extracted characters. |
| US09647749B2 |
Satellite constellation
A communication system includes a constellation of communication devices orbiting the earth. Each communication device has a corresponding orbital path or trajectory with an inclination angle of less than 90 degrees and greater than zero degrees with respect to the equator of the earth. The constellation includes a first group of communication devices orbiting at a first altitude from the earth and at a first inclination angle. The constellation also includes a second group of communication devices orbiting at a second altitude from the earth lower than the first altitude and at a second inclination angle different from the first inclination angle. |
| US09647746B1 |
Receiving device
A radio receiver includes: a plurality of tuners that receives a broadcast signal through separate antennas; phase shifters, an adder, and a phase diversity processing unit for adjusting and compositing a phase of an output signal of each tuner of the tuners; a demodulating unit that performs demodulation processing to an input signal; a noise component detecting unit that detects a predetermined noise component included in composited output of phase diversity; and a switching processing unit that sets the signal before the composition of the phase diversity to be an object to which the demodulating unit performs the demodulation processing when the detected noise component exceeds a threshold value, and sets the signal after the composition of the phase diversity to be the object to which the demodulating unit performs the demodulation processing when the noise component has not exceeded the threshold value. |
| US09647745B2 |
Channel tracking and transmit beamforming with frugal feedback
In general, this disclosure describes techniques for beamforming using limited feedback that exploit the spatio-temporal channel correlation and avoid the limitations of codebook-based feedback and Markov chain modeling. In one example, a receiving device includes a plurality of receive antennas for receiving communication information, a memory for storing the communication information, and one or more processors for processing the communication information. The one or more processors are configured to receive, through a wireless communication channel, a pilot signal transmitted by a transmitting device, determine, based on the received pilot signal, channel state feedback comprising a quantized representation of the pilot signal as received at the receiving device, and send, through the wireless communication. |
| US09647739B2 |
Method and device for acquiring channel information
The present disclosure discloses a method and device for acquiring channel information, and relates to a massive antenna array transmission technology. The method includes that: a receiving side acquires indexes L of M antennae which send reference signals in N antennae of a sending side; channel information Y between the M antennae and a receiving antenna of the receiving side is acquired; a unitary matrix W with a dimension of N×N is acquired; and an estimate S′ of channel information S between the N antennae of the sending side and the receiving antenna of the receiving side is determined by virtue of the indexes L, the unitary matrix W and the channel information Y. |
| US09647738B2 |
Method and device for transmitting channel state information in wireless communication system
The present invention relates to a wireless communication system. A method for transmitting channel state information (CSI) in a wireless communication system, according to one embodiment of the present invention, comprises steps of: subsampling a codebook for a four-antenna port including 16 precoding matrices; and performing feedback for the CSI on the basis of a subsampled codebook, wherein when a rank indicator (RI) is four, a subsampled codebook includes, from 16 precoding matrices, a first precoding matrix having index 0, a third precoding matrix having index 2, a ninth precoding matrix having index 8, and an eleventh precoding matrix having index 10. |
| US09647735B2 |
Hybrid digital and analog beamforming for large antenna arrays
A hybrid digital and analog beamforming device for a node operable with an antenna array is disclosed. In an example, the hybrid digital and analog beamforming device can include computer circuitry configured to: Segment antenna elements of an antenna array into at least two groups of antenna elements; map antenna ports for transmission chains to one group of the antenna elements; constrain digital precoding weights for a digital precoder for the antenna elements, where the digital precoding weight includes a digital phase and amplitude; and determine analog precoding weights for an analog precoder for the antenna elements, where the analog precoding weight includes an analog phase. |
| US09647733B2 |
Coding scheme for a wireless communication system
Coding techniques for a (e.g., OFDM) communication system capable of transmitting data on a number of “transmission channels” at different information bit rates based on the channels' achieved SNR. A base code is used in combination with common or variable puncturing to achieve different coding rates required by the transmission channels. The data (i.e., information bits) for a data transmission is encoded with the base code, and the coded bits for each channel (or group of channels with the similar transmission capabilities) are punctured to achieve the required coding rate. The coded bits may be interleaved (e.g., to combat fading and remove correlation between coded bits in each modulation symbol) prior to puncturing. The unpunctured coded bits are grouped into non-binary symbols and mapped to modulation symbols (e.g., using Gray mapping). The modulation symbol may be “pre-conditioned” and prior to transmission. |
| US09647730B2 |
Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal
According to one embodiment, a method of transmitting at least one broadcasting signal having PLP (Physical Layer Pipe) data and preamble data includes: encoding the PLP data; encoding the preamble data; mapping the encoded PLP data to PLP data symbols by QAM (Quadrature Amplitude Modulation) modulations; mapping the encoded preamble data to preamble data symbols by QAM modulations; building a signal frame including the PLP data symbols and the preamble data symbols, wherein the preamble data symbols include first signaling information and second signaling information, wherein the first signaling information is for the second signaling information and includes size information of the second signaling information, and wherein the second signaling information is for the PLP data symbols; modulating the signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method; and transmitting the modulated signal frame. |
| US09647728B2 |
Information processing apparatus, method for controlling the same, and non-transitory computer-readable medium
An information processing apparatus comprises: a write unit which writes information to a wireless communication tag; and a setting unit which sets, for the wireless communication tag, one of a plurality of interrupt settings that include at least a first interrupt setting that is for generating an interrupt signal when an external apparatus moves close to the wireless communication tag and a second interrupt setting that is for generating an interrupt signal when information is written to the wireless communication tag from an external apparatus, wherein if the write unit writes first information to the wireless communication tag, the setting unit sets the first interrupt setting for the wireless communication tag, and if the write unit writes second information to the wireless communication tag, the setting unit sets the second interrupt setting for the wireless communication tag. |
| US09647724B2 |
Wireless device pairing
A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit. |
| US09647715B2 |
Contactless signal splicing using an extremely high frequency (EHF) communication link
A first electronic device includes a first electronic circuit and a second electronic circuit. The first electronic device may include an internal communication link providing a signal path for conducting communication signals between the first electronic circuit and the second electronic circuit. An interface circuit may be operatively coupled to the internal communication link. The interface circuit may include an extremely high frequency (EHF) communications circuit configured to receive an EHF electromagnetic signal from another EHF communications circuit of a second electronic device. This EHF electromagnetic signal may enable the second electronic device to control or monitor the first electronic device. |
| US09647712B2 |
Phone holder
The present invention relates to a phone holder for holding a mobile phone. The holder includes at least one lateral support. At least one insert can be located between the lateral support and the phone. Preferably, the insert can be replaceable, and the lateral support is manufactured separately and fastenable to a common body used with holders for multiple phone types. |
| US09647711B2 |
Electronic device
According to one embodiment, an electronic device includes a cover, a flexible board, a coupler, a communication module, and an output device. The cover covers at least a part of the flexible board. The coupler is on the flexible board and has flexibility. The communication module performs close proximity wireless communication by using the coupler. The output device outputs at least a part of data received by the coupler. |
| US09647708B2 |
Advanced signal processors for interference cancellation in baseband receivers
A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the interference canceller are configurable for processing multi-mode signals. |
| US09647703B2 |
Multi-band device with reduced band loading
In an embodiment, an apparatus includes a first radio frequency (RF) signal path and a second RF signal path. The first RF signal path can provide a first RF signal when active and the second RF signal path can provide a second RF signal when active. The second RF signal path can include a matching network with a load impedance configured to prevent a resonance in the second RF signal path due to coupling with the first RF signal path when the first RF signal path is active. |
| US09647697B2 |
Method and system for determining soft information offsets
Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset. |
| US09647692B2 |
Upstream forward error correction codeword filling
A device for codeword filling comprises at least one processor circuit. The at least one processor circuit is configured to receive portions of a data burst, encode the portions into blocks, and add the blocks to a buffer. The at least one processor circuit is configured to generate a first codeword from blocks of the buffer when a number of blocks in the buffer satisfies a threshold, remove the blocks from the buffer, and provide the first codeword for transmission. The at least one processor circuit is configured to generate a set of codewords from remaining blocks of the buffer when a marker indicating a data burst end is detected, the set of codewords being determined based at least on a number of the remaining blocks in the buffer when the marker is detected. The at least one processor circuit is configured to provide the set of codewords for transmission. |
| US09647687B2 |
System and method for low-power digital signal processing
A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal. |
| US09647684B2 |
Memory-based history search
Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware. |
| US09647682B1 |
Data compression system and method
A divider divides an input data into a plurality of data blocks. A hash calculator calculates a hash value of each data block. A compression dictionary memory stores a compression dictionary that stores a previous input data and includes a shared dictionary shared by different data lengths. A hash table memory stores a hash table that stores an address representing a storage location of the data block corresponding to the hash value on the compression dictionary for each data block and includes a shared table shared by different data lengths. An address acquirer acquires the address corresponding to the data block based on the hash table. A matcher determines sameness between the previous data block indicated by the address and the new input data. An encoder generates a compressed data that includes matching information and a matched portion is converted to the address. |
| US09647681B2 |
Pad encoding and decoding
A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a character writing engine for writing a binary character to an empty cell of a multi-dimensional shape beginning with a starting empty cell; a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located; a loop facilitator for looping back to the character writing engine and the next cell determining engine until there are no more data characters or a next empty cell is not determined; and a serialization engine for serializing the cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters. |
| US09647679B1 |
Methods and apparatus for a delta sigma ADC with parallel-connected integrators
Various embodiments of the present technology may comprise a method and device for a delta-sigma ADC. The method and device may comprise receiving an input signal to at least two parallel-connected first-stage integrators and corresponding feedback DACs, and simultaneously integrating the input signal by each of the first-stage integrators. The method and device may further comprise a second stage integrator connected in series with the first-stage integrators, a quantizer, and digital to analog converters, coupled between the output of the quantizer and the inputs of the first-stage integrators. |
| US09647678B2 |
Method for operating radio frequency digital to analog conversion circuitry in the event of a first and a subsequent second input sample with different signs and an digital to analog conversion circuitry
A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample. |
| US09647674B2 |
Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers
A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse. |
| US09647673B2 |
Controllable circuits, processes and systems for functional ESD tolerance
An electronic circuit (100) includes a first circuit (140) having an output and operable to give a warning but that has a sensitivity to an electrostatic discharge (ESD) event, a second circuit (120) that is operationally at least sometimes coupled with the output of said first circuit (140), whereby subject to some of the sensitivity, and a third circuit (240) interposed between said first circuit (140) and said second circuit (120) and operable to filter out at least one instance of an unnecessary warning so as to reduce the sensitivity to the ESD event. |
| US09647672B2 |
Digitally compensated phase locked oscillator
A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phased locked loop (PLL), the phased locked loop comprising: a phase frequency detector, an oscillator, and a PLL output coupled to the output; a first direct digital synthesizer (DDS), the first DDS having an output coupled to the PLL to supply a DDS signal to the PLL for adjusting the frequency within the PLL so as to maintain phase lock over the operating temperature; a temperature sensor; and a processor coupled to the first DDS, the phase frequency detector, and the temperature sensor, the processor configured to set the frequency of the first DDS according to a temperature sensed by the temperature sensor. |
| US09647670B2 |
Oscillator with dynamic gain control
In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit provides the gain control signal to set an absolute value of the gain to a first level during a startup state, and changes the gain control signal to reduce the absolute value of the gain to a second level lower than the first level after the first clock signal has reached a steady state. |
| US09647665B2 |
Semiconductor device and electronic device
To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit. |
| US09647662B1 |
Superconducting tunable coupler
A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane region, a second ground plane region electrically isolated from the first ground plane region by portions of the coplanar superconducting circuit, and a tunable coupler having a first port and a second port. The tunable coupler comprises a variable inductance coupling element coupled between the first port and the second port, a first termination inductor having a first end coupled between a first end of the variable inductance element and a second end coupled to the first ground plane region, and a second termination inductor having a first end coupled between a second end of the variable inductance element and a second end coupled to the second ground plane region. |
| US09647654B2 |
Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device
A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result. |
| US09647653B2 |
Method for reduced power clock frequency monitoring
An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold. |
| US09647652B2 |
Semiconductor device
A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal. |
| US09647643B2 |
Low power buffer with gain boost
The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities. |
| US09647635B2 |
Elastic wave resonators, and elastic wave filters, antenna duplexers, modules and communication devices using same
An elastic wave resonator including comb-shaped electrodes and reflector electrodes formed on a piezoelectric substrate. In one example, an overlapping portion between the comb-shaped electrodes includes a first overlapping region and second overlapping regions. The second overlapping regions can be provided on both outside edges of the first overlapping region. In one example, the overlapping width of the first overlapping region is greater than the overlapping width of the second overlapping region, and the electrode finger pitch in the second overlapping region is greater than the electrode finger pitch in the first overlapping region. |
| US09647634B2 |
Elastic wave filter device and duplexer comprising magnetically coupled inductances
In an elastic wave filter device, a package substrate is provided with an elastic wave filter chip defining a ladder circuit including a plurality of series arm resonators and a plurality of parallel arm resonators, and a first inductance connected in parallel with at least one of the series arm resonators and a second inductance connected between at least one of the parallel arm resonators and a ground potential. The first inductance and the second inductance provided in the package substrate, and the first inductance is magnetically coupled to the second inductance to shift a frequency position of an attenuation pole. |
| US09647633B2 |
Acoustic wave element, branching filter and communication module
SAW element has a substrate; an IDT having a first comb-shaped electrode and a second comb-shaped electrode located on an upper surface of the substrate; and a capacitance element located on the upper surface of the substrate. The capacitance element has a first counter electrode connected to the first comb-shaped electrode and a second counter electrode connected to the second comb-shaped electrode and facing the first counter electrode across a third gaps. The direction from the first counter electrode through the third gaps toward the second counter electrode is a reverse direction from the direction from the first comb-shaped electrode through the gaps toward the second comb-shaped electrode. If it is assumed that the gap and width of the gap are di and wi, and the gap and width of the third gap are Dj and Wj, the following formula holds: 0<Σ(Wj/Dj2)<2Σ(wi/di2). |
| US09647632B2 |
Lumped element radio frequency tuning calibration process
A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port. |
| US09647629B1 |
Variable capacitors for high accuracy tuning
Improved interdigital parallel plate rotary capacitors to be used in automatic MHz range tuners have a grounding technique based on bronze sliding contact to effectively and continuously lead to the ground terminal the rotating comb-like blades of the capacitor and (optional) damping resistors inserted between the sliding contact and the ground terminal. The resistors reduce the high Q of the series resonance of the capacitor with the fringe lead inductance. Tuning sensitivity is reduced and tuning accuracy and repeatability are increased. |
| US09647623B2 |
Signal processor suitable for low intermediate frequency (LIF) or zero intermediate frequency (ZIF) operation
A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops. |
| US09647621B2 |
Methods, systems, and media for controlling audio of an HDMI audio system
Mechanisms for controlling an audio level of an HDMI audio system are provided, the mechanisms comprising: causing audio data to be presented by an HDMI audio system at a current system volume level; receiving a requested volume level from a second screen device; and controlling a system volume level by: (a) determining the current system volume level; (b) determining a change in volume based on a difference between the requested volume level and the current system volume level; (c) determining a direction in which to cause the system volume level to change; (d) sending a volume control message to the system using a consumer electronic control bus connected to the system indicating whether to increase or decrease the system volume level based on the determined direction of system volume change; and (e) repeating (a)-(d) until the current system volume level reaches a predetermined value. |
| US09647620B2 |
Electronic device and integrated circuit comprising a gain control module and method therefor
A method for controlling a gain applied to an audio signal. The method comprises applying a gain step to a gain setting at defined time intervals, and upon detection of at least one zero crossing point within the audio signal, applying the gain setting to a gain control signal for controlling the gain applied to the audio signal. |
| US09647613B2 |
Differential amplifier
A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current. |
| US09647606B2 |
Counter based circuit for measuring movement of an object
An apparatus for measuring movement of an object has a quadrature incremental encoder for providing first and second phases of encoder pulses corresponding to incremental displacements of the object. A first counter counts edges of the encoder pulses according to the sense of the displacement. Clock pulse counts are also made. Acquiring movement data at periodic speed processing moments includes the decoder adjusting encoder pulse data from the first counter using a clock pulse count that is a function of a lapse of time between when the most recent edge of the encoder pulses and the speed processing moment. The clock pulse counts are reset by edges of the first and second phases of the encoder pulses when the decoder acquires the movement data. |
| US09647603B2 |
Controller and control method for electric motor
To provide controller and control method for an electric motor including plural energization systems composed of an inverter and coils corresponding to plural phases. According to the present invention, if any abnormality is detected in one energization system being energized through first diagnosis processing, second diagnosis processing is executed on the energization system having the abnormality detected, which is switched to an unenergized state. Then, if the second diagnosis processing reveals occurrence of a short-circuit, a control gain of a normal energization system is lowered. In addition, a threshold used in the first diagnosis processing on the normal energization system is changed so as to make it difficult to detect an abnormality, hereby keeping the energization control on the normal energization system. Hence, if a short-circuit occurs in at least one of the energization systems, it is possible to avoid stopping the output from the normal energization system. |
| US09647602B1 |
Determination of stator winding resistance in an electric machine
An electric machine assembly includes an electric machine having a stator and a rotor. The stator has stator windings at a stator winding temperature (tS) and the rotor is configured to rotate at a rotor speed (ω). A controller is operatively connected to the electric machine and has a processor and tangible, non-transitory memory on which is recorded instructions for executing a method for determining stator winding resistance. The controller is configured to determine a high-speed resistance factor (rH) which is based at least partially on the torque command (T*), the stator winding temperature (tS), the rotor speed (ω), a characterized torque error and the number of pole pairs (P). The controller may determine a total resistance value (R) based on a weighting factor (k), the high-speed resistance factor (rH) and the low-speed resistance factor (rL). |
| US09647600B2 |
Device for controlling a polyphase inverter
The device according to the invention controls a polyphase inverter (10, 14, 17) intended for powering from a DC current source (CC) a polyphase rotating electric machine (1). The device is of the type of those generating commutation functions driving commutation elements (9, 13) of the inverter in such a way as to obtain a reduction of the losses in the commutation elements and a decrease of an effective current in a decoupling capacitor (16) of the source (CC). According to the invention, this reduction and this decrease are obtained by means of a set of control strategies (21, 24) determining the commutation functions by using additional degrees of freedom of the polyphase machine (1) with respect to a three-phase reference machine. The polyphase machine comprises first and second phase windings forming a first three-phase system (2, 3, 4) and a second three-phase system (5, 6, 7) with distinct neutral points (11, 15) offset angularly by a predetermined angle of offset (Θ). The first and second phase windings are linked respectively to three first and three second power arms (8, 12) formed by the commutation elements. |
| US09647599B2 |
Electronic apparatus
An electronic apparatus includes a rotating electric machine that has a plurality of multi-phase winding sets, each of which has a plurality of phase windings; a plurality of inverter circuits that are connected to the plurality of multi-phase winding sets respectively; and a control circuit that controls the plurality of inverter circuits such that a multi-phase alternating current is supplied to each of the plurality of multi-phase winding sets from each of the plurality of inverter circuits. The control circuit determines that a short circuit occurs when i) a plurality of phase current added values obtained by adding each phase current flowing through each of the plurality of phase windings calculated at each of the plurality of multi-phase winding sets; and ii) an absolute value of a total phase current added value obtained by adding all of the plurality of phase current added values is smaller than a predetermined value. |
| US09647597B2 |
Motor control apparatus and method for controlling motor
A motor control apparatus includes a voltage regulator to execute a voltage increase mode to increase a voltage applied to an induction motor from a lower limit of a first range over time. A frequency regulator executes a frequency decrease mode to decrease a frequency of the voltage from an upper limit of a second range over time. The frequency regulator limits decrease of the frequency when a bus voltage of a bus exceeds a first threshold in the frequency decrease mode. The bus supplies DC power to an inverter to drive the motor. A mode changer alternatively changes the voltage increase mode and the frequency decrease mode to control the motor to change from a free running state to a state in which the voltage and the frequency satisfy a relationship. The determinator determines whether the voltage and the frequency satisfy the relationship. |
| US09647593B2 |
Switched reluctance motors and excitation control methods for the same
Provided are multiple switched reluctance motors and excitation control methods for same. Motors with various structures are provided having the same structural characteristics, a stator formed of an even number of salient pole pairs and a rotor formed of an even number of salient pole pairs. The salient poles of the stator salient pole pairs are arranged opposite the salient poles of the rotor salient pole pairs, with minimal air gaps left between said salient pole pairs, thus leaving the shortest magnetic return paths between the stator salient pole pairs and the rotor salient pole pairs arranged opposite one another, thus satisfying the minimum reluctance principle of the switched reluctance motor. In addition, due to the magnetic isolation between each stator salient pole pair, the performance of the magnetic pole of each stator salient pole pair is controlled by an excitation control power source and changed independently. |
| US09647592B2 |
Inverter drives having a controlled power output
An electromechanical system includes an inverter drive, a component arranged during operation to generate a variable force having one or more periodic frequency components, and processing circuitry arranged to determine the power output of the inverter drive, measure a difference between the power output and a reference power output, and control an output frequency of the inverter drive as a function of the measured difference, so as to stabilize the power output during operation of the component. Other example electromechanical systems, inverter drives and methods are also disclosed. |
| US09647591B2 |
Magnet degradation and damage controls and diagnostics for permanent magnet motors
Techniques for motor magnet degradation controls and diagnostics are disclosed. An exemplary technique determines q-axis current, d-axis current, q-axis voltage, and/or d-axis voltage of a permanent magnet motor based upon sensed current and voltage information of the motor. This information is utilized to determine flux information. The flux information is utilized in evaluating collective state conditions of a plurality of motor magnets and evaluating localized state conditions of a subset of the plurality of motor magnets. The evaluations can be used to identify degradation or damage to one or more of the magnets which may occur as a result of elevated temperature conditions, physical degradation, or chemical degradation. |
| US09647590B2 |
Apparatus for compensating phase error in inverter output voltage
A phase compensation apparatus in an inverter output voltage in a system is provided, whereby performance of an inverter can be enhanced by compensating a time delay of measured voltage of inverter output voltage detection unit. |
| US09647582B2 |
Induction motor-permanent magnet generator tandem configuration starter-generator for hybrid vehicles
Disclosed in the present invention is a tandem starter-generator construction that includes an induction motor-generator, a permanent magnet motor-generator and power transmission unit disposed adjacent to the motor-generators. The induction motor-generator is utilized predominantly as a motor to provide mechanical power at relatively high efficiency as a motor, and as a generator to provide electrical power during regenerative braking. The permanent magnet motor-generator is used predominantly as a generator for very high efficiency power conversion and to capture additional electrical power during regenerative braking to compensates for the regenerative energy captured at lower efficiency by the induction motor-generator. Accordingly, the tandem motor-generator construction disclosed herein overcomes the drawbacks of low efficiency of an induction motor-generator operating in regenerative mode and a permanent magnet motor-generator magnetic drag losses during periods of non-utilization at high speeds in order to improve fuel efficiency of a parallel hybrid vehicle. |
| US09647580B2 |
Wireless signal transmitting apparatus and wireless illumination control apparatus using the same
A wireless signal transmitting apparatus, includes: a piezoelectric harvester configured to generate electrical energy responsive to user switch manipulation; and, a wireless communication circuit configured to generate wireless signals from the electrical energy and wirelessly transmit the wireless signals to an external wireless power receiving device. |
| US09647572B2 |
Method for controlling a converter
A method for controlling a converter including a resonant circuit, where the converter is controlled such that control switches are switched into a first state at the occurrence of an event that is related to a dependent variable of the converter and are switched into a second state at the occurrence of an event that is not related to a dependent variable of the converter. The method may be employed in a converter or an inductive power transfer transmitter. |
| US09647571B2 |
Internal inverter communications
Inverter internal communication features are disclosed. A multiple-stage inverter includes DC to DC and DC to AC converter switches in different power domains, which share no common return path connection. Operating parameters for converter switches in both power domains are determined by a single controller, located in one of the power domains. Converter control signals are communicated from the controller across an interface between the power domains. Respective, separate controllers in each power domain are not required. Components on each side of the interface could be integrated into respective integrated circuits. A planar transformer implemented in wiring levels of a Printed Circuit Board (PCB) that carries components of the inverter could be provided to enable communications between the power domains while reducing component count and physical space requirements. |
| US09647567B2 |
Regulating controller for controlled self-oscillating converters using bipolar junction transistors
A power converter controller and methods for its operation are provided that can control a self-oscillating power converter that uses a Bipolar Junction Transistor (BJT) as a switch by manipulating the current flowing in a control winding. The controller is able to determine the optimum time to remove a short circuit applied to the control winding, as well as being able to determine the optimum time to pass current through the control winding. The controller can further draw power from the power converter using the control winding. The controller is capable of maintaining the midpoint voltage of the power converter in the case that the converter has more than one switch. The controller estimates the output power of the converter without requiring a connection to the secondary side of the converter transformer. The controller further controls entry and exit into a low-power mode in which converter oscillations are suppressed. |
| US09647563B1 |
Active energy recovery clamping circuit to improve the performance of power converters
A regenerative clamping circuit for a power converter using clamping diodes to transfer charge to a clamping capacitor and a regenerative converter to transfer charge out of the clamping capacitor back to the power supply input connection. The regenerative converter uses a switch connected to the midpoint of a series connected inductor and capacitor. The ends of the inductor and capacitor series are connected across the terminals of the power supply to be in parallel with the power supply. |
| US09647556B2 |
DC to DC converters and controllers thereof
In a controller for a DC to DC converter, PWM signal generating circuitry generates a set of PWM signals phase-shifted relative to one another, and controls states of the PWM signals according to a set of control signals. Each PWM signal of the PWM signals has an on-time state and an off-time state. Ramp signal generating circuitry, coupled to the PWM signal generating circuitry, generates a set of ramp signals having substantially the same ramp slope. Each ramp signal of the ramp signals is generated in response to detecting an on-time state of a corresponding PWM signal of the PWM signals. Additionally, a comparing circuit, coupled to the PWM and ramp signal generating circuitry, alternately compares the ramp signals with a preset reference to generate the control signals. A corresponding control signal of the control signals changes the corresponding PWM signal from the on-time state to an off-time state. |
| US09647554B1 |
Single inductor multi-output DC-DC converter and operating method thereof
Provided is a DC-DC converter including an inductor configured to store input energy, a ground switch configured to provide a ground path of the inductor in response to a first signal, an inductor switch connected in parallel to the inductor so as to maintain the energy stored in the inductor in response to a second signal, output switches configured to output the energy stored in the inductor as multi-output voltages in response to third signals, and a switch controller including a switch controller configured to determine cross regulation between the multi-outputs and generate the first to third signals for decreasing the cross regulation. |
| US09647550B2 |
Negative voltage signal generation circuit
A negative voltage signal generation circuit is described. The first thin film transistor (TFT) connects the first ground terminal to the control signal generation unit. The second TFT switch connects to the first TFT switch, the control signal generation unit and the negative voltage signal output terminal. The first capacitor connects to the first TFT switch, the second TFT switch and the control signal generation unit. The present invention is capable of improving the stability of the negative voltage signal generation circuit. |
| US09647546B2 |
Dual-mode voltage doubling buck converter with smooth mode transition
Devices and methods provide a voltage regulating device including voltage supply circuitry configured to receive a first voltage, generate at least a second voltage based on the first voltage, and output an output voltage, the output voltage being one of the first voltage and the second voltage based on a voltage selection signal; regulator circuitry configured to switch between the output voltage and a reference potential based on a control signal; and control circuitry configured to generate the control signal, the control signal having a first duty cycle if the output voltage is the first voltage and a second duty cycle if the output voltage is the second voltage, the control circuitry configured to adjust the second duty cycle based on, at least in part, a droop voltage in the regulator circuitry. |
| US09647544B2 |
Magnetic component, power converter and power supply system
A magnetic component has a core on which windings are wound. The windings are electrically connected in series to constitute a coil of a first reactor. The winding constitutes a coil of a second reactor. The core has a leg portion on which the winding is wound, a leg portion on which the winding is wound, and a leg portion on which the winding is wound. When a current flows through the windings, magnetic fluxes produced from the windings, respectively, and flowing through the winding counteract each other. Furthermore, when a current flows through the winding, induced voltages produced from the windings, respectively, by the magnetic flux produced by the winding counteract each other. |
| US09647537B2 |
Charge pump circuit for generating a negative voltage
A circuit for generating a negative voltage on the basis of a positive voltage, including: at least one first transistor between a first terminal for applying a potential greater than a reference potential and a first node; a first capacitive element between the first node and a second node, a control terminal of said first transistor being linked to the second node; a first switch between the first node and a second terminal for applying the reference potential; a second switch between the second node and a third terminal for providing said negative voltage; a third switch between the second node and the second terminal; and a second capacitive element between the third terminal and the second terminal. |
| US09647534B2 |
Power conversion apparatus
A power conversion apparatus is constituted by a power conversion circuit and a control section. The control section causes a gate driving signal to alternately open and close a set of a first switch and a fourth switch, and a set of a second switch and a third switch based on a circuit current flowing through the power conversion circuit and a voltage of an AC power supply. A current in which a high frequency component is mixed into a low frequency component of the AC power supply flows through the power conversion apparatus by the opening and closing the sets of the switches. |
| US09647530B2 |
Switching power supply with preventive maintenance function
A switching power supply is designed so that a switching frequency deviates from a predetermined range before an output voltage deviates from a predetermined voltage range due to degradation of a choke coil and an output capacitor. The switching power supply designed in that manner is provided with a switching frequency monitoring unit which monitors a switching waveform. By checking if the operating frequency is within a predetermined tolerance, it is determined whether the switching power supply is normally operating or not. |
| US09647528B2 |
Switch control circuit and resonant converter including the same
A resonant converter includes a first switch coupled between a first node and a primary side ground, a second switch coupled between an input voltage and the first node, at least one capacitor and at least one inductor coupled in series between both ends of the first switch, and a switch control circuit that shifts switching frequencies of the first and second switches during a period for which an abnormal event lasts when occurrence of the abnormal event is detected, and shifts the switching frequencies in an opposite direction when the abnormal event ends. |
| US09647524B2 |
Linear actuator
A linear actuator includes an inner core, and an outer core that is provided outside the inner core in a radial direction while being supported by a pair of flat springs. Permanent magnets are formed at one of the inner core and the outer core, and magnetic pole portions are formed at the other of the inner core and the outer core to face the permanent magnet with predetermined gaps formed therebetween. Spacers are respectively provided between the inner core and the flat springs, abutting portions are respectively configured by abutting facing surfaces of the spacers and the inner core and facing surfaces of the spacers and the flat springs adjacent to the spacers in the axial direction, and a plurality of engagement portions including recesses and protrusions are arranged at the abutting portions. |
| US09647522B2 |
Linear induction generator using magnetic repulsion
An electrical generator and method for generating electricity are provided using a linear induction generator that operates based on magnetic repulsion. The electrical generator includes a tube assembly having a tube with an induction coil surrounding the tube and an induction magnet within the tube. A rotor assembly includes a rotor magnet that is positioned with an opposing magnetic moment to the induction magnet and moved in proximity to the induction magnet to cause it to repel the induction magnet causing it to move within the tube and generate and electromotive force in the induction coil surrounding the tube. |
| US09647519B2 |
Inflatable air gap tooling for assembly of rotor and stator
A number of variations may include a method of assembly of a rotor and a stator having a concentric air gap in an electric motor comprising: providing inflatable gap support tooling in a deflated state in an air gap between a rotor and a stator; filling the inflatable gap support tooling with a fluid so that it uniformly fills at least a portion of the air gap between the stator and the rotor and holds the stator and the rotor together as a single unit; placing the single unit into a motor assembly; seating a plurality of bearings into the motor assembly; locking the stator into place in the motor assembly; removing the fluid from the inflatable gap support tooling; and removing the inflatable gap support tooling from the motor assembly. |
| US09647517B2 |
Manufacturing method for helical core for rotating electrical machine and manufacturing device for helical core for rotating electrical machine
A manufacturing method of a helical core for a rotating electrical machine includes: first step forming a yoke portion extending along one direction and tooth portions protruding toward a width direction of the yoke portion from a first side edge of the width direction, with respect to a belt-shaped metal plate extending along the one direction; second step forming a notch at a position between tooth portions of the yoke portion after the first step; and third step processing the belt-shaped metal plate into a helical shape by applying bending to the metal plate so that the belt-shaped metal plate is curved toward the width direction sequentially from a portion where the notch is formed after the second step, and in the third step, a distance between a position where the application of bending starts and the position where the notch is formed is limited to within a predetermined dimension. |
| US09647516B2 |
Fan device
A fan device includes two magnetic members, a fan and a wire. The fan is disposed between the magnetic members, and includes a rotatable hub and a plurality of fan blades radiating from the hub. The wire is mounted on the fan, and has two electrode ends and a plurality of induction portions that are disposed between the electrode ends. Each induction portion is coupled to a respective fan blade, and is co-rotatable with the respective fan blade to intersect a magnetic field between the magnetic members to thereby generate an induced current that flows toward the electrode ends of the wire. |
| US09647515B2 |
Brushless motor and fuel pump having a terminal structure for reducing tensile forces between stator coils
Relay terminals, which are formed integrally with a W-phase terminal, a V-phase terminal and a U-phase terminal provided radially outside bobbins, connect stator coils and the W-phase terminal, the V-phase terminal and the U-phase terminal. Second connection parts of the relay terminals connected to the coils are provided radially inside the W-phase terminal, the V-phase terminal and the U-phase terminal. Thus distances between the second connection part and the inner wall surface of a housing are increased to maintain insulation between the relay terminals and the housing. Thus the relay terminals are protected from breakage. |
| US09647514B2 |
Motor control unit having integrated inverter unit
A motor control unit is obtained by integrating an inverter unit and a motor unit having a motor, the inverter unit having a control board erected on a support board. |
| US09647512B2 |
Electric machine
The electric machine has a casing housing a stator and a rotor and containing a gas, and a dryer for the gas. The dryer is connected to the casing. The dryer includes a separation group, for separating humidity from the gas, a water accumulator, for at least temporally accumulating water discharged from the separation group, at least a detector for the water contained in the water accumulator. |
| US09647510B2 |
Cooling jacket and deflection unit for cooling jackets
A cooling jacket (14) for cooling an electric motor, in particular a stator (23), wherein a first spiral line (16) for transporting a coolant is formed at least partially on the cooling jacket (14). The aim of the invention is to provide a cooling system that is optimized in terms of mounting space and ensures axially equalized cooling. This aim is achieved in that a second spiral line (17) for transporting coolant is formed at least partially, and in that based on a common spiral axis R, both spiral lines (16, 17) form an axially integrated double spiral, wherein the first spiral line (16) is an inflow line and the second spiral line (17) is a return flow line. The invention further relates to a deflection unit (12) for the return into the second line (17), which substantially prevents the static pressure from dropping. |
| US09647507B2 |
Motor with one-way rotation
A motor with one-way rotation including: a stator having a stator core, an upper insulator joined to the upper portion of the stator core, and a lower insulator joined to the lower portion of the stator core; a rotor having a rotor housing which includes a disc part having a hollow portion formed at the center and a side wall part vertically formed along the outer circumference of the disc part in the upward direction, and a plurality of magnets attached to the inner face of the side wall part of the rotor housing, the disc part having a one-way bearing seating portion formed around the hollow portion; a rotary shaft penetrating through the central portions of the stator and the rotor; and a one-way bearing having an outer wheel joined to the one-way bearing seating portion and an inner wheel joined to the rotary shaft. |
| US09647505B2 |
Rotating electrical machine
A rotating electrical machine is configured such that, in a rotor coil, ventilation passages are formed in two lines arranged in a width direction of the rotor coil, and formed in the same shape at a plurality of positions spaced from each other in a longitudinal direction, 0.3≦W1/W2≦0.7 . . . (Expression 1) is satisfied, where (W1) is a width dimension of the ventilation passage in the longitudinal direction and (W2) is a width dimension from one end of the ventilation passage to one end of another ventilation passage adjacent thereto, and 0.025≦W4/W3≦0.08 . . . (Expression 2) is satisfied, where (W3) is a width dimension of the rotor coil and (W4) is a width dimension of the ventilation passage. |
| US09647504B2 |
Interphase insulator
Electrically insulating material so foldable as to form an interphase insulator so configured as to be inserted in the slots of the stator or the rotor of an electric machine to prevent separate coils inserted in the same slot to be in direct contact with one another and to prevent the coil heads of different coils to be in direct contact is described herein. The interphase insulator may be so folded that the coil heads are properly insulated from one another. |
| US09647502B2 |
Stator and rotating electric machine
A stator includes an annular stator core, a stator coil and a resin adhesive. The stator coil is comprised of a plurality of electric wires. The electric wires are partially received in slots of the stator core so that the stator coil has a pair of coil end parts protruding outside the slots respectively from opposite axial end faces of the stator core. The resin adhesive is filled in the slots of the stator core and/or applied to the coil end parts of the stator coil. Moreover, each of the electric wires includes an electric conductor and an insulating coat that covers an outer surface of the electric conductor. The insulating coat is two-layer structured to include an inner coat and an outer coat. The adhesion strength of the outer coat to the resin adhesive is lower than the adhesion strength of the inner coat to the resin adhesive. |
| US09647499B2 |
Electric machine
An electric machine, especially a transversal flux machine, the stator being composed of a stack of phase segments, each phase segment having at least one stator segment and one stator winding, especially a single winding, each stator segment having an annular stator bridge, on which pole shoes are premolded, which in particular extend radially inward, and/or which extend in the direction of the rotor and/or which are situated between the rotor and the annular stator bridge, the pole shoes having the same shape, in particular, the axial width of the pole shoe decreasing with increasing radial clearance, the associated profile being disposed between a first and a second profile, the first profile being a linear function of the radial clearance, the pole back associated with the first profile being a planar area, in particular, the second profile being a circular function, in particular a circular segment function, the pole back associated with the second profile being a cylindrical section area, in particular. |
| US09647497B2 |
Wireless power transmitter
Disclosed is a wireless power transmitter. The wireless power transmitter includes a coil in a first case; a first passage groove having a shape corresponding to a shape of the first case; and a second case coupled to the first case. |
| US09647491B2 |
UPS systems and methods using variable configuration
A system includes a plurality of module locations at which uninterruptible power supply (UPS) modules are installable and a control circuit configured to selectively support standby UPS and on-line UPS operation of modules installed at the plurality of module locations. The system may include a plurality of UPS modules installed in the plurality of module locations and including at least one UPS module configured to operate as a standby UPS. The plurality of UPS modules may further include at least one UPS module configured to operate as an on-line UPS. The UPS modules may share a common architecture including a submodule location at which a submodule is installable and circuitry configured to support operation of submodules with different functions in the submodule location. |
| US09647483B1 |
Closed magnetic wireless power transfer system
A wireless power transfer system includes a receive coil system nested within a transmit coil system forming a closed magnetic circuit. The transmit coil system includes a non-planar tapered transmit coil disposed within a tapered ferrite housing and a layer of insulating material surrounding the non-planar tapered transmit coil and the tapered ferrite housing. The receive coil system includes a ferrite plug comprising a column portion centrally secured to a plate portion, a non-planar receive coil wound around the column portion, a layer of insulating material surrounding the column portion and the non-planar receive coil, and a hemispherical covering surrounding the insulated column portion and non-planar receive coil. The non-planar receive coil has a smaller diameter than the non-planar tapered transmit coil. The maximum outside diameter of the hemispherical covering is less than or equal to the minimum inside diameter of the non-planar tapered transmit coil. |
| US09647481B2 |
Apparatus and methods for docking a dockee with a docking host utilizing a wireless charger in a wireless docking environment
Apparatus and methods are disclosed relating to the use and performance of a wireless charger, such as one that utilizes inductive coupling between a primary coil at the charger and a secondary coil at a mobile device that lands on the charger. In particular, the wireless charger is implemented in a wireless docking environment, where the mobile device docks with a docking host. In one example, the wireless charger is integrated as a unit with the wireless docking host. In another example, the wireless charger is a peripheral in the wireless docking environment managed by the docking host. |
| US09647478B2 |
Method and device for discharging an electrical network
A method, a device and an electrical system for discharging a first electrical network. The first electrical network comprises in particular an intermediate circuit which comprises in particular an intermediate-circuit capacitor. The first electrical network is connected to a second electrical network by means of a DC-DC converter for this purpose. The first electrical network is discharged by means of the DC-DC converter. At the same time, the DC-DC converter transfers electrical energy into the second electrical network. For discharging, the output voltage of the DC-DC converter is set to a first voltage value, which is larger than the nominal voltage of the second electrical network. For discharging, the output voltage of the DC-DC converter is set to the first voltage value for a predefinable first period of time. |
| US09647476B2 |
Integrated bias supply, reference and bias current circuits for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. |
| US09647469B2 |
Charge and discharge control circuit, charge and discharge control unit, and battery device
Provided is a highly safe battery device in which the accuracy of an overcurrent detection current value is high. A charge and discharge control circuit includes an overcurrent detecting terminal, an overcurrent detecting circuit for detecting overcurrent of a secondary battery, the overcurrent detecting circuit being connected to the overcurrent detecting terminal, and a constant current circuit for causing a current to flow to the overcurrent detecting terminal. |
| US09647468B2 |
Charge control device, charge control method, program, and system
A charge control device including: a charge control unit configured to select a power storage device to be charged from a plurality of power storage devices in accordance with degrees of subsequent deterioration of the power storage devices, the degrees being calculated based on battery information of the power storage devices each having a secondary battery; and a transmission unit configured to transmit a charge command to a power storage device selected by the charge control unit. |
| US09647467B2 |
System and method for balancing energy storage devices
A system for balancing a series connection of energy storage devices having: an intermediate storage element coupled between a pair of sections of one or a number of adjacent energy storage devices of a series connection of energy storage devices, sections each having a more positive terminal (A) at one end and a more negative terminal (B) at its other end; and a switching device for switching sequentially between coupling terminals (A) to each other via intermediate storage element and coupling terminals (B) to each other via intermediate storage element wherein the sections are non-adjacent. A method for balancing a series connection between energy storage devices is also disclosed. |
| US09647465B2 |
Charge and discharge control circuit and battery device
A short-circuit and overcurrent detecting circuit includes a reference voltage circuit including a constant current circuit, a first impedance element, a first transistor having a resistance value depending a voltage of a secondary battery, a second impedance element, and a second transistor having a resistance value depending the voltage of the secondary battery, which are connected in series. The reference voltage circuit outputs a first reference voltage from a node of the constant current circuit and the first impedance element, and outputs a second reference voltage from a node of the first transistor and the second impedance element. The short-circuit and overcurrent detecting circuit further includes: a first comparator circuit for comparing a voltage of an overcurrent detecting terminal with the first reference voltage; and a second comparator circuit for comparing the voltage of the overcurrent detecting terminal with the second reference voltage. |
| US09647464B2 |
Low noise power sources for portable electronic systems
Power supplies for electronic devices (e.g., portable ultrasound devices) are disclosed herein. In one embodiment, a stack of batteries and one or more switches between the batteries can change a voltage provided to a terminal that is connectable to a load. A charge pump comprising a number of capacitors are connected by switches. In one configuration, the switches are set so that each capacitor is charged from a common voltage source. In another mode, the switches are connected such that capacitors can be connected in series to provide a multiple of the charging voltage to the load. |
| US09647463B2 |
Cell balancing module and method in voltage balancing device for a stack of batteries which compares the cell voltages to a coded reference voltage derived from at least two reference voltages
The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In1, . . . , InN) for connecting a stack of energy storage cells (BAT1, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In1, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT1, . . . , VBATn) of the stack of energy storage cells (BAT1, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT1, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT1, . . . , VBATn). The invention also relates to a voltage balancing device and method for cell balancing, particularly for voltage balancing of a stack of batteries. |
| US09647457B2 |
Control device for damping grid oscillations
The invention relates to a method for damping grid oscillations. The oscillations may be damped by controlling e.g. wind turbine generators to inject power to the grid in anti-phase with the grid oscillations. Instead of controlling one or more wind turbine generators to generate the same anti-phase power signal, a plurality of wind turbine generators are controlled so that each of them only generates a part of the anti-phase power signal, but so that all of the wind turbine generators in combination generates the entire anti-phase power signal. |
| US09647454B2 |
Methods and apparatus for determining conditions of power lines
Techniques for determining conditions of power lines in a power distribution system based on measurements collected by a plurality of sensor units deployed in the power distribution system. Techniques include obtaining first transformed data associated with a first set of one or more measurements collected by a first sensor unit in the plurality of sensor units and second transformed data associated with a second set of one or more measurements collected by a second sensor unit in the plurality of sensor units, and determining, by using at least one processor and based at least in part on one or more features calculated from the first transformed data and the second transformed data, at least one condition of at least one power line in the power distribution system. |
| US09647452B2 |
Electrostatic discharge protection for level-shifter circuit
In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain. |
| US09647451B2 |
Discharge circuit
A discharge circuit includes a discharge switch trigger unit, a discharge switch unit and a discharge resistor unit. The discharge switch unit is coupled connected to the discharge switch trigger unit. The discharge resistor unit is coupled connected to the discharge switch unit. The discharge switch trigger unit and the discharge resistor unit are coupled connected to a voltage output side. When the output voltage of a power supply reaches a predetermined rated limitation, an over voltage protection circuit is activated, and the discharge switch unit is turned on by the discharge switch trigger unit, then the output voltage starts to decrease through the discharge resistor unit. |
| US09647450B2 |
Fault current limiter
This specification relates to fault current limiter (FCL). More particularly, to solve problems of protecting and designing current limiting impedance in a protective coordination system, as limitations of the related art, the fault current limiter may measure heat capacity of a current limiting impedance unit by detecting fault current flowing to the current limiting impedance unit and limiting the fault current flowing to the current limiting impedance unit according to the measured heat capacity, which may result in preventing the current limiting impedance unit from being damaged due to the fault current, preventing an extended accident due to the damaged current limiting impedance unit and enabling a stabilized system and line protection. |
| US09647448B2 |
System and method providing over current and over power protection for power converter
System and method for protecting a power converter. A system includes a threshold generator configured to generate a threshold signal, and a first comparator configured to receive the threshold signal and a first signal and to generate a comparison signal. The first signal is associated with an input current for a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and adjust the input current for the power converter. The threshold signal is associated with a threshold magnitude as a function of time. The threshold magnitude increases with time at a first slope during a first period, and the threshold magnitude increases with time at a second slope during a second period. The first slope and the second slope are different. |
| US09647442B2 |
Arc detection and prevention in a power generation system
A method for arc detection in a system including a photovoltaic panel and a load connectible to the photovoltaic panel with a DC power line. The method measures power delivered to the load thereby producing a first measurement result of the power delivered to the load. Power produced by the photovoltaic panel is also measured, thereby producing a second measurement result of power produced by the photovoltaic panel. The first measurement result is compared with the second measurement result thereby producing a differential power measurement result. Upon the differential power measurement result being more than a threshold value, an alarm condition may also be set. The second measurement result may be modulated and transmitted over the DC power line. |
| US09647441B2 |
Terminal box
Provided is a terminal box that allows easy insertion of a tab thereto, irrespectively of the position or direction of the tab extended from a solar cell module. A terminal box with a pair of tabs connected thereto for outputting electric power generated by a solar cell module, includes a case having an accommodating space therein and a pair of electrode plates disposed in the accommodating space. Each one of the pair of electrode plates has a terminal connecting portion to be connected with the tab and a cable connecting portion to which an output cable transmitting the electric power to an external device is connected. The case has tab inserting holes allowing insertion of the tabs into the accommodating space, the tab inserting holes being formed in an opposing face of the case opposing the electrode plates and at positions across the terminal connecting portion of at least one of the pair of electrode plates as the case is viewed perpendicularly above the opposing face. |
| US09647437B2 |
Re-enterable enclosure and configuration for mounting
A telecommunications enclosure (20) including a housing (22) with a dome (24) that connects to a base (26). The enclosure (20) includes an insert assembly (28) that fits within the housing (22) and the insert assembly (28) includes a sealing unit (30) that fits within the base (26) and defines a plurality of cable ports (32). The insert assembly (28) also includes a frame (34) attached to the sealing unit (30) and a telecommunications component (36) mounted to the frame (34). The enclosure (20) further includes a mounting bracket (38) for mounting the housing (22) at a desired mounting location. The mounting bracket (38) has a first securement interface (114) for attaching the mounting bracket (38) to the base (26) of the housing (22) and a second securement interface (122) for attaching the mounting bracket (38) to the insert assembly (28). |
| US09647433B2 |
Rail-less solar panel assembly and installation method
In various representative aspects, an assembly for securing array skirts and solar panel modules in an array on a roof by providing a leveling system that utilizes a barrel bolt and barrel nut to vertically adjust the assembly. Improved electrical bonding by utilizing bonding pins installed in mounting plates of a support clamp are also provided. Additionally, an improved array skirt design that is installed on the outer row of the array, as well as improved designs in the support clamp and splice mechanisms are also provided. Finally, an improved wire management system is included as well as a method of installation of the array assembly. |
| US09647428B2 |
Spark plug for internal combustion engine
A spark plug includes a tubular housing, a tubular insulator, a center electrode, a ground electrode, a resistor, and a stem. The insulator is supported inside the housing. The center electrode is supported inside the insulator so as a distal end portion thereof protrudes. The ground electrode forms a spark discharge gap G between the ground electrode and the center electrode. The resistor is supported inside the insulator at a proximal side of the central electrode. The stem is supported inside of the insulator at a proximal side of the resistor. Of an outer peripheral surface of the insulator, and closer to a distal end side than a proximal portion of the resistor is, there is formed a high emissivity surface of which thermal emissivity is at least 0.7 on at least a part of a portion facing an inner circumferential surface of the housing. |
| US09647426B1 |
Polarization insensitive colorless optical devices
Embodiments of the invention describe polarization insensitive optical devices utilizing polarization sensitive components. Light comprising at least one polarization state is received, and embodiments of the invention select a first optical path for light comprising a first polarization state or a second optical path for light comprising a second polarization state orthogonal to the first polarization state. The optical paths include components to at least amplify and/or modulate light comprising the first polarization state; the second optical path includes a polarization rotator to rotate light comprising the second polarization state to the first polarization state. Embodiments of the invention further describe optical devices including a polarization mode converter to convert light comprising a first and a second polarization state to light comprising different spatial modes of the first polarization state; light comprising the different spatial modes of the first polarization state is subsequently amplified and modulated. |
| US09647425B1 |
Method of manufacturing optical semiconductor device
A refractive index of the active layer is obtained by a photoluminescence inspection and an equivalent refractive index of the optical semiconductor element is computed. A refractive index of the optical waveguide layer is obtained by a photoluminescence inspection and an equivalent refractive index of the optical waveguide is computed. A film thickness of the refractive index adjustment layer is adjusted by etching the refractive index adjustment layer so that the equivalent refractive index of the optical semiconductor element and the equivalent refractive index of the optical waveguide are matched to each other. After adjusting the film thickness of the refractive index adjustment layer, a contact layer is formed on the second cladding layer and the refractive index adjustment layer. The optical waveguide is a passive waveguide to which no electrical field is applied and no current is injected. |
| US09647420B2 |
Package and methods for the fabrication and testing thereof
Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component. |
| US09647418B1 |
Laser generation using dual seeded nested and/or in-series Raman resonators, for telecommunications applications
A desired Nth-order Stokes output and zeroth-order Stokes pump input are seeded into a rare-earth doped amplifier where the power of the zeroth-order Stokes signal is amplified prior to both signals entering a Raman amplifier comprised of N−1 Raman resonators, each uniquely tuned to one of the N−1 Stokes orders, in various configurations to include one or more nested and/or in-series Raman resonators. The zeroth-order Stokes signal is converted to the Nth−1-order Stokes wavelength in steps and the power level of the Nth-order Stokes wavelength is amplified as the two signals propagate through the Raman resonators. Each Raman resonator includes a photosensitive Raman fiber located between a pair of Bragg gratings. The linewidths of the Stokes orders can be controlled by offsetting the reflectivity bandwidths of each pair of Bragg gratings respectively located in the Raman resonators. |
| US09647416B2 |
Bidirectional long cavity semiconductor laser for improved power and efficiency
The invention relates to bi-directional long-cavity semiconductor lasers for high power applications having two AR coated facets (2AR) to provide an un-folded cavity with enhanced output power. The lasers exhibit more uniform photon and carrier density distributions along the cavity than conventional uni-directional high-power lasers, enabling longer lasers with greater output power and lasing efficiency due to reduced longitudinal hole burning. Optical sources are further provided wherein radiation from both facets of several 2AR lasers that are disposed at vertically offset levels is combined into a single composite beam. |
| US09647414B2 |
Optically pumped micro-plasma
A laser and methods for providing a continuous wave output beam. The laser and method includes positioning a micro-plasma chip capable of creating micro-plasmas within a resonant cavity. A gas is input into the resonant cavity and flows around the micro-plasma chip. Micro-plasmas ignite and excite the gas to create metastables. The metastables are further excited by an optical pump having an energy sufficient to cause the metastables to lase. |
| US09647413B2 |
High-efficiency parallel-beam laser optical fibre drawing method and optical fibre
Provided are a high-efficiency parallel-beam laser optical fiber drawing method and optical fiber, the method including the steps of: S1: providing base planes on the side surfaces of both a gain optical fiber preform and a pump optical fiber preform, inwardly processing the base plane of the gain optical fiber preform to make a plurality of ribs protrude, and inwardly providing a plurality of grooves on the base plane of the pump optical fiber preform; S2: embedding the ribs into the grooves, tapering and fixing one end of the combination of the ribs and the grooves to form a parallel-beam laser optical fiber preform; S3: drawing the parallel-beam laser optical fiber preform into parallel-beam laser optical fibers. The process has high repeatability, and the obtained parallel-beam laser achieves peelability of pump optical fibers in a set area, thus facilitating multi-point pump light injection of parallel-beam laser optical fibers. |
| US09647407B1 |
Quasi-parametric chirped-pulse amplifier
Quasi-parametric chirped-pulse amplifier comprising a signal path, a pump path, and an amplifier. A dedicated nonlinear crystal doped with rare-earth-ions is used which has strong absorption around the idler waveband. Both the chirped signal pulse and the pump pulse incident into the amplifier, where energy continuously transfers from the pump pulse to the signal pulse and a newly generated idler pulse. The energy of the generated idler pulse is continually absorbed by the rare-earth ions doped in the amplifier. |
| US09647406B2 |
Laser unit and extreme ultraviolet light generating system
There is provided a laser unit that may include a master oscillator, a laser amplifier, and an adjuster. The master oscillator may be configured to output a laser light beam. The laser amplifier may be disposed in a light path of the laser light beam outputted from the master oscillator. The adjuster may be disposed in the light path of the laser light beam, and may be configured to adjust a beam cross-sectional shape of the laser light beam amplified by the laser amplifier to be a substantially circular shape. The beam cross-sectional shape may be at a beam waist of the laser light beam or in the vicinity of the beam waist of the laser light beam, and may be in a plane orthogonal to a light path axis. |
| US09647404B2 |
Brush holder apparatus and system
A brush holder apparatus includes a stationary support member having at least one groove, and a fork electrical connector. The stationary support member has a conductive bar configured to pass through a portion of the stationary support member's main body. The conductive bar is configured to provide electrical conductivity with a collector mount and the fork electrical connector. A brush retainment member is configured to be releasably affixed to the stationary support member. The brush retainment member has at least one rail configured to slide along the at least one groove, and a knife electrical connector configured to mate with the fork electrical connector. The stationary support member is configured for electrical connection to a collector mount and the brush retainment member is configured to retain at least one brush. |
| US09647392B2 |
RF connector
A connector for surface mounting to a circuit substrate is disclosed having an insulator, a center conductor mounted to the insulator; and a shielding shell externally mounted on the insulator. The shielding shell has a connecting portion and a mounting portion. The mounting portion has a connector mounting body with a shielding portion, a fluid communication well, and at least one opening. A plurality of solder legs are formed on the connector mounting body. |
| US09647389B2 |
Plug connector part comprising a locking element
A plug connector part for connecting to an associated mating plug connector part includes a housing. A plug-in portion is arranged on the housing and can be plugged into the associated mating plug connector part in a plugging direction to engage with the mating plug connector part when in a connection position. At least one electrical contact element is arranged on the plug-in portion. The at least one electrical contact element is for making electrical contact with the mating plug connector part. A locking element is movably arranged on the housing. The locking element has a locking position for locking the plug connector part with respect to the mating plug connector part when in the connected position. The locking element can be moved out of the locking position to unlock the connection between the plug connector part and the mating plug connector part. |
| US09647387B1 |
Electrical connector with grounding terminal
A connector includes a first contact module, a second contact module, a shielding shell and a latching member. The contact modules each include a number of contacts and an insulator retaining the contacts. The contact has a fastening portion assembled in the insulator, a contacting portion extending from the fastening portion, and a terminal portion extending from the fastening portion opposite to the contacting portion. The shielding shell covers around the first and the second contact modules. The latching member assists to secure the connection between the electrical connector with a complementary connector. The first contacts and the second contacts each have a pair of grounding terminals and the latching member connects with the pair of grounding terminals. |
| US09647379B2 |
Dust and debris tolerant dual poppet valve connector
A debris exclusion and removal apparatus for connectors which have a dual-poppet value configuration containing a pressurized substance. Coupling of the female and male connectors causes the poppet valve to eject a cleaning substance which will eliminate debris from the male connector prior to mating with the female connector. |
| US09647375B2 |
Power connector products with improved safety shutters
The present invention relates to a power connector for receiving an electric plug. The power connector is provided with a three-piece safety shutter architecture to prevent unwanted or improper insertion of a single plug pole into the power receptacles. In this architecture, the locking bar is formed with a first and a second tabs. The first and second tabs work with a protrusion formed therebetween to engage with the safety shutters and keep the safety shutters spaced apart from each other by a predetermined distance, so that the safety shutters are slidably latched in parallel by the locking bar and only allowed to travel dependently of each other along the travel direction, making the invention to meet the strict international safety standards for household plugs, adapters and socket-outlets. |
| US09647369B2 |
Electrical receptacle connector
An electrical receptacle connector includes a first insulated member and a second insulated member that are received in a metallic shell. A plurality of first receptacle terminals and a plurality of second receptacle terminals are respectively held in the first insulated member and the second insulated member. The first insulated member includes a tongue portion. The second insulated member includes a terminal positioning portion on the surface of the first insulated member. The surface of the terminal positioning portion and the surface of the tongue portion are at the same horizontal plane. A surface texture of the terminal positioning portion is different from a surface texture of the tongue portion. |
| US09647366B1 |
Connector shielding in an electronic device
Connector shielding devices are described herein. One connector shielding device includes a circuit board having a connector that is connectable with a connector of an additional circuit board. The shielding device further includes a plurality of spring fingers connected to and extending from a first surface of the circuit board or a base support adjacent to the first surface of the circuit board. The plurality of spring fingers provides a perimeter around the connector of the circuit board. Additionally, each spring finger of the plurality of spring fingers is configured to deflect toward the first surface of the circuit board when the connector of the circuit board connects with the connector of the additional circuit board. Further, a Faraday cage is provided by the circuit board, the additional circuit board, and the plurality of spring fingers when the connector and the additional connector are connected. |
| US09647364B2 |
Thin connector
A thin connector includes a first connector and a second connector both having a flat plate shape, the first connector includes first conductive layers disposed on a first insulating layer and superimposed on one another via an intermediate insulating layer, each first conductive layer has a spring contact array, among the first conductive layers, a first conductive layer closer to the first insulating layer has the spring contact array disposed more frontward in the fitting direction while a first conductive layer farther from the insulating layer has the spring contact array disposed more rearward in the fitting direction, the second connector includes a single second conductive layer disposed on a second insulating layer, the second conductive layer has projection arrays, among the projection arrays, a projection array disposed more frontward in the fitting direction are lower while a projection array disposed more rearward in the fitting direction are higher. |
| US09647360B2 |
Electrical receptacle connector
An electrical receptacle connector includes an insertion module, an adapting circuit board, and an adapting terminal module. The insertion module and the adapting terminal module are on the adapting circuit board. The insertion module includes first and second receptacle terminals, a grounding plate, and an insulated housing. The first and the second receptacle terminals are fixed on the insulated housing. First and second tail portions of the first and the second receptacle terminals are protruding from the insulated housing, respectively. The adapting circuit board includes first, second, and third soldering portions. The first, second, and third tail portions are soldered with the first, second, and third soldering portions, respectively. The third receptacle terminal includes a third tail portion and a fourth tail portion. The third tail portions are soldered with the third soldering portions, and the fourth tail portions are protruding from the adapting insulated member. |
| US09647358B2 |
Electrical plug connector
An electrical plug connector includes an insulated housing, a plurality of terminals, a metallic shell, and a positioning plate. The insulated housing includes a base portion, an upper portion, and a lower portion. The upper portion and the lower portion are extending from one side of the base portion. A mating room is between the upper portion and the lower portion. The terminals are held in the insulated housing. The metallic shell includes a tubular portion and a receiving cavity defined in the tubular portion. The insulated housing is received in the receiving cavity. The positioning plate is at the rear of the metallic shell to enclose the base portion. The positioning plate includes a first leg and a second leg respectively located at two sides of the base portion, so that the positioning plate can be assembled with a circuit board stably. |
| US09647356B2 |
Eye-of-needle compliant pin
A first connector includes a first plurality of eye-of-needle (EON) pins. Each EON pin of the first plurality includes two opposing spring arms. Each EON pin of the first plurality is configured to be received within a corresponding electrical via of a printed circuit board (PCB) such that the spring arms engage walls of the corresponding electrical via at a set of contact points. A second connector includes a second plurality of EON pins. Each EON pin of the second plurality includes two opposing spring arms. Each EON pin of the second plurality is configured to be received within a same corresponding electrical via of the PCB as a corresponding EON pin of the first plurality located at a same relative connector body location such that the spring arms engage the walls of the same corresponding electrical via at a different set of contact points. |
| US09647351B2 |
Temporary electrical grounding system having a magnetic component coupled to a conductive surface
An apparatus for providing a temporary electrical grounding connection is described. The apparatus comprises a cable electrically joining first and second conductive couplings, the first and second conductive couplings each electrically coupled to a conductive surface using a clamp, magnetic component, or other connection component. A conductive coupling may be connected to the magnetic component using a clamp connected to a stub extending from the magnetic component, and there may be multiple clamps or magnetic components used in different combinations or series to provide an electrical bypass between two or more conductive surfaces. |
| US09647347B2 |
Method and apparatus for channel bonding using multiple-beam antennas
A system is provided that enhances the throughput and reliability of wireless communications by providing multi-beam user terminals that exhibit directional discrimination. Multiple wireless communication channels are matched with multiple beams created from an array antenna by a beam-forming processor. The multiple wireless communication channels are bonded into a single virtual channel, thereby increasing data bandwidth while reducing interference and multi-path effects that can degrade communications. The beam-forming function may be performed in a dedicated beam-forming processor or may reside within a general-purpose microprocessor located in the user terminal. In addition, a wireless communications system with access points featuring multiple beams that exhibit directional discrimination that can concurrently support multiple users with multi-beam terminals via a common frequency channel. Both forward and return links feature multiple-folded frequency reuse, enabling multiple users with higher throughput and improved reliability. The spectrum utility of the communications system has been enhanced with multiple folds. |
| US09647344B2 |
Antenna with resonant cavity
The invention relates to an antenna comprising a resonant cavity deliminated by a partially reflecting surface comprising an array of resonant cells, each resonant cell forming a micro-antenna, a totally reflecting surface facing said partially reflecting surface, a radiating source disposed in said resonant cavity and configured so as to radiate a wave between the partially reflecting surface and the totally reflecting surface, said wave illuminating resonant cells of the partially reflecting surface, the partially reflecting surface being curved and resonant cells being individually configured to introduced upon the passage of the incident wave radiated by the source a phase shift dependent on the curvature of the partially reflecting surface at the level of the corresponding resonant cell. |
| US09647339B2 |
Wearable device
A wearable device includes a nonconductive base, a metal loop, and a matching circuit. The nonconductive base substantially has a hollow structure. The metal loop is disposed on the nonconductive base, and has a feeding point and a grounding point. The metal loop has at least one notch. The grounding point of the metal loop is coupled through the matching circuit to a ground voltage. An antenna structure of the wearable device is formed by the metal loop and the matching circuit. |
| US09647338B2 |
Coupled antenna structure and methods
Antenna apparatus and methods of use and tuning. In one exemplary embodiment, the solution of the present disclosure is particularly adapted for small form-factor, metal-encased applications that utilize satellite wireless links (e.g., GPS), and uses an electromagnetic (e.g., capacitive) feeding method that includes one or more separate feed elements that are not galvanically connected to a radiator element of the antenna. In addition, certain implementations of the antenna apparatus offer the capability to carry more than one operating band for the antenna. |
| US09647336B2 |
Reconfigurable radiating phase-shifting cell based on complementary slot and microstrip resonances
A radiating phase-shifting cell is designed to favour the excitation of an equivalent resonance of the “slot” type in a first part of the phase cycle, and to favour an equivalent resonance of the “microstrip” type in a second part of the phase cycle. This property notably allows the bandwidth of the phase-shifting cells to be optimized. A phase range of 360° can in effect be segmented into two sub-ranges of around 180°. This segmentation into two sub-ranges is made possible by the complementarity of the resonant modes of the slot or microstrip type. The radiating phase-shifting cell is notably applicable to reflector arrays for an antenna designed to be installed on a space craft such as a telecommunications satellite or on a terrestrial terminal for satellite telecommunications or broadcasting systems. |
| US09647334B2 |
Wide scan steerable antenna
A steerable antenna configuration having all actuators and the feed source mounted on a stationary side of the antenna thereby eliminating the need of having to supply power and/or communication signal through, a rotation mechanism. A first actuator rotates a reflector assembly about a first axis, and a second actuator rotates at least a main reflector of the reflector assembly about a second axis perpendicular to the first axis. The second axis is rotatable about the first axis via the first actuator. |
| US09647332B2 |
Electronic device antenna with interference mitigation circuitry
An electronic device may be provided with an antenna. The antenna may have an antenna resonating element and an antenna ground. The antenna resonating element may be formed from peripheral conductive housing structures. An audio jack or other connector may be mounted in an opening in the peripheral conductive housing structures. The audio jack may overlap the antenna ground. Contacts in the audio jack may be coupled to an interference mitigation circuit. The interference mitigation circuit may include capacitors coupled to the ground and inductors coupled between the contacts and the capacitors. Radio-frequency signal blocking inductors may be coupled between the interference mitigation circuit and respective ports in an audio circuit. |
| US09647328B2 |
Patch radiator
A patch radiator has a radiator surface designed as an annular and/or frame-shaped radiator surface, extending around a recess area. The radiator surface is extended so as to transition into the lateral surfaces or lateral walls. On the lateral surfaces or lateral walls, a lateral surface radiator structure electrically connected to the radiator surface is formed. In the peripheral direction of the lateral surfaces or lateral walls, there are lateral radiator surface sections, between which electrically non-conductive recess areas are provided. |
| US09647327B2 |
Multilayered film element
The invention relates to a multilayered film element (1) comprising a first component, more particularly an RFID antenna in the form of a multilayered film element, and to a method for fixing a second component on a film element (1) of this type. The film element (1) has a dielectric layer (10) having a front side (10V) and a rear side (10R). The film element (1) has a layer (11, 12) forming a first component, and at least one component contact area (23, 24) arranged on the front side (10V) and connected to the first component. The film element (1) has at least one thermode contact layer (30) which is arranged on the dielectric layer (10) and which, as seen perpendicularly to the dielectric layer (10), is arranged in the region of the at least one component contact area (23, 24). The thermode contact layer (30) has a thermode contact area (32) on a side facing away from the dielectric layer (10), said thermode contact area forming an outer surface of the film element (1). |
| US09647320B2 |
Antenna assembly and electronic device using the antenna assembly
An antenna assembly includes a first antenna, a second antenna, and a metal member. The second antenna is separate and spaced from the first antenna. A gap is defined on the metal member to divide the metal member into a first frame assembly and a second frame assembly. The first antenna is connected to the first frame assembly, the second antenna is connected to the second frame assembly, and the first antenna is electronically coupled to the second antenna. |
| US09647316B2 |
Transmission line and electronic component
A transmission line and an electronic component including a resonator using the transmission line are provided. The transmission line is capable of transmitting electromagnetic waves of at least one frequency ranging from 1 GHz to 10 GHz and is composed of a first dielectric with a first relative permittivity and a surrounding dielectric portion composed of a second dielectric with a second relative permittivity, wherein, the first dielectric is represented by a formula of {XBaO.(1−X)SrO}TiO2 (0.25 |
| US09647311B2 |
Wave dielectric transmission device, manufacturing method thereof, and in-millimeter wave dielectric transmission method
A millimeter wave transmission device, the millimeter wave transmission device having (a) a first signal processing board for processing a millimeter wave signal; (b) a second signal processing board signal-coupled to the first signal processing board to receive the millimeter wave signal and perform signal processing with respect to the millimeter wave signal; and (c) a viscoelastic member provided between the first signal processing board and the second signal processing board and having a predetermined relative dielectric constant and a predetermined dielectric dissipation factor. The member constitutes a dielectric transmission path via which the millimeter wave signal is transmitted between the first signal processing board and the signal processing board. |
| US09647307B2 |
Tunable filter and duplexer including filter
A filter includes a plurality of resonance cavities, where a resonance tube and a tuning bolt penetrating into space enclosed by the resonance tube are disposed in each resonance cavity; further includes a tuning part disposed between the tuning bolt and the resonance tube, where the tuning part and the resonance tube form a first capacitor, and the tuning part and the tuning bolt form a second capacitor; and further includes an adjusting structure used for rotating the tuning part, so as to change relative areas between the tuning part and the resonance tube and between the tuning part and the tuning bolt, so that the first capacitor and the second capacitor change synchronously. In the present invention, the tuning part is disposed between the tuning bolt and the resonance tube, so that the tuning part forms a double-capacitor structure with the resonance tube and the tuning bolt. |
| US09647301B2 |
Battery monitoring apparatus
A battery monitoring apparatus monitors a battery pack configured by a plurality of battery cells. The battery monitoring apparatus includes a main monitoring unit, a sub monitoring unit and a control unit. The main monitoring unit monitors a plurality of physical quantities indicating a battery state of the battery pack. The sub monitoring unit monitors a part of the physical quantities separately from the main monitoring unit. The control unit detects malfunction of the battery pack on the basis of at least one of a monitoring result of the main monitoring unit and a monitoring result of the sub monitoring unit. |
| US09647297B2 |
Production method for non-aqueous electrolyte secondary battery
According to the present invention, there is provided a seal step (ST105) storing an electrode laminate in which a separator is disposed between a positive electrode and a negative electrode and an electrolyte within an exterior body constituted by a laminate film and sealing the exterior body; a pressure application step (ST106) of applying a pressure to the exterior body in which the electrode laminate is stored by means of a flat plate press working or so forth; charge step (ST102) of charging up to a full charge; a gas removal step (ST107) of unsealing the exterior body and removing gas generated within the exterior body at the charge step; and a re-seal step (ST108) of sealing the exterior body after the gas removal step.The number of times of the gas removal steps is small and an influence of gas on battery characteristics is suppressed. |
| US09647290B2 |
Electrolyte for redox flow battery and redox flow battery
Provided is an electrolyte for a redox flow battery, the electrolyte allowing suppression of generation of precipitate during a battery reaction. In the electrolyte for a redox flow battery, the total concentration of impurity element ions contributing to generation of precipitate during a battery reaction is 220 mass ppm or less. In a case where the impurity element ions contributing to generation of precipitate include metal element ions, the total concentration of the metal element ions may be 195 mass ppm or less. In a case where the impurity element ions contributing to generation of precipitate include non-metal element ions, the total concentration of the non-metal element ions may be 21 mass ppm or less. |
| US09647289B1 |
Unit for glucose depletion
The present invention relates to treating of multiple pathological conditions through controlled lowering of glucose levels in blood. The present invention further relates to devices capable of lowering glucose levels in blood by exposing blood to enzyme-treated pole. |
| US09647288B2 |
Phosphoric acid-based electrolytes and applications thereof
A liquid electrolyte formed by reacting phosphoric acid (H3PO4) in the liquid state with silicon tetrachloride (SiCl4), thereby forming a fluid suspension. The fluid suspension is heated to yield a liquid electrolyte including phosphoric acid (H3PO4), pyrophosphoric acid (H4P2O7), and a particulate solid comprising a silicophosphoric acid, wherein the silicophosphoric acid is an acidic molecular compound including silicon and phosphorus. A concentrated silicophosphoric acid composition prepared by removing most of the liquid from the liquid electrolyte is dissolved in water to yield a homogeneous solution. The homogeneous solution is dried to yield a solid electrolyte. In some cases, the homogenous solution is dried on a substrate to coat at least a portion of the substrate with a proton conductive solid electrolyte. A fuel cell may include the liquid electrolyte, the solid electrolyte, or the coated substrate. |
| US09647287B2 |
Fuel cell system
The fuel cell system includes a hydro-desulfurizer that removes a sulfur compound in raw material gas; a raw material gas heating unit that heats raw material gas before the raw material gas enters the hydro-desulfurizer; a reformer that generates reformed gas using the raw material gas that has passed through the hydro-desulfurizer; a fuel cell that generates electric power using the reformed gas from the reformer as fuel; a combustor that combusts fuel unused in the fuel cell; an exhaust gas channel through which exhaust gas generated in the combustor flows; and a housing that is provided in a part of the exhaust gas channel and houses the raw material gas heating unit and the hydro-desulfurizer, in which exhaust gas flowing through the housing undergoes heat exchange with the raw material gas heating unit and the hydro-desulfurizer. |
| US09647283B2 |
Measurement device for measuring voltages along a linear array of voltage sources
A measurement device for measuring voltages along a linear array of voltage sources, such as a fuel cell stack, includes at least one movable contact or non-contact voltage probe that measures a voltage of an array element. |
| US09647278B2 |
Metal separator for fuel cells and manufacturing method thereof
To provide a metal separator for fuel cells that can equalize the wet environment of a membrane electrode assembly and a manufacturing method thereof. A metal separator for fuel cells and a manufacturing method thereof are characterized in that, a first separator (14) made of metal, which is layered in a membrane electrode assembly (12) to which a pair of electrodes is provided on both sides of a solid polymer electrolyte membrane (120), is formed into a corrugated sheet shape having convex parts and concaved parts, a noble metal thin film (147) is formed on a convex part (145) of the first separator (14), and holes (148) through which the first separator (14) is exposed are formed in the noble metal thin film (147). |
| US09647271B2 |
Batteries and related structures having fractal or self-complementary structures
An aspect of the subject technology/invention of the present disclosure includes electrode structures or elements/components that have (e.g., present) fractal and/or self-complementary shapes or structures, e.g., on a surface. Such shapes or structures can be pre-existing. The electrodes can be made of any suitable material. The electrodes may function or operate or be used as a “seed” structure to incorporate or receive a material or materials useful for lattice assisted nuclear reactions and/or cold fusion processes. |
| US09647270B2 |
Binder for lithium ion secondary battery electrode, production method for lithium ion secondary battery electrode, lithium ion secondary battery electrode, and lithium ion secondary battery
The present invention provides a binder for a lithium ion secondary battery electrode that has good adhesive properties and a low degree of swelling with respect to an electrolytic solution. There is used a binder for a lithium ion secondary battery electrode, which comprises a polyvinyl acetal-based resin (A) containing structural units represented by chemical formulae (1) to (3): (R1 is a hydrogen atom or an alkyl group having 1 to 10 carbon atoms), and (R2 is a functional group containing an ethylenically unsaturated bond). |
| US09647266B2 |
Amorphous titania/carbon composite electrode materials
An isolated salt comprising a compound of formula (H2X)(TiO(Y)2) or a hydrate thereof, wherein X is 1,4-diazabicyclo[2.2.2]octane (DABCO), and Y is oxalate anion (C2O4−2), when heated in an oxygen-containing atmosphere at a temperature in the range of at least about 275° C. to less than about 400° C., decomposes to form an amorphous titania/carbon composite material comprising about 40 to about 50 percent by weight titania and about 50 to about 60 percent by weight of a carbonaceous material coating the titania. Heating the composite material at a temperature of about 400 to 500° C. crystallizes the titania component to anatase. The titania materials of the invention are useful as components of the cathode or anode of a lithium or lithium ion electrochemical cell. |
| US09647265B2 |
All-solid state cell
An all-solid-state cell, which includes a lithium-containing anode, a cathode and a lithium ion-conducting solid-state electrolyte separator situated between the anode and the cathode. To improve the safety and cycle stability of the cell, the cathode includes a composite material including at least one lithium titanate and at least one lithium ion-conducting solid-state electrolyte. Furthermore, the invention relates to a corresponding all-solid-state battery and a mobile or stationary system equipped with it. |
| US09647263B2 |
Electroactive material
A composition for use in a lithium ion battery includes a plurality of elongate elements and a plurality of particles. The elongate elements and particles each include a metal or semi-metal selected from one or more of the group including silicon, tin, germanium, aluminum or mixtures thereof. The composition may include additional ingredients such as a binder, a conductive material and a further electro-active material, such as graphite. The compositions can be used for the fabrication of electrodes, preferably anodes in the manufacture of lithium ion batteries and optionally batteries based on magnesium ions or sodium ions. The composition is able to intercalate and release lithium during the charging and discharging cycles respectively of a battery into which it has been incorporated. Methods of fabricating the composition and electrodes including the composition are included as well as electrodes thus prepared and devices including such electrodes. |
| US09647262B2 |
Core-shell type anode active material for lithium secondary battery, method for preparing the same and lithium secondary battery comprising the same
The present invention relates to a core-shell type anode active material for a lithium secondary battery, a method of preparing the same, and a lithium secondary battery comprising the same. The anode active material for a lithium secondary battery according to the present invention comprises a carbon based material core portion; and a shell portion formed outside of the carbon based material core portion by coating the carbon based material core portion with a spinel-type lithium titanium oxide. The anode active material for a lithium secondary battery according to the present invention has the metal oxide shell portion, and thus has the improved conductivity, a high output density, and consequently excellent electrical characteristics. |
| US09647252B2 |
Nonaqueous electrolyte battery pack with gas-releasing portion for transferring heat
According to one embodiment, a nonaqueous electrolyte battery includes a case member, a negative electrode terminal, an electrode group, a negative electrode lead, a rupture member, and a gas releasing portion. The electrode group is provided in the case member, and includes positive and negative electrodes. The negative electrode lead electrically connects the negative electrode terminal to the negative electrode. The gas releasing portion is provided in the case member, is able to transfer a heat from the negative electrode lead and includes a zeolite-based porous material. |
| US09647249B2 |
Cooling system for vehicle batteries
The present disclosure relates to a cooling system for a vehicle battery, having: a cooling plate; an inlet manifold configured to supply fluid from a heat exchanger to the cooling plate; an outlet manifold configured to return fluid to the heat exchanger; and a plurality of micro-conduits formed in the cooling plate, configured to deliver fluid between the inlet manifold and outlet manifold. |
| US09647244B2 |
Integration equipment for replacing an evaporation material and use method for the same
An integration equipment for replacing an evaporation material and a use method thereof are provided. The integration equipment includes an evaporation chamber region, a material replacing chamber region, a valve door disposed between the evaporation chamber region and the material replacing chamber region, and for separating the above two regions, a substrate disposed inside the evaporation chamber region, and a material feeding door disposed at a side of the material replacing chamber region away from the valve door. Each of the evaporation chamber region and the material replacing chamber region includes a carrying platform, multiple evaporation sources disposed on the carrying platform, multiple exchanging devices for fixing and delivering the multiple evaporation sources, an independent vacuum-pumping device, and a heating device disposed inside the carrying platform. The equipment is capable of replacing and preheating an evaporation material without breaking vacuum of the evaporation chamber region to increase production efficiency. |
| US09647242B2 |
Heat-conductive sealing member and electroluminescent element
Provided is a heat-conductive sealing member which has high moisture barrier properties, has heat dissipation properties, and is capable of encapsulating an element by a simple method. The heat-conductive sealing member has a metal base material, an insulating layer that is formed on the metal base material, has heat conductivity and contains at least polyimide, and a tacky adhesive layer that is formed on the insulating layer and has heat resistance. |
| US09647238B2 |
Light-emitting device and electronic apparatus
A first light-emitting element and a second light-emitting element that have a resonance structure that causes output light from a light-emission functional layer to resonate between a reflective layer and a semi-transmissive reflective layer, and a pixel definition layer, and in which an aperture part is formed to correspond to each of the first light-emitting element and the second light-emitting element, are formed on a base. A first interval between the reflective layer and the semi-transmissive reflective layer in the first light-emitting element and a second interval between the reflective layer and the semi-transmissive reflective layer in the second light-emitting element are different, and a film thickness of the pixel definition layer is less than a difference between the first interval and the second interval. |
| US09647237B2 |
Thin film transistor substrate and display panel having the same
A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON). |
| US09647232B2 |
Organic electroluminescent device, illumination apparatus, and illumination system
An organic electroluminescent device includes a first electrode, an insulating layer, an organic light emitting layer, and a second electrode. The insulating layer is provided on the first electrode. The insulating layer includes a first opening for exposing a part of the first electrode. The organic light emitting layer includes a first part and a second part. The first part is provided on the part of the first electrode. The second part is provided on the insulating layer. The second electrode is provided on the organic light emitting layer. The second electrode includes a conductive part and a plurality of second openings. The conductive part is disposed on at least a part of the first part. Each of the second openings exposes a part of the organic light emitting layer. The second electrode is light-reflective. |
| US09647230B2 |
Display panel and display device
A display panel includes a first display surface, a second display surface, and a plurality of pixel units arranged in an array form between the two display surfaces. Each pixel unit includes an active light-emitting layer that emits light in a double-sided manner. A first light-emitting surface of the active light-emitting layer faces the first display surface, and a second light-emitting surface thereof faces the second display surface. The display panel further includes a first shielding layer that shields a portion of the first display surface and a second shielding layer that shields a portion of the second display surface. The first shielding layer includes a plurality of first shielding units, the second shielding layer includes a plurality of second shielding units, and the first shielding units and the second shielding units are arranged in a staggered manner in both a row direction and a column direction. |
| US09647229B2 |
Color filter for organic electroluminescence display device, and organic electroluminescence display device
When a large-screen organic EL display device is developed, the generation of a brightness unevenness is prevented between its screen central region and its screen outer circumferential region. Cost risk is decreased about the formation of a structure of preventing the generation of the brightness unevenness. Furthermore, an original protecting function for its organic EL elements is maintained. The color filter of the present invention comprises a transparent substrate, a colored layer that is a pixel region formed on the transparent substrate, and a non-pixel area formed around the colored layer, wherein a convex pillar is formed in at least one spot of the non-pixel area, and an auxiliary electrode layer on a top and a side of the convex pillar, and on the non-pixel area. |
| US09647225B2 |
Stacked organic light emitting device having high efficiency and high brightness
Disclosed is a stacked organic light emitting device and a display apparatus including the stacked organic light emitting device. The stacked organic light emitting device includes an anode connected to an external power source, a cathode connected to the external power source, at least two light emitting sections aligned between the anode and the cathode, including a light emitting layer, and an internal electrode aligned between the light emitting sections. The internal electrode is a single-layered internal electrode which is made from one selected from the group consisting of a metal, alloys of the metal, and metal oxides thereof, having a work function below 4.5 eV, each light emitting section includes an organic material layer containing an organic material having an electron affinity above 4 eV, and the organic material layer is formed between the light emitting layer of the light emitting section and the electrode facing the anode connected to the external power source in two electrodes which make contact with the light emitting section. |
| US09647222B2 |
Gate insulator layer for organic electronic devices
Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as gate insulator layers used in the fabrication of electronic devices, the electronic devices that encompass such polycycloolefin gate insulator and processes for preparing such polycycloolefin gate insulator layers and electronic devices encompassing such layers. |
| US09647221B2 |
Organic light-emitting devices
Organic electronic devices comprising a covalently bonded organic/inorganic composite layer. The composite layer may be formed by the reaction of a metal alkoxide with a charge transport compound having one or more hydroxyl groups. Examples of metal alkoxides that can be used include vanadium alkoxides, molybdenum alkoxides, titanium alkoxides, or silicon alkoxides. This composite layer can be used for any of the various charge conducting layers in an organic electronic device, including the hole injection layer. |
| US09647217B2 |
Organic electroluminescent materials and devices
The present invention relates to novel organic compounds comprising at least two different selections selected from the group consisting of N-phenyl carbazole, dibenzofuran, dibenzothiophene, triphenylene, aza-(N-phenyl carbazole), aza-dibenzofuran, aza-dibenzothiophene, and aza-triphenylene. The compounds are useful for organic light-emitting diodes. The compounds are also useful for charge-transport and charge-blocking layers, and as hosts in the light-emissive layer for organic light emitting devices (OLEDs). |
| US09647215B2 |
Organic electronic material
The present invention also relates to an organic electronic material with the structure of formula (I). It is a kind of hole transport and injection material with good thermal stability, high hole mobility and excellent solubility. The OLEDs prepared thereof have the advantages such as good light emitting efficiency, excellent color purity and long lifetime. |
| US09647208B2 |
Low voltage embedded memory having conductive oxide and electrode stacks
Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer. |
| US09647207B2 |
Resistive random access memory (RRAM) structure
A resistive random access memory (RRAM) cell with a high κ layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided. |
| US09647205B2 |
Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion
An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding. |
| US09647202B2 |
Magnetic random access memory with perpendicular enhancement layer
The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. |
| US09647199B2 |
Piezoelectric device and method for manufacturing piezoelectric device
In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film. |
| US09647196B2 |
Wafer-level package and method for production thereof
A hermetic wafer-level package composed of two piezoelectric wafers, preferably identical in terms of material, and a production method therefor are presented. The electrical and mechanical connection between the two wafers is accomplished with frame structures and pillars, the partial structures of which, distributed between two wafers, are wafer-bonded with the aid of connecting layers. |
| US09647192B2 |
Solar concentrator assembly and methods of using same
A solar concentrator assembly includes a tripod, a base, a reflective dish, a receptacle, and a thermoelectric module or a heat transfer module. The tripod includes legs and a top tripod connector coupled to top portions thereof. The base includes a rod coupled to the tripod; a bottom support structure coupled to the rod; a top support structure coupled to the bottom support structure; an extension coupled to the bottom support structure and the top support structure; and a cap with recesses mounted to the top support structure. The reflective dish includes support rods received within the recesses; a pliable material forms panels, wherein the support rods are inserted into seams between the panels; and a reflective material disposed on the pliable material. The receptacle is connected to the base and disposed within the reflective dish. The thermoelectric module or the heat transfer module is partially disposed within the receptacle. |
| US09647188B2 |
Wafer-level flip chip device packages and related methods
In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon. |
| US09647186B2 |
Method for producing an electronic component and electronic component
A method for producing an electronic component comprising barrier layers for the encapsulation of the component comprises, in particular, the following steps: providing a substrate with at least one functional layer, applying at least one first barrier layer on the functional layer via plasma enhanced atomic layer deposition (PEALD), and applying at least one second barrier layer on the functional layer by means of plasma-enhanced chemical vapor deposition (PECVD), where the at least one first barrier layer is applied at a temperature of less than 100° C. |
| US09647185B2 |
Composition for reflection film for light emitting element, light emitting element, and method of producing light emitting element
A light emitting element having a light emitting layer, an electro-conductive reflection film that reflects light emitted from the light emitting layer and a substrate in this order, wherein the electro-conductive reflection film contains metal nanoparticles. |
| US09647184B2 |
Light emitting device package and lighting apparatus including the same
A light emitting device package includes a package body, first and second lead frames located on the package body, a light source mounted on at least one of the first or second lead frames, a lens located on the package body, and a wavelength conversion unit partially located on the package body between the package body and the lens. |
| US09647183B2 |
Vertical light emitting diode with photonic nanostructures and method of fabrication thereof
There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer. There is also provided a vertical light emitting diode with the self-assembly derived ordered nanoparticles. |
| US09647182B2 |
Enhanced emission from plasmonic coupled emitters for solid state lighting
There is provided an illumination device (100) comprising an energy source (102) for exciting a photon emitter; a first wavelength conversion layer (104) and a second wavelength conversion layer (106). At least one of the first and second wavelength conversion layer comprises a periodic plasmonic antenna array comprising a plurality of individual antenna elements (108). The wavelength converting medium in the wavelength conversion layer in which the antenna array is arranged comprises photon emitters arranged in close proximity of the plasmonic antenna array such that at least a portion of photons emitted from the wavelength conversion layer are emitted by a coupled system comprising the photon emitter and the plasmonic antenna array. The plasmonic antenna array is configured to support plasmonic-photonic lattice resonances at a frequency range corresponding to the wavelength range of the photon emitter in the layer in which the plasmonic antenna array is arranged, such that light emitted from the plasmonic antenna array has an anisotropic angle distribution. |
| US09647177B2 |
Semiconductor optoelectronic device with an insulative protection layer and the manufacturing method thereof
The present disclosure is to provide an optoelectronic device. The optoelectronic device comprises a heat dispersion substrate; an insulative protection layer on the heat dispersion substrate, wherein the insulative protection layer comprises AlInGaN series material; and an optoelectronic unit comprising an epitaxial structure comprising multiple layers on the insulative protection layer, wherein at least one layer of the epitaxial structure comprises III-V group material devoid of nitride. |
| US09647175B2 |
Light emitting element and lighting device comprising same
The present disclosure provides a light emitting element, wherein each of first and second semiconductor layers has first and second pits disposed therein, wherein the first pit has a first depth and the second pit has a second depth smaller than the first depth, and the first and second pits are coupled to each other, wherein a density of the second pits in an upper portion of the second semiconductor layer is lower than a density of the second pits in an upper portion of the first semiconductor layer, wherein a density of the first pits in the upper portion of the second semiconductor layer is equal to a density of the first pits in the upper portion of the first semiconductor layer. |
| US09647173B2 |
Light emitting device (LED) having an electrode hole extending from a nonconductive semiconductor layer to a surface of a conductive semiconductor layer
A light-emitting device comprises a first conductive type semiconductor layer; a second conductive type semiconductor layer under the first conductive type semiconductor layer; an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a nonconductive semiconductor layer on the first conductive type semiconductor layer and including a light extraction structure formed in the nonconductive semiconductor layer; a recess disposed from the nonconductive semiconductor layer to an upper portion of the first conductive type semiconductor layer; a first electrode layer on the upper portion of the first conductive type semiconductor layer; a second electrode layer under the second conductive type semiconductor layer. |
| US09647171B2 |
Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems. |
| US09647169B2 |
Light emitting diode (LED) using carbon materials
Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. |
| US09647163B2 |
Solar cell having a double-sided structure, and method for manufacturing same
The present invention relates to a solar cell having nanostructures on both surfaces of a transparent substrate, and to a method for manufacturing same. The nano-structures, which face each other with respect to the substrate and which transport electrons, are formed using zinc-oxide nanowires. Also, a hole-transport layer using CIS nanoparticles is formed in order to absorb light having a short wavelength and to transport generated holes. A hole-transport layer including CIGS nanoparticles for absorbing light having a relatively long wavelength is formed on the side facing the hole-transport layer including the CIS nanoparticles. |
| US09647156B1 |
Heteroepitaxial growth of orientation-patterned materials on orientation-patterned foreign substrates
A layered OP material is provided that comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more. A method of forming the OPGaP is also provided. |
| US09647152B2 |
Sensor circuit and semiconductor device including sensor circuit
A sensor circuit includes a transistor comprising an oxide semiconductor; a first circuit which supplies one of a first potential and a second potential; a first switch; a second switch; and a second circuit to which a current flowing between a source and a drain of the transistor is applied via the second switch when the first potential is applied to a gate of the transistor. The first potential is lower than a potential of the source or a potential of the drain of the transistor, and the second potential is higher than the potential of the source or the potential of the drain of the transistor. The first switch electrically connects the source and the drain of the transistor when the second potential is applied to the gate of the transistor, and electrically isolates them when the first potential is applied to the gate of the transistor. |
| US09647149B2 |
Method and system for rapid and controlled elevation of a raisable floor for pools
A method for assembling a rapid elevation floor system in a pool, the method comprising the stages of: assembling a raisable floor inside said pool and adding sensors to said raisable floor, and connecting said raisable floor platform to auxiliary units. The method further comprises laying flooring tiles on said raisable floor and sinking said raisable floor to a bottom of said pool. |
| US09647148B2 |
Device for individual finger isolation in an optoelectronic device
An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact. |
| US09647146B2 |
Semiconductor device, manufacturing method, and electronic apparatus
A method of manufacturing a semiconductor device includes: forming, on a cover glass, a film having a predetermined specific gravity and configured to shield an alpha ray that arises from the cover glass; and bonding the cover glass on which the film is formed and an image pickup device, by filling a transparent resin between the cover glass and the image pickup device. |
| US09647143B2 |
Non-volatile memory unit and method for manufacturing the same
A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer. |
| US09647142B2 |
Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer. |
| US09647138B2 |
Metal oxide semiconductor transistor
A metal oxide semiconductor transistor includes a gate, a metal oxide active layer, a gate insulating layer, a source, and a drain. The metal oxide active layer has a first surface and a second surface, and the first surface faces to the gate. The gate insulating layer is disposed between the gate and the metal oxide active layer. The source and the drain are respectively connected to the metal oxide active layer. The second surface defines a mobility enhancing region between the source and the drain. An oxygen content of the metal oxide active layer in the mobility enhancing region is less than an oxygen content of the metal oxide active layer in the region outside the mobility enhancing region. The metal oxide semiconductor transistor has high carrier mobility. |
| US09647134B2 |
Thin-film transistor and method for manufacturing the same
According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film. |
| US09647132B2 |
Semiconductor device and memory device
A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN ( t ) = V 0 × ⅇ - ( t τ ) β ( 1 ) |
| US09647130B2 |
Display device
According to one embodiment, a display device includes a thin-film transistor. The thin-film transistor includes a gate electrode, an insulating layer disposed to superpose the gate electrode, and a semiconductor layer disposed on the insulating layer. The gate electrode is opposed to at least the semiconductor layer in part. The gate electrode includes a laminate including a first layer containing silicon as a main component and a second layer which contains titanium as a main component and which is in contact with the first layer, and is in contact with the insulating layer. |
| US09647124B2 |
Semiconductor devices with graphene nanoribbons
Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. |
| US09647118B2 |
Device having EPI film in substrate trench
The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation. |
| US09647115B1 |
Semiconductor structure with enhanced contact and method of manufacture the same
A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well. |
| US09647114B2 |
Methods of forming highly p-type doped germanium tin films and structures and devices including the films
Methods of forming p-type doped germanium-tin layers, systems for forming the p-type doped germanium-tin layers, and structures including the p-type doped germanium-tin layers are disclosed. The p-type doped germanium-tin layers include an n-type dopant, which allows relatively high levels of tin and/or p-type dopant to be included into the p-type doped germanium-tin layers. |
| US09647112B1 |
Fabrication of strained vertical P-type field effect transistors by bottom condensation
A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers. |
| US09647109B2 |
Semiconductor device
According to one embodiment, the fifth semiconductor region contacts the first semiconductor region. The metal region is provided on the fifth semiconductor region. The first insulating film extends in a thickness direction of the semiconductor layer. The first insulating film is adjacent to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first semiconductor region. The second insulating film extends in the thickness direction of the semiconductor layer. The second insulating film is provided between the fourth semiconductor region and the first conductive unit, between the third semiconductor region and the first conductive unit, and between the second semiconductor region and the first conductive unit. |
| US09647101B2 |
Silicene material layer and electronic device having the same
Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a 2-dimensional honeycomb structure formed as one of a monolayer and a double layer. The silicene material layer includes a doping region doped with at least one material from the group of Group 1, Group 2, Group 16 and Group 17 and at least one of a p-type dopant or an n-type dopant. |
| US09647095B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section. |
| US09647092B2 |
Method and structure of forming FinFET electrical fuse structure
An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness. |
| US09647088B2 |
Manufacturing method of low temperature polysilicon thin film transistor
The invention provides a manufacturing method of a low temperature polysilicon thin film transistor, including: providing a substrate; forming a buffer layer on the substrate; simultaneously forming a polysilicon layer and a photoresist layer on the buffer layer; implanting ions into a source region and a drain region; removing the photoresist layer; forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; and forming a passivation layer on the insulating layer. The passivation layer covers the gate electrode. The invention can only use one time of mask process and one time of ion implantation process to complete the manufacturing processing of the polysilicon layer, the manufacturing process can be simplified and therefore the cost of process is reduced and the productivity is improved. |
| US09647085B2 |
CMOS device with double-sided terminals and method of making the same
A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface. The source and drain terminals are connected to the respective source and drain regions. The transistor device further include a body terminal disposed on the second surface and configured to connect the highest or lowest voltage supply to the semiconductor substrate. |
| US09647082B2 |
Diodes with multiple junctions
A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface. |
| US09647080B2 |
Schottky device and method of manufacture
A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer. |
| US09647078B2 |
Closed cell configuration to increase channel density for sub-micron planar semiconductor power device
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate. |
| US09647073B2 |
Transistor structures and fabrication methods thereof
Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure. |
| US09647067B1 |
FinFET and fabrication method thereof
Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, an III-V group material, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer as a gate electrode. |
| US09647064B2 |
Semiconductor device and related electronic device
A semiconductor device may include the following elements: a first n-type region; a second n-type region; a p-type region, which directly contacts each of the first n-type region and the second n-type region; a first p-type portion, which directly contacts the first n-type region; a first n-type portion, which directly contacts each of the first n-type region and the p-type region; a first electrode, which is electrically connected to each of the first p-type portion and the first n-type portion; a second p-type portion, which directly contacts the second n-type region; a second n-type portion, which directly contacts each of the second n-type region and the p-type region; and a second electrode, which is electrically connected to each of the second p-type portion and the second n-type portion. |
| US09647061B2 |
Electronic device of vertical MOS type with termination trenches having variable depth
An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area. |
| US09647052B2 |
Flexible display substrate, flexible organic light emitting display device and method for manufacturing the same
A flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same are provided. The flexible display substrate comprises a flexible substrate including a display area and a non-display area extending from the display area, a first wire formed on the display area of the flexible substrate, and a second wire formed on the non-display area of the flexible substrate, wherein at least a part of the non-display area of the flexible substrate is curved in a bending direction, and the second wire formed on at least a part of the non-display area of the flexible substrate includes a first portion formed to extend in a first direction and a second portion formed to extend in a second direction. |
| US09647051B2 |
Organic light emitting diode display and repairing method thereof
An organic light emitting diode display includes an emission control connector between a driving transistor and an organic light emitting diode of a pixel. The emission control connector connects the driving transistor and the organic light emitting diode and overlaps a portion of a repair line. A first shorting assistance member overlaps the repair line and the emission control connector, and serves to induce a chain reaction to allow a short to form between the repair line and the emission control connector when a low-energy laser beam is applied. |
| US09647049B2 |
OLED pixel structure
The present invention provides an OLED pixel structure, comprising red, green, blue sub pixel areas, and the red, the green, the blue sub pixel areas respectively comprise a substrate, an anode formed on the substrate, a flat layer formed on the anode, an organic light emitting layer formed on the flat layer and a cathode formed on the organic light emitting layer, and an aperture area is formed on the flat layer, and the organic light emitting layer contacts the anode through the aperture area, and the anode comprises a positive electrode and a positive electrode compensation area coupled to the positive electrode, and the cathode, the positive electrode compensation area and a sandwiched layer between the cathode and the positive electrode compensation area constitute a compensation capacitor, and the compensation capacitor respectively makes total capacitance values of the red, green, blue sub pixel areas are equivalent to reach the capacitance value required by an drive circuit of the OLED element. |
| US09647048B2 |
Capacitor structures for display pixel threshold voltage compensation circuits
A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a thin-film drive transistor. Each display pixel may have thin-film transistors and capacitor structures that form a circuit for compensating the drive transistor for threshold voltage variations. The capacitor structures may be formed from interleaved stacked conductive plates. The conductive plates may be formed from layers of material that are used in forming the drive transistor and other thin-film transistors such as a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and interposed dielectric layers. |
| US09647047B2 |
Organic light emitting display for initializing pixels
A pixel includes an organic light emitting diode and a pixel control circuit. The pixel control circuit includes a first transistor, a second transistor, and a third transistor. The first transistor controls an amount of current to the organic light emitting diode from a first power source based on a voltage applied to a first node. The second transistor is coupled between the first node and a data line and turns on when a scan signal is supplied to a scan line. The third transistor is coupled between the first power source and a second node that is a common terminal of first and second capacitors, which are coupled in series between the first node and the first power source. In operation, the third transistor turns on when a first control signal is supplied to a first control line. |
| US09647046B2 |
Organic light emitting diode display having high aperture ratio and method for manufacturing the same
An organic light emitting diode (OLED) display includes a substrate in which an emission area and a non-emission area are defined, an OLED disposed in the emission area. The OLED display further includes a thin film transistor disposed in the non-emission area, a first insulation layer overlapping the thin film transistor in the non-emission area, a first storage capacitance electrode disposed in the emission area on the first insulation layer, a second insulation layer disposed to cover the first storage capacitance electrode and the thin film transistor except a portion of the thin film transistor, said portion of the thin film transistor being exposed through the second insulation later. The OLED display further includes an organic protective layer disposed on the second insulation layer, and an anode electrode of the OLED disposed on the second insulation layer, the anode electrode electrically connected to the thin film transistor. |
| US09647044B2 |
Organic light-emitting diode array substrate and manufacturing method thereof, and display device
Embodiments of the invention disclose an organic light-emitting diode array substrate and a manufacturing method thereof, and a display device. The array substrate comprises: a base substrate, a thin film transistor disposed above the base substrate, an organic light-emitting diode and a filling layer, the organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, wherein, in a light transmissive region of the organic light-emitting diode array substrate, the base substrate, the filling layer and the organic light-emitting layer of the organic light-emitting diode are disposed to be sequentially abutting. |
| US09647043B2 |
Display panel and electronic device
A display panel includes a flexible substrate, a first display region, a second display region, and a third display region. The first display region has a quadrangle outline and includes a first side and a second side forming a first corner portion of the outline. The second display region is in contact with the first side and the width of the second display region in a direction parallel to the first side coincides with the length of the first side. The third display region is in contact with the second side and the width of the third display region in a direction parallel to the second side coincides with the length of the second side. The substrate includes a notch portion corresponding a region facing the first display region with the first corner portion provided therebetween. |
| US09647037B2 |
Resistive random access memory device with resistance-based storage element and method of fabricating same
A method of fabrication of a device includes forming a first electrode and a second electrode. The method further includes forming a resistive material between the first electrode and the second electrode to form a resistance-based storage element of a resistive random access memory (RRAM) device. |
| US09647036B2 |
Resistive random-access memory with implanted and radiated channels
Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound. |
| US09647031B2 |
Memory device and manufacturing method thereof
A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate. |
| US09647029B2 |
Light-emitting device and manufacturing method of a display
In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip. |
| US09647028B2 |
Wafer on wafer stack method of forming and method of using the same
A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. |
| US09647026B2 |
Solid-state image pickup device, method of manufacturing the same, and electronic apparatus
A solid-state image pickup device, including: a plurality of pixels; a separation structure provided along a boundary line adjacent to the plurality of pixels; the separation structure includes a groove provided from a back surface of the semiconductor substrate to a depth corresponding to a wavelength, the groove being positioned along the boundary line, a first separation layer provided in the groove, and a second separation layer provided above the first separation layer and corresponding to the boundary line, the second separation layer being connected to the first separation layer; and methods including the same. |
| US09647022B2 |
Multi-layer structure for high aspect ratio etch
The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers. |
| US09647020B2 |
Light sensing circuit and control method thereof
A light sensing circuit for solving the problem of low reliability in illumination detection includes a photo transistor having a gate, a drain and a source; a first transistor electrically connecting between the gate and source of the photo transistor; a first capacitor electrically connecting between the gate and the drain of the photo transistor; a second transistor electrically connecting with the drain of the photo transistor, the first capacitor, and a data signal; a second capacitor electrically connecting between the source of the photo transistor and a ground contact; a third transistor electrically connecting with the photo transistor, the first transistor, and the second capacitor; and a switch adapted to alternatively connect the third transistor with a buffer or a zero signal. A control method of the above light sensing circuit is also disclosed. Therefore, the above identified problem can be surely solved. |
| US09647019B2 |
TFT and manufacturing method thereof, array substrate and manufacturing method thereof, X-ray detector and display device
A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3′), a semiconductor-layer thin film (4′) and a passivation-shielding-layer thin film (5′) successively; forming a pattern (5′) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a′); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c′) and a drain electrode (4b′). The source electrode (4c′) and the drain electrode (4b′) are disposed on two sides of the active layer (4a′) respectively and in a same layer as the active layer (4a′). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate. |
| US09647017B2 |
Curved image sensor and electronic device having the same
A curved image sensor includes a supporting substrate, a bonding pattern provided over the supporting substrate a sensing substrate provided over the supporting substrate and in contact with the bonding pattern, and having a curved surface receiving incident light, and a fixing pattern provided over the supporting substrate and surrounding a periphery of the sensing substrate. |
| US09647013B2 |
Manufacturing method of TFT array substrate
Embodiments of the invention provide a manufacturing method of a TFT array substrate. The TFT array substrate is formed to comprise a plurality of scanning lines, a plurality of data lines and a plurality of pixel units defined by intersecting these scanning lines and these data lines with each other. Each of the pixel units comprises a TFT and a pixel electrode. The TFT is formed to comprise a gate electrode, a gate insulating layer, a metal oxide semiconductor layer used as an active layer, an etch stopping layer formed on a portion of the surface of the metal oxide semiconductor layer, a source electrode and a drain electrode. In this method, the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by a same patterning process. |
| US09647009B1 |
TFT array substrate structure
A TFT array substrate structure includes a patterned metal light-shielding layer that includes a plurality of metal light-shielding blocks arranged in an array and a narrowed metal strip connected between two adjacent ones of the metal light-shielding blocks. The metal light-shielding layer and a common electrode are connected to and receive a common voltage signal. For each of TFT, the pixel electrode is connected to a drain electrode of the TFT; the pixel electrode has a portion overlapping the common electrode to form a first storage capacitor; and the metal light-shielding layer has a portion overlapping the drain electrode and the pixel electrode to form a second storage capacitor. The first storage capacitor and the second storage capacitor are connected in parallel to increase the capacity of the storage capacitor. The metal light-shielding layer is arranged in a light-shielded area and thus the modification thereof does not affect aperture ratio. |
| US09647007B2 |
Dual-gate array substrate, display panel and display device
A dual-gate array substrate, a display panel and a display device are provided. The dual-gate array substrate includes a plurality of pixel unit pairs arranged in an array, every pixel unit pair including a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit sharing a data line disposed there-between; a common electrode line disposed between every two adjacent pixel unit pairs in a row direction; a first strip structure disposed between the first pixel unit and the data line; a second strip structure disposed between the second pixel unit and the data line; and a first cross structure, a second cross structure and an intermediate cross structure electrically connecting the first strip structure to the second strip structure. The first cross structure and the second cross structure are disposed at two sides of the intermediate cross structure, respectively. |
| US09647006B2 |
Light shielding pattern pixel structure having a one side overlapping scan line
An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the insulation layer and electrically connected to a scan line, a protection layer covering the gate electrode, a source electrode and a drain electrode electrically connected to a source region and a drain region of the semiconductor layer. A channel region is disposed between the source region and the drain region. A source lightly doped region is disposed between the channel region and the source region. A drain lightly doped region is disposed between the channel region and the drain region. The light shielding pattern shields the source region, the drain region, the source lightly doped region and the drain lightly doped region. The light shielding pattern is overlapped with one side of the scan line and not overlapped with another side of the scan line. |
| US09647005B2 |
Display device and manufacturing method thereof
A display device includes: a gate electrode, a gate line, and data lines on a substrate, the data lines in a same layer as the gate line; a gate insulating layer on the gate line; a semiconductor member on the gate insulating layer; an etch stopper layer on the semiconductor member and the gate insulating layer; a first passivation layer on the etch stopper layer; a source electrode on the first passivation layer and the etch stopper layer and connected to the data lines; a drain electrode on the etch stopper layer; a common electrode on the first passivation layer and separated from the source electrode and the drain electrode; a second passivation layer on the source electrode, the drain electrode and the common electrode; and a pixel electrode on the second passivation layer and connected to the drain electrode. |
| US09647002B2 |
Array substrate, manufacture method thereof, and display device with the array substrate
An array substrate, a manufacture method thereof, and a display device with the array substrate are provided. The array substrate includes a substrate; a first gate scanning line; a first gate insulating layer; an active layer; a date scanning line; a pixel electrode formed in a pixel unit defined by the first gate scanning line and the data scanning line and over the data scanning line; and a second gate scanning line formed over or below the first gate scanning line. The second gate scanning line is substantially overlapped with the first gate scanning line in a stacking direction of the array substrate, and is arranged to be insulated from the first gate scanning line, the active layer, the data scanning line, and the pixel electrode, respectively. |
| US09647001B2 |
Array substrate, method for fabricating the same and display device
An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a metal shield layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer sequentially formed on the base substrate. At least one first via hole penetrating to the metal shield layer is formed in the interlayer dielectric layer and the gate insulation layer. The source-drain metal layer is formed in the at least one first via hole and on the interlayer dielectric layer having the at least one first via hole. |
| US09647000B2 |
Display device
A display device includes a first electrode, a first insulating layer having a first top surface and a first side wall, the first side wall having a closed shape and being exposed to a first opening reaching the first electrode, an oxide semiconductor layer on the first side wall, the oxide semiconductor layer including a first portion and a second portion, the first portion being connected with the first electrode, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer above the first top surface, the first transparent conductive layer being connected with the second portion, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer. |
| US09646998B2 |
Array substrate and manufacturing method thereof, as well as display device
This disclosure provides an array substrate and manufacturing method thereof, as well as a display device, the array substrate comprising: a substrate and a pattern comprising a source and a drain located on the substrate, further comprising: a tunnel junction structure located between the substrate and the pattern comprising the source and the drain, the tunnel junction structure forming an active layer of the array substrate and resulting in tunneling effect. The above array substrate and the manufacturing method thereof, as well as the display device have one or more beneficial effects as follows: a relatively high current carrier mobility, a higher switching speed of TFT; the threshold voltage of the TFT is not easily drifted, and has a relatively high uniformity; each pixel can use less TFTs, the switching speed of the pixel is higher; and the fabricating process is simpler and more practicable. |
| US09646997B2 |
Array substrate, method for manufacturing the same and display device
The present invention provides an array substrate. The active layer of the array substrate comprises at least two metal oxide semiconductor layers, wherein the at least two metal oxide semiconductor layers includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, the first metal oxide semiconductor layer is formed on a gate insulating layer, an etching barrier layer is formed on the second metal oxide semiconductor layer, and the mobility of the first metal oxide semiconductor layer is greater than the mobility of the second metal oxide semiconductor layer. |
| US09646996B2 |
Thin film transistor substrate and manufacturing method thereof
A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer. |
| US09646993B2 |
Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming
Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide. |
| US09646991B2 |
Semiconductor device with surrounding gate transistors in a NOR circuit
A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit. |
| US09646990B2 |
NAND memory strings and methods of fabrication thereof
Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed. |
| US09646983B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers. |
| US09646982B2 |
Semiconductor device and method of manufacturing the semiconductor device
According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern. |
| US09646976B2 |
Ferroelectric random-access memory with pre-patterned oxygen barrier
Structure of F-RAM cells are described. The F-RAM cell include a contact extending through a first dielectric layer on a surface of a substrate. A barrier structure is formed over the contact by depositing and patterning a barrier layer. A second dielectric layer is deposited over the patterned barrier layer and planarized to expose a top surface of the barrier structure. A ferro-stack is deposited and patterned over the barrier structure to form a ferroelectric capacitor. A bottom electrode of the ferroelectric capacitor is electrically coupled to the diffusion region of the MOS transistor through the barrier structure. The barrier layer is conductive so that a bottom electrode of the ferroelectric capacitor is electrically coupled to the contact through the barrier structure. In one embodiment, patterning barrier layer comprises concurrently forming a local interconnect (LI) on a top surface of the first dielectric layer. |
| US09646973B2 |
Dual-port SRAM cell structure with vertical devices
Dual-Port SRAM cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate transistors. Each transistor includes a first source/drain region in an active area, a channel extending above the active area, and a second source/drain region above the channel. First source/drain regions of pull-down transistors are electrically coupled through a first active area. First source/drain regions of pull-up transistors are electrically coupled through a second active area. A first, and a second, gate electrode is around channels of the first, and second, pull-down and pull-up transistors, respectively. Second source/drain regions of the first pull-down, first pull-up, and first and third pass-gate transistors are electrically coupled to the second gate electrode. Second source/drain regions of the second pull-down, second pull-up, and second and fourth pass-gate transistors are electrically coupled to the first gate electrode. |
| US09646971B2 |
Semiconductor devices including nanowire capacitors and fabricating methods thereof
Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film. |
| US09646970B2 |
Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. |
| US09646967B2 |
Semiconductor device
Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer. |
| US09646966B2 |
N-channel and P-channel end-to-end finFET cell architecture
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. |
| US09646964B2 |
Semiconductor device
The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer. |
| US09646963B1 |
Integrated circuits with capacitors and methods for producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer. |
| US09646962B1 |
Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET
A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer. |
| US09646959B2 |
Slim bezel and display having the same
A bezel of a display includes source lines with a same length, gate in panel (GIP) lines, and at least two customized integrated circuit (IC) chips arranged along a straight line in a lateral direction. Each of the customized IC chips is coupled to at least one of the source lines or the GIP lines. Circuit layouts on the customized IC chips are, together, equivalent to a circuit layout on a standard IC chip. A sum of widths of the customized IC chips in the lateral direction is greater than a width of the standard IC chip. |
| US09646958B2 |
Integrated circuits including dummy structures and methods of forming the same
An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures. |
| US09646957B2 |
LED packaging structure having stacked arrangement of protection element and LED chip
A light emitting diode (LED) packaging structure including a metal pad, an electric static discharge (ESD) protection element and an LED chip is provided. The metal pad has a first pad portion having a first top surface with a first concave configured thereon and a second pad portion having a second top surface with a second concave configured thereon. The ESD protection element has two first electrode portions respectively configured in the first concave and the second concave. The LED chip is located above the ESD protection element and has two second electrode portions respectively configured on the first top surface and the second top surface. A frame and a light emitting device having the frame that both include the above LED packaging structure are described herein. A light emitting device having an omni-directional light emitting effect is also described and includes the above LED packaging structure. |
| US09646955B2 |
Packages and methods of forming packages
Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). |
| US09646954B2 |
Integrated circuit with test circuit
An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer or printed circuit board forming a portion of the test circuit. |
| US09646952B2 |
Microelectronic package debug access ports
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact. |
| US09646951B2 |
Method of forming a semiconductor device and structure therefor
In one embodiment, a conductor bump is formed on an under bump conductor of a semiconductor device to extend a first distance away from a surface of the under bump conductor including forming a protective layer on an outer surface of the conductor bump wherein the plurality of semiconductor dies are subsequently singulated by etching through the semiconductor substrate with an etchant and wherein the protective layer protects the conductor bump from the etchant. |
| US09646949B2 |
Solderless mounting for semiconductor lasers
A first contact surface of a semiconductor laser chip can be formed to a first target surface roughness and a second contact surface of a carrier mounting can be formed to a second target surface roughness. A first bond preparation layer comprising a first metal can optionally be applied to the formed first contact surface, and a second bond preparation layer comprising a second metal can optionally be applied to the formed second contact surface. The first contact surface can be contacted with the second contact surface, and a solderless securing process can secure the semiconductor laser chip to the carrier mounting. Related systems, methods, articles of manufacture, and the like are also described. |
| US09646944B2 |
Alignment structures and methods of forming same
Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface. |
| US09646943B1 |
Connector structure and method of forming same
Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask. |
| US09646938B2 |
Integrated circuit with backside structures to reduce substrate warp
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit. |
| US09646937B2 |
Packaging structure for thin die and method for manufacturing the same
A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthening layer is disposed on the thin die; and the encapsulation body is formed on the substrate and covers both the thin die and the strengthening layer. The strengthening layer can bear pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing the packaging structure for the thin die is further provided to manufacture the above packaging structure for the thin die. |
| US09646935B1 |
Heat sink of a metallic shielding structure
A heat sink of a metallic shielding structure is provided in this disclosure, which includes a heating module and a cooling module. The heating module includes a heat generating component, a substrate, and a shield housing. The heat generating component is electrically connected to one side surface of the substrate and forms an opening corresponding the substrate. The cooling module includes a body and a working fluid is disposed in the body. |
| US09646934B2 |
Integrated circuits with overlay marks and methods of manufacturing the same
Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block. |
| US09646931B1 |
Formation of liner and metal conductor
In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer of a first metal having a first conductivity is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element. A portion of the non-reacted first metal is selectively removed. That portion of the first metal which has reacted to form the alloy liner on the patterned dielectric sidewall remains after the removal process. A second metal layer is deposited on the liner layer with a second metal on the liner and filling the conductive line trenches with the second metal layer. The second metal has a second conductivity higher than the first conductivity. A device fabricated by the method is another aspect of the invention. |
| US09646928B2 |
Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer. |
| US09646926B2 |
Wiring substrate and method of manufacturing the same
A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring interval wider than the first wiring interval, a metal plane layer formed on a portion of a first insulation layer formed on the first wiring layer, the first wiring part being located below the portion, a second insulation layer formed on the first insulation layer and the metal plane layer and having a first via hole and a second via hole, a second wiring layer formed on the second insulation layer and connected to the first wiring layer via a first via conductor formed in the first via hole, and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via a second via conductor formed in the second via hole. |
| US09646925B2 |
Interconnect array pattern with a 3:1 signal-to-ground ratio
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair. |
| US09646913B2 |
Thermal interface material on package
A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. |
| US09646912B2 |
Semiconductor device and semiconductor module having cooling fins
A semiconductor module having a plurality of cooling fins and a fixing cooling fin longer than the plurality of cooling fins, the fixing cooling fin having a threaded hole provided in distal end portion thereof, a cooling jacket having a cooling medium passage in which the plurality of cooling fins and the fixing cooling fin are housed, and an opening formed so as to enable a screw to be inserted in the threaded hole, and a screw passed through the opening to be inserted in the threaded hole, the cooling jacket being fixed to the semiconductor module with the screw are provided. |
| US09646908B2 |
Method for manufacturing semiconductor device and semiconductor device
In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching. |
| US09646907B2 |
Mold package and manufacturing method thereof
A mold package includes a substrate having a first surface and a second surface disposed opposite to the first surface, a wiring part disposed on the first surface in protruded manner, a molding resin, and a resin film. The molding resin partially seals the first surface of the substrate and the wiring part and intersects with the wiring part. The resin film is disposed between the first surface of the substrate and the end of the molding resin, and seals the wiring part and the first surface of the substrate adjacent to the wiring part. The resin film includes a first portion disposed inside the molding resin and a second portion disposed outside the molding resin. An upper surface of the second portion is lower than an upper surface of the first portion and has less uneven portions than the upper surface of the first portion. |
| US09646899B2 |
Interconnect assemblies with probed bond pads
An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. |
| US09646898B2 |
Methods for treating a substrate by optical projection of a correction pattern based on a detected spatial heat signature of the substrate
Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology. |
| US09646895B2 |
Semiconductor package and manufacturing method thereof
A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern. |
| US09646894B2 |
Packaging mechanisms for dies with different sizes of connectors
Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package. |
| US09646892B2 |
Transistor device and a method of manufacturing same
A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation. |
| US09646886B1 |
Tailored silicon layers for transistor multi-gate control
Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate. |
| US09646885B1 |
Method to prevent lateral epitaxial growth in semiconductor devices by performing plasma nitridation process on Fin ends
A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin ends. A plasma nitridation process is performed to the set of exposed fin ends. The plasma nitridation process forms a set of nitride layer covered fin ends. Dielectric material is deposited over the FinFET structure. The dielectric is etched to reveal sidewalls of the fins and the set of nitride layer covered fin ends. The nitride layer prevents epitaxial growth at the set of spacer covered fin ends. |
| US09646883B2 |
Chemoepitaxy etch trim using a self aligned hard mask for metal line to via
A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features. |
| US09646881B2 |
Hybrid subtractive etch/metal fill process for fabricating interconnects
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal. |
| US09646879B2 |
Depression filling method and processing apparatus
A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region. |
| US09646876B2 |
Aluminum nitride barrier layer
A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased. |
| US09646875B2 |
Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry. |
| US09646871B2 |
Semiconductor structure with shallow trench isolation and manufacturing method thereof
A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface. |
| US09646867B2 |
Plasma processing apparatus, power supply unit and mounting table system
A plasma processing apparatus includes a mounting table including a lower electrode and an electrostatic chuck, a high frequency power supply electrically connected to the lower electrode, a heater provided in the electrostatic chuck, a heater power supply for supplying a power to the heater, a filter unit including a filter connected to the heater power supply, a rod-shaped power feeder connecting the heater power supply and the heater via the filter, an insulating tubular portion having an inner hole through which the power feeder extends, and a conductive choke portion serving to suppress a microwave propagating through the tubular portion. The choke portion includes a first portion extending from the power feeder in a direction intersecting with a longitudinal direction of the power feeder and a cylindrical second portion extending, between the tubular portion and the power feeder, from a peripheral portion of the first portion. |
| US09646863B2 |
Multilayer styrenic resin sheet
Disclosed are a multilayer styrenic resin sheet including 10 to 50 laminated layers which are each made of a styrenic resin composition that includes 29 to 65 mass % of a styrene/conjugated diene copolymer (A), 51 to 15 mass % of a polystyrene resin (B) and 20 to 9 mass % of an impact-resistant polystyrene resin (C) and which each have an average thickness of 2 to 50 μm; and a packaging material (such as carrier tape or tray) for electronic components which is formed from the multilayer styrenic resin sheet. The melt tension of the styrenic resin composition at 220° C. is preferably 10 to 30 mN, and the content of the conjugated diene is preferably 10 to 25 mass % relative to 100 mass % of the copolymer (A). |
| US09646862B2 |
Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium
Heating within a plane of a substrate may be uniform while a thermal budget is decreased. A substrate processing apparatus includes a process chamber configured to accommodate a substrate; a substrate mounting unit installed in the process chamber and configured to have the substrate placed thereon; an electromagnetic wave supply unit configured to supply an electromagnetic wave to the substrate placed on the substrate mounting unit; and a choke groove formed on a side surface of the substrate mounting unit. |
| US09646859B2 |
Disk-brush cleaner module with fluid jet
Embodiments of the present invention relates to an apparatus and method for cleaning a substrate using a disk brush. One embodiment provides a substrate cleaner comprising a substrate chuck disposed in the processing volume, and a brush assembly disposed in the processing volume, wherein the brush assembly comprises a disk brush movably disposed opposing the substrate chuck, and a processing surface of the disk brush contacts a surface of the substrate on the substrate chuck. |
| US09646858B2 |
Semiconductor cleaner systems and methods
In an embodiment, the present invention discloses a EUV cleaner system and process for cleaning a EUV carrier. The euv cleaner system comprises separate dirty and cleaned environments, separate cleaning chambers for different components of the double container carrier, gripper arms for picking and placing different components using a same robot handler, gripper arms for holding different components at different locations, horizontal spin cleaning and drying for outer container, hot water and hot air (70 C) cleaning process, vertical nozzles and rasterizing megasonic nozzles for cleaning inner container with hot air nozzles for drying, separate vacuum decontamination chambers for outgassing different components, for example, one for inner and one for outer container with high vacuum (e.g., <10−6 Torr) with purge gas, heaters and RGA sensors inside the vacuum chamber, purge gas assembling station, and purge gas loading and unloading station. |
| US09646855B2 |
Semiconductor device with metal carrier and manufacturing method
Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer. |
| US09646853B1 |
IC device having patterned, non-conductive substrate
A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires. |
| US09646852B2 |
Manufacturing process for substrate structure having component-disposing area
A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic layer and a component-disposing area is provided. The metallic layer is disposed on the first surface and patterned to form a patterned metallic layer including pads located in the component-disposing area. A first dielectric layer is formed on the first surface and covers the patterned metallic layer. A laser-resistant metallic pattern is formed on the first dielectric layer and surrounds a projection area of the first dielectric layer. A release film is disposed on the projection area and covers a portion of the laser-resistant metallic pattern within the projection area. A second dielectric layer is formed on the first dielectric layer and covers the release film and the laser-resistant metallic pattern. A first open hole and a plurality of second open holes are formed. |
| US09646849B2 |
Semiconductor device with nano-gaps and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer. |
| US09646847B2 |
Method for manufacturing array substrate, film-etching monitoring method and device
A method for manufacturing an array substrate, a film-etching monitoring and a film-etching monitoring device. The monitoring method comprises: monitoring and recording the transmittance reference value of a film after a film pattern is formed; and monitoring the transmittance present value of the film in real time in the process of etching an overcoating layer to form a through hole after the overcoating layer is formed on the film pattern, and monitoring the etching degree of the film by determining the variation between the transmittance present value and the transmittance reference value. The device comprises a plurality of light sources (3) and a plurality of light-sensitive probes (4) disposed in the chamber. The light sources (3) are configured to irradiate the film on a substrate; and the light-sensitive probes (4) are configured to sense the transmittance of the film. |
| US09646845B2 |
Method of forming a mask for substrate patterning
Techniques herein include using acid-diffusion—controllable to specific diffusion lengths—to create sacrificial structures that, when removed, define a critical dimension (CD) of various features and contact openings. Removing such sacrificial structures defines a trench of a precisely controllable width. The surrounding material is then neutralized from additional solubility shifts using a ballistic electron treatment, thereby creating a first mask layer. A second mask layer formed on top of the first mask layer can be lithographically exposed and developed. The combined mask layers define a pattern for transfer into an underlying target layer. Accordingly, techniques disclosed herein enable patterning of features and contact openings having widths in a range from less than about 1 nanometer and up to around 50 nanometers or more. Techniques herein can also enable use of high-speed EUV (extreme ultraviolet) patterning. |
| US09646843B2 |
Tunable magnetic field to improve uniformity
Implementations described herein provide a magnetic ring which enables both lateral and azimuthal tuning of the plasma in a processing chamber. In one embodiment, the magnetic ring has a body. The body has a top surface and a bottom surface, and a plurality of magnets are disposed on the bottom surface of the body. |
| US09646828B2 |
Reacted particle deposition (RPD) method for forming a compound semi-conductor thin-film
A method is provided for fabricating a thin-film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor material. This pre-reaction typically includes processing above the liquidus temperature of the compound semiconductor. The compound semiconductor material is reduced to a particulate form and deposited onto a substrate to form a thin-film having a composition and atomic structure substantially the same as a composition and atomic structure of the compound semiconductor material. |
| US09646827B1 |
Method for smoothing surface of a substrate containing gallium and nitrogen
Disclosed is a method for processing GaN based substrate material for manufacturing light-emitting diodes, lasers, and other types of devices. In various embodiments, a GaN substrate is exposed to nitrogen and hydrogen at a high temperature. This process causes the surface of the GaN substrate to anneal and become smooth. Then other processes, such as growing epitaxial layers over the surface of GaN substrate, can be performed over the smooth surface of the GaN substrate. |
| US09646826B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film. |
| US09646825B2 |
Method for fabricating a composite structure to be separated by exfoliation
The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite structure, a treatment step modifying the optical properties in reflection at an interface between the support substrate and the separation layer or on an upper face of the support substrate. |
| US09646821B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes processing a substrate accommodated in a process container accommodated in a housing by supplying a process gas onto the substrate; and exhausting the process container using an exhaust system comprising a first exhaust pipe connected to the process container, the first exhaust pipe having circular or oval cross-section perpendicular to an exhausting direction thereof; and a second exhaust pipe connected to the first exhaust pipe, the second exhaust pipe having square or rectangular cross-section perpendicular to the exhausting direction, wherein at least a portion of the second exhaust pipe is disposed within the housing. |
| US09646819B2 |
Method for forming surface oxide layer on amorphous silicon
The invention provides a method for forming a surface oxide layer on an amorphous silicon including steps: using a HF acid to clean a surface of the amorphous silicon; using a water to clean the surface of the amorphous silicon being cleaned by the HF acid; drying the surface of the amorphous silicon after being cleaned by the water; using an extreme ultraviolet lithography to form a first oxide layer on the surface of the amorphous silicon after being dried; using an oxidizing solution to clean the surface of the amorphous silicon with the first oxide layer to thereby form a second oxide layer; and drying the surface of the amorphous silicon with the second oxide layer. By using the extreme ultraviolet lithography to form the first oxide layer, the surface of the amorphous silicon is given with strong hydrophilicity and therefore the distribution of water would be uniform. |
| US09646813B2 |
Mass spectrometer
A mass spectrometer is disclosed comprising a first quadrupole rod set mass filter, a collision cell, an ion mobility spectrometer or separator, an ion guide or collision cell arranged downstream of the ion mobility spectrometer or separator, a second quadrupole rod set mass filter and an ion detector. |
| US09646811B2 |
Miniaturized ion mobility spectrometer
By utilizing the combination of a unique electronic ion injection control circuit in conjunction with a particularly designed drift cell construction, the instantly disclosed ion mobility spectrometer achieves increased levels of sensitivity, while achieving significant reductions in size and weight. The instant IMS is of a much simpler and easy to manufacture design, rugged and hermetically sealed, capable of operation at high temperatures to at least 250° C., and is uniquely sensitive, particularly to explosive chemicals. |
| US09646808B2 |
Cold plasma annular array methods and apparatus
Methods and apparatus are described that use an array of two or more cold plasma jet ports oriented to converge at a treatment area. The use of an array permits greater tissue penetration by cold plasma treatments. This approach enables treatment of deeper infections of soft and hard tissues without surgical intervention. For example, this approach can treat sub-integumental infections, such as those common to joint replacements, without surgically opening the issues overlying the deeper infection. |
| US09646804B2 |
Method for calibration of a CD-SEM characterisation technique
A calibration method for a CD-SEM technique, includes determining a match function converting at least one parameter obtained by modelling a measurement supplied by the CD-SEM technique into a function of at least one parameter representative of a measurement supplied by a characterisation technique different from the CD-SEM technique, the match function being characterised by a plurality of coefficients; performing measurements on a plurality of patterns chosen to cover the desired validity range for the calibration, the measurements being done using both the CD-SEM technique to be calibrated and the reference technique; determining, from the measurements, a set of coefficients of the match function minimising the distance between the functions of the parameters measured using the reference technique and applying the match function to the parameters obtained by modelling measurements supplied by the CD-SEM; using the set of coefficients during the implementation of the calibrated CD-SEM technique. |
| US09646803B2 |
Transmission electron microscopy supports and methods of making
A method of making a Transmission Electron Microscopy support comprising depositing a sacrificial layer to the top side of a lacey or holey carbon structure or support or wire mesh, depositing an Atomic Layer Deposition layer to the bottom side of the sacrificial layer, removing the sacrificial layer, forming a Transmission Electron Microscopy support. The Transmission Electron Microscopy support comprises an Atomic Layer Deposition layer which is carbon-less, thin, flexible, can be thermally cleaned, can be plasma cleaned, and contains chemical functionalities to immobilize particles. |
| US09646801B2 |
Multilayer X-ray source target with high thermal conductivity
In various embodiments, a multi-layer X-ray source target is provided having two or more layers of target material at different depths and different thicknesses. In one such embodiment the X-ray generating layers increase in thickness in relationship to their depth relative to the electron beam facing surface of the source target, such that X-ray generating layer further from this surface are thick than X-ray generating layers closer to the electron beam facing surface. |
| US09646800B2 |
Traveling wave tube system and control method of traveling wave tube
A traveling wave tube system includes a traveling wave tube, and a power supply device for supplying required power supply voltages to the respective electrodes of the traveling wave tube. The power supply device includes a control voltage generation circuit for generating a control voltage which is a negative DC voltage on the basis of a ground potential and supplying the control voltage to the anode, an anode voltage generation circuit for generating an anode voltage which is a negative DC voltage on the basis of the potential of the anode and supplying the anode voltage to the cathode, and a collector voltage generation circuit for generating a collector voltage which is a positive DC voltage on the basis of the potential of the cathode and supplying the collector voltage to the collector. |
| US09646797B2 |
Ferroelectric emitter for electron beam emission and radiation generation
Disclosed are methods and devices suitable for generating electron beams and pulses of radiation. Specifically, in some disclosed embodiments, multiple emitting electrodes of a ferroelectric emitter are sequentially activated, generating a relatively long electron beam pulse that is substantially a series of substantially consecutive short electron beam pulses generated by the sequentially-activated individual emitting electrodes. |
| US09646793B2 |
Offset bus connection with field shaping and heat sink
Method and apparatus for reducing the minimum clearance needed between an electrical conductor and ground in switchgear and similar electrical isolation equipment provide a bus-connector having an extended toroidal shape that is designed to allow the size of the switchgear cabinet to be reduced while complying with industry-standard performance requirements. The toroidal shaped bus-connector has mostly or only smooth and rounded surfaces so there are no hard or sharp edges or corners from which electrical discharge from/to ground or other conductors may occur. The shaped bus-connector also has an elongated body that produces an offset connection resembling a “Z,” which allows power buses and breaker terminals that do not vertically line up to connect. |
| US09646792B2 |
Gap adjusting method in trip mechanism of molded case circuit breaker
Disclosed is a gap adjusting method which easily adjusts a gap between a bimetal and a crossbar by using a gap adjusting block and an adjusting screw in a trip mechanism of a molded case circuit breaker without a separate additional device. The gap adjusting method in the trip mechanism of the molded case circuit breaker includes setting a reference gap between a crossbar and a bimetal, measuring a total resistance of the trip mechanism and a trip stroke of a switching mechanism to set a compensation gap, placing a gap adjusting block on a position separated from a crossbar by a gap based on the sum of the reference gap and the compensation gap, rotating an adjusting screw assembled with the bimetal to contact the adjusting screw with the gap adjusting block, and adhering the adjusting screw to the bimetal. |
| US09646788B2 |
Electrical pyrotechnic switch
An electrical switch includes a first conductive terminal having a first contact portion, a second conductive terminal having a second contact portion, and a moveable body moveable from a first position, in which the first and second contact portions are electrically disconnected, to a second position, in which the first and second contact portions are electrically connected. The first and second contact surfaces are cylinders parallel to respectively the first and second contact portions, such that the second contact surface freely goes through the first contact portion, the first contact surface enters in connection with the first contact portion simultaneously to the moment when the second contact surface enters in connection with the second contact portion, and at least one of the first and second surfaces and the corresponding one of the first and second contact portions are arranged so that the moveable body is maintained in the second position. |
| US09646783B1 |
Encoder assembly for an appliance knob
A knob assembly is provided that includes a knob having a rotatable shaft, a rotatable first circuit board rigidly attached to the rotatable shaft, and a fixed second circuit board positioned near the first circuit board. The first circuit board includes an encoding portion configured to provide positioning data of the knob, and an eccentric rotating mass (ERM) motor mounted to the rotatable, first circuit board with a shaft of the ERM motor perpendicular to the rotatable shaft of the knob. The ERM motor is configured to produce and transfer vibration to the rotatable shaft of the knob. The second circuit board includes a sensor configured to determine a position of the first circuit board and thereby the knob at least in part from the positioning data provided by the encoding portion. |
| US09646774B2 |
Power wafer
A power wafer includes an enclosure that houses an energy plate such as a battery, capacitor, super-capacitor or other type of electrical energy storage device. A power wafer uses conductive infusions to make internal electrical connections. In some embodiments, the power wafer has an enclosure formed of a top structure and a bottom structure, which are configured to snap together. The bottom structure has an energy plate void and conductive infusion voids. In some embodiments, the infusions have carbon nanotubes that are magnetically aligned to increase the electrical and thermal conductivity of the infusions. In certain embodiments, the enclosure is configured to hold multiple energy plates in parallel and/or in series to increase the amperage and/or voltage of the power wafer. When the plates are stacked in parallel, an insulating barrier is placed between the plates. |
| US09646772B2 |
High voltage electrode for electric dual layer capacitor and method of manufacturing the same
A high voltage electrode includes a through type aluminum sheet, a plurality of first hollow protrusion members protruded to one side of the through type aluminum sheet, a plurality of second hollow protrusion members protruded to the other side of the through type aluminum sheet, a metal oxidation layer coated on the through type aluminum sheet, the plurality of first hollow protrusion members, and the plurality of second hollow protrusion members, a first active material sheet bonded to the metal oxidation layer so that it is placed in the first surface of the through type aluminum sheet, and a second active material sheet bonded to the metal oxidation layer so that it is placed in the second surface of the through type aluminum sheet. |
| US09646770B2 |
Multilayer ceramic capacitor and mounting board for multilayer ceramic capacitor
There is provided multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers laminated therein, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein, an upper cover layer formed on an upper portion of the active layer, a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer, first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer, and first and second external electrodes covering the both end surfaces of the ceramic body. |
| US09646769B2 |
Multilayer ceramic component and board having the same
A multilayer ceramic component including a multilayer ceramic capacitor including first and second external electrodes disposed on a mounting surface of a ceramic body; and first and second terminal electrodes each including an upper horizontal part disposed on a lower surface of the respective external electrode, a lower horizontal part disposed below the upper horizontal part and spaced apart from the upper horizontal part, and a connecting part connecting the upper horizontal part and the lower horizontal part, the connecting part having a plurality of openings alternately facing opposite end surfaces of the ceramic body. |
| US09646764B2 |
Rectangular wire edgewise-bending processing device and rectangular wire edgewise-bending processing method
Provided is a rectangular wire edgewise-bending processing device for performing an edgewise-bending process for a rectangular wire to form a coil, the rectangular wire edgewise-bending processing device including a fixing unit for fixing the rectangular wire, a pressing tool for pressing a surface formed by a long side of a rectangular cross section of the rectangular wire, and a bending tool for bending the rectangular wire into a predetermined coil shape, wherein the edgewise-bending process is performed while the surface formed by the long side of the rectangular cross section of the rectangular wire is pressed. |
| US09646763B2 |
Contactless power transfer system
A contactless inductively coupled power transfer system is provided including multiple pairs of power transmitter and power receiver coils and a power management module for controlling the supply of power to transmitter coils or the power supplied by the power receiver module to loads. The design is particularly suited for use in a wind turbine to supply power to the nacelle. The transmitter coils may be driven in phase at the same frequency or at different frequencies selected to avoid interaction between transmitter coils and the power transmitter module. The transmitter and receiver coils may be arranged in a traditional slip ring type configuration with adjacent coil pairs are physically spaced apart to avoid cross coupling with adjacent transmitter and receiver coil pairs shielded from each other. The power transmitter module may employ Zero Voltage Switching (ZVS). |
| US09646758B2 |
Method of fabricating integrated circuit (IC) devices
Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other. |
| US09646754B2 |
Linear solenoid
A linear solenoid has a coil assembly, a plunger, a stator core, and an elastic member. The coil assembly has a coil provided by a conducting wire. The plunger is disposed inside of the coil assembly and is movable in an axial direction. The stator core has a guiding portion guiding the plunger to move in the axial direction, an attracting portion attracting the plunger by generating a magnetic attractive force when the coil is energized, and a blocking portion blocking a magnetic field between the guiding portion and the attracting portion. The elastic member has an annular shape and is disposed between the blocking portion and the coil assembly. The elastic member is in contact with both an outer wall surface of the blocking portion and an inner wall surface of the coil assembly entirely in a circumferential direction of the elastic member. |
| US09646751B2 |
Arcuate magnet having polar-anisotropic orientation, and method and molding die for producing it
A die apparatus for molding an arcuate magnet having polar-anisotropic orientation in a magnetic field, which comprises a die made of non-magnetic cemented carbide, which is arranged in a parallel magnetic field generated by a pair of opposing magnetic field coils; an arcuate-cross-sectional cavity having an inner arcuate wall, an outer arcuate wall and two side walls, which is disposed in the die; a central ferromagnetic body arranged on the side of the outer arcuate wall of the cavity; and a pair of side ferromagnetic bodies symmetrically arranged on both side wall sides of the cavity; the cavity being arranged such that its radial direction at a circumferential center thereof is identical with the direction of the parallel magnetic field; the width of the central ferromagnetic body being smaller than the width of the cavity in a direction perpendicular to the parallel magnetic field; and a pair of the side ferromagnetic bodies being arranged such that the cavity is positioned in a region sandwiched by a pair of the side ferromagnetic bodies. |
| US09646748B2 |
Resistive voltage divider made of a resistive film material on an insulating substrate
A resistive voltage divider includes first and second resistors, which are electrically connected in series and are made of a resistive film material which is applied in the form of a trace onto an insulating substrate. The divider's voltage ratio has a value between ten and one million. To improve the accuracy of the voltage divider, the first and second resistors are made of the same resistive film material, have a trace length above a corresponding specific trace length, and have approximately the same trace width. |
| US09646745B2 |
Thermistor assembly including elastomeric body
A thermistor assembly according to an exemplary aspect of the present disclosure includes, among other things, an elastomeric body, a thermistor housed at least partially inside the elastomeric body and a thermistor tip that protrudes outside of the elastomeric body. |
| US09646741B2 |
Nested shielded ribbon cables
The disclosure generally relates to nested shielded ribbon cables that form an electrical cable assembly. The electrical cable assembly includes features that can facilitate bending and movement of the cable. |
| US09646739B2 |
Method for producing silver-plated product
There is provided a silver-plated product which has a good bendability and which can restrain the rise of the contact resistance thereof even if it is used in a high-temperature environment, and a method for producing the same. In a silver-plated product wherein a surface layer of silver is formed on the surface of a base material of copper or a copper alloy, or on the surface of an underlying layer of copper or a copper alloy formed on the base material, the percentage of an X-ray diffraction intensity on {200} plane of the surface layer with respect to the sum of X-ray diffraction intensities on {111}, {200}, {220} and {311} planes of the surface layer is 40% or more. |
| US09646732B2 |
High speed X-ray microscope
A high resolution x-ray microscope with a high flux x-ray source that allows high speed metrology or inspection of objects such as integrated circuits (ICs), printed circuit boards (PCBs), and other IC packaging technologies. The object to be investigated is illuminated by collimated, high-flux x-rays from a movable, extended source having a designated x-ray spectrum. The system also comprises a means to control the relative positions of the x-ray source and the object; a scintillator that absorbs x-rays and emits visible photons positioned in very close proximity to (or in contact with) the object; an optical imaging system that forms a highly magnified, high-resolution image of the photons emitted by the scintillator; and a detector such as a CCD array to convert the image to electronic signals. |
| US09646729B2 |
Laser sintering systems and methods for remote manufacture of high density pellets containing highly radioactive elements
The invention relates to remotely operated laser sintering systems and methods for manufacturing pellets containing highly radioactive elements. The highly radioactive elements can be recovered from used nuclear fuels. The systems and methods of the invention employ a feed composition including one or more highly radioactive elements and a ceramic matrix material. The feed composition is distributed in the form of a layer and sintered by directing at least one laser beam to form a pattern in the layer of the feed composition. The pattern corresponds to the shape of the pellet. Further, the sintering process can be repeated as necessary to achieve a pre-determined pellet height. |
| US09646727B2 |
System and apparatus for visual inspection of a nuclear vessel
Embodiments provide a system and apparatus for visual inspection of a nuclear vessel. The system includes a submersible remotely operated vehicle (SROV) system that is movable to an area within a nuclear vessel. The SROV system includes a maneuverable inspection camera assembly for visual inspection of nuclear vessel components, where the inspection camera assembly is maneuverable in relation to the SROV system. The system also includes a control system located in an area remote from the area within the nuclear vessel. The control system is configured to control the movement of the SROV system and the maneuvering of the inspection camera assembly. |
| US09646723B2 |
Thermoacoustic enhancements for nuclear fuel rods and other high temperature applications
A nuclear thermoacoustic device includes a housing defining an interior chamber and a portion of nuclear fuel disposed in the interior chamber. A stack is disposed in the interior chamber and has a hot end and a cold end. The stack is spaced from the portion of nuclear fuel with the hot end directed toward the portion of nuclear fuel. The stack and portion of nuclear fuel are positioned such that an acoustic standing wave is produced in the interior chamber. A frequency of the acoustic standing wave depends on a temperature in the interior chamber. |
| US09646722B2 |
Method and apparatus for a fret resistant fuel rod for a light water reactor (LWR) nuclear fuel bundle
A method and apparatus for a fret resistant fuel rod for a Boiling Water Reactor (BWR) nuclear fuel bundle. An applied material entrained with fret resistant particles is melted or otherwise fused to a melted, thin layer of the fuel rod cladding. The applied material is made of a material that is chemically compatible with the fuel rod cladding, allowing the fret resistant particles to be captured in the thin layer of re-solidified cladding material to produce an effective and resilient fret resistant layer on an outer layer of the cladding. |
| US09646720B2 |
Self-repair logic for stacked memory architecture
Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. |
| US09646718B2 |
Semiconductor memory device having selective ECC function
A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device. |