最新美国发明专利第2017-04-18期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09627686B2	Method for manufacturing lithium-containing composite oxide To simply manufacture a lithium-containing oxide at lower manufacturing cost. A method for manufacturing a lithium-containing composite oxide expressed by a general formula LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)). A solution containing Li and P is formed and then is dripped in a solution containing M (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) to form a mixed solution. By a hydrothermal method using the mixed solution, a single crystal particle of a lithium-containing composite oxide expressed by the general formula LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) is manufactured.
US09627685B2	Method for preparing lithium iron phosphate nanopowder The present invention relates to a method for preparing a lithium iron phosphate nanopowder, including the steps of (a) preparing a mixture solution by adding a lithium precursor, an iron precursor and a phosphorus precursor in a reaction solvent, and (b) putting the mixture solution into a reactor and heating to prepare the lithium iron phosphate nanopowder under pressure conditions of 10 to 100 bar, and a lithium iron phosphate nanopowder prepared by the method. When compared to a common hydrothermal synthesis method and a supercritical hydrothermal synthesis method, a reaction may be performed under a relatively lower pressure. When compared to a common glycothermal synthesis method, a lithium iron phosphate nanopowder having effectively controlled particle size and particle size distribution may be easily prepared.
US09627684B2	High capacity, dimensionally stable anode from low-bulk density amorphous silicon for lithium-ion batteries An anode active material for a lithium-ion battery cell comprises low density silicon. The anode active material is provided in an anode for a lithium-ion battery. Also disclosed are methods of making the anode active material.
US09627681B2	Silicon-based composite and production method thereof The present invention relates to a silicon-based composite including a silicon oxide which is coated thereon with carbon and bonded therein to lithium. The present invention also relates to a method of producing a silicon-based composite, comprising coating a surface of silicon oxide with carbon, mixing the silicon oxide coated with carbon with lithium oxide, and heat-treating a mixture of the silicon oxide coated with carbon and the lithium oxide in an inert atmosphere.
US09627674B2	Battery module A battery module includes a plurality of battery cells, each including terminal portions on a first surface thereof, the plurality of battery cells being aligned in a first direction; and a terminal connecting member configured to connect terminal portions of first and second battery cells of the plurality of battery cells that are adjacent to each other, and the terminal connecting member includes first and second contact portions spaced apart from each other to respectively come in surface contact with the terminal portions of the first and second battery cells, and a body portion connecting the first and second contact portions to each other.
US09627670B2	Battery cell and method for making battery cell Embodiments provide a battery cell including a porous membrane, the porous membrane including transformed semiconductor material. The porous membrane separates a first half-cell from a second half-cell of the battery cell. The porous membrane comprises channels allowing ions and/or an electrolyte to move between the first half-cell and the second half-cell.
US09627667B2	Lid including rib adjacent safety valve for a battery case In a lid for a battery case where an annular thin portion is formed integrally with a lid main body by coining, a pair of ribs formed integrally with the lid main body so as to bulge from the lid main body and extending in a short direction of the lid main body are disposed on both sides of the annular thin portion in a long direction of the lid main body.
US09627665B1	Battery module and manufacturing method thereof A manufacturing method of a battery module is firstly to produce two integrated electrodes. An electrode plate has a plurality of electrode openings, and two electrode side plates have individual side-plate screw contact openings. The side walls of the two electrode side plates have individually inner-wall surfaces facing to each other. Two screw members are then bonded to the inner-wall surfaces of the two electrode plates. Two holder frames cover the electrode plate and the two screw members to form an integrated holder frame. Two holder frame side openings of the two holder frames are located respective to the side openings. A plurality of battery cells, each of which has a first and a second electrode, is combined to the two integration-battery-holder frames. The second electrode electrically connect one of the integrated electrodes, and a plurality of wires connects the first electrode to a plate bonding portion, such that a battery module can be produced.
US09627664B2	Battery module of excellent structural stability Disclosed is a battery module including a base plate on which unit modules, each with two or more secondary batteries therein, are stacked in a vertically erected state, a pair of end plates disposed in tight contact with outer surfaces of outermost unit modules while bottoms of the end plates are fixed to the base plate, and supporting bars connected between opposite sides of upper or side parts of the end plates so as to support the end plates, wherein each of the end plates includes a main body contacting a corresponding one of the unit modules, and a top wall, a bottom wall, and a pair of side walls protruding outward from the perimeter of the main body, the thickness of each of the side walls being increased from the top to the bottom wall, thereby dispersing pressure (bending load) from the unit modules and the supporting bars.
US09627662B2	Secondary battery A secondary battery includes an electrode assembly, a case that accommodates the electrode assembly, a cap plate that seals the case, an electrode terminal assembled to penetrate through the cap plate, and a short-circuit inducing member that is fixed to a top surface of the cap plate, the short-circuit inducing member being displaceable according to a deformation of the cap plate to induce a short-circuit by contact with the electrode terminal.
US09627654B2	Organic light emitting diode device An OLED display includes a first substrate, a first electrode on the first substrate, a pixel defining layer having a first aperture exposing the first electrode, an organic light emitting layer on the first electrode, a second electrode on the organic light emitting layer, a second substrate disposed to face the first substrate, a black matrix disposed on the second substrate and having a second aperture, and a lens disposed to cover at least a part of the second aperture and protruding toward the first substrate.
US09627653B2	Organic electroluminescence element and planar light-emitting body each having light extraction sheet Provided is an organic EL element having both excellent light extraction efficiency and excellent weather resistance. The organic EL element (10) has a configuration comprising: an organic EL element main body (1) including an organic compound layer (13) including a light-emitting layer; and a light extraction sheet (2) provided on the light-extraction side of the organic EL element main body (1). In addition, the organic EL element (10) is characterized by: the light extraction sheet (2) including a silicon compound; the haze value of the light extraction sheet (2) being at least 90; and the total light transmittance of the light extraction sheet (2) being at least 80%.
US09627650B2	Multiple light-emitting element device each with varying wavelength To provide a novel light-emitting device, a light-emitting device that emits light of a plurality of colors includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first lower electrode, a first light-emitting layer over the first lower electrode, a second light-emitting layer over the first light-emitting layer, and an upper electrode over the second light-emitting layer. The second light-emitting element includes a second lower electrode, the first light-emitting layer over the second lower electrode, the second light-emitting layer over the first light-emitting layer, and the upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer. A distance between the first lower electrode and the first light-emitting layer is shorter than a distance between the second lower electrode and the first light-emitting layer.
US09627649B2	Organic light emitting display device Discussed is an organic light emitting display device. An OLED including a transparent anode formed of one conductive transparent material and an organic light emitting diode (OLED) including a cavity anode formed of a plurality of conductive materials are provided in one panel.
US09627645B2	Mask plate, organic light-emitting diode (OLED) transparent display panel and manufacturing method thereof A mask plate for manufacturing an organic light-emitting diode (OLED) transparent display panel, the OLED transparent display panel and a manufacturing method thereof are disclosed. The mask plate includes a substrate and a plurality of hollowed-out areas and a plurality of opaque areas disposed on the substrate, and a pattern of the hollowed-out areas correspond to a pattern of a cathode of the OLED transparent display panel to be manufactured; and all the hollowed-out areas are communicated with each other.
US09627644B2	Organic light emitting diode device In an aspect, an organic light emitting diode device including a first electrode, a second electrode facing the first electrode, and an emission layer positioned between the first electrode and second electrode, wherein the first electrode includes samarium (Sm) is provided.
US09627631B2	Organic electroluminescent materials and devices Boron-nitrogen polyaromatic compounds having a fused aromatic ring system are provided, where the compounds include a [1,2]azaborino[1,2-a][1,2]azaborine which is optionally fused to one or more aromatic rings or fused aromatic rings; wherein the fused aromatic ring system is substituted by one or more substituents, R, that are not fused to the aromatic ring system, selected from the group consisting of deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; and wherein any two adjacent substituents, R, are optionally joined to form one or more non-aromatic rings. Devices, such as organic light emitting devices (OLEDs) that comprise light emitting materials are also provided.
US09627630B2	Organic electroluminescent element, display device and lighting device Disclosed is an organic electroluminescent device having long life, while exhibiting high luminous efficiency. Also disclosed are an illuminating device and a display, each using such an organic electroluminescent device. In the organic electroluminescent device, a compound represented by the general formula (A) which is suitable as a host material for a phosphorescent metal complex is used at least in one sublayer of a light-emitting layer.
US09627623B2	Organic electroluminescent element, compound, and light emitting device, display device and lighting device each using organic electroluminescent element An organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and at least one organic layer including a light emitting layer, disposed between the electrodes. At least one kind of a compound represented by the following general formula (I) is contained in any layer of the at least one organic layer. The organic electroluminescent element has good luminous efficiency, driving voltage, and driving durability, and has low dependence of such performance on a deposition rate. Wherein: L1 to L4, n1 to n4, A1, A5, A6, A10 and, R are as defined in the application.
US09627618B2	Substrate for use in manufacturing display device and method for forming element on substrate A substrate is for use in manufacturing a display device. The substrate includes a first area that corresponds to pixel positions. The substrate further includes a second area adjacent to the first area. The substrate further includes a first mark disposed in the second area, wherein a first virtual line corresponds to the first mark. The substrate further includes a second mark disposed in the second area and spaced from the first mark, wherein a second virtual line corresponds to the second mark and intersects the first virtual line at a virtual reference point. The substrate further includes an indicator disposed in the second area, spaced from the first mark and the second mark, and corresponding to an opening of a mask, wherein a positional relation between the virtual reference point and a point of the indicator represents a positional relation between the substrate and the mask.
US09627617B2	Method for manufacturing organic EL panel A method for manufacturing an organic EL panel includes: applying sealing resin for forming a sealing resin layer to a plurality of spots on an application target surface of one of an EL substrate and a CF substrate, the application target surface being a surface to which the sealing resin is to be applied, and stacking the EL substrate and the CF substrate one on top of the other after the sealing resin is applied, and when the sealing resin is applied, the amount of the sealing resin applied to a spot near an edge of the application target surface is less than the amount of the sealing resin applied to a spot further inward than the spot near the edge.
US09627614B2	Resistive switching for non volatile memory device using an integrated breakdown element A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.
US09627604B2	Tubular spring for receiving and pretensioning an actuator A tubular spring is provided for receiving and pretensioning a piezoelectric or magnetostrictive actuator of an actuator unit, e.g., for actuating a fuel injector valve in internal combustion engines, wherein the tubular spring comprises at least two types of recesses, each comprising different maximum lateral extensions in the longitudinal direction of the tubular spring. The tubular spring is designed to comprise a uniform load distribution about the circumference of the tubular spring even without welding the longitudinal sides thereof abutting one another.
US09627600B2	Mg—Si system thermoelectric conversion material, method for producing same, sintered body for thermoelectric conversion, thermoelectric conversion element, and thermoelectric conversion module Provided are: an Mg—Si system thermoelectric conversion material which exhibits stably high thermoelectric conversion performance; a sintered body for thermoelectric conversion, which uses this Mg—Si system thermoelectric conversion material; a thermoelectric conversion element having excellent durability; and a thermoelectric conversion module. A method for producing an Mg—Si system thermoelectric conversion material according to the present invention comprises a step for heating and melting a starting material composition that contains Mg, Si, Sb and Zn. It is preferable that the contents of Sb and Zn in the starting material composition are respectively 0.1-3.0 at % in terms of atomic weight ratio.
US09627599B2	LED lighting apparatus and heat dissipation module Provided is an LED light which may include a base plate, an LED module disposed under the base plate, a plurality of heat pipes provided over the base plate, and a plurality of heat dissipation fins provided over the base plate. The plurality of heat pipes may include a first portion thermally coupled to the base plate and a second portion that extends from the first portion. The plurality of heat dissipation fins may be spaced apart from each other and thermally coupled to the second portion of the heat pipes to dissipate heat from the LED module. The LED light may include an upper bracket provided over the plurality of heat dissipation fins and fastened to a hanger, and a plurality of studs that connect the base plate to the upper bracket.
US09627598B2	Light emitting device A light emitting device has: a plurality of light emitting elements, a base having a first main surface and a second main surface on the opposite side from the first main surface, the base having conductive patterns disposed on the first main surface on which the light emitting elements are mounted, conductive patterns disposed on the second main surface, and a groove provided on the second main surface of the base corresponding to a space between the light emitting elements, and a light reflecting member that integrally covers side surfaces of the plurality of light emitting elements.
US09627586B2	Electroluminescent element and lighting apparatus comprising the same An electroluminescent element includes a first transparent electrode, a second transparent electrode, a light emitting layer sandwiched between the first transparent electrode and the second transparent electrode, a first transparent member formed on a surface of the first transparent electrode opposite to the light emitting layer, and a second transparent member formed on a surface of the second transparent electrode opposite to the light emitting layer, wherein refractive indices of the first transparent electrode and the second transparent electrode are selected such that as seen from the light emitting layer, a reflectance of an interface between the light emitting layer and the first transparent electrode becomes higher than a reflectance of an interface between the light emitting layer and the second transparent electrode, and wherein a refractive index of the first transparent member is set to be higher than a refractive index of the second transparent member.
US09627585B2	Wiring structure, thin film transistor array substrate including the same, and display device In a wiring conversion part which connects a lower conductive film to a first conductive film each functioning as a wiring, a first transparent conductive film is formed into a pattern in which it covers an end surface of the first conductive film, and an angle formed at a corner part in a portion of the first transparent conductive film making contact with a lower first insulating film (outside a width of the first conductive film) is larger than 90 degrees and smaller than 270 degrees or the corner part has an arc shape. A second transparent conductive film is connected to the lower conductive film and the first transparent conductive film, and the first transparent conductive film is connected to the first conductive film, so that the lower conductive film and the first conductive film are electrically connected to each other.
US09627584B2	Light emitting device and light emitting device package A light emitting device includes a light emitting structure including a plurality of compound semiconductor layers. A current spreading layer is provided under the light emitting structure, and a plurality of wavelength conversion structures is provided in the current spreading layer. An electrode layer is provided under the current spreading layer, and an electrode is provided on the light emitting structure.
US09627583B2	Light-emitting device and method for manufacturing the same There is provided a light-emitting device comprising a light-emitting element. The light-emitting device of the present invention comprises an electrode part for the light-emitting element; a reflective layer provided on the electrode part; and the light-emitting element provided on the reflective layer such that the light-emitting element is in contact with at least a part of the reflective layer, wherein the light-emitting element and the electrode part are in an electrical connection with each other by mutual surface contact via the at least a part of the reflective layer, wherein the electrode part serves as a supporting layer for supporting the light-emitting element, and wherein the electrode part extends toward the outside of the light-emitting element and beyond the light-emitting element.
US09627581B2	Nitride semiconductor structure, electronic device including the nitride semiconductor structure, light-emitting device including the nitride semiconductor structure, and method for producing the nitride semiconductor structure A nitride semiconductor structure includes a nitride semiconductor layer having a principal plane and including a nitride semiconductor. The normal to the principal plane of the nitride semiconductor layer is inclined at 5 degrees or more and 17 degrees or less with respect to the [11-22] axis of the nitride semiconductor constituting the nitride semiconductor layer in the direction of the +c-axis of the nitride semiconductor. The nitride semiconductor structure may further include a substrate having a principal plane which supports the nitride semiconductor layer on the principal plane. The substrate may include any one selected from the group consisting of a nitride semiconductor, sapphire, and Si.
US09627572B2	Light receiving and emitting element module and sensor device using same A light receiving and emitting element module includes a substrate; a light emitting element and a light receiving element on an upper surface of the substrate; a frame-shaped outer wall that on the upper surface of the substrate; and a light shielding wall that is positioned inside the outer wall and partitions an internal space of the outer wall into spaces respectively corresponding to the light emitting element and the light receiving element. The light shielding wall includes a light emitting element-side shading surface on the light emitting element side, a light receiving element-side shading surface on the light receiving element side, and a lower surface that is connected to each of the light emitting element-side shading surface and the light receiving element-side shading surface, and that faces the substrate. The lower surface has an inclined surface inclined with respect to the upper surface of the substrate.
US09627571B2	Semiconductor device An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.
US09627564B2	Optoelectronic device comprising nanostructures of hexagonal type crystals An optoelectronic device comprising: a first conductive layer, a second conductive layer, an active layer between the first conductive layer and the second conductive layer, wherein the active layer comprises a submicrometer size structure of hexagonal type crystals of an element or alloy of elements selected from the carbon group.
US09627562B2	Method of manufacturing a monolayer graphene photodetector and monolayer graphene photodetector In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided.
US09627561B2	Method for etching multi-layer epitaxial material A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate.
US09627560B2	Radiographic image detector A radiographic image detector includes a phosphor layer, a heat shield layer, and a photoelectric converter in this order, wherein the heat shield layer has a thickness T (μm) and a thermal conductivity C (W/m·K) satisfying that C/T is from 0.004 to 5.
US09627551B2	Ultrahigh-voltage semiconductor structure and method for manufacturing the same The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.
US09627549B1	Semiconductor transistor device and method for fabricating the same A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.
US09627547B2	Semiconductor structure A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.
US09627541B2	Non-planar transistor and method of forming the same A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.
US09627534B1	Semiconductor MOS device having a dense oxide film on a spacer A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.
US09627533B2	High selectivity nitride removal process based on selective polymer deposition A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
US09627532B2	Methods and apparatus for training an artificial neural network for use in speech recognition Methods and apparatus for training a multi-layer artificial neural network for use in speech recognition. The method comprises determining for a first speech pattern of the plurality of speech patterns, using a first processing pipeline, network activations for a plurality of nodes of the artificial neural network in response to providing the first speech pattern as input to the artificial neural network, determining based, at least in part, on the network activations and a selection criterion, whether the artificial neural network should be trained on the first speech pattern, and updating, using a second processing pipeline, network weights between nodes of the artificial neural network based, at least in part, on the network activations when it is determined that the artificial neural network should be trained on the first speech pattern.
US09627523B2	High electron mobility transistor A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region. The matrix electrode comprises a plurality of first electrodes arranged on the epitaxial stack, a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes, a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes. One of the plurality of first electrodes comprises a first side, a second side, a third side and a fourth side. The first side and the third side are opposite sides, and the second side and the fourth side are opposite sides. Two of the plurality of second electrodes are arranged on the first side and the third side, and two of the plurality of third electrodes are arranged on the second side and the fourth side.
US09627518B2	Power integrated devices, electronic devices including the same and electronic systems including the same A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.
US09627514B1	Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device is provided as follows. Epitaxial layers is formed on an active fin structure of a substrate. First metal gate electrodes are formed on the active fin structure. Each first metal gate electrode and each epitaxial layer are alternately disposed in a first direction on the active fin structure. ILD patterns are formed on the epitaxial layers, extending in a second direction crossing the first direction. Sacrificial spacer patterns are formed on the first metal gate electrodes. Each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the first metal gate electrodes. Self-aligned contact holes and sacrificial spacers are formed by removing the ILD patterns. Each self-aligned contact hole exposes a corresponding epitaxial layer disposed under each ILD pattern. Source/drain electrodes are formed in the self-aligned contact holes. The sacrificial spacers are replaced with air spacers.
US09627513B2	Method for manufacturing lateral double-diffused metal oxide semiconductor transistor The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type. The method simplifies a manufacturer process and improves reliability of the resultant devices.
US09627510B1	Structure and method for replacement gate integration with self-aligned contacts A method for fabricating a semiconductor device comprises forming a dummy gate on a substrate; forming spacers at opposing sides of the dummy gate; depositing a sacrificial interlayer dielectric over the dummy gate; planarizing the interlayer dielectric to expose the dummy gate; removing the dummy gate; forming a replacement metal gate with a protective cap between the spacers and on the substrate to replace the removed dummy gate; removing the sacrificial interlayer dielectric; siliciding exposed areas of the substrate adjacent to the replacement metal gate; depositing a final interlayer dielectric over the replacement metal gate and the exposed silicided areas; and forming vias through the final interlayer dielectric to the silicided areas.
US09627508B2	Replacement channel TFET A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.
US09627506B2	Method of manufacturing semiconductor device A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
US09627503B2	Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.
US09627499B2	Electrical conduction element, electronic device, and method for operating electrical conduction element A nonvolatile three-terminal element is provided that operates by controlling a bandgap in an electron state of a graphene-based material. An ion conductor (5) having hydrogen ion or oxygen ion conductivity is provided between graphene oxide or graphene (hereinafter, referred to as GO) (6), and a gate electrode (1). In addition, a drain electrode (2) and a source electrode (3) are provided on a GO (6) side.
US09627498B2	Contact structure for thin film semiconductor A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.
US09627497B1	Semiconductor device with trench epitaxy and contact A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench.
US09627495B2	Method for manufacturing semiconductor device A method of fabricating a semiconductor device includes forming fin-shaped semiconductor layers on a semiconductor substrate. First and second pillar-shaped semiconductor layers are formed, and first and second control gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second selection gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second contact electrodes are formed around upper portions of the first and second pillar-shaped semiconductor layers, respectively.
US09627478B1	Integrated vertical nanowire memory A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the semiconductor substrate provides electrical isolation between the substrate and the second crystalline segment. Second and fourth crystalline segments are each formed from a p-type or an n-type semiconductor material, while the third crystalline segment is formed from a semiconductor material that is oppositely doped with respect to the second and fourth crystalline segments.
US09627477B2	Trench isolation structure having isolating trench elements A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle θ (0°<θ<90°) from the first direction.
US09627472B2	Semiconductor structure with varying doping profile and related ICS and devices An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
US09627471B2	Super junction semiconductor device having strip structures in a cell area A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.
US09627457B2	Organic light emitting display device and method of manufacturing the same An organic light emitting display device includes a spacer on a pixel defining layer. The pixel defining layer includes openings corresponding to pixels. The device further includes first pixels to third pixels emitting light having different colors. The first pixels and the second pixels are alternately disposed in a row direction, and the third pixels are continuously disposed in a row direction. The row in which the first pixels and the second pixels are alternately disposed and the row in which the third pixels are continuously disposed are adjacent to each other in a column direction The spacer is disposed between two of the third pixels.
US09627456B2	Organic light-emitting display apparatus An organic light-emitting display apparatus includes: a display substrate; at least one thin film transistor (TFT) on the display substrate; an organic light-emitting diode (OLED) electrically connected to the TFT, the OLED including: a first electrode on each sub-pixel on the display substrate; an intermediate layer on the first electrode; and a second electrode on the intermediate layer; an encapsulation substrate covering the OLED; a filler filling a space between the display substrate and the encapsulation substrate, the filler including scatterers having optical anisotropy; and a color filter between the encapsulation substrate and the filler, the color filter including a color filter electrode at a surface of the color filter.
US09627453B2	Display unit A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values.
US09627452B2	Organic light emitting display apparatus An organic light emitting display apparatus wherein a shift of white light caused by a viewing angle is reduced by adjusting an offset distance between one end of a corresponding emission region and one end of the black matrix adjacent to the one end of the corresponding emission region, thereby preventing a white color shift phenomenon at various viewing angles. Accordingly, a certain image is produced regardless of a use environment of a user's viewing angle.
US09627450B2	Organic light emitting display device An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other.
US09627444B2	Fine metal mask and method of manufacturing the same A method of manufacturing a fine metal mask is provided. The method of manufacturing a fine metal mask includes: forming a first recessed portion in a first surface of a base member; forming an edge portion of the first recessed portion in a uniform depth; forming a second recessed portion in a second surface of the base member, the second surface being opposite to the first surface; and communicating the first recessed portion and the second recessed portion of the base member. A fine metal mask produced by the inventive method is also described and may be used to fabricate OLEDs having better resolution and an increased aperture ratio in comparison with OLEDs prepared using the fine metal masks of the conventional art.
US09627442B2	Horizontally oriented and vertically stacked memory cells Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.
US09627439B2	ZnO-based system on glass (SOG) for advanced displays A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display.
US09627438B1	Three dimensional memory arrays and stitching thereof The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.
US09627436B2	Substrate free LED package A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.
US09627431B2	Solid-state imaging device A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.
US09627424B2	Photodiodes for ambient light sensing and proximity sensing Ambient light sensing and proximity sensing is accomplished using pairs of stacked photodiodes. Each pair includes a shallow diode with a shallow junction depth that is more sensitive to light having a shorter wavelength and a deeper diode with a deeper junction depth more sensitive to light with longer wavelengths. Photodiodes receiving light passed through cyan, yellow, and magenta filters and light passed without a color filter are used to generate red, green, and blue information through a subtractive approach. The shallow diodes are used to generate lux values for ambient light and the deeper diodes are used for proximity sensing. One or more of the deep diodes may be used in correction to lux determinations of ambient light.
US09627418B2	Semiconductor device Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween.
US09627416B2	Array substrate and method for manufacturing the same, display device An array substrate is disclosed. The array substrate includes gate lines and data lines, and first and second signal lines. A first data line is between first and second pixel units, respectively including first and second film transistors. A first gate line is electrically connected to the gate electrodes of the first and second film transistors. The second electrode of the second film transistor is electrically connected to the first data line, and the second electrode of the first film transistor is electrically connected to the first signal line. The array substrate also includes a common electrode layer partially located between a third pixel unit and the first pixel unit, which is electrically insulated. In addition, a portion of the common electrode layer between the first pixel unit and the second pixel unit overlaps the first data line.
US09627409B2	Semiconductor device with thin-film resistor A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.
US09627408B1	D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.
US09627405B1	Semiconductor device and manufacturing method thereof A semiconductor device may include a multi-layered source layer, conductive patterns, interlayer insulating layers, and a channel pillar. The multi-layered source layer may include a lower source layer, an interlayer source layer, and an upper source layer. The conductive patterns and interlayer insulating layers may be alternately disposed on the multi-layered source layer. The channel pillar may penetrate the conductive patterns. The interlayer insulating layers, the upper source layer, and the interlayer source layer, the channel pillar may extend into the lower source layer. The channel pillar may be in contact with the interlayer source layer. Doped regions having various structures can be formed at a lower portion of the channel pillar, thereby improving the operational reliability of the semiconductor device.
US09627403B2	Multilevel memory stack structure employing support pillar structures A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.
US09627400B2	Nonvolatile semiconductor memory device and method for manufacturing same According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.
US09627398B2	Method of manufacturing semiconductor device A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.
US09627397B2	Memory device and method for fabricating the same A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.
US09627396B2	Semiconductor device including a stack having a sidewall with recessed and protruding portions A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.
US09627393B2	Height reduction in memory periphery A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a corresponding contact pad by a lead line. The word lines in the memory array area have a first height and low-profile areas of lead lines in the word line hookup area have a second height that is less than the first height.
US09627391B2	Non-volatile memory device According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
US09627380B2	Semiconductor devices having work function adjusting films with chamfered top surfaces A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.
US09627378B2	Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
US09627375B2	Indented gate end of non-planar transistor In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.
US09627374B2	Electronic circuits including a MOSFET and a dual-gate JFET Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
US09627373B2	CMOS compatible fuse or resistor using self-aligned contacts A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.
US09627371B1	Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.
US09627359B2	Semiconductor device and manufacturing method of the same Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
US09627358B2	Method for interconnecting stacked semiconductor devices A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
US09627355B2	Package-on-package structure having polymer-based material for warpage control A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.
US09627352B2	Devices and methods for processing singulated radio-frequency units Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a plate having a plurality of apertures. Each aperture can be dimensioned to receive and position a singulated RF package to thereby facilitate processing of the singulated RF packages positioned in their respective apertures. In some embodiments, such a device can be utilized to batch process high volume of RF packages as if the RF packages are still in a panel format.
US09627350B2	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor element. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.
US09627343B2	Power semiconductor module with switching device and assembly A power semiconductor module and an arrangement including it. The module includes a housing, a switching device having a substrate connected to the housing, a connecting device, load connection devices and a pressure device movable relative to the housing. The substrate has a first central passage and conductor tracks which are electrically insulated from one another. A power semiconductor component sits on a conductor track. The connecting device has two main surfaces and an electrically conductive film. The pressure device has a pressure body with a second passage, in alignment with the first passage and a first recess. A pressure element projects out of the recess, and presses onto a section of the second main surface. This section is within the surface of the component projects normal to the substrate. The first and second passages receive a fastener which force-fittingly fastens the module to the cooling device.
US09627342B2	Electronic component and method of manufacturing electronic component Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties.
US09627340B2	Semiconductor device According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal. The second semiconductor chip receives, by the first bus width, the first signal transferred through the first via.
US09627339B2	Method of forming an integrated circuit device including a pillar capped by barrier layer A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.
US09627337B2	Integrated circuit device An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.
US09627334B2	Self-aligned under bump metal An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.
US09627326B2	Method for forming alignment marks and structure of same A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
US09627324B2	Apparatus and method for processing a substrate A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at said temperature T2 until the substrate has been covered with a film comprising a metal.
US09627320B2	Nanowires coated on traces in electronic devices Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.
US09627314B2	Fuse structure and method of blowing the same A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
US09627312B2	On-chip capacitors and methods of assembling same An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.
US09627311B2	Chip package, package substrate and manufacturing method thereof A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.
US09627305B2	Semiconductor module with interlocked connection A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.
US09627304B2	Method of producing a large number of support apparatus which can be surface-mounted, arrangement of a large number of support apparatus which can be surface-mounted, and support apparatus which can be surface-mounted A method of producing a multiplicity of surface-mountable carrier devices includes: A) providing a carrier plate having a first main face and a second main face located opposite the first main face, B) applying an electrically conductive layer to the first main face, C) applying a solder resist mask to a side of the electrically conductive layer remote from the carrier plate, wherein a multiplicity of adjoining regions are formed on the electrically conductive layer by the solder resist mask, D) applying a solder material to the solder resist mask and the electrically conductive layer, wherein the solder resist mask and the electrically conductive layer are at least partially covered by the solder material, and E) singulating the carrier plate and the electrically conductive layer along and through the solder resist mask and the solder material, wherein the solder material remains at least partially on the solder resist mask.
US09627302B2	Power semiconductor device An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.
US09627301B2	Integrated circuit arrangement An integrated circuit arrangement includes a flange, a transistor die, and a first conducting element defining a lead. The flange includes a conducting material and the transistor die is disposed on a surface of the flange. The first conducting element is electrically connected to the transistor die via connecting elements to allow current flow from the transistor die. The flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die. The flange includes one or more reduced thickness portions that are configured to limit the return current paths and control current flow passing through the flange to the transistor die.
US09627300B2	Amplifier package with multiple drain bonding wires An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.
US09627297B2	Solder flow-impeding plug on a lead frame Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame.
US09627295B2	Devices, systems and methods for manufacturing through-substrate vias and front-side structures Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.
US09627288B2	Package structures and methods of forming the same Package structures and methods of forming the same are disclosed. A package structure includes a die, a dielectric layer, an encapsulant and a plurality of supports. The die includes, over a first side thereof, a plurality of connectors. The dielectric layer is formed over the first side of the die aside the connectors. The encapsulant is aside the die. The supports penetrate through the dielectric layer. The grinding rate of the supports is substantially the same as that of the encapsulant but different from that of the dielectric layer.
US09627287B2	Thinning in package using separation structure as stop A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.
US09627285B2	Package substrate A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art.
US09627283B2	Display device In a liquid crystal display device it is desirable to test in the state of TFT substrates, without reducing the number of TFT substrates to be obtained from one mother TFT substrate, and without increasing the overall size of the TFT substrates. Test terminals are formed on the outside of terminals for driving the liquid crystal display device. The test terminals of the specific TFT substrate are formed in another TFT substrate just below the specific TFT substrate. The area in which the test lines are formed is a space in which a sealing material is formed, between the display area and an end of the lower TFT substrate. Thus, the size of the TFT substrates is not actually increased. A test line area is not separately formed and not discarded, so that the number of TFT substrates to be obtained from one mother TFT substrate is not reduced.
US09627282B2	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.
US09627281B2	Semiconductor chip with thermal interface tape A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.
US09627277B2	Method and structure for enabling controlled spacer RIE A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.
US09627276B2	Self-aligned low defect segmented III-V finFET A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice structure and the substrate comprising a second material comprising a second lattice structure. Forming the one or more fin structures on the substrate includes forming one or more trenches in the substrate, and growing the first material in the one or more trenches. The first lattice structure is different from the second lattice structure. The one or more fin structures are self-aligned by the one or more trenches.
US09627272B2	Patterning scheme to minimize dry/wets strip induced device degradation A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.
US09627270B2	Dual work function integration for stacked FinFET A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.
US09627268B2	Method for fabricating semiconductor device A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.
US09627264B2	Semiconductor device and formation thereof A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.
US09627255B1	Semiconductor device package substrate having a fiducial mark A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.
US09627253B2	Semiconductor device including air gaps and method of fabricating the same A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.
US09627251B2	Forming array contacts in semiconductor memories Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
US09627250B2	Method and apparatus for back end of line semiconductor device processing A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.
US09627245B2	Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.
US09627241B2	Resin sheet attaching method A resin sheet attaching method of attaching a resin sheet to a workpiece. The resin sheet attaching method includes a molecular weight reducing step of applying vacuum ultraviolet radiation to the front side of the resin sheet, thereby cutting an intermolecular bond in a surface region having a depth of tens of nanometers from the front side of the resin sheet to thereby reduce the molecular weight of the surface region and produce an adhesive force, and a resin sheet attaching step of attaching the front side of the resin sheet to the workpiece after performing the molecular weight reducing step.
US09627239B2	Wafer surface 3-D topography mapping based on in-situ tilt measurements in chemical vapor deposition systems The surface topography of at least one wafer can be determined in-situ based on deflectometer measurements of surface tilt. The deflectometer is re-positioned by a scanning positioner to facilitate tilt mapping of the wafer surface for each of the at least one wafer. A surface height mapping engine is configured to generate a three-dimensional topographic mapping of the surface of each of the at least one wafer based on the mapping of the tilt.
US09627237B2	Apparatus, method and non-transitory storage medium for accommodating and processing a substrate A substrate accommodating and processing apparatus is provided with a cassette mounting table, a processing part, a substrate transfer mechanism, a partition wall, a cassette stage, and a lid attaching/detaching mechanism. The lid attaching/detaching mechanism is provided with a key configured to be engaged with a key hole installed in the lid, and configured to switch a latch between locking and unlocking positions. The mechanism is also provided with a lid abnormality detecting sensor, a lid attaching/detaching mechanism closing sensor, a lid attaching/detaching mechanism opening sensor, a pressure sensor and a control part.
US09627236B2	Substrate treating apparatus A substrate treating apparatus is provided which includes housing and a door assembly. The housing provides a process space for treating a substrate therein and has an opening formed at a sidewall thereof. The door assembly opens and closes the opening. The door assembly includes a shutter, a driving member, and a gap maintaining unit. The driving member transfers the shutter to an open position where the shutter faces to the opening and to a blocking position where the shutter gets out of the open position. The gap maintaining unit maintains a constant gap between the shutter and the sidewall.
US09627226B2	Fabrication method of semiconductor package A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.
US09627224B2	Semiconductor device with sloped sidewall and related methods A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.
US09627223B2	Methods and apparatus of packaging with interposers Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
US09627222B2	Method for fabricating nitride semiconductor device with silicon layer A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.
US09627221B1	Continuous process incorporating atomic layer etching A method of continuous fabrication of a layered structure on a substrate having a patterned recess, includes: (i) forming a dielectric layer on a substrate having a patterned recess in a reaction chamber by PEALD using a first RF power; (ii) continuously after completion of step (i) without breaking vacuum, etching the dielectric layer on the substrate in the reaction chamber by PEALE using a second RF power, wherein a pressure of the reaction chamber is controlled at 30 Pa to 1,333 Pa throughout steps (i) and (ii); a noble gas is supplied to the reaction chamber continuously throughout steps (i) and (ii); and the second RF power is higher than the first RF power.
US09627209B2	Method for producing a semiconductor A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.
US09627208B2	Semiconductor switch According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film.
US09627207B2	Methods of forming semiconductor device having gate electrode Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.
US09627205B2	Method of manufacturing a semiconductor device using purified block copolymers and semiconductor devices In a method of manufacturing a semiconductor device, a blend solution that includes a block copolymer and an adsorbent is prepared. The block copolymer is synthesized by a copolymerization between a first polymer unit and a second polymer unit having a hydrophilicity greater than that of the first polymer unit. The adsorbent on which the block copolymer is adsorbed is extracted. The block copolymer is separated from the adsorbent. The block copolymer is collected. The block copolymer may be used to form a mask on an object layer on a substrate and the mask used to etch the object layer.
US09627204B2	Composition for forming a coating type BPSG film, substrate formed a film by said composition, and patterning process using said composition The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process.
US09627199B2	Methods of fabricating micro- and nanostructure arrays and structures formed therefrom Methods of fabricating micro- and nanostructures comprise top-down etching of lithographically patterned GaN layer to form an array of micro- or nanopillar structures, followed by selective growth of GaN shells over the pillar structures via selective epitaxy. Also provided are methods of forming micro- and nanodisk structures and microstructures formed from thereby.
US09627196B2	Method for processing a carrier According to various embodiments, a method for processing a carrier may include: co-depositing at least one metal from a first source and carbon from a second source over a surface of the carrier to form a first layer; forming a second layer over the first layer, the second layer including a diffusion barrier material, wherein the solubility of carbon in the diffusion barrier material is less than in the at least one metal; and forming a graphene layer at the surface of the carrier from the first layer by a temperature treatment.
US09627190B2	Energy resolved time-of-flight mass spectrometry A time-of-flight mass spectrometer (TOF-MS) utilizes an ion dispersion device and a position-sensitive ion detector or an energy-sensitive ion detector to enable measurement of time of flight and kinetic energy of ions arriving at the detector. The measurements may be utilized to improve accuracy in calculating ion masses.
US09627189B2	Vacuum system The invention concerns a vacuum system, comprising a first vacuum chamber and a second vacuum chamber, the first vacuum chamber being evacuated by a first vacuum pump, in particular a turbomolecular pump, the first and the second vacuum chamber being connected by a passage, wherein the passage is surrounded by a sealing arrangement comprising an inner seal and an outer seal with a plenum positioned between the inner seal and the outer seal, the plenum being evacuated by a support vacuum pump, and wherein at least one sealing face of the inner seal consists of the wall material of the first or the second vacuum chamber, in particular the inner seal being formed by direct contact between the wall material of the first vacuum chamber and the wall material of the second vacuum chamber. Additionally, the invention concerns a mass spectrometry system.
US09627188B2	Method and system for the quantitative chemical speciation of heavy metals and other toxic pollutants This invention relates to systems and methods for measuring quantitatively multiple species or heavy metals, including mercury, and other toxic pollutants. More specifically, the systems and methods of the invention allows for determination of the analytes even at very low concentration, through concentration on a collection interface, desorption and analysis by mass spectrometry. The invention also provides for a portable device or kit for modifying an existing mass spectrometer.
US09627186B2	System, method and apparatus for using optical data to monitor RF generator operations A system and method monitoring a plasma with an optical sensor to determine the operations of a pulsed RF signal for plasma processing including a plasma chamber with an optical sensor directed toward a plasma region. An RF generator coupled to the plasma chamber through a match circuit. An RF timing system coupled to the RF generator. A system controller is coupled to the plasma chamber, the RF generator, the optical sensor, the RF timing system and the match circuit. The system controller includes a central processing unit, a memory system, a set of RF generator settings and an optical pulsed plasma analyzer coupled to the optical sensor and being capable to determine a timing of a change in state of an optical emission received in the optical sensor and/or a set of amplitude statistics corresponding to an amplitude of the optical emission received in the optical sensor.
US09627185B2	Methods and apparatus for in-situ cleaning of a process chamber Methods and apparatus for in-situ cleaning of substrate processing chambers are provided herein. A substrate processing chamber may include a chamber body enclosing an inner volume; a chamber lid removably coupled to the chamber body and including a first flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first outlet; a chamber floor including a second flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first inlet; and a pump ring disposed in and in fluid communication with the inner volume, the pump ring comprising an upper chamber fluidly coupled to a lower chamber, and a second outlet fluidly coupled to the lower chamber to selectively open or seal the inner volume to or from the second outlet.
US09627178B2	Charged particle beam drawing apparatus, information processing apparatus and pattern inspection apparatus A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level.
US09627173B2	Stage device and charged particle beam apparatus using the stage device To attain the above object, in the present invention, proposed are a stage apparatus including a sample stage that mounts a sample, a first position detection device that detects a position of the sample stage, a second position detection device that detects a position of the sample stage when the sample stage is positioned in a part of a stage movement range that the first position detection device is capable of detecting, and a control device that adjusts an offset amount of the first position detection device on the basis of a position detection result obtained by the second position detection device, and a charged particle beam apparatus using the stage apparatus.
US09627170B2	Electrode for use in ion implantation apparatus and ion implantation apparatus An electrode for use in an ion implantation system includes a body portion and a penetration portion. The penetration portion includes penetration holes which are closely and regularly arranged. The penetration holes have the shape of a circle or a regular polygon with at least four sides. The electrode has an increased aperture ratio which, in turn, increases the density of the ion beam, thereby improving the efficiency of the ion implantation process.
US09627167B2	Apparatus for generating plasma Provided herein an apparatus for generating plasma, the apparatus including a nozzle array, first electrode, and housing. The nozzle discharges plasma. The first electrode is disposed to surround the nozzle array. The housing is disposed to surround the nozzle array and first electrode. The nozzle includes a plurality of nozzles disposed adjacent to one another and in the form of an array, each nozzle configured to discharge plasma. Therefore, it is possible to generate a large size plasma evenly and stably.
US09627165B2	Circuit breaker tripping shaft with over-molded levers A tripping shaft apparatus for a circuit breaker. Tripping shaft apparatus includes a rigid shaft portion and a polymer shaft portion molded onto the rigid shaft portion, wherein the polymer shaft portion includes a first molded lever. At least one other lever is a part of the tripping shaft apparatus. A torsion spring is received over the shaft between the first molded lever and the second lever providing an integral torsion spring positioned between the levers. Circuit breaker tripping assemblies and methods of assembling a circuit breaker tripping assembly are provided, as are other aspects.
US09627162B1	Finger activated mouse device/switching device The embodiments herein show a switching device/mouse device activated by proximal phalanx of a finger(s). The switching device/mouse is ergonomically designed to prevent carpal-tunnel effect and bending of fingers. The switching device/mouse includes an enclosure having a top wall, a bottom wall, and sidewalls. The switching device/mouse includes an upper levers/elongated buttons pivotally supported by the top wall. The upper levers/elongated buttons are elevated surfaces to better support a user's fingers in a rest position. The mouse is operated by pressing down on the elevated surfaces of the upper levers with the proximal phalanx of the fingers without bending the fingers.
US09627160B1	Systems and methods for rotary knob friction adjustment control A circuit breaker including a trip unit having an internal support and a friction adjustment control system for knob control is provided. The internal support includes a first opening to receive a first rotary knob having one or more first smooth rings and a second opening to receive a second rotary knob having one or more second smooth rings. The trip unit includes a first knob control of the first rotary knob. The first knob control includes a first structural support, a first housing and a first spring installed in the first housing against the first structural support. The trip unit further includes a second knob control of the second rotary knob. The second knob control includes a second structural support, a second housing and a second spring installed in the second housing against the second structural support.
US09627158B2	Keyboard key using an asymmetric scissor-type connecting element A keyboard module includes a first key and a second key. The first key includes a first keycap and a first scissors-type connecting element. The first scissors-type connecting element includes a first outer frame and a first inner frame. The second key includes a second keycap and a second scissors-type connecting element. The second scissors-type connecting element includes a second outer frame and a second inner frame. The first outer frame, the first inner frame and the second inner frame have symmetrical structures. The second outer frame has an asymmetrical structure.
US09627156B2	Snap-action switch A snap-action switch has at least two switching contacts, at least one flexible circuit carrier carrying conductor tracks and at least one multifunction component receiving the flexible circuit carrier. The switching contacts and the conductor tracks are connected with each other via a non-detachable connection. The region of the flexible circuit carrier between the switching contacts is configured as a bending tab.
US09627153B2	Electrical medium or high voltage switching device An electrical switching device for medium or high voltage circuits having at least a nominal contact arrangement, wherein the nominal contact arrangement includes at least a first nominal contact including a plurality of contact fingers forming a finger cage concentric with respect to a longitudinal axis, wherein the contact fingers are separated from one another by empty slots extending up to a free end of the contact fingers. The empty slots include first and second empty slots, wherein the second empty slots are shorter than the first empty slots, and wherein the contact fingers are grouped in groups, with the contact fingers of each group being separated by second empty slots and the contact fingers of adjacent groups being separated by first empty slots.
US09627152B2	Low resistance electrode for electric dual layer capacitor and method of manufacturing the same A low resistance electrode includes a through type aluminum sheet, a plurality of first hollow protrusion members protruded to one side of the through type aluminum sheet, a plurality of second hollow protrusion members protruded to the other side of the through type aluminum sheet, a conductive adhesive layer coated on a first surface and second surface of the through type aluminum sheet, a first active material sheet bonded to the first surface of the through type aluminum sheet, and a second active material sheet bonded to the second surface of the second surface of the through type aluminum sheet.
US09627151B2	Electrical storage module An electrical storage module in which a plurality of electricity storage elements are electrically connected by conductive member, includes: a voltage detection board having voltage detection conductor that detects terminal voltage of the electricity storage element; a first external threaded component that connects the voltage detection conductor of the voltage detection board to the conductive member; and a cover that covers the voltage detection board; wherein: the cover is made from an insulating material; the conductive member has a first internal threaded portion into which the first external threaded component is to be screwingly engaged; and the distance between the inside surface of the cover that faces a head portion of the first external threaded component and an upper surface of the head portion of the first external threaded component is shorter than the distance between an end portion of the first internal threaded portion towards the cover side and an end of shaft portion of the first external threaded component.
US09627147B2	Composition and method for forming electroactive coating comprising conjugated heteroaromatic polymer, capacitor and antistatic object comprising the electroactive coating, and solid electrolytic capacitor and method for fabricating the same A composition for forming an electroactive coating is described, including an acid as a polymerization catalyst, at least one functional component, and at least one compound of formula (1) as a monomer: wherein X is selected from S, O, Se, Te, PR2 and NR2, Y is hydrogen (H) or a precursor of a good leaving group Y− whose conjugate acid (HY) has a pKa of less than 30, Z is hydrogen (H), silyl, or a good leaving group whose conjugate acid (HY) has a pKa of less than 30, b is 0, 1 or 2, each R1 is a substituent, and the at least one compound of formula (1) includes at least one compound of formula (1) with Z═H and Y≠H.
US09627145B2	Electrolytic capacitor for use in a charge/discharge circuit with shorter period and greater voltage difference An electrolytic capacitor according to the present invention employs a capacitor element wherein an anode foil having an anode internal terminal and a cathode foil having a cathode internal terminal are wound or laminated through a separator. The end of the anode foil faces with the cathode foil through the separator and the surface area of the cathode internal terminal is provided with an enlargement treatment, whereby the small area portion of the cathode foil that faces with the anode foil is eliminated, and the charge/discharge characteristics are thus improved. Furthermore, in the electrolytic capacitor provided with the capacitor element wherein the anode foil having the anode internal terminal and the cathode foil having the cathode internal terminal are wound or laminated through the separator, the capacitor element being impregnated with an electrolyte, the cathode internal terminal is composed of an aluminum material, the surface of the cathode internal terminal is etched and the concentration of iron in the etching layer is less than 300 ppm.
US09627141B2	Ceramic multi-layered capacitor A ceramic multi-layer capacitor includes a main body, which has ceramic layers arranged along a layer stacking direction to form a stack, and first and second electrode layers arranged between the ceramic layers. The multi-layer capacitor also includes a first external contact-connection arranged on a first side surface of the main body and electrically conductively connected to the first electrode layers, and a second external contact-connection arranged on a second side surface (62) of the main body (2). The second side surface is situated opposite the first side surface and is electrically conductively connected to the second electrode layers.
US09627139B2	Multilayered ceramic capacitor and board for mounting the same There is provided a multilayered ceramic capacitor including: a ceramic body in which a plurality of dielectric layers are stacked; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance; an upper cover layer formed above the active layer, a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes formed to cover both end surfaces of the ceramic body, wherein a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9.
US09627138B1	Apparatus and associated methods for capacitors with improved density and matching Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.
US09627135B2	Laminated ceramic capacitor A ceramic capacitor having dielectric ceramic layers that include Ba, Re (Re is at least one of La, Ce, Pr, Nd, and Sm), Ti, Zr, M (M is at least one of Mg, Al, Mn, and V), Si, and optionally Sr, where at least some of the Ba, Re, Ti, and Zr and optionally Sr are in the form of a perovskite compound. Respective amounts, expressed as parts by mol, of the elements of the dielectric ceramic layers satisfy, with respect to a total of 100 of the Ti amount and the Zr amount, 0≦a≦20.0 where a is the Sr amount; 0.5≦b≦10.0 where b is the Re amount; 46≦c≦90 where c is the Zr amount; 0.5≦d≦10.0 where d is the M amount; 0.5≦e≦5.0 where e is the Si amount; and 0.990≦m≦1.050 where m is a ratio of a total of the Ba amount, the Sr amount, and the Re amount, to the total of the Ti amount and the Zr amount.
US09627131B2	Multilayer ceramic capacitor having an intermitting part A multilayer ceramic capacitor includes: a ceramic body; first and second internal electrodes disposed so as to be alternately exposed to both end surfaces of the ceramic body with each of dielectric layers; first and second external electrodes formed so as to be extended onto portions of one main surface of the ceramic body, respectively; third and fourth external electrodes formed on both side surfaces of the ceramic body, respectively, so as to be extended onto portions of both main surfaces of the ceramic body, respectively; an intermitting part connecting the third and fourth external electrodes to one another; first and second land patterns formed so as to be connected to the first and third external electrodes, respectively; and a third land pattern formed so as to be connected to both of the second and fourth external electrodes.
US09627130B2	Magnetic connection and alignment of connectible devices A first and second electronic device each including a connection surface and a magnetic element. The first and second devices may be in contact along the respective connection surfaces. The magnetic elements may be configured to align the first and second devices by moving either or both of the first and second devices relative to each other to achieve an aligned position. The magnetic element may also be operative to resist disconnection of first and second electronic devices when in the aligned position.
US09627127B2	High-efficiency, energy-saving device for inserting between a power source and a motive and/or lighting power load An energy-saving device (1) inserted between a three-phase power supply (A) and a three-phase load (L), includes a three-phase electrical transformer (10), each phase of which includes a transformation assembly (11) with a primary winding (2) connected at a first end (5) to one phase of the power supply (A) and electromagnetically coupled to a secondary winding (3) connected at its second end (S1) to one phase of the load (L). The device (1) involves the second ends (6) of the primary windings (2) in each of the transformation assemblies (11), lying opposite the first ends (5), being electrically connected to one another by a first switch (4). The device (1) also involves each of the secondary windings (3) being connected in parallel to a second switch (7) for enabling or disabling the operation of the energy-saving device (1) between the power source (A) and the load (L).
US09627126B2	Printed circuit board including inductor A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element.
US09627124B2	Ignition coil with molding mark In an ignition coil, a housing has an inner chamber, and a transformer is installed in the inner chamber of the housing. A molded side-core assembly of a transformer includes an arched side core magnetically coupled to first and second ends of a longitudinal center core and located outside a circumferential part of primary and secondary windings. The molded side-core assembly includes an insulation cover molded to cover at least part of the arched side core. The insulation cover has a surface and at least one molding mark formed on the surface thereof. An insulation filler is filled in the inner chamber of the housing while the at least part of the arched side core is exposed from the insulation filler and the at least one molding mark is hermetically sealed in the insulation filler.
US09627119B2	Persistent-mode MRI magnet fabricated from reacted, monofilamentary MgB2 wires and joints A superconducting magnet and method for making a superconducting magnet, are presented. The superconducting magnet is made by forming a coil from windings of a first wire comprising a reacted MgB2 monofilament, filling a cavity of a stainless steel billet with a Mg+B powder. Monofilament ends of the first wire and a similar second wire are sheared at an acute angle and inserted into the billet. A copper plug configured to partially fill the billet cavity is inserted into the billet cavity. A portion of the billet adjacent to the plug and the wires is sealed with a ceramic paste.
US09627118B2	Gapped magnet core A gapped core leg for a shunt reactor, comprising magnetic core elements separated by spacers cast directly between the core elements. Accordingly, a rigid core leg construction is achieved.
US09627117B2	Thin film ferrite lamination Forming a ferrite thin film laminate includes heating a layered assembly to form a laminate. The layered assembly includes a first coated substrate having a first ferrite layer opposite a first thermoplastic surface and a second coated substrate having a second ferrite layer opposite a second thermoplastic surface to form a laminate. Each coated substrate is formed by forming a ferrite layer on a surface of a thermoplastic substrate. The coated substrates are arranged such that the first ferrite layer contacts the second thermoplastic surface. Heating the layered assembly includes bonding the first coated substrate to the second coated substrate such that the first ferrite layer is sandwiched between a first thermoplastic substrate and a second thermoplastic substrate. The ferrite thin film laminate may include a multiplicity of coated substrates.
US09627114B2	Magnetic plasmonic nanoparticle positioned on a magnetic plasmonic substrate Described embodiments include a system, method, and apparatus. The apparatus includes a magnetic substrate at least partially covered by a first negative-permittivity layer comprising a first plasmonic outer surface. The apparatus includes a plasmonic nanoparticle having a magnetic element at least partially covered by a second negative-permittivity layer comprising a second plasmonic outer surface. The apparatus includes a dielectric-filled gap between the first plasmonic outer surface and the second outer surface. The first plasmonic outer surface, the dielectric-filled gap, and the second plasmonic outer surface are configured to support one or more mutually coupled plasmonic excitations.
US09627106B2	High density shielded electrical cable and other shielded cables, systems, and methods A shielded cable includes adjacent first and second conductor sets. Each conductor set includes two or more insulated conductors. The first conductor set also includes a ground conductor that generally lies in the plane of the insulated conductors of the first conductor set. At least 90% of the periphery of each conductor set is encompassed by a shielding film. First and second non-conductive polymeric films are disposed on opposite sides of the cable and form cover portions substantially surrounding each conductor set, and pinched portions on each side of the cable. When the cable is laid flat, the distance between the center of the ground conductor of the first conductor set and the center of the nearest insulated conductor of the second conductor set is σ1, the center-to-center spacing of the insulated conductors of the second conductor set is σ2, and σ1/σ2 is greater than 0.7.
US09627104B2	Harness exterior protection member and wire harness using the same A harness exterior protection member with an electric wire bundle inserted therein includes a bent portion and a straight portion which are formed in a cylindrical shape in an integrated manner formed of a flame-retardant polyamide resin composition. A thickness of the straight portion is set to be twice to four times of a thickness of the bent portion. A bending radius of the bent portion is 10 mm or larger, and a bending strength of the straight portion is 15 to 25 N.
US09627102B2	Wire harness An outer cover includes a flexible tube portion having flexibility and an inflexible tube portion. The flexible tube portion has a corrugated tubular shape in which concave portions and convex portions both extending in a circumferential direction are alternately formed side by side in an axial direction and in which intervals of the adjacent concave portions or intervals between the adjacent convex portions are partially changed.
US09627098B2	Real-time moving collimators made with X-ray filtering material An apparatus includes an x-ray source operable to generate x-ray beams, a collimator comprising one or more leaves configured to modify the x-ray beams, a motorized system operable to move the one or more leaves of the collimator independently in or out of the x-ray beams, and a controller configured to synchronize operation of the x-ray source and the motorized system, allowing modification of the x-ray beams substantially in real time with generation of the x-ray beams. At least one leaf or each of the leaves of the collimator may be configured to modulate a beam quality of the x-ray beams.
US09627097B2	Systems, methods and apparatus for infusion of radiopharmaceuticals Systems, apparatus and methods are provided through which an injector system automates a process of injecting an individual dose from a multiple dose of a radiotracer material. In some embodiments, the injector system includes a first dose calibrator system that receives a multidose vial of a radiotracer, a second dose calibrator system, an injection pump and an intravenous needle. In some embodiments, the first dose calibrator system and the multidose vial have an integrated shape. In some embodiments, the first dose calibrator system includes a pneumatic arm that receives the multidose vial.
US09627096B2	Semiconductor memory device A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
US09627089B2	Shift register, gate driving circuit, and display device The present invention provides a shift register, a gate driving circuit and a display device. The shift register comprises a precharge and reset module, a pull-up module, a pull-down module and a cut-off module, the cut-off module, the pull-up module and the pull-down module are connected at a first node, and the cut-off module is connected between the first node and the precharge and reset module. In the present invention, the cut-off module is provided to disconnect electric connection between the precharge and reset module and the pull-up module, such that the first node cannot discharge through the precharge and reset module, which effectively avoids internal discharge of the shift register, and further ensures normal output of the signal output from the output terminal of the shift register, and improves stability of the shift register.
US09627088B2	One time programmable non-volatile memory and read sensing method thereof A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.
US09627086B2	Nonvolatile memory device, operating method thereof and memory system including the same A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
US09627085B2	Refresh method for flash memory and related memory controller thereof A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.
US09627082B2	NAND flash memory device Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
US09627080B2	Semiconductor memory device A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
US09627074B2	Method for determining an optimal voltage pulse for programming a flash memory cell A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.
US09627069B1	Semiconductor memory device and operating method thereof A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device.
US09627065B2	Memory equipped with information retrieval function, method for using same, device, and information processing method CPUs are not effective for search processing for information on a memory. Content-addressable memories (CAMs) are effective for information searches, but it is difficult to build a large-capacity memory usable for big data using the CAMs. A large-capacity memory may be turned into an active memory having an information search capability comparable to that of a content-addressable memory (CAM) by incorporating an extremely small, single-bit-based parallel logical operation unit into a common memory. With this memory, a super fast in-memory database capable of fully parallel searches may be realized.
US09627064B2	Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.
US09627061B2	Electronic device having resistance element An electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance variable element interposed between the first electrode and the second electrode, and a conductor arranged at least one of a first side and a second side of the resistance variable element to apply an electric field to the resistance variable element while being spaced apart from the resistance variable element, the first side facing the second side.
US09627058B2	Resistance random access memory with accurate forming procedure, operating method thereof and operating system thereof An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value.
US09627050B2	Memory access module for performing memory access management A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate at least a first digital value of a storage cell, wherein each subsequent sensing operation corresponds to a sensing voltage which is determined according to a result of the previous sensing operation; processing means for using the first digital value to obtain soft information of a bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding.
US09627048B2	Semiconductor memory device which stores plural data in a cell A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
US09627045B1	Superconducting devices with ferromagnetic barrier junctions A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.
US09627044B2	Offset detection There is provided a method of detecting offset in a sense amplifier of an SRAM memory unit. The method comprises using a sense amplifier of the SRAM memory unit to implement a read of a first data value stored in a memory cell of the SRAM memory unit, and measuring a first time for the sense amplifier to read the first data value. The method further comprises using the sense amplifier to implement a read of a second data value stored in a memory cell of the SRAM memory unit, and measuring a second time for the sense amplifier to read the second data value. The method then comprises calculating a difference between the first time and the second time, and determining whether an offset adjustment should be applied to the sense amplifier in dependence upon the difference between the first time and the second time.
US09627040B1	6T static random access memory cell, array and memory thereof A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.
US09627039B2	Apparatus for reducing write minimum supply voltage for memory Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
US09627038B2	Multiport memory cell having improved density area A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.
US09627034B2	Electronic device Provided is an electronic device including a circuit for reading data from a memory cell that can store multilevel data. The electronic device includes a memory cell array region, N sense amplifier regions, and switching elements. The memory cell array region includes memory cells that store, when (N+1)-level data is stored, the (N+1)-level data as different potentials. Each of the N sense amplifier regions compares a read potential, which depends on a charge released to a bit line and a wiring or the like connected thereto, with a reference potential and performs amplification. Each of the switching elements electrically isolates a sense amplifier region from the other sense amplifier regions after all of the N sense amplifier regions are electrically connected to the bit line. Each of the sense amplifier regions can output a write potential to the bit line.
US09627033B2	Sense amplifier and semiconductor device for securing operation margin of sense amplifier A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.
US09627031B1	Control methods and memory systems using the same A control method for a memory system is provided. A memory controller of the memory system is configured to control the memory device. After a condition is met, the memory controller performs a retry operation to compensate for shifting of a data strobe signal sent from the memory device until the memory system enters a normal operation mode. When the shifting of the data strobe signal is compensated for, the number of pulses of the data strobe signal in the gating window is equal to the first predetermined number.
US09627021B2	8-transistor dual-ported static random access memory An 8-transistor SRAM (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines. Prior to each read operation, the differential read bit lines are precharged to the low voltage level. During read operations, one of the two differential read bit lines is pulled high towards a high voltage level while the complementary bit line remains at the low voltage level resulting from the precharge. The difference in voltage between the differential read bit lines is sensed to determine the value stored in each 8-transistor SRAM storage cell and complete the read operation.
US09627020B1	Semiconductor device A semiconductor device may be provided. The semiconductor device may include a reference mat including a reference bit line and a reference word line, the reference mat, located adjacent to a normal mat, and the reference mat configured such that a capacitance of the reference bit line is adjusted based on a signal of the reference word line. The semiconductor device may include a drive controller configured to drive the signal of the reference word line with a drive voltage based on a boosting voltage, the drive voltage having a lower voltage level than the boosting voltage.
US09627017B1	RAM at speed flexible timing and setup control Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.
US09627009B2	Interleaved grouped word lines for three dimensional non-volatile storage A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines.
US09627004B1	Video frame annotation A system and methodology provide for annotating videos with entities and associated probabilities of existence of the entities within video frames. A computer-implemented method selects an entity from a plurality of entities identifying characteristics of a video item, where the video item has associated metadata. The computer-implemented method receives probabilities of existence of the entity in video frames of the video item, and selects a video frame determined to comprise the entity responsive to determining the video frame having a probability of existence of the entity greater than zero. The computer-implemented method determines a scaling factor for the probability of existence of the entity using the metadata of the video item, and determines an adjusted probability of existence of the entity by using the scaling factor to adjust the probability of existence of the entity. The computer-implemented method labels the video frame with the adjusted probability of existence.
US09627000B1	Canary testing for storage devices Embodiments are disclosed for analyzing data storage devices. The present disclosure employs a “canary” test that selects multiple storage devices and tests the same for a predetermined period of time. By analyzing the statuses of the storage devices monitored and recorded during the applicable tests, the present disclosure can generate an analytical result regarding the characteristics of the storage devices. The analytical result can be presented to an operator in a meaningful way so as to enable him or her to make an informed decision when utilizing a storage device with characteristics similar to the tested storage devices.
US09626998B2	Write interference reduction when reading while writing to a hard disk drive media A hard disk drive device and a method and apparatus for control of the hard disk drive is provided. The hard disk drive includes disk media, a slider head, a head gimbal assembly and a control means. The disk media includes at least two layers for data storage. The slider head flies above the disk media and includes a writer and a reader, and a head gimbal assembly supports the slider head above the disk media. The control means is physically coupled to the head gimbal assembly and electrically coupled to the writer and the reader for reducing write interference from the writer when the writer is writing to the disk media while the reader is reading from the disk media, wherein write interference is reduced in one or more of a time domain and a frequency domain.
US09626997B1	Variable spinning rates for hard disk drives Systems and techniques for varying the spindle speed of a hard disk drive are disclosed. In some embodiments, the systems and techniques involve a hard disk drive (HDD) that is accessible to a storage controller. A spin speed of the HDD is set to a full spinning speed, and an amount of time that the HDD is unassigned is compared to a threshold. After detecting that the threshold is exceeded, the spin speed of the HDD is decreased to a reduced spinning speed. Likewise, upon determining that the HDD is assigned, the spin speed of the HDD is increased to the full spinning speed. In various such embodiments, assigning the HDD may include assigning the HDD to a volume group or assigning the HDD operate as an in-use hot spare.
US09626995B2	Disk apparatus, controller, and control method According to one embodiment, there is provided a disk apparatus including a disk medium and a controller. The disk medium has a data area and a servo area. The controller obtains offset amount of a head from a target position along an cross-track direction based on a signal read from the data area by the head and performs first control to cause the head to approach the target position based on the offset amount.
US09626994B2	Usage of state information from state-space based track-follow controller A method according to one embodiment includes generating track following controller state information based on a positional signal of a head relative to a medium. One or more portions of the state information corresponding to particular frequencies are used to determine at least one of: lateral tape movement, tape skew, vibration operation conditions, and roller performance.
US09626990B2	Perpendicular magnetic recording (PMR) writer with hybrid shield layers A perpendicular magnetic recording writer with an all wrap around (AWA) shield design wherein one or more of the leading shield, trailing shield, and side shields comprises a magnetic hot seed layer made of a >19 kG to 24 kG material that adjoins a gap layer, and a side of the hot seed layer opposite the gap layer adjoins a high damping magnetic layer made of a 10-16 kG material (or a 16-19 kG material in the trailing shield) having a Gilbert damping parameter a >0.04. In one embodiment, the high damping magnetic layer is FeNiRe with a Re content of 3 to 15 atomic %. The main pole leading and trailing sides may be tapered. Side shields may have a single taper or dual taper structure. Higher writer speed with greater areal density capability is achieved.
US09626985B2	Audio processing method and apparatus Audio processing methods and apparatus are provided. An audio processing method may include: receiving audio data packets; buffering the audio data packets to a buffer; reading the audio data packets from the buffer and playing the audio data packets; accumulating an actual total playing time length and a total sampling time length of the audio data packets that currently have been read from the buffer and have been played; and suspending reading and playing, when a sum of sampling time lengths of audio data packets that are buffered and unread in the buffer is less than or equal to a first threshold, until a sum of sampling time lengths of the audio data packets in the buffer that are unread is greater than or equal to a current network jitter estimated value.
US09626983B2	Temporal gain adjustment based on high-band signal characteristic The present disclosure provides techniques for adjusting a temporal gain parameter and for adjusting linear prediction coefficients. A value of the temporal gain parameter may be based on a comparison of a synthesized high-band portion of an audio signal to a high-band portion of the audio signal. If a signal characteristic of an upper frequency range of the high-band portion satisfies a first threshold, the temporal gain parameter may be adjusted. A linear prediction (LP) gain may be determined based on an LP gain operation that uses a first value for an LP order. The LP gain may be associated with an energy level of an LP synthesis filter. The LP order may be reduced if the LP gain satisfies a second threshold.
US09626978B2	Bandwidth extension of harmonic audio signal Methods and arrangements in a codec for supporting bandwidth extension, BWE, of an harmonic audio signal. The method in the decoder part of the codec comprises receiving a plurality of gain values associated with a frequency band b and a number of adjacent frequency bands of band b. The method further comprises determining whether a reconstructed corresponding frequency band b′ comprises a spectral peak. When the band b′ comprises a spectral peak, a gain value associated with the band b′ is set to a first value based on the received plurality of gain values; and otherwise the gain value is set to a second value based on the received plurality of gain values. The suggested technology enables bringing gain values into agreement with peak positions in a bandwidth extended frequency region.
US09626976B2	Apparatus and method for encoding/decoding signal An encoding method and apparatus and a decoding method and apparatus are provided. The decoding method includes skipping extension information included in an input bitstream, extracting a three-dimensional (3D) down-mix signal and spatial information from the input bitstream, removing 3D effects from the 3D down-mix signal by performing a 3D rendering operation on the 3D down-mix signal, and generating a multi-channel signal using a down-mix signal obtained by the removal and the spatial information. Accordingly, it is possible to efficiently encode multi-channel signals with 3D effects and to adaptively restore and reproduce audio signals with optimum sound quality according to the characteristics of an audio reproduction environment.
US09626971B2	Speaker recognition Method for text-dependent Speaker Recognition using a speaker adapted Universal Background Model, wherein the speaker adapted Universal Background Model is a speaker adapted Hidden Markov Model comprising channel correction.
US09626969B2	Systems and methods for improving the accuracy of a transcription using auxiliary data such as personal data A method is described for improving the accuracy of a transcription generated by an automatic speech recognition (ASR) engine. A personal vocabulary is maintained that includes replacement words. The replacement words in the personal vocabulary are obtained from personal data associated with a user. A transcription is received of an audio recording. The transcription is generated by an ASR engine using an ASR vocabulary and includes a transcribed word that represents a spoken word in the audio recording. Data is received that is associated with the transcribed word. A replacement word from the personal vocabulary is identified, which is used to re-score the transcription and replace the transcribed word.
US09626964B2	Voice recognition terminal, server, method of controlling server, voice recognition system, non-transitory storage medium storing program for controlling voice recognition terminal, and non-transitory storage medium storing program for controlling server A voice recognition terminal is provided to be able to communicate with a server capable of voice recognition for recognizing voice, and includes a voice input acceptance portion accepting voice input from a user, a voice recognition portion carrying out voice recognition of the voice input accepted, a response processing execution portion performing processing for responding to the user based on a result of voice recognition of the voice input accepted, and a communication portion transmitting the voice input accepted by the voice input acceptance portion to the server and receiving a result of voice recognition in the server. The response processing execution portion performs the processing for responding to the user based on the result of voice recognition determined as more suitable, of the result of voice recognition by the voice recognition portion and the result of voice recognition received from the server.
US09626963B2	System and method of improving speech recognition using context A system and method are provided for improving speech recognition accuracy. Contextual information about user speech may be received, and then speech recognition analysis can be performed on the user speech using the contextual information. This allows the system and method to improve accuracy when performing tasks like searching and navigating using speech recognition.
US09626962B2	Method and apparatus for recognizing speech, and method and apparatus for generating noise-speech recognition model An apparatus and method for recognizing a speech, and an apparatus and method for generating a noise-speech recognition model are provided. The speech recognition apparatus includes a location determiner configured to determine a location of the apparatus, a noise model generator configured to generate a noise model corresponding to the location by collecting noise data related to the location, and a noise model transmitter configured to transmit the noise model to a server.
US09626958B2	Speech retrieval method, speech retrieval apparatus, and program for speech retrieval apparatus A method for speech retrieval includes acquiring a keyword designated by a character string, and a phoneme string or a syllable string, detecting one or more coinciding segments by comparing a character string that is a recognition result of word speech recognition with words as recognition units performed for speech data to be retrieved and the character string of the keyword, calculating an evaluation value of each of the one or more segments by using the phoneme string or the syllable string of the keyword to evaluate a phoneme string or a syllable string that is recognized in each of the detected one or more segments and that is a recognition result of phoneme speech recognition with phonemes or syllables as recognition units performed for the speech data, and outputting a segment in which the calculated evaluation value exceeds a predetermined threshold.
US09626957B2	Speech retrieval method, speech retrieval apparatus, and program for speech retrieval apparatus A method for speech retrieval includes acquiring a keyword designated by a character string, and a phoneme string or a syllable string, detecting one or more coinciding segments by comparing a character string that is a recognition result of word speech recognition with words as recognition units performed for speech data to be retrieved and the character string of the keyword, calculating an evaluation value of each of the one or more segments by using the phoneme string or the syllable string of the keyword to evaluate a phoneme string or a syllable string that is recognized in each of the detected one or more segments and that is a recognition result of phoneme speech recognition with phonemes or syllables as recognition units performed for the speech data, and outputting a segment in which the calculated evaluation value exceeds a predetermined threshold.
US09626954B2	Active vibration/noise control apparatus A control signal filter 2 receives a sound source signal determined by a control frequency specified in conformity with the vibration/noise source that produces vibration/noise, and outputs a control signal. A filter coefficient update unit 4 updates coefficients of the control signal filter 2 in response to a sound source signal and an error signal. A signal-to-interference ratio measuring unit 5 outputs a signal-to-interference ratio determined from the vibration/noise and the interference contained in the error signal in response to the control frequency and error signal. An update controller 6 adjusts an update step of the filter coefficient update unit 4 in accordance with the signal-to-interference ratio.
US09626947B1	Fret scanners and pickups for stringed instruments Techniques are described that relate to various aspects of converting the mechanical energy of instrument strings to digital representations for use in a variety of applications.
US09626939B1	Viewer tracking image display Image information displayed on an electronic device can be adjusted based at least in part upon a relative position of a viewer with respect to a device. In some embodiments, image stabilization can be provided such that an image remains substantially consistent from the point of view of the viewer, not the display element of the device. The image can be stretched, rotated, compressed, or otherwise manipulated based at least in part upon the relative viewing position. Similarly, the viewer can move relative to the device to obtain different views, but views that are consistent with the viewer looking at an object, for example, through a piece of glass. The device can overlay information on the image that will adjust with the adjusted image. Three-dimensional modeling and display can be used to offset parallax and focus point effects.
US09626937B2	Driving method and driving system for display panel The invention provides a driving method and a driving system for a display panel. The driving method comprises: partitioning the display panel into N display sub-areas, each of which is used for displaying the 1/N sub-picture of the whole frame of picture to be displayed and correspondingly controlled by one timing controller, wherein N≧2 and N is an integer, and the data signal of the whole frame of picture to be displayed is allocated to each of the timing controllers. According to the driving method and the driving system, by allocating the data signal of the whole frame of picture to be displayed to each of timing controllers, the backlight brightness provided by the different backlight sub-areas is the same, and then a joint or boundary phenomenon occurring among the different backlight sub-areas is avoided.
US09626935B2	Stereoscopic image display device and method for driving the same Embodiment relate to a display panel that modulates 3D image data based on pixel data of adjacent lines. The display panel includes data lines, gate lines, and a plurality of pixels; a data modulation unit. The modulation unit modulates kth pixel data of a jth line in 3D image data based on the kth pixel data of the jth line and kth pixel data of a line adjacent to the jth line. The data driving circuit converts the modulated 3D image data into analog data voltages and outputs the analog data voltages to the data lines. A gate driving circuit sequentially outputs gate pulses to the gate lines.
US09626930B2	Display device A display device includes: a first display panel including: a display area including a first edge, a second edge and a third edge, where the first and second edges are disposed opposite to each other, and the third edge is connected to the first and second edges, a peripheral area around the display area, and a plurality of pixels disposed in the display area; a first common voltage transmitting line extending along the third edge, where the first common voltage transmitting line transmits a first common voltage to the display area through a plurality of input points sequentially disposed along the third edge; and a second common voltage transmitting line extending along the third edge, where the second common voltage transmitting line transmits a second common voltage to the display area through a supplementary input point, which is adjacent to the second edge or the third edge.
US09626924B2	Display auxiliary device, display system, display method, and program medium A display auxiliary device includes a light receiving sensor that receives display light from a display target, and a CPU that determines whether or not a switching display synchronous signal is included in the received display light, shields both a left-eye liquid crystal shutter and a right-eye liquid crystal shutter during a light reception period of time of the switching display synchronous signal based on the switching display synchronous signal, and performs a shutter switching operation of the left-eye liquid crystal shutter for the left-eye image and the right-eye liquid crystal shutter for the right-eye image to be switched and displayed, when the switching display synchronous signal is determined to be included.
US09626922B2	GOA circuit, array substrate, display device and driving method There are provided a GOA circuit, an array substrate, a display device and a driving method. The GOA circuit includes clock signal input lines and more than two GOA units connected in cascade, wherein each of the GOA units includes a selection signal output sub-unit and a selection sub-unit; the selection signal output sub-unit is configured to receive a source signal, and output a selection signal in accordance with the source signal; the selection sub-unit receives the selection signal and N clock signals, and outputs the received signal in accordance with the selection signal; and the clock signal input lines are no less than a number of N, and are configured to input the clock signals to the selection sub-unit, where N is an integer number which is higher than or equal to two. The gate driving structure of the GOA circuit, the array substrate and the display device occupies a small area. The driving method can achieve a single dot polarity inversion.
US09626920B2	Liquid crystal display device and method for driving same In a liquid crystal display device for performing pause driving, occurrence of flicker is effectively suppressed while an increase in power consumption is suppressed.When a frame in which an image signal (DAT) is inputted from an external portion without output of a request signal (RO) for requesting the external portion to input the image signal (DAT) is defined as a first input frame, a reversal driving control portion (10) sets the reversal driving technique in the first input frame to the column-reversal driving while setting the first input frame to a refresh frame defined as a first refresh frame, sets three frames subsequent to the first refresh frame to pause frames, sets a frame subsequent to the final pause frame to a refresh frame defined as a second refresh frame, and sets the reversal driving technique in the second refresh frame to the dot-reversal driving.
US09626919B2	Display method and display device applied to MVA wide viewing angle liquid crystal screen According to the method provided by some embodiments of the present disclosure, under different gray-scale voltages, the liquid crystal deflection directions of liquid crystal molecules are different, such that when a first frame is displayed, the deflection difference between the deflection direction of the liquid crystal molecules in the pixel structure in the liquid crystal display screen and the deflection direction when a second frame is displayed is increased, after human eyes view the displayed first frame and second frame, an image obtained after the first frame and the second frame are displayed may be observed at different viewing angles, and at this time, the viewing angle of the liquid crystal display screen is increased on the premise of not increasing the number of sub-domains in the pixel structure of the liquid crystal display screen.
US09626917B2	Image display apparatus, driving method of image display apparatus, signal generation apparatus, signal generation program, and signal generation method An image signal for red color display, an image signal for green color display, and an image signal for blue color display which correspond to a pixel are denoted as reference symbol RnL, reference symbol GnL, reference symbol BnL, respectively, a minimum value thereof is denoted as MinRGBnL, and a threshold defined as a predetermined value is denoted as reference symbol TH1. In a case, where MinRGBnL≦TH1 holds: the value of the signal for the white color sub-pixel is MinRGBnL/TH1, the value of the signal for the red color sub-pixel is RnL−MinRGBnL, the value of the signal for the green color sub-pixel is GnL−MinRGBnL, and the value of the signal for the blue color sub-pixel is BnL−MinRGBnL. In a case, where MinRGBnL>TH1 holds: the value of the signal for the white color sub-pixel is 1, the value of the signal for the red color sub-pixel is (RnL−TH1)/(1−TH1), the value of the signal for the green color sub-pixel is (GnL−TH1)/(1−TH1), and the value of the signal for the blue color sub-pixel is (BnL−TH1)/(1−TH1).
US09626907B2	Driving circuit and organic light emitting display apparatus There are disclosed a driving circuit of an organic light emitting display panel and an organic light emitting display apparatus. The driving circuit comprises: a power supply detection circuit configured to detect an operating state of an external input power supply, send a normal signal of power supply detection when it is determined that the external input power supply is in a normal state, and send a abnormal signal of power supply detection when it is determined that the external input power supply is in an abnormal state; a clock control circuit configured to convert a received video data into image data recognizable by the organic light emitting display panel and then output it to the organic light emitting display panel when the normal signal of power supply detection sent by the power supply detection circuit is received, and output image data of black picture to the organic light emitting display panel when the abnormal signal power supply detection sent by the power supply detection circuit is received. In this way, pixel charges accumulated on respective display pixels can be released, which avoids transistors inside the display pixels from producing stress, and finally avoids occurrence of shutdown image sticking due to power-down.
US09626906B2	Organic light emitting device Disclosed is an organic light emitting display in which a sensing period during which the source voltage of the driving TFT is raised toward a data voltage applied to a gate electrode of the driving TFT in order to compensate a change in mobility of the driving TFT, a first gate signal is maintained at an ON level and a second gate signal is maintained at an OFF level, and the first and second gate signals are maintained at an OFF level in a light emission period following the sensing period; and a first falling time of the first gate signal and a second falling time of the second gate signal, which indicate a period of time required to change from the ON level to the OFF level, are set to be longer than a predetermined reference value, respectively.
US09626904B2	Display device, electronic device, and driving method of display device Provided is a display device including a driving transistor, a switching unit, and a control unit. The driving transistor includes a control terminal, a first terminal, and a second terminal, and controls supply of current to a light emitting element, which is connected to the first terminal and emits light in accordance with the current amount, in accordance with a signal voltage applied to the control terminal. The switching unit can switch a conduction and non-conduction state, and, by being brought in the conduction state, forms a path that bypasses the light emitting element so that the current is not supplied to the light emitting element. The control unit performs control so that the switching unit is brought in the non-conduction state after the signal voltage is written into the control terminal, and controls a potential of the control terminal in synchronization with the control of the switching unit.
US09626902B2	Light emission driver for display device, display device and driving method thereof A light emission driver for a display device is disclosed. In one aspect, the driver includes a first node to which first and second light emitting power source voltages are applied according to respective clock signals. The driver also includes a second node to which the first and third light emitting power source voltages are applied according to the respective clock signals. The driver further includes first and second transistors respectively turned on by the first and second nodes and respectively transmitting the second and first light emitting power source voltages to a light emitting signal output terminal, respectively.
US09626901B2	Display device Discloses is a display device that may include a display panel; sub-pixels in a display area of the display panel; upper and lower data lines separated in a central portion of the display area; and an electrostatic discharge circuit formed in the central portion of the display area, the electrostatic discharge circuit electrically connected to the upper and lower data lines.
US09626900B2	Electro-optical device An electro-optical device includes first and second signal lines that extend in directions for intersecting each other on a component substrate, a pixel area in which a pixel electrode is disposed in correspondence with an intersection of the first and second signal lines, a signal output circuit that is disposed outside the pixel area and outputs a driving signal to the first signal line, and a connection wiring that connects the signal output circuit and the first signal line together. An outer peripheral edge of the pixel area has a curved portion or a bent portion in a portion facing the signal output circuit, and the signal output circuit includes a plurality of circuit blocks, and the circuit blocks are arranged along the curved portion or the bent portion of the portion facing the signal output circuit with deviated between adjacent circuit blocks in the direction of extension of the first signal line and/or the direction of extension of the second signal line.
US09626895B2	Gate driving circuit A gate driving circuit is provided. The gate driving circuit includes a plurality of gate driving units sequentially coupled to each other. Each of the gate driving units includes a shift register and a de-multiplexer. The shift register receives a start pulse signal, and generates a first control signal and a second control signal according to the start pulse signal and a scan controlling signal, where when the shift register converts the first control signal into the second control signal, the shift register pulls down a voltage level of the first control signal according to the second control signal. The de-multiplexer receives a part of a plurality of clock signals for generating a plurality of gate signals sequentially according to the first control signal, where the clock signals are enabled sequentially, and enable periods of two sequential clock signals are partially overlapped with each other.
US09626892B2	Optimization method and system of real-time LCD white balance selection An optimization system of real-time LCD white balance selection includes an RGB to YUV conversion unit, a white balance adjustment unit, and a YUV to RGB conversion unit. The RGB to YUV conversion unit receives an image signal and converts the image signal from RGB domain to YUV domain to generate a first YUV image signal. The white balance adjustment unit is connected to the RGB to YUV conversion unit for performing a white balance adjustment on the first YUV image signal and thus generating a second YUV image signal. The YUV to RGB conversion unit is connected to the white balance adjustment unit for converting the second YUV image signal from YUV domain to RGB domain.
US09626882B2	Color-changing sealant A sealing element that utilizes cohesive peeling to visually indicate when a sealing element has been opened. The peel layer and bulk layer can be coupled together and contain coloring agents which are complementary colors that together make up a secondary color. Alternatively, the peel layer can be coupled to a first bulk layer and the first bulk layer coupled to a second bulk layer. The colors of the coloring agents applied to the peel layer and first bulk layer together do not make up a secondary color, and the colors of the coloring agents of the second bulk layer and the first bulk layer together do not make up a secondary color.
US09626879B2	Dynamic operator behavior analyzer Dynamic industrial vehicle monitoring for modification of vehicle operator behavior comprises identifying a metric that characterizes an event associated with the operation of an industrial vehicle, the metric having at least one behavior modification action and at least one performance parameter to evaluate the event against. Monitoring operation of the industrial vehicle is carried out for the event. Upon detecting an occurrence of the event, event data is recorded that characterizes a response of a vehicle operator to the event. The recorded event data is evaluated against at least one performance parameter associated with the corresponding metric to determine whether the vehicle operator demonstrated appropriate behavior for the event. A vehicle operator score is updated based upon the evaluation and the updated vehicle operator score is communicated.
US09626877B2	Mixing a video track with variable tempo music The teachings described herein are generally directed to a system, method, and apparatus for separating and mixing tracks within music. The system can have a video that is synchronized with the variations in the musical tempo through a variable timing reference track designed and provided for a user of the preselected piece of music that was prerecorded, wherein the designing of the variable timing reference track includes creating a tempo map having variable tempos, rhythms, and beats using notes from the preselected piece of music.
US09626875B2	System, device, and method of adaptive teaching and learning Device, system, and method of adaptive teaching and learning. A computerized method includes operations performed in order to dynamically group and re-group students based on their monitored progress of interacting with digital educational learning objects; performing dynamic layout of components and elements of a digital learning object by taking into account pedagogic goals, pedagogic priorities or pedagogic significance or elements; allowing a teacher to define differential stop-lines for different groups of students; allowing a teacher to command that all student devices temporarily present a uniform learning object; allowing a content publisher to receive aggregated feedback based on monitored progress; and allowing a content publisher to package the objects as portable stand-alone playback modules.
US09626874B1	Systems and methods for managing restricted areas for unmanned autonomous vehicles Methods, systems, and devices for providing data from a server to a UAV enable the UAV to navigate with respect to areas of restricted air space (“restricted areas”). A server may receive from a UAV, a request for restricted area information based on a position of the UAV. The server may determine boundaries of a surrounding area containing the position of the UAV and a number of restricted areas. The server may transmit coordinate information to the UAV defining the restricted areas contained within the surrounding area.
US09626873B2	Method, system and computer program for providing, on a human-machine interface, data relating to an aspect of the operation of an aircraft A method, system and computer program for providing, on a human-machine interface, data relating to an aspect of the operation of an aircraft and grouped into one and the same area of the interface, the method comprising the following steps. A step of detecting a request to display an aspect of the operation of the aircraft. The method also includes a step of computing a flight situation and generating a consolidated aeroplane situation. A step of associating the elementary data linked to the consolidated aeroplane situation to extract therefrom updated situational data. The method then includes a step of grouping the updated situational data into a plurality of sub-sets to allow display of the data in the display area. Finally the method includes a step of displaying, in the display area, the sub-sets of data.
US09626872B2	Enhanced flight crew display for supporting multiple controller/pilot data link communications (CPDLC) versions An avionics system comprising a human machine interface configured to display a user interface and a control device is provided. The control device coupled to the human machine interface, wherein the control device is configured to send and receive controller/pilot data link communications (CPDLC) messages and adjust the user interface based on a first CPDLC version of an established first CPDLC session.
US09626862B2	Methods and systems for operating a logical sensor network Methods and systems for operating a sensor network comprising a plurality of nodes and at least one resource, where a resource can be a sensing device (e.g., a camera or microphone) or other peripheral devices (e.g., a storage or recording system). In at least one embodiment of the present invention, at least one node in a network determines at least one resource available to it and the type of the resource or its capabilities. Based on the type or capabilities of the resource, the node associates with one or more logical node names and acquires instructions for performing at least one function.
US09626861B2	Wireless device and wireless control system A wireless device 101 is a wireless device having identification information, and includes: an operation unit 11; a power generating unit 12 that generates electric power by operation on the operation unit 11; a signal generating unit 13 that operates by using the electric power generated by the power generating unit 12 and is capable of outputting a signal of a kind corresponding to the content of each operation on the operation unit 11; a storage unit 15 that operates by using the electric power generated by the power generating unit 12 and nonvolatilely stores the content of an output signal of the signal generating unit 13, the identification information, and reference information; and a transmission control unit 14 that compares the content of the output signal with the reference information when the operation on the operation unit 11 satisfies a predetermined condition, the content of the output signal and the reference information being stored in the storage unit 15, and transits to a transmission permission state in which transmitting a wireless signal including the identification information stored in the storage unit 15 to a different device is permitted when a result of the comparison satisfies a predetermined condition.
US09626856B2	Detecting presence using a presence sensor network Concepts and technologies are disclosed herein for detecting presence using a presence sensor network. In some embodiments, a computer executing a presence service generates a user interface for display at a user device. The user interface can include a control that, when selected, generates room data defining a monitored location. The computer can obtain sensor identifier data that identifies a presence sensor located at the monitored location and a location of the presence sensor at the monitored location. The computer can provide the user interface to the user device to obtain the room data and obtain the room data. The computer also can store the room data and the sensor identifier data.
US09626855B2	Systems and methods for beacon tethering in a monitoring system Various embodiments of the present inventions are related to monitoring physical location of a monitored target, but not limited to, use of beacon location information.
US09626849B2	Using scene information from a security camera to reduce false security alerts A process reduces false positive security alerts. The process is performed at a computing device having one or more processors, and memory storing one or more programs configured for execution by the one or more processors. The process computes a depth map for a scene monitored by a video camera using a plurality of IR images captured by the video camera and uses the depth map to identify a first region within the scene having historically above average false positive detected motion events. In some instances, the first region is a ceiling, a window, or a television. The process monitors a video stream provided by the video camera to identify motion events, excluding the first region, and generates a motion alert when there is detected motion in the scene outside of the first region and the detected motion satisfies threshold criteria.
US09626846B2	Evacuation slide with a lighting system for illuminating an escape route An evacuation slide comprises a sliding face having a top end portion adapted to be positioned adjacent to an exit of a region to be evacuated, and a bottom end portion adapted to be positioned adjacent to an escape route leading away from the region to be evacuated and being arranged at a lower height than the region to be evacuated. A light signal generating device is adapted to irradiate at least one light beam onto the escape route which extends further in a direction parallel to a center line of the escape route than in a direction perpendicular to the center line of the escape route so as to indicate a predefined evacuation direction along the escape route.
US09626842B1	Accessorized doorbell device The accessorized doorbell device has a device control in wireless communication with an actuator, such as a doorbell. Chosen music and other informational playback upon an actuator's enablement plays from a plethora of music and other choices stored within and available to the device. A plurality of wireless playback units is provided such that chosen playback is selectively heard throughout or in an isolated area in an abode. A plurality of control buttons, a monitor, and a speaker provide discriminating input from the device control.
US09626840B2	Electronic gaming device with smart wild functionality Examples disclosed herein relate to an electronic gaming device including a memory, a processor, and a plurality of reels. The electronic gaming device may include a plurality of reels. The plurality of reels may include one or more areas. The memory may include one or more smart wild feature structures. The processor may generate one or more symbols to be located in the one or more areas. The processor may move a first smart wild to a first replacement location based on the first replacement location having a top award amount.
US09626839B2	Gaming system and method providing an additional award opportunity when a designated quantity of displayed symbols is associated with a displayed background Various embodiments of the present disclosure provide a gaming system and method providing an additional award opportunity when a designated quantity of displayed symbols is associated with a displayed background. For a play of a game, the gaming system displays one of a plurality of different backgrounds and a plurality of a plurality of different symbols on, over, or otherwise in addition to the displayed background. The gaming system determines and provides any awards associated with the displayed symbols. If a designated quantity of at least one of the displayed symbols is associated with the displayed background, the gaming system provides an additional award opportunity.
US09626832B2	Virtualized magnetic player card A method of implementing a player tracking system in a gaming network includes receiving a virtual player tracking card identifier and a virtual player tracking card password, authenticating the identifier and the password; receiving a virtual player tracking card PIN, identifying a gaming machine that transmitted the virtual player tracking card PIN, and crediting an account associated with the virtual player tracking card PIN based on game play on the gaming machine.
US09626830B2	Reserve credits for use on gaming device Embodiments of the present invention are directed to methods and apparatus in which a player plays one of a plurality of networked gaming devices. Game awards below a predefined level are tracked and stored on the network. If the game awards are less than a predefined criterion, a pay command is sent over the network to the player's gaming device, which may be used for a free game. Implementation in a single gaming device is also disclosed.
US09626829B2	Data processing device and method for interaction detection The current invention discloses devices and methods that may be used for detection and verification of interactions, such as collisions, between objects in application programs, such as online games. After receiving interaction information from a first terminal, a server may send the interaction information to another terminal for verification based on the first terminal's credit rating. When the credit rating is high, the server may broadcast the interaction information before the verification process, which may be conducted randomly. On the other hand, when the credit rating is low, the server may wait for the verification results from the other terminal and only broadcast the interaction information when the information is confirmed. Such an approach optimizes the interaction verification process, reduces security risk, and saves computing resources.
US09626827B2	Gaming device with a secure interface A system for an electronic gambling device output has been developed. The system includes, a first computing device with slot machine game logic circuitry that generates an output signal that is content tested and approved by a gaming regulatory authority for output by the slot machine. It also includes a second computing device that is external to the slot machine. This device controls the tested output content and output content that has not been tested by the gaming regulatory authority. The untested output content replaces or supplements the tested output content.
US09626815B2	Method for unlocking electronic device, and apparatus therefor A method for unlocking an electronic device and an apparatus therefor are provided. The method includes the following steps: when an electronic device is in a function locked state, acquiring unlock trigger information generated by at least one operation in an operation area of the electronic device, where the unlock trigger information includes duration information of each operation of the at least one operation; and unlocking the function locked of the electronic device when the unlock trigger information matches preset unlock information. Concealment when a user unlocks function locked of an electronic device can be improved, so that security of data in the electronic device can be improved.
US09626809B1	Resolving graphical conflicts between objects A request is received to assign a first graphical asset and a second graphical asset associated with a three-dimensional (3D) geometry of a simulated character of a video game to the same physical location on the 3D geometry. A graphical conflict between the first graphical asset and the second graphical asset is detected, where the graphical conflict indicates that at least a portion of the first graphical asset and at least a portion of the second graphical asset graphically overlap at the same physical location on the 3D geometry. Attributes of the first and second graphical assets at the same physical location on the 3D geometry are compared. One of the first graphical asset or the second graphical asset is then provided for display at the physical location on the 3D geometry.
US09626805B2	Interactive mixed reality system and uses thereof An interactive mixed reality simulator is provided that includes a virtual 3D model of internal or hidden features of an object; a physical model or object being interacted with; and a tracked instrument used to interact with the physical object. The tracked instrument can be used to simulate or visualize interactions with internal features of the physical object represented by the physical model. In certain embodiments, one or more of the internal features can be present in the physical model. In another embodiment, some internal features do not have a physical presence within the physical model.
US09626798B2	System and method to digitally replace objects in images or video A method includes receiving video data and identifying a second object in at least one video frame of the video data. The method also includes determining whether to replace the second object in the at least one video frame with a first object based on at least one object matching rule. In response to determining that the second object is to be replaced with the first object, the method includes manipulating the three-dimensional model of the first object to generate a representation of the first object that matches at least one visual property of the second object and replacing the second object with the representation of the first object in the at least one video frame.
US09626796B2	Method to optimize the visualization of a map's projection based on data and tasks A method and system for generating a map using a computer is based on data and weighted factors to minimize corresponding projection distortions. The method and system includes determining visualization goals from analyzing a set of datasets for a map using the computer. A set of visualization characteristics are calculated for each dataset based on the visualization goals using the computer. The visualization characteristics are analyzed to weight factors for each of the datasets. Each of the weighted factors is adjusted based on the relevance of each of the datasets for visualization of the map. An aggregate vector of weighted factors is calculated based on all of the datasets, and the map for visualization is generated based on the aggregate vector of weighted factors.
US09626795B2	Reducing shading by merging fragments from the adjacent primitives Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2×2 block of pixels are possible.
US09626793B2	Variable depth compression In accordance with some embodiments, the number of bits allocated to depth compression may be changed variably based on a number of considerations. As a result, depth data may be compressed in a more efficient way.
US09626792B2	Rendering an infinite plane A machine may render a view that includes a portion of an infinite plane within a three-dimensional (3D) space. The machine may determine a polygon within a frustum in the 3D space. The polygon may be determined by calculating an intersection of the frustum with the infinite plane. The polygon may represent that portion of the infinite plane which lies within the boundaries of the frustum. The machine may then determine a color of an element of this polygon according to one or more algorithms, default values, or other programming for depicting the infinite plane within the 3D space. The color of this element of the polygon may be that applied by the machine to a further element that is located on the far plane of the frustum, and this further element may be located at a height above the polygon within the 3D space.
US09626790B1	View-dependent textures for interactive geographic information system Systems and methods for rendering a view-dependent texture in conjunction with a polygon mesh to provide a textured three-dimensional model of a geographic area are provided. The view-dependent texture can be optimized for viewing the three-dimensional model from a single reference direction. When a user navigates to a camera viewpoint of the three-dimensional model associated with the single reference direction, the view-dependent texture can be rendered in conjunction with the three-dimensional model to provide a more realistic representation of the geographic area to the user. When a user navigates to a camera viewpoint of the three-dimensional model that is not associated with the single reference direction, a base texture can be rendered in conjunction with the three-dimensional model. The base texture can be optimized based on viewing the three-dimensional model from a plurality of differing viewpoints.
US09626786B1	Virtual-scene control device A handheld device includes: an input control configured to control and modify a virtual scene including a virtual camera; and a display that shows a representation of the controlled and modified virtual scene generated by the virtual camera. A system includes: a computer system configured to execute program instructions for generating a virtual scene including a virtual camera; and handheld device configured to communicate with the computer system for controlling and modifying the virtual scene, the handheld device comprising: an input control configured to control and modify the virtual scene; and a display that shows a representation of the controlled and modified virtual scene generated by the virtual camera.
US09626784B2	Image display system, display device, and image processing method According to an embodiment, an image display system includes a first generator and a second generator. The first generator generates a first image which includes first text data representing at least a portion of text data and which is displayed by a first display device of stationary type. The second generator generates a second image which includes second text data representing at least a portion of the first text data and which is displayed by a second display device that is worn by a first user.
US09626783B2	Helmet-used device capable of automatically adjusting positions of displayed information and helmet thereof A helmet-used device capable to automatically adjusting positions of displayed information and a helmet thereof. The device includes an angle detection unit, an eyeball detection unit, a processing unit and a projector unit. The processing unit serves to receive a first detection signal to correct an image signal and receive a second detection signal to adjust output positions of multiple graphic and text data of the image signal. The projector unit serves to receive the image signal to generate and project an image. The graphic and text information contained in the projected image is automatically adjusted to a visible position corresponding to the eyes of the wearer for the wearer to conveniently watch the displayed information.
US09626782B2	Image processing apparatus, image processing method and computer-readable storage medium This invention can develop a part of RAW image data and display the developed part of RAW image data with a result of processing, even if the part of the RAW image data refers to other part of the RAW image data.An image processing apparatus obtains an output area of RAW image data to be displayed on a window and a reference area of RAW image data to be pasted to the output area of the RAW image data. The apparatus develops the output area of the RAW image data and the reference area of the RAW image data. Then, the apparatus pastes a development result of the reference area of the RAW image data on a development result of the output area of the RAW image data. After that, the apparatus executes display processing to the development result of the output area of the RAW image data.
US09626779B1	Efficient back-projection operation using precomputed table A method and system are provided. The method includes pre-computing, by a computing device having a processor, a plurality of coefficients for a given two-dimensional point on which a voxel of a three-dimensional object is projected, based on integer parts of coordinates of surrounding two-dimensional points with respect to the given two-dimensional point. The plurality of coefficients lack inclusion of the coordinates. The method further includes storing, by a non-transitory storage device, the plurality of coefficients. The method additionally includes computing, by the computing device during a back-projection operation that forms a reconstructed three-dimensional image, an intensity value at the given two-dimensional point. The computing device computes the intensity value by reading the plurality of coefficients from the non-transitory storage device and combining the plurality of coefficients with the coordinates.
US09626771B2	Image-based analysis of a geological thin section Techniques for an image-based analysis of a geological thin section include (i) acquiring a plurality of images from a geological thin section of a rock sample from a subterranean zone; (ii) manipulating the plurality of images to derive a composite image; (iii) optimizing the composite image to derive a seed image; (iv) identifying, in the seed image, a particular seed pixel of a plurality of contiguous pixels that comprise an image of a grain of a plurality of grains of the rock sample in the seed image; (v) determining, with a specified algorithm, a shape of the grain based on the seed pixel; (vi) determining, based on the shape of the grain, a size of the grain; and (vii) preparing the determination of the size of the grain for presentation to a user.
US09626769B2	Digital video encoder system, method, and non-transitory computer-readable medium for tracking object regions A video compression framework based on parametric object and background compression is proposed. At the encoder, an object is detected and frames are segmented into regions corresponding to the foreground object and the background. The encoder generates object motion and appearance parameters. The motion or warping parameters may include at least two parameters for object translation; two parameters for object scaling in two primary axes and one object orientation parameter indicating a rotation of the object. Particle filtering may be employed to generate the object motion parameters. The proposed methodology is the formalization of the concept and usability for perceptual quality scalability layer for Region(s) of Interest. A coded video sequence format is proposed which aims at “network friendly” video representation supporting appearance and generalized motion of object(s).
US09626761B2	Sampling method and image processing apparatus of CS-RANSAC for estimating homography Disclosed is a sampling method for estimating a homography matrix. This sampling method, for estimating a homography matrix that represents conversion correlations between pluralities of images by means of Constraint Satisfaction-Random Sample Consensus (CS-RANSAC), includes the steps of: sampling to divide an input image into a form of grids (N by N), select features, which are used for calculating a homography matrix, from features, which are abstracted from the input image, by means of a random sampling, and inspect whether the features selected by the random sampling satisfy predefined constraints; and executing model estimation to calculate the homography matrix from the features only if the selected features satisfy the constraints.
US09626759B2	Method for the automatic recognition of anatomical structures in images obtained by positron emission tomography, system and computer program for performing said method A method is described for automatic recognition of anatomical structures in images obtained by position emission tomography, comprising the steps of: acquiring a 3D matrix of standardized uptake values, SUVs, associated with a plurality of PET pixels in an anatomic volume of patient; calculating the Jacobian matrix of the matrix of standardized uptake values, SUVs, projections, in a predetermined anatomical direction, of the matrix of standardized uptake values, SUVs, or of its Jacobian matrix on an anatomic reference plane; locating a two-dimensional minimum of the matrix of standardized uptake values, SUVs, or of its Jacobian matrix, projected on the anatomic reference plane; locating a one-dimensional minimum in the anatomic direction of projection, corresponding to the coordinates of the two-dimensional minimum located on the reference anatomic plane of projection; and determining a center of gravity of the anatomical structure according to the coordinates of said two-dimensional and one-dimensional minima.
US09626752B2	Method and apparatus for IC 3D lead inspection having color shadowing A system for three-dimensional inspection of leads mounted on an integrated circuit device includes an integrated circuit device, a first light source having a first color, a second light source having a second color different from the first color, a RGB color camera and a processor. The first light source is disposed at an acute angle to the integrated circuit device, and is configured to illuminate the leads such that lead shadows are created in a first color plane. The second light source is disposed in front of a surface of the integrated circuit device on which the leads are mounted, and is configured to illuminate the leads in a second color plane. The camera is configured to image the illuminated leads and lead shadows. The processor is configured to analyze the first and second color planes of a single image to detect three-dimensional bent leads.
US09626749B2	Sub-pixel modification of digital images by locally shifting to an arbitrarily dense supergrid Methods and systems may provide for receiving an input image having an input pixel density and defining a single filter based on a sub-pixel modification value, wherein the single filter has a working lattice density that is greater than the input pixel density. Additionally, the single filter and the input image may be used to generate an output image. In one example, defining the single filter includes converting the input pixel density to the working lattice density at an aperture level of the single filter.
US09626747B2	Image enhancement and repair using sample data from other images A image manipulation technique allows a user to correct an image using samples obtained from other images. These samples may be obtained from one or more other images in a library of images. Matching techniques may identify an image that best matches the image to be corrected, or may aggregate or average multiple images that are identified as containing an area corresponding to the area to be corrected. Identification of the image or images to use as the source of the samples may be automatic or manual. The images may be from a library of images under the control of the user or from a library of images maintained by another person or service provider. Application of the samples to correct the image may be manually or automatically directed.
US09626745B2	Temporal multi-band noise reduction Systems, methods, and computer readable media to fuse digital images are described. In general, techniques are disclosed that use multi-band noise reduction techniques to represent input and reference images as pyramids. Once decomposed in this manner, images may be fused using novel low-level (noise dependent) similarity measures. In some implementations similarity measures may be based on intra-level comparisons between reference and input images. In other implementations, similarity measures may be based on inter-level comparisons. In still other implementations, mid-level semantic features such as black-level may be used to inform the similarity measure. In yet other implementations, high-level semantic features such as color or a specified type of region (e.g., moving, stationary, or having a face or other specified shape) may be used to inform the similarity measure.
US09626741B2	Systems and methods for configuring the display magnification of an electronic device based on distance and user presbyopia Systems and methods dynamically configure a display (104) of an electronic device (102) to a desired display resolution and/or a magnification factor without noticeable impact on the user viewing experience. According to certain aspects, the distance between a user (100) and the display is measured (1002), and the desired display resolution is determined (1006) based on the distance. If a user is exhibiting (1008, 1010) symptoms of presbyopia, a magnification factor may be determined (1012). A request indicating the desired display resolution and/or magnification factor is transmitted (1016) to a server that supplies images, such as pictures or videos. The image is received (1018) from the server and displayed (1020) on the display. A focus area distance and/or a pupil orientation of the user may also influence the desired display resolution. Bandwidth, processing, and power savings may result through the use of these systems and methods.
US09626737B2	Devices, systems, and methods for examining the interactions of objects in an enhanced scene Systems, devices, and methods obtain a sequence of images of a physical scene that includes a physical representation of a first object; calculate a sequence of first transform values of the physical representation of the first object based on the sequence of images store the sequence of first transform values; generate an enhanced scene; maintain the first object in the enhanced scene at positions and orientations that are indicated by the sequence of first transform values; receive an indication of selected transform values in the sequence of first transform values; retrieve the selected transform values; and generate a replay image of the enhanced scene, from a second observer viewpoint, that shows the first object at the position and the orientation that are indicated by the selected transform values.
US09626736B2	Memory-aware matrix factorization Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.
US09626735B2	Page management approach to fully utilize hardware caches for tiled rendering Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
US09626734B2	Display driver and image signal processing system including the same A display driver and an image signal processing system including the same, the display driver including a register block configured to sequentially store commands received from an application processor through a data lane, and a command processing unit configured to sequentially execute the commands during a plurality of frames.
US09626733B2	Data-processing apparatus and operation method thereof A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.
US09626732B2	Supporting atomic operations as post-synchronization operations in graphics processing architectures Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.
US09626731B2	Image processing apparatus and image processing method that calculate a number of pixels, required for outputting a size of an output image, according to obtained processing parameters and a predetermined processing order Input amount calculation processing and output amount calculation processing corresponding to each processing module are defined. The input amount calculation processing and the output amount calculation processing are performed in a processing order (a reverse order to the processing order) to obtain a favorable peripheral pixel amount.
US09626729B2	Oil-field trucking dispatch Provided is a process including: receiving a tank-nearly-full message indicating that a tank at an oil or gas related facility is or will be ready for a truck to unload and transport fluid accumulating in the tank; in response to the tank-nearly-full message, creating a tank-run record; sending a description of the tank-run to a mobile device of a driver of an oilfield truck; receiving, from the mobile device of the driver of the oilfield truck, a tank-run claimed message indicating that the driver will drive to the oil or gas related facility and transport at least some of the fluid accumulating in the tank; and after the tank-run claimed message, performing steps including: confirming that the tank-run has not yet been claimed; after the confirmation, designating the tank-run as claimed by the driver; and sending confirmation to the mobile device of the driver.
US09626727B2	Integrating metadata from applications used for social networking into a customer relationship management (CRM) system Integrating metadata from applications used for social networking into a customer relationship management (CRM) system includes obtaining, from applications used for social networking, metadata associated with users of the applications, analyzing the metadata from the applications to infer opportunities, relationships for mapping clients, structures, and subject matter experts, and integrating the opportunities, the relationships for mapping the clients, the structures, and the subject matter experts into a CRM system to populate the CRM system.
US09626717B2	Methods and systems for dynamic and embeddable storefront widget Methods and systems for extracting and displaying one or more products on a virtual storefront embedded in a topical community web page are disclosed. The displayed products may then be purchased by a user or a community member or a member of the group or forum directly at the virtual storefront. The community web page is related to a particular interest or a context and hosts information or media related to that particular context. The systems and methods disclosed herein may facilitate the community web page administrator, community web page owner, or any other person in similar capacity to either select one or more products statically or the products are dynamically extracted from one or more of a connected storefront or a marketplace or both.
US09626714B2	Laser mobile put wall A method of fulfilling orders and order fulfillment system includes a mobile assembly cart having a plurality of order assembly positions and a pointer assembly. The pointer assembly generates a beam and directs the beam to at least one of said assembly positions for selectively identifying at least one of the assembly positions for putting an item to or retrieving an order from each identified position. The assembly cart can be positioned with respect to the pointer assembly for the picking or putting and moved away from the pointer assembly after the picking or putting.
US09626712B1	System and method for visual verification of order processing One or more images of items for an order being processed at processing station of an order fulfillment center may be captured and associated with the order. Alternatively, a short video clip may be captured of the order being packaged. An electronic notification that the order has been processed may be sent to a customer associated with the order. The electronic notification may include a reference to one or more of the captured images or video clips. The customer may use a reference included in the notification to view the captured images. The customer may view captured images to verify that the order has been correctly processed. The captured images may include images of the items being packaged for shipment and may show the shipping address on the package allowing the customer to verify that indeed it is his package in the images.
US09626709B2	In-store field-of-view merchandising and analytics Concepts and technologies disclosed herein are directed to aspects of in-store field-of-view merchandising and analytics. According to one aspect disclosed herein, a system receives a message from a user device. The message can include an orientation of the user device and a location of the user device within an environment, such as a store. The system can obtain a potential field-of-view of a user associated with the user device. The system can determine, based upon the orientation, the location of the user device and the potential field-of-view of the user, an estimated field-of-view of the user. The system can query a database to look-up items located within the estimated field-of-view. The system can receive, in response to the query, a query response identifying an item located within the estimated field-of-view of the user within the environment.
US09626706B2	Apparatus and method for facilitating a purchase using information provided on a media playing device Disclosed are apparatus and method for facilitating a purchase in conjunction with media content information. The apparatus includes a receiver configured to receive a transmission of media content, information regarding the content, and information for facilitating a purchase of at least one of a copy of the content, a good, and/or a service. The content may include broadcast media content and entertainment media content. The apparatus also includes a processor configured to process the information regarding the content and the information for facilitating a purchase of the copy of the content, the good, and/or the service. The apparatus also includes a display device for displaying information.
US09626704B2	Automobile transaction facilitation based on a customer selection of a specific automobile A system, methods, and apparatus for performing automobile transactions are disclosed. In an example embodiment, automobile market data representative of current automobile market characteristics is stored. The automobile market data may include pricing, inventory, and consumer interest information received from dealers, manufacturers, and consumers. A consumer may provide a request for a response regarding a specific automobile using an image of a vehicle identification number or a graphical user interface. Automobile market data may be provided to a dealer based on the request. Bids to sell the specific automobile may be requested from dealers based on the request. Dealer bids may be provided to the consumer with prices and a delivery options. The consumer may select a bid which specifies a pickup location at a first dealer.
US09626702B2	Method and apparatus for providing embedded transaction modules Method and apparatus for provided embedded transaction modules are disclosed. One disclosed method comprises receiving a user input in an embedded transaction module displayed on a first webpage, wherein the user input is associated with a transaction and the embedded transaction module is not affiliated with the first webpage, and completing the transaction within the first webpage.
US09626699B2	Frequent markup techniques for use in native advertisement placement Techniques are provided that include obtaining a Document Object Model of an HTML document, such as a web page of a publisher. Elements of the Document Object Model may be identified that are associated with native advertisement placement candidate containers. Based at least in part on analysis associated with the Document Object Model, and utilizing at least some of the identified elements, one or more native advertisement placement candidate containers may be determined. Some techniques may utilize, in the analysis, construction and utilization of a suffix tree of a string of tags comprising all tags in the Document Object Model. Some techniques may utilize, in the analysis, a node flattening technique in connection with the Document Object Model.
US09626698B2	Systems and methods for power efficient discovery of infrastructure services on a network Systems, methods, and devices for power-efficient discovery of infrastructure services on a network are disclosed. In one aspect, a method for using advertising windows to transmit service information on a network is disclosed. The method includes transmitting timing information regarding an advertising window during which information on services offered by one or more nodes on the network will be advertised. The method further includes during the advertising window, transmitting information on services offered by one or more nodes on the network.
US09626693B2	Provision of anonymous context information and generation of targeted content Embodiments of the present disclosure are directed towards selective disclosure of user or computing environment attributes to facilitate generation and/or provision of targeted content. In various embodiments, a likelihood that disclosure of an attribute of a user or of a computing environment associated with the user will enable identification of the user may be determined based on an associated population count of users or computing environments sharing the same attribute. In various embodiments, the attribute may be selectively disclosed to a content provider configured to provide targeted content, or a recommendation may be selectively provided to the user as to whether the user should disclose the attribute to the content provider, based on the determination and a risk tolerance associated with the user. In various embodiments, a dimension authority may track and make available population counts of users or computing environments having various attributes.
US09626692B2	On-line advertising with social pay In one embodiment, a method includes receiving an indication of a reward-generating event associated with an advertisement. The reward-generating event includes an action by a user in response to the advertisement being presented to the user. The method also includes determining based at least in part on the action by the user a reward to allocate to the user for the reward-generating event.
US09626690B2	System and method for using data tags to manage tasks and rewards in providing object-to-object services The present invention relates to a method and system that use data tags to track tasks in applications to provide Object-to-Object (OTO) services. A first application data tag is issued by a data tag server as in an OTO service platform in response to an initiation of a first application by a first initiator. The first data tag specifies at least one first task for fulfilling a first service. The first application data tag is scanned by a first user terminal by a first participant. A first action data tag is issued by the data tag server. A first dynamically variable task data tag is issued by the data tag server to track the first task in the first action. The first dynamically variable task data tag is updated to record the completion of the first task in the first action when the first task is completed.
US09626689B1	Incentivizing location-based actions by groups A method of incentivizing location-based actions by groups is disclosed. A group of users of a game networking system is notified that an incentive reward is to be provided based on a number of members of the group performing a location-based action transgressing a threshold. The incentive reward is provided based on the number of members of the group performing the location-based action transgressing the threshold.
US09626685B2	Systems and methods of mapping attention The disclosure describes systems and methods of ranking user interest in physical entities based on the attention given to those entities as determined by an analysis of communications from devices over multiple communication channels. The attention ranking systems allow any “Who, What, When, Where” entity to be defined and ranked based, at least in part, on information obtained from communications between users and user proxy devices. An entity rank is generated for entity known to the system in which the entity rank is derived from the information in communications that are indicative of user actions related to the entity. The entity ranks are then used to modify the display of information or data associated with the entities. The system may also generate a personal rank for each entity based on the relation of the entity to a specified user.
US09626683B2	Method and system for advanced messaging An implementation of the inventive concept enables an outside entity to alter user's internet experience on a system-wide level. Specifically, inventive system enables a merchant, a distributor or any other entity to send contextually-relevant messages directly to the user's computer. Upon the receipt of the messages by the controller application residing on the user's computer, the messages are shown to the user by being incorporated into representation of various resources viewed by the user. For example, the received messages are incorporated into web pages viewed by the user by means of code injection. This way, the merchant, distributor or any other entity may provide targeted advertising to the user in a contextually relevant manner. Specifically, the controller application residing on the user's computer may detect requests for specific resources issued by the user in accordance with a predetermined criteria and incorporate the aforesaid received messages into those selected resources.
US09626681B2	Negotiable information access in electronic social networks A method for implementing an electronically-based negotiation session between users within an ESN. The method includes sending a message including a request portion and a response portion from a first user to a second user in a round of successive rounds, and in response to receiving the message from the first user, sending a message from the second user to the first user in a subsequent round, the message from the second user including a response portion responsive to the request portion of the message from the first user and a request portion. When a new round is performed, evaluating whether an agreement exists by checking messages previously exchanged, and exchanging subsequent messages, when any rounds remain and the session has not been terminated, and granting access and exchanging data between the users, executing actions, and setting policies as negotiated, when the session has been terminated and an agreement exists.
US09626680B1	System and method for detecting malicious payment transaction activity using aggregate views of payment transaction data in a distributed network environment Embodiments of systems and methods for fraud prevention in an online distribution network are disclosed. In certain embodiments, service providers that provide forms in association with merchant's web sites for submission of transactions may implement pro-active threat detection based on an aggregate view of transactions in that distributed computer network.
US09626675B2	Updating a widget that was deployed to a secure wallet container on a mobile device Updating a widget comprises receiving a query from a mobile device for the existence of an updated widget; transmitting information indicative of the availability of the updated widget to the mobile device; receiving a request for the updated widget from the mobile device; and transmitting the updated widget to the mobile device.
US09626671B2	System and method for processing orders Aspects of the disclosure relate generally to an order processing system that receives and prints orders and provides an indication of the number of the orders that have been printed and are awaiting acknowledgment by a user.
US09626668B2	Rights expression profile system and method using templates A system and method for creating a rights expression for association with an item for use in a system for controlling use of the item in accordance with the rights expression, including specifying rights expression information indicating a manner of use of an item, the rights expression information including at least one element, the element having a variable and corresponding value for the variable; and performing an encoding process, including determining an identifier associated with a template corresponding to the rights expression information, extracting from the rights expression information the value for the variable corresponding to the element, and encoding a license adapted to be enforced on a device based on the variable and the identifier, the license including an identification of the template and the value for the variable.
US09626667B2	Digital rights management engine systems and methods Systems and methods are described for performing digital rights management. In one embodiment, a digital rights management engine is provided that evaluates license associated with protected content to determine if a requested access or other use of the content is authorized. In some embodiments, the licenses contain control programs that are executable by the digital rights management engine.
US09626662B1	Systems and methods for alignment of check during mobile deposit An alignment guide may be provided in the field of view of a camera associated with a mobile device used to capture an image of a check. When the image of the check is within the alignment guide in the field of view, an image may be taken by the camera and provided from the mobile device to a financial institution. The alignment guide may be adjustable at the mobile device. The image capture may be performed automatically by the camera or the mobile device as soon as the image of the check is determined to be within the alignment guide. The check may be deposited in a user's bank account based on the image. Any technique for sending the image to the financial institution may be used.
US09626661B2	E-meeting requirement assurance for E-meeting management Embodiments of the present invention provide a system and computer program product for e-meeting requirements assurance in e-meeting management. In an embodiment of the invention, a computer program product for e-meeting requirements assurance in e-meeting management is provided. The computer program product includes selecting a scheduled e-meeting for an invitee in memory of a computer, retrieving resource requirements published for the selected scheduled e-meeting, inspecting local computing resources of the invitee, comparing the local computing resources to the retrieved resource requirements to identify local resource deficiencies, and generating a notice of the local resource deficiencies to the invitee prior to a scheduled date and time for the e-meeting.
US09626660B2	Conflict management in scheduling meetings A floating meeting is set up such that the actual meeting time is not fixed until after pre-defined parameters are satisfied. One parameter is a point in time nearer to the proposed meeting date(s) than the time of the original meeting invitation. At the later point in time, subsequent and potentially conflicting meetings are automatically avoided to maximize invitee availability or otherwise meet a meeting organizer's objective.
US09626657B2	Clustering electronic calendar schedules to reduce visual complexity and improve efficiency of meeting scheduling A system for clustering electronic calendar schedules in an event scheduling user interface displays the availability of invitee clusters that each include invitees with sufficiently similar availability during a target period. An invitee cluster list includes an invitee cluster entry for each invitee cluster, such that each invitee cluster entry displays the availability for all invitees contained in the corresponding cluster, as well as the number of invitees contained in the cluster. Invitees that do not belong to any cluster are listed as individual outlier entries, such that each outlier entry displays the availability for the corresponding outlier invitee and the invitee's name. The names of invitees contained in an invitee cluster are displayed in response to user selection of the cluster entry. A degree of similarity required for invitees to be clustered together, and/or a permitted total number of clusters, may be input from a user.
US09626656B2	Dialer with real-time reverse look-up including social data Methods and systems directed to a dialer application that performs a reverse look up on an outgoing communication to determine a specific member of a social networking system associated with the outgoing communication, and, based on the social relationship between the detected member and the sender of the communication, display particular information to the sender. In this manner, a user is provided a dialer that leverages information stored remotely on a social network.
US09626650B2	Cost-effective resource apportionment technologies suitable for facilitating therapies Configuration technologies for apportioning resources and communicating indications of potential or actual incentives based on one or more measurements or other objective indications that therapeutic components have been administered to an individual, other attributes of the therapeutic components or the individual, or other such determinants. Techniques for apportioning resources cost-effectively (between providers and other parties, e.g.) and for facilitating or handling implementations thereof or output therefrom.
US09626646B1	Distributed optimization method for real-time omnichannel retail operations Embodiments are directed to a computer implemented method of generating inventory valuation data for an omnichannel (OC) retail operation. The method starts with an unsolvable OC nonlinear nonconvex problem, applies transformations to generate a mixed-integer program (MIP) that is a tractable linear nonconvex form, solves the MIP, fixes prices at optimal values to achieve dimensionality reduction and eliminate all non-convexity by eliminating the pricing dimension. The method further obtains inventory flow linear programming (LP) that is linear convex, and solves the LP to recover a dual solution as initial inventory valuations.
US09626645B2	System, method and apparatus for locating and merging data fields of lost records with found records In one embodiment, a system, method, and apparatus to generate a merged record comprises: a client server configured to generate a first report and a recovery server configured to: receive the first report, determine if a descriptive term matches a generic term, associate a generic code to the at least one descriptive term if there is a match; determine if the descriptive term matches a product term if there is no match; associate a product code to the descriptive term if there is a matches; and associate the descriptive term with a main code, the main code based upon the generic code or product code.
US09626643B2	Object-based information collection in operation performance A method to be performed in a computer system in association with initiating a physical operation includes receiving a request object that corresponds to a request to initiate a physical operation. The method includes generating, using the request object, an information collection object configured to represent performance of the physical operation. The method includes obtaining data generated in the performance of the physical operation and recording the data in the information collection object. A computer system includes a request management module configured to generate the request object upon receiving a request to initiate a physical operation, and an information collection module configured to generate the information collection object using the request object.
US09626641B2	Tennis game analysis using inertial sensors A method for analyzing a tennis session for game improvement using a portable device and a tennis analysis system, includes collecting information from the tennis session using the portable device attached to a racket used in a game for a plurality of strokes, transferring the collected information from the portable device to the tennis analysis system using a communication interface; analyzing information relating to the plurality of strokes; analyzing information relating to collections of strokes from said plurality of strokes to identify rallies, games, sets and matches played during the session, by said tennis analysis system; and generating a plurality of game statistics.
US09626639B2	Image processing and item transport Embodiments relate generally to new and useful systems and methods for processing digital images of items to facilitate item transport and/or handling. In some embodiments, a method is provided for operating an image processing and item transport system having a computing system that includes a digital image processing component. In some embodiments, the method can involve the digital image processing component acquiring a digital image and processing the digital image to obtain a digital representation of an item represented in the digital image, to estimate a dimensional size and/or weight of the item represented in the digital image, and to convert the digital image to a format suitable for outputting. In some embodiments, the method can include processing the estimated dimensional size and/or weight to identify personnel and/or equipment capable of transporting the item represented in the digital image, and outputting a transport instruction identifying the personnel and/or equipment capable of transporting the item represented in the digital image.
US09626636B2	Method and apparatus for tracking and reporting environmental impact of food products Various embodiments of the present disclosure include methods and apparatus for tracking and reporting the environmental impact of food products. In an example embodiment, an apparatus comprises a hand-held device including a display and one or more input devices to sense product identification indicia associated with a food product that is grown or raised in an agricultural operation. The hand-held device includes at least one processor to determine a machine-readable identification code from the product identification indicia; send the identification code to at least one remote server; receive, from the at least one remote server, information that is associated with the product, the information including environmental impact information that is associated with the production of the food product; and display at least some of the received environmental impact information on the display in human readable form.
US09626634B2	Industrial plant equipment, process and maintenance optimization A method includes obtaining at least first, second and third data corresponding to an industrial plant, wherein the first data is indicative of a performance of equipment of the industrial plant, the second data is indicative of a process of the industrial plant, and third data is indicative of a reliability of the industrial plant, analyzing the first, second and third data with respect to predetermined metrics of the industrial plant, and generating a signal indicative of a recommendation for at least one of use of the equipment or implementation of the process based on a result of the analyzing.
US09626630B2	Machine learning customer valuation functions A computing device determines one or more first degree correlations based on valuation information. The computing device determines one or more important variables based on at least a comparison between the absolute value of the one or more first degree correlations to a first threshold value. The computing device determines a valuation function based on at least one or more of the determined one or more important variables.
US09626628B2	Point-to-multipoint communication infrastructure for expert-based knowledge feed-back using learning machines In one embodiment, techniques are shown and described relating to a point-to-multipoint communication infrastructure for expert-based knowledge feed-back using learning machines. A learning machine may communicate an expert discovery request into a network to discover one or more experts, and then receive from the one or more experts, one or more expert discovery responses. Based on the one or more received expert discovery responses, the learning machine may then build a dynamic multicast tree of experts to assist the learning machine in a computer network.
US09626623B2	Method of automated discovery of new topics The present disclosure relates to a method for performing automated discovery of new topics from unlimited documents related to any subject domain, employing a multi-component extension of Latent Dirichlet Allocation (MC-LDA) topic models, to discover related topics in a corpus. The resulting data may contain millions of term vectors from any subject domain identifying the most distinguished co-occurring topics that users may be interested in, for periodically building new topic ID models using new content, which may be employed to compare one by one with existing model to measure the significance of changes, using term vectors differences with no correlation with a Periodic New Model, for periodic updates of automated discovery of new topics, which may be used to build a new topic ID model in-memory database to allow query-time linking on massive data-set for automated discovery of new topics.
US09626622B2	Training a question/answer system using answer keys based on forum content An approach is provided to train a question answering (QA) system using answer keys based on forum content. In the approach, a question is selected from a post in a threaded discussion. An answer to the selected question is automatically identified from crowd-based sources, with the identified answer having a confidence level greater than a threshold. An answer key is built using the selected question and the identified answer. The QA system is automatically trained using the answer key.
US09626621B2	Systems and methods for combining stochastic average gradient and hessian-free optimization for sequence training of deep neural networks A method for training a deep neural network (DNN), comprises receiving and formatting speech data for the training, performing Hessian-free sequence training (HFST) on a first subset of a plurality of subsets of the speech data, and iteratively performing the HFST on successive subsets of the plurality of subsets of the speech data, wherein iteratively performing the HFST comprises reusing information from at least one previous iteration.
US09626619B2	Systems and methods for synchronizing a plurality of RFID interrogators in a theatre of operation RFID tags are used for many purpose including tracking. RFID interrogators are used to retrieve information from tags. In many applications, a plurality of RFID interrogators are required. Synchronization between interrogators in the same theatre of operation is critical to ensure that their broadcasts do not interfere with each other. In fixed RFID interrogator applications, RFID interrogators can be wired together allowing a channel to synchronize the transmissions of the RFID interrogators. Methods described herein can ensure that synchronization is maintained in the event of the failure of a synchronizing master. Furthermore, additional methods for synchronizing RFID interrogators in wireless applications are described allowing synchronization in the absence of wired connections between interrogators.
US09626614B2	Protection of a radio frequency transmit-receive terminal against electromagnetic disturbances An antenna circuit for a device of transmission/reception by inductive coupling, including a first inductive element in parallel with a capacitive element and, between each node of the parallel association and two terminals of a switch, a second inductive element.
US09626610B2	System and method for quality management utilizing barcode indicators A quality management system for products including a multiplicity of barcoded quality indicators, a barcode indicator reader and a product type responsive indication interpreter, each of the barcoded quality indicators including a first barcode including at least one first colorable area, the first barcode being machine-readable before exceedance of the at least one time and temperature threshold, at least a second barcode including at least one second colorable area, the second barcode not being machine-readable before exceedance of the at least one time and temperature threshold, a coloring agent located at a first location on the indicator and a coloring agent pathway operative to allow the coloring agent to move, from the first location to the first and second colorable areas simultaneously thereby causing the first barcode to become unreadable and at the same time causing the second barcode to become machine-readable.
US09626605B2	Image processing apparatus, information processing method, and storage medium for processing rendering data including a pixel pattern for representing a semitransparent object An apparatus includes a determination unit configured to determine whether rendering positions of two pieces of rendering data, each representing a semitransparent state by including pixels that are to be rendered by a rendering unit and pixels that are not to be rendered, overlap, and a control unit configured to, if it is determined by the determination unit that the rendering positions of the two pieces of rendering data overlap, perform control such that one of the two pieces of rendering data is not rendered by the rendering unit. Based on the level of the overlap between a plurality of semitransparent objects, the apparatus converts each hatch pattern so that image quality deterioration does not occur.
US09626598B2	Method and apparatus for image processing A method is provided for recognition of a ceiling portion, a vertical object portion and a ground portion in an image of indoor scene executed in an electronic system. The image is divided into a plurality of pixel sets. Expected values of each pixel sets with a ceiling distribution function, a vertical object distribution function and a ground distribution function are calculated. The expected values of each pixel set in the ceiling distribution function, the vertical object distribution function and the ground distribution function are compared to determine whether each pixel set belongs to a ceiling object, a vertical object or a ground object.
US09626597B2	Systems and methods for facial age identification Systems and methods are provided for acquiring classification functions for facial age identification. For example, a plurality of facial images associated with different ages are acquired; the facial images are assigned into a plurality of facial image collections based on at least information associated with a plurality of first age groups; for a first age group, one or more first facial image collections associated with one or more second age groups older than the first age group are acquired as positive samples; one or more second facial image collections associated with one or more third age groups younger than the first age group are acquired as negative samples; and training is performed based on at least information associated with the first positive samples and the negative samples to determine one or more classification functions for the first age groups.
US09626595B2	Method and apparatus for tracking superpixels between related images A method for pixel mapping between an origin superpixel in a first image and a target superpixel in a second image and an apparatus configured to perform the method. The apparatus comprises a feature vector determining unit, which determines a feature vector of an origin pixel of the origin superpixel and which further determines feature vectors of target pixels of the target superpixel. A mapping pixel selector selects a mapping pixel for the origin pixel among the target pixels based on a comparison of the feature vectors.
US09626590B2	Fast cost aggregation for dense stereo matching Methods, systems, computer-readable media, and apparatuses for fast cost aggregation for dense stereo matching are presented. One example method includes the steps of receiving first and second images of a scene; rectifying the images; computing a cost volume based on the first and second images; subsampling the cost volume to generate a subsampled cost volume; for each pixel, p, in the subsampled cost volume, determining one or more local extrema in the subsampled cost volume for each neighboring pixel, q, within a window centered on the pixel, p; for each pixel, p, performing cost aggregation using the one or more local extrema; performing cross checking to identify matching pixels; and responsive to identifying unmatched pixels, performing gap-filling for the unmatched pixels to generate a disparity map; and generate and storing a depth map from the disparity map.
US09626588B1	Detecting and locating lasers pointed at aircraft The present invention provides various apparatus and methods for detecting laser beams, locating their origin, recording these events, and alerting law enforcement agencies as the event unfolds. The apparatus includes at least two communicably coupled camera systems coupled to one or more image processors. A method for detecting the laser beam includes the use of optical, temporal and two-dimensional spatial image filtering. A method for computing the location of the laser beam consists of performing geometric computations using triangulation techniques and physical surveying of the cameras. A method for communicating the location of the laser beam in real-time includes the use of wired or wireless communications means, including the coordination with local air traffic control information.
US09626587B2	Iterative reconstruction scheme for phase contrast tomography A method of tomographic imaging the real part of the refractive index of the internal structure of an image volume and a corresponding apparatus for performing the method. The method includes a two-step process of first retrieving phase projections of an image volume from projective intensity measurements through the image volume. The second step of the method includes iterative image reconstruction of an image of the image volume using phase projections taken at multiple projection angles. The first step of intensity measurements and subsequent phase retrieval can use one of many possible phase retrieval methods including the Bronnikov phase retrieval method. The second step of iterative image reconstruction can be performed using the total variation minimization method, the algebraic reconstruction technique method, or any other iterative image reconstruction method.
US09626586B2	Optimized fast hessian matrix computation architecture Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
US09626584B2	Image cropping suggestion using multiple saliency maps Image cropping suggestion using multiple saliency maps is described. In one or more implementations, component scores, indicative of visual characteristics established for visually-pleasing croppings, are computed for candidate image croppings using multiple different saliency maps. The visual characteristics on which a candidate image cropping is scored may be indicative of its composition quality, an extent to which it preserves content appearing in the scene, and a simplicity of its boundary. Based on the component scores, the croppings may be ranked with regard to each of the visual characteristics. The rankings may be used to cluster the candidate croppings into groups of similar croppings, such that croppings in a group are different by less than a threshold amount and croppings in different groups are different by at least the threshold amount. Based on the clustering, croppings may then be chosen, e.g., to present them to a user for selection.
US09626578B2	Viewing aid with tracking system, and method of use A viewing aid includes a camera, a viewing surface within a field of view of the camera, a memory, a display, and software programmed to track a tracking element within the field of view. Viewing material is placed on the viewing surface. The camera, viewing surface, and material all remain substantially stationary. The camera captures and stores an initial image of the material in the memory. The software then tracks the location of a tracking element within the field of view then maps the location to a portion of the initial image in memory using an X-Y coordinate system, and/or identifies character elements of the material adjacent the tracking element then maps the character elements to corresponding character elements of the initial image in memory. An enhanced image is then displayed on the display corresponding to the mapped portion of the initial image.
US09626577B1	Image selection and recognition processing from a video feed A system that selects image frames from a video feed for recognition of objects (such as physical objects, text characters, or the like) within the image frames. The individual frames are selected using robust historical metrics that compare individual metrics of the particular image (such as focus, motion, intensity, etc.) to similar metrics of previous image frames in the video feed. The system will select the image frame for object recognition if the image frame is relatively high quality, that is the image frame is suitable for a later object recognition processing.
US09626571B2	Method and device for determining a valid lane marking A method and a device for determining a valid lane marking using a vehicle camera system. A series of pictures are taken of an area in front of the vehicle. At least a first lane marking and a second lane marking different from the first lane marking are detected in corresponding image data. A vehicle driving ahead of the vehicle is detected in at least two successively taken pictures and its position relative to the first lane marking as well as its position relative to the second lane marking is determined. Dependent on the positions of the vehicle driving ahead determined with the aid of the pictures, one of the detected lane markings is selected as the valid lane marking.
US09626566B2	Methods and apparatus for autonomous robotic control Sensory processing of visual, auditory, and other sensor information (e.g., visual imagery, LIDAR, RADAR) is conventionally based on “stovepiped,” or isolated processing, with little interactions between modules. Biological systems, on the other hand, fuse multi-sensory information to identify nearby objects of interest more quickly, more efficiently, and with higher signal-to-noise ratios. Similarly, examples of the OpenSense technology disclosed herein use neurally inspired processing to identify and locate objects in a robot's environment. This enables the robot to navigate its environment more quickly and with lower computational and power requirements.
US09626565B2	Automated conversion of two-dimensional hydrology vector models into valid three-dimensional hydrology vector models A system for automated conversion of two-dimensional hydrology vector models into valid three-dimensional hydrology vector models, comprising a vector extraction engine that retrieves vectors from, and sends vectors to, a vector storage, a DSM server that retrieves a DSM from a DSM storage and computes a DSM from stereo disparity measurements of a stereo pair retrieved from a raster storage, and a rendering engine that provides visual representations of images for review by a human user, and a method for automated hydrology vector model development utilizing the system of the invention.
US09626561B2	Method and apparatus for connecting devices using eye tracking A method for connecting an electronic device using an eye-tracking technique and an electronic device that implements the method are provided. The method includes acquiring eye-tracking information, obtaining image information corresponding to the eye-tracking information, comparing the image information with specific information about at least one external device, and based on the comparison, determining a specific external device to be connected from among the at least one external device.
US09626546B2	Electronic device and control method thereof A method for controlling an electronic device is provided. The electronic device has a child mode and an adult mode. The method includes capturing a touch image of a finger contacting with a touch screen when a touch operation is applied to unlock the touch screen. An area value of a touch image of the finger contacting with the touch screen is calculated based on the captured touch image and compared with one or more predefined area values. The user is determined to be a child or an adult according to the comparison result. The electronic device is controlled to alternatively enter the adult mode or the child mode based on the determination result.
US09626542B2	Host feedback of scan status A multi-mode ring scanner (MMRS) has a ring unit for wearing on a finger. The MMRS optionally has a wrist unit coupled to the ring unit, such as via a cable. The MMRS optionally communicates wirelessly with a computing device. The ring unit has one or more scanners (such as an optical scanner or an RFID tag reader). The ring unit optionally has two paddle switches for activation by inward pressure from fingers adjacent to the finger. The two switches enable specifying operation of the MMRS in a plurality of modes and/or to communicate a plurality of information codes to the computing device. The computing device is optionally enabled to assign a function to each combination of activation of the two switches. A scanning system including the MMRS optionally provides feedback to a user based on feedback from a host processor.
US09626539B2	Device, system and method for identification of object in an image, and a transponder A device and method for identification of at least one object in an image registered with an image registration device, wherein each of the at least one object is provided with a wireless tag. The device includes at least one sensor for registering a wireless signal from the wireless tag and for registering at least one direction to the wireless tag, wherein the wireless signal includes identification for the object.
US09626532B2	Electronic device and method for unlocking touch screen thereof In a method for unlocking a touch screen of an electronic device, a cube is generated for unlocking the touch screen, and an unlocking mode of each surface of the cube is set. The cube is displayed on the touch screen for receiving touch signals. After the touch signals are received from each surface of the cube, a touch mode of each surface of the cube are obtained based on the touch signals. The touch screen of the electronic device is unlocked when the touch mode of each surface of the cube is in accordance with the unlocking mode of each surface of the cube.
US09626531B2	Secure control of self-encrypting storage devices Generally, this disclosure provides systems, devices, methods and computer readable media for secure control of access control enablement and activation on self-encrypting storage devices. In some embodiments, the device may include a non-volatile memory (NVM) and a secure access control module. The secure access control module may include a command processor module configured to receive a request to enable access controls of the NVM from a user, and to enable the access controls. The secure access control module may also include a verification module configured to verify a physical presence of the user. The secure access control module may further include an encryption module to encrypt at least a portion of the NVM in response to an indication of success from the verification module.
US09626527B2	Server and method for secure and economical sharing of data The present invention relates to a web server having a web application using published API of one or more cloud storage providers, said web application being dedicated to secure and economical sharing of encrypted files residing at the cloud storage providers, said files being managed under a virtual folder which is shared by a group of different entities.
US09626523B2	Systems and methods of audit trailing of data incorporation The technology disclosed relates to creating an audit trail of data incorporation in user profiles. In particular, it relates to linking trust objects to fields of the user profiles.The technology disclosed also relates to maintaining an opt trail that captures user opt-ins by recording the circumstances surrounding opt-in actions. In particular, it relates to linking trust objects to user profiles that connect users to an advertising campaign.The technology disclosed further relates to tracking and measuring reputation of product models in consumer markets. In particular, it relates to assembling consumer feedback on the product models from online social networks and service records of the product models and applying sentiment analysis on the consumer feedback.
US09626518B2	Avoiding encryption in a deduplication storage Avoiding encryption in a deduplication vault. In one example embodiment, a method may include analyzing an allocated plain text block stored in the source storage to determine if the block is already stored in the deduplication storage, in response to the block not being stored, encrypting the allocated plain text block and analyzing the encrypted block to determine if the encrypted block is already stored in the deduplication storage, analyzing a second allocated plain text block stored in the source storage to determine if the block is already stored in the deduplication storage, in response to the block already being stored, avoiding encryption of the second allocated plain text block by not encrypting the second allocated plain text block and instead associating the location of the second allocated plain text block in the source storage with the location of the duplicate block already stored.
US09626507B2	Hosted application sandboxing This specification describes technologies relating to software execution. A sandboxing computer system accesses at least one application file and instantiates a sandbox environment. The sandbox environment does not having allocated, when instantiated, a memory buffer for use by a running application. The application file is run in the sandbox environment to produce an application output. A memory buffer is for use by the running application after the application has begun running, and a client computer system is provided with the application output.
US09626505B2	Method and apparatus for managing authentication A method of and an apparatus for managing authentication in an electronic apparatus are provided. The method includes obtaining authentication information using an authentication module; pairing the authentication information with an object to which access is controlled; and displaying an image related to the object together with the authentication information. The electronic apparatus includes an authentication module configured to obtain authentication information; a control module configured to pair the authentication information with an object to which access is controlled; and a display module configured to display an image related to the object together with the authentication information.
US09626503B2	Methods and systems for managing services and device data Computationally implemented methods and systems include acquiring property data regarding at least one property of one or more devices, generating anonymized data by altering the acquired property data to obscure one or more portions of the acquired property data that uniquely identify the one or more devices and/or one or more users of the one or more devices, presenting the anonymized data to one or more service providers configured to generate one or more services, and acquiring the generated one or more services, said generated one or more services at least partly based on the anonymized data. In addition to the foregoing, other aspects are described in the claims, drawings, and text.
US09626502B2	Method and system for enterprise network single-sign-on by a manageability engine A manageability engine (ME) receives an authentication response from a user during pre-boot authentication and registers the user with a key distribution center (KDC), indicating that the user has successfully authenticated to the PC. The KDC supplies the ME with single-sign-on credentials in the form of a Key Encryption Key (KEK). The KEK may later be used by the PC to obtain a credential used to establish secure access to Enterprise servers.
US09626500B2	Managing access to an electronic system A method, system or computer usable program product for managing access to an electronic system through a touchscreen device including presenting a display of a first and a second scrolling stream of icons; responsive to user input, detecting contemporaneous selection of a first icon from the first scrolling stream and a second icon from the second scrolling stream; and responsive to the selection of the first and second icon matching an established unlock pattern, unlocking the electronic system.
US09626497B2	Sharing USB key by multiple virtual machines located at different hosts A system for sharing a USB Key by multiple virtual machines located at different hosts including at least two virtual machine managers, each virtual machine manager including a virtual machine transceiver module which is configured to receive a request for accessing a USB Key from a virtual machine within its host; a storage module which is configured to store an association relationship between a USB Key and the virtual machine authenticated by the USB Key; a verification module which is configured to, in response to judging that the virtual machine of the received request can access the USB Key, transmit the request for accessing the USB Key to a USB Key transceiver module of a virtual machine manager of the host where the USB Key is located; and a USB Key transceiver module which is configured to receive a request for accessing a USB Key, and to transmit an access request to a connected USB Key.
US09626496B2	Method and apparatus for processing sensor data of detected objects A system that incorporates teachings of the subject disclosure may include, for example, a method for detecting, by a system including at least one processor, a presence of an object from sensor data generated by a sensor device, retrieving, by the system, from a memory device a plurality of profiles biometrically descriptive of approved objects, asserting, by the system, an alarm responsive to determining from the sensor data that the detected object is not biometrically correlated to any of the plurality of profiles, classifying, by the system, the detected object as an authorized object responsive to determining from the sensor data that the detected object is biometrically correlated to at least one of the plurality of profiles, and notifying, by the system, at least one neighboring device responsive to asserting the alarm or responsive to classifying the detected object as the authorized object. Other embodiments are disclosed.
US09626494B2	Method and system for encryption and/or decryption Disclosed is a method which comprises receiving a user input which includes a password component and a non-password component that is defined by a user, the non-password component is arranged relative to the password component in a random manner determined by the user; verifying a presence of a pre-assigned password within the user input, wherein the pre-assigned password is associated with the user and stored in a first database; and based on the verified presence of the pre-assigned password within the received user input, identifying the non-password component. This way, even if a third party has full view of the user input entry, the visitor would be unable to discover the password and additional information individually.
US09626492B2	Sharing and executing sensitive logic semantics Obfuscating denotational logic in a source program. A non-rule-based object oriented source program is received. The source program is transformed into a rule-based source program that includes an object model and a ruleset. Attribute domains of the rule-based source program are characterized by a structure of their values in which the structure of the values is nominal, ordered, interval, or ratio. A minimum cardinality is calculated for each domain attribute. First domain attributes are randomly mapped to second domain attributes, each second domain attribute having the same value structure and a same or higher cardinality as the corresponding first domain attribute. For each randomly mapped pair a domain range of the first domain attribute is mapped to a domain range of the second domain attribute. In the rule-based source program first domain input fields and values are replaced with the respective second domain input fields and values.
US09626490B2	Systems and methods for enabling playback of digital content using electronic tickets and ticket tokens representing grant of access rights Systems and methods for accessing digital content using electronic tickets and ticket tokens are disclosed. In one system, a user device includes a processor, a network interface, and memory configured to store an electronic ticket, and a ticket token, and the processor is configured by an application to send a request for digital content, receive a ticket token from a merchant server, wherein the ticket token is generated by a DRM server and associated with an electronic ticket that enables playback of the requested digital content, send the ticket token to a DRM server, receive an electronic ticket that enables playback of requested digital content, request the digital content associated with the electronic ticket, and play back the requested digital content using the electronic ticket.
US09626489B2	Object rendering systems and methods Systems and methods are described that protect intellectual property rights in connection with 3-dimensional printing processes. In certain embodiments, an object a user would like to render with a 3-dimensional printing device may be compared with one or more managed objects having certain associated intellectual property rights. If the object is found to be similar to a managed object (e.g., similar in shape, function, composition, etc.), policy associated with the managed object may be enforced in connection with rendering the object. In this manner, intellectual property rights associated with the managed objects may be enforced.
US09626484B2	Medication storage and dispensing apparatus having linear drawer assembly including discrete storage modules A medication storage and dispensing workstation for use in a medication management system administering the inventory and distribution of pharmaceuticals and medical supplies in a healthcare environment is disclosed. The workstation incorporates a linear drawer assembly having a plurality of discrete, removable, storage modules for containing medications and/or other medical supplies. The storage modules are arranged in a linear array extending longitudinally along the travel path of the linear drawer assembly. Each storage module, in turn, comprises a drawer that is extensible laterally relative to the linear arrangement of the storage modules. As such, the drawer assemblies comprise a compartmentalized “drawer-in-drawer” arrangement that provides an efficient use of storage space and enables a user to utilize the workstation in a workspace having a smaller footprint that traditional storage cabinet apparatus.
US09626479B2	Systems, methods, user interfaces and analysis tools for supporting user-definable rules and smart rules and smart alerts notification engine Computer implemented methods and systems operating on real-time data derived from a plurality of data sources for supporting user-definable rules and providing user notifications for providing user notifications and smart alarms. A user-interface configured to dynamically display a parameter and toggle between a tabular display and a graphical display is generated. At least one of a user-defined rule or a threshold value associated with the parameter from a user-interface element is received. A notification is provided to a user when the parameter satisfies the user-defined rule or exceeds the threshold value.
US09626474B2	Expanded canonical forms of layout patterns Aspects of the disclosed technology relate to techniques for determining expanded canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices for a plurality of windows may then be determined. The plurality of windows comprise the window, are centered in the same location as the window, and have different sizes.
US09626472B2	Method and system of forming layout design A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.
US09626471B2	Methods and systems for filtering components in hierarchically-referenced data A computer-implemented method for filtering components from a logical component hierarchy is provided. The method uses a computing device having a processor and a memory. The method includes identifying, in the memory, a filter associated with the logical component hierarchy. The method also includes comparing, by the processor, a sub-component of the logical component hierarchy with the filter. The method further includes identifying the sub-component for filtration based on the comparison of the sub-component with the filter. The method also includes filtering the sub-component from the logical component hierarchy.
US09626463B2	Accelerated algorithm for modal frequency response calculation A computer-implemented method is provided for simulating a modal frequency response of a real-world object. The computer-implemented method includes dividing a plurality of excitation frequencies into a plurality of excitation frequency subsets, calculating modal frequency responses for at least a portion of the excitation frequencies in a given excitation frequency subset, and generating a simulation of the real-world object based at least in part on the modal frequency responses.
US09626460B2	Method for creating accurate, updateable vertical ramps that fall on ramp geometry in transition areas of laminated composite parts Methods for product data management and corresponding systems and computer-readable mediums. A method includes receiving one or more layer boundaries of one or more plies of a composite part. The method includes creating a topological definition from the layer boundaries, the topological definition includes one or more vertices and half-edges. The method includes identifying one or more vertical ramp sections of one or more vertical ramps from the topological definition that form one or more discontinuities in the topological definition. The method includes adding one or more additional vertices and half-edges to the topological definition based on the layer boundaries and the vertical ramp sections. The method includes creating one or more faces in the topological definition along the vertical ramp based on the additional vertices and half-edges to resolve the discontinuities. The method includes transmitting the topological definition with the faces.
US09626450B2	Flash redirection with browser calls caching In particular embodiments, a client loads a flash player. The flash player requests a flash redirection browser to execute an NPN call, the NPN call including a string. The flash redirection browser determines whether a cache at the client includes the string, and if the cache includes the string, the flash redirection browser determines an identifier associated with the string in the cache and returns the identifier to the flash player.
US09626448B2	System and/or method for linking network content The present invention provides a system (10) for linking network content (12n) over a communications network (14n). The system (10) including: at least one memory or storage unit (20n) operable to store and/or maintain a plurality of linked-content facilities (30n), each of the linked-content facilities (30n) being independently associated with a network location that contains network content (12n); at least one processor operable to execute software that generates, maintains and/or controls access to the linked-content facilities (30n) for a plurality of users (24n); and, at least one input/output device (22n) operable to provide an interface for the users (24n) to operate the software in order to retrieve and/or view the linked-content facilities (30n) for selected network locations from the memory or storage unit (20n), via the communications network (14n). Wherein the linked-content facilities (30n) stored and/or maintained on the memory or storage unit (20n) include system generated link content (32n,32An), and/or user generated link content (32n,32An) received from at least one user (24n), regarding network content (12n) related to the respective network locations. The present invention also provides associated methods (100) for linking network content (12n) for use with the system (10) of the invention.
US09626443B2	Searching and accessing application functionality A method of performing a search includes receiving, at a computing device, search results transmitted from a search system in communication with the computing device. The search results include a header for an application executable on the computing device and application access mechanisms associated with the header. Each application access mechanism has a reference to the application and indicates one or more performable operations for the application. The method includes displaying, on a display in communication with the computing device, a graphical user interface including the header, an expansion element associated with the header, and user selectable access links grouped with the header. Each access link is associated with an application access mechanism for the application. The expansion element has an expanded state and a collapsed state.
US09626442B1	System and method for a customer care document management system A customer care knowledge management system. The system comprises a server computer comprising more than one search engine, configured to search an answer to the problem in the document, in a social community, and in at least one external website, wherein a social community is a computer managed online social community. The server computer further comprises a user interface server application, configured to combine search results from the more than one search engine, attach relevant discussions in a social community to the document, wherein a discussion is an aggregation of comments, replies, or posts on a topic, issue, or subject matter, filter at least some search results based on a profile of a customer care agent and the type of the problem, and notify at least one subject matter expert of the problem if no answer is found.
US09626439B2	Method for searching in a database The present invention relates to a method for searching in a database containing at least one set of objects each linked to at least one descriptor, the search being done by a search engine from at least one request by a user in order to return at least one result object, said search method being characterized in that the request comprises at least one search parameter comprising a series of at least one search element (10, 11, 12, 13) obtained by freely adding (15) elements to said series by the user, the addition step being able to be repeated multiple times until a search instruction is given.
US09626437B2	Search scheduling and delivery tool for scheduling a search using a search framework profile A search request from a user is received wherein the search request includes a search framework profile and at least one search term. Scheduling information is accessed from the search framework profile and a search operation is scheduled for execution in accordance with the at least one search term and search scheduling information. An indication that the search request is scheduled for execution is returned to the user.
US09626436B2	Systems, methods, and computer readable medium for generating playlists Methods, systems and computer program products are provided for generating a playlist. An application programming interface (API) receives a request to generate a playlist, where the request includes a set of rule-primitives. A playlist engine evaluator evaluates a rule corresponding to each rule-primitive in the set of rule-primitives across a catalog of media content, calculates a cost associated with each item in the catalog of media content, and generates a playlist based on the items of the catalog having the lowest costs.
US09626432B2	Defect record classification An approach to classify different defect records by mapping plain language phrases to a taxonomy. The approach includes a method that includes receiving, by at least one computing device, a defect record associated with a defect. The method further includes receiving, by the least one computing device, a plain language phrase or word. The method further includes mapping, by the least one computing device, the plain language phrase or word to a taxonomy. The method further includes classifying, by the least one computing device, how the defect was at least one of detected and resolved using the taxonomy.
US09626426B2	Clustering using locality-sensitive hashing with improved cost model Embodiments are disclosed for using an improved locality sensitive hashing (LSH) operation for the K-means clustering algorithm. In some embodiments, parameters of an LSH function are optimized with respect to a new cost model. In other embodiments, an LSH operation is applied with optimized parameters to a K-means clustering algorithm.
US09626424B2	Disambiguation and tagging of entities Tagging of content items and entities identified therein may include a matching process, a classification process and a disambiguation process. Matching may include the identification of potential matching candidate entities in a content item whereas the classification process may categorize or group identified candidate entities according to known entities to which they are likely a match. In some instances, a candidate entity may be categorized with multiple known entities. Accordingly, a disambiguation process may be used to reduce the potential matches to a single known entity. In one example, the disambiguation process may include ranking potentially matching known entities according to a hierarchy of criteria.
US09626423B2	Information processing apparatus, information processing method, and program for processing and clustering post information and evaluation information An information processing apparatus includes a communication unit and a control unit. The control unit is configured to control the communication unit to receive a plurality of pieces of post information sent from a first user, to obtain a plurality of pieces of evaluation information of another user with respect to the received plurality of post information, to classify the plurality of pieces of post information into a plurality of clusters, and to determine, as an advantage cluster of the first user, a cluster with the highest evaluation in the plurality of pieces of evaluation information out of the plurality of clusters.
US09626422B2	Systems and methods for reslicing data in a relational database Systems and methods for reslicing data in a representation of a relational database are disclosed. In one embodiment, the database includes a representation including a first slice. The database system creates a plurality of new slice and to create a plurality of write queues. The database system copies units of data in the first slice to the new slices according to a distribution function. The distribution function determines, for each unit of data in the first slice, one of the new slices into which to copy the unit of data. The database system asynchronously writes one or more actions of a set of one or more asynchronous database transactions to the first slice when copying the data in the first slice to the new slices. The database asynchronously enqueues the one or more actions of the set of asynchronous database transactions in the write queues according to the distribution function.
US09626421B2	ETL-less zero-redundancy system and method for reporting OLTP data A system includes a relational database management system component and a column-oriented data processing component. The relational database system component stores database information in a row format. The column oriented data processing component stores the database information in a column format. In response to a database update request, the relational database management system component updates the database information stored in the row format; the relational database management system component notifies the column-oriented data processing component of the database update request; and the column-oriented data processing component updates the database information stored in said column format. In response to a query request, the column-oriented data processing component generates a query response based on the database information stored in said column format. In this manner, the system is able to generate up-to-date reports without the need for extraction, translation and loading procedures.
US09626419B2	Optimizing data synchronization between mobile clients and database systems Mechanisms and methods are provided for optimizing data synchronization between clients and database systems. These mechanisms and methods provide optimizations for synchronization requests, by either breaking a synchronization request into multiple smaller requests, or by executing different code routines for differing client types, or by pre-caching data that a user is anticipated to want at a future point. Such optimization techniques can enable clients with varying capacities (e.g., mobile client vs. full desktop client) to optimally utilize their respective device capabilities.
US09626414B2	Automatic log record segmentation Methods and arrangements for segmenting log records. A log file is received. Candidates for a sequential pattern within the log file are automatically discerned, and, for each candidate, a likelihood is estimated that it represents a boundary within the log file. Other variants and embodiments are broadly contemplated herein.
US09626410B2	Vertically partitioned databases A method for a distributed computing system managing vertically partitioned data includes receiving a query for a first row of data, where a first column of the first row of data is stored in a first data server and a second column of the first row of data is stored a second data server. The method translates the query for the first row of data into two queries, wherein a first translated query is for the first column of the first row of data and a second translated query is for the second column of the first row of data. The method sends the first translated query to the first data server and the second translated query to the second data server. Responsive to receiving the first column and the second column of the first row of data, the method sends the first column and the second column of the first row of data.
US09626403B2	Relational data model variant Systems and methods for handling queries are disclosed. A computer determines that a data-table includes a problematic-key. The problematic-key includes a key used in queries that fails to generate results within a threshold time period. The computer creates a variant-table configured to store at least a portion of the data in the data-table and optimize processing queries using the problematic-key. The computer receives a new query including a key. Upon determining that the query-key is a problematic-key and that resolving the new query using information associated with a latest update time of the variant-table is acceptable, the computer generates a result for the new query using the variant-table. Upon determining that the query-key is a not a problematic-key or that resolving the new query using information associated with a latest update time of the variant-table is unacceptable, the computer generates a result for the new query using the data-table.
US09626395B2	Document management apparatus and recording medium A document management apparatus includes a reception unit, an operation information extraction unit, a memory, an executability determination unit, and an operation execution unit. The reception unit receives an operation request for an electronic document from an operator. The operation information extraction unit extracts operation information related to the operation request. The memory stores operation history information which is an accumulation of previous operation information which is operation information related to previous operation requests previously made for electronic documents. The executability determination unit reads the operation history information from the memory to determine whether or not an operation pertaining to the operation request is executable on the basis of the operation information and the operation history information. The operation execution unit executes the operation pertaining to the operation request in the case where the executability determination unit determines that the operation is executable.
US09626393B2	Conditional validation rules Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating conditional validation rules. One of the methods includes rendering a plurality of cells arranged in a two-dimensional grid having a first axis and a second axis, the two-dimensional grid including one or more subsets of the cells, each subset associated with a respective field of an element of the dataset, and multiple subsets of the cells extending in a direction along the second axis of the two-dimensional grid, one or more of the multiple subsets associated with a respective validation rule. The method includes applying one or more validation rules to an element of the dataset based on user input received from at least some of the cells. A condition cell associated with a field includes an input element for receiving input.
US09626392B2	Context transfer for data storage A method for context transfer for data storage is disclosed. The method includes receiving, from an analysis environment, a request to load a data item for analysis, creating, based on the request, a task request including context information of the data item, transmitting the task request to a data manager environment, receiving, from the data manager environment, an approval of the task request based on the context information, and loading the data item in a master data store in response to the approval.
US09626389B1	Data compression model for mobile device disconnected operations A method for analyzing an enterprise application linked to a mobile device application. The method includes determining that the enterprise application performs a first set of roles. The method also includes analyzing the mobile device application. The method also includes determining that the mobile device application performs a second set of roles. The method also includes receiving an input parameter at the mobile device application, and generating a mobile data structure in response to the determining that the mobile device performs the second set of roles. The method also includes receiving an indication of a planned disconnect of the mobile device application from the enterprise application. The method also includes storing, in response to the receiving the indication of planned disconnect, the generated data structure in the mobile device for disconnected execution.
US09626388B2	Metadata automated system A method can include: providing a schema definition language defining trait observations linked to an entity and the trait observations grouped together in a module with metadata; generating physical tables for the module and the entity having a link therebetween based on at least one of the trait observations; and populating the physical tables with data in accordance with the metadata.
US09626385B2	Semantic model of everything recorded with ur-url combination identity-identifier-addressing-indexing method, means, and apparatus A computer program product embodied on a non-transitory computer readable storage medium, comprising non-transitory computer executable program code configured to perform the steps of: receiving a representation of an unlabeled event; labeling the unlabeled event according to a unitary relative event ontology; and storing the labeled event in the computer readable storage medium. The unitary relative event ontology can comprise an information description vector comprising a plurality of ontological primitives, and the plurality of ontological primitives can comprise a point description element, a reference-body description element, an observer description element, a position description element, a scene description element, and a specification description element.
US09626384B2	Techniques for user customization in a photo management system A computer-implemented technique can receive a plurality of photos and automatically select a subset of the plurality of photos having a high degree of representativeness by jointly maximizing both photo quality and photo diversity to obtain a photo album. The technique can determine one or more clusters for the photo album using a hierarchical clustering algorithm, and store the photo album according to the one or more clusters. The technique can control the manner in which the photo album is displayed using the one or more clusters. The technique can adjust at least one of the one or more clusters and the automatic photo album generation based on user input. The user input can include at least one of adding, deleting, and moving a photo with respect to the one or more clusters. The technique can then re-cluster, automatically generate a new photo album, and/or adjust the presentation.
US09626380B1	Stochastic chunk-based map generation An approach to facilitating stochastic chunk-based map generation is provided. Tile chunks may be obtained for inclusion in a map of a virtual space. The obtained tile chunks may include first and second tile chunks having map tiles of different tile types. The first tile chunk may have a first tile of a first tile type and a second tile of a second tile type different from the first tile type. The second tile chunk may have a third tile of a third tile type and a fourth tile of a fourth tile type different from the third tile type. Stochastic distribution of the obtained tile chunks over a map area in the map may be effectuated. Distribution of individual map tiles between the distributed tile chunks on the map area may be effectuated.
US09626379B1	Optimistic commit processing for an offline document repository A revision request is received at a revision control system that includes a repository identifier, version summary information, and a change description. In response to receiving the revision request, a determination is made as to whether a document repository identified by the repository identifier is active or offline. If the document repository is offline, the version summary information is utilized to determine whether the revision request is probably consistent with current contents of the document repository. If the revision request is probably consistent with the current contents of the document repository, the revision request is placed into a queue, an acceptance message is transmitted in response to the revision request, the document repository is placed into an active state, and the revision request is dequeued and applied to the document repository using the change description.
US09626377B1	Cluster file system with metadata server for controlling movement of data between storage tiers A cluster file system comprises a metadata server coupled to a plurality of object storage servers via a network. The metadata server comprises a controller configured to implement storage tiering control functionality for at least first and second storage tiers comprising respective disjoint subsets of the plurality of object storage servers. The metadata server is thereby configured to control movement of data between the first and second storage tiers. The object storage servers in the first storage tier may be configured to interface with object storage targets of a first type and the object storage servers in the second storage tier may be configured to interface with object storage targets of a second type different than the first type. For example, the object storage targets of the first type may comprise non-volatile electronic storage devices such as flash storage devices, and the object storage targets of the second type may comprise disk storage devices.
US09626376B1	Local area network distributed storage Systems and methods are disclosed for managing distributed data storage. A data storage device is configured to operate in at least two modes of operation, including a first mode, in which the data storage device may sync a file directory with a corresponding file directory of a separate data storage device when the data storage devices are connected over a broadcast connection in a first local area network (LAN). In a second mode of operation, the data storage device may connect to a host device over a dedicated point-to-point connection over a second LAN when the data storage device is not connected to the first LAN.
US09626373B2	Optimizing data block size for deduplication Provided herein is technology relating to data deduplication and particularly, but not exclusively, to methods and systems for determining an efficiently optimal size of data blocks to use for backing up a data source. Also provided herein are systems for identifying duplicate data in data backup applications.
US09626367B1	Managing a backup procedure A method for managing a backup procedure is described. In one embodiment, the method includes performing a first backup of a dataset, selecting a value N, dividing the dataset into N segments, and upon writing at least the portion of the dataset to the second storage system, performing a first rewrite. Each segment of the dataset includes 1/Nth of the dataset. The first backup includes writing at least a portion of the dataset from a first storage system to a second storage system. The first rewrite includes writing a first segment of the dataset from the first storage system to the second storage system.
US09626363B2	System and method for placeshifting media playback Systems and methods of placeshifting media playback between two or more devices are provided. For example, a method for placeshifting media may include downloading onto a first device an index of files accessed or modified on a second device via a data storage server, at least one of the files being a media file played on the second device. The first device may display a user selectable list of the files on the first device before issuing a request for the media file to the data storage server. The data storage server may send the media file to the first device from the data storage server, and the first device may play back the media file where the second device left off.
US09626361B2	User-trained searching application system and method System, apparatus, user equipment, and associated computer program and computing methods are provided for suggesting websites that are relevant based on the user's browsing history and past search results. In one aspect, a hosted computer application stores the user's browsing history and search results using a cloud-based storage facility, and computing methods, using machine learning techniques, are operative to predict websites the user may want to visit next. Example machine learning techniques may be configured to use non-parsed and unstructured data to identify patterns and map hundreds of thousands of data elements, to predict which website(s) the user might like to visit in a search/browsing session. Example machine learning techniques may be further operative to recognize patterns and analyze data at each interaction with the user. The training of example machine learning techniques is driven by user interaction, allowing the removal of non-relevant or less relevant websites from the suggested websites via a suitable user interface.
US09626360B2	Analyzing web site for translation A system, method and computer readable medium for synchronizing web content is disclosed. The method includes retrieving a first web content in a first language from a web site, the first web content corresponding to a second web content wherein the second web content is a translation in a second language of the first web content. The method further includes dividing the first web content into a plurality of translatable components and generating a unique identifier for each of the plurality of translatable components. The method further includes matching each of the plurality of translatable components to a plurality of translated components of the second web content using the unique identifier of each of the plurality of translatable components. If a translatable component is not matched to a translated component, the method further includes designating the translatable component for translation into the second language.
US09626359B1	Dynamic data encapsulating systems A proxy that encapsulates computer code transmitted between a client and a server is disclosed. The proxy encapsulates one portion of the computer code within another portion of computer code, such as encapsulating Javascript within HTML or encapsulating Javascript within VBScript within HTML. The proxy could selects portions of the computer code to encapsulate in accordance with a selective algorithm or a randomizer, and could randomize function names that are executed to produce the encapsulated code. If the proxy detects a response from a client that is malformed, the proxy could trigger appropriate security measures to adjust communication protocols with the client.
US09626358B2	Creating ontologies by analyzing natural language texts Systems and methods for creating ontologies by analyzing natural language texts. An example method comprises: receiving a plurality of semantic structures associated with a text corpus; identifying a first semantic structure and a second semantic structure, wherein the first semantic structure comprises a first substructure and a second substructure, wherein the second semantic structure comprises a third substructure and a fourth substructure, and wherein the first substructure is similar to the third substructure in view of a first similarity criterion; and responsive to determining that the second substructure is similar to the fourth substructure in view of a second similarity criterion, associating, with a certain concept of an ontology associated with the text corpus, objects represented by the second substructure and the fourth substructure.
US09626356B2	System support for evaluation consistency A system and computer product for validating the consistency between quantitative and natural language textual evaluations. An example method involves computing a numeric score for a textual evaluation, comparing the numeric score to a quantitative evaluation, and producing a rating based on the similarity of the two evaluations.
US09626353B2	Arc filtering in a syntactic graph The present disclosure provides methods and systems for performing syntactic analysis of a text. In some implementations the method includes performing rough syntactic analysis of the text, generating a graph of generalized constituents of the text and filtering arcs of the graph of generalized constituents with a combination classifier which includes a tree classifier and one or more linear classifiers. The combination classifier is trained using parallel analysis of an untagged two-language text corpus.
US09626350B2	Date picker in excel In various embodiments, methods, systems, and non-transitory computer-readable media are disclosed that allow developers to place date pickers on columns, rows, and cells using a desktop integration framework. The date picker can be tied to components, forms, or model metadata. In one aspect, date picker metadata is provided separately from the document to which one or more date pickers will eventually be added.
US09626342B2	Dynamic page generator An custom page server is provided with user preferences organized into templates stored in compact data structures and the live data used to fill the templates stored local to the page server which is handing user requests for custom pages. One process is executed on the page server for every request. The process is provided a user template for the user making the request, where the user template is either generated from user preferences or retrieved from a cache of recently used user templates. Each user process is provided access to a large region of shared memory which contains all of the live data needed to fill any user template. Typically, the pages served are news pages, giving the user a custom selection of stock quotes, news headlines, sports scores, weather, and the like. With the live data stored in a local, shared memory, any custom page can be built within the page server, eliminating the need to make requests from other servers for portions of the live data. While the shared memory might include RAM (random access memory) and disk storage, in many computer systems, it is faster to store all the live data in RAM.
US09626339B2	User interface with navigation controls for the display or concealment of adjacent content A computerized system including a graphical interface is provided for storing, retrieving, and displaying individual sentences or subunits of a data source as stand-alone entities, independent of how they are ordered within the source document. The graphical user interface provides an interactive display that allows a user to dynamically develop his or her own context for displayed document subunits, such as sentences, by means of incremental displays of surrounding material or of material related by other relations or criteria, so that relevant sentences or subunits from a single source or different sources can be retrieved, aggregated, compared, and displayed along with context specifically tailored for each user-relevant sentence or subunit as appropriate.
US09626334B2	Systems, apparatuses, and methods for K nearest neighbor search Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.
US09626326B2	Data storage expanding apparatus A data storage expanding apparatus is electrically coupled to a terminal equipment and multiple data storage groups. Each data storage group includes a plurality of data storage devices. The data storage expanding apparatus configured to transmit an operating data between the terminal equipment and to a particular data storage device. The data storage expanding apparatus includes a data storage expanding module and multiple signal expanding modules. The data storage expanding module is electrically coupled to the terminal equipment. The signal expanding modules are electrically coupled in series, and to the data storage groups, respectively. One of the signal expanding modules is electrically coupled to the data storage expanding module. The operating data signal is transmitted to the signal expanding module via the data storage expanding module electrically connected to the signal expanding module, and then transmitted to particular data storage device via the signal expanding module.
US09626324B2	Input/output acceleration in virtualized information handling systems Methods and systems for I/O acceleration on a virtualized information handling system include loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation.
US09626316B2	Managing shared resources between multiple processing devices In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.
US09626313B2	Trace buffer based replay for context switching A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more operations in the command stream in a trace buffer, wherein the first set of one or more operations accesses one or more memory locations in memory, and wherein the data include an indication of contents of the one or more memory locations associated with the first set of one or more operations. The command processor may interrupt the processing of the command stream. The command processor may, in response to resuming processing of the command stream subsequent to the interrupting of the processing of the command stream, replay at least a portion of the command stream, including processing a second set of one or more operations of the command stream based at least in part on the data stored in the trace buffer.
US09626312B2	Storage region mapping for a data storage device A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a second meta-block if the storage size associated with the first group is less than the threshold storage size. The second meta-block includes a respective block of each data storage die of the first group and further includes a respective block of each data storage die of the second group. Each data storage die of the second group is associated with a second priority.
US09626311B2	Memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
US09626308B2	Method and apparatus for improving decreasing presentation latency in response to receipt of latency reduction mode signal Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09626301B2	Implementing advanced caching Embodiments are disclosed for implementing a priority queue in a storage device, e.g., a solid state drive. At least some of the embodiments can use an in-memory set of blocks to store items until the block is full, and commit the full block to the storage device. Upon storing a full block, a block having a lowest priority can be deleted. An index storing correspondences between items and blocks can be used to update priorities and indicated deleted items. By using the in-memory blocks and index, operations transmitted to the storage device can be reduced.
US09626298B2	Translation of input/output addresses to memory addresses An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
US09626296B2	Prefetch list management in a computer system Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
US09626295B2	Systems and methods for scheduling tasks in a heterogeneous processor cluster architecture using cache demand monitoring Systems, methods, and computer programs are disclosed for scheduling tasks in a heterogeneous processor cluster architecture in a portable computing device. One embodiment is a system comprising a first processor cluster and a second processor cluster. The first processor cluster comprises a first shared cache, and the second processor cluster comprises a second shared cache. The system further comprises a controller in communication with the first and second processor clusters for performing task migration between the first and second processor clusters. The controller initiates execution of a task on a first processor in the first processor cluster. The controller monitors a processor workload for the first processor and a cache demand associated with the first shared cache while the task is running on the first processor in the first processor cluster. The controller migrates the task to the second processor cluster based on the processor workload and the cache demand.
US09626294B2	Performance-driven cache line memory access According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.
US09626292B2	Memory tile access and selection patterns In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
US09626291B2	Lock-free, scalable read access to shared data structures using garbage collection At least one read operation of at least one object of a data container is initiated. The data container includes an anchor object, a first internal data object and a first garbage collection object, the anchor object comprising a pointer to a versioned structure tree. Thereafter, in response to the at least one incompatible write operation, a second internal data object and a second garbage collection object are created for the data container. The second garbage collection object has a reference to the second internal data object. Subsequently, the second internal data object is installed in the anchor object and the first garbage collection object is passed to a garbage collection process so that space used by the first garbage collection object in a database can be reused. Related apparatus, systems, techniques and articles are also described.
US09626290B2	Memory channel connected non-volatile memory An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
US09626289B2	Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock.
US09626287B2	Solid state memory formatting The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.
US09626285B2	Storage resource allocation to dataflows based on data requirements and attributes There is provided with a resource allocation apparatus. An attribute indicating a requirement for a data storage resource to be allocated to a plurality of data flows to which the attribute is provided beforehand is acquired. A data flow relationship graph indicating a relationship between the plurality of data flows which potentially lead to access contention in the data storage resource is generated. Based on the attribute and the data flow relationship graph, allocation of the data storage resource to the plurality of data flows is determined such that no access contention occurs.
US09626278B2	Streaming breakpoint for data tuples based on resource usage A streams manager monitors data tuples processed by a streaming application represented by an operator graph. The streams manager includes a tuple breakpoint mechanism that allows defining a tuple breakpoint that fires based on resource usage by the data tuple. When the tuple breakpoint fires, one or more operators in the operator graph are halted according to specified halt criteria. Information corresponding to the breakpoint that fired is then displayed. The tuple breakpoint mechanism thus provides a way to debug a streaming application based on resource usage by data tuples.
US09626275B1	Dynamic rate adjustment for interaction monitoring Methods and systems for implementing dynamic rate adjustment for interaction monitoring are disclosed. At an entity, the collection of trace information is initiated according to a first sampling rate. The trace information is indicative of interactions between the entity and one or more additional entities. A second sampling rate is determined based at least in part on information external to the entity. The second sampling rate is determined after the collection of the trace information is initiated at the entity according to the first sampling rate. At the entity, the collection of additional trace information is initiated according to the second sampling rate.
US09626270B2	Link retraining based on runtime performance characteristics Systems and methods may provide for monitoring one or more runtime performance characteristics of a link and determining a state of the link based on at least one of the one or more runtime performance characteristics. Additionally, a retraining of the link may be automatically scheduled based on the state of the link. In one example, scheduling the retraining of the link further includes setting one or more retraining parameters.
US09626268B2	Controlling a byte code transformer on detection of completion of an asynchronous command Controlling a byte code transformer on detection of completion of an asynchronous command. An asynchronous command is received by an asynchronous manager from a test framework. The asynchronous command manager issues the asynchronous command to an application. A transformer is loaded for transforming byte code associated with the application in order to output one or more method names and associated timestamps of one or more method entry points and one or more method exit points. A check is made as to whether an expected result has been generated by the application. In response to determining that an expected result has been successfully generated, a time period associated with successful generation of the expected result is compared with the timestamps in order to determine matching timestamps and associated matching method names. The transformer is modified in accordance with the matching method names such that a subsequent transformation executes on byte code associated with the matching method names.
US09626265B2	Efficiency of cycle-reproducible debug processes in a multi-core environment An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
US09626264B2	Memory device test apparatus and method having multiple memory devices connected to downstream ports of a PCI express switch at the same time Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.
US09626262B1	Primary role reporting service for resource groups Methods and apparatus for a primary role reporting service for resource groups are disclosed. A reporting intermediary assigned to a resource group of a network-accessible service receives role information indicating the identity of a primary member of the group from a state manager of the network-accessible service. The intermediary receives a health status query pertaining to the resource group from a health checking subsystem used by a network address discovery service, and provides a health status response based on the role information. The response provided by the reporting intermediary is used by the network address discovery service to provide a network address in response to a lookup query for the resource group.
US09626259B2	Auxiliary power supply and user device including the same A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).
US09626258B2	Systems, methods, and apparatus related to wireless charging management Various systems, methods, and apparatuses for operating a wireless charging device in an electric vehicle are disclosed. One method includes detecting a system fault indicative of one or more faults in the wireless charging device in the electric vehicle or in the transmitter. The method further includes determining a fault severity level from a plurality of fault severity levels based on a type of the system fault detected. A total number of types of system faults can be greater than a total number of the plurality of fault severity levels. The method further includes performing one or more system fault response operation based on the determined fault severity level. Each of the plurality of fault severity levels can be associated with a different set of system fault response operations.
US09626255B2	Online restoration of a switch snapshot One embodiment of the present invention provides a switch. The switch includes one or more ports, a persistent storage module, a restoration module, and a retrieval module. The persistent storage module stores configuration information associated with the switch in a data structure, which includes one or more columns for attribute values of the configuration information, in a local persistent storage. The restoration module instantiates a restoration database instance in the persistent storage from an image of the persistent storage. The retrieval module retrieves attribute values from a data structure in a current database instance and the restoration database instance in the persistent storage. The restoration module then applies the differences between attribute values of the restoration database instance and the current database instance in the persistent storage to switch modules of the switch, and operates the restoration database instance as the current database instance in the persistent storage.
US09626254B2	Backup and non-staged recovery of virtual environment data Methods for creating backup of data of a virtual environment to allow non-staged recovery are described. The described method may include receiving data of a virtual environment through one or more data streams for backup. The method also includes generating metadata corresponding to the received data and storing the received data at a first location of a backup storage unit. Further, the method includes storing the generated metadata at a second location of the backup storage unit, where the second location is different from the first location of the backup storage unit. The method further includes mapping the at least one predefined file to the stored data to create a mapping table to allow direct access to the stored data for non-staged recovery.
US09626251B2	Undo configuration transactional compensation A method of for system management, comprising initiating a workflow operating on a processor. Initiating a sub-workflow operating on the processor from the workflow. Electronically reading state data for one or more resources designated by the sub-workflow prior to performing a first logical process of the sub-workflow. Storing the state data in a non-transient data memory. Performing logical processes associated with the sub-workflow using the processor. Restoring the state data for the one or more resources if it is determined that an error has occurred.
US09626250B2	Data synchronization of block-level backup As disclosed herein a computer program product for optimizing data synchronization when performing a block-level backup includes program instructions comprising instructions to receive a customized merging plan, create a padding map comprising missing data information, request missing data from a local backup server, wherein the instructions to request missing data comprise instructions to send the padding map to the local backup server, receive from the local backup server the missing data, and perform a snapshot consolidation according to the customized merging plan to provide a consolidated snapshot. The program instructions may include instructions to record missing data files and data blocks in the padding map. A computer system, corresponding to the computer program product is also disclosed herein.
US09626243B2	Data error correction device and methods thereof A method and device for error detection includes performing error detection for each data word received in a burst access to a memory. When no error is detected, the data words are written to a cache and indicated as valid data. In response to detecting an error in a data word, the error is corrected and the corrected data written to the cache without indicating the data as valid. In addition, the location of the detected error, indicating the data symbol associated with the error, is recorded in an error vector. The error vectors associated with each data word in the burst access are compared to determine whether a detected error was properly corrected.
US09626242B2	Memory device error history bit Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.
US09626234B2	Inter-processor communication techniques in a multiple-processor computing platform This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.
US09626232B2	Event queue management Queue storage queues event entries from a hardware event detector that are to be communicated to a software event handler. An event register stores a most recently received event entry. A comparator compares a newly received event entry with the content of the event register and if a match occurs, then these event entries are merged by setting a merged entry bit and discarding the newly received event entry. When a non-matching event entry is received, then the unqueued event within the event register is stored into the queue storage. If the queue storage is empty, then the event register and the comparator are bypassed. When the queue storage becomes empty, then any currently unqueued event within the event register is stored into the queue storage. The event entries may be translation error event entries in a system which translates between virtual addresses and physical addresses.
US09626231B2	Database dispatcher Example methods and systems are directed to dispatching database tasks. An application may access data associated with a task. The data may indicate features (e.g., processing functionality) that will be used to complete the task. The application may determine whether all such features are implemented in the database layer. The application may dispatch the task to the database layer if all features are implemented therein. The application may perform the task in the application layer if one or more of the features are not available in the database layer. In some example embodiments, the task involves materials requirements planning. Such a task may include determining, for a given bill of materials (“BOM”), the quantity of materials available on-hand, the quantity available from suppliers, the transport or delivery time for the various quantities, and other data regarding the BOM.
US09626227B2	Technologies for offloading and on-loading data for processor/coprocessor arrangements Technologies for transferring offloading or on-loading data or tasks between a processor and a coprocessor include a computing device having a processor and a sensor hub that includes a coprocessor. The coprocessor receives sensor data associated with one or more sensors and detects events associated with the sensor data. The coprocessor determines frequency, resource usage cost, and power state transition cost for the events. In response to an offloaded task request from the processor, the coprocessor determines an aggregate load value based on the frequency, resource usage cost, and power state transition cost, and determines whether to accept the offloaded task request based on the aggregate load value. The aggregate load value may be determined as an exponential moving average. The coprocessor may determine whether to accept the offloaded task request based on a principal component analysis of the events. Other embodiments are described and claimed.
US09626221B2	Dynamic guest virtual machine identifier allocation An example method of updating a virtual machine (VM) identifier (ID) stored in a memory buffer allocated from guest memory includes supplying firmware to a guest running on a VM that is executable on a host machine. The firmware includes instructions to allocate a memory buffer. The method also includes obtaining a buffer address of the memory buffer. The memory buffer is in guest memory and stores a VM ID that identifies a first instance of the VM. The method further includes storing the buffer address into hypervisor memory. The method also includes receiving an indication that the VM ID has been updated. The method further includes using the buffer address stored in hypervisor memory to update the VM ID.
US09626216B2	Graphics processing unit sharing between many applications A technique for executing a plurality of applications on a GPU. The technique involves establishing a first connection to a first application and a second connection to a second application, establishing a universal processing context that is shared by the first application and the second application, transmitting a first workload pointer to a first queue allocated to the first application, the first workload pointer pointing to a first workload generated by the first application, transmitting a second workload pointer to a second queue allocated to the second application, the second workload pointer pointing to a second workload generated by the second application, transmitting the first workload pointer to a first GPU queue in the GPU, and transmitting the second workload pointer to a second GPU queue in the GPU, wherein the GPU is configured to execute the first workload and the second workload in accordance with the universal processing context.
US09626212B2	Live migration of virtual machines with memory state sharing Embodiments described herein rapidly migrate child virtual machines (VM) by leveraging shared memory resources between parent and child VMs. In a first, proactive phase, parent VMs are migrated to a plurality of potential target hosts. In a second, reactive phase, after a request is received to migrate a child VM to a selected target host, memory blocks that are unique to the child VM are migrated to the selected target host. In some examples, memory blocks are compressed and decompressed as needed. In other examples, the operation environment is modified. Aspects of the disclosure offer a high performance, resource efficient solution that outperforms traditional approaches in areas of software compatibility, stability, quality of service control, resource utilization, and more.
US09626207B2	Managing configuration and system operations of a non-shared virtualized input/output adapter as virtual peripheral component interconnect root to single function hierarchies A computer implemented method of managing an adapter includes determining that an adapter is assigned to an operating system and generating a single root input/output virtualization (SR-IOV) function associated with the adapter. The SR-IOV function may be correlated to a non-SR-IOV function, and the non-SR-IOV function may be used to modify an operational status of the adapter.
US09626205B2	Hypervisor driven embedded endpoint security monitoring Aspects of the present disclosure are directed to methods and systems of hypervisor driven embedded endpoint security monitoring. A computer implemented method may include providing one or more computer processors configured to operate a bare-metal hypervisor; launching a user OS virtual machine operatively connected to the hypervisor; launching a security virtual machine operatively connected to the hypervisor and receiving data from the security virtual machine via the hypervisor; and receiving data representative of security information from the computer processor processed by the security virtual machine. The hypervisor may include using a virtual switch for providing communications between the user OS virtual machine and the security virtual machine. The method may include using the security virtual machine to monitor malware on the user OS virtual machine.
US09626202B2	Parallel processing of data A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.
US09626200B2	Electronic device mode detection In embodiments of electronic device mode detection, a mode detection application, implemented on an electronic device, correlates an identifier of a wireless device and an activity of the electronic device based at least in part on multiple instances of detecting the identifier of the wireless device during the activity of the electronic device. In some embodiments, the mode detection application correlates the identifier of the wireless device and the activity of the electronic device based at least in part on the identifier of the wireless device not being detected during one or more different activities of the electronic device. After correlating the identifier of the wireless device and the activity of the electronic device, the mode detection application configures the electronic device to automatically switch to a mode associated with the activity responsive to detecting the identifier of the wireless device.
US09626199B2	Techniques for overlaying a custom interface onto an existing kiosk interface utilizing non-visible tags into screen definitions of the existing interface Techniques for overlaying a custom interface onto an existing kiosk interface are provided. An event is detected that triggers a kiosk to process an agent that overlays, and without modifying, the kiosk's existing interface. The agent alters screen features and visual presentation of the existing interface and provides additional alternative operations for navigating and executing features defined in the existing interface. In an embodiment, the agent provides a custom interface overlaid onto the existing interface to provide a customer-facing interface for individuals that are sight impaired, and the method further comprises injecting non-visible tags into screen definitions for the existing interface that are recognized only by the agents to handle exception conditions and actively ignored by the existing interface.
US09626197B1	User interface rendering performance Disclosed are various embodiments for improving user interface rendering performance. A network page is generated that is configured to defer loading of control code associated with a user interface component. The network page includes code that renders an initial view of the user interface component. The code that renders the initial view is configured to obtain one or more events generated by one or more user interactions with the initial view. The code that renders the initial view is further configured to obtain additional code in response to obtaining the one or more events. The code that renders the initial view is further configured to process the one or more events by executing the additional code.
US09626196B2	Broadcasting management information using fountain codes Technologies for broadcasting management information include a management server and a number of client devices. The management server encodes management data such as a certificate revocation list into a number of message fragments using a fountain code encoding algorithm and broadcasts the message fragments continually over a network. Each client device analyzes the network during a boot process to receive the broadcast message fragments. Each client device decodes the message fragments using a fountain code decoding algorithm and determines whether the message is complete. If the message is complete, the client device parses the message to retrieve the management data and may install the management data on the client device. If the message is incomplete, the client device may store the message fragments in nonvolatile storage for processing during future boot events. The client device may perform those operations in a pre-boot firmware environment. Other embodiments are described and claimed.
US09626195B2	Booting system A booting system includes a control module, a voltage regulation module, a complex programmable logic device (CPLD), and a power supply unit (PSU). The control module is configured to output a booting signal. The CPLD is coupled to the control module for receiving the booting signal and is configured to sense status of the voltage regulation module, a power control signal is outputted from the CPLD when the CPLD receives the booting signal and status of the voltage regulation module are normal. The PSU is coupled to the CPLD for receiving the power control signal from the CPLD and outputs a power signal for booting up a computer.
US09626194B2	Thread livelock unit Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
US09626193B2	Coalescing adjacent gather/scatter operations According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
US09626187B2	Transactional memory system supporting unbroken suspended execution Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
US09626186B2	Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
US09626182B2	System and method for tracking suspicion across application boundaries A method, computer program product, and computer system for receiving, from a first and second application by a computing device, shapes of artifacts and components of the first and second application. The shapes of the artifacts and components of the first and second application are conformed to a standard format. One or more changes to the shapes of the artifacts and components of the first and second application are tracked. One or more suspicious relationships across the first and second application are displayed based upon, at least in part, the one or more changes to the shapes of the artifacts and components of the first and second application.
US09626179B2	Method and system for using a ROM patch A method and system for using a ROM patch are provided. In one embodiment, a computing device obtains an original assembly code and a modified assembly code which is a modified version of the original assembly code, the original assembly code being used for an executable code which is stored in a ROM of a device. The computing device compares the original assembly code and the modified assembly code to identify difference(s) in the modified assembly code with respect to the original assembly code. The computing device then compiles the difference(s) (sometimes, after adjusting the differences) and generates a ROM patch by converting the compiled difference(s) into a replacement executable code for some of the executable code stored in the ROM of the device. In another embodiment, a method and system for using a ROM patch are disclosed.
US09626178B2	Method and apparatus for auto installing applications into different terminals An apparatus and method of automatically installing an application in different terminals by storing terminal information of a user and allowing the user to install an application when the user installs an application in at least two terminals, and in which an installation process may be automatically conducted is provided. Information related to an application installed in a first terminal is received from the first terminal; and a second terminal is requested to install another application corresponding to the application, in the second terminal, by using the received information related to the application.
US09626177B1	Peer to peer upgrade management A method and apparatus for updating an application on a group of nodes is presented. According to one embodiment, an application is updated at a first node. The first node updates a registry to indicate that an update was performed at the first node and propagates the update to the registry to one or more second nodes. At a second node, the second node determines that one or more application updates are available at the first node. Upon such a determination, the second node requests one or more update packages from the first node. Based on an update policy associated with the second node, the second node updates the application using the one or more update packages.
US09626176B2	Update installer with technical impact analysis An update installer generates an update display for a user that allows a user to select updates in an identified environment. The update installer accesses the objects and layers in the identified environment and displays an impact display identifying portions of the identified environment that will be affected by the selected updates, before the updates are installed.
US09626173B1	Non specification supported application deployment descriptors and web application deployment descriptors A method is described that inserts first and second deployment descriptors into an application archive file. The first deployment descriptor conforms to a first document type definition that is defined by a standard specification. The second deployment descriptor conforms to a second document type definition that is not defined by the standard specification. The second deployment descriptor has an element that is directed to a service that is an extension to the services offered by an environment described by the standard specification. The first and second deployment descriptors provide configuration information selected from the group consisting of: a) configuration information that pertains to the application as a whole; and, b) configuration information that pertains to a web application portion of the application.
US09626171B2	Composing a module system and a non-module system A bridge module is generated to bridge standard modules in a module system and non-module code in a non-module system. The bridge module includes explicit dependencies associated with a namespace, such as a dependency path corresponding to the non-module code. The bridge module exposes packages of the non-module code at least to the standard modules. Operations are performed on a code base that uses standard modules, bridge modules, and non-module code.
US09626165B1	Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language A method for generating a description of a systolic array includes prompting a user to input information about the systolic array. A high-level synthesis language is generated that describes channels of processing elements of the systolic array and a topology of the processing elements in response to the information provided by the user.
US09626158B1	Dynamic availability-based integration of external functionality A system includes a user interface allowing a developer to select a function to supplement functionality of an application under development. A data store holds identifiers for functions representing external functionality available from third party applications. A code generation module provides a software object to the developer for incorporation into a state of the application. The state includes a user interface element associated with an entity. When the state is instantiated, an action query is transmitted to a search system with the unique identifier of the selected function and information about the entity. The user interface element is selectively visually adapted in response to the search system response. In response to user selection of the user interface element, a search result, the search system is displayed, including (i) an identifier of a target application and (ii) an access mechanism for a specified state of the target application, is displayed.
US09626157B2	Method of projecting a workspace and system using the same A method of projecting a workspace includes the following steps. Firstly, a projectable space instance which is instantiated from a unified script is provided through a URI (uniform resource identifier). The unified script is defined to configure at least one of an matterizer, information and tool to model a workspace. The projectable space instance is used for building a projected workspace corresponding to the workspace so as to provide an interface for operating at least one of the matterizer, the information and the tool to perform a task. Then, a projector is used to parse the projectable space instance and build a working environment to configure at least one of the matterizer, the information and the tool. Consequently, the projected workspace is executed for providing interaction between at least one user and the projected workspace.
US09626155B2	Determining recommended optimization strategies for software development In one example, a device for recommending an optimization strategy for software includes a memory storing data for a sparse matrix including empty cells and non-empty cells, wherein non-empty cells of the sparse matrix represent ratings for optimization strategies previously applied to programs, and one or more hardware-based processors configured to predict values for empty cells of a sparse matrix, fill the empty cells with the predicted values to produce a complete matrix, determine, for a current program that was not included in the programs of the sparse matrix, a recommended optimization strategy that yields a highest rating from the complete matrix, and provide an indication of the recommended optimization strategy.
US09626148B2	Creating an event driven audio file In one example, a device for creating an event-driven audio file may comprise a processor and an audio engine to, when executed by the processor, receive a configuration file designating a number of device-external data feeds and create an event-driven audio file based on the configuration file. In an example, a method of creating event-driven audio may comprise creating, with a processor, a configuration file, the configuration file comprising links defining device-external data feeds and with an audio engine, parsing the configuration file, and, based on the data defined in the configuration file, creating an event-driven audio file.
US09626147B2	Method for controlling a display apparatus, sink apparatus thereof, mirroring system thereof A display device controlling method, a sink device thereof, and a mirroring system thereof are provided. The display device controlling method includes receiving metadata and media data for mirroring a screen image at a sink device from a source device, if a request is received, determining whether the request is an independent request for requesting to perform an operation of the sink device independent from an operation of the source device, or a dependent request for requesting to perform an operation of the sink device dependent to an operation of the source device, and, if the request is an independent request, carrying out the request at the sink device. When the request is input to the sink device, an operation desired by a user may be quickly performed.
US09626144B2	Computer system A computer system includes a display, a user input interface connected to at least one input device, an external device interface for exchanging data with an external device, a network interface for connection to a wired/wireless network, and a controller for, when electronic devices connected to the same network are detected in a booting, controlling the display to display a dual control screen for a dual control mode for control of the detected electronic devices through the input device. Accordingly, it is possible to provide a user interface environment in which several electronic devices may be controlled by an input device used in one of the electronic devices and the other electronic devices may be easily controlled by the input device, thereby enhancing user convenience.
US09626142B2	Automated model selection A server is configured to store a library of printable content and to select an item from the library in response to a user request. Instead of the user specifying a particular item, the server can automatically select from a number of different items. The server may automatically determine a printer type for the user and select a suitable, corresponding model for immediate fabrication by the printer.
US09626138B2	Reconstruction of suspended print jobs System and methods for reconstructing a suspended print job. In one embodiment, a print controller receives a print job, and initiates construction of a sheet based on logical pages of the print job. Print controller determines a sheet number for the sheet that identifies a page number of one or more logical pages related to the construction of the sheet, an offset for the sheet that identifies an order of the sheet with respect to other sheets that share the sheet number. Print controller also assigns a sheet identifier to the sheet that includes the sheet number and the offset, and receives the sheet identifier in response to a determination to resume the print job from a suspended state. Print controller initiates processing for resuming the print job from the sheet based on the sheet number and the offset in the sheet identifier.
US09626136B2	Image forming apparatus, image forming system, and non-transitory storage medium An image forming apparatus comprising: a receiver for receiving a print job; a printing unit; a storage unit; an input interface for receiving a print execution command from a user; a power source for supplying an electric power; and a controller configured to: control the power source to stop or reduce the power supply to the printing unit when the receiver has not received a next print job within an after-printing standby time from completion of the printing; and control the power source to stop or reduce the power supply to the printing unit when the print job is a print-execution-command-input required print job requiring the print execution command and the receiver has not received a next print job within an after-print-job-receipt standby time from the receipt of the print-execution-command-input required print job, the after-print-job-receipt standby time being longer than the after-printing standby time.
US09626133B2	Information processing apparatus control method and storage medium When an information processing apparatus displays an icon of a group of a plurality of peripheral devices, the apparatus displays on a home screen an icon of a peripheral device intended by a user, separately from the one icon of the group of the peripheral devices. Further, on the home screen, an icon of a device selected by the user on a screen of a device management application managing the peripheral devices is displayed.
US09626132B2	Printing device, printing method, computer program product, and recording medium A printing device includes a print data management unit that is capable of storing and managing print data so as to be associated with corresponding identification information used in user identification; an identification information storing unit that stores the identification information; a receiving unit that receives the print data; an identification information obtaining unit that obtains the identification information included in the print data; a registration determining unit that determines whether the obtained identification information is already registered in the identification information stored in the identification information storing unit; an identification information registering unit that registers in the identification information storing unit the obtained identification information when the registration determining unit determines that the obtained identification information is unregistered; and a print data storing unit that stores the received print data in the print data management unit so as to be associated with the obtained identification information.
US09626129B2	Storage system A computer system is provided which includes a host computer having a volume, a storage apparatus including a storage media, the storage apparatus providing a RAID group configured by the storage media, a logical volume configured by the RAID group, a pool configured by the logical volume, and a virtual volume allocated from the pool and corresponding to the volume of the host computer. The computer system also includes a management server to store performance information regarding the logical volume and/or RAID group and mapping information regarding a relationship among components of the computer system in view of logical and physical connections. The management server determines whether a correspondence relationship exists among the components by referring to the performance information, and outputs a relationship among the components based on the determination of the correspondence relationship and the mapping information.
US09626126B2	Power saving mode hybrid drive access management A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A drive access system, which is typically part of an operating system of a computing device, issues input/output (I/O) commands to the hybrid drive to store data to and retrieve data from the hybrid drive. The drive access system supports multiple priority levels and obtains priority levels for groups of data identified by logical block addresses (LBAs). The LBAs read while the device is operating in a power saving mode are assigned a priority level that is at least the lowest of the multiple priority levels supported by the device, increasing the likelihood that LBAs read while the device is operating in the power saving mode are stored in the performance part of the hybrid drive.
US09626125B2	Accounting for data that needs to be rebuilt or deleted A method begins by a dispersed storage (DS) processing module identifying a plurality of encoded data slices requiring rebuilding. The method continues with the DS processing module determining an amount of reserve memory required for storage of rebuilt slices for the identified plurality of encoded data slices requiring rebuilding. The method continues with the DS processing module updating memory utilization information to include the amount of reserve memory required. The method continues with the DS processing module indicating the memory utilization. The method continues with the DS processing module obtaining rebuilt slices. The method continues with the DS processing module storing the rebuilt slices in the memory and updating the memory utilization information.
US09626117B2	Computer system and management method for computer system A computer system, having: a storage apparatus having: a storage volume constructed by a physical resource; a host computer having a storage volume assigned from the storage apparatus; management computers having: a first management computer configured to manage the storage apparatus; and a second management computer configured to manage the host computer, the second management computer including: first template information for identifying a change that occurs in the host configuration information; and management subject resource relationship information, the first management computer being configured to notify, before the management operation accompanying the configuration change is carried out for the storage apparatus, the second management computer of a change that occurs in the storage configuration information, the second management computer being configured to identify the change that occurs in the host configuration information based on the change that occurs in the storage configuration information notified by the first management computer.
US09626116B1	Distributed service level objective management in active-active environments Techniques are described for determining I/O workload. A first device of a first data storage system and a second device of a second data storage system are configured as synchronous mirrored devices of a first logical device. The host issues I/O operations to the first logical device over first and second paths. First I/O workload information is determined for a first data portion of the first logical device. Second I/O workload information is determined for the first data portion. The first I/O workload information and the second I/O workload information each include a first number of read operations that is a sum of read operations directed to the first logical device over both the first path and the second path. Data storage optimizations are performed on the first data storage system using the first I/O workload information and/or the second data storage system using the second I/O workload information.

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