| Document | Document Title |
|---|---|
| US09627831B1 |
Rotating contact ring with legs extending at an angle to a lower surface of the ring
A rotating contact device is described. The rotating contact device can include a contact ring and a pair of legs extending from a lower ring surface of the contact ring. Along an upper ring surface of the contact ring can be disposed one or more raised contacts. The rotating contact device can also include an inside contact held within an inside of the contact ring. Application of a downwards force on the upper ring surface of the contact ring causes the pair of legs to deflect and the contact ring and the inside contact to rotate and translate. When mated with opposing contacts, this rotation can function to radially wipe the opposing contacts and the upper ring surface. |
| US09627826B2 |
Power connector assembly with contacts conveniently soldered to cable wires
A power connector assembly (100) includes a cable (7) including a number of wires (70), an insulative housing (1), and a number of electrical contacts (2). The electrical contacts include at least one detection contact (22) and plural contacts (21). Each of the plural contacts includes a pair of mating portions (211), a pair of middle portions (212) extending rearwardly from the mating portions respectively, a connecting portion (213) connected with the middle portions, and a first soldering portion (214) connected with the connecting portion. The at least one detection contact includes a second soldering portion (223). Each of the first soldering portions and the second soldering portion includes a soldering area soldered to respective one of the wires, and all of the soldering areas are disposed at a common horizontal plane, arranged in a straight line, and soldered to corresponding wires at same time. |
| US09627820B2 |
Power entry and distribution for network processing systems
Power entry and distribution for network communication systems are disclosed. For certain embodiments depicted, a power distribution board with an open-grid configuration receives power feed/return lines from a power entry connector and distributes the power feed/return lines for a network processing system. The open-grid configuration facilitates airflow through a chassis and thereby provides improved cooling. Further, a modular power entry connector can be used to facilitate connection of power feed/return cables to the chassis for the network processing systems while improving safety for high power implementations. |
| US09627819B2 |
Insulation insert with an integrated shielding element
The invention relates to an insulation insert that can be inserted into a plug-in connector housing (11) of a plug-in connector (10), wherein in the insulation insert (1), at least one contacting element for electrically contacting a conductor core of a cable (12) to be connected may be provided, wherein the insulation insert (1) is provided in one area with a conductive coating, wherein the coated area forms a shielding element (3) that can be electrically contacted with a shielding braid of the cable (12) to be connected and at the same time with the plug-in connector housing (11), and wherein the insulation insert (1) and the shielding element (3) are integrally formed in. |
| US09627818B1 |
Electrical connector fixed to circuit board
An electrical connector is fixed to a circuit board, and includes an inner insulating body and terminal modules. The inner insulating body includes a docking portion and a mounting portion. Each module has a carrier and terminals. The carrier is disposed on the mounting portion. The contacts are formed from a metal film and fixed to the carrier. Each terminal has a mating portion, a tail portion and a base portion connected between the mating portion and the tail portion. The mating portion extends from outside the carrier to inside the mating hole. The tail portion extends from outside the carrier to a surface of the circuit board. Each tail portion of a portion of the terminals has a soldering surface attached to the surface of the circuit board and a soldering pin passing through the surface of the circuit board respectively. |
| US09627817B2 |
Electrical connector having a good high frequency transmission performance
An electrical connector includes an insulating body, multiple terminals received in the insulating body, and a metal member fixed to the insulating body. The terminals includes at least one ground terminal. The metal member has a first section and a second section. The second section is higher than the first section. The first section has at least one first elastic piece, the second section has at least one second elastic piece. The first elastic piece and the second elastic piece contact with a same terminal of the at least one ground terminal. |
| US09627816B2 |
High speed grounded communication jack
A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, forming a shielding case surrounding the housing, forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing. |
| US09627815B2 |
Receptacle connector for cable
A receptacle connector assembly has a first shell including a plurality of side walls, a receiving cavity surrounded by the side walls and extending therethrough along a front-to-back direction. A number of spring fingers are formed on the respective side walls and protruding inwardly into the receiving cavity. A number of punched holes receiving the respective spring fingers communicate with the receiving cavity. An insulative body includes a base assembled to the first shell and a tongue extending forwardly therefrom. The tongue is received in the receiving cavity and has a top face and a bottom face disposed in a vertical direction. A number of contacts are arranged in a side-by-side manner along a transverse direction perpendicular to the front-to-back direction and the vertical direction. A second shell covers the first shell and encloses the punched holes therein. An insulative case encloses the second shell therein. |
| US09627814B2 |
Moving part coaxial connectors
A coaxial connector includes a body having a longitudinal axis passing through first and second opposed body ends, the second body end for engaging a male coaxial connector, within the body a coil spring, a connector center conductor, and a second body end insulator supporting the connector center conductor, and a spring for urging an electromagnetic shield to protrude from the body. |
| US09627813B1 |
Card connector with identification function
A card connector includes a base member including a bottom wall, two opposite sidewalls, a first space and a second space defined between the two sidewalls at different elevations and disposed in communication with each other and an identification terminal that has an actuation segment upwardly backwardly extended from the bottom wall, conducting terminals mounted in the base member, and a cover member including a mating conduction terminal that has a falling segment downwardly extended from a top portion of the cover member and a horizontal segment horizontally extended from the distal end of the falling segment and suspended below the distal end of the actuation segment of the identification terminal so that the identification terminal is pressable downward into contact with the mating conduction terminal upon insertion of a predetermined card. |
| US09627809B2 |
Land grid array socket for electro-optical modules
An LGA socket suitable for electro-optical modules, such as transceivers having channels operable at 25 Gbit/s, or greater. A socket may include a socket body having a bottom side to face a printed circuit board (PCB), and a backstop on a top side to receive a leading edge of a module substrate. The backstop has an overhang to contact a first side of the module substrate when seated into the socket body. The socket further includes a first and a second row of electrical contacts, the first row being more proximate to the backstop than is the second row. Contacts extend through the socket body between the top and bottom sides and are positioned relative to the overhang to be compressed against contact pads on a second side of the module substrate by a torque applied to the module substrate about a fulcrum within the socket body. |
| US09627808B2 |
One piece connector with integral latching members
An electrical connector having a housing, a seal and a retainer. The housing includes a component receiving opening which extends through a mating end. The housing is molded from a first material. The seal is provided in the component receiving opening and is integrally molded in the component receiving opening of the housing, the seal being molded from a second material which is different than the first material. The retainer is positioned proximate the mating end and is integrally molded to the housing. The retainer cooperates with a mating component to retain the mating component in the component receiving opening. |
| US09627804B2 |
Snap button fastener providing electrical connection
Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other. The first electrical connector and the second electrical connector are to be electrically connected when the first mechanical part and the mechanical part are interlocked, and first electrical connector and the second electrical connector are to be disconnected when the first mechanical part and second mechanical part are separated. |
| US09627803B2 |
Connectors with movable magnetic components and method of connecting devices
A connector for an electronic device has a housing with a peripheral surface and guides defining first and second paths. The second path extends from a first location proximate the peripheral surface to a second location farther from the peripheral surface and closer to the first path. A magnetic contact assembly in the housing is magnetically movable along the first path between a first position for joining the connector in data communication with an adjacent connector, and a second position withdrawn from the peripheral surface. A magnet in the housing and is movable by attraction to an adjacent connector along the second path, to magnetically hold the connector to an adjacent connector. The guides are configured so that the magnet and the magnetic contact assembly magnetically bias one another inwardly along the first and second paths. |
| US09627802B2 |
Electrical charging devices and assemblies
Electrical charging devices and assemblies are provided herein. An example device includes a housing tray having a sidewall extending perpendicularly from the housing tray, the housing tray being configured to hold a personal electronic device, the housing tray including an electrical connector interface that couples with a charging connector of the personal electronic device. Also, the device includes an electrical connector for electrically coupling with a DC source, the electrical connector capable of being placed in either a deployed configuration where the electrical connector can couple with the DC source or a stored configuration where the electrical connector cannot couple with the DC source. |
| US09627798B2 |
Connector part and connector assembly for use in a severe environment
A connector part for use underwater or in a wet or severe environment, the connector part comprising a pin, projecting axially forwardly from a support, the pin comprising an axially extending electrically conductive portion, an axially extending sleeve comprising fiber reinforced plastic around the conductive portion, a protective layer around the sleeve to prevent exposure of the sleeve to ambient conditions when the pin is exposed to ambient conditions, and an axially extending conductive and impermeable layer between the sleeve and the protective layer. |
| US09627794B2 |
Connector element having a contact module engagement
An electrical connector has a connector housing and a contact receiving body. The connector housing has a body receiving space, a body receiving end, a terminating end wall positioned opposite the body receiving end and having an inner surface facing the body receiving space, a body receiving opening positioned on the body receiving end, and a first locking mechanism positioned on the inner surface of the terminating end wall. |
| US09627780B2 |
System incorporating current path between conductive members
An electrical system having a current path formed in a region between first and second electrodes. When a low pressure is sustained in the region, and a plasma is generated in a portion of a gap between the electrodes, current flows across the gap from the first electrode to the second electrode. In one embodiment the system is operable as a motor or a generator, having a first electrode and a member including a second electrode which is rotatable with respect to the first electrode. In another embodiment a first conductor is positioned to carry current toward or away from a first terminal at a high temperature, and a second conductor is spaced apart from the first terminal to carry current toward or away from a second terminal when the second conductor is at a low temperature relative to the temperature of the first region. |
| US09627774B2 |
Antenna device and system having active and passive modules
Embodiments of the present application disclose an antenna device and system. The antenna device includes: an antenna array, configured to radiate or receive an electromagnetic wave signal; a feed network, configured to connect the antenna array and a signal multiplexer; at least one signal multiplexer, configured to divide one path of signal from the feed network into at least two paths of signal, or combine at least two paths of signal to one path of signal and transmit the one path of signal to the feed network; and at least two interface modules connected to a passive module or an active module, is configured to receive a signal sent from the passive module or the active module, or send a signal to the passive module or the active module. The present application can be used for sharing the antenna array and other parts in the active and passive antenna systems. |
| US09627763B2 |
Antenna device and mobile terminal
The disclosure provides an antenna device and mobile terminal including such an antenna device. The antenna device includes a coil including a conductor wound around a plate-shaped magnetic core. A flat conductor is positioned adjacent to the coil, and the coil is positioned such that it is closer than the flat conductor to an antenna of a communication partner positioned near the antenna device. The coil conductor includes a first conductor portion adjacent to a first main surface of the magnetic core and a second conductor portion adjacent to a second main surface thereof. The magnetic core and the coil conductor form an antenna coil. A circuit substrate includes a ground electrode formation area and a ground electrode non-formation area. The antenna coil is mounted on the ground electrode non-formation area of the circuit substrate with the first main surface of the magnetic core facing the circuit substrate. |
| US09627762B2 |
Antenna device, communication terminal device, and communication terminal device cover
An antenna device includes a feed coil including a coil conductor and being connected to a feed circuit, and an antenna coil including a coil conductor, a portion of the antenna coil being a coupler portion that electromagnetically couples with the feed coil. The winding axis of the coil conductor of the feed coil is not parallel to the direction along which the coil conductor of the antenna coil at the coupler portion extends. Further, at other than the coupler portion, a first magnetic body portion is arranged at a feed coil side of the antenna coil, and at the coupler portion, a second magnetic body portion is arranged at a side of the antenna coil opposite to the feed coil. |
| US09627756B2 |
Interlaced element UHF/VHF/FM antenna
A UHF/VHF/FM antenna consisting of two elongated octagonal elements formed individually from ¼″ O.D. (Outer Dimension) flexible copper tubing, interlaced with each other before coupling of the open tubing ends, then concentrically aligned perpendicular to each other, and soldered at a interlacing cross points. Signals received by the interlaced elements are directed to a 300-75 ohm transformer balun through two bare 12-guage copper wires, each bent approximately 90°, then soldered to the mid-points of adjacent element short sides and perpendicular element cross points. |
| US09627753B2 |
Antenna structures and methods thereof for determining a frequency offset based on a measured data
A system that incorporates the subject disclosure may include, for example, a circuit for determining a magnitude difference between a first signal supplied to an antenna and a second signal radiated by the antenna, determining a phase difference between the first signal supplied to the antenna and the second signal radiated by the antenna, measuring a change in reactance of an antenna, detecting an offset in an operating frequency of the antenna based on one of the magnitude difference, the phase difference, the change in reactance, or any combination thereof, and adjusting a resonant frequency of the antenna to mitigate the offset in the operating frequency of the antenna. Other embodiments are disclosed. |
| US09627752B2 |
Receiving unit driving control method, receiving device and electronic apparatus
An RF receiving circuit unit that receives a GPS satellite signal from a GPS satellite is intermittently driven by a first driving control of intermittently driving the RF receiving circuit unit with a first intermittent driving pattern and a multistage driving control of intermittently driving the RF receiving circuit unit with a multistage intermittent driving pattern in which a driving period in the first intermittent driving pattern is set to a second intermittent driving pattern of which an intermittent cycle is shorter than that of the first intermittent driving pattern. |
| US09627751B2 |
Device for decoupling antennas in compact antenna array and antenna array with the device
Devices and methods for decoupling two antennas in a compact antenna array and antenna arrays comprising the devices are disclosed. According to an embodiment, the device comprises a first resonator coupled with a source, the source being connected with a first antenna of the two antennas; and a second resonator coupled with the first resonator and a load, the load being connected with a second antenna of the two antennas, wherein the first and second resonators are configured so that a first coupling between the source and the first resonator, a second coupling between the first and second resonators, and a third coupling between the second resonator and the load are satisfied with a constraint that an isolation coefficient in a whole network composed of a first two-port network consisting of the two antennas and a second two-port network consisting of the first and second resonators in parallel approach zero as well as reflection coefficients of each port of the whole network are minimized. |
| US09627750B2 |
Radio device
A radio device includes a rectangular substrate including first and second opposite sides and third and fourth opposite sides; a ground plane formed in the substrate, cut out along the third side from a corner at one end of the second side; a first monopole antenna extending away from the ground plane along the third side from a first feeding unit provided on the third side; a second monopole antenna extending away from the ground plane along the fourth side from a second feeding unit provided on the fourth side; and a ground element formed in the ground plane, extending toward the second side along the third side, from one end of the ground element connected to the ground plane. A length from the first feeding unit through the one end to another end of the ground element corresponds to one fourth of a wavelength of radio waves. |
| US09627743B2 |
Antenna device and mobile terminal having the same
A mobile terminal can include a bar type terminal body including a conductive case, and having an upper part and a lower part; and an antenna device disposed on the lower part; the conductive case can include first and second conductive cases forming a side appearance of the mobile terminal, the first conductive case is disposed at a lower end of the terminal body; the second conductive case covers a side surface of the mobile terminal; the first and second conductive cases are separated by an opening with a dielectric therebetween; the antenna can include a first member and a second member extended from an end of the first member and is in a printed circuit board (PCB); the first and second members are near the first conductive case; and the PCB has a socket for connecting an external device, and a key of a user input unit. |
| US09627742B2 |
Mobile device housing including at least one antenna
Embodiments of systems and methods for providing in-mold laminate antennas are generally described herein. Other embodiments may be described and claimed. |
| US09627741B2 |
Wireless module and wireless device
As a wireless module which is capable of improving heat dissipation while suppressing degradation of antenna characteristics, there is provided a wireless module including: a first substrate having a first surface on which a plurality of antennas and a ground portion are disposed; and a heat dissipating member disposed opposite the first surface of the first substrate. The heat dissipating member includes a plurality of openings corresponding to the plurality of antennas respectively and an intervening portion which intervenes between the plurality of openings. The ground portion is disposed between the first substrate and the heat dissipating member. |
| US09627738B2 |
Wideband multilayer transmission line transformer
Embodiments of the invention include transmission line transformers. According to one aspect, a multilayer transmission line transformer (TLT) includes a first set of two conductors forming a first clockwise spiral. The TLT includes a second set of two conductors forming a second counterclockwise spiral that is substantially coaxial with the first spiral. The first and second spirals are arranged to cause a substantial cancellation of common mode currents in the first and second sets of conductors during operation of the TLT. |
| US09627735B2 |
High-frequency signal line and electronic device provided with the same
A high-frequency signal line includes a dielectric base with a first line portion and a second line portion each extending along a predetermined straight line parallel or substantially parallel to a predetermined direction, and a third line portion mutually connecting first side ends of the first line portion and the second line portion in the predetermined direction, a signal line, a first ground conductor located on the first side in the layer stacking direction of the signal line, a second ground conductor located on a second side in the layer stacking direction of the signal line, and one or more interlayer connection conductors connecting the first ground conductor and the second ground conductor. In the third line portion, the interlayer connection conductor is provided on the second side in the predetermined direction of the signal line when viewed from the layer stacking direction. |
| US09627734B2 |
High-frequency signal line and method for producing base layer with signal line
A high-frequency signal line includes a first base layer having flexibility, a linear signal line provided on the first base layer and including a first line portion having a first width and a second line portion having a second width greater than the first width, and a first reinforcing conductor provided on the first base layer along the first line portion. |
| US09627731B2 |
Resonance device and filter including the same
A resonance device and a filter including the same are provided. The resonance device includes a case having a first ground surface and a second ground surface which are facing each other, and a first conductive layer located in the case, and the first conductive layer includes a main part grounded via the first ground surface, and a protruding part which has a width different from that of the main part and is located to be spaced apart from the second ground surface. |
| US09627728B2 |
Rechargeable anion battery cell using a molten salt electrolyte
A rechargeable electrochemical battery cell includes a molten carbonate salt electrolyte whose anion transports oxygen between a metal electrode and an air electrode on opposite sides of the electrolyte, where the molten salt electrolyte is retained inside voids of a porous electrolyte supporting structure sandwiched by the electrodes, and the molten salt includes carbonate including at least one of the alkaline carbonate including Li2Co2, NA2CO2, and K2CO2, having a melting point between 400° C. and 800° C. |
| US09627727B2 |
Lithium-air battery with cathode separated from free lithium ion
A lithium-air electrochemical cell is provided. The battery comprises: an anode compartment; a cathode compartment; and a lithium ion conductive membrane separating the anode compartment from the cathode compartment. The anode compartment comprises an anode having lithium or a lithium alloy as active metal and a lithium ion electrolyte, while the cathode compartment comprises an air electrode and an ionic liquid capable of supporting the reduction of oxygen. A lithium ion concentration in the cathode compartment is such that the lithium ion concentration is greatest at the lithium ion selective membrane and lowest at the cathode. |
| US09627726B2 |
Shutdown system for metal-air batteries and methods of use thereof
This invention provides a shutdown system and methods for battery shutdown followed by a standby mode using a washing solution controlled by pH such that the electrode remains stable. |
| US09627725B2 |
Battery pack
A battery pack having a battery module, a thermoelectric heat pump, and a cooling manifold is provided. The battery module has a first battery cell, a housing, and a first solid cooling fin. A first panel portion of the first solid cooling fin is disposed against the first battery cell. A second panel portion of the first solid cooling fin is disposed on an outer surface of the housing and is coupled to an end portion of the first panel portion. A first side of the thermoelectric heat pump is disposed against the second panel portion, and a second side of the thermoelectric heat pump is disposed against the cooling manifold. The thermoelectric heat pump transfers heat energy from the first solid cooling fin to the cooling manifold in response to a first electrical current flowing through the thermoelectric heat pump in a first direction, to reduce a temperature level of the first battery cell. |
| US09627723B2 |
Operation of electrochemical energy systems
Electrochemical cells that include resistor switch assemblies that can operate according to temperature and batteries and power systems including such cells are disclosed. |
| US09627715B2 |
Non-aqueous electrolyte secondary battery and battery pack
A non-aqueous electrolyte secondary battery of an embodiment includes an exterior member, a negative electrode containing a titanium-containing oxide housed in the exterior member, a positive electrode housed in the exterior member, a separator housed in the exterior member and arranged between the positive electrode and the negative electrode, and a non-aqueous electrolyte solution housed in the exterior member. At least one type or more chain carbonates are contained in a solvent of the non-aqueous electrolyte solution. A self-diffusion coefficient of the chain carbonate in −20° C. is front 1.4×10−10 to 2.0×10−10 m2/sec. |
| US09627713B2 |
Composite electrolyte including polymeric ionic liquid matrix and embedded nanoparticles, and method of making the same
A composite electrolyte comprising includes a polymeric ionic liquid matrix; and a plurality of functionalized nanoparticles embedded therein, wherein at least one of a nitrogen cation moiety, a phosphorus cation moiety, and a sulfur cation moiety is tethered to the nanoparticle. |
| US09627712B2 |
Heteroaromatic-based electrolytes for lithium and lithium-ion batteries
The present invention provides an electrolyte for lithium and/or lithium-ion batteries comprising a lithium salt in a liquid carrier comprising heteroaromatic compound including a five-membered or six-membered heteroaromatic ring moiety selected from the group consisting of a furan, a pyrazine, a triazine, a pyrrole, and a thiophene, the heteroaromatic ring moiety bearing least one carboxylic ester or carboxylic anhydride substituent bound to at least one carbon atom of the heteroaromatic ring. Preferred heteroaromatic ring moieties include pyridine compounds, pyrazine compounds, pyrrole compounds, furan compounds, and thiophene compounds. |
| US09627711B2 |
Non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery includes a positive electrode, a negative electrode, and a separator disposed between the positive electrode and the negative electrode. The positive electrode of this secondary battery contains a positive electrode active substance having a hollow structure, which has a shell portion and a hollow portion formed inside the shell portion. In addition, a heat-resistant barrier layer is disposed between the positive electrode and the separator. |
| US09627707B1 |
Device for preventing deformation of fuel cell stack
A device for preventing deformation of a fuel cell stack module includes vertical plates and a horizontal plate, The vertical plates and the horizontal plate are combined to form a deformation prevention frame and disposed between a plurality of fuel cell stack modules, which is vertically stacked, and on both surfaces of the respective fuel cell stack modules which are perpendicular to an end plate. Each of the plurality of fuel cell stacks includes an end plate disposed perpendicular to the vertical plates. |
| US09627702B2 |
Electrolyte emulsion and process for producing same
A method for producing an electrolyte emulsion, the method including: Step (1) in which an ethylenic fluoromonomer and a fluorovinyl compound having an SO2Z1 group, wherein Z1 is a halogen element, are copolymerized at a polymerization temperature of 0° C. or higher and 40° C. or lower to provide a precursor emulsion containing a fluoropolymer electrolyte precursor; and Step (2) in which a basic reactive liquid is added to the precursor emulsion and the fluoropolymer electrolyte precursor is chemically treated, whereby an electrolyte emulsion with a fluoropolymer electrolyte dispersed therein is provided, wherein the electrolyte emulsion has an equivalent weight (EW) of 250 or more and 700 or less. |
| US09627701B2 |
Integrated gaseous fuel CPOX reformer and fuel cell systems, and methods of producing electricity
Integrated gaseous fuel catalytic partial oxidation (CPOX) reformer and fuel cell systems can include a plurality or an array of spaced-apart CPOX reactor units, each reactor unit including an elongate tube having a gas-permeable wall with internal and external surfaces, the wall enclosing an open gaseous flow passageway with at least a portion of the wall having CPOX catalyst disposed therein and/or comprising its structure. The catalyst-containing wall structure and open gaseous flow passageway enclosed thereby define a gaseous phase CPOX reaction zone, the catalyst-containing wall section being gas-permeable to allow gaseous CPOX reaction mixture to diffuse therein and hydrogen rich product reformate to diffuse therefrom. The gaseous fuel CPOX reformer also can include one or more igniters, and a source of gaseous reformable fuel. The hydrogen-rich reformate can be converted to electricity within a fuel cell unit integrated with the gaseous fuel CPOX reformer. |
| US09627700B2 |
Liquid fuel CPOX reformer and fuel cell systems, and methods of producing electricity
Integrated liquid fuel catalytic partial oxidation (CPOX) reformer and fuel cell systems can include a plurality or an array of spaced-apart CPOX reactor units, each reactor unit including an elongate tube having a gas-permeable wall with internal and external surfaces, the wall enclosing an open gaseous flow passageway with at least a portion of the wall having CPOX catalyst disposed therein and/or comprising its structure. The catalyst-containing wall structure and open gaseous flow passageway enclosed thereby define a gaseous phase CPOX reaction zone, the catalyst-containing wall section being gas-permeable to allow gaseous CPOX reaction mixture to diffuse therein and hydrogen rich product reformate to diffuse therefrom. The liquid fuel CPOX reformer also can include a vaporizer, one or more igniters, and a source of liquid reformable fuel. The hydrogen-rich reformate can be converted to electricity within a fuel cell unit integrated with the liquid fuel CPOX reactor unit. |
| US09627698B2 |
Gas distribution element for a fuel cell
The gas distribution element for a fuel cell or an electrolyzing device including a first layer and a second layer, the first and second layers are disposed with a gas distribution structure forming a pattern for a fluid flow of a first reactant fluid. The second layer is a homogenizing element, which has first apertures, wherein at least some of the first apertures have a length and a width, with the length being greater than the width and the length extending in a transverse direction to the main direction of fluid flow. |
| US09627688B2 |
Anode for secondary battery and lithium secondary battery including same
The present disclosure provides an anode for a secondary battery, including: an electrode current collector; a first coating layer formed on the electrode current collector and including an anode active material, a first aqueous binder and a conducting material; and a second coating layer formed on the first coating layer and including a second nonaqueous binder. Since the anode of the present disclosure can reduce volume change of the anode active material, a lithium secondary battery including same may have improved cycle characteristics. |
| US09627683B2 |
Anode and lithium battery including the same
An anode includes a plurality of metal fibers with a three-dimensional (3D) network structure, and a silicon-containing layer having a thickness of about 0.3 μm or less formed on a surface of and inside the 3D network structure of the plurality of metal fibers. |
| US09627682B2 |
Negative electrode for nonaqueous electrolyte secondary batteries and nonaqueous electrolyte secondary battery including the same
A negative electrode for nonaqueous electrolyte secondary batteries includes a negative electrode core member and a negative electrode mixture layer attached to the negative electrode core member, wherein the negative electrode mixture layer contains negative electrode active material particles with a graphite structure and a binder, the mixture density of the negative electrode mixture layer is 1.5 g/cm3 to 1.8 g/cm3, the ratio I(002)/I(110) of the diffraction intensity I(002) of the (002) plane to the diffraction intensity I(110) of the (110) plane satisfies 60≦I(002)/I(110)≦120 as determined by measuring the negative electrode mixture layer by an X-ray diffraction method, the amount of particles with a size of 1 μm to 10 μm in the particle size distribution of a crushed product of the negative electrode mixture layer is 12% to 25% by volume. |
| US09627677B2 |
Rechargeable battery
A battery includes a plurality of electrode assemblies arranged in a case, each electrode assembly including a first electrode, a second electrode and a separator between the first electrode and the second electrode, and an interior safety member including an interior plate between the electrode assemblies, the interior safety member being electrically connected to at least one of the plurality of electrode assemblies. |
| US09627675B2 |
Bus bar module and power-supply unit
A power-supply unit and a bus bar module which can reduce die cost of an insulating cover are provided. Each of the two insulating covers is provided so as to cover both a first receiving portion and a second receiving portion. For this reason, the two insulating covers arranged on a plate and aligned in an overlapping direction of a battery can be formed in the same shape and same size. |
| US09627672B2 |
Separator for nonaqueous electrolyte batteries containing a porous membrane
A multilayer porous membrane comprising a porous membrane containing a polyolefin resin as a main component; and a porous layer containing an inorganic filler and a resin binder and laminated on at least one surface of the porous membrane; wherein the porous membrane has an average pore size d=0.035 to 0.060 μm, a tortuosity τa=1.1 to 1.7, and the number B of pores=100 to 500 pores/μm2, which are calculated by a gas-liquid method, and the porous membrane has a membrane thickness L=5 to 22 μm. |
| US09627671B2 |
Fabrication method for metal battery electrode with pyrolyzed coating
A method is provided for forming a metal battery electrode with a pyrolyzed coating. The method provides a metallorganic compound of metal (Me) and materials such as carbon (C), sulfur (S), nitrogen (N), oxygen (O), and combinations of the above-listed materials, expressed as MeXCYNZSXXOYY, where Me is a metal such as tin (Sn), antimony (Sb), or lead (Pb), or a metal alloy. The method heats the metallorganic compound, and as a result of the heating, decomposes materials in the metallorganic compound. In one aspect, decomposing the materials in the metallorganic compound includes forming a chemical reaction between the Me particles and the materials. An electrode is formed of Me particles coated by the materials. In another aspect, the Me particles coated with a material such as a carbide, a nitride, a sulfide, or combinations of the above-listed materials. |
| US09627668B1 |
Multi-region battery separators
Disclosed is a battery separator, comprising two fiber regions comprising glass fibers, and a middle fiber region disposed between them comprising larger average diameter fibers and specified amounts of silica, or fine fibers, or both; and processes for making the separator. Also disclosed is a battery separator, comprising a fiber region and either one or two silica-containing region(s) adjacent thereto, each of the regions containing a specified amount of silica; and processes for making the separator. Such separators are useful, e.g., in lead-acid batteries. |
| US09627663B2 |
Rechargeable battery pack including pack cover
A battery pack includes at least one unit cell with a top end, the unit cell including a vent hole, and a pack cover over the top end of the unit cell. The pack cover includes a discharge part having a bottom member that is sloped with respect to the top end of the unit cell. The bottom member of the pack cover including an aperture corresponding to the vent hole of the unit cell. |
| US09627659B2 |
Rectangular secondary battery
An insulation sheet is disposed between a rectangular housing and an electrode body. A first side wall of the insulation sheet is disposed between a large-area side surface of the rectangular housing and the electrode body. The first side wall includes a first folded portion that is folded along an edge of the first side wall near a sealing plate. The first folded portion extends from an edge of the first side wall near the sealing plate toward a bottom surface of the rectangular housing and is disposed between the large-area side surface and the electrode body in such a way that the first folded portion overlaps the first side wall. |
| US09627658B2 |
Battery and battery pack
According to one embodiment, a battery includes a container, an electrode group, an electrolytic solution, a sealing plate, a terminal, an injecting port, a sealing plug, a lead and a pressing member. The injecting port is opened in the sealing plate. The sealing plug closes the injecting port of the sealing plate, and is made of an elastic material. The lead electrically connects a positive electrode or a negative electrode of the electrode group to the terminal. The pressing member is integrated with the lead. The pressing member presses the sealing plug to the sealing plate. |
| US09627657B2 |
Cylindrical alkaline storage battery
An alkaline storage battery includes: a cylindrical case having a side wall including an opening end portion and a bottom; a sealing plate; a gasket interposed between the sealing plate and the opening end portion; and a sealant between the gasket and the opening end portion. The side wall has an annular groove opened at an outer surface thereof, and an inwardly curl portion at the opening end portion. In at least part of the groove, the minimum width L1 is within 0.2 mm. The sealant includes a polyamide resin formed such that when two test-plate materials are bonded together at bonding faces facing each other via a bonding portion of the sealant, and moved in parallel with the bonding faces and in opposite directions to have a relative displacement within 0.5 to 5 mm, a stress at least 0.02 N/mm2 is applied to the bonding portion. |
| US09627656B2 |
Organic light-emitting display apparatus and method of manufacturing the same
In an aspect, an organic light-emitting display apparatus is provided, including a display substrate; a sealing substrate configured to face the display substrate; a sealing material for bonding the display substrate and the sealing substrate and surrounding a circumference of the display unit; and a bonding layer comprising a plurality of through holes, wherein the plurality of through holes comprise partition walls therein. |
| US09627652B2 |
Organic light emitting diode with light extracting electrode
An organic light emitting diode (10) includes a substrate (20), a first electrode (12), an emissive active stack (14), and a second electrode (18). At least one of the first and second electrodes (12, 18) is a light extracting electrode (26) having a metallic layer (28). The metallic layer (28) includes light scattering features (29) on and/or in the metallic layer (28). The light extracting features (29) increase light extraction from the organic light emitting diode (10). |
| US09627647B2 |
Organic light-emitting diode display and manufacturing method thereof
An organic light-emitting diode display includes an organic light-emitting display device including a first electrode, an intermediate layer including an organic emission layer, and a second electrode; a first inorganic encapsulation layer on the second electrode; a second inorganic encapsulation layer on the first inorganic encapsulation layer; and an organic encapsulation layer on the second inorganic encapsulation layer. A refractive index of the first inorganic encapsulation layer is higher than a refractive index of the second inorganic encapsulation layer. The first inorganic encapsulation layer has an extinction coefficient of 0.02 to 0.07 and a refractive index of 2.1 to 2.3 at a blue wavelength. |
| US09627643B2 |
Optoelectronic component
Various embodiments may relate to an optoelectronic component, including a substrate, a first electrically conductive electrode layer, a second electrically conductive electrode layer, an organic layer structure, and a conductor track layer. The first electrically conductive electrode layer, the second electrically conductive electrode layer and the conductor track layer are formed in each case from an optically transparent material. |
| US09627641B2 |
Charge carrier modulation for color and brightness coordination in organic light-emitting diodes
The device for charge carrier modulation is a current-controlled component, which has semiconductor layers arranged on top of each other. The organic semiconductor layers arranged on top of each other are an electron transport layer, which is arranged between a first and a second hole transport layer, and/or a hole transport layer, which is arranged between a first and a second electron transport layer. The respective central layer is the modulation layer having a contact for a modulation voltage. By applying a modulation voltage, a modulation current flow is generated over the modulation layer. The modulation current flow influences the component current flow which flows from the first into the second hole or electron transport layer via the respective modulation layer. |
| US09627640B2 |
Light-emitting element, light-emitting device, display device, electronic appliance, and lighting device
A multicolor light-emitting element in which light-emitting layers emitting light of different colors are stacked and color adjustment is easily made is provided. A multicolor light-emitting element which is inexpensive and has favorable emission efficiency is provided. A light-emitting element in which at least two light-emitting layers emitting light of different colors are formed in contact with each other and the light emitted from the two light-emitting layers is obtained from exciplexes is provided. In addition, the light-emitting element in which the exciplexes emit delayed fluorescence is provided. |
| US09627639B2 |
Organic light emitting display device and lighting apparatus for vehicles using the same
Disclosed are an organic light emitting display device and lighting apparatus for vehicles using the same. The organic light emitting display device includes a first layer including a first organic layer and a first emission layer on a first electrode, a second layer including a second emission layer and a second organic layer on the first layer, a second electrode on the second layer, and a third organic layer between the first layer and the second layer. A thickness of the first emission layer is equal to or greater than a thickness of each of the first organic layer and the second organic layer. |
| US09627637B2 |
Flexible display device having a flexible panel with a bending portion and manufacturing method thereof
A flexible display device includes: a flexible panel having a bending portion that is configured to bend about a radius with respect to an inner peripheral surface of the bending portion, and a housing supporting the flexible panel. The bending portion has one or more recesses at the inner peripheral surface of the bending portion, and an entry width of each of the recesses, a number of the recesses, and a thickness of the flexible panel meet the relation equation of πd=nG, where G denotes the entry width of each of the recesses, n denotes the number of the recesses, and d denotes the thickness of the flexible panel. |
| US09627636B2 |
Flexible display apparatus and manufacturing method thereof
A flexible display apparatus includes a first flexible substrate including carbon, a second flexible substrate on the first flexible substrate, a metal layer between the first flexible substrate and the second flexible substrate, a barrier layer on the second flexible substrate, a thin film transistor (TFT) on the barrier layer, and an organic light-emitting device (OLED) electrically connected to the TFT. |
| US09627635B2 |
Light-emitting device
A novel light-emitting device that is highly convenient or reliable is provided. The light-emitting device includes a framework, a flexible first light-emitting panel supported by the framework so as to form a first developable surface, and a flexible second light-emitting panel supported by the framework so as to form a second developable surface. |
| US09627634B2 |
Heterocyclic compound and organic light-emitting diode including the same
Provided is a heterocyclic compound represented by Formula 1 and an organic light-emitting diode including the same: |
| US09627633B2 |
Perylene functionalized porphyrin dyes for dye-sensitized solar cells
The invention relates to dyes for dye-sensitized solar cells, and in particular, to perylene functionalized porphyrin dyes for dye-sensitized solar cells. The invention further relates to a dye molecule comprising perylene functionalized porphyrin moiety. |
| US09627632B2 |
Materials for organic electroluminescent devices
An uncharged compound of the formula (1) M(L)n(L′)m(L″)o Formula (1) containing a substructure M(L)n of the formula (3) or (4) M is a transition metal; E is identical or different on each occurrence and is in each case a sp2-hybridized carbon or nitrogen atom; Z is identical or different on each occurrence and is in each case C(R)2 or NR; Cy1 and Cy2 are identical or different on each occurrence and are in each case a substituted or unsubstituted heterocycle which coordinates to M via the N atom and may have a bond to the group Z. The compound can also be used in an oligomer, polymer, dendrimer or an electronic component. |
| US09627629B2 |
Compound for organic optoelectronic device, organic light emitting diode including the same, and display including the organic light emitting diode
A compound for an organic optoelectronic device represented by Chemical Formula 1 wherein, in Chemical Formula 1, variables A, Y1 to Y4, X1, m, R1 to R4, L1 to L3, n1 to n3, Ar1 and Ar2 are described in the specification. |
| US09627626B2 |
Compounds for organic electroluminescent devices
The present invention relates to aromatic nitrogen heterocycles, and to electronic devices, in particular organic electroluminescent devices, which comprise these aromatic nitrogen heterocycles, in particular in a hole-injection layer and/or in a hole-transport layer and/or in a hole-blocking layer and/or in an electron-transport layer and/or in an emitting layer. |
| US09627625B2 |
Light-emitting device material and light-emitting device
An organic thin film light-emitting element having both high luminous efficiency and high durability can be provided using a light-emitting element material that comprises a compound having a specified carbazole skeleton. |
| US09627624B2 |
Compound for organic optoelectronic device organic light emitting diode including the same and display including the organic light emitting diode
A compound for an organic optoelectronic device is represented by the following Chemical Formula 1. wherein R1, R2, R3, R4, Ar1, Ar2, Ar3, L1, L2, L3, n1, n2, and n3 are further defined in the specification. |
| US09627621B2 |
Polymeric semiconductors, devices, and related methods
A polymer comprises a polymeric chain represented by formula (I) or (II). In formula (I) a, b, d, and n are integers, a from 0 to 3, b from 1 to 5, c from 1 to 3, d from 1 to 5, and n from 2 to 5000; R1 and R2 are side chains; R3 and R4 are each independently H or a side chain; and when a is 0, R3 and R4 are side chains. In formula (II), a, b, c, d, e, and n are integers, a from 1 to 3, b and c being independently 0 or 1, d and e being independently 1 or 2, and n from 2 to 5000; R1 and R2 are side chains except —COOalkyl; and X1, X2 and X3 are independently O, S, or Se. Semiconductors and devices comprising the polymer are also provided. |
| US09627620B2 |
Organic light-emitting diode display and method of manufacturing the same
An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the method includes performing a first mask process of forming an active layer of a thin-film transistor (TFT) and a first electrode of a capacitor over a substrate and performing a second mask process of i) forming a gate insulating layer and ii) forming a gate electrode of the TFT and a second electrode of the capacitor over the gate insulating layer. The method also includes performing a third mask process of i) forming first and second interlayer insulating layers and ii) removing portions of the first and second interlayer insulating layers so as to form a contact hole that exposes a portion of the active layer. The method also includes performing a fourth mask process of forming a pixel electrode over the second interlayer insulating layer. |
| US09627619B2 |
Thin film forming apparatus and thin film forming method using the same
A thin film forming apparatus includes: a thin film source including a thin film on one surface of the thin film source to be transferred to a substrate; and a light emitter configured to apply light energy to the thin film source to transfer the thin film to the substrate. |
| US09627616B2 |
Electronic device and method for fabricating the same
An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity. |
| US09627613B2 |
Resistive random access memory (RRAM) cell with a composite capping layer
A resistive random access memory (RRAM) cell with a composite capping layer is provided. A tantalum oxide based layer is arranged over a bottom electrode layer. The composite capping layer is arranged over and abutting the tantalum oxide based layer. The composite capping layer includes a first metal layer and a second metal layer overlying the first metal layer. The first metal layer is more reactive with the tantalum oxide based layer than the second metal layer. A top electrode layer is arranged over the composite capping layer. A method for manufacturing the RRAM cell is also provided. |
| US09627612B2 |
Metal nitride keyhole or spacer phase change memory cell structures
Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure. |
| US09627611B2 |
Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material. |
| US09627610B2 |
Method of forming a pattern using ion beams of bilateral symmetry, a method of forming a magnetic memory device using the same, and an ion beam apparatus generating ion beams of bilateral symmetry
A pattern-forming method includes providing a first ion beam at a first incidence angle and a second ion beam at a second incidence angle to a surface of an etch target layer formed on a substrate. Patterns are formed by patterning the etch target layer using the first and second ion beams. The first ion beam and the second ion beam are substantially symmetrical to each other with respect to a normal line that is perpendicular to a top surface of the substrate. Each of the first and second incidence angles is greater than 0 degrees and smaller than an angle obtained by subtracting a predetermined angle from 90 degrees. |
| US09627609B2 |
Method of manufacturing a magnetic memory device
A method of manufacturing a magnetic memory device may include forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction pattern by etching a stacked structure including the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a boron-absorption layer covering the magnetic tunnel junction pattern, and performing a heat treatment process so that boron included in the upper and lower magnetic layers may be absorbed by the boron-absorption layer. The heat treatment process may be undertaken in a gaseous atmosphere including at least one of hydrogen, oxygen, and nitrogen. |
| US09627608B2 |
Dielectric repair for emerging memory devices
Systems and method include providing a non-volatile random access memory (NVRAM) stack including a plurality of layers. The plurality of layers includes a dielectric layer and a metal layer. The metal layer of the NVRAM stack is patterned. The patterning causes damage to lateral side portions of the dielectric layer. The lateral portions of the dielectric layer are repaired by depositing dielectric material on the lateral side portions of the dielectric layer. |
| US09627605B2 |
Displacement sensor having a piezoelectric layer comprising polylactic acid, displacement detecting device and operation device having the same
A displacement sensor having a rectangular shaped elastic member. A piezoelectric element is attached to a first main face of the elastic member. The piezoelectric element has a rectangular-shaped piezoelectric sheet and electrodes on both main faces of the piezoelectric sheet. The piezoelectric sheet is made of poly-L-lactic acid and is at least uniaxially-stretched. The piezoelectric element is attached so that the uniaxial-stretching direction of the piezoelectric sheet is 45° relative to a long-side direction of the elastic member. When the elastic member is bent along the long-side direction, the piezoelectric sheet is stretched along the long-side direction, and the piezoelectric element generates voltage of predetermined level. |
| US09627603B2 |
Quartz vibrator having a dome-shaped cap
A quartz vibrator that includes a substrate, a quartz vibrating element, and a dome-shaped cap. The quartz vibrating element is mounted on the substrate. The cap is bonded to the substrate. The cap defines and forms a sealed space that seals the quartz vibrating element along with the substrate. The cap has a side wall portion, a ceiling portion, and a connecting portion. The side wall portion encloses the quartz vibrating element. The ceiling portion is positioned above the quartz vibrating element. The connecting portion connects the side wall portion and the ceiling portion. The connecting portion is thinner than the side wall portion and the ceiling portion. |
| US09627597B2 |
Package, light-emitting device, and method for manufacturing the same
A package includes a plurality of electrode pairs, each electrode pair including a first electrode on one side and a second electrode on another side in a plan view. The first electrode is electrically connected to the second electrode included in an electrode pair adjacent to a first or second lateral side of the one electrode pair, and is not electrically connected to the first electrode included in the electrode pair adjacent to the first or second side of the one electrode pair. The second electrode is electrically connected to the first electrode included in an electrode pair adjacent to a lower side of the one electrode pair, and is not electrically connected to the second electrode included in the electrode pair adjacent to the first or second lateral side of the one electrode pair. |
| US09627596B2 |
Light emitting device, light emitting device package including the device and lighting apparatus including the package
Embodiments provide a light emitting device including a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a sub-mount, first and second metal pads disposed on the sub-mount and electrically spaced apart from one another, a one first bump disposed between the first conductive semiconductor layer and the first metal pad and a second bump located between the second conductive semiconductor layer and the second metal pad. A plurality of active areas in which The first semiconductor layer and the active layer are disposed are spaced apart from one another when viewed in plan. |
| US09627594B2 |
Light emitting device and method for manufacturing the same
A light emitting device in an embodiment includes first and second light transmissive insulators and a light emitting diode arranged between them. First and second electrodes of the light emitting diode are electrically connected to a conductive circuit layer provided on a surface of at least one of the first and second light transmissive insulators. Between the first light transmissive insulator and the second light transmissive insulator, a third light transmissive insulator is embedded which has at least one of a Vicat softening temperature of 80° C. or higher and 160° C. or lower and a tensile storage elastic modulus of 0.01 GPa or more and 10 GPa or less. |
| US09627591B2 |
Mounting substrate and electronic device including the same
A mounting substrate includes: a base; and at least one pair of wiring patterns disposed apart from each other on the base. At least one of the wiring patterns has a mounting portion, which is configured to support an electronic part thereon and which is rectangular in a plan view. The at least one of the wiring patterns defines a hole, which exposes a part of the base and which is disposed in at least a part of an outer edge of the mounting portion. |
| US09627589B2 |
LEDs with efficient electrode structures
Aspects include Light Emitting Diodes that have a GaN-based light emitting region and a metallic electrode. The metallic electrode can be physically separated from the GaN-based light emitted region by a layer of porous dielectric, which provides a reflecting region between at least a portion of the metallic electrode and the GaN-based light emitting region. |
| US09627588B2 |
Method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip
A method for producing an optoelectronic semiconductor chip is specified, comprising the following steps: providing an n-conducting layer (2), arranging a p-conducting layer (4) on the n-conducting layer (2), arranging a metal layer sequence (5) on the p-conducting layer (4), arranging a mask (6) at that side of the metal layer sequence (5) which is remote from the p-conducting layer (4), in places removing the metal layer sequence (5) and uncovering the p-conducting layer (4) using the mask (6), and in places neutralizing or removing the uncovered regions (4a) of the p-conducting layer (4) as far as the n-conducting layer (2) using the mask (6), wherein the metal layer sequence (5) comprises at least one mirror layer (51) and a barrier layer (52), and the mirror layer (51) of the metal layer sequence (5) faces the p-conducting layer (4). |
| US09627587B2 |
Radiation-emitting semiconductor chip comprising a structured mirror layer which is electrically non-conductive during operation
A radiation-emitting semiconductor chip (1) is specified, comprising—a semiconductor layer sequence (2) having a first main surface (3) and a second main surface (4) situated opposite the first main surface (3) wherein the semiconductor layer sequence (2) has an active zone (5) suitable for generating electromagnetic radiation, —a structured mirror layer (6), which is electrically non-conductive during operation and is arranged on the side of the first main surface (3) of the semiconductor layer sequence (2), wherein the mirror layer (6) has at least one mirror region (6A, 6B, 6C) which regionally covers the first main surface (3), —at least one encapsulation region (7A, 7B, 7C) which surrounds the at least one mirror region (6A, 6B, 6C) on all sides and is in direct contact with the mirror region (6A, 6B, 6C), wherein the at least one encapsulation region (7A, 7B, 7C); is electrically non-conductive during operation. |
| US09627579B2 |
Semiconductor device and a method of making a semiconductor device
An LED device capable of emitting electromagnetic radiation ranging from about 200 nm to 365 nm, the device. The device includes a substrate member, the substrate member being selected from sapphire, silicon, quartz, gallium nitride, gallium aluminum nitride, or others. The device has an active region overlying the substrate region, the active region comprising a light emitting spatial region comprising a p-n junction and characterized by a current crowding feature of electrical current provided in the active region. The light emitting spatial region is characterized by about 1 to 10 microns. The device includes an optical structure spatially disposed separate and apart the light emitting spatial region and is configured to facilitate light extraction from the active region. |
| US09627578B2 |
Epitaxial wafer for light-emitting diodes
The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3≦X≦0.7, 0.51≦Y≦0.54). |
| US09627577B2 |
Semiconductor light-emitting device and method for forming the same
A method of applying a fluorescent material to a surface includes providing a substrate, providing a semiconductor light-emitting stack on the substrate, bonding the substrate to the semiconductor light-emitting stack, and overlaying top and side surfaces of the semiconductor light-emitting stack with the fluorescent material, wherein the fluorescent material contains no binding material. |
| US09627576B2 |
Monolithic tandem chalcopyrite-perovskite photovoltaic device
Monolithic tandem chalcopyrite-perovskite photovoltaic devices and techniques for formation thereof are provided. In one aspect, a tandem photovoltaic device is provided. The tandem photovoltaic device includes a substrate; a bottom solar cell on the substrate, the bottom solar cell having a first absorber layer that includes a chalcopyrite material; and a top solar cell monolithically integrated with the bottom solar cell, the top solar cell having a second absorber layer that includes a perovskite material. A monolithic tandem photovoltaic device and method of formation thereof are also provided. |
| US09627573B2 |
Optical sensor having a light emitter and a photodetector assembly directly mounted to a transparent substrate
An optical sensor is described that includes a light emitter and a photodetector assembly directly attached to a transparent substrate. In one or more implementations, the optical sensor comprises at least one light emitter and a photodetector assembly (e.g., photodiodes, phototransistors, etc.). The light emitter(s) and the photodetector assembly are directly mounted (e.g., attached) to a transparent substrate. |
| US09627569B2 |
Integrated Avalanche Photodiode arrays
The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed. |
| US09627566B2 |
Foil-based metallization of solar cells
Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions. |
| US09627558B2 |
Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells
Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask. |
| US09627557B2 |
Solar cell
The solar cell (1) of the present invention is provided with an n-side electrode (14), a p-side electrode (15), and a photoelectric conversion unit (20) having a first main surface (20a) and a second main surface (20b). The first main surface (20a) includes an n-type surface (20an) and a p-type surface (20ap). The photoelectric conversion unit (20) has a semiconductor substrate (10) and a semiconductor layer (12n). The semiconductor substrate (10) has first and second main surfaces (10b, 10a). The semiconductor layer (12n) is arranged on a portion of the first main surface (10b). The semiconductor layer (12n) constitutes either the n-type surface (20an) or the p-type surface (20ap). The semiconductor layer (12n) includes a relatively thick portion (12n1) and a relative thin portion (12n2). The n-side electrode (14) or the p-side electrode (15) is arranged on at least the relatively thin portion (12n2) of the semiconductor layer (12n). The solar cell of the present invention, by means of the aforementioned configuration, is able to extend the lifetime of the minor carriers by means of the relatively thick portion (12n1), to maintain low resistance between the semiconductor substrate (10) and the n-side electrode (14) by means of the relatively thin portion (12n2), and to increase hole and electron collection efficiency. |
| US09627556B2 |
Composition for forming electrode of solar cell and electrode manufactured by using same
The present invention relates to a composition for preparing solar cell electrodes including: a silver (Ag) powder; a glass frit containing about 0.1 mole % to about 50 mole % of elemental silver; and an organic vehicle, the composition introduces a glass frit including a silver cyanate or a silver nitrate to enhance contact efficiency between an electrode and a wafer, and solar cell electrodes prepared from the composition have minimized contact resistance (Rc) and serial resistance (Rs), thereby exhibiting excellent conversion efficiency. |
| US09627546B2 |
Oxide thin film transistor, array substrate, methods of manufacturing the same and display device
An oxide thin film transistor, an array substrate, methods of manufacturing the same and a display device are disclosed. The oxide thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an oxide active layer, drain/source electrodes sequentially disposed on the base substrate. The oxide TFT transistor further includes an ultraviolet barrier layer disposed on the oxide active layer, the ultraviolet barrier layer is made of a resin material contains an ultraviolet absorbent. The stability of the oxide TFT is enhanced by disposing the ultraviolet barrier layer over the oxide active layer of the oxide TFT, since the ultraviolet barrier layer blocks the impact of UV light on the oxide TFT. |
| US09627545B2 |
Semiconductor device
Provided is a semiconductor device in which deterioration of electrical characteristics can be suppressed. The semiconductor device includes a first oxide semiconductor layer over an insulating surface, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer whose one surfaces are in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer, a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a gate insulating film over the third oxide semiconductor layer, and a gate electrode layer over the gate insulating film. The second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer. Part of the third oxide semiconductor layer is in contact with the other surfaces of the source electrode layer and the drain electrode layer. |
| US09627544B2 |
Method of forming semiconductor device
A method of forming a semiconductor device is disclosed. At least one suspended first semiconductor nanowire and two first semiconductor blocks at two ends of the first semiconductor nanowire are formed in a first area, and at least one suspended second semiconductor nanowire and two second semiconductor blocks at two ends of the second semiconductor nanowire are formed in a second area. A transforming process is performed, so the first semiconductor nanowire is transformed into a nanowire with stress, and the second semiconductor blocks are simultaneously transformed into two blocks with stress. First and second gate dielectric layers are formed respectively on surfaces of the nanowire with stress and the second semiconductor nanowire. First and second gates are formed respectively across the nanowire with stress and the second semiconductor nanowire. |
| US09627540B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material. |
| US09627539B2 |
Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost
A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material. |
| US09627538B2 |
Fin field effect transistor and method of manufacturing the same
A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET includes a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack is formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation includes a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation. |
| US09627536B2 |
Field effect transistors with strained channel features
A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor. |
| US09627535B2 |
Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region
A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches. |
| US09627529B1 |
Well-tap structures for analog matching transistor arrays
In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region. |
| US09627528B2 |
Semiconductor device having gate structures and manufacturing method thereof
A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region. |
| US09627527B2 |
Semiconductor device
In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain. |
| US09627526B2 |
Assymetric poly gate for optimum termination design in trench power MOSFETs
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate. |
| US09627525B2 |
Silicon carbide semiconductor device
Provided is a silicon carbide semiconductor device that enables integration of a transistor element and a Schottky barrier diode while avoiding the reduction of an active region. A silicon carbide semiconductor device includes a silicon carbide layer, a gate insulating film, a Schottky electrode being Schottky functioned to a drift layer via a first contact hole and an opening, a gate electrode being arranged on the gate insulating film, an insulating layer being arranged so as to cover the gate insulating film, the gate electrode, and the Schottky electrode and having a second contact hole for exposing the gate electrode, and a gate pad electrode being arranged on the insulating layer so as to overlap the Schottky electrode in a plan view and being electrically connected to the gate electrode via the second contact hole. |
| US09627524B2 |
High voltage metal oxide semiconductor device and method for making same
The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device). |
| US09627521B1 |
Trench IGBT with tub-shaped floating P-well and hole drains to P-body regions
A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation. |
| US09627520B2 |
MOS transistor having a cell array edge zone arranged partially below and having an interface with a trench in an edge region of the cell array
A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array. |
| US09627519B2 |
Semiconductor device
A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region. |
| US09627515B2 |
Method of manufacturing thin-film transistor substrate
A method of manufacturing a thin-film transistor substrate that includes a thin-film transistor having a semiconductor layer, includes: forming a CuMn alloy film (third conductive film) above a substrate; forming a first silicon oxide film (first insulation film) on the CuMn alloy film at a first temperature; forming an aluminum oxide film (second insulation film) on the first silicon oxide film; and forming a second silicon oxide film (third insulation film) on the aluminum oxide film at a second temperature higher than the first temperature. |
| US09627509B2 |
Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device. |
| US09627507B2 |
Strained asymmetric source/drain
The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes receiving a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed. |
| US09627502B2 |
Circuit arrangement and method of forming a circuit arrangement
A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode. |
| US09627501B2 |
Graded dielectric structures
Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material. |
| US09627496B2 |
Semiconductor with a two-input NOR circuit
A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area. |
| US09627494B2 |
Pillar-shaped semiconductor device and production method therefor
A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2 layer. Two stacks of layers, each stack being constituted by a Ni layer, a poly-Si layer containing a donor or acceptor impurity atom, and a SiO2 layer, are formed in a peripheral portion of the opening, and heat treatment is performed to silicidate the poly-Si layers into NiSi layers. The NiSi layers protrude and come into contact with the side surface of the Si pillar by silicidation, and a donor or acceptor impurity atom diffuses from the NiSi layers into the Si pillar. Thus an N+ region and a P+ region serving as a source and a drain of surrounding gate MOS transistors are respectively formed above and under the SiO2 layer. |
| US09627493B2 |
Forming a conductive connection between a common electrode of an optical front plane and an electrical contact part of an opposite back plane
A technique for creating a conductive connection between a contact part (24) of a display back plane (34) and a common electrode (20) of a display front plane (32), comprising the step of compressing a compressible conductive component (30) between the display front plane (32) and the display back plane (34), wherein the method further comprises the step of interposing one or more layers (10, 36) having a low modulus of elasticity not larger than 5 GPa between the contact part (24) and the compressible conductive component (30) prior to the compressing step. |
| US09627492B2 |
Semiconductor device
A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a LOCOS insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the LOCOS insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the LOCOS insulating layer from a direction of the body area. |
| US09627491B2 |
Aspect ratio trapping and lattice engineering for III/V semiconductors
A semiconductor structure including a III/V layer on a SiGe layer, edges of the SiGe layer are relaxed, the III/V layer is a semiconductor in a III/V semiconductor group, the SiGe layer is directly on an insulator layer, barrier layers on two adjacent sides of the SiGe layer and the III/V layer, and the barrier layer is directly on the insulator layer. |
| US09627488B2 |
Silicon carbide semiconductor device and method for manufacturing same
A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided. |
| US09627482B2 |
Reduced current leakage semiconductor device
A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein. |
| US09627480B2 |
Junction butting structure using nonuniform trench shape
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer. |
| US09627476B2 |
Fin structure of semiconductor device
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. |
| US09627475B2 |
Dummy gate structure for semiconductor devices
A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer. |
| US09627473B2 |
Parasitic channel mitigation in III-nitride material semiconductor structures
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates. |
| US09627464B2 |
Display module
An organic display device includes a pixel driving circuit having a TFT connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the TFT. The first electrode is connected to the TFT through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over pixels. |
| US09627461B2 |
Array substrate, its manufacturing method and display device
The present disclosure provides an array substrate, its manufacturing method and a display device. The array substrate includes a thin film transistor. A source electrode and a drain electrode are located above a pattern of an active layer, and the source electrode and the drain electrode are in electrical contact with the pattern of the active layer through a first via-hole penetrating an insulating structure. Before the formation of the source electrode and the drain electrode, the pattern of the active layer is subjected to ion injection through the first via-hole, so as to form an ion injection region. |
| US09627451B2 |
Pixel structure and display apparatus
A pixel structure includes a plurality of pixel cells each including two sub-pixel cells. Each of the two sub-pixel cell includes: a first sub-pixel; and at least two second sub-pixels parallelly adjacent to each other. Herein, organic material parts of the at least two second sub-pixels are interconnected and the first sub-pixel is arranged staggered with any of the at least two second sub-pixels in both a first direction and a second direction, and the first direction is perpendicular to the second direction. |
| US09627449B2 |
Pixel arrangement structure for organic light-emitting diode display
A pixel arrangement structure for an organic light-emitting diode display includes at least one first sub-pixel line having alternately disposed first and second sub-pixel units in a first direction. Each first sub-pixel unit includes four diagonally disposed red sub-pixels. Each second sub-pixel unit includes four diagonally disposed green sub-pixels. At least two second sub-pixel lines are respectively located on two sides of the first sub-pixel line. Each second sub-pixel line includes third sub-pixel units arranged in the first direction. Each third sub-pixel unit is located between one of the first sub-pixel units and one of the second sub-pixel units in a second direction perpendicular to the first direction and includes two blue sub-pixels arranged in the second direction. A red sub-pixel, a green sub-pixel, and a blue sub-pixel, which are adjacent to each other and which are respectively of the first sub-pixel line and the second sub-pixel line, form a pixel. |
| US09627448B2 |
OLED panel
The present invention provides an OLED panel. The OLED panel includes a substrate and a plurality of walls formed on the substrate. The substrate and the walls define a plurality of containing areas. Each of the containing areas is corresponding to each of a plurality of sub-pixels. The sub-pixels are separated from each other by the walls. Each of the sub-pixels includes one of emitting materials formed in one of the containing areas. At least one of the containing areas corresponding to the sub-pixel includes a first partition. The height of the first partition is lower than the walls. |
| US09627446B2 |
Display device
A display device includes a substrate and subpixel groups disposed on the substrate. Each subpixel group includes four first subpixels for emitting four first color lights, four second subpixels for emitting four second color lights, and eight third subpixels for emitting eight third color lights. The first subpixels, the second subpixels, and the third subpixels are respectively arranged adjacent to each other along a first axis and a second axis intersecting the first axis, in which each of the first subpixels is located adjacent to another one of the first subpixels along the first axis or the second axis, each of the second subpixels is located adjacent to another one of the second subpixels along the first axis or the second axis, and each of the third subpixels is located adjacent to another one of the third subpixels along at least one of the first axis and the second axis. |
| US09627445B2 |
Optoelectronic component and a method for manufacturing an optoelectronic component
Various embodiments relate to an optoelectronic component including: an electronic circuit structure including an electronic circuit and a metallization structure disposed over the electronic circuit, the metallization structure including one or more contact pads electrically connected to the electronic circuit; and an optoelectronic structure disposed over the metallization structure, the optoelectronic structure including at least one electrode structure being in direct contact with the one or more contact pads, wherein the electrode structure includes an electroless plated electrically conductive material. |
| US09627443B2 |
Three-dimensional oblique two-terminal memory with enhanced electric field
Providing for three-dimensional memory cells having enhanced electric field characteristics is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance. |
| US09627440B2 |
Phase change memory apparatuses
Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses. |
| US09627435B2 |
Light emitting device
A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material. A light-transmitting material is used in both the first insulation layer and the second insulation layer. The inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane based on the substrate. |
| US09627433B2 |
Method of manufacturing junction field effect transistor
A method of manufacturing a junction field effect transistor having a channel region disposed in a semiconductor substrate, deeper than one of a source region and a drain region, the method includes a first step of forming a first mask having a first opening portion over the semiconductor substrate in which a first semiconductor region of a first conductivity type is disposed, a second step of forming a second semiconductor region of a second conductivity type defined as the channel region, in the first semiconductor region by implantation of ions of second conductivity type opposite to the first conductivity type using the first mask, and a third step of forming a third semiconductor region of the second conductivity type defined as the one of the source region and the drain region, by implantation of ions of the second conductivity type, using the first mask. |
| US09627430B2 |
Method and apparatus for low resistance image sensor contact
A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line. |
| US09627429B2 |
Semiconductor device and electronic device having bonded substrates
A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer. |
| US09627423B2 |
Solid-state image pickup apparatus and image pickup system having a clipping circuit arranged close to an N-row signal mixing region
Provided is a solid-state image pickup apparatus, including: a pixel region, in which a plurality of pixels each including an amplifier transistor are arranged two-dimensionally in rows and columns, and which includes an n-row signal mixing region in which outputs of n amplifier transistors are mixed, where n is a natural number of 1 or more, and an m-row signal mixing region in which outputs of m amplifier transistors are mixed, where m>n; a column signal line to which a voltage from the amplifier transistor is output; and a clipping circuit, which is configured to clip a voltage in the column signal line, and is arranged at a position that is closer to the n-row signal mixing region than to the m-row signal mixing region. |
| US09627422B2 |
Photodetector
There is provided a photodetector, comprising a semiconductor heterostructure having in sequence: a first collection layer having substantially uniform doping of a first doping type; a radiation-absorbing layer having substantially uniform doping of the first doping type and having a band gap less than or equal to that of the first collection layer; and a barrier layer having a band gap greater than that of the radiation-absorbing layer, the top of the valence band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is n-type or the bottom of the conduction band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is p-type; wherein a first portion of the barrier layer is of the first doping type and a second portion of the barrier layer is of a second doping type, the first portion of the barrier layer being adjacent to the radiation-absorbing layer, forming a heterojunction within the barrier layer which gives rise to a depletion region within each portion of the barrier layer. |
| US09627421B2 |
Array substrate and method for manufacturing the same, and display device
An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode (8), including a first portion (b) in a non-display region and a second portion (a) in a display region; a first electrode (6) formed on the first portion (b) of the pixel electrode (8); a passivation layer (9) formed on the pixel electrode (8) and the first electrode (6), the passivation layer (9) includes a via hole (11) located over the first electrode (6); an active layer (4) and a second electrode (7) that are formed on the passivation layer (9), the active layer (4) being connected to the first electrode (6) through the via hole (11) of the passivation layer (9). With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, materials of the electrodes are less subjected to corrosion, and quality of the array substrate is enhanced. |
| US09627420B2 |
Method for forming an electronic device on a flexible substrate supported by a detachable carrier
A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device. |
| US09627419B2 |
Display device and method of manufacturing the same
A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel unlike the related art and thus thickness and manufacturing cost are reduced. |
| US09627417B2 |
Method of manufacturing display apparatus and display apparatus manufactured through the method
A method of manufacturing a display apparatus includes: preparing a substrate including a pixel circuit region and a driving circuit region; forming a first active layer at the pixel circuit region; forming a second active layer at the driving circuit region; forming gate electrodes that overlap the first active layer and the second active layer, respectively, with a gate insulating layer disposed therebetween; forming a first insulating layer covering the first and second active layers; forming a first contact hole that passes through the first insulating layer until a portion of the first active layer is exposed; heat-treating the substrate where the first insulating layer, in which the first contact hole is formed, is formed; and forming a second contact hole that passes through the first insulating layer disposed on the heat-treated substrate until a portion of the second active layer is exposed. |
| US09627414B2 |
Metallic oxide thin film transistor, array substrate and their manufacturing methods, display device
The present invention provides a metallic oxide thin film transistor and its manufacturing method, an array substrate and its manufacturing method, as well as a display device, which is belong to the field of thin film transistor manufacturing technology. The method for manufacturing the metallic oxide thin film transistor comprises a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process. |
| US09627413B2 |
Semiconductor device and display device
The semiconductor device includes a transistor including an oxide semiconductor film, a first gate electrode overlapping with the oxide semiconductor film, a gate insulating film between the oxide semiconductor film and the first gate electrode, a first insulating film over the oxide semiconductor film, a pair of electrodes that are over the first insulating film and electrically connected to the oxide semiconductor film, a second insulating film over the first insulating film and the pair of electrodes, and a second gate electrode that is over the second insulating film and overlaps with the oxide semiconductor film. The first insulating film includes a region having a thickness of 1 nm or more and 50 nm or less, and the pair of electrodes includes a region in which a distance between the electrodes is 1 μm or more and 6 μm or less. |
| US09627410B2 |
Metallized junction FinFET structures
FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal. |
| US09627407B2 |
Semiconductor device comprising a NOR decoder with an inverter
A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer. |
| US09627399B2 |
Three-dimensional memory device with metal and silicide control gates
An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers. |
| US09627395B2 |
Enhanced channel mobility three-dimensional memory structure and method of making thereof
A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility. |
| US09627392B2 |
Method to improve floating gate uniformity for non-volatile memory devices
The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region. |
| US09627390B2 |
Semiconductor device having fin-type active patterns and gate nodes
A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode. |
| US09627388B2 |
Memory system having overwrite operation control method thereof
The memory system has an overwrite operation and an operation control method thereof. A nonvolatile memory device has a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate. When data of memory cells connected to a word line of a selected memory block is read, the need of reclaim is determined based on an error bit level of the read data. In the case that memory cells having an erase state among the memory cells connected to the word line become a soft program state, the read data is overwritten in the memory cells connected to the word line of the selected memory block. |
| US09627387B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines. |
| US09627386B2 |
Memory device and electronic device
A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell. |
| US09627382B2 |
CMOS NFET and PFET comparable spacer width
Embodiments of the present disclosure provide a structure including: a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate and source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate. |
| US09627381B1 |
Confined N-well for SiGe strain relaxed buffer structures
Techniques for effectively confining n-well dopants during fabrication of relaxed SiGe on SRB devices are provided. In one aspect, a method for forming a semiconductor device includes the steps of: forming a SiGe stress relief buffer layer on a substrate; growing a bottom confinement layer on the stress relief buffer layer; growing a SiGe layer on the bottom confinement layer; growing a top confinement layer on the SiGe layer; forming STI regions extending through the top confinement layer, through the SiGe layer, and at least down to the bottom confinement layer, wherein the STI regions define at least one active area in the SiGe layer; and implanting at least one well dopant into the at least one active area which is confined to the at least one active area by the top confinement layer, the bottom confinement layer, and the STI regions. A semiconductor device is also provided. |
| US09627379B1 |
FinFET devices and methods of forming the same
FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate. |
| US09627376B2 |
Semiconductor device with active fins separated by shallow and deep trench isolations and method for fabricating the same
A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base. |
| US09627372B2 |
Electrostatic discharge protection device
An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node. |
| US09627369B2 |
Packages and methods for forming the same
A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. |
| US09627367B2 |
Memory devices with controllers under memory packages and associated systems and methods
Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host. |
| US09627366B2 |
Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
A microelectronic semiconductor package includes first and second microelectronic elements and a substrate positioned between them. Each of the microelectronic elements has active and passive surfaces, first edges bounding the surfaces in a first lateral direction and second edges bounding the surfaces in a second lateral direction transverse to the first lateral direction. The first microelectronic overlies the second microelectronic element and the active surface of the first microelectronic element faces toward the passive surface of the second microelectronic element. Each of the first edges of the first microelectronic element are disposed beyond each of the adjacent first edges of the second microelectronic element. Each of the second edges of the second microelectronic element are disposed beyond each of adjacent second edges of the first microelectronic element. |
| US09627365B1 |
Tri-layer CoWoS structure
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die. |
| US09627363B2 |
Display device using semiconductor light emitting devices
A display device including a wiring substrate having a wiring electrode; a plurality of semiconductor light emitting devices which form pixels; and a conductive adhesive layer configured to electrically connect the wiring electrode with the plurality of semiconductor light emitting devices. Further, the conductive adhesive layer includes a body provided with a resin having an adhesive property; and a metallic aggregation part disposed in the body, and formed as metallic atoms precipitated from a metal-organic compound and aggregated with each other. |
| US09627362B2 |
Illumination device
An illumination device includes a light-emitting device and a diffusion member. The light-emitting device has a plurality of light-emitting elements that emit light having a peak wavelength in a wavelength region of 380 to 420 nm, a first phosphor that emits visible light having a peak wavelength in a wavelength region of 560 to 600 nm, a second phosphor that is excited by ultraviolet ray or short-wavelength visible light and emits visible light in complementary color relationship with the visible light emitted by the first phosphor, and a light-transmitting member that covers the plurality of light-emitting elements and contains the first phosphor and the second phosphor dispersed therein. The diffusion member diffuses at least a part of the light emitting from the light-emitting device. |
| US09627360B2 |
Circuit board having bypass pad
An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. |
| US09627354B1 |
Semiconductor memory device
A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad. |
| US09627353B2 |
Method of manufacturing a semiconductor package
Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first carrier to a first surface of an interposer in wafer form, forming conductive bumps on a second surface of the interposer, bonding a second carrier to the conductive bumps utilizing a film adhesive, removing the first carrier from the interposer, bonding a semiconductor die to the first surface of the interposer, and encapsulating the die and the first surface of the interposer in an encapsulant material. The second carrier and the film adhesive may be removed from the conductive bumps utilizing a slide-off process. The interposer and encapsulant may be diced into a plurality of interposer and die structures. One of the die and interposer structures may be bonded to a substrate. The die may be bonded to the interposer utilizing a mass reflow process. |
| US09627348B2 |
Laser assisted bonding for semiconductor die interconnections
Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass. |
| US09627347B2 |
Method of manufacturing semiconductor device and semiconductor device manufacturing apparatus
A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves. |
| US09627346B2 |
Underfill pattern with gap
An embodiment is a structure comprising a package, a substrate, and external electrical connectors mechanically and electrically coupling the package to the substrate. The package contains a die. The external electrical connectors are between the package and the substrate. An underfill material is around a periphery region of the package and between the periphery region and the substrate. A gap is between a central region of the package and the substrate, and does not contain the underfill material. The underfill material may seal the gap. The gap may be an air gap. In some embodiments, the underfill material may fill greater than or equal to 10 percent and no more than 70 percent of a volume between the package and the substrate. |
| US09627345B2 |
Semiconductor-mounted product and method of producing the same
A semiconductor-mounted product includes a semiconductor package, a circuit board, a solder bonding part, and a resin reinforcing part. Wiring is formed on the surface of the circuit board, and the semiconductor package is mounted on the circuit board. The solder bonding part electrically connects the semiconductor package with the wiring. The resin reinforcing part is formed on a side surface of the solder bonding part such that the solder bonding part is partially exposed. The bonding part has a first solder region formed closer to the semiconductor package than the circuit board, and a second solder region formed closer to the circuit board than the semiconductor package. |
| US09627344B2 |
Semiconductor device
The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer. |
| US09627341B2 |
Wafer arrangement, a method for testing a wafer, and a method for processing a wafer
According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component. |
| US09627338B2 |
Semiconductor device and method of forming ultra high density embedded semiconductor die package
A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film. |
| US09627336B2 |
Semiconductor device allowing metal layer routing formed directly under metal pad
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad. |
| US09627335B2 |
Method for processing a semiconductor workpiece and semiconductor workpiece
A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte. |
| US09627331B1 |
Method of making a wire support leadframe for a semiconductor device
A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe. |
| US09627327B2 |
Semiconductor package and method of manufacturing the same
Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material. |
| US09627321B2 |
Methods and apparatuses to form self-aligned caps
At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line. |
| US09627316B1 |
Field effect transistor devices having interconnect structures and manufacturing method thereof
A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer. |
| US09627315B2 |
Semiconductor device having a multi-level interconnection structure
A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view. |
| US09627313B2 |
Opening fill process and structure formed thereby
Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening. |
| US09627310B2 |
Semiconductor device with self-aligned interconnects
A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface. |
| US09627309B2 |
Wiring substrate
A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers. |
| US09627308B2 |
Wiring substrate
A wiring substrate includes a first wiring substrate, a first insulation layer covering the first wiring layer, a second insulation layer stacked on the first insulation layer, and a cavity extending through the second insulation layer and exposing a portion of the upper surface of the first insulation layer. The cavity includes an opening, which is defined by an upper portion of a stepped inner wall surface of the second insulation layer, and a recess, which is defined by a lower portion of the stepped inner wall surface that contacts the upper surface of the first insulation layer. The recess is wider than the opening. An electronic component is mounted on the upper surface of the first insulation layer. The opening and the recess are filled with a third insulation layer that covers the electronic component and the second insulation layer. |
| US09627299B1 |
Structure and method for diminishing delamination of packaged semiconductor devices
A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities. |
| US09627298B2 |
Semiconductor device
To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads. |
| US09627296B2 |
Semiconductor package with cantilever leads
A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe. |
| US09627294B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes: a stacked unit including a semiconductor module and a plurality of coolers each having a flow passage through which a coolant flows, the semiconductor module being disposed between the coolers; a coolant supply-discharge pipe configured to supply the coolant to the coolers or discharge the coolant from the coolers, the coolant supply-discharge pipe being passed through the stacked unit in a stacking direction of the stacked unit; a displacement restricting member provided at a first end portion of the coolant supply-discharge pipe, the displacement restricting member being configured to restrict displacement of the stacked unit in the stacking direction of the stacked unit; and a pressurizing member provided at a second end portion of the coolant supply-discharge pipe, the pressurizing member being configured to apply force to the stacked unit in a direction toward the first end portion. |
| US09627292B2 |
Semiconductor housing with rear-side structuring
A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted. |
| US09627290B2 |
Bump structure design for stress reduction
Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress. |
| US09627284B2 |
Semiconductor device
A semiconductor device includes: a resin case that houses a semiconductor element; a parallel plate that is disposed inside the resin case while being connected with the semiconductor element, the parallel plate including two flat plates parallel to each other with an insulating material therebetween; and two electrodes that are each led out from an upper end of the parallel plate and are disposed on an upper surface of the resin case at a predetermined interval. Upper end portions of the two flat plates of the parallel plate between two electrode lead-out portions are bent toward the outside being a direction in which the upper end portions of the two flat plates become more distant from each other, the two electrodes being led out from the corresponding two electrode lead-out portions. |
| US09627279B2 |
Method for removing defective light emitting diode (LED) package from LED package arrary
An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit. |
| US09627275B1 |
Hybrid semiconductor structure on a common substrate
A semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system. |
| US09627274B1 |
Methods of forming self-aligned contacts on FinFET devices
One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material. |
| US09627273B2 |
Methods of manufacturing semiconductor devices having a nanowire channel structure
A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different. |
| US09627269B2 |
Transistor and fabrication method thereof
A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer. |
| US09627262B2 |
Method of patterning features of a semiconductor device
A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate. |
| US09627261B1 |
Multi-chip integrated circuit
An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip. |
| US09627259B2 |
Device manufacturing method and device
A device manufacturing method according to an embodiment includes forming a film on the second surface side of a substrate having a first surface and the second surface, forming a trench in part of the substrate from the first surface side, while leaving the film to remain, and injecting a substance onto the film from the second surface side, to remove the film at the portion on the second surface side of the trench. |
| US09627256B2 |
Integrated circuit interconnects and methods of making same
A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer. |
| US09627252B2 |
Semiconductor device with air gap and method of fabricating the same
A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts. |
| US09627247B2 |
Semiconductor device and method of fabricating the same
Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles. |
| US09627246B2 |
Method of forming shallow trench isolation (STI) structures
A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate. |
| US09627244B2 |
Methods and systems for supporting a workpiece and for heat-treating the workpiece
Apparatuses and methods for supporting a workpiece such as a semiconductor wafer. A support system is configured to support the workpiece while allowing thermally-induced motion of the workpiece, which may include thermal bowing or thermal bending. The system may include a support member having a moveable engagement portion engageable with the workpiece, the engagement portion being moveable to allow the thermally-induced motion of the workpiece while supporting the workpiece. The moveable engagement portion may include a plurality of moveable engagement portions of a plurality of respective support members, which may be resiliently engageable with the workpiece. The support members may include flexible support members each having an unconstrained portion and a constrained portion, and the moveable engagement portions may include the unconstrained portions. Alternatively, the support members may be rigid and the system may include a plurality of force applicators such as springs in communication with the support members. |
| US09627243B2 |
Method and apparatus of holding a device
Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. |
| US09627242B2 |
Wafer processing method
In a wafer processing method, a protective film is formed by applying a liquid resin to the front side of a wafer. A protective tape is adhered to a surface of the protective film. A modified layer is formed by applying a laser beam having such a wavelength as to be transmitted through the wafer along each of division lines, with a focal point positioned inside the wafer. The modified layer is formed inside the wafer along each of the division lines. The back side of the wafer is ground while supplying grinding water to thin the wafer to a predetermined thickness and to crack the wafer along the division lines using the modified layers as crack starting points so as to divide the wafer into individual device chips, after the protective film is formed, the protective tape is adhered, and the modified layer is formed. |
| US09627240B2 |
Electrostatic chuck
According to an aspect of the invention, there is provided an electrostatic chuck including: a ceramic dielectric substrate having a first major surface, a second major surface, and a through-hole; a metallic base plate which has a gas introduction path that communicates with the through-hole; and a bonding layer which is provided between the ceramic dielectric substrate and the base plate and includes a resin material, the bonding layer having a space which is provided between an opening of the through-hole in the second major surface and the gas introduction path and is larger than the opening in a horizontal direction, and a first area in which an end face of the bonding layer on a side of the space intersects with the second major surface being recessed from the opening further than another second area of the end face which is different from the first area. |
| US09627238B2 |
Substrate transfer apparatus, substrate transfer method, and storage medium
A substrate transfer apparatus unloads a substrate from a transfer container in which a cover body airtightly closes a substrate unloading opening formed at a front surface of a container main body and multiple substrates are accommodated in the form of shelves. The substrate transfer apparatus includes a load port to which the transfer container is loaded; a detection unit configured to detect an accommodation status of the substrate in the container main body that is loaded to the load port and separated from the cover body; a substrate transfer device configured to enter the container main body and unload the substrate; and a correction device configured to correct the accommodation status of the substrate in the container main body before the substrate is unloaded from the container main body by the substrate transfer device when the detection unit detects abnormality in the accommodation status. |
| US09627234B2 |
Method and apparatus for localized and controlled removal of material from a substrate
A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path. |
| US09627232B2 |
Substrate processing method, substrate processing apparatus and non-transitory storage medium
There is provided a substrate processing method including: supplying a developing liquid to a surface of an exposed substrate to form a resist pattern; supplying a cleaning liquid to the surface of the substrate to remove a residue generated in the developing step from the substrate; supplying a replacing liquid to the surface of the substrate to replace the cleaning liquid existing on the substrate with the replacing liquid, the replacing liquid having a surface tension of 50 mN/m or less and containing a percolation inhibitor for restraining the replacing liquid from percolating into a resist wall portion constituting the resist pattern; and forming a dry region by supplying a gas to a central portion of the substrate while rotating the substrate so as to dry the surface of the substrate by expanding the dry region to a peripheral edge portion of the substrate with a centrifugal force. |
| US09627229B2 |
Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the underfill material. An active region of the first semiconductor die is disposed over the opening in the substrate. The trench contains the outward flow of underfill material. Underfill material is blocked from flowing over unintended areas on the surface of substrate, into the opening in the substrate, and over sensors of the first semiconductor die. A second semiconductor die is disposed over the substrate. The trench is formed by a first and second dam or a first insulating layer. A second insulating layer is formed over the first insulating layer. A dam is formed over the second insulating layer. |
| US09627219B2 |
CMP wafer edge control of dielectric
Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer. |
| US09627218B2 |
Pattern forming method and manufacturing method for semiconductor device
According to one embodiment, a mask material is formed on a processing layer, a mask pattern with a top surface and a bottom surface is formed on the mask material, a protective film is formed on the top surface of the mask pattern, and after the formation of the protective film, the bottom surface of the mask pattern is etched in a depth direction. |
| US09627217B2 |
Silicon-containing EUV resist underlayer film-forming composition including additive
There is provided a composition for forming an EUV resist underlayer film which shows a good resit form. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (A) containing a hydrolyzed condensate of hydrolyzable silane (a); and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (B) containing a hydrolyzed condensate of hydrolyzable silane (a) and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. The polysiloxane (A) is preferably a co-hydrolyzed condensate of a tetraalkoxysilane, an alkyltrialkoxysilane and an aryltrialkoxysilane. |
| US09627215B1 |
Structure and method for interconnection
A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench. |
| US09627214B2 |
Stratified gate dielectric stack for gate dielectric leakage reduction
A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness. |
| US09627206B2 |
Method of double patterning lithography process using plurality of mandrels for integrated circuit applications
A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material. |
| US09627202B2 |
Methods for forming fine patterns of semiconductor device
The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns. |
| US09627201B2 |
Methods of forming holes using mask pattern structures
In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes. |
| US09627200B2 |
Synthesis of CdSe/ZnS core/shell semiconductor nanowires
The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires. |
| US09627198B2 |
Method for manufacturing thin film semiconductor device
An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor. |
| US09627194B2 |
Methods for masking and applying protective coatings to electronic assemblies
One or more masks may be used to control the application of protective (e.g., moisture-resistant, etc.) coatings to one or more portions of various components of an electronic device during assembly of the electronic device. A method for applying a protective coating to an electronic device includes assembling two or more components of the electronic device with one another. A mask may then be applied to the resulting electronic assembly. The mask may shield selected portions of the electronic assembly, while other portions of the electronic assembly, i.e., those to which a protective coating is to be applied, may remain exposed through the mask. With the mask in place, application of a protective coating to portions of the electronic assembly exposed through the mask may commence. After application of the protective coating, the mask may be removed from the electronic assembly. Embodiments of masked electronic assemblies are also disclosed. |
| US09627192B2 |
Substrate processing method, substrate processing apparatus, and computer-readable storage medium stored with substrate processing program
Disclosed is a substrate processing apparatus (a substrate processing method, and a computer readable storage medium having a substrate processing program stored therein) of cleaning an etched substrate with a polymer removing liquid, in which any of isopropyl alcohol vapor, water vapor, deionized water and isopropyl alcohol, ammonia water, and ammonia water and isopropyl alcohol is supplied to the substrate before the substrate is cleaned with the polymer removing liquid. |
| US09627191B2 |
Extendable multi-tool including interchangable light bulb changer and accessories
An extendable multi-tool comprising an extendable pole and a head unit selectively detachably coupled together. The head unit comprises a grasping mechanism configured to engage a light bulb, a control switch and a rotation mechanism. The control switch configured to cause the grasping mechanism to become secured to a light bulb, and to cause the rotation mechanism to automatically detect when a light bulb is secured to the grasping mechanism and then rotate the grasping unit and the secured light bulb in a first direction based on the position of the control switch. The tool further comprises an arm unit for positioning the grasping mechanism in a desired configuration to engage the light bulb, wherein the arm member is coupled to the grasping mechanism. |
| US09627187B2 |
Sputtering apparatus
A sputtering apparatus includes a deposition preventing plate arranged between a substrate stage and a plurality of cathode electrodes, and a shutter plate arranged between the deposition preventing plate and the substrate stage. The deposition preventing plate has holes at positions respectively facing a plurality of targets held by the plurality of cathode electrodes. Concentric concavo-convex shapes centered on the rotation axis of the shutter plate are formed on surfaces, that face each other, of the deposition preventing plate and the shutter plate. |
| US09627184B2 |
Cleaning method of processing apparatus, program for performing the method, and storage medium for storing the program
A plasma processing apparatus includes a processing chamber, in which a wafer W is plasma-processed, and a CPU controlling an operation of each component. A processing gas is introduced into the processing chamber under a first condition defined by a flow rate and a molecular weight of the processing gas, specifically based on a magnitude of a product A1 (=Q1×m1) of the flow rate Q1 and the molecular weight m1 of the processing gas, and a surface of the wafer W is physically or chemically etched. And then, a pre-purge gas which may be identical to or different from the processing gas is introduced into the processing chamber through a shower head under a second condition derived from the first condition. |
| US09627183B2 |
Plasma processing device, plasma processing method and method of manufacturing electronic devices
To provide a plasma processing device, a plasma processing method and a method of manufacturing electronic devices capable of performing high-speed processing as well as using the plasma stably. In an inductively-coupled plasma torch unit, a coil, a first ceramic block and a second ceramic block are arranged in parallel, and a long chamber has an annular shape. Plasma generated in the chamber is ejected from an opening in the chamber toward a substrate. The substrate is processed by moving the long chamber and the substrate mounting table relatively in a direction perpendicular to a longitudinal direction of the opening. A discharge suppression gas is introduced into a space between the inductively-coupled plasma torch unit and the substrate inside the chamber through a discharge suppression gas supply hole, thereby generating long plasma stably. |
| US09627181B2 |
Plasma processing apparatus
There is provided an inductively coupled plasma etching apparatus capable of suppressing a wavelength effect within a RF antenna and performing a plasma process uniformly in both a circumferential and a radial direction. In the plasma etching apparatus, a RF antenna 54 is provided on a dielectric window 52 to generate inductively coupled plasma. The RF antenna 54 includes an inner coil 58, an intermediate coil 60 and an outer coil 62 in the radial direction. The inner coil 58 includes a single inner coil segment 59 or more than one inner coil segments 59 connected in series. The intermediate coil 60 includes two intermediate coil segments 61(1) and 61(2) separated in a circumferential direction and electrically connected with each other in parallel. The outer coil 62 includes three outer coil segments 63(1), 63(2) and 63(3) separated in a circumferential direction and electrically connected with each other in parallel. |
| US09627174B2 |
Multi species ion source
A high brightness ion source with a gas chamber includes multiple channels, wherein the multiple channels each have a different gas. An electron beam is passed through one of the channels to provide ions of a certain species for processing a sample. The ion species can be rapidly changed by directing the electrons into another channel with a different gas species and processing a sample with ions of a second species. Deflection plates are used to align the electron beam into the gas chamber, thereby allowing the gas species in the focused ion beam to be switched quickly. |
| US09627171B2 |
Charged particle beam device
An objective of the present invention is to provide a charged particle beam device with which information based on a charged particle which is discharged from a bottom part of high-aspect structure is revealed more than with previous technology. To achieve the objective, proposed is a charged particle beam device comprising: a first orthogonal electromagnetic field generator which deflects charged particles which are discharged from a material; a second orthogonal electromagnetic field generator which further deflects the charged particles which are deflected by the first orthogonal electromagnetic field generator; an aperture forming member having a charged particle beam pass-through aperture; and a third orthogonal electromagnetic field generator which deflects the charged particles which have passed through the aperture forming member. |
| US09627169B2 |
Plasma ion source for use with a focused ion beam column with selectable ions
An inductively coupled plasma source having multiple gases in the plasma chamber provides multiple ion species to a focusing column. A mass filter allows for selection of a specific ion species and rapid changing from one species to another. |
| US09627164B2 |
Circuit breakers including short wired pigtail, base pans, installation methods and assemblies thereof
A circuit breaker including a housing and a short wired pigtail exiting the housing. The short wired pigtail has a factory length from a point of exit from the housing to a terminal end of less than about 16 cm, and can include pre-configured bends, and may be pre-stripped. In another aspect, a base pan for mounting a circuit breaker is provided. Base pan includes a plurality of busses, and an insulating base portion receiving the busses, the base pan configured to receive a circuit breaker thereon, the insulating base portion including a pigtail guide channel configured to direct a short wired pigtail towards a neutral bar socket as the circuit breaker is mounted to the insulating base portion. Circuit breakers, base pan assemblies, and methods of installing circuit breakers are provided, as are other aspects. |
| US09627161B2 |
Operating switch
A multi-directional operating switch to be used chiefly for operating a variety of electronic apparatuses is disclosed. This operating switch can determine a tilt angle of an operating body accurately. The operating switch comprises a fixed electrode body, a movable electrode body made of conductive material, and the operating body. The fixed electrode body includes a first fixed electrode on its top face. The movable electrode body is disposed on the fixed electrode body and includes a first pressing projection protruding toward the first fixed electrode. The operating body is disposed on the movable electrode body and can be tilted such that it presses the first pressing projection from above. The movable electrode body is elastic, so that the first pressing projection can be deformed such that an electrostatic capacity generated between the first pressing projection and the first fixed electrode can be changed. |
| US09627159B2 |
Method and apparatus for providing slide actuation on a device
A slide actuation apparatus includes a bezel configured to maintain a configuration of the slide actuation apparatus. The bezel also includes an opening on an external surface. The slide actuation apparatus also includes an actuator configured to move within a compartment formed by the opening and a sliding rail configured to guide movements of the actuator along a surface of the sliding rail. The sliding rail is compressible downward in response to movement of the actuator along the surface of the sliding rail. The slide actuation apparatus further includes a slide contact configured to make an electrical connection to a flexible circuit and configured to provide a signal of a change to a circuit board of an attached computing device in response to downward compression of the sliding rail. |
| US09627157B1 |
Keyboard
A keyboard including a fixing plate, a base plate, and a plurality of keys is provided. The base plate includes a plurality of magnetic elements, and each magnetic element corresponds to one key. Each key further includes a first support element and a second support element, and the first support element is made of a magnetic material. The key is disposed on the fixing plate, and the base plate may move relative to the fixing plate, so that the magnetic element is displaced and attracts the first support element to ascend or descend, so as to adjust the height of the key. |
| US09627155B2 |
Electrical switching device with a triple motion contact arrangement
A contact arrangement has a longitudinal axis and includes a first contact group with a first contact and a second contact and a second contact group with a third contact and a fourth contact. The first contact interacts electrically and mechanically with the third contact, and/or the second contact interacts electrically and mechanically with the fourth contact, for closing and opening the contact arrangement. At least one mechanical coupling is provided for transmitting an actuation force to the second contact group and thereby moving the second contact group. The at least one mechanical coupling is adapted to move the third and the fourth contact in such a way that their speeds differ along at least a portion of a travel path of the third contact or along at least a portion of a travel path of the fourth contact. |
| US09627149B2 |
Solid electrolytic chip capacitor and manufacturing method thereof
A solid electrolytic chip capacitor is provided which comprises a substrate layer, an electrical insulating block, a conductive polymer layer, a patterned reinforcement layer, and an electrode layer. The electrical insulating block is formed on the substrate layer to define an anode region and a cathode region on the substrate layer. The conductive polymer layer is formed to cover the cathode region of the substrate layer. The patterned reinforcement layer is formed to cover the conductive polymer. The electrode layer is formed to cover the patterned reinforcement layer. Whereby, the mechanical strength of the chip solid electrolytic capacitor can be improved without loss of capacitance. |
| US09627148B2 |
All-solid-state capacitor
An all-solid-state capacitor includes an inorganic solid electrolyte; and a pair of current collectors disposed so as to hold it in between. The inorganic solid electrolyte has a polycrystalline structure, and the all-solid-state capacitor satisfies a relationship given as: R1 |
| US09627142B2 |
Multilayer ceramic capacitor and board for mounting of the same
A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body. |
| US09627140B2 |
Capacitor component
The invention relates to a capacitor component having a first integrated capacitor (C1) and an integrated Y capacitor, wherein the Y capacitor has a second capacitor (C2) and a third capacitor (C3), and the second and third capacitor (C2, C3) are connected in series with one another and in parallel with the first capacitor (C1). The invention further relates to a method for producing such a capacitor component. |
| US09627137B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, length-direction first and second outer layer sections, and width-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A boundary portion between the outer portion and the inner portion has a larger Si content than the outer portion. The inner portion has a higher composition ratio of Mn to Ti than the outer portion. Each of minimum dimensions in the length direction of the length-direction first and second outer layer sections is greater than both dimensions in the width direction of the width-direction first and second outer layer sections. |
| US09627133B2 |
Laminated ceramic electronic component
A laminated ceramic electronic component that includes a laminated body formed by laminating a ceramic layer and an internal electrode, and forming an external electrode on an outer surface of the laminated body so as to be electrically connected to the internal electrode. The external electrode includes a conducting layer that is in contact with the internal electrode, and the internal electrode contains Ni. The conducting layer contains metal particles containing a Cu3Sn alloy, and a thermosetting resin. The internal electrode and the conducting layer are bonded to each other with a CuSnNi alloy phase interposed therebetween. |
| US09627132B2 |
Method of making multi-layer electronic components with plated terminations
Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrodes and optional anchor tabs, such as via electroless and/or electrochemical processes, until exposed portions of selected groups thereof are connected. |
| US09627129B2 |
Non-contact power supply system
In the present invention, it is possible to activate an electrical device, such as a flat-screen television or a photo frame, while the electrical device is located in a housing space (41) of a movable assembly (30). The degree of freedom in selecting the electrical device to be placed in the movable assembly (30) can be thus increased. Moreover, since a sliding door (movable assembly (30)) is moveable by sliding, the position of the sliding door, and thus of the electrical device, can be altered as a user desires. |
| US09627128B2 |
Antenna module, communication device and method of manufacturing antenna module
A communication device that, when incorporated in an electronic device, can reduce the size and the thickness of a housing of the electronic device while maintaining communication characteristics. The communication device includes an antenna coil that is arranged on a peripheral part of a housing surface facing a reader-writer of a mobile phone, a magnetic sheet that attracts the magnetic filed transmitted from the reader-writer to the antenna coil, and a communication processing unit that is driven by a current flowing through the antenna coil and communicates with the reader-writer. The magnetic sheet is arranged to be closer to reader-writer than the antenna coil in the central part, and the antenna coil is arranged to be closer to the reader-writer on the outer periphery side, and at least a part of the conductive line of the antenna coil is superimposed in a direction orthogonal to a circuit board. |
| US09627123B2 |
Solenoid
A solenoid includes: a coil wound around a bobbin; a case section accommodating the coil; a tubular yoke arranged on an inner circumferential portion of the coil; and a plunger arranged on an inner circumferential portion of the yoke, and moving from a start position along an axial direction of the yoke by magnetic attraction force generated in the yoke, wherein a diameter increasing portion whose diameter is increased from the start position toward a lower part in the axial direction is formed on an outer circumferential surface of the yoke, and the diameter increasing portion overlaps at least a part of a moving region of a lower-part side end portion of the plunger, and wherein an inner circumferential surface of the yoke guides the movement of the plunger and the yoke includes a contact member that regulates the movement of the plunger on the inner circumferential surface. |
| US09627122B2 |
High temperature solenoid actuator
A solenoid actuator includes a housing, a bobbin assembly, a coil, and a washer. The bobbin assembly is disposed at least partially within the housing, and includes a return pole and an armature. The return pole is fixedly coupled to the housing, and the armature is axially movable within the housing. The coil is disposed within the housing and is wound around at least a portion of the bobbin assembly. The washer is disposed between the coil and a portion of the bobbin assembly and surrounds a portion of the return pole. The washer is formed of an electrical insulator material. |
| US09627121B2 |
Solenoid robust against misalignment of pole piece and flux sleeve
An electromagnetic solenoid is disclosed. The solenoid includes a coil, a bobbin, a flux sleeve, an armature, and a pole piece, arranged in such a way that the solenoid is robust against misalignment of the pole piece with the flux sleeve. The configuration facilitates the integration of either the pole piece or the flux sleeve into a hydraulic circuit. |
| US09627115B2 |
Magnetic plasmonic nanoparticle dimer
Described embodiments include a system, method, and apparatus. The apparatus includes a plasmonic nanoparticle dimer. The dimer includes a first plasmonic nanoparticle having a first magnetic element covered by a first negative-permittivity layer comprising a first plasmonic outer surface. The dimer includes a second plasmonic nanoparticle having a second magnetic element covered by a second negative-permittivity layer comprising a second plasmonic outer surface. The dimer includes a separation control structure configured to establish a dielectric-filled gap between the first plasmonic outer surface and the second plasmonic outer surface. A magnetic attraction between the first magnetic element and the second magnetic element binds the first plasmonic nanoparticle and the second plasmonic nanoparticle together, separated by the dielectric-filled gap established by the separation control structure. The first plasmonic outer surface, the dielectric-filled gap, and the second plasmonic outer surface are configured to cooperatively support one or more mutually coupled plasmonic excitations. |
| US09627113B2 |
R-T-B based sintered magnet
The present invention provides a permanent magnet with a coercivity that will not be significantly decreased and a light weight compared to conventional R-T-B based permanent magnets. A core-shell structure is formed for the major phase grain by adding Cu to the R-T-B based magnet which is the raw material. When the mass concentration of Y in the core portion is set as EY, the mass concentration of Y in the shell portion is set as LY and the mass concentration of Y in the R2—Fe14—B crystal grain calculated from the ratio R1:Y in the total composition is set as SY, the ratio α of EY to SY (EY/SY) is 1.1 or more. Thus, the magnetic insulation among the crystal grains becomes better which prevents the coercivity from decreasing due to the addition of Y. Further, the addition of Y makes the magnet lighter in weight. |
| US09627112B2 |
Sintered ferrite magnet and motor provided therewith
A sintered ferrite magnet comprises a main phase of an M type Sr ferrite having a hexagonal crystal structure. An amount of Zn is 0.05 to 1.35 mass % in terms of ZnO and M1/M2 is 0.43 or less when an amount of a rare-earth element (R) is M1 in terms of mol and the amount of Zn is M2 in terms of mol. |
| US09627110B2 |
Chip resistor
[Problem] There is demand for chip resistors that are compact and that have high resistivity. [Solution] A chip resistor (100) has a substrate (11), a first connection electrode (12) and a second connection electrode (13) that are formed on the substrate (11), and a resistor network that is formed on the substrate (11) and that has ends one of which is connected to the first connection electrode (12) and the other one of which is connected to the second connection electrode (13). The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line (103) that is provided along inner wall surfaces of trenches (101). The resistive element film line (103) extending along the inner wall surfaces of the trenches (101) is long and has a high resistivity as a unit resistive element. [Effect] The resistivity of the chip resistor (100) as a whole can be increased. |
| US09627107B2 |
Method for operating a superconductive device without an external shunt system, in particular with a ring shape
A method for operating a superconducting device (1; 1a, 1b), having a coated conductor (2) with a substrate (3) and a quenchable superconducting film (4), wherein the coated conductor (2) has a width W and a length L, is characterized in that 0.5≦L/W≦10, in particular 0.5≦L/W≦8, and that the coated conductor (2) has an engineering resistivity ρeng shunting the superconducting film (4) in a quenched state, with ρeng>2.5 Ω, wherein RIntShunt=ρeng*L/W, with RIntShunt: internal shunt resistance of the coated conductor (2). The risk of a burnout of a superconducting device in case of a quench in its superconducting film is thereby further reduced to such an extent that the device can be operated without use of an additional external shunt. |
| US09627105B2 |
Coaxial cable for the electrical transmission of a radiofrequency and/or high-speed data signal, rotating joint comprising two such coaxial cables, and retaining apparatus comprising at least one such rotating joint
The invention relates to a coaxial cable for electrical transmission of a high-frequency and/or high-speed data signal, in particular for medical-engineering applications, comprising a arranged radially inside and a plurality of shields which surround the core radially outside, the core exhibiting a litz with a plurality of individual wires. The invention further relates to a rotary coupling with two coaxial cables of such a type, and also to a holding device, in particular a ceiling support, with such a rotary coupling. |
| US09627100B2 |
High-power low-resistance electromechanical cable
A high-power low-resistance electromechanical cable constructed of a conductor core comprising a plurality of conductors surrounded by an outer insulating jacket and with each conductor having a plurality of wires that are surrounded by an insulating jacket. The wires can be copper or other conductive wires. The insulating jacket surrounding each set of wires or each conductor can be comprised of ethylene tetrafluoroethylene, polytetrafluoroethylene, polytetrafluoroethylene tape, perfluoroalkoxyalkane, fluorinated ethylene propylene or a combination of materials. A first layer of a plurality of strength members is wrapped around the outer insulating jacket. A second layer of a plurality of strength members may be wrapped around the first layer of a plurality of strength members. The first and/or second layer of strength members can be made of single wires, synthetic fiber strands multi-wire strands, or rope. If either or both layers are made up of synthetic fiber, then the synthetic fibers may be surrounding and encapsulated by an additional insulating and protective layer. |
| US09627099B2 |
Crosslinkable halogen-free resin composition, cross-linked insulated wire and cable
A crosslinkable halogen-free resin composition includes a polymer blend, and a metal hydroxide mixed in an amount of 120 to 200 parts by mass per 100 parts by mass of the polymer blend. The polymer blend includes a maleic anhydride-modified high-density polyethylene, 30 to 50 parts by mass of an ethylene-acrylic ester-maleic anhydride terpolymer, 5 to 20 parts by mass of a maleic anhydride modified ethylene-α-olefin copolymer and 10 to 30 parts by mass of an ethylene-acrylic ester copolymer. |
| US09627095B1 |
Memory module, memory system including the same and operation method thereof
A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips. |
| US09627093B2 |
Memory device having RRAM-based non-volatile storage array and repair function
A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. |
| US09627092B2 |
Semiconductor device performing error correction operation
A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region. |
| US09627091B1 |
Memory device and stress testing method of same
A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells. |
| US09627090B1 |
RAM at speed flexible timing and setup control
Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches. |
| US09627084B2 |
Storage device including nonvolatile memory device and controller
A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation. |
| US09627081B2 |
Manufacturing mode for secure firmware using lock byte
Upon initialization or startup of an electronic device, the device checks a predetermined section of non-volatile memory, referred to as the signature byte or lock byte, and allows either the manufacturing mode which allows for installation of the final or production version of firmware to be loaded into non-volatile memory, or the production mode which write-protects certain portions of non-volatile memory before giving operating control of the electronic device to another program, for example, an operating system. By only allowing execution of operating system or other executable code after write-protecting certain portions of non-volatile memory, system security, integrity, and robustness are substantially increased. |
| US09627079B1 |
Storage device, memory system having the same, and operating method thereof
There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed. |
| US09627077B2 |
Semiconductor memory device storing management data redundantly in different pages
A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data. |
| US09627076B2 |
Nonvolatile memory device and erasing method thereof
According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation. |
| US09627075B1 |
Semiconductor memory device and semiconductor system
A semiconductor memory device may include: a memory cell array comprising a plurality of memory cells coupled to a plurality of bit line pairs and a plurality of word lines; and an operation circuit suitable for setting a parameter corresponding to an input command, and performing an operation corresponding to the input command on the memory cell array based on the set parameter, wherein, when the input command is of the same type as a previous input command, the operation circuit skips setting the parameter for each of preset word line groups. |
| US09627073B2 |
Systems, methods, and apparatus for memory cells with common source lines
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor. |
| US09627072B2 |
Variant operation sequences for multibit memory
A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode. |
| US09627068B2 |
Twin memory cell interconnection structure
Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline. |
| US09627067B2 |
Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described. |
| US09627057B2 |
Programming two-terminal memory cells with reduced program current
Providing for programming a two-terminal memory cell array with low sneak path current is described herein. Groups of two-terminal memory cells can be arranged into blocks or sub-blocks, along sets of bitlines and local wordlines. Further, groups of local wordlines within a given sub-block can be electrically isolated from bitlines outside the sub-block. A programming signal can be applied to the two-terminal memory cells from an associated local wordline thereof. Sneak path currents can be mitigated or avoided with respect to bitlines outside a particular sub-block, or on non-selected wordlines of the sub-block. This can significantly reduce a magnitude of combined sneak path current within the sub-block in response to the programming operation. |
| US09627055B1 |
Phase change memory devices and systems having reduced voltage threshold drift and associated methods
Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold drift to increase read accuracy of phase change memory. A pre-read pulse can be delivered across a select device and a phase change material of a phase change memory cell to at least partially reset the voltage threshold drift of the select device while maintaining a program state of the phase change material. |
| US09627053B2 |
Memory device and access method
A memory device includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction crossing the first direction, and a plurality of memory cells. Each memory cell includes a memory element and two select transistors disposed along the first direction and the memory element being configured to store information based on changes in resistance. A first and a second column are formed by repeatedly arranging a first group and a second group of the memory cells, respectively, along the first direction, and the second column is disposed adjacent to the first column and the first group is displaced in the first direction such that, in the second direction, a first select transistor in respective memory cells in the first column is aligned with a second select transistor in respective memory cells in the second column. |
| US09627052B1 |
Apparatuses and methods for current limitation in threshold switching memories
Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell. |
| US09627049B1 |
Reprogram without erase using capacity in multi-level NAND cells
Inventive aspects include a memory device having one or more memory pages including a plurality of memory cells each having a plurality of programmable state levels. The memory device includes a memory control logic section including a program logic section and page-level reprogram state metadata. The program logic section may program the plurality of memory cells dependent on the page-level reprogram state metadata. The program logic section may program a first state level, a second state level, and a third state level of each of the memory cells in consecutive programming operations of the plurality of memory cells dependent on the page-level reprogram state metadata, without requiring any erase operations or read operations during or between the programming operations. |
| US09627043B1 |
9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures. |
| US09627037B2 |
Semiconductor memory device with a power gating circuit for reducing an instantaneous voltage drop
A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction. |
| US09627036B2 |
Static random access memory layout structure
A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects. |
| US09627032B2 |
Address generation circuit and memory device including the same
An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit. |
| US09627030B1 |
Efficient calibration of a data eye for memory devices
A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times. |
| US09627029B2 |
Method for training a control signal based on a strobe signal in a memory module
A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal. |
| US09627022B2 |
Double pumped memory techniques
A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal. |
| US09627016B2 |
Systems, methods, and devices for parallel read and write operations
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground. |
| US09627011B1 |
Sense amplifier circuit with offset compensation for a non-volatile memory device
A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step. |
| US09627010B2 |
Semiconductor device, electronic component, and electronic device
Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating. |
| US09627008B2 |
Recording medium, reproducing apparatus, and reproducing method
In a recording medium on which is recorded a multiplexed stream including a plurality of first packets (V_main) constituting a first I-picture in a first video stream and a plurality of second packets (V_sub) constituting a second I-picture in a second video stream, information for identifying the first I-picture and information for identifying the second I-picture are recorded on the medium. A recording medium can thereby be obtained that enables the rapid detection, from a small amount of information, of a particular picture included in a stream such as a TS in which multiple content streams are multiplexed. |
| US09627005B2 |
Video processing apparatus and control method of video processing apparatus
In a video processing apparatus, an input processing unit inputs a video frame, a first video processing unit performs image processing on the input video frame, and an output processing unit outputs the image processed video frame to display it. Further, a control unit in the video processing apparatus controls the image processing so that a video frame subjected to freeze display in response to an input of a pause instruction to the video processing apparatus is displayed in the high image quality. |
| US09627003B2 |
Explosion proof underground mining recording system and method of using same
Methods, systems, and apparatuses are disclosed for an explosion proof recording system for recording an underground mining environment and other hazardous, low or restricted visibility environments. |
| US09627002B2 |
Editing digital film
An apparatus and method for editing digital picture computer files and digital audio computer files is disclosed herein. The apparatus and method for editing involves recording digital picture files and digital audio files. The digital picture files are copied onto a storage area network, and loaded onto a data storage system. Metadata from the digital picture files is uploaded onto a metadata database. The digital picture files on the storage area network are compressed. The compressed digital picture files are combined and synchronized with their corresponding digital audio files. These resultant digital files are then organized with their corresponding metadata. Once the metadata is incorporated into the resultant digital files, the files are edited and an editing decision list document as well as editing instructions are generated. Digital picture files are downloaded from the data storage system and conformed with digital audio files to produce the final media product. |
| US09626999B1 |
Systems and methods for real time ITI compensation in a multi-dimensional equalizer
Systems and methods relating generally to data storage, and more particularly to systems and methods for accessing and storing information using multiple sensors. |
| US09626996B2 |
Block copolymer self-assembly for pattern density multiplication and rectification
Provided herein is a method, including a) transferring an initial pattern of an initial template to a substrate; b) performing block copolymer self-assembly over the substrate with a density multiplication factor k; c) creating a subsequent pattern in a subsequent template with the density multiplication factor k; and d) repeating steps a)-c) with the subsequent template as the initial template until a design specification for the subsequent pattern with respect to pattern density and pattern resolution is met. |
| US09626993B2 |
Actuator coil temperature estimation using skew values
A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a controller of a data storage device to cause the controller to perform a method including, determining, by the controller, a test skew gain of a coil using skew information from a servo subsystem of the controller; comparing, by the controller, the test skew gain to a stored reference gain; and taking an action, by the controller, in response to the comparing of the test skew gain to the reference gain. |
| US09626992B2 |
Read assembly, data storage system, and methods of using the same
In various embodiments, a read assembly for reading a dual-layered medium may be provided. The dual-layered medium may include a servo layer and a data layer over the servo layer. The read assembly may include a data read head configured to read the data layer. The read assembly may also include a servo read head configured to read the servo layer. |
| US09626991B2 |
Near-field transducer with enlarged region, peg region, and heat sink region
A near-field transducer includes an enlarged region having a top side adjacent to a magnetic pole, a base side opposite the top side, and a circumference that extends from proximal to a media-facing surface to distal to a media-facing surface. The near-field transducer includes a peg region in contact with a region of the bas side of the enlarged region, the peg region extending from the enlarged region towards the media-facing surface. The near-field transducer also includes a heat sink region having a contact side, a base side, and a circumference that extends from proximal to the media-facing surface to distal from the media-facing surface. The contact side of the heat sink region is in thermal contact with both the peg region and at least a region of the base side of the enlarged region. |
| US09626986B2 |
Estimation of background noise in audio signals
The invention relates to a background noise estimator and a method therein, for supporting sound activity detection in an audio signal segment. The method comprises reducing a current background noise estimate when the audio signal segment is determined to comprise music and the current background noise estimate exceeds a minimum value. This is to be performed when an energy level of an audio signal segment is more than a threshold higher than a long term minimum energy level, lt_min, which is determined over a plurality of preceding audio signal segments, or, when the energy level of the audio signal segment is less than a threshold higher than lt_min, but no pause is detected in the audio signal segment. |
| US09626982B2 |
Device and method for quantizing the gains of the adaptive and fixed contributions of the excitation in a CELP codec
A device is for retrieving a quantized gain of a fixed contribution of an excitation in a sub-frame of a frame. The device includes a receiver of a gain codebook index; an estimator of the gain of the fixed contribution of the excitation in the sub-frame, wherein the estimator is supplied with a parameter representative of a classification of the frame; a gain codebook for supplying a correction factor in response to the gain codebook index; and a multiplier of the estimated gain by the correction factor to provide a quantized gain of the fixed contribution of the excitation in said sub-frame. |
| US09626979B2 |
Apparatus for quantizing linear predictive coding coefficients, sound encoding apparatus, apparatus for de-quantizing linear predictive coding coefficients, sound decoding apparatus, and electronic device therefore
A quantizing apparatus is provided that includes a quantization path determiner that determines a path from a first path not using inter-frame prediction and a second path using the inter-frame prediction, as a quantization path of an input signal, based on a criterion before quantization of the input signal; a first quantizer that quantizes the input signal, if the first path is determined as the quantization path of the input signal; and a second quantizer that quantizes the input signal, if the second path is determined as the quantization path of the input signal. |
| US09626973B2 |
Adaptive bit allocation for multi-channel audio encoding
The invention provides a highly efficient technique for encoding a multi-channel audio signal. The invention relies on the basic principle of encoding a first signal representation of one or more of the multiple channels in a first encoder and encoding a second signal representation of one or more of the multiple channels in a second, multi-stage, encoder. This procedure is significantly enhanced by providing a controller for adaptively allocating a number of encoding bits among the different encoding stages of the second, multi-stage, encoder in dependence on multi-channel audio signal characteristics. |
| US09626967B2 |
Information processing method and electronic device
The present disclosure discloses an information processing method and an electronic device. The electronic device comprises a first processing unit and a second processing unit. The second processing unit is capable of executing at least one application program. The information processing method comprises: collecting first sound information; when the first sound information comprises first information which matches with audio data preset in the first processing unit, generating a first instruction, and transmitting the first instruction to the second processing unit; when it is determined that there is a first application which meets a predetermined condition in the at least one application program, generating, by the second processing unit, a second instruction based on the first instruction and the first application; and executing the second instruction in the first application. |
| US09626965B2 |
Efficient empirical computation and utilization of acoustic confusability
Efficient empirical determination, computation, and use of an acoustic confusability measure comprises: (1) an empirically derived acoustic confusability measure, comprising a means for determining the acoustic confusability between any two textual phrases in a given language, where the measure of acoustic confusability is empirically derived from examples of the application of a specific speech recognition technology, where the procedure does not require access to the internal computational models of the speech recognition technology, and does not depend upon any particular internal structure or modeling technique, and where the procedure is based upon iterative improvement from an initial estimate; (2) techniques for efficient computation of empirically derived acoustic confusability measure, comprising means for efficient application of an acoustic confusability score, allowing practical application to very large-scale problems; and (3) a method for using acoustic confusability measures to make principled choices about which specific phrases to make recognizable by a speech recognition application. |
| US09626961B2 |
Systems and methods for personifying communications
Systems and methods are described for personifying communications. According to at least one embodiment, the computer-implemented method for personifying a natural-language communication includes observing a linguistic pattern of a user. The method may also include analyzing the linguistic pattern of the user and adapting the natural-language communication based at least in part on the analyzed linguistic pattern of the user. In some embodiments, observing the linguistic pattern of the user may include receiving data indicative of the linguistic pattern of the user. The data may be one of verbal data or written data. Written data may include at least one of a text message, email, social media post, or computer-readable note. Verbal data may include at least one of a recorded telephone conversation, voice command, or voice message. |
| US09626960B2 |
Systems and methods for providing metadata-dependent language models
Techniques for generating language models. The techniques include: obtaining language data comprising training data and associated values for one or more metadata attributes, the language data comprising a plurality of instances of language data, an instance of language data comprising an instance of training data and one or more metadata attribute values associated with the instance of training data; identifying, by processing the language data using at least one processor, a set of one or more of the metadata attributes to use for clustering the instances of training data into a plurality of clusters; clustering the training data instances based on their respective values for the identified set of metadata attributes into the plurality of clusters; and generating a language model for each of the plurality of clusters. |
| US09626952B2 |
Emulsion composition for vibration damping materials
The present invention aims to provide a composition for vibration damping materials which provides excellent vibration damping property. The present invention relates to an emulsion composition for vibration damping materials including: a vibration damping modifier including a compound that has 7 or more carbon atoms, a boiling point of 190° C. or higher, and at least two ether groups or at least two ester groups in the molecule; and a polymer emulsion. |
| US09626951B2 |
Mounting system for a fish finding device
There is provided a mounting system for a fish finding device to a watercraft which has a support for supporting a fish finding device on a watercraft. The support has a top, a bottom and a peripheral side wall which form a receptacle housing for a battery. Mounting means are positioned at the top of the support to receive a fish finder. Securing means are provided on the bottom of the support for mounting the support to a surface on a watercraft. Mounting means are provided for detachably securing a transducer to a watercraft. |
| US09626950B2 |
Audio system and method for reduction and/or elimination of distortion
A microphone or instrument sound pickup for various musical instruments and singers is coupled to an amplifier, the output of which is coupled to a speaker system. A microphone is positioned within the output range of the speaker system and is coupled to one input of a comparator circuit. The remaining input of the comparator circuit is coupled to the microphones or pickups. An additive device receives the output signal of the comparator and the originating signal from the microphones or pickups to form a correcting audio signal which is applied to the amplifier. In an alternate embodiment, an adaptive preamplifier is interposed between the originating microphones and audio pickups and the amplifier. The adaptive preamplifier receives the output of the comparator and imposes alteration upon the signal processed through the preamplifier for application to the amplifier. |
| US09626948B2 |
Systems and methods for a variable aperture electromagnetic pickup for stringed musical instruments
Embodiments disclosed herein describe systems and methods for asymmetrical bobbin configurations. Embodiments of asymmetrical bobbin configurations are configured to allow manufacturers and users to modify, adjust, change, etc. the tone of pickups. The asymmetrical bobbin configurations are configured to boost frequencies on strings on an instrument, wherein based on the configurations of the bobbins different frequencies may be modified. |
| US09626943B1 |
Method and apparatus for producing balanced drumstick pairs
One or more drumsticks may be optimally balanced using a grip point of the drumstick by calculating a radius of gyration. The radius of gyration is a controlling parameter wherein the radius of gyration correlates with the grip point, which is itself based on a particular gripping style and hand size. Given the radius of gyration, the center of gravity of the one or more drumsticks may be re-located at a point along the drumstick closely aligned to the radius of gyration. The re-location may be performed by adding a weight to the butt end of the drumstick. Balanced drumstick pairs provide optimum performance, control and handling characteristics for a drummer. |
| US09626942B2 |
Flute support
An apparatus comprises a flute, a base, and a thumb rest. The base is attached to the flute and defines a channel. The thumb rest is inserted into the channel and defines an elongate body. The thumb rest is positioned such that a flutist may rest a right thumb against the thumb rest while using conventional fingering to play the flute. |
| US09626940B2 |
Data processing device, display control device, semiconductor chip, method of controlling display device, and computer-readable medium
A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory. The controller is configured to, when the processed update-data and the update-control-information identifier are stored on the first memory, execute the drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored in the first memory in response to the instruction from the updating unit. |
| US09626938B2 |
Display unit
A display unit has a flexible display section, a detection section for detecting a deflection amount and a deflection direction of the display section, a determination section for determining a visible portion and a non-visible portion of the display section based on the deflection amount and the deflection direction, and a control section for controlling display contents of the display section. The control section either prevents an image display on the non-visible portion or displays one of a fixed image or a pre-set moving image on the non-visible portion. The display unit also includes a displacement sensor located in the same region as the display section. |
| US09626936B2 |
Dimming module for augmented and virtual reality
The technology provides a dimming module for a near-eye display (NED) device that controls an amount of ambient light that passes through the transmissive near-eye display to a user. The dimming module includes at least one electrochromic cell that enables variable density dimming so that the NED device may be used in an augmented reality (AR) and/or virtual reality (VR) application. The electrochromic cell may be a monochrome electrochromic cell having stacked layers of, a monochrome electrochromic compound layer and insulator sandwiched between a pair of transparent substrates and conductors. A current may be applied to the conductor layers to control the amount of dimming in response to a dimming value. A NED device having a dimming module may be included in a visor, or other type of head-mounted display (HMD). The dimming module may be flat and supported by a flat waveguide mount in the user's field of view. |
| US09626931B2 |
Display device
A display device is capable of preventing damage to a driver integrated circuit (IC) when a malfunction occurs therein, the display device including a display panel including a gate line, a data line, a first dummy line, and a second dummy line; a first data driver integrated circuit connected to one side of the data line; a second data driver integrated circuit connected to another side of the data line; a first power supply configured to apply a part of first enable signals to the first data driver integrated circuit, and to apply a part of second enable signals to the second data driver integrated circuit through the second dummy line; and a second power supply configured to apply the rest of the second enable signals to the second data driver integrated circuit, and to apply the rest of the first enable signals to the first data driver integrated circuit through the first dummy line. |
| US09626927B2 |
Driving circuit and liquid crystal display (LCD) apparatus thereof
A driving circuit comprising a signal edge cutting circuit is described. The signal edge cutting circuit comprises a first switch unit, a second switch unit and a third switch unit wherein the third switch unit decreases a voltage amplitude of the scanning signal by an edge-cutting resistor for implementing the signal edge cutting procedure of the scanning signal. The present invention further provides an LCD apparatus and employs the third switch unit for eliminating the image sticking phenomenon of the display image advantageously. |
| US09626926B2 |
Liquid crystal display device
Provided is a liquid crystal display device that includes: pixels, a pixel control unit, and a common voltage generation unit. The pixel includes: a display element; a first switching unit configured to sample each frame data; a first holding unit configured to form an SRAM, and to hold sub-frame data sampled; a second switching unit configured to output the sub-frame data; and a second holding unit configured to form a DRAM, and configured of which stored content is rewritten by the sub-frame data. The pixel control unit is configured to repeat writing the sub-frame data into the first holding units, and to operate to rewrite the stored content in the second holding units. The common voltage generation unit is configured to change a voltage value of a common voltage from a first voltage value to a second voltage value determined based on at least the one frame period. |
| US09626925B2 |
Source driver apparatus having a delay control circuit and operating method thereof
A source driver apparatus and an operating method thereof are provided. The source driver apparatus can drive a plurality of source lines of a display panel, wherein the display panel further comprising a gate driver apparatus. The source driver apparatus includes driving channels and a delay control circuit. The driving channels output source driving signals. The delay control circuit controls the driving channels to change delay times of the source driving signals within the same period, such that the delay times of the source driving signals respectively correspond to distances from the source lines to the gate driver apparatus. |
| US09626923B2 |
Display device and electronic apparatus
According to an aspect, a display device includes an image display panel, data lines, and scan lines. The image display panel includes arrays of pixels including a plurality of sub-pixels. The arrays of pixels include cyclically arranged columns of first columns each of which includes first sub-pixels, second columns that include second sub-pixels, and third columns. Third sub-pixels and fourth sub-pixels are alternately arranged in the third columns in the direction along the third columns, and are alternately arranged in a direction along the row in the same row of the third columns. Each of the scan lines is coupled to either of the third sub-pixels adjacent thereto or the fourth sub-pixels adjacent thereto, as sub-pixels to be selected thereby. |
| US09626921B2 |
Projection display providing additional modulation and related methods
A projection display system includes a spatial modulator that is controlled to compensate for flare in a lens of the projector. The spatial modulator increases achievable intra-frame contrast and facilitates increased peak luminance without unacceptable black levels. Some embodiments provide 3D projection systems in which the spatial modulator is combined with a polarization control panel. |
| US09626914B2 |
Display device and output buffer circuit for driving the same
Disclosed herein is a display device including: a plurality of pixel circuits; a power source line connected to corresponding ones of the plurality of pixel circuits; and an output buffer circuit for supplying currents to corresponding ones of the plurality of pixel circuits by alternately applying a first potential applied to a first power source supply terminal, and a second potential applied to a second power source supply terminal to the power source line. The output buffer includes a variable resistance circuit connected to a path between the first power source supply terminal and the power source line, the variable resistance circuit serving to change a resistance value thereof in accordance with a magnitude of a total sum of the currents. |
| US09626912B2 |
Electroluminescent display and method of driving the same
An electroluminescent display and a method of driving the same are disclosed. In one aspect, the display includes a display panel including a plurality of pixel units electrically connected to a plurality of data lines and a plurality of gate lines. The pixel units are arranged in a matrix of a plurality of rows and a plurality of columns, the pixel units in the same column are connected to the same data line, and the pixel units in the same diagonal line of the matrix are connected to the same gate line. The display also includes a data driver located at a first side of the display panel, the data driver being configured to drive the data lines, and a gate driver located at the first side of the display panel and configured to drive the gate lines. |
| US09626911B2 |
Light emitting period setting method, driving method for display panel, driving method for backlight, light emitting period setting apparatus, semiconductor device, display panel and electronic apparatus
Disclosed herein is a light emitting period setting method for a display panel wherein the peak luminance level is varied through control of a total light emitting period length which is the sum total of period lengths of light emitting periods arranged in a one-field period, including a step of setting period lengths of N light emitting periods, which are arranged in a one-field period, in response to the total light emitting period length such that the period lengths of the light emitting periods continue to keep a fixed ratio thereamong, N being equal to or higher than 3. |
| US09626910B2 |
Pixel driver circuit, display panel and driving method for the pixel driver circuit
A pixel driver circuit including a first transistor, second transistor, third transistor, fourth transistor, first capacitor, second capacitor, and organic light-emitting diode is provided. A drain of the second transistor is coupled to a cathode of the organic light-emitting diode, and an anode of the organic light-emitting diode is couple to a power line. A source of the second transistor is respectively coupled to drains of the third transistor and the fourth transistor. A source of the third transistor is coupled to a gate of the second transistor, and gates of the third transistor and the fourth transistor receives a compensation control voltage. A source of the fourth transistor is grounded. A shift of the threshold voltage of an AMOLED can be compensated in an embodiment of the present invention, whereby uniformity between a picture and grayscales of the organic light-emitting diodes can be improved. |
| US09626909B2 |
Organic light emitting diode driver
Disclosed are controllable drive circuits for powering an organic light emitting diode (OLED) or other electronic load. According to one implementation, a circuit structure is provided that applies a pulse width modulated (PWM) drive current to an OLED. The time-average drive current to the OLED can be modulated in accordance with a periodically sampled control signal. In turn, the luminance of the OLED can be suitably varied over a control range. Circuit structures provided may be fabricated at least in part on a common substrate such that respective integrated circuit devices are defined. In one or more implementations, at least a portion of drive circuits may be fabricated within a 65 nanometer (or smaller) environment. |
| US09626908B2 |
Smart pixel lighting and display microcontroller
A light emitting assembly is described. In one embodiment, one or more light emitting diode (LED) devices and one or more microcontrollers are bonded to a same side of a substrate, with the one or more microcontrollers to switch and drive the one or more LED devices. |
| US09626905B2 |
Pixel circuit and electroluminescent display including the same
A pixel circuit and an electroluminescent display including the same are disclosed. In one aspect, the pixel circuit includes a scan transistor connected between a data line and a first node and having a gate electrode configured to receive a scan signal, a driving transistor connected between a first power supply voltage and a third node and having a gate electrode connected to a second node, an emission control transistor connected between the third node and a fourth node and having a gate electrode configured to receive an emission control signal, a light-emitting diode connected between the fourth node and a second power supply voltage less than the first power supply voltage, and a compensation circuit initializes the second node to an initial voltage during a first compensation period and electrically connects the second node to the third node during a second compensation period following the first compensation period. |
| US09626903B2 |
Organic light-emitting diode (OLED) display panel for decreasing off-leakage current and OLED display having the same
An organic light-emitting diode (OLED) display panel is disclosed. In one aspect, the panel includes a first transistor which receives a data signal transferred through a data line in response to a scan signal transferred through a gate line and a second transistor which receives a first power signal in response to a bias signal and outputs a source-driving signal. The panel also includes a third transistor which receives the source-driving signal in response to an output signal of the first transistor and outputs a driving signal, an organic light-emitting element which comprises a first electrode being connected to the third transistor and which receives the driving signal and a second electrode which receives a second power signal. The panel further includes a fourth transistor which is electrically connected to the third transistor and which receives the driving signal. |
| US09626899B2 |
Electro-optical apparatus and electronic apparatus
There is provided an electro-optical apparatus which is wearable on a human body, including: a display unit that includes pixels and a drive circuit which drives the pixel; and an case that contains the display unit and includes a contact surface which comes into contact with the human body. The contact surface is arranged to have at least one space from the display unit. |
| US09626898B2 |
Flat panel display
A flat panel display is disclosed. In one aspect, the flat panel display includes a plurality of pixels arranged in rows and columns. The pixels include red, green, and blue pixels. The green pixels are formed to be spaced apart in the row and column directions such that at least two neighboring green pixels are indistinguishable at a predetermined viewing distance. |
| US09626894B2 |
Method and apparatus for subpixel rendering
Method and apparatus for subpixel rendering. In one example, for each of an array of pixels on a display, a first signal including a first set of components is received. The first set of components are converted to a second set of components. The second set of components include a first component representing a first attribute of the pixel and a second component representing a second attribute of the pixel. The second set of components of the first signal are modified to generate a second signal by applying at least one operation to at least one of the first and second components based on the corresponding attribute of the pixel. The modified second set of components are converted to a modified first set of components of the second signal. A third signal is generated based on the modified first set of components for rendering subpixels corresponding to the pixel. |
| US09626889B2 |
Method and program for driving information processing device
A method for driving an information processing device which is adaptable to a wider variety of input methods is provided. The coordinates of an operating body at a starting point in the XYZ space and the coordinates of the operating body at an ending point in the XYZ space after a certain period of time are obtained, and the Z coordinate at the ending point and the movement distance on the X-Y plane in the certain period of time are calculated. Then, a signal is output only in the case where both the distance from an operating surface to the operating body in the vertical direction and the movement distance in the horizontal direction exceed the respective threshold values. In this manner, input operation can be performed by a three-dimensional motion, which includes movement of the operating body in the vertical direction as well as in the horizontal direction. |
| US09626888B2 |
Method and apparatus for testing display panel
A method and an apparatus for testing a display panel are provided. The apparatus comprises an interface circuit for connecting to the display panel to be tested, and a test circuit for generating a test signal to the display panel through the interface circuit in a test state for a display panel, and for generating an adjustment signal to the display panel through the interface circuit in a predetermined state for the display panel, wherein at least a portion of an afterimage signal in the display panel is reduced by the adjustment signal. |
| US09626885B1 |
Secure door display holder and protector
A device for protecting a door includes a body extending over at least a portion of the door and two inserts, extending from opposing edges of the body between the door and the door frame. A rod attached to the two inserts and extending therebetween contacts a surface of the door and secures the device thereto. |
| US09626884B2 |
LED light engine for signage
A durable LED light engine includes a printed circuit board including LEDs mounted thereon positioned between a substantially U-shaped top enclosure and a bottom enclosure. Once assembled together using alignment holes and projections, the combination of the substantially U-shaped top enclosure, the printed circuit board and the bottom enclosure are held together with a molding material. |
| US09626881B1 |
Skull mount
An adjustable mounting bracket for mounting a skull of an animal onto a wall or other flat surface. The mounting bracket is adjustable so that the angle at which the skull is held can be changed, so that the mounted skull of the animal can be rotated from side to side, and so that the stinger to which the skull is secured to the mounting bracket can be lifted off of the base of the mounting bracket without removing the base from the wall to which it is secured. The base can be made in a variety of shapes and designs to add to the esthetics of the mount. Adjustment of the mounting bracket does not require any tools. The stinger is removable which facilitates marketing, packaging and distribution requirements in addition to making it easier to attach a skull to it. |
| US09626880B2 |
Modular system of building with elastic material and potential applications
A system of construction that uses a discrete repertoire of elastic modular units that interconnect forming assemblies of diverse curved geometries applicable at any scale.Each modular unit is formed with linear elements with less than infinite elastic modulus. The modular units connect to one another under tension creating structural networks that have stored elastic potential energy.The linear elements may be formed of carbon based composite materials and their future permutations, including smart materials. The modular assemblies created using this system have application in terrestrial, space and aquatic environments and as an educational tool. |
| US09626870B2 |
Method for communicating within an ad hoc-type motor vehicle communication system
A method for communicating based on an ad hoc-type motor vehicle communication system, in which transportation users communicate with one another and/or transportation users and the transportation infrastructure communicate, includes determining the valid directions of travel independently based on messages transmitted by transportation users and determining travel in the wrong direction based on these messages. Corresponding further messages may be transmitted in response to the hazardous situation. A transportation infrastructure device and to a transportation user device may implement the method. |
| US09626867B2 |
False warning suppression in a collision avoidance system
A system and method for suppressing collision warning in a host vehicle is provided. The system receives position data from a remote vehicle. The host vehicle suppresses a collision warning when a detected stationary object is in a safe-zone based on the remote vehicle position data, thereby preventing false collision warnings. |
| US09626866B2 |
Active warning system using the detection of driver awareness of traffic signs
Traffic sign warnings are provided to a driver by optically scanning an area in front of the moving vehicle to obtain an image of said area in front of the moving vehicle. Road signs are recognized and their importance categorized. A driver's eyes are continuously scanned to determine whether the driver's eyes' ever focus on, or are directed to a detected and recognized road sign. Multiple different visual and/or audible warnings or alarms are generated based on the nature of a road sign, its proximity to the moving vehicle, and the driver's determined awareness of the road sign. |
| US09626860B2 |
Intraoral methods and apparatus for controlling services and devices
Methods and systems are disclosed that, in some aspects, provide for receiving input from sensors placed in a user's mouth. The methods and systems may include a plurality of sensors in communication with a controller. Each sensor may be affixed to one of a plurality of teeth. The controller may generate an action signal when a sensor signal exceeds a sensor signal threshold value. Aspects of the disclosure also provide for methods that may include detecting a sensor signal exceeding a sensor signal threshold value, generating an action signal, and transmitting the action signal, the action signal comprising information identifying the sensor associated with the detected sensor signal. |
| US09626859B2 |
Electronic locking systems, methods, and apparatus
Electronic locking devices, systems, and methods may require the utilization of an electronic key generated by an electronic key generation device. The electronic key may be generated using a data payload received from server and/or an administrative device. The administrative device is enabled to remotely manage the locking device and locking system via, for example, a software application running on the administrative device and/or a website. |
| US09626857B2 |
System for transmitting baggage items
A system for transmitting baggage items in vehicles, having a first communication module for communicating with a communication terminal that requests authorization data via a network, an identification routine that identifies a supplier, a second communication module for communication to a control device of an access system for a vehicle, a second identification routine for identification of the system by the access system, a third communication module for receiving request information (AA) from the driver, and an updating routine for updating authorization data of the system. A baggage detection unit detects baggage items loaded into the vehicle. Data regarding the baggage items is transmitted to a logistics service provider and after executing the updating routine transmits information on the baggage items to the vehicle access system. The control device of the access system generates a message regarding the transmission of baggage items via a bus system in the vehicle. |
| US09626854B2 |
Lifeguard alarm system for detecting a state of a swimmer
A lifeguard alarm system for swimmers, capable of detecting whether a swimmer is moving forward or drowning. The system includes a detecting device, an accelerometer disposed on the detecting device and a computing unit; the accelerometer configured to output respective acceleration values along X, Y, and Z axes of the detecting device and of gravity, the computing unit configured to calculate a sum of squares of the X, Y and Z acceleration values of the accelerometer as a first value and square of an acceleration of gravity as a second value and to compare the first value with the second value. A relationship between the first value and the second value can be used to control the warming unit. |
| US09626853B2 |
Thermal switch
Technology for a thermal switch is described. The thermal switch can include a first conducting layer. The thermal switch can include a second conducting layer. The thermal switch can include a material layer in between the first conducting layer and the second conducting layer. The material layer can be a conductor when above a defined temperature and a dielectric when below the defined temperature. The thermal switch can be operable to close an electrical circuit when the material layer is a conductor and open the electrical circuit when the material layer is the dielectric. |
| US09626848B2 |
Security device
There is described a security device for insertion into a container product for protection of the container product. The security device comprises a body portion moveable between a contracted configuration and an expanded configuration; and a locking mechanism operable to lock the body portion in the expanded configuration and operable to unlock the body portion from the expanded configuration; wherein, when the body portion is locked in the expanded configuration, the body portion has a length that cannot be reduced below a predefined length. |
| US09626847B2 |
Systems and methods for emergency egress and monitoring system
Various embodiments of the present technology may comprise a system disposed within a structure comprising a network of individually addressed devices, wherein each device comprises a microcontroller electrically connected to a communication module, an output module, and/or a sensor module. The sensor module may produce data of an environmental condition and may transmit a signal to the microcontroller based on the data. The microcontroller may receive and processes the signal from the sensor module to identify a detected event and selectively activates at least one of the output module and the sensor module based on the detected event. The selectively activated output module and sensor module may located within the same device as the microcontroller and/or any number of devices in the network. |
| US09626841B2 |
Occupant notification of visitor interaction with a doorbell at a smart-home
This patent specification relates to apparatus, systems, methods, and related computer program products for providing home security/smart home objectives. More particularly, this patent specification relates to a plurality of devices, including intelligent, multi-sensing, network-connected devices, that communicate with each other and/or with a central server or a cloud-computing system to provide any of a variety of useful home security/smart home objectives. |
| US09626838B2 |
Load balancing lottery system
The present invention relates to a lottery system for redirecting an online lottery client to impede crashing owing to increased traffic during a lottery jackpot. The system includes node servers including a first node server and a second node server. A broker server indicates to the first node server that the second node server is allocated to the client so that the first node server can redirect the client to the second node server to distribute traffic among node servers and impede crashing. |
| US09626835B2 |
System and method for providing a secondary contest dependent on the results of a primary game
Systems and methods for providing a secondary contest involving a plurality of players playing a primary award wagering game. The players enter wagers in the primary game, and the results from the primary wagering game determine the outcome of a secondary pari-mutuel contest in which players compete against each other. The results from the primary wagering game resolve the secondary contest where the highest ranking results will win the wagers placed in the secondary contest on a tiered basis. |
| US09626834B2 |
Method for displaying gaming result
Embodiments of the invention include a gaming device that has a video display. When the player initiates the game, an animation is shown. If the game had a losing outcome, the animation is very short and allows the player to quickly try for a win. If instead the game has a winning outcome the gaming device spins reels or otherwise shows the player how much he or she has won. The animation may also indicate progress toward a mystery jackpot or a group mystery jackpot. |
| US09626828B2 |
Gaming system and method providing a multiplayer card game with multiple fold options and interrelated bonuses
Various embodiments of the present disclosure are directed to a gaming system and method providing a multiplayer card game with multiple fold options and interrelated bonuses. In one embodiment, the gaming system enables a player to input either a first fold input or a second different fold input should the player desire to fold the player's hand during a play of the card game. If the gaming system receives the first fold input from the player, the gaming system: (a) folds the player's hand, (b) automatically removes the player from the virtual table, and (c) automatically assigns the player to a second different virtual table for at least one subsequent play of the card game. If, on the other hand, the gaming system receives the second fold input from the player, the gaming system folds the player's hand and does not remove the player from the virtual table. |
| US09626825B2 |
Game machine
A game machine has an operation lever device disposed on a front side of the game machine, having a lever having a grip section that is configured to be held by a game player and that rotates bi-directionally with respect to a shaft, a light guide plate disposed on the grip section of the lever in a viewable manner, a light source section that supplies light into the light guide plate. The grip section is formed into a long shape. The light guide plate has a viewable surface provided with a light emission pattern for forming an image by emitted light. |
| US09626824B2 |
Game result graphical verification on remote clients
Methods an apparatus are described for verifying a game of chance is displayed correctly on a remote client. The verification may include storing game history information associated with a game of chance presented at a remote client. The server can provide a game outcome associated with the game of chance, and the game outcome can be presented visually on the remote client. A sample game outcome can be generated on a remote client and a user may be asked one or more questions about the sample game outcome to verify that the sample game outcome is correctly displayed on the remote client. In addition, the remote client can then generate a hash of the 1 game outcome and send the hash to the server. The server can store the client-generated hash and game history. If a dispute arises, this client-generated hash can be compared to a server-generated hash. A comparison of these hashes can be used to verify that the correct outcome was displayed on the remote client. |
| US09626823B2 |
System and method of predicting future demand of a charging station
A system and method of predicting future demand of a charging station include collecting probe data from a plurality of electric vehicles. The probe data includes charging activity history of the plurality of electric vehicles. A usage pattern of a charging station is determined based on the probe data for the charging station. A future demand for the charging station is predicted by applying the usage pattern to a factor associated with a requesting electric vehicle. The predicted future demand for the charging station is provided to the requesting electric vehicle. |
| US09626822B2 |
Medicine supply device
A preparation task for medicine, which must be manually prepared in advance, is efficiently performed without error. A medicine supply device includes: a medicine supply means having a plurality of medicine receiving portions, the medicine supply means being configured to receive a medicine per a dosing time and appropriately discharge the received medicine; a display means including a plurality of display portions, the display portions being provided in association with the medicine receiving portions respectively; and a display control means configured to allow the display portion of the medicine receiving portion, which receives a corresponding medicine among the medicine receiving portions, to operate based on a prescription data. The display portion of the display means is configured to display a number corresponding to the dosing time of each medicine included in the prescription data. |
| US09626821B2 |
Electronic payment system
The specification and drawing figures describe and show a system for making a payment across a point-of-sale device that includes at least one a payment instrument having financial data required to conduct a financial transaction across a credit network. The system also includes a mobile wireless instrument having a data processor operatively connectable to the point-of-sale device and to the payment instrument. At least one algorithm is provided for transmitting the financial data from the payment instrument to the data processor of the mobile wireless instrument, and for decrypting an encryption key, as well as transmitting an instruction from the mobile wireless instrument to the point-of-sale device to authorize the payment. |
| US09626820B2 |
Card reader
A card reader may include a card insertion port; a card passage; and a disturbing magnetic field generator. The disturbing magnetic field generator may include a core part including a core formed and a disturbing magnetic field generation coil wound around the core. The core part may include a first end face and a second end face which are disposed so as to face substantially the front side. The disturbing magnetic field generator may generate a disturbing magnetic field whose flux line changes into a direction from the first end face toward the second end face and a direction from the second end face toward the first end face. The direction of the magnetic flux lines are substantially parallel to the passing direction of the card. In a width and thickness direction of the card, the magnetic flux line crosses a position where the magnetic stripe is passed. |
| US09626818B2 |
Failsafe operation for unmanned gatelines
Systems and techniques are presented for enabling fail-safe operation of an automatic pedestrian access control gate during a health and safety event. Gateline sensor data is received from at least one gateline sensor. The gateline sensor data indicates that an event concerning health and safety has occurred. An alert is generated in response to receiving the gateline sensor data. The alert is transmitted to a remote monitoring device that is remote from the access control gate. A determination is made that a preset amount of time has elapsed since transmitting the alert. A further determination is made that an acknowledgement of the alert has not been received. Based on determining that the preset amount of time has elapsed and determining that the acknowledgement has not been received, a predefined action is triggered. |
| US09626817B2 |
Apparatuses, systems, and methods for storing and dispensing medication proximate a patient
Provided herein are various apparatuses, systems, and methods for improving the efficiency of medication distribution within a healthcare facility. In particular, embodiments may provide for storing and dispensing medications to an authorized medical person for administration to a patient in a healthcare facility. A storage and dispensing system may include a housing defining a cavity, a door movable between an open and a closed position to provide access to the cavity, two or more receivers disposed within the cavity, a lock to lock the door in the closed position, and a user interface configured to receive a request for medications stored within the cavity. The medications may be configured to be presented to a user in response to a request for the medications, while unrequested medications remain inaccessible. |
| US09626816B2 |
Physical access request authorization
In a method for controlling physical access to a computing device a first access request to a room containing the computing device is received. In response, a processor determines that the first access request is valid based on the room and the date and time of the first access request and unlocks a door to the room to permit entry to the room. Subsequently, a second access request to a cabinet that is located in the room and contains the computing device is received. In response, a processor determines that the second access request is valid based on the cabinet and the date and time of the second access request and unlocks the cabinet to permit access to the computing device. |
| US09626814B2 |
Smart door lock
In some embodiments, systems, methods, and techniques relating to security and/or automation systems, collectively referred to as automation systems, may include determining a presence of a first device proximate at least one entry to a location, obtaining information related to an identification of an entity associated with the at least one device, authenticating the first device, the authenticating based at least in part on obtaining information related to the identification, and taking an action based at least in part on determining the authenticity. |
| US09626812B2 |
SCR aftertreatment system maintenance inducement method
Systems and methods are disclosed that relate to an SCR aftertreatment system and incentives/inducements for an operator/user to maintain the SCR aftertreatment in compliance with operating requirements and/or regulations. An engine is operationally coupled to at least one of a DEF tank and an SCR aftertreatment system. An inducement signal value is determined in response to a threshold value being obtained relating to at least one of the DEF tank level indication, a DEF quality indication, and an SCR aftertreatment system malfunction indication. The inducement signal value initiates at least one derate value of the engine to incentivize or induce the operator to have the aftertreatment system maintained and avoid or prevent out-of compliance operation of the SCR aftertreatment system. |
| US09626811B2 |
Vehicle fault early warning system
A vehicle fault early warning system is provided in which a central processing system (e.g., vehicle manufacturer, service center, third party) transmits a warning once a set of conditions is identified that routinely leads to a particular vehicle malfunction, where the malfunction may either cause the failure of a component/subsystem or cause a component/subsystem to perform out-of-spec. The warning may be accompanied by instructions as to how to avoid, or at least mitigate, the effects of the vehicle malfunction. |
| US09626808B2 |
Image-based deformation of simulated characters of varied topology
A graphical asset associated with a simulated character of a video game is received. A first image and a second image associated with the simulated character are subsequently received, the first image comprising graphical displacement mapping information for a first topology of image deformation and the second image comprising graphical displacement mapping information for a second topology of deformation. A portion of the graphical asset is then deformed using the graphical displacement mapping information from the first image and the second image to change the 3D geometry of the portion of the graphical asset. |
| US09626806B2 |
Image processing apparatus, image processing method, and program
An information processing system that acquires video data captured by an image pickup unit; detects an object from the video data; detects a condition corresponding to the image pickup unit; and controls a display to display content associated with the object at a position other than a detected position of the object based on the condition corresponding to the image pickup unit. |
| US09626804B2 |
Article information providing apparatus that provides information of article, article information providing system,and article information provision method
Provided is an article information providing apparatus that includes a display circuit, an imaging circuit, an object recognizing circuit, and an article discriminating circuit. The display circuit displays an article information image in which article information is shown. The imaging circuit images real space. The object recognizing circuit recognizes the object imaged by the imaging circuit. The article discriminating circuit discriminates the article from the object recognized by the object recognizing circuit and displays the article information image on the display circuit based on the state of the discriminated article. In addition, the article discriminating circuit displays the article information image on the display circuit when a dynamic state change of the discriminated article is identified. |
| US09626803B2 |
Method and apparatus for image processing in augmented reality systems
Disclosed are a system, apparatus, and method for depth and color camera image synchronization. Depth and color camera input images are received or otherwise obtained unsynchronized and without associated creation timestamps. An image of one type is compared with an image of a different type to determine a match for synchronization. Matches may be determined according to edge detection or depth coordinate detection. When a match is determined a synchronized pair is formed for processing within an augmented reality output. Optionally the synchronized pair may be transformed to improve the match between the image pair. |
| US09626797B2 |
Generating a consensus mesh from an input set of meshes
Techniques are disclosed for generating a consensus mesh to cover a received set of points. In one embodiment, a meshing application generates multiple meshes that cover the received point set by varying parameters of an interpolating meshing technique, such as the ball-pivoting technique, tangent-space Delaunay triangulation, and the like. Different values for the one or more parameters are used to generate each of the meshes. After generating the multiple meshes, the meshing application may sort triangles in the meshes based on the frequency in which the triangles appear in the meshes. The meshing application may then iteratively add next-best triangles which are also compatible with the current consensus mesh to the consensus mesh, with the next-best triangle being a most frequently occurring triangle which has not yet been added to the consensus mesh. Compatibility may be defined using various criteria, such as producing a manifold and orientable triangulation. |
| US09626794B2 |
Storage medium, information processing apparatus and calculation method
An information processing apparatus obtains an incident radiance at a shading point by obtaining a light emission radiance of a target light source expressed by a spherical Gaussian (SG expressed), approximating by a spherical Gaussian (SG approximating) a function indicating a spread of the target light source from a perspective of the shading point, and obtaining the product of these. Also, the apparatus SG approximates a bidirectional reflection distribution function (BRDF) at a shading point, and calculates the radiance at the shading point based on information indicating the viewpoint for which the shading point is to be rendered, an incident radiance at the shading point, and the SG approximated BRDF at the shading point. |
| US09626791B2 |
Method for representing a participating media in a scene and corresponding device
A method and device for rendering a participating media delimited by a bounding box and rendered from a viewpoint, the media being at a determined distance from the viewpoint according to a viewing direction. In order to represent the limits of the participating media, the method comprises for at least one point of the volume formed by the bounding box, estimating a set of directions having for origin the at least one point; for each direction, estimating a first intersection point, corresponding to the intersection between the direction and the participating media, for which the associated density value is greater than a first threshold value; and estimating third intersection points, corresponding to the intersections between the viewing direction and the participating media, from an item of information representative of distances separating the first intersection point from a second intersection point corresponding to the intersection between the direction and the bounding box for each direction of the at least one part of the set of estimated directions. |
| US09626789B2 |
Implicit texture map parameterization for GPU rendering
Embodiments are described for a method for processing textures for a mesh comprising quadrilateral polygons for real-time rendering of an object or model in a graphics processing unit (GPU), comprising associating an independent texture map with each face of the mesh to produce a plurality of face textures, packing the plurality of face textures into a single texture atlas, wherein the atlas is divided into a plurality of blocks based on a resolution of the face textures, adding a border to the texture map for each face comprising additional texels including at least border texels from an adjacent face texture map, and performing linear interpolation of a trilinear filtering operation on the face textures to resolve resolution discrepancies caused when crossing an edge of a polygon. |
| US09626788B2 |
Systems and methods for creating animations using human faces
Systems and methods in accordance with embodiments of the invention enable collaborative creation, transmission, sharing, non-linear exploration, and modification of animated video messages. One embodiment includes a video camera, a processor, a network interface, and storage containing an animated message application, and a 3D character model. In addition, the animated message application configures the processor to: capture a video sequence using the video camera; detect a human face within a sequence of video frames; track changes in human facial expression of a human face detected within a sequence of video frames; map tracked changes in human facial expression to motion data, where the motion data is generated to animate the 3D character model; apply motion data to animate the 3D character model; render an animation of the 3D character model into a file as encoded video; and transmit the encoded video to a remote device via the network interface. |
| US09626787B2 |
For node in render setup graph
Systems and methods for rendering three-dimensional images using a render setup graph are provided. A dependency graph is accessed. The dependency graph comprises a plurality of supplier nodes, a multiplexer node, and a plurality of graphlet nodes. The plurality of supplier nodes is accessed. The supplier nodes each have an output of a first type. These outputs are connected to the multiplexer node. A graphlet is accessed. The graphlet comprises the plurality of graphlet nodes. An output of the multiplexer node connects to the graphlet by connecting to an input of one node of the plurality of graphlet nodes. The multiplexer is configured to generate an instance of the graphlet for each supplier node connected to the multiplexer node. An image is rendered utilizing the accessed graphlet. |
| US09626780B1 |
Visualizing transactions of a transaction-based system
Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the transaction. For each line representing a transaction, the start end of the line is located at a first x-coordinate corresponding to a start time of the transaction and a first y-coordinate of zero. For each line, the terminating end of the line is located at a second x-coordinate corresponding to an end time of the transaction and a second non-zero y-coordinate that is the same for each line. Each line is displayed on the display device using the processor in combination with the x-y coordinate system. |
| US09626773B2 |
Augmented reality alteration detector
Technologies are generally described for systems and methods effective to detect an alteration in augmented reality. A processor may receive a real image that corresponds to a real object and may receive augmented reality instructions to generate a virtual object. The processor may determine that the virtual object at least partially obscures the real object when the virtual object is rendered on a display. The processor may, upon determining that the virtual object at least partially obscures the real object when the virtual object is rendered on the display, simulate an activity on the real object to produce a first activity simulation and simulate the activity on the virtual object to produce a second activity simulation. The processor may determine a difference between the first and the second activity simulation and modify the augmented reality instructions to generate a modified virtual object in response to the determination of the difference. |
| US09626772B2 |
Distinct encoding and decoding of stable information and transient/stochastic information
A method and a signal processor for receiving a data stream comprising at least two distinct sets of encoded data, at least one set of which is relative to transient/stochastic components of a signal. Based at least in part on the distinct sets of encoded data, the signal processor decodes and reconstructs a corresponding rendition of signal for each set of the encoded data. The distinct sets of renditions of signal are then combined into a single rendition of reconstructed signal. |
| US09626770B2 |
Generating synthetic video frames using optical flow
A novel method of using optical flow algorithm that maximizes the benefit of optical flow synthetic frames while minimizing the associated computation cost is provided. When using optical flow to produce synthetic frames between two actual/recorded frames, the method computes a set of estimates of optical flows (or a flow estimate) between the two frames. These flow estimates are then used to compute all synthetic frames that are needed between the two actual frames by interpolation, which creates each synthetic frame based on its temporal distances from the pair of actual frames. |
| US09626768B2 |
Optimizing a visual perspective of media
One or more signals are used to identify regions of interest of an image. The signals are applied to the image to generate one or more models that are based on the regions of interest. The models may present different perspectives of the image by emphasizing various features and focal points. The models may be ranked and displayed according to a scoring paradigm that is based on one or more signals. Multi-tiered feedback mechanisms allow for the collection of user intent and/or other forms of explicit input. Feedback associated to the models may be obtained and used to generate additional models that are based on one or more signals and the feedback. The feedback may also be stored and utilized for machine learning purposes. |
| US09626767B2 |
Surface normal information producing apparatus, image capturing apparatus, surface normal information producing method, and storage medium storing surface normal information producing program
The surface normal information producing apparatus acquires, as captured images of an object, multiple first images in which light source positions relative to the object are mutually different and three or more second images in which polarization states are mutually different, and performs area division of a surface of the object depending on at least one of luminance information that changes corresponding to the light source positions acquired from the first images and polarization information acquired from the second images. The apparatus selects, for each divided area obtained by the area division, information to be used in production of surface normal information from information relating to change of the luminance information corresponding to the light source positions and the polarization information to produce the surface normal information. |
| US09626766B2 |
Depth sensing using an RGB camera
A method of sensing depth using an RGB camera. In an example method, a color image of a scene is received from an RGB camera. The color image is applied to a trained machine learning component which uses features of the image elements to assign all or some of the image elements a depth value which represents the distance between the surface depicted by the image element and the RGB camera. In various examples, the machine learning component comprises one or more entangled geodesic random decision forests. |
| US09626763B1 |
Pothole detection
A system for pothole detection comprises an input interface configured to receive sensor data and a pothole detector configured to determine a pothole based at least in part on the sensor data; and store pothole data associated with the pothole, wherein the pothole data comprises a pothole video. |
| US09626760B2 |
System and method to align and merge differently exposed digital images to create a HDR (High Dynamic Range) image
The present invention provides a system and method to align and merge differently exposed digital images to create a HDR image. In the present system, all the modules starting from the receiving module to fusion module are configured to produce a HDR image with better color purity and sharpness. Each captured image in the system is configured to operate in the HSI color space. The alignment module is configured to align the pixels of each image in a pyramid shaped resolution structure to derive alignment vectors for one or more regional partitions of each image across one or more levels of the pyramid. The system is configured such that, the saturation component in the HSI color space is used to pick the color purity of pixels and intensity channel is used to weigh the sharpness of pixels of each of the differently exposed captured images. |
| US09626757B2 |
System and method for the validation and quality assurance of computerized contours of human anatomy
A system and method for validating the accuracy of delineated contours in computerized imaging using statistical data for generating assessment criterion that define acceptable tolerances for delineated contours, with the statistical data being conditionally updated and/or refined between individual processes for validating delineated contours to thereby adjust the tolerances defined by the assessment criterion in the stored statistical data, such that the stored statistical data is more closely representative of a target population. The present invention may be used to facilitate, as one example, on-line adaptive radiation therapy. |
| US09626756B2 |
Methods and systems for producing an implant
A computer implemented method for determining the 3-dimensional shape of an implant to be implanted into a subject includes obtaining a computer readable image including a defective portion and a non-defective portion of tissue in the subject, superimposing on the image a shape to span the defective portion, and determining the 3-dimensional shape of the implant based on the shape that spans the defective portion. |
| US09626748B2 |
Projector and method for controlling the same
A filter coefficient calculation portion detects a maximum and a minimum of a pixel-basis deformation factor representing the degree of deformation due to trapezoidal distortion and calculates filter coefficients corresponding to a plurality of deformation factors in accordance with the range of the deformation factors (minimum to maximum). The filter coefficients are corrected by multiplying the calculated filter coefficients by a luminance correction coefficient for correcting luminance deviation due to the trapezoidal distortion, and the corrected filter coefficients are stored in a filter coefficient storage portion. A deformation factor calculation portion calculates the deformation factor in a pixel to be processed by a filter operation portion, and the filter operation portion reads the filter coefficient corresponding to the deformation factor calculated by the deformation factor calculation portion from a filter coefficient storage portion. The filter operation portion then performs filtering. |
| US09626746B2 |
Image processing apparatus and image processing method
An image processing apparatus includes a gain calculation unit that calculates a gain for each of a plurality of pixels of an image signal, respectively, and an addition unit that adds the gain for each pixel to the corresponding pixel of the plurality of pixels of the image signal. The gain calculation unit includes a first order differential operation unit that calculates a first value from first order differential of the image signal for each of the plurality of pixels and second order differential operation unit that calculates a second value from a second order differential of the image signal for each of the plurality of pixels, and calculates the gains for each pixel based on the first and second values for each pixel. |
| US09626744B2 |
Global approximation to spatially varying tone mapping operators
Techniques to generate global tone-mapping operators (G-TMOs) that, when applied to high dynamic range images, visually approximate the use of spatially varying tone-mapping operators (SV-TMOs) are described. The disclosed G-TMOs provide substantially the same visual benefits as SV-TMOs but do not suffer from spatial artifacts such as halos and are, in addition, computationally efficient compared to SV-TMOs. In general, G-TMOs may be identified based on application of a SV-TMO to a down-sampled version of a full-resolution input image (e.g., a thumbnail). An optimized mapping between the SV-TMO's input and output constitutes the G-TMO. It has been unexpectedly discovered that when optimized (e.g., to minimize the error between the SV-TMO's input and output), G-TMOs so generated provide an excellent visual approximation to the SV-TMO (as applied to the full-resolution image). |
| US09626739B2 |
Inferring diagram structure through implicit shape relationships
Information in a diagram is logically structured using lists, containers, and callouts without requiring the diagram author to explicitly define a structure or map any diagram contents to a structure. Logical relationships are inferred based on actions associated with shapes, groupings, and attributes of shapes/groupings taken by the author. Feedback mechanisms are provided to communicate an underlying structure to the author. Intelligent behaviors are enabled to expose manipulation of diagrams based on their logical structure. |
| US09626738B2 |
Image processing apparatus, image processing method, and storage medium
An image processing apparatus includes a detection unit that detects segments from a first image; a selection unit that selects pairs of segments formed of a predetermined number of segments counted from a higher priority in an order of length among the detected segments and segments in a second image, the second image being a model of the first image; and a calculation unit that calculates distortion of the first image with respect to the second image by using the pairs of segments. |
| US09626726B2 |
Location based social networking system and method
A method, computer program product, and computer system for receiving, at a first computing device, location information of a second computing device and one or more computing devices. The location information is received in response to an action performed with at least one of the first computing device and the one or more computing devices. At the first computing device, the one or more computing devices that are within a pre-defined distance from the second computing device are identified based upon, at least in part, the location information. At least a portion of automatically-suggested user information associated with the one or more computing devices within the pre-defined distance from the second computing device is sent from the first computing device to the second computing device. |
| US09626721B2 |
Wireless beacon connections for providing digital letters of credit on detection of a user at a location
There are provided systems and methods for wireless beacon connections for providing digital letters of credit on detection of a user at a location. A payment provider may authorize use of one or more wireless beacons at a merchant location. |
| US09626720B2 |
Linked user accounts
Separate user accounts can be linked into a group of linked user accounts so that content items assigned to each of the user accounts can be accessed by each user account in the group. Linking user accounts in this way allows the individual user accounts to share content items while also retaining their individual properties such as username, password, preference data, etc. Linking user accounts allows each user account to retain the content items assigned to the user account when the user account is unlinked from the group. Linking user accounts can be restricted according to linking rules that dictate how many user accounts can be included in a group, when a user account can be added or removed from a group, etc. A master user account can set parameters restricting content items accessible to the user accounts in the group, as well as money spent be each user account. |
| US09626718B2 |
Lead marketplace system and method with lead auctions
A lead marketplace system and method are provided. The lead marketplace system and method provides an auction for leads. |
| US09626713B2 |
Method for rapid development of schedule controled networkable merchant ecommerce sites
An improved computerized ecommerce method, optimized for smaller merchants such as florists who often provide seasonal perishable gifts that require local delivery, and who often desire to form cooperative networks with local merchants offering related gift services, as well as other related merchants such as other florists in more distant locations. The web server based method allows merchants to easily set up non-static (time variable) websites that automatically provide schedule driven promotions. New products can be quickly uploaded from smartphones, and sophisticated time and location aware algorithms can compute accurate delivery costs and make such costs transparent to customers. Other participating merchants can be easily added to the system to form local and distant cooperative merchant networks. The system simplifies customer use of promotional offers by cross checking customer URL versus promotion lists. Recipient gift appreciation is optimized by providing interfaces to allow customer designed gift cards and messages. |
| US09626711B2 |
Systems and methods for providing product recommendations incorporating secondary sources of information
A system and method provides product/service recommendations by rendering and analyzing content on webpages that are linked to on a user's personal webpage. In this manner, the system and method compiles a more complete view of the user's interest and preferences, thus providing more effective and finely-attuned user recommendations. |
| US09626710B1 |
Best practice analysis, optimized resource use
Embodiments of the present disclosure are directed to, among other things, providing resource allocation advice, configuration recommendations, and/or migration advice regarding data storage, access, placement, and/or related web services. In some examples, a web service may utilize or otherwise control a client instance to control, access, or otherwise manage resources of a distributed system. Based at least in part on one or more resource usage checks and/or configuration checks, resource usage information and/or configuration information of an account utilizing a web service, and/or user preferences and/or settings, resource allocation advice, system configuration recommendations, and/or migration advice may be provided to a user of an account. Additionally, in some examples, one or more remediation operations may be performed automatically. |
| US09626701B2 |
System and method for facilitating cash payment transactions using a mobile device
Disclosed herein are systems and methods for facilitating transactions between a merchant-partner and an end-user. In one embodiment, a service provider: (a) stages a transaction between a merchant and a consumer; (b) creates a transaction-specific unique reference locator (URL) linked to a transaction-specific web page; and (c) sends the transaction-specific URL to the consumer's mobile device. Whereupon the consumer clicks on the transaction specific URL on their mobile device, the service provider displays a token ID on the transaction-specific web page. The token ID is linked to the staged transaction and is used to initiate data communication between a point-of-sale (POS) terminal and the service provider's processing unit. The service provider can then: receive confirmation that the consumer has presented the token ID and a payment to the POS terminal; display a transaction receipt on the transaction-specific web page; and/or notify the merchant that the consumer has provided the payment. |
| US09626694B2 |
Methods, computer program products, and apparatus for receiving targeted content based on locally stored user data
Targeted content is delivered to and received by at least one user device based on user information stored locally at the user device. Program content and targeted content are received. The targeted content received is associated with user information stored locally on the user device, while the program content is broadcast to multiple users. A determination by a scanning process is made at what position or at what time in the program content to include the targeted content. The program content and the targeted content are rendered, with the targeted content included at the determined position or time in the program content, for presentation to the user. |
| US09626691B2 |
Determining a bid modifier value to maximize a return on investment in a hybrid campaign
Systems and methods for determining a bid modifier value include determining, for one or more sets of keywords used in a campaign, a predicted conversion rate for a first device type and a predicted conversion rate for a second device type. Predicted campaign-level conversion rates are determined for the first and second device types using the predicted conversion rates for the one or more sets of keywords used in the campaign. A ratio is also determined between the predicted campaign-level conversion rate for the first device type and the predicted campaign-level conversion rate for the second device type. The ratio may be used as a bid modifier value that relates bids for the first device type to bids for the second device type. |
| US09626688B2 |
Method and system for facilitating access to a promotional offer
A method of facilitating access to a promotional offer, the method comprising: receiving at a server system a page request from a client device; and sending program code executable in a browser application to the client device in response to the page request, the program code being executable to display at least one promotional offer and a promotional code, to provide a flash object at a display position of the promotional code and, in response to selection of the flash object, to cause the promotional code to be copied to a user-accessible memory of the client device and to open a new browser display of the browser application. |
| US09626686B2 |
Selecting sporting events based on event status
Accessing one or more sets of sporting event data, each of which being associated with a particular one of one or more sporting events, and each of which comprising one or more sporting event data that indicate at least current event status of the associated sporting event at a current time. For each of the sporting events, calculating a value by applying the set of sporting event data associated with the sporting event to one or more algorithms, each of which having been determined for a particular sport to which the sporting event is categorized, comparing the value to a threshold requirement, and if the value satisfies the threshold requirement, then displaying the sporting event data associated with the sporting event. |
| US09626682B2 |
Systems and methods for reseller discovery and analysis
Methods and systems relating to a reseller analysis tool are described. In some embodiments, electronic commerce transaction information associated with a plurality of electronic commerce transactions occurring using an electronic commerce system is received at the electronic commerce system. A set of resale transactions from the plurality of electronic commerce transactions is identified using the electronic commerce transaction information, including identifying the set of resale transactions based on resale criteria capable of indicating a sale of an item by an entity that previously purchased the item using the electronic commerce transaction system. A set of rules associated with resale transactions is generated, including generating the set of rules based on the electronic commerce transaction information associated with the set of resale transactions. Based on the set of rules, user transaction information relevant to a transaction associated with a user is provided. |
| US09626677B2 |
Identification of computerized bots, and identification of automated cyber-attack modules
Devices, systems, and methods of detecting whether an electronic device or computerized device or computer, is being controlled by a legitimate human user, or by an automated cyber-attack unit or malware or automatic script. The system monitors interactions performed via one or more input units of the electronic device. The system searches for abnormal input-user interactions; or for an abnormal discrepancy between: the input-unit gestures that were actually registered by the input unit, and the content that the electronic device reports as allegedly entered via such input units. A discrepancy or abnormality indicates that more-possibly a malware or automated script is controlling the electronic device, rather than a legitimate human user. Optionally, an input-output aberration or interference is injected, in order to check for manual corrective actions that only a human user, and not an automated script, is able to perform. |
| US09626674B1 |
System and method for exchanging, sharing and redeeming credits
An independently verifiable system and method for the exchange of a sequence of tokens corresponding to units of currency. A credit or unit of currency is represented by a digital image referred to as a graphical token which may be displayed on an electronic viewing device or printed on paper. Each token contains a digital code that uniquely identifies the previous graphical token in a series of exchanges. After generating a token, a first user provides that token to a second user in order to initiate an exchange. The second user may choose to verify the validity and currency of the token before accepting the token. Either user may choose to register the token and any parameters associated with the exchange with a registry system. Once a user accepts a token, they may choose to issue a new token in the sequence. They may also choose to redeem the token for the credit associated with a sequence of tokens. |
| US09626673B2 |
Financial transaction based on device-to-device communications
The systems, devices and techniques disclosed provide a credit card type device which is integrated with active electronics to perform credit card type financial transactions. In one aspect, a credit card type device includes a device-to-device communication port to wirelessly communicate with another device in an attempt to complete a financial transaction. The credit card type device includes an authentication mechanism to authenticate access to the credit card type device for the initiated financial transaction. The credit card type device includes controller circuitry to control operations of the device-to-device communication port and the authentication mechanism. The credit card type device includes an output device to display information associated with the access authentication and the financial transaction. |
| US09626672B2 |
Using harvested power for NFC transactions
In some embodiments, a system includes a mobile communication device and a secure element physically coupled to the mobile communication device. The mobile communication device includes a first wireless transceiver, first processor, and first memory. The secure element includes a second wireless transceiver, second processor, and second memory. The mobile communication device is configured to transmit data via the first wireless transceiver to the secure element in packets, using a packet protocol. The secure element is configured to transmit data via the second wireless transceiver to the mobile communication device in messages, using a messaging protocol distinct from the packet protocol. |
| US09626666B2 |
Dual validator self-service kiosk
Apparatus and methods are provided for a dual validator self-service kiosk (“SSK”). The SSK may include a first validator. The first validator may examine a deposit inserted into the SSK. The SSK may include a second validator. The second validator may examine a tangible item before the SSK dispenses the tangible item. The SSK may retract the tangible item if the tangible item in not collected by a customer. The second validator may examine the tangible item after being retracted by the SSK. The first validator may apply a first examination routine to the deposit. The second validator may apply a second examination routine before the SSK dispenses the tangible item. The second validator may apply a third examination routine to a tangible item retracted by the SSK. |
| US09626665B2 |
Retail send transaction system
A system and method for performing transactions uses a plurality of tokens for retail sale, each token representing a send transaction. A computer system is connectable to receive data representing a send transaction identifier of at least one token and the computer system presents to the sender a completion interface that includes fields for receiving send transaction information comprising sender identification information, recipient identification information and options related to the transfer. In response to receipt of sufficient information entered at the completion interface, a memory stores an active, funded send transaction record in the computer system including the options. |
| US09626663B2 |
System and method for collecting and distributing digital receipts
According to certain embodiments of the present invention, a method for coordinating the provision of a digital receipt associated with a financial transaction is provided. According to the method, a digital receipt and an identifier corresponding to the digital receipt are communicated from an acquirer and received at a digital receipt server. The digital receipt and the corresponding identifier may be communicated through a second network, such as the Internet. The digital receipt and the identifier corresponding to the digital receipt are then stored in the digital receipt server. The digital receipt server also receives an inquiry and an identifier corresponding to the inquiry, which are communicated from an issuer. The inquiry and the corresponding identifier may be communicated through the second network. Prior to this, the identifier is transmitted from the acquirer to the issuer, for example, through a first network such as an electronic funds transfer (“EFT”) network. |
| US09626659B2 |
Conflict management in scheduling meetings
A floating meeting is set up such that the actual meeting time is not fixed until after pre-defined parameters are satisfied. One parameter is a point in time nearer to the proposed meeting date(s) than the time of the original meeting invitation. At the later point in time, subsequent and potentially conflicting meetings are automatically avoided to maximize invitee availability or otherwise meet a meeting organizer's objective. |
| US09626653B2 |
Document distribution and interaction with delegation of signature authority
Improved workflows allow delegation of authority to electronically sign a document according to a delegation rule. The delegation rule specifies a document criterion and a delegate who is authorized to sign documents meeting the criterion. The criterion may be based on subject matter, document originator, or receipt time. Delegation rules can also be invoked in response to specified conditions or events, such as receipt of an automated out-of-office notification, or failure to receive any response to a signature request within a certain time. When an electronic signature system processes a document meeting the specified criterion, or detects one of the specified conditions or events, the document is sent to the delegate for signature instead of the originally intended signatory. The workflow initiator and delegator are optionally notified of such delegation before the document is sent to the delegate, thus giving him/her a degree of control over the delegation. |
| US09626652B2 |
System comprising providing means for providing data to a user
The invention relates to a system comprising providing means for providing data, electing means for electing one or more parameters associated to said data, assessment means for assessing at least one characteristic of at least one of said elected parameter, and a lighting system for office rooms which comprises one or more light sources, the lighting system being capable of emitting light of different characteristic to the office room. The system is configured such that the characteristic of the light emitted to the office room is changed depending on the characteristic of the elected parameter. |
| US09626648B2 |
Recommending contacts in a social network
A method and system for recommending potential contacts to a target user is provided. A recommendation system identifies users who are related to the target user through no more than a maximum degree of separation. The recommendation system identifies the users by starting with the contacts of the target user and identifying users who are contacts of the target user's contacts, contacts of those contacts, and so on. The recommendation system then ranks the identified users, who are potential contacts for the target user, based on a likelihood that the target user will want to have a direct relationship with the identified users. The recommendation system then presents to the target user a ranking of the users who have not been filtered out. |
| US09626647B2 |
Providing a contact service
An embodiment relates generally to a method of providing a service. The method includes receiving a request to determine a status of a user and determining an on-line status of the user. The method also includes providing a geographic proximity of the user in response to the on-line status of the user being on-line. |
| US09626644B2 |
Method and apparatus for monitoring the status and transfer of food products
A system and method is provided for monitoring a status of a plurality of products, such as prepared food, located in product locations within stations throughout a restaurant. The status of each product indicates whether that product exists in a particular storage location, and whether that product has exceeded its shelf life or hold time. The storage time which has elapsed for each product is automatically counted and compared to the hold time. A cook time, which is that duration of time required to cook a particular product, is also maintained for each of the products. The status indicates when additional product should be cooked in order to have new product prior to the expiration of existing product by indicating when the hold time less the cook time has elapsed. The status also indicates which product is the oldest to facilitate the transfer and use of the oldest product first. A transfer of one product to another product location automatically transfers the corresponding elapsed storage time with that product. |
| US09626637B2 |
Method and system for managing business deals
In accordance with embodiments, there are provided mechanisms and methods for managing business deals. The mechanisms and methods for managing business deals may enable embodiments to provide a dynamic and interactive user-interface including any combination of contacts, accounts, opportunities, allowing users to create tasks, events, leads (e.g., from Data.com), reports, dashboards, instant messenger, external deal spaces, email service (e.g., Outlook), a cloud-based productivity suite for businesses that allows work on any device (e.g., Google apps), mobile access, private messaging, lead management, mass email templates, social media monitoring (e.g., from Radian6), role-based sharing and security, and/or additional storage, for example. In an embodiment, the number of contacts may be unlimited. |
| US09626633B2 |
Providing access to one or more messages in response to detecting one or more patterns of usage of one or more non-communication productivity applications
A computationally implemented method includes, but is not limited to: detecting one or more occurrences of one or more specific patterns of usage of one or more non-communication (NC) productivity applications by one or more end users; and providing to the one or more end users, in response to said detecting, access to one or more particular messages through one or more channels of one or more NC productivity application interfaces, the one or more NC productivity application interfaces for accessing the one or more NC productivity applications by the one or more end users. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. |
| US09626632B2 |
Apparatus, system, and method for logically packaging and delivering a service offering
An apparatus, system, and method are disclosed for logically packaging and delivering a service offering. A set of service implementation artifacts, a service ordering process, and a service provisioning process are selected and configured to implement a service offering. A requirements specification for the set of service implementation artifacts is defined. Logical associations between parameters are defined such that a change of a parameter for a first component triggers a change for a parameter of a second component. Beneficially, such an apparatus, system, and method accelerates the self-service ordering and deployment of service offerings. |
| US09626629B2 |
Categorization of user interactions into predefined hierarchical categories
User interactions are categorized into predefined hierarchical categories by classifying user interactions, such as queries, during a user interaction session by labeling text data into predefined hierarchical categories, and building a scoring model. The scoring model is then executed on untagged user interaction data to classify the user interactions into either action-based or information-based interactions. |
| US09626613B2 |
System and method for computed radiography using near field communication technology
A system and method for obtaining an intra-oral X-ray image of a patient. The system includes an information carrier plate having an affixed NFC/RFID tag. The NFC/RFID tag includes a memory. A primary tagging device reads and writes temporary information into the tag's memory over a first communication channel. A scanner is in communication with a secondary tagging device to read and write the temporary information saved in the tag's memory over a second communication channel. |
| US09626609B1 |
Asset creation from hardware asset tags using a mobile device
Various of the disclosed embodiments concern computer systems, methods, and programs for extracting information from an asset tag that can be used to monitor the corresponding asset. An operator, e.g. employee of an enterprise, logs into an application executed by a mobile device that includes a camera. A tag template can then be manually selected by the operator or automatically selected by the application. The tag template is used during scanning to locate and identify machine-readable elements, human-readable elements, structural elements, or some combination thereof. Once the application registers a successful scan of the asset tag, the operator can review and confirm the information was extracted correctly. Generally, the extracted information is transmitted to an asset management system, which creates a database entry that allows the asset to be continually monitored by the enterprise, e.g. each time the asset tag is subsequently scanned. |
| US09626608B2 |
Additive manufactured serialization
Methods for forming an identifying mark in a structure are described. The method is used in conjunction with an additive manufacturing method and includes the alteration of a process parameter during the manufacturing process. The method can form in a unique identifying mark within or on the surface of a structure that is virtually impossible to be replicated. Methods can provide a high level of confidence that the identifying mark will remain unaltered on the formed structure. |
| US09626606B2 |
Data generating apparatus, data generating method, and non-transitory storage medium
The numbers of pages making up respective records are acquired as individual page counts by analyzing page description data used for variable data printing. The maximum page count among the acquired individual page counts is determined as a common page count. Imposition data representing a common and single page layout made up of the determined common page count are generated. |
| US09626604B2 |
Method for dynamic printing process calibration
A method for the dynamic printing process calibration of a printing press includes determining a calibration dataset for the colored halftones of the process colors, determining a calibration dataset for the gray halftones of the process colors, determining a weighting factor for the two calibration datasets as a function of the original print and calculating a combined calibration dataset from the two determined calibration datasets, with reference to the weighting factor. The calculated combined calibration dataset is applied to the calibration of the printing process of a printing press. |
| US09626603B2 |
Method and system for utilizing transformation matrices to process rasterized image data
A method and system render rasterized data by receiving non-rasterized page description language data and a corresponding transformation matrix representing transformation operations to be performed. The non-rasterized page description language data is rasterizing to create rasterized data. The corresponding transformation matrix is decomposed into a plurality of individual transformation operation matrices and a discrete transformation operation value, from each corresponding individual transformation operation matrix, is generated for each transformation operation to be performed upon the rasterized data. The transformation operations are performed upon the rasterized data based upon the generated discrete transformation operation values. |
| US09626596B1 |
Image variation engine
Various features described herein may include ways of processing multiple images to determine whether any duplicates are among the multiple images. A hashing algorithm may be used to create a hash key of an image. Multiple hash keys corresponding to multiple images may be compared to determine whether those images are duplicate images. A root mean square algorithm may be used to further identify whether multiple images are duplicate images. An image variation engine, which uses intensity coding, may be used to display differences between images. For example, similar areas in images may be drawn with low intensity or high opacity, while different areas in images may be drawn with high intensity or low opacity. |
| US09626593B2 |
System and method for conflating road datasets
In one aspect, a computer-implemented method for conflating a base dataset with a secondary dataset may generally include defining a locker boundary around each of a plurality of base polylines of the base dataset and identifying a plurality of initial matched segments and a plurality of initial mismatched segments for a plurality of secondary polylines of the secondary dataset, wherein each portion of the secondary polylines that is included within a locker boundary is defined as an initial matched segment and each portion of the secondary polylines that is not included within a locker boundary is defined as an initial mismatched segment. The method may also include identifying an offset parameter defined between a first initial matched segment and its corresponding base polyline using a three-vertex approximation and, if the offset parameter exceeds a predetermined offset threshold, defining the first initial matched segment as a mismatched segment. |
| US09626592B2 |
Photographing method, photo management method and device
A photographing method that includes: acquiring to-be-photographed first content; after determining a first subject with which a user is concerned in the first content, acquiring an image composition relationship between a second subject in the first content and the first subject, where the second subject is another background subject in the first content except the first subject; matching the image composition relationship between the second subject and the first subject with a preset image composition template to obtain a matching evaluation degree, and providing an image composition adjustment suggestion on the first content for the user according to the matching evaluation degree and the image composition template, where the adjustment suggestion is a tip on how to adjust the image composition relationship in the first content so that the image composition relationship completely matches the preset image composition template. |
| US09626591B2 |
Enhanced contrast for object detection and characterization by optical imaging
Enhanced contrast between an object of interest and background surfaces visible in an image is provided using controlled lighting directed at the object. Exploiting the falloff of light intensity with distance, a light source (or multiple light sources), such as an infrared light source, can be positioned near one or more cameras to shine light onto the object while the camera(s) capture images. The captured images can be analyzed to distinguish object pixels from background pixels. |
| US09626589B1 |
Preview image acquisition user interface for linear panoramic image stitching
A system and method that allows the capture of a series of images to create a single linear panoramic image is disclosed. The method includes capturing an image, dynamically comparing a previously captured image with a preview image on a display of a capture device until a predetermined overlap threshold is satisfied, generating a user interface to provide feedback on the display of the capture device to guide a movement of the capture device, and capturing the preview image with enough overlap with the previously captured image with little to no tilt for creating a linear panorama. |
| US09626585B2 |
Composition modeling for photo retrieval through geometric image segmentation
A composition model is developed based on the image segmentation and the vanishing point of the scene. By integrating both photometric and geometric cues, better segmentation is provided. These cues are directly used to detect the dominant vanishing point in an image without extracting any line segments. Based on the composition model, a novel image retrieval system is developed which can retrieve images with similar compositions as the query image from a collection of images and provide feedback to photographers. |
| US09626583B2 |
Automated epithelial nuclei segmentation for computational disease detection algorithms
In aspects, the subject innovation can comprise systems and methods capable of automatically labeling cell nuclei (e.g., epithelial nuclei) in tissue images containing multiple cell types. The enhancements to standard nuclei segmentation algorithms of the subject innovation can enable cell type specific analysis of nuclei, which has recently been shown to reveal novel disease biomarkers and improve diagnostic accuracy of computational disease classification models. |
| US09626582B2 |
System and method for measuring mobile document image quality
A system and method for detecting the quality of a captured digital image depicting a hardcopy document are disclosed. The captured digital image is analyzed to determine a corresponding blurriness, noise, hotspot, and uneven illumination metric representing a quality level of the image data. The blurriness, noise, hotspot, and uneven illumination metrics are then combined to formulate a pass/caution/fail indicator for the user to respond to the captured digital image quality. |
| US09626574B2 |
Biometric notification system
A biometric notification system compares images or indicia of images and where there is a match provides a notification of the same. |
| US09626573B2 |
Traffic lane marking recognition apparatus and traffic lane marking recognition program
A traffic lane marking recognition apparatus includes a candidate detecting unit, a gap detecting unit, and a recognition reducing unit. The candidate detecting unit detects a lane dividing line candidate which is a candidate for a lane dividing line that defines a traffic lane on a road, based on an image of the road captured by an on-board camera that is mounted in a vehicle. The gap detecting unit detects a gap included in the lane dividing line candidate detected by the candidate detecting unit. When the gap is detected by the gap detecting unit, the recognition reducing unit reduces a probability of recognition of the lane dividing line candidate as a lane dividing line to a first probability that is lower than the probability when the gap detecting unit does not detect the gap, in a region from the gap closest to the vehicle towards a direction away from the vehicle. |
| US09626572B2 |
Apparatus for detecting boundary line of vehicle lane and method thereof
In vehicle-lane boundary line detection, low-luminance values are acquired from areas corresponding to below a tire and directly below a vehicle center based on a road surface image. A snow rut degree is calculated based on a luminance ration between the areas. A probability is calculated from a map based on the calculated snow rut degree. A parameter indicating the degree of snow rut likeness is calculated by a low-pass filtering process. A snow rut determination is made by the calculation result being compared with a predetermined threshold. A final determination of whether or not a snow rut is present is made, with reference to an outside temperature. When determined that a snow rut is present, a determination is made not to perform the detection. When determined that a snow rut is not present, a determination is made to perform the detection. |
| US09626570B2 |
Vehicle control system and image sensor
A vehicle control system includes a light-receiving section which has a plurality of filters having different pass bands, and a plurality of light-receiving elements, each of which receives incident light via any one of the filters; an image data generation section which, when receiving general image data which is an output of the light-receiving section, extracts outputs of the light-receiving elements correlated to the filters to generate discrete image data, which is image data for each of the filters; an image data processing section which detects at least one object, based on the discrete image data generated by the image data generation section or composite image data generated by combining the discrete image data; and a vehicle control section which performs vehicle control, according to the object detected by the image data processing section. |
| US09626564B2 |
System for enabling eye contact in electronic images
Techniques are disclosed for improving perceived eye-contact in video communications on personal communication devices that have a camera positioned offset slightly away from a display screen, such as found in tablets, mobile phones, laptops, desktops ultrabooks, all-in-ones, and the like. A three-dimensional mesh, such as a point cloud, may be created from an image and depth information that is captured of the user. A viewing direction of is determined by assessing the three-dimensional mesh and the mesh is rotated to minimize the angle between the viewing direction and a line of sight between the user's eyes and the camera. |
| US09626563B2 |
Mobile identity platform
The present disclosure is directed towards a compact, mobile apparatus for iris image acquisition, adapted to address effects of ocular dominance in the subject and to guide positioning of the subject's iris for the image acquisition. The apparatus may include a sensor for acquiring an iris image from a subject. A compact mirror may be oriented relative to a dominant eye of the subject, and sized to present an image of a single iris to the subject when the apparatus is positioned at a suitable distance for image acquisition. The mirror may assist the subject in positioning the iris for iris image acquisition. The mirror may be positioned between the sensor and the iris during iris image acquisition, and transmit a portion of light reflected off the iris to the sensor. |
| US09626562B2 |
Compact biometric acquisition system and method
A method of determining the identity of a subject while the subject is walking or being transported in an essentially straight direction is disclosed, the two dimensional profile of the subject walking or being transported along forming a three dimensional swept volume, without requiring the subject to change direction to avoid any part of the system, comprising acquiring data related to one or more biometrics of the subject with the camera(s), processing the acquired biometrics data, and determining if the acquired biometric data match corresponding biometric data stored in the system, positioning camera(s) and strobed or scanned infrared illuminator(s) above, next to, or below the swept volume. A system for carrying out the method is also disclosed. |
| US09626560B2 |
Method and apparatus for compressed sensing
Method and apparatus for compressed sensing yields acceptable quality reconstructions of an object from reduced numbers of measurements. A component x of a signal or image is represented as a vector having m entries. Measurements y, comprising a vector with n entries, where n is less than m, are made. An approximate reconstruction of the m-vector x is made from y. Special measurement matrices allow measurements y=Ax+z, where y is the measured m-vector, x the desired n-vector and z an m-vector representing noise. “A” is an n by m matrix, i.e. an array with fewer rows than columns. “A” enables delivery of an approximate reconstruction, x#, of x. An embodiment discloses approximate reconstruction of x from the reduced-dimensionality measurement y. Given y, and the matrix A, approximate reconstruction x# of x is possible. This embodiment is driven by the goal of promoting the approximate sparsity of x#. |
| US09626558B2 |
Environmental reproduction system for representing an environment using one or more environmental sensors
A environmental reproduction system multiplexes information from a variety of sources to reproduce a target environment having visual and/or auditory impediments. The visual impediments may include one or more environmental conditions, such as rain, sleet, snow, darkness, brightness, or any other type of environmental condition. The auditory impediments may include loud noises, such as construction noises, or sounds that are too low, such as an emergency vehicle sound not being heard. The environmental reproduction system may determine the environmental condition from one or more sources, such as an internal microphone, an external microphone, temperature sensor, a camera, a weather receiver, or other types of sensors. The environmental reproduction may be in communication with an environmental condition database and operative to apply a signal processing action to a recording (video and/or audio recording) of the target environment based on the determined environmental condition. |
| US09626557B2 |
Detection of the presence of an item using reflection characteristics
The present invention provides an apparatus for detecting presence or otherwise of an item comprising at least two regions having different optical characteristics, said apparatus comprising: an emitter operative to illuminate a measuring region of said apparatus with electromagnetic radiation; and a detector located and operative to receive electromagnetic radiation reflected from said measuring region of said apparatus and operative to output a signal corresponding to a measured characteristic of said electromagnetic radiation reflected from said measuring region, wherein said apparatus is operative to compare said measured characteristic with a set of pre-defined characteristics, and further wherein if said measured characteristic is consistent with at least one of said pre-defined characteristics, the apparatus is operative to output a signal indicative of presence or otherwise of one of said at least two regions of said item in said measuring region.Also provided is a method for detecting presence or otherwise of an item comprising at least two portions having different optical characteristics, and a banknote counting apparatus comprising the detection apparatus and operative to implement the method. |
| US09626556B2 |
Client side filtering of card OCR images
The technology of the present disclosure includes computer-implemented methods, computer program products, and systems to filter images before transmitting to a system for optical character recognition (“OCR”). A user computing device obtains a first image of the card from the digital scan of a physical card and analyzes features of the first image, the analysis being sufficient to determine if the first image is likely to be usable by an OCR algorithm. If the user computing device determines that the first image is likely to be usable, then the first image is transmitted to an OCR system associated with the OCR algorithm. Upon a determination that the first image is unlikely to be usable, a second image of the card from the digital scan of the physical card is analyzed. The optical character recognition system performs an optical character recognition algorithm on the filtered card. |
| US09626555B2 |
Content-based document image classification
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for classifying one or more document images based on its content by determining blocks layout of the document image; recognizing the document image to obtain digital content data representing text content or the potential graphical content of the image; calculating feature values of the document image for features based on the digital content data and the blocks layout; and classifying the document image as belonging to one of document classes based on the calculated feature values. |
| US09626554B2 |
Motion capture system that combines sensors with different measurement ranges
Motion capture system with a motion capture element that uses two or more sensors to measure a single physical quantity, for example to obtain both wide measurement range and high measurement precision. For example, a system may combine a low-range, high precision accelerometer having a range of −24 g to +24 g with a high-range accelerometer having a range of −400 g to +400 g. Data from the multiple sensors is transmitted to a computer that combines the individual sensor estimates into a single estimate for the physical quantity. Various methods may be used to combine individual estimates into a combined estimate, including for example weighting individual estimates by the inverse of the measurement variance of each sensor. Data may be extrapolated beyond the measurement range of a low-range sensor, using polynomial curves for example, and combined with data from a high-range sensor to form a combined estimate. |
| US09626544B2 |
Removable module for mobile communication terminal
A decodable indicia reading system can comprise a mobile communication terminal and a removable module. The mobile communication terminal can comprise a microprocessor, a memory, and an imaging device comprising a two-dimensional image sensor, all disposed within a housing. The removable module can comprise a housing at least partially containing an encoded information reading (EIR) device, an illumination module, and/or an optical system configured to focus the light reflected by a physical object located within a field of view of the two-dimensional image sensor onto the two-dimensional image sensor. The decodable indicia reading system can further comprise a decoding program executable by the microprocessor, which can be configured to input an encoded information item the imaging device and/or the EIR device. The removable module can be mechanically attached to the mobile communication terminal. The removable module can further comprise a memory configured to store a secret string. The decoding program can be further configured to output a decoded message by decoding the encoded information item responsive to validating the secret string and/or decrypting, using the secret string, at least one data item stored in the memory. |
| US09626541B2 |
Methods, system and apparatus for conducting a point of sale transaction
A method, system, and apparatus to scan visual codes are described. An image of a first visual code marked on an item is captured and the image of the first visual code is displayed on an electronic screen of the apparatus for a point-of-sale terminal that is enabled to scan the image of the first visual code. A scan signal emitted by the point-of-sale terminal is detected, the scan signal indicating that the image of the first visual code was scanned. A second image of a second visual code is displayed on the electronic screen of the apparatus. |
| US09626540B1 |
Secure wire marking for identification and authentication
Secure wire marking for identification and authentication is disclosed herein. An example apparatus includes a first strand that is electrically conductive, the first strand being embedded with a first set of particles, wherein the first set of particles have a first optical response when they are illuminated by light having a first wavelength. |
| US09626538B2 |
Method and system for increasing the operational safety of mobile machines in aboveground or underground mining operations for the extraction of minerals by utilizing the RFID technology
A system and method for increasing the operational safety of mobile machines in mining operations by utilizing RFID technology includes a transmitting unit at the mobile machine, a receiving unit, and a non-machine-related RFID transponder which can be activated by the transmitting unit and in the case of activation is contactlessly detected. A reference transponder and a control unit for actuating the transmitting unit and evaluating transponder signals in measuring cycles is provided. To improve the energy requirement of the method and system, the reference transponder may be mounted on the mobile machine at a defined distance, stored in the control unit, from the transmitting unit. The signal field strength L of the transmitter signal of the transmitting unit may be changed in dependence on the response signal of the reference transponder in a calibration cycle (KCB) for eliminating the environmental influences. |
| US09626537B2 |
RFID system with distributed read structure
A radio frequency identification (RFID) system includes a portable RFID reader, and a read infrastructure that includes a distributed read structure, which may be part of a display (such as a shelf) for holding objects. The read structure is used to couple the RFID reader to RFID devices (tabs and/or labels) on or near the structure. The RFID reader and the read structure communicate in a near field or proximity region communication, without any use of a direct ohmic electrical connection. The RFID reader may have an antenna that is configured for near field or proximity communication with a coupler of the read infrastructure. The RFID reader may also have a separate antenna for use in far field communication. The RFID reader may be able to obtain information more efficiently in the near field or proximity mode, allowing information to be received faster and with greater reliability. |
| US09626536B2 |
Identification tags and their manufacture
In FIG. 9 a female identification tag is formed by overmolding between mold parts (8, 9) a base section (1) which will include inwardly directed projections or fingers (4) to retain in use the head of a male tag and may include an RFID coil (6). As the mold parts (8,9) separate, the core (10) can start to eject, moving through the flexible opening (13) formed at the top of the soft boss (12) of the tag. Subsequently, a hard insert can close off the opening (13) in providing tamperproofing. The core (10) can be caused to rotate as it moves through the flexible opening (13) in order to break any bond between the plastics material and the core (10). |
| US09626529B2 |
Secure data storage device and data writing and read methods thereof
A secure data storage device for preventing tampering with data stored thereon includes a two-dimensional memory array for storing data, the array includes a predetermined number of data words. Each data word includes a set of bits, and is associated with a single physical address in the memory array. A key storage area for storing a key of the data storage device is included in the device. The secure data storage device includes an address conversion unit configured to convert a logical address to a corresponding physical address which points to a location in the memory array. The device includes a bit mixing unit for mixing bit values of an input data word to obtain a mixed word value, such that the mixed word value is a rearrangement of the bit values of the input data word. The device is electrically connectable to a host. |
| US09626528B2 |
Data leak prevention enforcement based on learned document classification
The present disclosure relates generally to the field of automatically learning and automatically adapting to perform classification of protected data. In various examples, learning and adapting to perform classification of protected data may be implemented in the form of systems, methods and/or algorithms. |
| US09626526B2 |
Trusted public infrastructure grid cloud
Systems and methods of implementing a secured cloud environment allow for design and instantiation of a security policy at the infrastructure level. An example system may comprise a first module to facilitate selecting at least two cloud computing component templates from a cloud computing component catalog. The system may comprise a second module to facilitate defining a connection between the at least two selected cloud computing component templates. The system may comprise a third module to facilitate assigning a security level and a policy to at least one of the at least two selected cloud computing component templates. The system may comprise a fourth module to facilitate building a cloud computing component blueprint. |
| US09626521B2 |
Physiological signal-based encryption and EHR management
Systems and methods are provided for encoding and decoding data (such as, for example, an encryption key) using a physiological signal. A data item string is separated into a defined number of component segments and each component segment is used as a coefficient of a polynomial equation. A plurality of signal features are then identified from a physiological signal and a plurality of ordered pairs are created based on the plurality of identified signal features using the polynomial equation. A data package including the plurality of ordered pairs and obfuscated by a plurality of chaff points is transmitted to another system. The receiver system uses a corresponding physiological signal to filter out the chaff points and to reconstruct the polynomial equation, for example, by LaGrangian interpolation. The coefficients of the reconstructed polynomial equation are then used to derive the encoded data item string. |
| US09626519B2 |
Motion input device for portable terminal and operation method using the same
The present invention relates to a motion input device for portable terminal and an operation method using the same. A motion input device of a portable terminal of the present invention includes a sensor unit configured to collect a sensor signal from at least one sensor; an operation recognition unit configured to generate a motion signal corresponding to an operation of portable terminal based on the sensor signal; a scenario preparation unit configured to generate an input scenario based on at least one motion signal; and a scenario mapping unit configured to detect, in a scenario database, a standards scenario corresponding to the input scenario, and to generate an input signal corresponding to the standards scenario. |
| US09626517B2 |
Non-deterministic encryption
A non-deterministic encryption functionality receives and encrypts an open-text input stream. Codes for error-correction are generated for the encrypted stream, and a correctable amount of non-deterministic random error is overlaid onto the encrypted stream and the codes for error-correction. The error-injected encrypted stream and codes for error-correction are re-encrypted and delivered to a using process. A non-deterministic decryption functionality reverses the encryption, in some embodiments using key values used during the encryption, and delivers an open-text stream to a using process. Some embodiments of a non-deterministic encryption include a reversible scrambling layer. In some embodiments, the non-deterministic encryption and decryption functionalities are performed, at least in part, by a controller of a solid state disk. In some embodiments, the functionalities are performed within a secure physical boundary provided by implementation within a single integrated circuit. |
| US09626514B2 |
Method and apparatus for selectively enabling a microprocessor-based system
A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the system is obtained. In the preferred embodiment of the invention, a valid hash value is determined, preferably based on the state information and preferably by locating the valid hash value within a table of valid hash values indexed by the state information. Candidate authorization information is obtained from the user, and a candidate hash value is generated by applying a hashing algorithm to the candidate authorization information, the state information, or a combination of the candidate authorization information and state information. The candidate hash value and the valid hash value are then compared, and the microprocessor-based system is enabled if the candidate hash value matches the valid hash value. In this manner, the designer or distributor of the system can determine, at the time of manufacture or distribution, the conditions and circumstances under which the system may be operated. |
| US09626513B1 |
Trusted modular firmware update using digital certificate
An electronic device includes a boot memory, a hardware memory programmed with a signing key, and a processor configured to implement a fixed trusted module and a dynamic trusted image module. The fixed trusted module contains a digital certificate, which includes a platform key used to verify a first boot module, and a package verification key used to validate authenticity of an image update file. The dynamic trusted image module contains a platform certificate signed by the signing key. The platform certificate includes a platform verification key used to validate at least one of (i) a second boot module, (ii) an operating system loader, (iii) an operating system, or (iv) a file system. The platform certificate also includes image information associated with one or more images stored in the platform certificate, key information associated with one or more public keys, and electronic device-specific data. |
| US09626510B2 |
Method, device and system for processing computer virus
A method, an apparatus and a system for processing a computer virus. The method comprises: obtaining the file type of a file which is infected with a computer virus and the process information of a process which is used by the virus when accessing the file; monitoring whether a malicious event occurs in s system, wherein the malicious event is an event which is triggered when the process corresponding to the process information accesses the file of the file type; and refusing the process to access the file of the file type when it is monitored that the malicious event occurs. |
| US09626509B1 |
Malicious content analysis with multi-version application support within single operating environment
Techniques for efficient and effective malicious content detection in plural versions of a software application are described herein. According to one embodiment, multiple versions of a software application are concurrently within a virtual machine (VM) executed within a data processing system. For each of the versions of the software application, a corresponding one of the versions is invoked to access a malicious content suspect within the VM without switching to another VM. The behaviors of each of the versions of the software application in response to the malicious content suspect is monitored to detect anomalous behavior indicative of malicious content in the malicious content suspect during execution of any of the versions of the software application. The detected anomalous behaviors, and, associated therewith, a version number corresponding to each of the versions of the software application whose execution resulted in the anomalous behavior are stored. An alert with respect to any indicated malicious content is issued. |
| US09626508B2 |
Providing supervisor control of control transfer execution profiling
In one embodiment, an apparatus includes a control transfer termination (CTT) state machine configured to raise a fault when an indirect control transfer instruction of a process is not terminated by a CTT instruction. A virtual machine monitor (VMM) is configured to selectively enable the CTT state machine for the process. In addition, a binary translation engine is configured to receive fault information associated with a fault raised by the CTT state machine, provide at least some of the fault information to a security agent associated with the process, and responsive to direction from the security agent, to translate a code block of the process to a translated code block including a first CTT instruction associated with the indirect control transfer instruction, such that when the translated code block including the indirect control transfer instruction and the first CTT instruction is to be executed, the CTT state machine will not raise a fault. Other embodiments are described and claimed. |
| US09626506B1 |
Dynamic password generation
Generating and authenticating a dynamic password. A first password string is received from a user. One or more string generation rules with corresponding reference character positions of the first password string are received. The first password string, the string generation rules, and the corresponding reference character positions of the first password string are associated with login credentials of a user. For authentication, a first password string associated with a user is received. A second password string is generated, based on a partial password string and one or more string generation rules, with corresponding reference character positions of the partial password string, all associated with the user. The first password string is compared with the second password string, and the user is authenticated if the strings match. |
| US09626504B2 |
Information processing device and information processing method
This technology relates to an information processing device and an information processing method capable of detecting that at least one of data and a parameter of a command is falsified. A command reception unit of an IC card receives a read command from a reader/writer through an antenna. A MAC calculation unit calculates a MAC based on a read address included in a parameter of the read command and read data to be transmitted to the reader/writer. A response transmission unit transmits the read data and the MAC to the reader/writer through the antenna. This technology is applicable to the IC card, for example. |
| US09626501B2 |
Method, system and mobile device employing enhanced user authentication
The described embodiments relate generally to methods and systems for user authentication for a computing device. In one embodiment, the method comprises: enabling receipt of input in relation to selection of a plurality of authenticators for consecutive use by the computing device to authenticate a user; and storing reference information identifying the selected plurality of authenticators in a memory of the computing device. The computing device may comprise a mobile device. |
| US09626498B2 |
Multi-person gestural authentication and authorization system and method of operation thereof
A system of authorizing access to a resource including a processor obtaining sensor information related to at least two users from one or more sensors, the sensor information including one or more of image information and proximity information of each of the at least two users. Further, an act of identifying current gestures is performed for each of the at least two users in accordance with the sensor information. The current gestures may be compared with pre-stored gesture information related to predetermined gestures and an order of the predetermined gestures. Further, access to the resource may be authorized when it is determined that the current gestures are in accordance with the predetermined gestures and the order of the predetermined gestures. |
| US09626493B2 |
Continuous digital content protection
Data from one or more sensors of a computing device can be employed to provide continuous protection of digital content. After user authentication and authorization, sensor data can be utilized to control access to protected content. More specifically, sensor data can be employed as a basis for initially providing an authorized user access to protected content and subsequently terminating access to the protected content. For additional security, content can be embedded with user identifying information in the form of a watermark. Further, such user identifying information can be provided to a content owner identifying one or more users who viewed the content. |
| US09626491B2 |
Enabling enforcement of licensing terms in distributing content in containers by including a key in the container containing the pertinent licensing terms
A method, system and computer program product for enforcing licensing terms when distributing content via a container image running in a container. Upon receiving a request for a service from the container by the isolation code, where the isolation code limits, accounts and isolates resource usage of process groups, the commerce code application programming interfaces (APIs) of the isolation code read a key of the container. The key contains licensing terms applied to the component(s) (e.g., applications) of the container. The commerce code APIs will then confirm that the container is in compliance with those licensing terms. If the container is in compliance with the licensing terms, the container will be allowed to execute. Otherwise, the container will be prevented from executing. In this manner, the commerce code APIs can enforce the licensing terms, including restrictions and enforcement of payment to the licensor upon distributing content in the container. |
| US09626488B2 |
Java store television
A non-transitory computer readable storage medium including computer readable code that, when executed by a processor, is configured to receive, from a user network device, a first request to execute an application on the user network device. The first request includes a user identification, routing information, and requested application information, encrypted using a public key. The user network device is configured to display the application on a television display device. The code is further configured to decrypt the routing information and requested application information using a private key, send a second request for subscription information to a service provider, receive the subscription information from the service provider, and determine that a license corresponding to the application is associated with the user. The code is further configured to generate and send an application package configured to deploy the application using a Java Runtime Environment on the user network device. |
| US09626485B2 |
Secure medication transport and administration system
A portable medication dispensing system is described. In some embodiments, the system includes a portable medication tote comprising a securable compartment configured to hold medication, and a controller, responsive to access information, configured to assign a patient to the securable compartment such that medications for the patient are authorized for placement into the securable compartment. The controller is also configured to selectively permit a user access to the medications for the patient in the securable compartment when the access information indicates the user has access to the securable compartment, and restrict access to retrieval of the medications for the patient in the securable compartment when the access information indicates the user does not have access to the securable compartment. The system also includes an information output module configured to output usage information regarding access to the securable compartment. |
| US09626482B2 |
Decision support tool for use with a medical monitor-defibrillator
Work flows are modeled as a graph of interdependent tasks to be performed. The tasks to be performed are set by a task file module configured to enable interactions between tasks and including modules for event viewing, protocol assistance, smart messaging, smart indices, reference material lookup. A decision support manager module is configured to construct data and model profiles for storage in a data and model profile bank, events for storage in a decision support events bank, and protocols for storage in a decision support protocol bank. Configuration files are provided to specify a configuration for execution of one of the tasks. Data entered through a user interface or from a network via a wireless or wired communication module may define task files in the task files module, configuration files in the configuration files module, as well as data, events, and protocols to be used for a defibrillation procedure. A decision support manager module is configured to construct a dependency graph of tasks as specified in at least one of the configuration files and to execute the dependency graph. |
| US09626480B2 |
Analyte testing method and system
Various systems and methods of operating an analyte measurement device is provided. The device has a display, user interface, processor, memory and user interface buttons. In one example, one of the methods can be achieved by measuring an analyte with the analyte measurement device; displaying a value representative of the analyte; prompting a user to activate a test reminder; and activating the test reminder to remind a user to conduct a test measurement at a different time. Other methods and systems are also described and illustrated. |
| US09626475B1 |
Event-based currency
An approach to facilitating event-based currency is provided. A first virtual currency usable by users of a game space to purchase in-space benefits may be managed. An event in the game space that is conducted during an event time period may be managed such that, during the event time period, an event virtual currency may be distributed to one or more of the users as a reward for certain operations and/or achievements performed in the game space during the event time period. Exchanges of in-space benefits associated with the event virtual currency may be effectuated for one or more of the users. In some implementations, the event virtual currency may not available to the users after the event time period, while the first virtual currency may be available to the users during and after the event time period. |
| US09626473B2 |
CMOS device including a non-straight PN-boundary and methods for generating a layout of a CMOS device
A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells.For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed. |
| US09626470B2 |
Generating a circuit description for a multi-die field-programmable gate array
A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation. |
| US09626468B2 |
Assertion extraction from design and its signal traces
Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification. |
| US09626465B2 |
Arbiter verification
Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter. |
| US09626464B2 |
Method for evaluating and configuring label application processes
A method for configuring a package labeler, and or labeling process including: providing a package defined as a computed mesh; providing a computed mesh description of a package labeler; providing operational parameters of a labeling operation for the package; simulating the interaction of the package and the package labeler according to the operational parameters of the labeling operation, the computed mesh of the package labeler and the computed mesh of the package; determining the location and/or deformation of the package mesh during at least a portion of the simulated interaction; and confirming, rejecting, or configuring the package labeler according to the determined location(s). |
| US09626462B2 |
Detecting tooth wear using intra-oral 3D scans
A method for detecting tooth wear using digital 3D models of teeth taken at different times. The digital 3D models of teeth are segmented to identify individual teeth within the digital 3D model. The segmentation includes performing a first segmentation method that over segments at least some of the teeth within the model and a second segmentation method that classifies points within the model as being either on an interior of a tooth or on a boundary between teeth. The results of the first and second segmentation methods are combined to generate segmented digital 3D models. The segmented digital 3D models of teeth are compared to detect tooth wear by determining differences between the segmented models, where the differences relate to the same tooth to detect wear on the tooth over time. |
| US09626458B2 |
Evaluation model generation device, evaluation model generation method, and evaluation model generation program
An evaluation model generation device is provided to generate an evaluation model which evaluates the function or non-function of an IT system based on a system model including a process model which describes processing between processes on the IT system, a server model which describes a physical system configuration of the IT system, and allocations which represent correspondence relations between the elements in the process model and those in the server model. The evaluation model generation device includes: path enumeration means 110 which extracts a process path between processes in the process model, and a server path corresponding to the process path and located on the server model; allocation estimation means 120 which estimates the allocation based on the process path and the server path; and model conversion means 130 which converts the system model into the evaluation model using the process paths, the server paths, and the estimated allocations. |
| US09626457B2 |
Method for real time computation of the state variables of a hybrid differential-algebraic process model
Method for real time computation of the state variables of a hybrid differential-algebraic process model (DAP) in succeeding time steps on a process computer with a process interface, the process computer detecting at least one process variable of a physical process and/or producing output for influencing the physical process, the hybrid DAP being solved at least by a integrator functionality, a condition evaluation functionality and identification of a condition change by a consistency detection functionality for structure decision variables, and depending on the result parts of the hybrid DAP being active or inactive. Prompt computation is possible when a condition of the hybrid DAP changes by the consistency detection functionality being carried out in a sorted consistency handling function (KHF), in the case of a condition change, first and third parts of the sorted KHF being carried out once and a second part thereof being carried out repeatedly. |
| US09626456B2 |
Crowd sourcing for file recognition
Methods for identifying content in encrypted or otherwise protected files utilize crowd sourcing for content identification. One such method includes, using a computer, selecting defined content titles to be presented with identifiers for data files for use in obtaining user selection data. The method may also include receiving the user selection data from multiple independent sources, the user selection data indicating users' selections of single ones of the content titles for respective single ones of the data files. The method may also include determining for ones of the identifiers, using the one or more computers processing the user selection data, respective ones of the content titles satisfying a minimum confidence threshold for association with the ones of the identifiers. An apparatus for performing the method comprises a processor coupled to a memory, the memory holding instructions for performing steps of the method as summarized above. |
| US09626455B2 |
Systems and methods for displaying estimated relevance indicators for result sets of documents and for displaying query visualizations
Systems and methods for displaying estimated relevance indicators for result sets of documents and for displaying query visualizations are disclosed. A method includes receiving a search query including a plurality of query terms. The method further includes searching a database using the search query to identify the result set of documents and calculating an estimated relevance score for the result set of documents. The estimated relevance score is indicative of a degree to which the result set of documents are relevant to the search query. The method further includes providing for display the estimated relevance indicator based on the estimated relevance score. The estimated relevance indicator provides a visual indication of the degree to which the result set of documents are relevant to the search query. Query visualizations including a plurality of nodes and a plurality of connectors are also disclosed. |
| US09626452B2 |
Fine-grained database access-control policy enforcement using reverse queries
A method of providing access control to a database accessible from a user interface is implemented at a policy enforcement point, which is located between the database and the user interface and includes the steps of: (i) intercepting a database query; (ii) assigning attribute values on the basis of a target table or target column in the query, a construct type in the query, or the user or environment; (iii) partially evaluating an access-control policy defined in terms of said attributes, by constructing a partial policy decision request containing the attribute values assigned in step ii) and evaluating the access-control policy for this, whereby a simplified policy is obtained; (iv) deriving an access condition, for which the simplified policy permits access; and (v) amending the database query by imposing said access condition and transmitting the amended query to the database. |