最新美国发明专利
Document Document Title
US09584680B2 Function providing system and recording medium for using functions provided by server
A function providing system for providing a function to an image forming apparatus includes a server and a function relaying circuit. The server provides a function for the image forming apparatus. The function relaying circuit is located outside the image forming apparatus, the function relaying circuit providing the function to the image forming apparatus. The function relaying circuit uses the function corresponding to an instruction from the image forming apparatus, and the function relaying circuit transmits a use result of the function to the image forming apparatus.
US09584675B2 Image processing apparatus, communication condition setting method
An image processing apparatus includes a speed detecting portion and a communication condition setting portion. The speed detecting portion performs wireless communications with a communication device in a plurality of predetermined frequency bands and detects communication speeds of the wireless communications that respectively correspond to the plurality of predetermined frequency bands. The communication condition setting portion sets a frequency band that corresponds to a highest communication speed among the communication speeds detected by the speed detecting portion, as a communication frequency band to be used in wireless communications that are performed to transmit and receive image data to/from the communication device.
US09584668B1 Method and system for a scalable computer-telephony integration system
Various aspects may include storing sets of call agent login information for several call agents within the computer-telephony integration system and across several independent computing systems in a contact center login database. Additionally, various aspects may include generating several contact center service categories and sets of contact information for each contact center service category, which may be stored in a contact center directory database. When an incoming call is received from a customer, various aspects may include obtaining customer call information from the customer and generating a customer call key, which may be stored as a reference to the customer call information in a contact center customer call information database. The call key may be used to reduce an amount of data electronically transferred between call agents during telephone call transfers.
US09584665B2 System and method for optimizing timing of responses to customer communications
A system and method for optimizing timing of responses to customer communications comprises a contact center and an operations center. The operations center includes a decision module that receives each communication and determines whether a partial response, such as an acknowledgement that the communication was received, is required. If a partial response is required, a response module sends a partial response to the sender that indicates the communication was received and preferably includes an estimate of the time required for a full response to the communication. All received communications are forwarded to a queue to await processing by an agent. The decision module determines whether a partial response is required based on an estimate of the amount of time required for a full response. If the time estimate is less than a predetermined threshold, a partial response is not sent and the communication is forwarded to a queue for processing.
US09584662B2 System and method for the automatic validation of dialog run time systems
A method, system and module for automatically validating dialogs associated with a spoken dialog service. The method comprises extracting key data from a dialog call detail record associated with a spoken dialog service, transmitting the key data as a dialog to a state-based representation (such as a finite-state machine) associated with a call-flow for the spoken dialog service and determining whether the dialog associated with the key data is a valid dialog for the call-flow.
US09584659B2 Using graphical text analysis to facilitate communication between customers and customer service representatives
Embodiments relate to facilitating communications between customers and customer service representatives. A method for facilitating communications between customers and customer service representatives is provided. The method generates a graph of expressions of a customer. The method generates a graph of expressions of each customer service representative of a plurality of customer service representatives. The method performs a graphical text analysis on the graph for the customer to identify an interaction style of the customer. The method performs a graphical text analysis on the graph for each customer service representative to identify an interaction style of the customer service representative. The method selects a customer service representative from the plurality of the customer service representatives based on the interaction style of the customer and the interaction styles of the plurality of the customer service representative. The method starts a communication between the customer and the selected customer service representative.
US09584658B2 Call distribution techniques
Increasing the efficiency of phone call usage is accomplished by using strategic call forwarding techniques to analyze incoming calls and process these calls in real time to: 1) divert unwanted robocallers and/or 2) provide information about unknown human callers. Robocallers are detected by analyzing incoming calls to determine if the audio is human-based or generated by a robocaller. Information about unknown human callers is obtained by real-time look up and reporting techniques to allow the user to determine whether to answer a call.
US09584653B1 Smartphone with user interface to externally localize telephone calls
A user interface of an electronic device includes icons that enable a user to answer a telephone call in monophonic sound or binaural sound. When the telephone call is answered in binaural sound, the electronic device convolves a voice in the call with head related transfer functions (HRTFs) of a person so the voice localizes to an external location that is away from but proximate to the person.
US09584652B2 Standard mobile communication device distraction prevention and safety protocols
Methods and systems for providing standardized mobile device distraction prevention and safety protocols are disclosed. In particular, an embodiment of a method for activating a distraction prevention or safety protocol behavior in a mobile device when the mobile device satisfies a specific condition is disclosed. The method includes discovering one or more protocol activators configured to transmit discovery information associated with a specific condition. The method further includes activating distraction prevention safety protocol behavior in the mobile device based at least in part on the discovery information. In an implementation, the specific condition may be a specified environment itself and or include an event when the mobile device enters a specified environment or a specified sequence of numbers is dialed from the mobile device.
US09584644B2 Electronic device and method for handling incoming call of the same
A method for handling an incoming call of an electronic device and an electronic device using the same is provided. The method includes displaying a user interface for handling the incoming call using a screen boundary of the electronic device, when receiving incoming call information while executing an application program on the electronic device, where the user interface for handling the incoming call using the screen boundary is displayed to overlap the user interface of the executed application program; sensing a touch event on the user interface for handling the incoming call using the screen boundary; and performing an incoming call handling function based on the sensed touch event.
US09584641B2 Messaging device
A portable messaging device is provided that can display visual messages and communicate with additional messaging devices via a local area network. The portable messaging device can include a display panel having an LED array, and a control unit. Lateral side walls, and the inner surface of the display panel can define at least part of a recessed opening configured to receive an electronic device such as a smartphone. The control unit can receive input via a user interface of the portable messaging device and, responsive to the input, provide a visual message to the LED array for display from the outer surface of the display panel.
US09584639B2 Mobile device modular magnetic assembly
In embodiments, a modular magnetic assembly includes a decorative modular section that is stackable with a functional modular section on a housing of a mobile device to form the modular magnetic assembly. The mobile device includes housing metal plates that are integrated in the housing of the device. The functional modular section includes magnets that are each positioned to couple with a respective housing metal plate that is integrated in the device housing. The decorative modular section includes section metal plates that are each positioned to couple with a respective one of the magnets of the functional modular section. The magnets of the functional modular section couple together the decorative modular section and the housing of the mobile device, where one side of the functional modular section stacks against the mobile device, and the other side stacks against the decorative modular section to form the modular magnetic assembly.
US09584636B2 Dynamic in-band service control mechanism in mobile network
A method, computer readable medium and apparatus for transmitting signaling information within payload traffic. For example, the method parses a certificate received from a service provider to obtain service imprint information associated with a mobile service, inserts a service control parameter derived from the service imprint information into a packet header, and forwards the packet header within payload traffic to a policy charging and enforcing function.
US09584633B2 Method and system for managing network communications
A system that incorporates teachings of the present disclosure may include, for example avoiding data copy and task switching by processing protocol headers of network PDUs as a serial tape to be processed in order such as by a single method. Other processing includes reducing stages and simplifying protocol processing and multiplexing during network communications. Address changing in an active network can be implemented by assigning multiple addresses to an entity so that a new address can replace the old address. Peer-to-peer application searching can be performed among networks that can be accessible or non-accessible networks. Utilizing anycast sets that include selected and alternative addresses to enable immediate or near immediate alternative route selection on failure or congestion. Other embodiments are disclosed.
US09584630B2 Light weight protocol and agent in a network communication
Systems and methods are provided for using a light weight protocol (LWP) and protocol agent in a network communication system. A protocol agent receives a message in LWP from an end node. The message in LWP is directed to a destination network node that uses a network protocol that the end node is incapable of supporting, such as Hypertext Transfer Protocol (HTTP), Real Time Streaming Protocol (RTSP), Session Initiation Protocol (SIP) or other network protocols. The protocol agent determines a network protocol to map the message to, and generates a message in the determined network protocol based on the received LWP message. The protocol agent then sends the generated message to the destination network node.
US09584629B2 Systems and methods for managing and publishing managed content
Systems and methods for content management server systems configured to manage and publish managed content in accordance with embodiments of the invention are disclosed. In one embodiment, a versioned content management server system, includes a processor, a versioned content management application, managed content, wherein managed content includes content and content version metadata, wherein the versioned content management application configures the processor to receive updated content, locate managed content based on the received updated content, determine version data based on a portion of the located managed content, the received updated content, update the content version metadata data, associate the updated version content data with the managed content, receive a request for content, identify a portion of the managed content that corresponds to the requested content, retrieve the identified portion of the managed content, and transmit the retrieved portion of the managed content.
US09584627B2 Control device, control system, and control method
A control device including: an input unit which accepts input of a reproduction mode; a content reproduction device determination unit which determines whether content is to be reproduced by a content reproduction device or by the control device, in accordance with the reproduction mode; and a display unit which displays reproduced content, wherein the content reproduction device determination unit transmits a content reproduction instruction to the content reproduction device if the content reproduction device determination unit determines that the content is to be reproduced by the content reproduction device, and the content reproduction device determination unit causes the display unit to display the content acquired from a server if the content reproduction device determination unit determines that the content is to be reproduced by the control device.
US09584623B2 Data sharing apparatus and method of mobile terminal
An apparatus and method for sharing data between a cloud server and at last one terminal are provided. The method includes displaying, when a data type is selected on a setting menu screen of a cloud service, meta information of real data corresponding to the selected data type, the meta information being downloaded from a server, downloading, when a piece of meta information is selected, the real data corresponding to the selected piece of meta information from the server, and deleting, when the downloaded real data is consumed completely, the consumed real data.
US09584622B2 Method for network controlled access selection
The invention provides an Access Selection Server (ASS) and a method for the same. The invention also provides a User Equipment (UE). The Access Selection Server (ASS) comprises storing means and software and is adapted for location in a communication network comprising at least one User Equipment (UE) and communication nodes. The ASS is also arranged to store information of all accesses for each UE in the communication network and information of overall load status of the communication network in the storing means by means of collecting information through interactions with the communication nodes, the UE and an Access Selection Server subscriber Data Base (ASS DB). The ASS is further arranged to communicate control messages, based on the stored information, from the ASS to the UE, thereby enabling control of multiple UE-accesses from the ASS.
US09584619B2 Business web applications lifecycle management with multi-tasking ability
Technical solutions for managing business application life cycle with multi-tasking ability are provided. In some implementations, a method includes: at an enterprise data processing application: (A) activating a first application page, which includes: loading a first data set from a first data source, and causing the first data set to be displayed on the first application page; (B) switching from the first application page to a second application page, by: deactivating, without closing, the first application page, including: causing the first data set to be stored in a temporary storage; and activating a second application page; and (C) switching from the second application page back to the first application page, by: deactivating, without closing, the second application page; and re-activating the first application page, including: loading the first data set from the temporary storage, and causing the first data set to be displayed on the first application page.
US09584617B2 Allocating cache request in distributed cache system based upon cache object and marker identifying mission critical data
Various embodiments of the present disclosure provide improved systems and techniques for intelligently allocating cache requests to caches based upon the nature of the cache objects associated with the cache requests, and/or the condition of the caches in the distributed cache system, to facilitate cache system utilization and performance. In some embodiments, an allocation of cache requests may be performed in response to detection of a problem at one of a group of cache servers. For example, in some embodiments, a particular cache server may be entered into a safe mode of operations when the cache's ability to service cache requests is impaired. In other embodiments, an allocation of cache requests may be performed based on an cache object data type associated with the cache requests.
US09584615B2 Redirecting access requests to an authorized server system for a cloud service
In some embodiments, a first server system of a cloud service can receive a bearer token for accessing the cloud service. The bearer token can be generated based on authenticating a remote client in communication with the first server system. The first server system can determine that a resource of the cloud service is hosted by a second server system of the cloud service rather than the first server system. The resource can be identified using the bearer token. The first server system can provide the bearer token to the remote client along with redirect information for accessing the second server system. The second server system can in respond to receiving the bearer token from the remote client by establishing a session with the remote client. The remote client can access the resource via the session with the second server system.
US09584611B2 Management device and management system
A hop count between a management device and a management target device is calculated, and a notification destination range of an unspecified notification pertaining to a power supply mode is obtained from the management target device. On the basis of the obtained results, it is determined whether or not an unspecified notification pertaining to the power supply mode can be received from the management target device. Furthermore, on the basis of the result of the determination, the management device requests the management target device to register the management device as an individual notification destination.
US09584605B2 System and method for preventing denial of service (DOS) attack on subnet administrator (SA) access in an engineered system for middleware and application execution
A system and method for supporting subnet management in a network environment is described. The system and method can be used in an engineered system for middleware and application execution, or a middleware machine environment. The system can associate a subnet administrator (SA) in a subnet with a plurality of SA proxies, each of which can receive plurality of requests from one or more client nodes. The SA can handle the requests, which are forwarded from the SA proxies. Additionally, each client node can be assigned a dedicated queue pair (QP) number, so that there is no need for always sending an initial request to a pre-defined well-known QP number.
US09584604B2 Utilization of subscriber data in a telecommunication system
A method of providing telecommunication services in a telecommunication system including a terminal, a serving network providing the terminal with services, and a bearer network in functional connection with the serving network. One or more databases including subscriber data are created in the telecommunication system, the subscriber database(s) being in functional connection with the bearer network. Data according to the subscriber database, such as a subscriber identifier, are transmitted to the serving network and/or the terminal. The terminal is provided with services in accordance with the transmitted subscriber data.
US09584599B2 Method and system for presenting storage in a cloud computing environment
Methods and systems for presenting a plurality of options to a client for using storage space in a cloud computing environment are provided. Each option is associated with a latency target and/or a throughput target. The latency target provides a delay in processing input/output (I/O) requests and the throughput target provides a number of I/O requests that are processed within a unit of time. An existing volume is assigned to the client when the existing volume meets a guaranteed latency target and/or a guaranteed throughput target for an option selected from the plurality of options, otherwise a new volume is allocated.
US09584597B2 Hardware level generated interrupts indicating load balancing status for a node in a virtualized computing environment
A computing node includes at least one hardware layer comprising a plurality of hardware resources and at least one virtualization layer operative to manage at one virtual machine defined by at least one resource from among the plurality of hardware resources. The computing node includes load balancing interrupt logic configured in the hardware layer of the node. The load balancing interrupt logic is operative to compare at least one resource utilization level of the plurality of hardware resources by the at least one virtual machine with at least one threshold. The load balancing interrupt logic is operative to generate at least one load balancing interrupt indicating at least one load balancing status of the computing node based on the comparison of the at least one resource utilization level with the at least one threshold.
US09584593B2 Failure management in a distributed strict queue
Methods and systems for implementing failure management in a distributed strict queue are disclosed. A plurality of messages are distributed to a plurality of queue servers based on strict order parameters for the messages. Messages that share a value for the strict order parameter are distributed to the same queue server. The messages are enqueued at the queue servers. Messages that share a value for the strict order parameter are enqueued in a strict order based on the time of receipt at the queue server. One or more queue clients are configured to attempt message processing for the enqueued messages. Log data is received from the one or more queue clients at the queue servers. The log data is descriptive of the attempted message processing.
US09584588B2 Multi-stage feedback controller for prioritizing tenants for multi-tenant applications
Methods, systems, and computer-readable storage media for determining weights for selecting requests from a plurality of tenant queues in a multi-tenant system receiving measured response time and measured throughput for each tenant in a set of tenants being considered in a current period, for each tenant in the set of tenants, determining a weight based on respective measured response times and respective measured throughput, the weight being determined based on one of a previous weight, an initialized weight, a modified proportional and integral (PI) control, and a volunteer weight increase, providing a set of weights that includes weight for each tenant in the set of tenants, and transmitting the set of weights to an access mechanism, the access mechanism selecting tenant requests for processing by a shared resource.
US09584585B2 Drive with server
The present invention relates to a drive system that includes a module that operates as a server, where at least sometimes the module is at least one of directly integrated with another module that operates as a drive and fully integrated to include the drive. The server allows for communications with one or more terminals via an internet-type communications medium, while the drive is for controlling, monitoring and/or otherwise interacting with at least one motor, electromechanical machine, or other appropriate type of machine/process. In at least some embodiments, the server is capable of providing web pages, executable programs and/or other information including, for example, information in accordance with an FTP protocol onto the internet for receipt by the terminals. The terminals communicate commands and other information via the internet back to the server, which in turn can influence the drive and the controlled machine/process.
US09584580B2 URL rescue by identifying information related to an item referenced in an invalid URL
A server system is disclosed that is capable of providing responsive content to a user when a request for an invalid URL is received. In a preferred embodiment, the server system implements multiple rescue strategies for attempting to rescue the invalid URL. One such rescue strategy involves repairing the URL by correcting for encoding errors, such as errors introduced by some web clients. Another rescue strategy involves determining that the URL contains an obsolete or outdated item identifier (e.g., product identifier) that renders the URL invalid, and returning information regarding one or more related items to the user. Another rescue strategy involves mining the invalid URL for one or more text strings reflective of the type of content desired, and then using the one or more text strings to execute a keyword search to identify content to provide to the user. The various rescue strategies may be attempted in sequence according to a hierarchy.
US09584577B2 Method for enabling use of HLS as a common intermediate format
In one embodiment a method, system, and apparatus is described for providing multimedia content from a server to a plurality of media devices, the method including providing a computing device an HTTP Live Streaming (HLS) playlist for playing in an adaptive bitrate client, the playlist including a list of at least two segments, each of the segments having an associated duration field, for each segment in the playlist, assigning a timestamp which is equal to the sum the durations of each previous segment in the playlist, calculating a calculated duration of the playlist by subtracting a time stamp of the first segment in the playlist from the time stamp of the last segment in the playlist, determining a real duration of the playlist by subtracting a first presentation time stamp (PTS) of the first segment in the playlist from the last presentation time stamp (PTS) of the last segment in the playlist, computing a playlist drift by subtracting the calculated duration of the playlist from the real duration of the playlist, determining a correction factor by dividing the playlist drift by the number of segments in the playlist, and calculating a new timestamp for each segment in the playlist by adding the correction factor to the time stamp of the segment. Related methods, systems, and apparatus are also described.
US09584575B2 Qualified video delivery
A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU. The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream.
US09584570B2 Dynamic media transcoding for P2P communications
An apparatus for distributing video content includes one or more video input modules each adapted to receive a video signal from a video source, and a video combiner for receiving the video signals from the one or more video inputs and generating a video packet data stream. The apparatus also includes at least one video output module adapted to transmit the video packet data stream, and a processor coupled to the video combiner and the at least one video output. The processor cooperates with one or both of the video combiner and the at least one video output to transcode at least a portion of the video packet data stream.
US09584568B2 Signal processing apparatus and signal processing method thereof for implementing a broadcast or a multicast communication
A communication system includes: a control apparatus that sets broadcast domains or multicast domains respectively for virtual networks configured in a physical network including a forwarding node(s), and sets, in the forwarding node(s), broadcast or multicast control information, associating a packet forwarding destination and a match condition including an identifier for identifying one of the broadcast domains or multicast domains; and the forwarding node(s) that performs a broadcast or multicast using the broadcast or multicast control information.
US09584562B2 System, method, and apparatus for user-initiated provisioning of a communication device
An embodiment of a method and apparatus for provisioning of a communication device includes receiving a registration request from a first communication device. The registration request includes an address associated with the first communication device. The method further includes registering the first communication device in response to receiving the registration request, placing a call request to the first communication device, and establishing a call session with the first communication device. The method further includes prompting a user of the first communication device for a user identifier, and receiving a user identifier from the user of the first communication device. The method still further includes sending one or more configuration parameters associated with the user identifier to the first communication device. The one or more configuration parameters are operable to configure the first communication device.
US09584559B2 Session establishment using one multimedia telephony (MMTEL) application server
According to a first aspect of the present invention there is provided a method of handling an IP Multimedia Subsystem, IMS, session establishment request received from a calling party at a Multimedia Telephone Application Server, MMTel AS, within an IMS network from a Serving Call Session Control Function, S-CSCF, over an IMS Service Control, ISC, interface. The method comprises, within the MMTel AS: a) determining that said request is an originating call case request; b) establishing a first Multimedia Telephone, MMTel, service engine instance within the MMTel AS and using that first MMTel service engine instance to handle the request according to an originating call case; c) determining whether or not a called party associated with said request is served by said MMTel AS and, if so, establishing a second MMTel service engine instance within the MMTel AS, passing the request to said second MMTel service engine instance, and using the second MMTel service engine instance to handle the request according to a terminating call case; and d) forwarding said IMS session establishment request over said ISC interface to said S-CSCF, or to another S-CSCF serving the called party.
US09584553B2 User experience of a voice call associated with a device
Aspects of the present disclosure provide techniques and apparatus for improving user experience of a voice call associated with a simultaneous voice and long-term evolution (SV-LTE) device (e.g., improving silent redial during a mobile originated (MO) call or mobile terminated (MT) call by a SV-LTE device. A method for wireless communications by a user equipment (UE) capable of communicating via a first packet-based radio access technology (RAT) and a second circuit-switched RAT is provided. The method generally includes detecting initiation of a mobile originated (MO) call, attempting to establish a connection with the first RAT prior to sending a session initiation protocol (SIP) message for the MO call, determining whether the connection is successfully established, and, if the connection is successfully established, sending the SIP message. Numerous other aspects are provided.
US09584546B2 Providing services to virtual overlay network traffic
In one embodiment, an apparatus includes a processor and logic integrated with and/or executable by the processor. The logic is configured to communicate with a first physical switch, a second physical switch, and an overlay network that connects the first physical switch to the second physical switch. The logic is also configured to receive a request for a communication path through the overlay network for a packet, the request including at least the packet, first information about a source of the packet, the source of the packet being connected to the first physical switch, and second information about a most closely connected physical switch to a destination of the packet. Moreover, the logic is configured to determine the destination of the packet, the destination of the packet being connected to the second physical switch. Also, the logic is configured to determine whether to apply a security policy to the packet.
US09584542B2 Relay attack countermeasure system
An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.
US09584534B1 Dynamic field re-rendering
A computer-implemented method involves identifying an initial element for serving by a web server system to a client device and recoding the element by creating a plurality of different elements that each represent a portion of the initial element. The different elements are then served in place of the initial element. A response is received form the client device and has portions that correspond to the different elements, and a combined response is created by combining the received portions in a manner that corresponds to a manner in which the initial element was recoded to create the plurality of different elements.
US09584533B2 Performance enhancements for finding top traffic patterns
A method for network traffic characterization is provided. Flow data records are acquired associated with a security alert signature. Unidimensional traffic clusters are generated based on the acquired data. A Bloom filter is populated with the acquired flow data records. Clusters of interest are identified from the generated unidimensional traffic clusters. The identified clusters of interest are compressed into a compressed set. A determination is made whether a multidimensional processing of the acquired flow data needs to be performed based on a priority associated with the alert signature. A multidimensional lattice corresponding to the unidimensional traffic clusters is generated. The multidimensional lattice is traversed and for each multidimensional node under consideration a determination is made if the Bloom filter contains flow records matching the multidimensional node under consideration. A determination is made if the unidimensional node corresponding to the multidimentional node is included in the compressed set of unidimensional nodes.
US09584531B2 Out-of band IP traceback using IP packets
A method and system for tracing internet protocol packets is disclosed. One aspect of the method involves generating traceback packets containing information relating to their origin, destination, and encountered devices. The generated traceback packets can differ depending on the network configuration and Internet traffic scenarios. Another aspect involves analyzing incoming Internet traffic and generating traceback packets based on the performed analysis. Another aspect involves discovering a denial-of-service attack. Another aspect involves modifying operational parameters in response to the attack. One aspect of the system involves traceback servers, which can collect and provide traceback information to the public or on a private network. Another aspect involves the dissemination of traceback information to interested and/or authorized parties.
US09584526B2 Anonymous discussion forum
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enabling anonymous posting of content, e.g., over a network (e.g., the internet). In some instances, users may inform a system of various attributes of the user, for example, job title, skills, and/or interests. The system may group similar users together. In some cases, users grouped together can see messages posted by the other users in the group in an anonymous discussion forum. In other cases, users grouped together can have other users in the group presented to them as potential options of users to follow, e.g., as part of an anonymous social media platform. In some implementations, users can identify particular user subsets to view posted content.
US09584522B2 Monitoring network traffic by using event log information
A solution is provided for associating network traffic traversing a networked environment according to a selected category item, such as a user name or other network entity identity-related information. The solution includes a collector and a monitor. The collector extracts a user name and a network address from an event log maintained on the networked environment. The monitor receives the network traffic and identifies at least one packet having a network address that matches the extracted network address. After at least one of the packets is identified, the collector associates the identified packet(s) with the extracted user name.
US09584519B2 Apparatus, and associated method, for controlling connectivity of a computer device with a computer network
A computer device can include a plurality of network adapters each operable to connect the computer device with a network, such as a private wired local area network (LAN) or a wireless local area network (WLAN). The computer device can include a controller to detect and select a first network of the plurality of networks. The controller can further enable a first network adapter of computer device to connect the computer device with the first network. In response to enabling the first network adapter, the controller can disable the other network adapter(s) to prevent connectivity with the other network(s).
US09584515B2 Enterprise system authentication and authorization via gateway
Methods and systems are disclosed for providing approaches to authenticating and authorizing client devices in enterprise systems via a gateway device. The methods and systems may include passing, by a computing device to an enterprise device, a request transmitted by a client device for access to an enterprise resource, and transmitting, by the computing device, authentication credentials associated with the client device with a request for authorization information associated with the enterprise resource. The methods and systems may also include receiving, by the computing device, the authorization information associated with the enterprise resource, transmitting, by the computing, the request transmitted by the client device for access to the enterprise resource with the received authorization information associated with the enterprise resource, and passing, by the computing device to the client device, information associated with the requested enterprise resource based on the received authorization information associated with the enterprise resource.
US09584513B2 Network resource management system utilizing physical network identification for privileged network access
The disclosed network resource management system employs a hardware configuration management (HCM) information handling system (IHS) that may couple to a single administered IHS or to multiple administered IHSs via an administrative network. An HCM tool in the HCM IHS may generate, modify and store hardware configuration information, including physical network identifications (PNet IDs), in an HCM database and share the HCM database with the administered IHSs. The administered IHS may be a privileged network access (PNA) IHS. The PNA IHS may receive a privileged network access management (PNAM) database from a PNAM IHS via the administrative network. The PNA tool may extract hardware configuration information, including PNet IDs, from the HCM database and privileged network access information, including PNet IDs, from the PNAM database. The PNA tool may utilize the information, including PNet IDs, to enable the PNA IHS to limit access to privileged networks.
US09584508B2 Peer to peer enterprise file sharing
Disclosed are various embodiments for facilitating the distribution of files from a file repository. Files from a file repository can be distributed via peer to peer transmissions where the peer devices can perform authentication functions. The authentication can be performed based upon metadata associated with the files as well as based upon authentication requests submitted to an authentication server.
US09584484B2 Systems and methods to secure a virtual appliance
The present disclosure relates to systems and methods for providing secure support to virtual appliances delivered to customer sites without passwords or enabled ports for service. A virtual appliance may be established on a first device. The virtual appliance may comprise a self-contained virtual machine with a pre-installed operating system and may be established with no root password enabled and a remote access port disabled. An administration tool may receive from a requestor a request to enable maintenance for the virtual appliance. The administration tool may generate, responsive to the request, a random password. The administration tool may enable, responsive to the request, the remote access port. The virtual appliance may wait for a connection to the remote access port for a predetermined period of time. The administration tool may transmit the random password to a service of a second device remote to the first device.
US09584483B2 Method and apparatus for transmitting an NFC application via a secure channel including a proxy and computing device
In a method for transmitting an NFC application, a secure channel is established by way of a proxy between a Trusted Service Manager and an NFC device via a computing device including the proxy and via an RFID reader being a part of the computing device. The NFC application received at the computing device from the Trusted Service Manager is channeled through the secure channel to the NFC device utilizing the proxy.
US09584480B2 System for and method of securing a network utilizing credentials
A system for and method of securing a network are described herein. A receiving device listens for packets with proper credentials. If a transmitting device sends the correct credentials, the receiving device will respond with an acknowledgment and further data is able to be transmitted. However, if the transmitting device does not send a packet with the proper credentials, then the receiving device will drop the packet and not respond. Thus, the transmitting device will be unaware of the presence of the receiving device, in particular when hackers are using scanning software to locate target devices.
US09584474B2 SIM card activation
A method of activation of a SIM in a mobile device includes sending an authentication request 30 from the SIM 4 in a mobile device 2 to an HLR 22 corresponding to the mobile network operator of the SIM 4. When the HLR 22 does not contain a record that the SIM is activated, not merely does the HLR 22 return a rejection of the authentication request but additionally a provisioning request 32 to provisioning server 24 is automatically made. The provisioning server 24 then, in response to the provisioning request, updates the HLR so that the HLR does contain a record 23 that the SIM is activated such that subsequent authentication requests from the SIM are not rejected by the HLR. In this way, the SIM is not activated before activation needed. This is of particular utility where the SIM is installed by the manufacturer in M2M apparatus.
US09584473B2 Facilitating content accessibility via different communication formats
Methods and systems for facilitating content accessibility via different communication formats are provided. According to one embodiment, a method is provided for directing content requests to an appropriate content delivery network. A content request is received from a client. The content request relates to web page content published by a content publisher in an Internet Protocol version 4 (IPv4) format or an Internet Protocol version 6 (IPv6) format that is obtained by the content delivery network from the content publisher and is translated to the other format by the content delivery network prior to receiving any content requests for the web page content. A communication format through which the client is capable of communicating is determined. The content request is directed to a content delivery network that supports the communication format through which the client is capable of communicating.
US09584466B2 Method of establishing an IP connection in a mobile network and various corresponding equipment items
The disclosure relates to the field of wireless communications, and more particularly a method of establishing an IP connection through a 3GPP mobile network, at least partially of IP type, a network equipment item, MME or PDN-GW, of that mobile network, a mobile network infrastructure, a mobile terminal and a corresponding system. The method includes the following steps, on a first equipment item, MME or PDN-GW, of the mobile network other than a mobile equipment item UE of the mobile network: receiving a fully qualified domain name, FQDN, sent by a mobile equipment item, UE, of the mobile network, the FQDN identifying a target data server; and on reception of the FQDN, triggering the resolution of the FQDN into an IP address of the target data server. Thus, a mobile user equipment item provided with a UICC card may be produced at low cost without incorporating DNS resolution mechanisms.
US09584465B2 Optimizing messages to users of a social network using a prediction model that determines likelihood of user performing desired activity
Techniques to optimize messages sent to a user of a social networking system. In one embodiment, information about the user may be collected by the social networking system. The information may be applied to train a model for determining likelihood of a desired action by the user in response to candidate messages that may be provided for the user. The social networking system may provide to the user a message from the candidate messages with a selected likelihood of causing the desired action.
US09584464B2 Systems and methods for establishing communications between mobile device users
Provided are systems and methods for establishing a communication between mobile device users that register with a collaboration system. The collaboration system determines a match between profile data of the first registered mobile device and profile data of the second registered mobile device. Displayed at the first registered mobile device is a first list of user identifications, which includes an identification of a user of the second registered mobile device and an identification of a user of at least one other mobile device. Displayed at the second registered mobile device is a second list of user identifications. The second list includes an identification of a user of the first registered mobile device and an identification of at least one other mobile device user.
US09584461B2 Method and apparatus for transmitting electronic mail
The present invention comprises a method and apparatus for e-mail communications with members of a group of members. In one or more embodiments, a server computer system determines whether a sender of an incoming e-mail message addressed to a recipient member of the group is a member of the group. If the sender is a member of the group, the server computer system replaces the senders existing e-mail address in the incoming e-mail message with a created e-mail address created by the server computer system for the sender.
US09584460B2 Communicating information describing activity of computer system users among computer system users
A computer-implemented method receiving receives information describing a current or future activity from a user of a computing system via a mobile device. The current activity is an activity occurring at a current time when the information is received, while the future activity is an activity occurring at a future time relative to a time when the information is received. The method transmits the information describing the current or future activity to a backend database coupled to the Internet and remote from the mobile device. The information describing the current or future activity is accessible to at least one recipient having access privilege to information associated with the user and describing the current or future activity via the Internet.
US09584459B2 Communicating information describing activity of computer system users among computer system users
A computer-implemented method receiving receives information describing a current or future activity from a user of a computing system via a mobile device. The current activity is an activity occurring at a current time when the information is received, while the future activity is an activity occurring at a future time relative to a time when the information is received. The method transmits the information describing the current or future activity to a backend database coupled to the Internet and remote from the mobile device. The information describing the current or future activity is accessible to at least one recipient having access privilege to information associated with the user and describing the current or future activity via the Internet.
US09584456B2 Storage and processing of ephemeral messages
A server includes volatile and non-volatile memories for storing messages received from a client device. A message reception module of the server stores a message received from a first client device in the volatile memory for an extended time period based on an indicator included in the message. The message reception module deletes the message from the volatile memory based on detection of a triggering event or stores the message in the non-volatile memory based on not detecting the triggering event before the extended time period has expired. The triggering event may include the message having been read by all specified recipients of the message. The indicator may be included in the message based on a relationship of the message to other messages. The message including the indicator may be related to other messages as part of a same conversation that has been determined to be suitable for short-term storage.
US09584455B2 Method and apparatus of processing expression information in instant communication
A method provides an expression picture in an instant communication conversation window; acquires information of a user operation activity information from a sending user with respect to the expression picture; searching a first expression database based on the expression picture and the acquired information of the user operation activity; generates a first response message corresponding to the expression picture under the user operation activity; and sends found information related to the expression picture and the acquired information of the user operation activity to a receiving client corresponding to a receiving user to facilitate the receiving client to generate a second response message corresponding to the expression picture under the user operation activity.
US09584453B2 Contact list aggregation and display
A technique for contact list aggregation across networks involves logging into low level networks through a high level network. A system constructed according to the technique may include a network interface coupled to the different low level networks. The system may further include a contact aggregation engine coupled to the network interface and a network contacts database. In operation the system logs into one or more of the low level networks (or facilitates login for a user). To the extent that the data in the network contacts database is not current, the contact aggregation engine updates the networks contacts database contact information, then provides an aggregated contact list including the contact information to a display device. A method according to the technique may include logging into a high level network and displaying contacts from the one or more low level networks in an aggregated contact list. The method may further include logging into the one or more low level networks.
US09584452B2 Method, apparatus, and system for adding electronic mail attachment
A method comprising: executing an operation on a file; obtaining a mail editing task list; determining at least one mail editing task; and sending an attachment adding instruction to a mail editing apparatus that generates the mail editing task to instruct the mail editing apparatus to add the file as an attachment of a mail corresponding to the mail editing task. Through the embodiments of the present invention, when a user executes an operation on a file, a current mail editing task list can be automatically obtained, and the file is used as an attachment of a mail corresponding to at least one determined mail editing task.
US09584445B2 Direct connect virtual private interface for a one to many connection with multiple virtual private clouds
Systems and methods include a direct connect virtual private interface includes a physical port configured to receive one physical connection in order to provide two or more virtual connections for multiple virtual private clouds (VPCs) within a public cloud provider's infrastructure. Each public cloud infrastructure has its own multiple VPCs. Each VPC is an on demand configurable pool of shared computing resources allocated within each public cloud provider's infrastructure that provides a certain level of isolation via an access control mechanism between different organizations using the pool of shared computing resources of that VPC's public cloud infrastructure. The direct connect virtual private interface is configured to provision a virtual circuit from the one physical connection between the public cloud infrastructure for each VPC within each public cloud provider's infrastructure.
US09584444B2 Routing communication between computing platforms
Routing communication in a data processing system. Communication is routed from a communication client having no own communication stack through a first own communication stack of a first communication bridge, and through a second own communication stack of a second communication bridge. Routing between the communication client and the first and the second communication bridges uses a communication mechanism that does not include an own communication stack. One of the first or the second communication bridges is configured to act as a master communication bridge, and the other of the second or the first communication bridges is configured to act as a slave communication bridge.
US09584442B2 Managing a set of assets of a shared pool of configurable computing resources
Disclosed aspects manage a set of assets of a shared pool of configurable computing resources. A set of usage data is established by the shared pool of configurable computing resources. The set of usage data corresponds to usage of the set of assets by a set of users. The shared pool of configurable computing resources determines an asset load-order based on the set of usage data. An operation associated with the set of assets is performed by the shared pool of configurable computing resources. In response to performing the operation associated with the set of assets, the set of assets is loaded based on the asset load-order by the shared pool of configurable computing resources.
US09584438B2 Idle worker-process page-out
Systems and methods for handling idle websites on a Web server are disclosed. The duration between requests for a website application is monitored and compared to an idle time-out value. The idle time-out value may be a user-selected value that is the same for all website applications or an idle time-out value selected for a group of worker processes. When the idle time-out value is reached, all inactive memory allocations for the website application are paged-out. When a request for the website application is later received, memory for the website application is paged-in so that the request can be processed.
US09584436B1 Method and system for managing class of service in a network
In general, embodiments of the invention relate to a method and system for managing network access for applications. More specifically, embodiments of the invention provide mock Internet Protocol (IP) addresses to the applications, where the applications may use the mock IP addresses to communicate with other systems (e.g., other computing devices, the management service, or any other system that is accessible via the network). Each mock IP address may be associated with one or more policies, where the policies dictate how packets that includes the mock IP address are processed. In one or more embodiments of the invention, the mock IP addresses may be used to maintain a class of service (CoS) between applications executing on the computing devices and an application service provider (ASP).
US09584433B2 Data transmission method and apparatus
Provided is a data transmission apparatus including a queue management unit to manage at least one queue in which information associated with at least one buffer descriptor (BD) is stored, a scheduler to estimate information to be transmitted among information associated with at least one media access control (MAC) protocol data unit (MPDU) using at least one transmission bitmap (Tx bitmap), a data transmitter to read the estimated information from information associated with a BD indicated in the at least one Tx bitmap, and transmit the read information to a physical layer, and a physical layer management unit to generate information associated with a presentation protocol data unit (PPDU) based on the transmitted information, and transmit the generated information over the air, wherein the at least one BD includes information associated with the at least one MPDU.
US09584428B1 Apparatus, system, and method for increasing scheduling efficiency in network devices
An apparatus for increasing scheduling efficiency in network devices may include (1) at least one memory device that stores at least one data chunk included in a packet, (2) a scheduler device that (a) schedules transmission of the packet that includes the data chunk and (b) issues a request to transmit the packet based at least in part on the scheduled transmission, and (3) a packet-delivery device that (a) receives the request to transmit the packet from the scheduler device, (b) prepares the packet for transmission at a faster rate than the scheduler device schedules the transmission of the packet, and then (c) facilitates transmitting the data chunk included in the packet to a computing device. Various other apparatuses, systems, and methods are also disclosed.
US09584425B2 Bandwidth optimization using coalesced DUP ACKs
After sending M consecutive DUP ACKs, M generally being three, the TCP receiver generates DUP ACKs every N packets, with N greater than one, with the eventually transmitted DUP ACK containing SACK information. After receiving the third DUP ACK the TCP transmitter uses the positive acknowledgements provided in the SACK information in the TCP header to inflate the congestion window. With the reduced DUP ACKs from the TCP receiver to the TCP transmitter, the impact of TCP DUP ACKs on the data rate from the TCP receiver to the TCP transmitter is substantially reduced.
US09584424B2 QOS control system, QOS control method, and program
Provided is a QoS control system, a QoS control method, and a program suitable for use in a server virtualization environment in which an I/O virtualization technology can be used. The QoS control system includes a network interface and a network interface management unit. The network interface holds a QoS (Quality of Service) parameter giving identification information for identifying traffic, a priority value to be applied to a packet belonging to the traffic, and information indicating the storage location of the priority value in the packet, stores the priority value in the packet belonging to the traffic, and then transmits a resulting packet. The network interface management unit holds a QoS policy including a QoS parameter to be applied to each traffic, and manages the network interface.
US09584422B2 Methods and apparatuses for automating return traffic redirection to a service appliance by injecting traffic interception/redirection rules into network nodes
Methods and apparatuses for automating return traffic redirection to a service appliance by injecting forwarding policies in a packet-forwarding element are disclosed herein. An example method for automating return traffic redirection can include: establishing a communication channel between a service appliance and a packet-forwarding element; and transmitting an out-of-band message over the communication channel to the packet-forwarding element. The message can include a forwarding policy that requests the packet-forwarding element to forward predetermined packets to the service appliance.
US09584419B1 Systems and methods for detecting consistent fabric congestion in a datacenter based on historical traffic data
Detecting network congestion at a network device by collecting, for various time intervals, measurements of a quantifiable characteristic of traffic transiting the network device at a plurality of respective measurement times during each of the time intervals. Described systems and methods select two or more sets of measurements, each set corresponding to a respective time interval; determine, for each of the selected sets of measurements, respective upper and lower boundaries for the quantifiable characteristic during the respective time interval; and analyze trends for a time window inclusive of the time intervals corresponding to the selected sets of measurements, the trends including an upper boundary trend and a lower boundary trend. Congestion is then identified responsive to the analysis detecting a substantially constant upper boundary trend concurrent with a rising lower boundary trend.
US09584418B2 Quantized congestion notification for computing environments
Embodiments of the invention relate to providing quantized congestion notification (QCN) in networks. One embodiment includes a method that includes determining a traffic flow congestion by a particular congestion point (CP) unit of multiple CP units that communicate with at least one end unit, at least one reaction point (RP) unit and at least one controller in a network. A first congestion notification message (CNM) and a second CNM are generated by the particular CP unit. The particular CP unit sends the first CNM directly to the controller and the second CNM directly to the RP unit. Traffic flow is managed among the multiple CP units by the controller based on the first CNM.
US09584417B2 Monitoring congestion status in a network
A network node arranged to monitor (531) the number of consecutive blocked scheduling attempts made by a terminal (532), and to identify a congestion event for the terminal (534) when the number of consecutive blocked scheduling attempts exceeds a threshold value (533).
US09584414B2 Throughput optimization for bonded variable bandwidth connections
The present disclosure provides for devices, systems, and methods which optimize throughput of bonded connections over multiple variable bandwidth logical paths by adjusting a tunnel bandwidth weighting schema during a data transfer session in response to a change in bandwidth capabilities of one or more tunnels. By making such adjustments, embodiments of the present invention are able to optimize the bandwidth potential of multiple connections being used in a session, while minimizing the adverse consequences of reduced bandwidth issues which may occur during the data transfer session.
US09584413B2 Systems and methods for determining input and out interfaces of a network device and copies of a same packet going through the network device
A method performed by a network device that taps to a network having a routing device, includes: receiving a first packet tapped from the network; determining a first information regarding an input interface of the routing device based on a destination address of the first packet; receiving a second packet tapped from the network; determining a second information regarding an output interface of the routing device based on a source address of the second packet; determining a first CRC for the first packet; determining a second CRC for the second packet; and comparing the first CRC with the second CRC at the network device to determine whether the first packet and the second packet are the same.
US09584410B2 System and method for selecting layer-2 adapter
The present invention relates to a Layer 2 adapter selecting system, including a Layer 3 packet requirements extracting module, a destination Layer 2 address acquiring module, a Layer 2 adapter metric acquiring module, an appropriate Layer 2 adapter identifier selecting module, a packet caching module and a packet scheduling module; wherein the packet caching module is configured to cache a received Layer 3 packet; the Layer 3 packet requirements extracting module is configured to read the Layer 3 packet and extract the type and a parameter value of the requirements; the Layer 2 adapter metric acquiring module is configured to acquire instant metric parameter values of each of the adapters; the appropriate Layer 2 adapter identifier selecting module calculates an adapter identifier and a Layer 3 packet metric; the destination Layer 2 address acquiring module is configured to acquire a Layer 2 address of each of the adapters associated with a destination Layer 3 address; and the packet scheduling module calls an external Layer 2 adapter driver, and the Layer 2 adapter driver completes packaging and sending of the packet. The present invention may solve the problem of resource waste of multiple links, so that the multiple links may be used dynamically in parallel.
US09584409B2 Network system and method of improving resource utilization
A network system of the present invention comprises a switch and a controller. The switch performs processes on a received packet in accordance with a flow entry in which are defined a rule and an action for uniformly controlling a packet as a flow. The controller sets the flow entry to a flow table of the switch. The switch notifies a vacancy status of a flow table of the switch itself to the controller. The controller performs a path calculation in consideration with the vacancy status of the flow table of the switch to improve a utilization of the flow table of the switch.
US09584407B2 Adaptive private network with path maximum transmission unit (MTU) discovery process
Systems and techniques are described for a path maximum transmission unit (MTU) discovery method that allows the sender of IP packets to discover the MTU of packets that it is sending over a conduit to a given destination. The MTU is the largest packet that can be sent through the network along a path without requiring fragmentation. The path MTU discovery method actively probes each sending path of each conduit with fragmentation enabled to determine a current MTU and accordingly increase or decrease the conduit MTU. The path MTU discovery process is resilient to errors and supports retransmission if packets are lost in the discovery process. The path MTU discovery process is dynamically adjusted at a periodic rate to adjust to varying network conditions.
US09584405B2 Application layer session routing
A method and server system for providing application layer session routing based on network element availability. A server system (12, 18) is arranged to monitor the abilities of session control edge nodes (21A-D) within a large VoIP and Multimedia transit network (20) to handle session set-up requests. A status module (38) in the server system receives status messages (22, 24) from the edge nodes and based on these messages a selection and modification module (40, 41) selects which edge nodes (21A-D) as well as which of their associated interconnects to other networks to include in a response (5) to a routing request (4) from a source node (21A-D).
US09584403B2 Communications scheduler
A system for providing communications over a communications network includes a communications interface and a processor. The communications interface communicates over the communications network. The processor directs a communications scheduler to determine at least one metric for a path within the communications network. The processor also selects a data flow for the path and determines whether to transmit a packet in the selected data flow based on the at least one metric. The processor then directs a communications protocol handler to generate the packet for the selected data flow.
US09584399B2 Preventing a loop in a vertical stack network
According to an example, a Port Extender (PE) device is bundled with a Core Backbone (CB) device to prevent a loop in a vertical stack network including the PE device and the CD device.
US09584398B2 Methods and apparatus to utilize route parameter sets for exchanging routes in a communication network
Methods and apparatus to utilize route parameter sets for exchanging routes in a communication network are disclosed. An example method to exchange routes in a communication network disclosed herein comprises receiving a route comprising a route identifier identifying the route and a plurality of route parameter values characterizing the route, and sending the route identifier and a pointer to forward the route to a recipient in the communication network, the pointer being associated with a route parameter set comprising the plurality of route parameter values.
US09584395B1 Adaptive metric collection, storage, and alert thresholds
Techniques for adaptive metric collection, metric storage, and alert thresholds are described. In an approach, a metric collector computer processes metrics as a collection of key/value pairs. The key/value pairs represent the dimensionality of the metrics and allows for semantic queries on the metrics based on keys. In an approach, a storage controller computer maintains a storage system with multiple storage tiers ranked by speed of access. The storage computer stores policy data that specifies the rules by which metric records are stored across the multiple storage tiers. Periodically, the storage computer moves database records to higher or lower tiers based on the policy data. In an approach, a metric collector in response to receiving a new metric, generates a predicted metric value based on previously recorded metric values and measures the deviation from the new metric value to determine whether an alert is appropriate.
US09584394B2 Notifying original state listeners of events in a domain model
Notifying original state listeners within a domain model. Identifying listener registration information pertaining to a listener. Monitoring a hierarchical relationship tree for an observable event, whereby the hierarchical relationship tree includes model objects, and whereby an observable event includes one or more of a change to a model object, an error condition associated with a model object, and the hierarchical relationship tree returning to an original state. Determining that a first observable event to the hierarchical relationship tree has occurred. Transmitting a notification to the listener detailing the occurrence of the first observable event. Determining that a second observable event to the hierarchical relationship tree has occurred. Determining that a third observable event to the hierarchical relationship tree has occurred, whereby the third observable event includes the hierarchical relationship tree returning to an original state. Transmitting a notification to the listener detailing the occurrence of the third observable event.
US09584392B2 Method and apparatus for managing segments connected via network
Provided is a method and apparatus that may generate a ping packet, transmit the generated ping packet to at least one tunnel end point (TEP), receive a response ping packet from each of the at least one TEP in response to the ping packet, and update information on a state of at least one segment connected to each of the at least one TEP based on the received response ping packet.
US09584389B2 Physical resource management
A method and system for resource management is provided. The method includes generating a physical server pool. Resources of the physical server pool and additional resources of additional physical server are monitored and monitored data is retrieved during the monitoring. A utilization rate of the additional physical server pools is determined to be less than a threshold value. In response a group of physical servers is migrated to a free server pool. The physical server pool is determined to need an additional server and each physical server pool is rated based on a calculated chance for required usage. A first physical server is allocated to the physical server pool.
US09584387B1 Systems and methods of sending a packet in a packet-switched network through a pre-determined path to monitor network health
Systems and methods for monitoring a computer network are provided. A network monitoring system generates a plurality of monitoring packets. The plurality of generated monitoring packets travel along respective paths through the computer network across a plurality of monitored links to respective destination nodes. Every monitored link in the computer network is included in at least one path. Each monitoring packet includes forwarding information which identifies each of the monitored links the monitoring packet is to traverse along its respective path. The network monitoring system tracks receipt of the generated monitoring packets by the respective destination nodes to detect faulty links.
US09584386B2 Node unit capable of measuring delay and distributed antenna system including the same
A node unit of distributed antenna system, the node unit comprises a delay measuring part configured to transmit a first test signal for delay measurement to an upper adjacent node unit and detect the first test signal looped back via the upper adjacent node unit and measure a round trip delay between the node unit and the upper adjacent node unit, and a delay providing part disposed on a signal transmission path through which a second test signal for delay measurement, to be transmitted from a lower adjacent node unit, is to be looped back to the lower adjacent node unit, and configured to provide a delay corresponding to the round trip delay.
US09584382B2 Collecting and using quality of experience information
Concepts and technologies are disclosed herein for collecting and using quality of experience information. A server computer executing a quality of experience management service can receive a request for quality of experience display data. The server computer can obtain location data defining a geographic location of a user device and analyze quality of experience information defining a quality of experience of an application program associated with the user device. The server computer can generate the quality of experience display data based upon the quality of experience information, and provide the quality of experience display data to the user device.
US09584380B2 Method and system for detecting slow page load
A method and system for detecting slow page load is provided. An example system comprises a page request detector, a session state information detector, a throughput calculator, a response builder, and a communications module. The page request detector may be configured to receive a request for a web page. The session state information detector may be configured to determine that the request does not include session state information. The throughput calculator may be configured to calculate a throughput value associated with the network connection between the client system and the server. The response builder may be configured to build an updated data packet by including, in the data packet, the throughput value and an instruction to store the throughput value on the client as session state information. The communications module may be configured to communicate the updated data packet to the client system.
US09584378B1 Computer-implemented command control in information technology service environment
A computer-implemented agent process running on a first computer automatically intercepts a command issued from the first computer to execute on a target computer prior to invocation of the command on the target computer. A server profile built for an application running on the target computer that supports the command may be retrieved. At least based on the server profile a risk enforcement policy is dynamically constructed. Based on the risk enforcement policy, one or more computer-executable enforcement actions to perform prior to sending the command to the target computer for execution is determined. Based on executing of one or more of the computer-executable enforcement actions, the command may be transmitted to execute on the target computer or prevented from executing on the target computer.
US09584376B2 Framework supporting content delivery with content delivery services
A framework supporting content delivery includes a plurality of devices, each device configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include services supporting content delivery.
US09584375B2 Method, system and apparatus for establishing and monitoring sessions with clients over a communication network
Systems and methods provide real-time communication between website operators and website visitors including monitoring, gathering, managing and sharing of information. The features include: simultaneous chatting with system's website visitor while responding/submitting tickets/emails and searching through company knowledge base; operator communicating message to another operator directly in active chat session, while message remains hidden to visitors/customers; displaying advertising messages to visitors/customers within chat window during active chat sessions; growing knowledge base by adding information into knowledge base during chat session; providing real-time access to system's website visitor information by seeing the content of visitor's shopping cart or by passing information from system's server into visitor's information located in operator's panel; creating and branding multiple chat windows and selectively linking all or some to the account; tagging and grouping each chat sessions; parent-child ticketing for project management; lead scoring; and mobile live chatting.
US09584374B2 Monitoring overall service-level performance using an aggregate key performance indicator derived from machine data
One or more processing devices derive a value for each of a plurality of key performance indicators (KPIs). Each KPI indicates a different aspect of how the same service provided by one or more entities is performing at a point in time. Each KPI is defined by a search query that derives the value for that KPI from machine data associated with the one or more entities that provide the same service. The one or more processing devices calculate a value for an aggregate KPI for the same service from the values for each of the plurality of KPIs.
US09584371B2 System and method for assigning multi-instance services in a provider network
A system and method for placing inline services having multiple instances in a service provider network. In one implementation, a topology of the service provider network and services to be placed therein are defined, wherein a network node may include a data forwarding functionality and a control plane functionality. Using service chaining policy requirements, the number of service instances, etc. as input, services and their multiple instances are placed within the network such that an overall network metric is optimized for all subscriber data flows.
US09584367B2 Node de-duplication in a network monitoring system
Systems, methods, apparatuses, and computer program products for node de-duplication. One method includes discovering, by a network monitoring apparatus, nodes in a network, and collecting a list of internet protocol (IP) addresses, media access control (MAC) addresses, domain name system (DNS) names, and sysnames for each of the nodes discovered in the network. The method may also include comparing the collected list of information for each of the discovered nodes with corresponding information for current nodes and other discovered nodes. The method may then includes determining duplicate nodes that are duplicates of the other discovered nodes and/or the current nodes based on the comparison of the IP addresses, MAC addresses, DNS names, and sysnames.
US09584366B2 System and method for controlling configuration settings for mobile communication devices and services
A system for controlling configuration settings for mobile data communication devices and services includes a redirection server and a policy generation system. The redirection server detects a triggering event in a host system and in response to the triggering event continuously redirects data items from the host system to a wireless network. Each mobile data communication device receives data items from the wireless network and includes a device configuration stored in a memory location on the mobile data communication device. The device configuration of each mobile data communication device controls one or more functions of the mobile data communication device. The policy generation system receives a policy setting from a user interface and stores the policy setting in a user information record associated with a mobile data communication device. The redirection server detects the policy setting in the user information record and in response to detecting the policy setting transmits the policy setting over the wireless network to the mobile data communication device associated with the user information record. The mobile data communication device automatically modifies the device configuration to include the policy setting. Methods of controlling a configuration setting in mobile data communication devices are also disclosed.
US09584363B1 Redundant storage solution
Method and apparatus for switching between a first server and a second server, each located within a virtual private cloud and the first server being located within a first zone and the second server being located within a second zone that is physically separate from the first zone. The method and apparatus further configured to determine that the first server has experienced a failure to send or receive data. The method and apparatus further configured to enable a second port on the second server. The method and apparatus further configured to create a new route table at the second server and flush the previous route table. The method and apparatus further configured to transmit, via the second port, a request to a virtual private cloud controller to update an elastic internet protocol address with the second port information and receive data from the virtual private cloud controller.
US09584360B2 Global server load balancing support for private VIP addresses
A site switch determines the mapping between public and private IP addresses of VIPs configured on the site switch. The site switch then transmits the public IP address, rather than the private IP address, to a load balancing switch that performs the load balancing for network resources accessible via the site switch. This public IP address has also been configured on an authoritative DNS server for which the load balancing switch serves as a proxy. The load balancing switch updates its address records, containing the VIPs configured on the site switch, with the public address of the VIP. When the load balancing switch reorders a DNS reply from the authoritative DNS server for a domain containing the public address, the load balancing switch correctly identifies the IP address as a VIP on the site switch and applies appropriate load balancing metrics to the received IP address.
US09584358B2 Global production rules for distributed data
Running a global production rule on data distributed over a plurality of machines may comprise receiving a local production rule that can run on each of the plurality of machines to jointly accomplish a global computation specified by the global production rule. The local production rule may be deployed to each of the plurality of machines, each of which stores a portion of the data and runs an instance of a rules engine that can run the local production rule. The plurality of machines are enabled to communicate intermediate data produced by the instance of the rules engine running the local production rule on said each of the machines. Coordinating between the plurality of machines is enabled to synchronize one or more local computations performed locally according to the local production rule on said each machine.
US09584348B2 Wireless communication device, program, wireless communication method, and wireless communication system
Provided is a wireless communication device, including a data processing unit that generates a data packet, and a transmitter unit that transmits the data packet generated by the data processing unit, wherein the data processing unit sets information for use other than an NAV setting to a Duration field in the data packet.
US09584347B2 Methods and systems for rapid detection of digital radio signals
Systems and methods are disclosed for rapid detection of digital content within received radio frequency (RF) signals. The disclosed embodiments digitize received RF signals and apply a sliding window average to subsampled complex magnitudes for the digital samples to generate subsampled magnitude values. The subsampled magnitude values are then collected over a small number of symbols for the digital content, and the results are analyzed to determine whether or not digital content is present with the received signals. For example, multi-symbol histograms and magnitude ratios determined over multiple symbols can then be utilized to make the determination of whether digital content is present in the received signals. The resulting detection determination can be utilized further to control operations of systems utilizing the disclosed embodiments. The disclosed embodiments can be used, for example, to detect the presence of HD (High Definition) Radio digital content within broadcast channels.
US09584346B2 Decision-feedback equalizer
A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.
US09584344B2 Stream creation with limited topology information
The discovery of a topology of a network with an unknown topology can enable the selection of a data path within the network, and the establishment of a data stream over the selected data path. Routing tables mapping originating nodes to input ports can be created based on the receipt of discovery messages generated by the originating nodes. A source node can select a data path between the source node and a sink node in order to establish a data stream using the routing tables. Data paths can be selected based on, for instance, routing table bandwidth information, latency information, and/or distance information. Data streams can be established over the selected data path, and each node can release any reserved output bandwidth determined to be unnecessary for the data stream.
US09584338B2 BUS device and BUS system with consumers, producers, and an allocation feature
A device, a fluidic system, a BUS system and a method of operating this BUS system are indicated. The BUS system includes a multitude of users which are producers and/or consumers of at least one process value. Information regarding at least one allocation feature is transmitted to the users of the BUS system by the users of a group of users of the BUS system and by the respective users of the groups themselves. The allocation feature is determined by the at least one process value produced and/or consumed by the respective users.
US09584337B2 Method and apparatus for network and service controlled hybrid access
A method for network controlled optimization of hybrid access traffic management for a residential user connected via a hybrid access home gateway, which provides at least two different network links with different technology to a core network, wherein the core network has a connection to the internet, wherein in the core network a Hybrid Access Server is located, includes: extracting by the Hybrid Access Server one or more of the following information: Network link availability, Network link utilization, Quality of Service information with respect to the services requested from the home gateway; and selecting networks links, network traffic routing, and/or service routing by the Hybrid Access Server in communication with the hybrid access home gateway and/or other components in the network.
US09584335B1 System and method of WiFi router based presence detection and control
A WiFi router based appliance control system and method. The router infers the presence of certain human or animal users based on the association between the user and the WiFi signals emitted by WiFi equipped computerized devices typically associated with the users. The router is configured to control various appliances (router controlled devices), and based on the inference that certain users are or are not local to the router, and various algorithms programmed into the router, the router will in turn control the various router controlled devices. Thus for example, if the router detects a WiFi equipped smartphone coming in range, it can respond by automatically turning on lights or adjusting heating and air conditioning appropriately.
US09584329B1 Physically unclonable function and helper data indicating unstable bits
Approaches for using a physically unclonable function (PUF) are described. A selector map is used to indicate stable and unstable bits in a PUF value that is generated by a PUF circuit. The stable bits of the PUF value generated by the PUF circuit may be selected for use by an application, and the unstable bits ignored.
US09584325B1 User-configurable cryptographic interface controller
Systems and methods for scalably provisioning cryptographic devices in a distributed computing environment are described. In some embodiments, a cryptographic interface controller capable of generating a plurality of hardware-emulated cryptographic devices in response to requests is implemented. In some embodiments, a cryptographic interface controller may present hardware-emulated cryptographic devices to computing entities, such as standalone computer systems or virtual computing systems, as standard cryptographic devices, such as through a Universal Serial Bus interface.
US09584321B2 Secure storage for shared documents
Embodiments are directed towards managing data storage for secure storage of shared documents. A user or an application may provide data destined for encryption and a public key. Instruction set information that references at least a seed file that may be installed on the network computer may be generated. An encryption key based on the instruction set information may be generated. Header information that includes the instruction set may be generated. And, the header information may be encrypted using the public key. A secure bundle that includes the public key, the encrypted header information, and the encrypted data may be generated and provided to the user that provided the data and the public key or the application that provided the data and the public key. Decrypting the data included in the secure bundle the above actions are generally performed in reverse.
US09584320B1 Blinding function in elliptic curve cryptography
A blinding function is generated. The blinding function is applied to a random value to generate a blinded random value. The blinded random value is utilized for one or more scalar multiplications in an elliptic curve cryptographic operation.
US09584316B1 Digital security bubble
A digital security bubble encapsulation is disclosed. A first key and a device identifier of at least one recipient is requested from a first server. A message containing one or more components is encrypted using a second key. The second key is encrypted using the first key. The encrypted message, the encrypted second key, and the device identifier are encapsulated in a digital security bubble encapsulation. The digital security bubble encapsulation is transmitted to a second server.
US09584306B2 Phase detection in an analog clock data recovery circuit with decision feedback equalization
An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.
US09584303B1 Reference-less frequency detector with high jitter tolerance
An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
US09584301B2 Periodic communication method between at least one first system and at least one second system by means of a full-duplex synchronous serial link
The invention relates to a periodic communication method between at least one first system (2) and at least one second system (3) by means of a full-duplex synchronous serial link (4), wherein, during a communication period, data are exchanged between the first system (2) and the second system (3), including: at least one message from the first system (2) to the second system (3), at least one message from the second system (3) to the first system (2) and a clock signal, the clock signal being routed by the link (4) over a time interval, the amplitude of which is less than the communication period, the message from the first system (2) to the second system (3) and the message from the second system (3) to the first system (2) both being routed by the link (4) over said time interval.
US09584300B2 Configuring uplink subframes and controlling power in a carrier aggregation system when the DCI format has first or second identifiers
The present invention relates to a wireless communication system. More particularly, the present invention relates to a method and an apparatus for a terminal controlling uplink power in the wireless communication system, comprising the steps of: configuring an uplink subframe (UL SF) of a first set and a UL SF of a second set; receiving a downlink control information (DCI) format including a bitmap for indicating transmit power control (TPC) for a plurality of terminals; and controlling transmit power of an uplink channel by using TPC information on the terminals from the bitmap, wherein the TPC information is used for controlling transmit power of an uplink channel transmitted from the UL SF of the first set when the DCI format comprises a first identifier, and the TPC information is used for controlling transmit power of an uplink channel transmitted from the UL SF of the second set when the DCI format comprises a second identifier.
US09584295B2 User equipment, and method and system side for configuring physical resource block of search space thereof
A method for configuring a physical resource block of a user equipment search space includes: a system side configuring a Physical Resource Block (PRB) pair of a default User equipment specific Search Space (USS), and notifying the user equipment of positions of the PRB pairs of the default USS, or the system side agreeing with the user equipment on the positions of the PRB pairs of the default USS. The user equipment obtains the positions of the PRB pairs of the default USS according to the notification from the system side, or agrees with the system side on the positions of the PRB pairs of the default USS. The embodiments of the present document further provide the system side and the user equipment.
US09584291B2 Control signaling for enabling two-hop orthogonalization for device-to-device broadcasts
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives one or more D2D broadcasts in a set of subchannels of a channel. In addition, the apparatus broadcasts in at least one subchannel of the channel information indicating a subset of the set of subchannels. The one or more D2D broadcasts may include a first set of broadcasts that includes control information and a second set of broadcasts that includes data traffic. The broadcasted information may be control information. The apparatus may determine a signal strength of each of the one or more D2D broadcasts received in the set of subchannels. The broadcasted information may further include the determined signal strength for each subchannel in the subset of the set of subchannels.
US09584287B2 Method and apparatus for transmitting uplink control information in wireless communication system
Provided are a method and an apparatus for transmitting uplink control information performed by a user equipment in a wireless communication system. The method comprises the steps of: receiving a first parameter for indicating whether to simultaneously transmit a first combination of an acknowledgement/negative-acknowledgement (ACK/NACK) and a channel quality indicator (CQI), and a second parameter for indicating whether to multiplex a second combination of an ACK/NACK and the CQI and transmitting same as a second physical uplink control channel (PUCCH) format; and multiplexing the first combination of the ACK/NACK or the second combination of ACK/NACK with the CQI and transmitting same as a first PUCCH format or the second PUCCH format, based on the first parameter and the second parameter.
US09584286B2 Method and apparatus for allocating resources in wireless communication system
A multiple distributed system is disclosed. An uplink control resource allocation method for a user equipment to transmit an Acknowledgement/Negative ACK (ACK/NACK) signal includes receiving one or more Enhanced-Physical Downlink Control Channels (E-PDCCHs), receiving one or more Physical Downlink Shared Channels (PDSCHs) corresponding to the one or more E-PDCCHs, and transmitting ACK/NACK signals for reception of the one or more PDSCHs through a Physical Uplink Control Channel (PUCCH), wherein Control Channel Element (CCE) indexes of the PUCCH transmitting the ACK/NACK signals are determined in consideration of first CCE indexes of the one or more E-PDCCHs and the number of CCEs of a PUCCH determined by a higher layer.
US09584285B2 Multi-point PUCCH attachment
Periodic over-the-air channel state information (CSI) reporting to serving cells and one or more non-serving cells via a control channel multi-point attachment is disclosed. The channel state information report may be transmitted based on information indicating how to transmit the channel state information report to the non-serving cell. The information indicating how to transmit the channel state information report may be provided by the serving eNodeB. The information may include a periodicity, offset parameters, timing advance commands, power control commands, and/or an aperiodic report request.
US09584282B2 HARQ method and apparatus for communication system
Methods and apparatuses are provided for data transmission of a User Equipment (UE) in a communication system supporting HARQ. A Physical Downlink Control Channel (PDCCH) corresponding to a second cell is received in a first cell. An Uplink/Downlink (UL/DL) configuration of the first cell is identified as an Uplink (UL) reference UL/DL configuration, if the UE is configured with at least two cells including the first cell and the second cell, a PDCCH corresponding to the second cell is monitored on the first cell, and a pair of the UL/DL configuration of the first cell and a UL/DL configuration of the second cell is a predetermined set. A Physical Uplink Shared Channel (PUSCH) transmission is adjusted based on the identified UL reference UL/DL configuration.
US09584279B2 Pilot signal configuration method, associated wireless network node, pilot-signal-based reception method and associated user equipment
The present disclosure discloses a pilot signal configuration method in a wireless communication system and an associated wireless network node. The method comprises allocating a dedicated pilot signal to a User Equipment (UE) within a combined cell. The method further comprises selecting, from all Transmit-Receive Points (TRPs) within the combined cell, at least one TRP in the proximity of the UE for transmission of the dedicated pilot signal to the UE. The present disclosure further provides a pilot-signal-based reception method in a wireless communication network and an associated UE.
US09584276B2 Method and apparatus for receiving downlink signal in wireless communication system
The present invention relates to a method for a first transmission point to transmit a downlink signal to a terminal in a wireless communication system, including a step of mapping a physical downlink shared channel (PDSCH) to resource elements (REs) in a first area, with the exception of an RE corresponding to a cell-specific reference signal (CRS) of a second transmission point from among the REs available for the PDSCH, and further including a step of, when the terminal is a second type of terminal, mapping the PDSCH to REs in a second area corresponding to the CRS of the second transmission point.
US09584275B2 Method and apparatus for generating an uplink reference signal sequence in a wireless communication system
A method of receiving, by a base station, a reference signal in a wireless communication system. The method includes transmitting a cell-specific sequence group hopping parameter to a plurality of user equipments (UEs) in a cell. The cell-specific sequence group hopping parameter is used to enable a sequence group hopping for the plurality of UEs in the cell. The method further includes transmitting a UE-specific sequence group hopping parameter to a certain UE, among the plurality of UEs. The UE-specific sequence group hopping parameter is used to disable the sequence group hopping, enabled by the cell-specific SGH parameter, for the certain UE. The method further includes receiving a reference signal, which is generated based on a sequence group number, from the certain UE. The sequence group number is determined by the UE-specific sequence group hopping parameter.
US09584267B2 Method and apparatus of controlling downlink HARQ timing
The present disclosure relates to an apparatus and method for controlling a downlink (DL) Hybrid Automatic Repeat reQuest (HARQ) timing in a system supporting a TDD-FDD joint operation and an FDD-TDD joint operation environment. A base station transmits a PDSCH and a UE transmits an HARQ response in response to the PDSCH. In the TDD-FDD joint operation, the interval between the PDSCH transmission and the HARQ response may be determined based on an FDD mode configuration when the PDSCH is transmitted through a TDD-based primary serving cell.
US09584264B2 Radio communication apparatus and radio communication method
Provided is a radio communication device which can make Acknowledgement (ACK) reception quality and Negative Acknowledgement (NACK) reception quality to be equal to each other. The device includes: a scrambling unit (214) which multiplies a response signal after modulated, by a scrambling code “1” or “e−j(π/2)” so as to rotate a constellation for each of response signals on a cyclic shift axis; a spread unit (215) which performs a primary spread of the response signal by using a Zero Auto Correlation (ZAC) sequence set by a control unit (209); and a spread unit (218) which performs a secondary spread of the response signal after subjected to the primary spread, by using a block-wise spread code sequence set by the control unit (209).
US09584262B2 Method and apparatus for variable header repetition in a wireless OFDM network with multiple overlapped frequency bands
Method and apparatus for use within a wireless OFDM network that transmits and receives first and second packets each having header bits and utilizing variable header repetition. The header bits in the first packet are communicated on multiple OFDM symbols and repeated on a plurality of OFDM subcarriers in a first frequency band. The header bits in a second packet are communicated on fewer OFDM symbols and in a second frequency band that overlaps with and is wider than the first frequency band.
US09584255B1 Method and apparatus for transmitting and receiving packets in a wireless communication network
A first network device including a medium access control module and a physical layer module. The medium access control module is configured to generate a frame to include a first header, a second header and a payload. The first header indicates a start of the frame for a second network device. The second header indicates a length of the payload for the second network device. The payload comprises a third header and data. Other than the payload, a format of the frame complies with IEEE 802.15.4. The physical layer module is configured to: receive the frame; repetition code the third header or repetition code the data; generate a signal including (i) the first header, (ii) the second header, and (iii) the repetition coded third header or the repetition coded data; modulate the signal; and transmit the modulated signal to the second network device.
US09584254B2 Data transmission method and device for reducing loss of information bits
The present invention provides a method and a device for data transmission. The method includes: according to a preconfigured second table, selecting a TBS value, where the second table is used for describing a corresponding relationship among a TBS value, the number of RBs and a TBS index, the number of RBs corresponding to the selected TBS value is smaller than or equal to a specific value, a modulation mode corresponding to a TBS index which corresponds to the selected TBS value is QPSK, and the selected TBS value is capable of satisfying the rate requirement required during transmission time interval TTI bundling transmission; and according to the selected TBS value, transmitting data carried by a PUSCH using bundled TTIs. The embodiments of the present invention can improve the coverage at a PUSCH medium data rate.
US09584251B2 System and method for classifying signal modulations
A method for pre-processing a signal prior to classification, where the signal includes non-contiguous segments; the method includes applying a coarse carrier frequency offset correction, applying a phase correction, applying a residual course frequency offset correction, and outputting a simulated continuous signal consisting of recorded continuous signal segments and modeled non-contiguous segments. A system for implementing the method is also disclosed.
US09584250B2 Symbol timing estimation for coherent polarization multiplex optical receivers
A received POLMUX signal is rotated by fixed rotation parameters (Rot0, Rot1, Rot2) and the rotated POLMUX signal with optimal signal performance is selected and phase information is derived from both polarities. A pre-filter improves the timing accuracy.
US09584246B2 Wavelength division multiplexing optical receiver
The present invention relates to a wavelength division multiplexing optical receiver and eliminates excess loss of one polarization component while eliminating the need for a polarization-independent operation of a light receiver. An input waveguide, made of a silicon wire waveguide, is connected to a loop waveguide equipped with a polarization rotator over a polarization beam splitter. A ring waveguide equipped with an output waveguide configuring an add-drop ring resonator array is optically connected to the loop waveguide. The output light from ports at both sides of the output waveguide is incident onto first and second light-receiving surfaces of a light receiver such that the optical distances are equal to each other.
US09584231B2 Integrated two dimensional active antenna array communication system
A base station (BS) capable of communication with a number of transmission points includes a processor configured to control a beamforming transmission or reception and an integrated antenna array system. The integrated antenna array system includes a baseband signal processing unit configured to perform baseband functions and disposed between the two sections. The integrated antenna array system also includes a plurality of physical antenna elements disposed in groups. Each of the groups includes an equal number of the plurality of physical antenna elements. The plurality of physical antenna elements are disposed symmetrically around the baseband signal processing unit.
US09584230B2 Technique for monitoring and managing output power
An apparatus is disclosed configured for receiving a first alternating signal and for transmitting a second alternating signal. A detector is configured to receive a third alternating signal which is a reflection of at least a portion in power of the second alternating signal. The detector is further configured to convert the third alternating signal into a rectified signal and measure the power of said rectified signal. The measured power of the rectified signal is indicative of a power of the reflected third signal.
US09584229B2 Data retransmission method, apparatus, and system
A data retransmission method, apparatus, and system can improve a success ratio of data packet retransmission. A data retransmission method includes: after a source node continuously transmits at least two data packets to a destination node according to a go-back-N automatic repeat request, monitoring and decoding, by a relay node, the at least two data packets; storing a copy of a successfully decoded data packet; monitoring a response message to each data packet, where the response message is returned by the destination node to the source node; and sending a copy of a data packet that corresponds to a reception negative acknowledgment message to the destination node, when the monitored response message is the reception negative acknowledgment message.
US09584227B2 Low-power mode signal bridge for optical media
System, methods and apparatus are described that facilitate transmission of data between two devices. A data transfer method includes receiving first data from a first interface, the first data being received in signaling transmitted by a first device according to a first protocol, determining a mode of operation for a communication link to be used for transmitting the first data to a second device, transmitting the first data to the second device over an optical path of the communication link in a first mode of operation, transmitting the first data in accordance with the first protocol to the second device over an electrical path of the communication link in a second mode of operation, and in a third mode of operation, translating the first data to obtain second data, and transmitting the second data in accordance with a second protocol to the second device over the electrical path.
US09584225B2 Realizing coarse wavelength-division multiplexing using standard multimode optical fibers
Tuning parameters of individual wavelength channels transmitted over a multimode optical fiber is provided. Characteristics of the multimode optical fiber used for an optical data link within an optical signal transmission system are retrieved. A wavelength channel grid including each central wavelength in a plurality of central wavelengths that corresponds to each particular wavelength channel in a plurality of wavelength channels used to transmit data via optical signals over the multimode optical fiber is determined. A maximum allowable data rate is calculated for each wavelength channel based on the characteristics of the multimode optical fiber at defined channel wavelengths, optical signal transceiver specifications, and data transmission performance requirements for the optical signal transmission system. Operational parameters are assigned to each wavelength channel based on the calculated maximum allowable data rate for each wavelength channel to achieve the data transmission performance requirements for the optical signal transmission system.
US09584224B2 Laser system including optical amplification subsystem providing an amplified laser output
A laser system including a seed laser and an optical amplification subsystem, receiving an output of the seed laser and providing an amplified laser output, the optical amplification subsystem including a first plurality of amplifier assemblies, each of the first plurality of amplifier assemblies including a second plurality of optical amplifiers, and phase control circuitry including phase modulating functionality associated with each of the first plurality of amplifier assemblies.
US09584219B2 Optical test device and systems
Systems, methods, and devices are disclosed for monitoring optical communications between a managed location and a remote location. In particular, an optical signal is transmitted over an optical fiber and passed-through a test device. A portion of the optical signal is filtered from the original optical signal and passed to a monitoring unit. The monitoring unit may instruct one or more switches in the test device to loop the optical signal back toward the managed location. Subsequently, testing and monitoring may be performed at the managed location. The device may provide a test output or may transmit the information to the managed location.
US09584218B2 Method and arrangement for monitoring optical transmission lines
There is proposed a mechanism for monitoring optical fibers (1) in an optical backhaul network that connects nodes (10, 20) of a distributed radio base station system. The nodes carry data streams using the Common Public Radio Interface (CPRI) protocol. The method includes: receiving from at least one node a CPRI alarm indicative of a transmission failure in a CPRI data stream, and triggering fault analysis of an optical fiber identified as carrying the CPRI data stream. Using CPRI alarms that are generated by transmission failures between nodes as a trigger for monitoring the physical fiber carrying the CPRI streams provides a targeted mechanism for determining fiber failures, which had a low response time and thus enables rapid repair of any fault and minimal disruption to the network.
US09584217B2 Determining properties of an optical communications path in an optical communications network
A method of determining properties of an optical communications path between a first optical network node (A) and a second optical network node (B) determines, at the second optical network node (B), a time difference between respective first and second optical test signals received on different wavelengths (λ1, λ2) from the first optical network node. The method also determines, at the second optical network node (B), a real-time chromatic dispersion parameter for each of the wavelengths using a respective coherent receiver at the second optical network node. The method can be used to determine length of the path between the nodes (A, B). The method can be used to determine propagation delay between the nodes (A, B), or asymmetry in propagation delay between the nodes (A, B). Where separate paths are used for forward and reverse transmission directions, measurements can be made of each path.
US09584211B2 Method and apparatus for transmitting uplink signal in wireless communication system
A method and apparatus for transmitting an uplink signal in a wireless communication system are disclosed. A transmission apparatus for receiving an uplink (UL) signal from a user equipment (UE) and transmitting the received UL signal to a base station (BS) in a wireless communication system includes: a plurality of reception antennas configured to receive UL signals from the UE; a radio frequency (RF) repeater configured to amplify and map the received UL signals to at least one transmission antenna; and a plurality of transmission antennas configured to transmit the amplified UL signals to the BS, wherein the RF repeater is configured to select M received UL signals from among a plurality of received UL signals which are received in the plurality of reception antennas, and map the M received UL signals to N transmission antennas from among the plurality of transmission antennas, and the number of the reception antennas (Nrx,REP) is higher than the number of the transmission antennas (Ntx,REP), and N is the number of the transmission antennas which is used to transmit the M received UL signals.
US09584210B2 Relay communication system
A relay communications system is described in which a base station is able to support both Frequency diversity R-PDCCH transmission and Frequency selective R-PDCCH transmission either within different cells, or within the same cell but not the same sub-frame or within the same cell and within the same sub-frame.
US09584201B2 SU-MIMO, MU-MIMO and beamforming operations using synchronized WLAN devices
An apparatus for wireless communication includes a plurality of antennas, a master baseband integrated circuit (BBIC) and a slave BBIC. The antennas are configured to communicate a Multiple-Input Multiple-Output (MIMO) signal. The master BBIC is configured to process a first component of the MIMO signal that is communicated via a first subset of the antennas. The slave BBIC is configured to process a second component of the MIMO signal that is communicated via a second subset of the antennas. The master BBIC is further configured to control the slave BBIC so as to jointly communicate the MIMO signal, based on the first and second components, via the entire plurality of the antennas.
US09584198B1 Reciprocity calibration for multiple-input multiple-output systems
Systems and associated methods for reciprocity calibration of multiple-input multiple-output (MIMO) wireless communication are disclosed herein. In one embodiment, a method for reciprocity calibration of the MIMO system includes transmitting a pilot symbol by a transmitter (TX) of the reference antenna and receiving the pilot symbol by receivers (RXes) of antennas of a base station as ri,0 pilot symbols. (Index “i” denotes individual antenna “i” of the base station, and “0” denotes the reference antenna.) The method further includes transmitting the received pilot symbols by TXes of the antennas of the base station, receiving the pilot symbols transmitted by the antennas of the base station by the reference antenna as r0,i pilot symbols, and calculating non-reciprocity compensation factors as r i , 0 r 0 , i .
US09584197B2 Methods and apparatus for overlapping MIMO physical sectors
A system is provided comprising: a first wireless cell transmission point with a multiple-input-multiple-output (MIMO) capability; a second wireless cell transmission point with a MIMO capability; and third circuitry in communication with first circuitry of the first wireless cell transmission point and second circuitry of the second wireless cell transmission point. The system is configured such that the first wireless cell transmission point cooperates with the second wireless cell transmission point in connection with a first transmission to a first MIMO-capable portable wireless device, for improving the first transmission. The system is further configured for: receiving first information from the first MIMO-capable portable wireless device; receiving second information from the first MIMO-capable portable wireless device; altering at least one aspect of the first transmission; and transmitting data in connection with the first transmission to the first MIMO-capable portable wireless device.
US09584196B2 Transmission apparatus and method, and reception apparatus and method
Modulated signal A is transmitted from a first antenna, and modulated signal B is transmitted from a second antenna. As modulated signal B, modulated symbols S2(i) and S2(i+1) obtained from different data are transmitted at time i and time i+1 respectively. In contrast, as modulated signal A, modulated symbols S1(i) and S1(i)′ obtained by changing the signal point arrangement of the same data are transmitted at time i and time i+1 respectively. As a result the reception quality can be changed intentionally at time i and time i+1, and therefore using the demodulation result of modulated signal A of a time when the reception quality is good enables both modulated signals A and B to be demodulated with good error rate performances.
US09584191B2 Antenna tuning unit
A system, apparatus, and method directed to impedance matching an antenna with a transmitter for non-directional radio beacons. The apparatus includes an L-type impedance network comprising non-capacitive elements and at least one variable inductor on each branch of the impedance network. Also, system, apparatus, and method directed to providing a low power signal for tuning the antenna. The apparatus includes an impedance matching network and a signal generator. Also, a system, apparatus, and method directed to providing an estimate of near-field strength of a signal from an antenna. The apparatus includes an impedance matching network, a near-field signal strength detector, and microcontroller configured to estimate the near-field signal strength. Corresponding systems includes using the respective apparatuses between an antenna and a transmitter. Corresponding methods are directed to the use of the apparatuses and systems.
US09584190B2 Vehicle driving system having wireless power transmission function and method thereof
A vehicle driving system having a wireless power transmission function includes a driving controller configured to generate a high frequency AC voltage corresponding to a device by using a DC voltage applied from a battery within a vehicle and generate a magnetic field by applying the generated high frequency AC voltage to a primary coil. A smoother is configured to smooth an AC voltage induced by a secondary coil into a predetermined level of DC voltage and supply a constant voltage to the device, wherein the device is operated based on the constant voltage supplied from the smoother.
US09584185B2 Relative phase detection in power line communications networks
Systems and methods for relative phase detection and zero crossing detection for power line communications (PLC) are described. In some embodiments, both transmit and receive PLC devices detect a zero crossing on an AC mains phase. The devices start a phase detection counter (PDC) by generating a zero crossing pulse within 5% of the actual zero crossing time. When a frame is transmitted, the transmitting device includes a PDC value in the frame control header (FCH). The PDC value corresponds to the start time of the FCH. When the frame is received at the receive PLC device, the receive PLC device measures a local PDC value between the zero crossing and the start of the FCH. The receive device compares the local PDC value to the PDC value in the FCH of the received frame and determines if the devices are on the same phase.
US09584182B2 Vectored DSL crosstalk cancellation
A vector DSL system includes a plurality of modems, which may be multi-port devices. Unprocessed user data is extracted from the modems and passed through a private vectoring data routing apparatus to one or more vectoring modules, such as vectoring cards. Each vectoring module includes one or more vector processors that include processing units configured to process the unprocessed user data on the basis of all modems' data for a given DSL tone grouping. Processing of the unprocessed user data removes the effects of FEXT from upstream and downstream user data and returns the processed user data to the modems using the vectoring data routing apparatus, which can be a specialized data transmission network utilizing one or more vector routers.
US09584180B1 Networking system and method
A system may include an interface connected to at least one of a plurality of nodes via non-power line wiring not used for Ethernet communications. The system may also include a controller carrying the interface, and the controller uses a broadband over power line protocol to provide Ethernet data communications over the non-power line wiring amongst each of the plurality of nodes.
US09584175B2 Radio frequency transceiver loopback testing
An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (RF) signal at a receiver input of the receiver portion. The transmitter portion is for transmitting an RF signal at a transmitter output of the transmitter portion. The modulated phase locked loop (PLL) is shared between the receiver portion and the transmitter portion. The transmitter output and receiver input are coupled together in a loopback configuration during a test mode. The transmitter portion and the receiver portion are enabled concurrently while a modulated PLL signal is provided to the receiver portion from the transmitter portion via the loopback configuration.
US09584174B1 Active cover for electronic device
Systems and methods of providing a mobile device cover are described. In some embodiments, the mobile device cover may include, for example, an acoustic sensor, a processor, and lighting devices. The processor can be operatively coupled to the acoustic sensor and the lighting devices. The acoustic sensor can be configured to receive sound generated by the mobile phone and to convert the sound into an acoustic signal. The processor can be configured to receive the acoustic signal and to determine whether the acoustic signal is similar to one of a plurality of acoustic signals previously stored on the mobile phone cover. Each of the previously stored acoustic signals can be indicative of, for example, a particular caller, a particular message sender, or a particular alert. Based on the acoustic signal determination, the processor is configured to cause lighting of the one or more lighting devices corresponding to the indicated caller, indicated message sender, or indicated alert.
US09584169B1 High frequency transmitter
A radio transmitter having a RF signal source. A splitter receives an input signal from the signal source and divides that input signal into two output signals. These output signals are fed into two phase shifters. A phase control signal is applied to each phase shifter so that the vector sum of the output signals represents the desired amplitude and phase of the desired transmitted signal. The outputs of both phase shifters are both frequency multiplied and amplified before recombining to form the transmitter output signal.
US09584165B2 High frequency amplifier and method of compensating for distortion
Disclosed is a high frequency amplifier which can properly compensate for distortion generated in a power amplifier even when an observation band of a feedback signal is made narrow. The high frequency amplifier includes a data correction unit that corrects transmission data through a digital pre-distortion method, and the data correction unit includes an orthogonalizer that orthogonalizes and outputs respective order components of a polynomial model for the digital pre-distortion method, and a compensator that compensates for a memory effect of the power amplifier for an output of the orthogonalizer.
US09584162B1 Microcode data recovery strategies for use of iterative decode
Various embodiments for data error recovery in a tape storage system, by a processor device, are provided. In one embodiment, a method comprises, in a tape storage system using an iterative hardware decoder and an iterative microcode decoder, modifying erasure control configuration settings upon rereading a buffered dataset having passed through at least one microcode-initiated iterative decode cycle.
US09584161B2 Transmission device
A transmission device transmitting a polarization-multiplexed optical signal includes: a frame encoder configured to encode an electric signal in accordance with a predetermined frame format; an error correction encoder configured to provide encoded signal data as a result of the encoding by the frame encoder with a predetermined error correction code; and a transmission loss information acquiring part configured to acquire transmission loss information based on a loss that the encoded signal data provided with the error correction code incurs when the encoded signal data is transmitted, from a receiving device as a transmission destination. The error correction encoder adjusts a redundancy of the error correction code given to the encoded signal data, based on the transmission loss information acquired by the transmission loss information acquiring part.
US09584160B2 Dynamically configuring erasure code redundancy and distribution
Example apparatus and methods monitor conditions in a tiered storage system. The conditions monitored may include the availability of different numbers and types of devices including an erasure code based object storage system. The conditions monitored may also include the availability and type of devices available to the erasure code based object storage system. A redundancy policy for storing an item using the erasure code based object storage system may be determined based on the conditions. Erasure codes associated with the item may then be stored in the erasure code based object storage system as controlled, at least in part, by the redundancy policy. The redundancy policy for the erasure codes may be updated dynamically in response to changing conditions on the tiered storage system.
US09584157B2 Coding method, decoding method, coder, and decoder
An encoding method of generating an encoded sequence by performing encoding of a given encoding rate based on a predetermined parity check matrix. The predetermined matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. A parity check polynomial satisfying zero of the LDPC convolutional code is expressible by using a specific mathematical expression.
US09584156B1 Creating a dynamic Huffman table
Techniques for creating a dynamic Huffman table in hardware are provided. In one aspect, a method for encoding data includes the steps of: implementing dynamic Huffman tables in hardware representing a plurality of Huffman tree shapes precomputed from a sample data set, wherein the Huffman tree shapes are represented in the dynamic Huffman tables by code length values; upon receipt of input data, writing symbols and their counts from the input data to the dynamic Huffman tables; calculating a score for each of the dynamic Huffman tables with the symbols and counts from the input data, wherein the score is based on the code length values of the precomputed Huffman tree shapes and the counts from the input data and selecting a given one of the dynamic Huffman tables having a lowest score for encoding the input data. A process for implementing the present techniques in SRAM is also provided.
US09584153B2 Efficient dithering technique for sigma-delta analog-to-digital converters
A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N−1 level quantizer function.
US09584146B2 System and method for measuring the DC-transfer characteristic of an analog-to-digital converter
Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.
US09584145B1 Circuit for and method of compensating for mismatch in a time-interleaved analog-to-digital converter
A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter is described. The circuit comprises an analog-to-digital converter circuit of a first channel of the plurality of channels configured to receive an analog input signal and to generate a digital value associated with the analog input signal; an arithmetic circuit configured to receive the digital value generated at the output of the analog-to-digital converter; a memory element configured to receive an output of the arithmetic circuit; and an accumulator circuit coupled to the memory element, wherein the accumulator generates an average value that is provided to the arithmetic circuit to modify the digital value generated at the output of the analog-to-digital converter while receiving the analog input signal.
US09584144B1 Asynchronous clock generation for time-interleaved successive approximation analog to digital converters
A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.
US09584139B2 Phase tracker for a phase locked loop
A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.
US09584138B2 Phase locked loop with accurate alignment among output clocks
A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
US09584136B1 Method and apparatus for synchronization
Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.
US09584132B2 Clock generator with stability during PVT variations and on-chip oscillator having the same
Provided is a clock generator that includes a comparator in which characteristics of two input signals vary over time. A voltage controller, having a resistor and at least one constant current source, generates a direct current (DC) voltage proportional to an output current of the constant current source and a resistance value of the resistor. The comparator compares a ramp voltage generated by the voltage controller with the DC voltage.
US09584127B2 Inverter, driving circuit and display panel
An inverter includes first, second, third, fourth, and fifth transistors, and first and second capacitors. The transistors and capacitors are connected in such way that the reverse conduction of the second transistor is prevented through controlling the gate electrode of the second transistor and maintaining the electrical potential at the gate electrode of the fifth transistor by the second capacitor. The electrical potential at the gate electrode of the fifth transistor is maintained stable when a first clock signal changes from high to low (when the first to fifth transistors are NMOS transistors) or from low to high (when the first to fifth transistors are PMOS transistors), so that the output signal of the inverter may not be affected by a change of the first clock signal, thus enabling the inverter to generate a stable output signal and a display panel comprising the inverter to obtain a better display effect.
US09584122B1 Integrated circuit power reduction through charge
Techniques for charge reuse in an integrated circuit. A processor may include a first logic circuit coupled to a source power supply node, a second logic circuit coupled to a destination power supply node, and a charge reuse circuit that selectively transfers charge from the first logic circuit to the second logic circuit. The charge reuse circuit may include an equalization device that selectively couples the source power supply node to the destination power supply node, and an equalization activation circuit that activates the equalization device in response to detecting assertion of an equalization control signal and further detecting that a voltage differential between the source power supply node and the destination power supply node is above a threshold value. The equalization activation circuit also prevents coupling of either the source power supply node or the destination power supply node to ground during activation of the equalization device.
US09584119B2 Triac or bypass circuit and MOSFET power steal combination
A power supply unit for use with thermostats or other like devices requiring power. A power supply unit may be designed to keep electromagnetic interference emissions at a minimum, particularly at a level that does not violate governmental regulations. A unit may be designed so that there is enough power for a triggering a switch at about a cross over point of a waveform of input power to the unit. Power for triggering may come from a storage source rather than line power to reduce emissions on the power line. Power for the storage source may be provided with power stealing. Power stealing may require switching transistors which can generate emissions. Gate signals to the transistors may be especially shaped to keep emissions from transistor switching at a minimum.
US09584118B1 Substrate bias circuit and method for biasing a substrate
A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.
US09584117B1 Hybrid resonant driver for sic MOSFET
A method including activating a biasing current source which provides a biasing current flowing through a biasing inductor electromagnetically coupled to a resonant inductor; waiting for the resonant inductor to reach a state of saturation; activating a voltage supply for applying a source voltage across a first and a second transistor connected serially, the resonant inductor being connected to a node between the first and second transistors and a driving gate of a driving transistor; determining a first control voltage for applying to a first gate of the first transistor and a second control voltage for applying to a second gate of the second transistor; and applying the first and the second control voltage to the first and the second gate, respectively, the application of the first and the second control voltage sending a current to the driving gate via the resonant inductor activating the driving transistor.
US09584113B2 Arrangement and method for a power semiconductor switch
An exemplary arrangement and method for a power semiconductor switch, where a first current between a first electrode and a second electrode can be controlled based on a control voltage between a third electrode and the first electrode. The arrangement includes an inductance connected in series with the power semiconductor switch, wherein a first end of the inductance is connected to the first electrode, first measuring source for generating a first measurement voltage based on the first end's voltage with respect to a reference potential, second measuring source for generating a second measurement voltage on the basis of the inductance's second end voltage with respect to the reference potential, a comparator for comparing the first measurement voltage with the second measurement voltage, and driver for generating the control voltage. The driver being configured to generate a first control voltage level and a second voltage level of the control voltage.
US09584103B2 Signal potential converter
In a signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential (signal IN) at the terminal node within the range of a first potential to a second potential. The clamp circuit includes a level adjuster circuit configured to adjust at least one of the first and second potentials according to a supply voltage of a circuit that drives the input signal CIN.
US09584102B2 Method and system for generating a ramping signal
A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.
US09584093B2 Vibrating device
A vibrating device having a number 2N (N is an integer equal to 2 or larger) of tuning fork arms extending in a first direction are arranged side by side in a second direction. Phases of flexural vibrations of the number N of tuning fork arms positioned at a first side of an imaginary line A, which passes a center of a region in the second direction where the number 2N of tuning fork arms are disposed and which extends in the first direction, are symmetric to phases of flexural vibrations of the number N of tuning fork arms positioned at a second side of the imaginary line opposite the first side.
US09584083B2 Loudness modification of multichannel audio signals
Scaling, by a desired amount sm, the overall perceived loudness Lm of a multichannel audio signal, wherein perceived loudness is a nonlinear function of signal power P, by scaling the perceived loudness of each individual channel Lc by an amount substantially equal to the desired amount of scaling of the overall perceived loudness of all channels sm, subject to accuracy in calculations and the desired accuracy of the overall perceived loudness scaling sm. The perceived loudness of each individual channel may be scaled by changing the gain of each individual channel, wherein gain is a scaling of a channel's power. Optionally, in addition, the loudness scaling applied to each channel may be modified so as to reduce the difference between the actual overall loudness scaling and the desired amount of overall loudness scaling.
US09584081B2 Signal processing apparatus and method, program, and data recording medium
The present invention relates to a signal processing apparatus and method, a program, and a data recording medium configured such that the playback level of an audio signal can be easily and effectively enhanced without requiring prior analysis. An analyzer 21 generates mapping control information in the form of the root mean square of samples in a given segment of a supplied audio signal. A mapping processor 22 takes a nonlinear function determined by the mapping control information taken as a mapping function, and conducts amplitude conversion on a supplied audio signal using the mapping function. In this way, by conducting amplitude conversion of an audio signal using a nonlinear function that changes according to the characteristics in respective segments of an audio signal, the playback level of an audio signal can be easily and effectively enhanced without requiring prior analysis. The present invention may be applied to portable playback apparatus.
US09584078B2 Apparatus and methods for radio frequency amplifiers
Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.
US09584077B2 Impedance synthesis for optimum frequency response of a radio frequency (RF) amplifier
A method and system of synthesizing impedance in a radio frequency (RF) amplifier includes receiving a voltage signal at a passive mixer. The passive mixer down-converts the voltage signal into a baseband frequency. The method includes converting the voltage signal into a digital signal. Further, the method includes performing convolution of the digital signal with an impulse response. The impulse response is of a low Q impedance and is programmable. Furthermore the method includes generating a current signal based on output of the convolution. Furthermore the method includes performing up-conversion of the current signal in the passive mixer. The passive mixer performs impedance transformation of the low Q impedance. Moreover, the method includes providing the current signal via the passive mixer to synthesize desired impedance in the RF amplifier, thereby controlling frequency response of the RF amplifier.
US09584076B2 Output matching network for differential power amplifier
An output matching network for a differential power amplifier comprises an output transformer having a center tap and a low pass filter. The output transformer is configured to receive a first amplified signal from a first differential output stage amplifier of the differential power amplifier and provide a first output signal to the low pass filter. The output transformer is also configured to receive a second amplified signal from a second differential output stage amplifier of the differential power amplifier and provide a second output signal to the low pass filter. The low pass filter is configured to receive the first and second output signal from the output transformer and provide a filtered output signal.
US09584073B1 Internally matched active single-to-differential RF converter
A single-to-differential converter and a method of fabricating the single-to-differential converter on an integrated circuit are described. The single-to-differential converter provides a pair of differential outputs based on a single-ended input and includes an input node to receive the single-ended input, and a first transistor connected to a power supply pin. A second transistor is connected to the power supply pin. The first transistor and the second transistor are biased under a same amount of direct current (DC) and the pair of differential outputs are generated at respective collectors of the first transistor and the second transistor.
US09584071B2 Envelope tracking with reduced dynamic range
Envelope power supply circuitry includes power converter circuitry and envelope tracking circuitry. The power converter circuitry is configured to receive an envelope power converter control signal and a supply voltage and provide an envelope power supply signal for an amplifier from the supply voltage and based on the envelope power converter control signal. The envelope tracking circuitry is coupled to the power converter circuitry. In a first mode of operation, the envelope tracking circuitry is configured to provide the envelope power converter control signal such that a gain of the amplifier remains substantially constant over a range of input power provided to the amplifier. In a second mode of operation, the envelope tracking circuitry is configured to limit the dynamic range of the envelope power supply signal.
US09584070B2 Apparatus and methods for envelope trackers
Apparatus and methods for envelope tracking are disclosed. In one embodiment, a power amplifier system including a power amplifier and an envelope tracker is provided. The power amplifier is configured to amplify a radio frequency (RF) signal, and the envelope tracker is configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker includes a buck converter for generating a buck voltage from a battery voltage and a digital-to-analog conversion (DAC) module for adjusting the buck voltage based on the envelope of the RF signal to generate the supply voltage for the power amplifier.
US09584069B1 Body driven power amplifier linearization
Embodiments include an apparatus, system, and method related to a body driven field effect transistor (FET). In embodiments, a body terminal of the FET may be electrically coupled with a source terminal of a second FET, and a drain terminal of the FET may be electrically coupled with a drain terminal of the second FET. Other embodiments may be described.
US09584067B2 Circuits and methods for increasing output frequency of an LC oscillator
Disclosed are circuits and methods for increasing an output frequency of an inductance-capacitance (LC) oscillator. In some embodiments, the LC oscillator can be implemented as a voltage-controlled oscillator (VCO) having differential outputs. When the VCO is implemented on a die, wirebond connections from the outputs to a ground results in an effective inductance that impacts a maximum frequency associated with the VCO. An electrical connection such as a wirebond between the differential outputs yields a reduction in the effective inductance thereby increasing the maximum frequency. In some embodiments, the wirebond between the differential outputs can be configured so that its contribution to mutual inductance is reduced or substantially nil.
US09584065B2 Solar cell structure
The invention relates to a solar cell structure (10) having at least one transparent photovoltaic cell (42), in particular having a dye solar cell or a thin-film semiconductor cell. It comprises at least one polymer layer (36) which is provided with a fluorescent material, or a mixture of a plurality of fluorescent materials, and covers the at least one transparent photovoltaic cell (42).
US09584061B1 Electric drive systems including smoothing capacitor cooling devices and systems
An electric drive system includes a smoothing capacitor including at least one terminal, a bus bar electrically coupled to the at least one terminal, a thermoelectric device including a first side and a second side positioned opposite the first side, where the first side is thermally coupled to at least one of the at least one terminal and the bus bar, and a cooling element thermally coupled to the second side of the thermoelectric device, where the cooling element dissipates heat from the thermoelectric device.
US09584057B2 Control device and method for improving voltage utilization ratio of inverter for green car
A control device and a control method can improve a voltage utilization ratio of an inverter for a green car, in which an input DC voltage of the inverter is modulated by a maximum amount into an output AC voltage of the inverter by changing the output AC voltage incapable of being linearly output into a voltage capable of being linearly output. The control method includes steps of: generating a two-phase current command having two phases of a first current command and a second current command; generating a two-phase voltage command having two phases of a first voltage command and a second voltage command; generating a three-phase pole voltage command; modulating the three-phase pole voltage command into a linear output voltage capable of being linearly output; and calculating a voltage gain value, using the two-phase voltage command and an input DC voltage of the inverter.
US09584056B2 Polyphasic multi-coil generator
A polyphasic multi-coil generator includes a driveshaft, at least first and second rotors rigidly mounted on the driveshaft so as to simultaneously synchronously rotate with rotation of the driveshaft, and at least one stator sandwiched between the first and second rotors. The stator has an aperture through which the driveshaft is rotatably journalled. A stator array on the stator has an equally circumferentially spaced-apart array of electrically conductive coils mounted to the stator in a first angular orientation about the driveshaft. The rotors and the stator lie in substantially parallel planes. The first and second rotors have, respectively, first and second rotor arrays.
US09584055B2 Voltage regulator system for a genset
A voltage regulator system for regulating an output voltage of a genset includes a voltage regulator for reducing terminal voltage in response to a reduction in terminal frequency. A plurality of under-frequency roll-off (UFRO) states is provided in the voltage regulator, with each UFRO state being configured to implement a UFRO characteristic. An operational signal indicative of an operating condition of the genset forms the basis for selection of the UFRO characteristic.
US09584050B2 Motor drive device and brushless motor equipped with same, and air conditioner
A motor drive device of the present invention includes a speed signal generator that generates a rotation speed signal indicating rotation speed; a PWM signal generator that acts on the power switch unit to control the power switch unit so as to generate coil-applied voltage; and a phase advance information generator that has characteristic curve information representing changes of rotation speed of and load on a brushless motor, preliminarily set. The phase advance information generator generates phase advance information according to the load characteristic curve to variably control the phase advance (the phase of voltage applied to the coils of the brushless motor, relative to the induced voltage phase) according to the load characteristic curve.
US09584048B2 Electroactive elastomer converter
An electroactive elastomer converter is described comprising at least one electroactive elastomer layer (3) with a top side and underside and an electrically conductive electrode body (1′) that is two-dimensionally connected to the top side at least in regions. An electrically conductive electrode body (1′) is dimensionally connected in at least two regions to the underside. At least one electrode body (1′) in each case has an electrode surface facing the elastomer layer (3). At least one opening (2) is present to which an a two-dimensional region in which there is no two-dimensional bond between the elastomer layer (3) and the electrode body (1′). A compressible medium is provided in the area of the opening.
US09584045B2 Converter controller with half bridge adaptive dead time circuit and method
The present disclosure relates to a controller, a circuit and method for controlling a power converter using pulse width modulation (PWM). At least one logic block (13, 15, 16) of the controller is configured to remove a command (4) which is configured to control the other power semiconductor switch (2) in a half-bridge (1,2) so that the other power semiconductor switch (2) remains in a non-conductive state while an antiparallel diode (6) allows an electric current (5) to pass in one direction, called the diode's forward direction, while blocking current in the opposite direction. In case the diode (6) is conducting instead of the other power semiconductor switch during the duration of the state of the command, the switching command (4) for the latter is omitted. The controller is further configured to modify the dead time interval (Tdead) between switching from the power semiconductor switch (3) to another power semiconductor switch (4) or vice versa in order to avoid a discontinuity in the transfer function (25).
US09584044B2 Technologies for converter topologies
In some embodiments of the disclosed inverter topologies, an inverter may include a full bridge LLC resonant converter, a first boost converter, and a second boost converter. In such embodiments, the first and second boost converters operate in an interleaved manner. In other disclosed embodiments, the inverter may include a half-bridge inverter circuit, a resonant circuit, a capacitor divider circuit, and a transformer.
US09584042B2 Method for driving inverters, and inverter adapted to reduce switching losses
A method for controlling the switching of an inverter, a bridge of which is adapted to chop a voltage from a direct voltage source for feeding a chopped voltage to a primary of a transformer; the inverter comprises a diode rectifier circuit receiving the input voltage from the secondary of the transformer in order to achieve a voltage fed to a chopper which feeds a load. The method comprises: a step in which the switches of the bridge are driven so that the power source is disconnected from the primary, the terminals of which are connected to each other by at least two of the electronic switches and recirculation diodes of the bridge itself, so that the voltage present on the secondary of said transformer is null; a step in which the switching of at least one electronic switch of a chopper branch is achieved when the voltage on the secondary is substantially null in order to minimize switching losses due to the opening/closing of the electronic switch of the chopper.
US09584039B2 Regulated AC-DC hybrid rectifier
A regulated hybrid AC-DC rectifier employing a boost stage is disclosed herein. The regulated hybrid AC-DC rectifier comprises a 12 pulse inductive current splitter/merger (CSM) system coupled to a boost stage. The boost stage may be regulated using a PWM controller. The regulated hybrid AC-DC rectifier may further include a three phase input filter configured to regulate the harmonic content of the AC-DC hybrid converter within a desired limit. The regulated hybrid AC-DC rectifier may further comprise a notch filter system configured to tune out harmonic ripples at known intervals, such as 11th and 13th order harmonics.
US09584036B2 Solar photovoltaic power conditioning units
We describe a photovoltaic power conditioning unit comprising: both dc and ac power inputs; a dc link; at least one dc-to-dc converter coupled between dc input and dc link; and a dc-to-ac converter coupled between dc link and ac output. The dc-to-dc converter comprises: a transformer having input and output windings; an input dc-to-ac converter coupled between dc input and input winding; and an ac-to-dc converter coupled between output winding the dc link. The output winding has a winding tap between the first and second portions. The ac-to-dc converter comprises: first and second rectifiers, each connected to a respective first and second portion of the output winding, to the dc link and winding tap; and a series inductor connected to the winding tap. Rectifiers are connected to the winding tap of the output winding via the series inductor wherein the series inductor is shared between the first and second rectifiers.
US09584034B2 Power converter circuit and method with asymmetrical half bridge
A power converter circuit includes a power converter with a plurality of series connected converter cells. Each of the plurality of converter cells includes at least one first half-bridge circuit including a first silicon MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) and a second silicon MOSFET. At least one of the plurality of converter cells is configured to operate in a continuous current mode.
US09584030B2 Controller for eliminating acoustic noise of a power converter and related method thereof
A controller for eliminating acoustic noise of a power converter includes a control unit and a gate signal generation unit. The control unit is used for detecting a frequency corresponding to a gate control signal in a burst mode of the power converter. When the frequency is greater than a predetermined frequency, the control unit increases a resistance of a compensation resistor coupled to a compensation pin of the power converter; and when the frequency is less than the predetermined frequency, the control unit decreases the resistance of the compensation resistor. The gate signal generation unit is coupled to the control unit for generating the gate control signal to a power switch of a primary side of the power converter according to the resistance of the compensation resistor. The power switch is turned on according to the gate control signal.
US09584025B2 Systems and methods for flyback power converters with switching frequency and peak current adjustments based on changes in feedback signals
System and method for regulating a power converter. The system includes a first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based on at least information associated with the first input signal and the second input signal, a pulse-width-modulation generator configured to receive at least the first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal, a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter, and a voltage-change-rate detection component configured to sample the feedback signal to generate a first sampled signal for a first modulation period and to sample the feedback signal to generate a second sampled signal for a second modulation period.
US09584022B1 System and method for a switched-mode power supply
In accordance with an embodiment, a method includes receiving an indication of a changed load condition or voltage characteristic of a power supply providing power to a load via an output port of the power supply in a first mode, and switching regulation of the power supply from sourcing a current to the load in the first mode to sinking the current from the load in a second mode in response to receiving the indication of the changed load condition or voltage characteristic. Sinking the current from the load in the second mode includes controlling the power supply to transfer energy from the output port of the power supply to an input port of the power supply.
US09584019B2 Switching regulator and control method thereof
A switching regulator including an output switch element; a rectification switch element; an oscillation circuit; an error amplifier circuit; a slope circuit; a first voltage comparison circuit; a second voltage comparison circuit; a one pulse generation circuit; a control circuit; and a backflow detection circuit, and a control method thereof suppress variations to be stabilized with respect to a target value of the load current for switching between a PWM control and a PFM control, and ensure the switching from the PFM control to the PWM control or from the PWM control to the PFM control even if various parameters including external elements such as chips, coils, and capacitors vary.
US09584015B2 Determination of phase offsets in a power supply system having multiple switching converters
A controller (500) for determining a distribution of switching phases among switching elements of a power supply system The power supply system has a plurality of voltage converters, each comprising a switching element and being arranged to convert an input voltage supplied to the voltage converters to a respective output voltage by switching the switching element at a predetermined frequency. The controller (500) comprises a receiver (510) for receiving one or more signals indicative of a respective contribution from each of the voltage converters to a ripple current component of an input current of the voltage converters, and a rank determining module (520) configured to rank the voltage converters in order of decreasing contribution to the ripple current. The controller (500) further comprises a switching phase offset calculator (530) configured to calculate a respective switching phase offset that is to be applied for the switching element in each of the voltage converters by: (i) calculating respective phase offsets of the two highest ranked voltage converters that would minimize an input current ripple caused only by said two highest ranked voltage converters; (ii) calculating a phase offset of the next-highest ranked voltage converter that would minimize an input current ripple caused only by said next-highest ranked voltage converter and the voltage converters ranked higher than said next-highest voltage converter; and (iii) repeating step (ii) for each subsequent voltage converter in the ranking. The controller (500) also includes an output signal generator (540) configured to generate one or more output signals defining the calculated switching phase offsets to be applied to the switching of the respective switching elements.
US09584014B2 DC-DC converter
According to one embodiment, a DC-DC converter includes a comparator circuit that compares a feedback voltage of an output voltage with a reference voltage and a control circuit that controls an output voltage based on an output signal of the comparator circuit. The comparator circuit performs a discrete-time operation in response to a clock signal, and a frequency of the clock signal is adjusted according to a load condition.
US09584011B1 Capacitive coupled input transfer gates
According to one embodiment, an apparatus is for use with a remote circuit. The apparatus has a first input for receiving an input voltage, a second input for receiving a power supply voltage, and a third input for receiving an input clock having a high state corresponding to the power supply voltage and a low state corresponding to a return for the power supply voltage. The apparatus includes a first shift circuit coupled to the first input and the third input, and configured to output a first output clock, the first output clock having a low state corresponding to the input voltage. The apparatus further includes a second shift circuit coupled to the first input and the first shift circuit, and configured to output a second output clock, the second output clock having a high state corresponding to the input voltage.
US09584010B2 Power supply apparatus
A power supply apparatus includes a transformer which has a primary coil and a secondary coil, a primary side semiconductor component which configures a primary side circuit connected to a side of the primary coil of the transformer, a secondary side semiconductor component which configures a secondary side circuit connected to a side of the secondary coil of the transformer, a choke coil which is connected to the secondary side semiconductor component, and a base plate on which the transformer, the primary side semiconductor component, the secondary side semiconductor component, and the choke coil are mounted. Any two of the transformer, the primary side semiconductor component, the secondary side semiconductor component, and the choke coil configure a first stacked body stacked in a normal direction of the base plate, and other two of the transformer, the primary side semiconductor component, the secondary side semiconductor component, and the choke coil configure a second stacked body stacked in the normal direction of the base plate. The power supply apparatus has a pair of first lines connecting the primary side semiconductor component and the transformer to each other, and a pair of second lines connecting the transformer and the secondary side semiconductor component to each other. The first lines and the second lines respectively have a pair of first current paths and a pair of second current paths which are arranged so as to be adjacent to each other and are configured so that currents flow in the normal direction of the base plate. At least one of the pair of the second current paths is adjacent to at least one of the pair of the first current paths in a second direction orthogonal to a first direction in which the pair of the first current paths are adjacent to each other. The first current paths and the second current paths adjacent to each other in the second direction are configured so that currents flow therethrough in directions opposite to each other.
US09584003B2 Energy-harvesting device
A semiconductor device includes a moveable element over a substrate, wherein the moveable element is moveable relative to the substrate. The semiconductor device further includes a first anchor portion connected to the substrate; and a second anchor portion connected to the substrate on an opposite side of the moveable element from the first anchor portion. The semiconductor device further includes a first connector configured to connect the moveable element to the first anchor portion. The semiconductor device further includes a second connector configured to connect the moveable element to the second anchor portion. The semiconductor device further includes a conductive wire loop on the moveable element; and a connection wire electrically connected to a first end of the conductive wire loop, wherein the connection wire extends across the first connector to the first anchor portion.
US09584002B2 Generator including a sliding member made of a biomass-containing material
A generator includes a sliding member, a first power generation element and a second power generation element. The sliding member is made of a biomass-containing material. The first power generation element is configured to slide with respect to the sliding member. The second power generation element is configured to generate electrical power by variation of its relative position with respect to the first power generation element.
US09584000B2 Method and device for torque generation based on electromagnetic effect
A method and device of torque generation based on electromagnetic effect is provided. An electromagnetic torque whose direction is opposite to the motor driving direction is generated in a magnetic field when a motor-drive armature winding is adopted based on the electro-magnetic induction principle. Meanwhile, a reverse electromagnetic torque which is reverse to the armature winding with the same magnitude, is applied on a magnet set and is transmitted to an underactuated system so as to provide required torque for the underactuated system. Advantageously, the provided torque is in direct ratio to speed, difficulty in control is significantly reduced, two-stage electromagnetic variable speed can be achieved, the design of the system is simple and reliable with a concise and clear structure, and the device may be employed in a wide variety of applications.
US09583999B2 Permanent magnet rotating machine
Provided is a technology for enhancing the reliability of a permanent magnet rotating machine against thermal degradation of a permanent magnet. Specifically, provided is a permanent magnet rotating machine comprising a housing which houses a rotation shaft, a rotor connected to the rotation shaft and configured to rotate together with the rotation shaft, a stator, and permanent magnets fastened to the rotor or the stator; an air intake port provided at one end of the housing and an air exhaust port provided at the other end of the housing, the air intake port and the air exhaust port being configured to allow cooling air to flow through the housing; and a blower for feeding the cooling air to the air intake port; wherein the permanent magnet rotating machine is configured to be driven by magnetic force of the permanent magnets, and among the permanent magnets, a permanent magnet in the air exhaust port side has a higher coercivity than a permanent magnet in the air intake port side.
US09583998B2 Method of assembling a rotor for an electric turbo-charger
A rotor assembling method for a turbo-charger may include washing and preparing components of a rotor having a connector, a permanent magnet, end caps, a retention ring, and a center pipe, inserting the connector into the permanent magnet, thermally inserting one or more end caps into the connector by cooling the connector and heating the one or more end caps under a first high-temperature condition for a first predetermined time to form a permanent magnet assembly, thermally inserting the permanent magnet assembly into the retention ring by cooling the permanent magnet assembly and heating the retention ring under a second high-temperature condition for a second predetermined time to form a rotor assembly, thermally inserting the center pipe into the rotor assembly by heating the rotor assembly under a third high-temperature condition for a third predetermined time to form a rotor assembling body, and post processing the rotor assembling body.
US09583997B2 Magnetizer and assembler for electrical machines
The present invention relates to a device for magnetizing and assembling an electrical machine comprising a stator and a rotor with at least one permanent magnet. The device includes a magnetizer unit for magnetizing the at least one permanent magnet of the rotor, a rotor load unit, and a translation unit for translating the rotor from the magnetizer unit to a rotor load unit for inserting the rotor into the stator. The invention also relates to a method for magnetizing and assembling an electrical machine comprising a stator and a rotor with at least one permanent magnet at a magnetizing unit.
US09583996B2 Actuator overspeed guard
A location and retention component is provided for positively locating an overspeed guard and retaining a centrifugal actuator at an optimum positional relationship relative to each other. The system includes a first and second retention element removably engagable to the output shaft of a motor and axially fixable to the shaft at corresponding locations to maintain the optimum positional relationship. The first retention element serves as a positive stop for assembling the overspeed guard on the motor shaft, while the second retention element ensures that the centrifugal actuator is properly placed within the overspeed guard.
US09583992B2 Device and method for controlling an active magnetic bearing
A command procedure for an active magnetic bearing, the magnetic bearing comprising a series of electromagnetic actuators forming a stator, each actuator being suitable for exerting radial force on the rotor, a ferromagnetic body forming a rotor, kept free of contact between the electromagnetic actuators and suitable for being set in rotation around an axis of rotation, the rotor being suitable to undergo precession movements in particular. Sensors suitable for detecting radial displacements of the rotor and issuing position signals representative of the radial position of the rotor in relation to the actuators. Calculation of at least one actuator command signal the calculation of the command signal consisting of the application of at least one transfer function to the position signals, the transfer function containing a number of correction coefficients.
US09583989B2 Electric generator
A simpler to manufacture electrical machine generator or motor designed to be built of 2 dimensionally cut flat stock materials with special utility as a larger than conventional diameter electric generator that is designed to operate at lower revolutions per minute than conventional generators so as to be able to be driven by human legs or arms or wind generation at low wind speeds, or water movement at low or zero water drop distance or ‘head’ or other applications.
US09583988B2 Can of a drive motor for a pump assembly
A can of a drive motor is provided for a pump assembly, wherein the can (22) is manufactured at least partly of plastic (52). At least in a part of the can (22) the plastic (52) is reinforced by individual fibers (32) distributed in the plastic (52). The fibers (32) in at least one layer (35) of the can (32) are aligned in a defined manner in the peripheral direction with respect to the longitudinal axis (Z) of the can (22). A method for manufacturing such a can is also provided.
US09583985B2 DC commutator motor and automobile including the same
A DC commutator motor includes a yoke, a field magnet, and an armature. A shaft is positioned on a central axis of the armature. A plurality of commutator segments is positioned in a circumferential direction of the shaft. A plurality of armature slots is formed on an outer periphery of an armature core. An upper coil is wound the number of turns Na through two armature slots, which are located apart from each other with the predetermined number of armature slots therebetween, at their opening sides. A lower coil is connected in parallel with the upper coil and wound the number of turns Nb through the two armature slots at their bottom sides. The number of turns Na is smaller than the number of turns Nb.
US09583980B2 Midfield coupler
Described herein are devices, systems, and methods for wireless power transfer utilizing a midfield source and implant. In one variation, a midfield source may be realized by a patterned metal plate composed of one of more subwavelength structures. These midfield sources may manipulate evanescent fields outside a material (e.g., tissue) to excite and control propagating fields inside the material (e.g., tissue) and thereby generate spatially confined and adaptive energy transport in the material (e.g., tissue). The energy may be received by an implanted device, which may be configured for one or more functions such as stimulation, sensing, or drug delivery.
US09583975B2 Charging and audio usage
Methods and apparatus, including computer program products, are provided for charging and audio usage. In one aspect there is provided a method, which may include detecting, by an accessory including a first connector and a second connector configured to enable coupling to a user equipment, a charger being coupled to the first connector; sending, based on at least the detected charger, an indication to the user equipment to change to a power receive mode; detecting, by the accessory, the change to the power receive mode; and allowing, based on at least the detected change, power to flow from the first connector to the second connector. Related systems, apparatus, and articles of manufacture are also disclosed.
US09583974B1 Uninterruptible power supply for an electric apparatus
An uninterruptible power supply system for supplying electrical power to an electrical apparatus. The system includes an alternating current (AC) power source providing AC power and a direct current (DC) power source providing DC power. The system also includes a power selector system having a power selector for selecting AC power or DC power for powering the electrical apparatus. The power selector system has a sensor for determining if AC power is acceptable for powering the electrical apparatus. In addition, the system includes a power automation system for charging the DC power source and a power management module for controlling the power selector system and the power automation system. The power management module switches to DC power for powering the electrical apparatus when the AC power is unacceptable. When DC power is used, DC power is provided directly to the electrical apparatus without converting the DC power.
US09583969B2 Electronic device, computer-readable storage medium, and portable terminal
An electronic device of the present invention has a secondary battery as a power source, and has a first interface arranged in one surface of the electronic device that includes a first communicating section which performs data communication with a first external device by near field communication and a power receiving section which is capable of receiving electric power from the first external device without being in direct contact and charging the secondary battery, and a second interface arranged in another surface of the electronic device that includes a second communicating section which performs data communication with a second external device by near field communication and a power transmitting section which is capable of transmitting electric power received from the secondary battery to the second external device without being in direct contact, and a control section which controls the operations of the first interface and the second interface.
US09583968B2 Photoluminescent disinfecting and charging bin
A charging and disinfecting tray for a vehicle is disclosed. The charging and disinfecting tray comprises a wireless charger for charging an electronic device and a lighting apparatus. The lighting apparatus comprises a disinfecting apparatus, which incorporates at least one photoluminescent indicator. A controller is in communication with the wireless charger and the lighting apparatus and is operable to control the photoluminescent indicator by initiating a sterilization operation with the disinfecting apparatus.
US09583967B2 Ruggedized pressure transducer with integrated wireless antenna and rechargeable battery system
A pressure transducer for a hammer union installation includes a lower body capable of withstanding the stresses of the hammer union installation. The lower body includes a cylindrical wall, a diaphragm, and a pressure port for exposing the diaphragm to pressure. The pressure transducer also includes one or more transducer elements mounted on the diaphragm that are operable to provide a signal related to pressure. A cap is received by the cylindrical wall and is slidable along the wall. The cap includes comprising an antenna for transmitting the signal. A spring is arranged in the lower body for dampening forces applied to the cap.
US09583964B2 Power receiving device, power transmitting device, wireless power transfer system, and wireless power transfer method
A power receiving unit includes a communication unit, a control unit, a detecting unit that performs metallic foreign matter detection, and a charge storage unit. The control unit is configured to control charging so electric power is stored in the charge storage unit for consumption by the detecting unit during Q-value measurement when the control unit receives a Q-value measurement command from the power transmitting device through the communication unit.
US09583962B1 Mobile device battery life protection
A method for controlling a charging process of a battery-operated device includes connecting the battery-operated device to a charger device to start the charging process, sending a first signal from the battery-operated device to the charger device in response to a charge level of a battery in the battery-operated device being below a first threshold, continuing the charging process until the charge level of the battery is above a second threshold, and sending a second signal from the battery-operated device to the charger device to stop the charging process in response to the charge level of the battery being above the second threshold.
US09583958B2 Voltage detecting device
A voltage detecting device includes a voltage detecting circuit configured to detect voltages of a plurality of battery cells constituting a battery; a plurality of voltage detecting lines connecting the respective battery cells to the voltage detecting circuit; discharging circuits connecting the respective voltage detecting lines to a ground, and discharging the battery cells in an overcharged state; a power adjusting section adjusting power of the battery, and supplying the voltage detecting circuit with the adjusted power as driving power; the voltage detecting circuit detecting the voltages of the respective battery cells via the voltage detecting lines; and an overvoltage protecting circuit protecting the voltage detecting circuit from voltage equal to or higher than a predetermined threshold value, the voltage being generated in the voltage detecting lines, the discharging circuits, and the power adjusting section.
US09583954B2 System and method for electrical charge transfer across a conductive medium
A method for supplying power to detected devices coupled to a conductive backplane includes: supplying a plurality of sensing signals at a plurality of transmit impedance values to the conductive backplane; analyzing a plurality of return signals received from the conductive backplane, the return signals corresponding to the sensing signals; detecting the presence of a sink device coupled to the conductive backplane based on the analyzed return signals; and supplying power from a power supply to the sink device via the conductive backplane after detecting the presence of the sink device.
US09583949B2 Power receiving apparatus and power transmission system
A power receiving apparatus includes a power reception circuit, a first member having a cylindrical shape, a power receiving coil disposed on a cylinder side surface of the first member and connected through wires to the power reception circuit, and a resonance coil configured to be freely movable along the cylinder side surface in a circumferential direction around a cylinder center axis of the first member, wherein the power receiving coil and the resonance coil are coupled to each other through electromagnetic induction.
US09583946B2 Method and apparatus for power converter input voltage regulation
A method and apparatus for regulating an input voltage to a power conversion module. In one embodiment, the method comprises computing a voltage regulation threshold based on an output voltage for the power conversion module; comparing an input voltage of the power conversion module to the voltage regulation threshold; and generating, when the input voltage satisfies the voltage regulation threshold, an average input voltage less than the voltage regulation threshold, wherein the average input voltage is generated from the input voltage.
US09583945B2 Frequency control method and frequency control apparatus
A frequency control method includes segmenting a range from a predetermined reference frequency to a predetermined lower limit frequency or a predetermined upper limit frequency into frequency range segments according to a number of battery apparatuses, detecting a current frequency of a power system, and causing battery apparatuses to charge from the power system or discharge to the power system in order to control a frequency or maintain a supply and demand balance of the power system, causing lager number of battery apparatuses to charge or discharge as a frequency range segment including the current frequency becomes farther apart from the reference frequency.
US09583943B2 Power supply system, power distribution apparatus, and power control method
A power supply system comprises a path switching means that switches a power supply path between power generation equipment and a load so that at least a part of output power of each power generation equipment is supplied to another power generation equipment during a power failure or power instability in the grid.
US09583941B2 Power connection control system and method
For each of consumers, a connection control apparatus is provided that includes an opening/closing device capable of connecting or disconnecting an electric power system and a consumer, that, when a power outage occurs in the electric power system, disconnects the electric power system and the consumer from each other by the opening/closing device at a command from an outage management apparatus or the like, and that connects the electric power system and the consumer to each other by the opening/closing device upon receiving a command from the outage management apparatus or the like at the time of restoration from the power outage. A power supply control apparatus supplies electric power from energy provision equipment to electrical appliances during a power outage in the electric power system.
US09583938B2 Electrostatic discharge protection device with power management
An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.
US09583936B1 Limiting the effects of faults in a data center
A data center includes one or more racks, computing devices mounted in the racks, and an electrical power system. The electrical power system supplies power to the computing devices in the racks. The electrical power system includes one or more rack power distribution units (PDUs) and one or more floor power distribution units (PDUs) or power panels. The rack PDUs include rack-level circuit protection devices that protect the computing devices receiving power from the rack PDU from overcurrent conditions. The floor PDUs or power panels include floor-level circuit protection devices that protect the computing devices from overcurrent conditions. The rack-level circuit protection devices have a faster response time than the floor-level circuit protection devices.
US09583926B2 Hanger bar
A hanger bar is provided for suspending and securing an electrical box between ceiling joists. The hanger bar is comprised of a main tube section, a box support bracket, a box which attaches to the box support bracket and two end plates which are attached to the main tube section without the use of fasteners or welding.
US09583923B2 Class I and class II modular wiring system
A modular wiring system carries different types or classes of wiring in a single cable. The modular wiring system includes two conduits, one inside the other. The outer conduit is a Class I conduit and the inner conduit is a Class II conduit. The Class II wiring is carried in the inner conduit and the Class I wiring is carried between the inner conduit and the outer conduit. The outer conduit may be any type of material that is approved for Class I. The inner conduit meets the same voltage rating as the outer conduit. The inner conduit may include a non-conductive outer surface and an inner metallic sheath. The inner metallic sheath is grounded and provides separation between the Class I and Class II conductors.
US09583919B2 Unit apparatus
In a unit apparatus in which units each equipped with a device are disposed in multiple stages and are attached to a housing, the unit apparatus includes: a device-protecting cover which is disposed on the front surface side of the unit and is formed by bending an upper part or a lower part thereof to protect the device; and a unit frame body having a unit base which is disposed in lapped relation on one of the bent upper part surface or the bent lower part surface of the device-protecting cover. The device-protecting cover and the unit frame body constitute a unit chamber; and the units are disposed in multiple stages in said housing, whereby the other of the bent upper part surface or the bent lower part surface of said bent device-protecting cover is shielded.
US09583918B1 Method and system for powering multiple computer platforms in symmetric configuration
Techniques pertaining to powering multiple platforms with a minimum impact on air passage in a predefined environment are disclosed. Instead of connecting each of the platforms in a chassis to a power supply therein, the present invention uses what is referred to as cascading powering to power all platforms within minimum cable delivery. According to one embodiment of the present invention, a power supply is disposed between two groups of platforms and powers them at the same time. At least one of the platforms has a power connector located towards or near the power supply so that only a short cable is needed to power the platform.
US09583911B2 Optical amplifier
The present embodiment relates to an optical amplifier which can perform an amplification operation equivalent to a normal operation even with an increase of dark current in a PD forming a part of a light detection circuit for monitoring signal light as an amplification object. In the optical amplifier, a detection controller performs an anomaly determination on a light detection circuit due to an increase of dark current in the PD based on a difference between temporal change amounts of a signal component of a voltage of output signal from a light receiving unit including the PD, and a voltage component in a high frequency region included in the signal component. An amplification controller can perform suitable switching of control on a drive current to a pumping light source, based on the result of the determination.
US09583904B2 Crimping pliers
The inventions relates to crimping pliers with two hand levers (3, 5) and two actuation elements (9, 10) located in the region of a pliers head (4). The actuation elements (9, 10) actuates dies (12) between which a workpiece can be crimped. A toggle lever drive (33) with two toggle levers (34, 35) which build a toggle lever angle (36) acts between the hand levers (3, 5) and the actuation elements (9, 10). One toggle lever (34) is built by a roller (23) which is pivotably mounted to the hand lever (5). The roller (23) rolls along a curved track (24) fixed at the other hand lever (3). A forced locking unit (48) is built with a toothed latching lever (28) which is supported for being rotated relatively to the roller (23).A lever part (30) of the toothed latching lever (28) is coupled by a sliding guide to the hand lever (3), whereas the other lever part (29) of the toothed latching lever (28) forms a toothing (31) for latching of the forced locking unit (48).
US09583903B1 Adapter for LED strip light
A waterproof adapter that connects strip light to a standard power cord, such that the power cord can then be routed to a power source. The adapter has an internal vertical barrier to separate power and ground leads, and gripping structures that help to retain the strip light within the adapter. A gasket or gaskets within the adapter seal the adapter from the elements.
US09583901B2 Field device using a seal board assembly
A seal board includes a circuit board with vias, conductor pins, and solder joints. The solder joints connect and seal each conductor pin to a single via, such that each conductor pin extends through the via and extends from a first side of the circuit board and a second side of the circuit board. The seal board is mounted to cover an opening in a bulkhead that separates a first compartment (such as a terminal block compartment) from a second compartment (such as an electronics or feature board compartment). The seal board provides electrical paths between the compartments while protecting components within one of the compartments from the surrounding environment.
US09583891B2 High-density electrical connector for plural multi-contact linear-array connections
An electrical connector for connecting plural multi-contact linear arrays with an electrical system, including: a base portion having a base member and an alignment member on the base member configured to hold the multi-contact linear arrays in place; an interconnect portion configured to mate with the base portion and having (1) a plurality of pins mounted thereto, each pin positioned for contact with a respective contact of the multi-contact linear arrays, and (2) an interconnect array having a plurality of conductive pathways to the electrical system; and one or more closure elements for holding the base and interconnect portions together, wherein each of the contacts of the multi-contact linear arrays is electrically connected to a corresponding point in circuits within the electrical system.
US09583888B2 Connector housing
A connector housing is provide and includes a single sheet of material, a plurality of first connection members, and a plurality of second connection members. The single sheet of material includes a top wall, a pair of side walls, a bottom wall having a first bottom wall portion and a second bottom wall portion connected to the pair of side walls, and a partition member disposed between the top wall and the bottom wall to partition an inner space defined by the top wall, the pair of side walls and the bottom wall. The plurality of first connection members are disposed along one of the pair of longitudinal edge portions, while the plurality of second connection members are disposed along the other of the pair of longitudinal edge portions. The plurality of first connection members are keyed with the plurality of second connection members, respectively.
US09583887B2 Cable connector assembly with spacer
A cable connector assembly has a connector and a cable with a number of coaxial wires and a number of unshielded wires. The connector includes an insulative housing with a front tongue and a rear end, a number of contacts with mating portions exposed on the front tongue and connecting portions exposed on the rear end, and a spacer assembled to the rear end. The spacer forms a plurality of positioning holes extending therethrough along a front-to-back direction, and a passageway extending therethrough along a vertical direction perpendicular to the front-to-back direction. The coaxial wires are inserted through the corresponding positioning holes and across the passageway to reach the corresponding contacts along the front-to-back direction so as to cut the coaxial wires in the passageway along the vertical direction.
US09583886B2 Receptacle assembly with guide frame
A receptacle assembly includes a guide assembly and at least one communication connector. The guide assembly has a guide frame extending from a connector housing. The guide frame includes a front panel and multiple frame members that extend between the front panel and a front wall of the connector housing. The frame members are spatially separated to allow air to flow through the guide frame. The frame members define first and second stacked channels that are each configured to guide a corresponding pluggable module that is received through the front panel through the guide frame to the connector housing. The communication connector is within the connector housing. The communication connector has first and second mating interfaces that extend through respective first and second apertures in the front wall of the connector housing into the first and second channels, respectively, to mate with the corresponding pluggable module within each channel.
US09583885B2 Connector assembly with grounding spring
A connector assembly (10) is disclosed in which a connector part (12) and a cable manager part (20) are provided. The cable manager part (20) can be provided with a housing part (40) that functions to ensure a grounded connection between the connector assembly (10) and a sheath (5) of a cable (4) via one or more springs (60, 66) secured within the housing part (40). In one embodiment, two parallel helical springs (60, 66) are disposed within the housing part (40).
US09583876B2 Connector locking mechanism
With leverage of a second arm, in a connector locking mechanism that releases a lock of a first arm that corresponds to a locking arm body, a working face of a supporting portion of the second arm is arranged on an upper surface of an upper wall portion of a fitting hood portion of a second connector housing. The fitting hood portion fits with respect to a first connector housing. The working face of the supporting portion of each of a pair of the second arms is arranged so as to be a plane perpendicular to a pressing-down direction of an operating end of each of the second arms.
US09583875B2 Plug connector with two types of locking devices
Provided is a plug connector for connecting electrical lines. The plug connector comprises a first plug connector housing and a second plug connector housing which can be plug-connected and locked to one another. The plug connector housings have two types of locking devices for locking purposes. In this case, the first type of locking device forms, from a rotary pin and a rotary bearing, a rotation axis about which the plug connector housings are mounted such that they can rotate in relation to one another. The second type of locking device is a type which is known from the prior art and which serves to fix the first plug connector housing to the second plug connector housing.
US09583874B2 Multiaxial connector for implantable devices
Disclosed are systems for wireless energy transfer including transcutaneous energy transfer. Embodiments are disclosed for electrical connections between an implanted wireless receiver and an implanted medical device powered by the receiver. Methods for manufacturing and using the devices and system are also disclosed.
US09583873B2 Electrical connector having detecting structure
An electrical connector includes an insulating housing, a plurality of conductive terminals received in the insulating housing, a detecting contact and a metallic shell shielding around the insulating housing. The insulating housing has a base portion and a mating tongue extending forwardly from the base portion. The metallic shell surrounds the meting tongue to form a receiving cavity opening forwardly. The conductive terminals have contacting sections exposed in the receiving cavity. The metallic shell has a resilient contacting portion contacting or disconnecting with the detecting contact so as to obtain detecting function.
US09583871B1 Electrical connector system with ferromagnetic actuators
Disclosed are interposer electrical connector embodiments including magnetic components used to facilitate interconnection of peripheral devices to standard input/output, or “I/O”, connectors (such as USB connectors) of devices such as mobile communications products (e.g. smart phones, tablets, and personal computers). The interposer connector embodiments disclosed include those in which a plurality of discrete permanent magnets are arranged with magnetic poles aligned in the same orientation perpendicular to and on one side of the electrical interface. Other embodiments include a plurality of bar permanent magnets located on opposite sides of the interface with all poles of the same type directed at the interface, but each one opposing a ferromagnetic element. These arrangements provide self-aligning capabilities useful for electrical connections that have restrictions on visibility or connection approach geometries. Other embodiments have a single magnet per mated connector pair and magnetic pole pieces and/or actuators to concentrate magnetic flux providing the magnetic attractive force for a plurality of electrical connections.
US09583870B2 Connector for preventing force transmission
A connector includes: a casing; a terminal which is connected to a mating terminal; a flexible conductor disposed inside the casing and on a side opposite to the mating terminal with respect to the terminal, and electrically connected to the terminal; a connecting member which is a conductor fixed to the casing, is disposed on a side opposite to the terminal with respect to the flexible conductor, and is electrically connected to the flexible conductor; and an electrical wire which is disposed on a side opposite to the terminal with respect to the connecting member, is electrically connected to the connecting member, and is drawn from the casing in a direction opposite to an insertion direction of the terminal toward the mating terminal.
US09583862B1 Connector assembly and retention mechanism configured to maintain a mated relationship
Connector assembly includes a communication connector configured to be at least one of electrically or optically coupled to a plug. The communication connector has a connector housing that includes a back side and a mating face that are on opposite ends of the connector housing. The connector assembly also includes a retention mechanism having a connector hinge and a retention clip. The connector hinge is a portion of the connector housing or is coupled to the connector housing. The retention clip has a panel, a hinge arm, and a plug arm. The panel extends between and couples to the hinge and plug arms. The hinge arm grips the connector hinge such that the retention clip is rotatable about the connector hinge between open and locked positions. The plug arm is shaped to press the plug toward the mating face when the retention clip is in the locked position.
US09583858B2 Connector terminal and connector
A connector terminal includes a conductive bar-shape member, a plurality of concavities each formed as a groove provided in an outer circumference of the bar-shape member, extending in a lengthwise direction of the bar-shape member, and spreading toward an opening from a bottom, and a convexity formed between the adjoining concavities. A first surface is formed on the bottom of the concavity. A second surface and a third surface that form different inclination angles relative to a depthwise direction of the concavity are alternately formed on an internal wall surface of the concavity from the bottom toward the opening.
US09583857B2 Electrical contactor and electrical connecting apparatus
An object of the present invention is to provide an electrical contactor highly resistant to deformation capable of achieving satisfactory performance of electrical contact with a small number of elements.An electrical contactor of this invention includes a barrel having a spring part achieving a spring function formed in a partial section, and a first plunger and a second plunger inserted in the barrel through an opening at one end and an opening at an opposite end of the barrel and fixed to the barrel. It is preferable that an end part of the first plunger in the barrel and an end part of the second plunger in the barrel are placed in internal space of the same non-spring part not to achieve a spring function. It is preferable that the barrel has three or more spring parts separated while non-spring parts are placed between the spring parts.
US09583852B1 PCB holder having a leg with a passageway with a conductive pin therein to electrically connect two PCBs
A horizontal printed circuit board (PCB) holder for connection to a first PCB and a second PCB may include a frame having one or more legs extending outwardly from the frame, each of the one or more legs having a passageway therein, and at least one conductive pin fixedly secured within the passageway of at least one of the one or more legs. The at least one conductive pin may convey electrical signals between the first PCB and the second PCB. A PCB holder assembly may include first and second PCBs connected to a PCB holder. A method of providing a PCB holder may include determining at least one characteristic of a first PCB and second PCB, configuring the PCB holder according to the determined characteristic(s), and connecting the first and second PCBs to the PCB holder.
US09583851B2 Orthogonal card edge connector
A system, according to one embodiment, includes a first end having several first contacts configured for coupling with a circuit board, a second end oriented about orthogonal to the first end, and a plurality of leads connecting the first and second contacts. The second end has a plurality of second contacts configured for coupling directly with a card edge of an electronic device. The orientation of the second end relative to the first end is fixed. A system, according to another embodiment, includes a circuit board, a plurality of such connectors.
US09583850B1 Connector module with a reseat actuator
An edge connector socket is configured to receive an edge connector on a memory module. A wedge member is slidably secured within the edge connector socket in alignment between contacts on the edge connector and pins within the edge connector socket. A cam is rotatably secured adjacent the wedge member, and an actuator is coupled to the cam. Rotation of the cam moves the wedge member between a first position and a second position. In the first position, the wedge member is disposed between the contacts and the pins and prevents engagement between the contacts and the pins. In the second position, the wedge member is withdrawn from between the contacts and the pins and allows reengagement between the contacts and the pins. Optionally, such a “reseat” action is performed in response to detecting an error associated with the memory module.
US09583845B1 Electrical connector for an information handling system
An electrical connector may be used to connect and propagate signals between electrical systems, devices, and components. The electrical connector may comprise a male conductor component with one or more contacts positioned on a member. The electrical connector may comprise a female conductor component configured to be a receptacle for receiving a portion of the male conductor and having one or more moveable conduction arms which may be actuated to contact respective one or more contacts positioned on the member of the male conductor component.
US09583844B2 Female contact comprising a spring
A female contact intended to receive a male contact, the female contact including a base and at least one side wall having a free edge defining an open end, the side wall being connected to the base and including an inner wall, wherein: the female contact includes a helical spring made of an electrically conductive material disposed between the base and the open end; part of the inner wall and the base are made of an electrically conductive material; and the inner wall of the female contact and/or the spring assure/assures electrical contact with a male contact in the position of use.
US09583840B1 Microwave zoom antenna using metal plate lenses
A zoom antenna includes an ordinary pyramidal horn antenna with either a coaxial or waveguide feed and two parallel plate waveguide lenses (commonly referred to as “metal plate lenses”) positioned with their optical axes collinear with the boresight of the pyramidal horn antenna and aligned with their plates parallel to the electric field vector. The zoom antenna outputs a collimated microwave beam having a diameter varied by translation of the lenses along boresight relative to each other and relative to the phase center of the horn antenna. The zoom antenna can be rotated to vary the azimuth and elevation angles of the collimated microwave beam produced therefrom, to thereby aim the beam in any direction.
US09583837B2 Differential planar aperture antenna
A planar differential aperture antenna that has a high gain and wide bandwidth at a millimeter wave band is provided. The differential aperture antenna has a cavity within it that has a height of roughly a quarter of a wavelength of the desired transmission band. The cavity is H-shaped, and has a cross shaped patch within the cavity that is fed differentially by two grounded coplanar waveguides. Two ends of the patch extend towards the ports on either side of the differential aperture antenna, and the other two ends of the patch extend into the cavity lobes, perpendicular with respect to the ports.
US09583834B2 Antenna module and radio communication device
An antenna module includes a first coil conductor, a second coil conductor and a magnetic layer. The first coil conductor and the second coil conductor are arranged with a magnetic layer interposed therebetween so that a coil aperture of the first coil conductor and a coil aperture of the second coil conductor are opposed to each other in alignment. An inner end portion of the first coil conductor and an inner end portion of the second coil conductor are electrically connected. The first coil conductor and the second coil conductor are connected to each other so that directions of magnetic fluxes generated in coil-wound axis directions of the first coil conductor and the second conductor are mutually opposite to each other. A magnetic flux φ entering a metal body in a perpendicular direction thereto flows in a lateral direction of the magnetic layer.
US09583832B2 Phase switching PLL and calibration method
The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.
US09583831B2 Electrically steerable antenna arrangement
An electrically steerable antenna arrangement comprising at least a first antenna function and a second antenna function, each antenna function comprising at least one antenna element, the antenna functions having at least one main radiation lobe that is electrically steerable, where each antenna function comprises at least one signal altering means arranged for altering the time characteristics and/or phase characteristics and/or frequency characteristics of a signal fed through the signal altering means, the electrically steerable antenna arrangement comprising a control unit arranged for feeding a signal comprising control information to the antenna functions via a control connection, the signal altering means being arranged to take certain settings in dependence of the control information, such that for certain settings of the signal altering means, a certain angular direction of said main radiation lobe in relation to an antenna reference plane is acquired. The electrically steerable antenna arrangement further comprises a first monitoring unit connected to the control connection, and a second monitoring unit connected to the antenna functions, the first monitoring unit being arranged to analyze the control information fed to the signal altering means and trigger a first alert via a first alert connection if there is a deviation which exceeds a first threshold, where furthermore the antenna functions are arranged to send signal information to the second monitoring unit regarding the resulting signal fed to said antenna elements, the second monitoring unit being arranged to analyze said signal information and to trigger a second alert via a second alert connection if there is a deviation which exceeds a second threshold.
US09583830B2 Radio frequency emissive display antenna and system for controlling
Apparatus and method improving the performance and allowing increased directionality and bandwidth via display-like software defined antenna. A surface is composed of an array of interconnected pixels which are capable of either becoming conducting or resistive allowing arbitrarily sized and shaped antenna structures. Each pixel is controlled by biasing the base which alters the conductivity on the top portion of the pixel. The specific pattern which is active on the display style antenna is based on the desired direction, frequency range, and waveform necessary for a required transmit and receive function.
US09583826B2 Resonance circuit for inhibiting interference between high-speed connector and antenna
The present invention is to provide a resonance circuit, which is applicable to a circuit board of a first electronic device provided thereon with a circuit layout, a high-speed connector (e.g., a USB 3.0 connector) at a lateral side of the circuit layout for connecting with a second electronic device, and an antenna for enabling the circuit board to receive and transmit wireless information at a predetermined frequency. The connector and antenna are respectively connected to first and second connecting points of the circuit layout, and the distance between the two connecting points is not less than one wavelength. The resonance circuit is connected to a third connecting point of the circuit layout provided between the above two connecting points, such that the resonance frequency of the resonance circuit covers the reception and transmission frequencies of the antenna, for effectively inhibiting interference between the connector and the antenna.
US09583825B2 Antenna device and electronic device with the same
An electronic device is provided. The electronic device includes a printed circuit board (PCB), a shield can disposed on the PCB, an antenna radiator of which at least a part enters an internal space of the shield can and is installed at an inner surface of the shield can, and an electrical connecting means which is installed at a corresponding position of the PCB so as to be electrically connected with the at least a part of the antenna radiator installed at the inner surface of the shield can.
US09583824B2 Multi-band wireless terminals with a hybrid antenna along an end portion, and related multi-band antenna systems
An antenna system may include a backplate that includes an end portion. The antenna system may also include a hybrid antenna that includes first and second antenna elements spaced apart from each other along the end portion of the backplate. The first antenna element may include a type of antenna element that is structurally different from the second antenna element. Additionally, the antenna system may further include a parasitic element between the first and second antenna elements along the end portion of the backplate.
US09583823B2 Foldable radome
In one embodiment, a foldable radome sub-assembly for an antenna reflector dish has flexible material connected to a plurality of rigid rim segments. Connection elements (e.g., inserts) are configured to interconnect two adjacent rim segments, such that, with the connection elements applied, the radome sub-assembly is configured as a radome connectable to the antenna reflector dish, and, without the connection elements applied, the radome sub-assembly is foldable between adjacent rim segments. The foldable radome sub-assembly can be folded up for efficient storage and shipping, yet is easy to configure in the field into a rigid radome for attachment to an antenna reflector dish.
US09583822B2 Broad band radome for microwave antenna
A radome for an antenna is provided as a composite of an isotropic outer layer and a structural layer of foamed polymer material. The composite is dimensioned to enclose an open end of the antenna. The radome may be retained upon the antenna by a retaining element and fasteners. The outer layer may be a polymer material with a water resistant characteristic.
US09583821B2 Antenna related features of a mobile phone or computing device
Antenna related features of a mobile phone or computing device are disclosed. In one embodiment, wireless control and signal are fed separately through difference types of flexes to optimize performance and cost. In one embodiment, active switching and processing of differing conductive trace lengths are performed on an antenna flex so that antenna performance can be optimized for multiple wireless technologies covering a wide range of wavelengths. In one embodiment, a cantilever arm affixed to a ground screw can provide double grounding in a region with no available screw points due to high z constraint. In one embodiment, a device can provide double feed for antenna through a single screw. In one embodiment, a short pin can be configured to support thinner metal. In one embodiment, a “vibrator bracket/LDS short pin” structure can be used to share a common screw point.
US09583819B2 Antenna device including a phase shifter and a feeding portion configured as a triplate line with a center conductor
An antenna device includes an input/output portion for a high frequency signal to be input or output, a distributing portion for distributing the high frequency signal input to the input/output portion into a plurality of high frequency signals, a phase shifting portion for imparting the plurality of high frequency signals with a predetermined amount of phase shift, and a feeding portion for feeding a plurality of antenna elements with the plurality of high frequency signals imparted with the predetermined amount of phase shift to cause the plurality of antenna elements to radiate the plurality of high frequency signals. The feeding portion is configured as a triplate line with a center conductor placed between one pair of parallel plate shaped outer conductors.
US09583816B2 Wireless transceiver
A wireless transceiver includes at least one antenna, a substrate, and a mechanical part on which the at least one antenna is disposed, wherein a relative position between the at least one antenna and the substrate is changed when an external force is applied to the mechanical part.
US09583810B2 High-frequency signal line
A signal line includes a first line portion at a first layer level and a second line portion at a second layer level, which are connected by a first interlayer connection. A first ground portion at the first layer level includes end portions closer to the first line portion than an intermediate portion, and a second ground portion at the second layer level includes end portions closer to the second line portion than an intermediate portion. A second interlayer connection connects one of the end portions of the first ground portion and one of the end portions of the second ground portion. A distance between the first and second interlayer connections is less than a distance between the first line portion and the intermediate portion of the first ground portion and is less than a distance between the second line portion and the intermediate portion of the second ground portion.
US09583808B2 Nonreversible circuit device
A nonreversible circuit device includes circulators of high pass type, each circulator including a first central conductor, a second central conductor, and a third central conductor arranged on a microwave magnetic body, to which a DC magnetic field is applied, in a relation intersecting each other in a mutually insulated state, and capacitance elements connected respectively in series between one end of the first central conductor and an antenna port, between one end of the second central conductor and a reception port, and between one end of the third central conductor and a transmission port. A pass frequency band of the circulator is lower than that of the circulator. The antenna ports of the circulators are electrically connected to provide one combined antenna port, and a low pass filter is inserted between the combined antenna port and the antenna port of the circulator.
US09583807B2 Hybrid resonators in multilayer substrates and filters based on these resonators
A filter of the present invention comprises a multilayer substrate, two terminals, a ground conductor and a hybrid resonator. The multilayer substrate includes a plurality of conductor layers and a dielectric configured to isolate said plurality of conductor layers from each other. The hybrid resonator is disposed in the multilayer substrate and comprises a first and a second resonant elements and a coupling strip connecting the first and said second resonant elements. Each resonant element comprises a signal via, a group of ground vias and an artificial dielectric. Each signal via is disposed through the multilayer substrate. Each group of ground vias is disposed through the multilayer substrate and configured to surround the signal via. Each artificial dielectric is disposed in the multilayer substrate and between the signal via and the group of ground vias. The artificial dielectric comprises a conductive plate connected to the first signal via and an isolating slit isolating the first conductive plate from the group of ground vias.
US09583806B2 Multi-band pass filter
An multi-band pass filter is disclosed. The multi-band pass filter in accordance with an embodiment of the present invention includes: a housing comprised with an input terminal and an output terminal separated from each other; a high pass filter installed in one inside of the housing and electrically connected to the input terminal and configured to form a plurality of resonator patterns with the circuit patterns on the printed circuit board; and a dual band reject filter series-connected with the high pass filter and provided between the high pass filter and the output terminal by forming a plurality of cavities inside the housing and furnishing each of the cavities with a resonator.
US09583805B2 RF filter assembly with mounting pins
An RF filter assembly comprising a substrate, an RF waveguide filter mounted on the substrate and a pair of alignment/mounting/RF signal transmission pins extending from respective apertures in the substrate into respective through-holes in the RF filter. In one embodiment, the RF waveguide filter is comprised of first and second blocks of dielectric material coupled together in an abutting side-by-side relationship and the pair of through-holes are defined in the first and second blocks respectively. In one embodiment, respective RF signal transmission pads defined on the respective first and second blocks of dielectric material are abutted against respective RF signal transmission pads defined on the substrate and interconnected by an RF signal transmission line in the interior of the substrate for transmitting the RF signal between the first and second blocks of dielectric material.
US09583802B2 Battery humidity control by diffusion barrier
Disclosed herein are various systems and methods for controlling humidity in batteries to reduce formation of condensate in a battery compartment. In one embodiment, a system consistent with the present disclosure may include a cooling system configured to produce a flow of coolant. A battery compartment may house a battery and may separate the battery from an environment. The flow of coolant may pass into the battery compartment and may be used to cool the battery. The battery compartment may include a vent configured to permit a flow of environmental air to enter the battery compartment. A diffusion barrier may be in fluid communication with the vent and configured to deliver the flow of environment air to the battery compartment. The diffusion barrier may decrease diffusion of water vapor from the environment into the battery compartment.
US09583798B2 Electric vehicle battery thermocouple
An example electric vehicle battery thermocouple includes a temperature sense lead of a first material, and an electric vehicle battery component of a second material different than the first material. In an exemplary embodiment, the electric vehicle battery component includes a voltage sense lead and a bus bar. In another exemplary embodiment, the electric vehicle battery component includes a voltage sense lead and a terminal. In yet another exemplary embodiment, the electric vehicle battery component includes a voltage sense lead.
US09583796B2 Method for monitoring/managing electrochemical energy device by detecting intercalation stage changes
A method for determining an operating state (e.g., state-of-charge or state-of-health) and/or generating management (charge/discharge) control information in a system including an electrochemical energy device (EED, e.g., a rechargeable Li-ion battery, supercapacitor or fuel cell) that uses optical sensors to detect the intercalation stage change events occurring in the EED. The externally or internally mounted optical sensors measure operating parameter (e.g., strain and/or temperature) changes of the EED during charge/recharge cycling, and transmit measured parameter data using light signals sent over optical fibers to a detector/converter. A processor then analyzes the measured parameter data, e.g., using a model-based estimation process, to detect intercalation stage changes (i.e., crystalline structure changes caused by migration of guest species, such as Li-ions, between the EED's anode and cathode), and generates the operating state and charge/discharge control information based the analysis.
US09583787B2 Additive for electrolyte and electrolyte and lithium secondary battery
An additive, the additive being for an electrolyte for a lithium secondary battery and represented by Chemical Formula 1: R1 to R4 each independently being hydrogen or a non-polar hydrocarbon group, is disclosed. An electrolyte, the electrolyte being for a lithium secondary battery and including: a non-aqueous organic solvent; a lithium salt; and the additive is also disclosed. A lithium secondary battery including: a positive electrode; a negative electrode facing the positive electrode; and a separator between the positive electrode and the negative electrode, the separator being impregnated with an electrolyte including the additive, is also disclosed.
US09583783B2 Prismatic secondary battery
A prismatic secondary battery includes: an electrode group including electrodes formed of positive electrodes and negative electrodes each having an active material layer coated on a surface of a metallic foil, the electrodes formed of positive and negative electrodes are flatly wound together with a separator intervening with the positive and negative electrodes, the positive and negative electrodes being each formed with a metallic foil exposed section at one end in a direction of a winding axis L; and connection plates that electrically connect the electrode group and electrode terminals. The metallic foil exposed sections of the electrode group and the connection plates are press-joined. At least a portion of the press-joined sections constituted by the metallic foil exposed sections and the connection plates is covered with a resin material.
US09583780B2 Fuel system using redox flow battery
An automotive or other power system including a flow cell, in which the stack that provides power is readily isolated from the storage vessels holding the cathode slurry and anode slurry (alternatively called “fuel”) is described. A method of use is also provided, in which the “fuel” tanks are removable and are separately charged in a charging station, and the charged fuel, plus tanks, are placed back in the vehicle or other power system, allowing fast refueling. The technology also provides a charging system in which discharged fuel is charged. The charged fuel can be placed into storage tanks at the power source or returned to the vehicle. In some embodiments, the charged fuel in the storage tanks can be used at a later date. The charged fuel can be transported or stored for use in a different place or time.
US09583777B2 Solid oxide fuel cell, cell stack device, fuel cell module, and fuel cell device
A solid oxide fuel cell, a cell stack device, a fuel cell module and a fuel cell device are disclosed. The solid oxide fuel cell includes a solid electrolyte layer, fuel electrode layer and an oxygen electrode layer. The solid electrolyte layer has gas blocking properties and includes first and second main surfaces opposite to each other. The fuel electrode layer is disposed on the first main surface while the oxygen electrode layer is disposed on the second main surface of the solid electrolyte layer. A thickness of the solid electrolyte layer is 40 μm or less. Porosity of the solid electrolyte layer in an arbitrary cross section thereof is 3 to 15% by area. An average pore diameter of pores in the solid electrolyte layer is 2 μm or less.
US09583775B2 Fuel cell system and electronic device controlling the same
A method of operating a fuel cell system which is controlled by an electronic device includes: transmitting a bit stream including a bit string which indicates identification information of the fuel cell system and a bit string which indicates status information of the fuel cell system to the electronic device through a serial communication line; receiving a bit stream including a bit string which indicates control information of the fuel cell system from the electronic device through the serial communication line; obtaining the control information of the fuel cell system from the received bit stream; and controlling power production of a fuel cell by controlling operations of peripheral devices of the fuel cell system based on the obtained control information of the fuel cell system.
US09583772B2 Oxide-ceramic high-temperature fuel cell
The present invention relates to high-temperature solid oxide fuel cells, in particular to rotationally symmetrical high-temperature solid oxide fuel cells. The inventive oxide-ceramic high-temperature fuel cell having one or more gas channel(s) open at at least one end. The fuel cell has a substrate surrounding the gas channel(s) at least sectionally, preferably completely. The gas channel(s) and/or the substrate surrounding the gas channel(s) has/have (a) changing cross-sections(s), preferably (a) conically tapering cross-section(s), seen in the direction of the longitudinal axis/axes of the gas channel(s).
US09583768B2 Negative electrode slurry composition, lithium ion secondary battery negative electrode, and lithium ion secondary battery
Provided is a negative electrode slurry composition including a binder resin, a water-soluble polymer, and a negative electrode active material, wherein the binder resin including (A) a styrene-butadiene copolymer latex having a gel amount of 70 to 98% and a glass transition temperature of −30° C. to 60° C. in dynamic viscoelasticity measurement and (B) an acryl polymer latex having a gel amount of 70 to 98% and a glass transition temperature of −100° C. to 0° C. in dynamic viscoelasticity measurement, and the negative electrode active material including a carbon-based active material and a silicon-based active material.
US09583767B2 Methods for making battery electrode systems
Methods for making battery electrode system are disclosed herein. In an example of the method, a mixture of a polymer binder, an active material and a conductive filler is deposited on a current collector. The deposited mixture is exposed to an external field having a field direction that is normal to a surface of the current collector. The exposure aligns, outward from and normal to the surface of the current collector, the active material and the conductive filler to form a plurality of discrete structures that extend outward from and normal to the surface of the current collector and are respectively aligned with a field line of the external field. Each of the plurality of discrete structures includes some of the active material and some of the conductive filler.
US09583761B2 Methods for making anodes for germanium-containing lithium-ion devices
Methods for making anodes for lithium ion devices are provided. The methods include milling germanium powder, carbon, and boron carbide powder to form a nano-particle mixture having a particle size of 20 to 100 nm; adding an emulsion of tungsten carbide nano-particles having a particle size of 20 to 60 nm to the mixture to form an active material; and adding a polymeric binder to the active material to form the anode, wherein the weight percentage of the germanium in the anode is between 5 to 80 weight % of the total weight of the anode, the weight percentage of boron in the anode is between 2 to 20 weight % of the total weight of the anode and the weight percentage of tungsten in the anode is between 5 to 20 weight % of the total weight of the anode.
US09583760B2 Method for producing negative electrode material for lithium ion batteries
A negative electrode material for lithium ion batteries is obtained by a method which includes: mixing carbon particles (B) such as graphite particles, particles (A), such as Si particles, containing an element capable of occluding and releasing lithium ions, a carbon precursor such as sucrose, a carboxylic acid compound such as acetic acid, and a liquid medium such as water or isopropyl alcohol to prepare a slurry; drying and solidifying the slurry; and heat-treating the resulting solidified material to carbonize the carbon precursor. A lithium ion battery is obtained using this negative electrode material.
US09583759B2 Cathode active material, method of manufacturing the same and battery
A cathode active material capable of obtaining a high capacity and capable of improving stability or low-temperature characteristics, a method of manufacturing the same, and a battery are provided. A cathode (21) includes a cathode active material including a lithium complex oxide including Li and at least one kind selected from the group consisting of Co, Ni and Mn, and P and at least one kind selected from the group consisting of Ni, Co, Mn, Fe, Al, Mg and Zn as coating elements on a surface of the lithium complex oxide. Preferably, the contents of the coating elements are higher on the surface of the cathode active material than those in the interior thereof, and decrease from the surface to the interior.
US09583758B2 Electrodes, batteries, electrode production methods, and battery production methods
Battery electrodes are provided that can include a conductive core supported by a polymeric frame. Methods for manufacturing battery electrodes are provided that can include: providing a sheet of conductive material; and framing the sheet of conductive material with a polymeric material. Batteries are provided that can include a plurality of electrodes, with individual ones of the electrodes comprising a conductive core supported by a polymeric frame.
US09583757B2 Electrodes, electrochemical cells, and methods of forming electrodes and electrochemical cells
Electrodes and methods of forming electrodes are described herein. The electrode can be an electrode of an electrochemical cell or battery. The electrode includes a current collector and a film in electrical communication with the current collector. The film may include a carbon phase that holds the film together. The electrode further includes an electrode attachment substance that adheres the film to the current collector.
US09583748B2 Battery pack having tension bar
Disclosed is a battery pack which improves coupling strength and space utilization of a plurality of battery modules.
US09583743B2 Electrical storage device
An electrical storage device includes a case body having an opening, a lid, which closes the opening and has a through hole, an electrode assembly accommodated in the case body, and an electrode terminal. The electrode terminal has a base and a polar column portion, which projects from the base and shaped to pass from the inside of the case body through the through hole and protrude to the outside. A sealing member is sandwiched between the inner surface of the lid and a seat surface of the base. In a root portion of the polar column portion coupled to the base, in at least a part of the polar column portion around an axis thereof, a tapered portion, which spreads in the cross-sectional shape toward the base along the axis of the polar column portion, is provided. The sealing member is arranged radially outside of the tapered portion.
US09583737B2 Organic electro-luminescence display device
An organic electro-luminescence display device includes a first substrate, plural pedestals which are provided in a convex shape on the first substrate and have inclined side surfaces, plural first electrodes respectively provided on the respective side surfaces of the pedestals, an organic electro-luminescence film which is provided above the plural pedestals and includes a light-emitting layer laminated on the plural fist electrodes, and a second electrode which is provided above the plural pedestals and is laminated on the organic electro-luminescence film. Light generated in the light-emitting layer is transmitted between a first reflection surface and a second reflection surface. The second electrode includes light transmission parts, through which the light passes, above upper end parts of the pedestals. A surface of the second electrode facing the organic electro-luminescence film is the second reflection surface except for the light transmission parts.
US09583735B2 Light-emitting element, light-emitting device, electronic device, and lighting device
A novel light-emitting device is provided. A novel light-emitting device with high emission efficiency, low power consumption, and small viewing angle dependence of chromaticity is provided. The light-emitting device includes at least one light-emitting element and one optical element. A spectrum of light emitted from the light-emitting element through the optical element in a range of greater than 0° and less than or equal to 70° with respect to a normal vector of the light-emitting element has a first local maximum value in a wavelength range of greater than or equal to 400 nm and less than 480 nm and a second local maximum value located on a longer wavelength side than the first local maximum value. The intensity ratio of the second local maximum value to the first local maximum value is less than or equal to 15%.
US09583729B2 Method for producing an electronic component
A method for producing an electronic component with at least one first electrode zone (21) and one second electrode zone (23), which are separated from one another by an insulator (9) and each comprise at least one sublayer of a first electrically conductive material. Also disclosed is an electronic component, which may be produced using the disclosed method.
US09583725B2 Conductive thin film, method for producing same, and electronic element comprising same
Provided are a conductive thin film, a method for producing same, and an electronic element comprising same. The conductive thin film has excellent conductivity, allows the easy adjustment of a work function, also allows easy film formation, and thus can be advantageously used in various electronic elements, such as organic light-emitting devices and organic solar cells.
US09583723B2 N-type thin film transistor
An N-type thin film transistor includes an insulating substrate, a gate electrode, an insulating layer, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, and a drain electrode. The gate electrode is located on a surface of the insulating substrate. The insulating layer is located on the gate electrode. The semiconductor carbon nanotube layer is located on the insulating layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer.
US09583722B2 Organic thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display device
An organic thin film transistor and a preparation method thereof, an array substrate and a preparation method thereof, and a display device; and the preparation method of the organic thin film transistor comprises: forming a source-drain metal layer including a source electrode (12a) and a drain electrode (12b), and forming an organic semiconductor active layer (13) in contact with the source electrode (12a) and the drain electrode (12b); and forming an organic insulating thin film (140) on a substrate (10) where the source-drain metal layer and the organic semiconductor active layer (13) have been formed, thinning the organic insulating thin film (140) and curing the thinned organic insulating thin film (140), or curing the organic insulating thin film (140) and thinning the cured organic insulating thin film (140), to form an organic insulating layer (14). The method can be used to form a thin and uniform organic insulating layer, so a technical difficulty in forming a via hole is reduced.
US09583721B2 Substrate for organic electronic device
Provided are a substrate for an organic electronic device, an organic electronic device and lighting. As a substrate for an OED such as an OLED, a substrate capable of providing an organic electronic system having excellent performance and reliability may be provided.
US09583720B2 Phenyl and fluorenyl substituted phenyl-pyrazole complexes of Ir
The invention provides emissive materials and organic light emitting devices using the emissive materials in an emissive layer disposed between and electrically connected to an anode and a cathode. The emissive materials include compounds with the following structure: wherein at least one of R8 to R14 is phenyl or substituted phenyl, and/or at least two of R8 to R14 that are adjacent are part of a fluorenyl group. The emissive materials have enhanced electroluminescent efficiency and improved lifetime when incorporated into light emitting devices.
US09583718B2 Pyrene-based compound and organic light-emitting diode including the same
A pyrene-based compound and an organic light-emitting diode including the same, the pyrene-based compound being represented by Formula 1, below:
US09583714B2 Material for organic electronics, organic electronic element, organic electroluminescent element, display element using organic electroluminescent element, illuminating device, and display device
Provided is a material for organic electronics which can produce an organic electronic element capable of lowering the driving voltage or capable of performing stable driving for a long time. The material for organic electronics contains at least an ionic compound and a compound having a charge transporting unit (hereinafter, referred to as charge transporting compound), and the ionic compound is composed of a counter cation and a counter anion, while the counter cation is any one kind or two or more kinds selected from H+, a carbocation, a nitrogen cation, an oxygen cation, and a cation having a transition metal.
US09583713B2 Interlayer for electronic devices
Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as interlayers applied to fluoropolymer layers used in the fabrication of electronic devices, the electronic devices that encompass such polycycloolefin interlayers and processes for preparing such polycycloolefin interlayers and electronic devices.
US09583710B2 Organic semiconductor polymer, composition for organic semiconductor material, and photovoltaic cell
An organic semiconductor polymer having a structural unit represented by the following Formula (I), a composition for organic semiconductor material, a photovoltaic cell and a polymer, wherein X represents Si, S or O; R1 represents a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group, an aromatic heterocyclic group or an oxygen atom; p represents 0, 1 or 2; herein, the bond between X and R1 is such that when X is Si, the bond is a single bond, and when X is S, the bond is a double bond. Furthermore, when X is O, p represents 0.
US09583707B2 Micro-nozzle and micro-nozzle array for OVJP and method of manufacturing the same
Embodiments of the disclosed subject matter provide a nozzle assembly and method of making the same, the nozzle assembly including a first aperture formed on a first aperture plate to eject a carrier gas flow having organic vapor onto a substrate in a deposition chamber, second apertures formed on a second aperture plate disposed adjacent to the first aperture to form a vacuum aperture, where the first aperture plate and the second aperture plate are separated by a first separator plate, third apertures formed on a third aperture plate to eject purge gas that are disposed adjacent to the second aperture plate, where the second aperture plate and the third aperture plate are separated by second separator plate, and a third separator plate is disposed adjacent to the one or more third aperture plates to form a gas channel in the one or more third aperture plates.
US09583706B2 Semiconductor apparatus and method for fabricating the same
A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern.
US09583705B2 Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked. After the insulating patterns are formed, metal-semiconductor compounds are formed on the exposed semiconductor patterns.
US09583704B2 Complementary resistance switch, contact-connected polycrystalline piezo- or ferroelectric thin-film layer, method for encrypting a bit sequence
Disclosed is a complementary resistor switch (3) comprising two outer contacts, between which two piezo- or ferroelectric layers (11a and 11b) having an inner common contact are situated. At least one region (11′, 11″) of the layers is modified, either the outer contacts are rectifying (S) and the inner contact is non-rectifying (O), or vice versa, the modified regions are formed at the rectifying contacts, the layers have different strain-dependent structural phases with different band gaps and/or different polarization charges, and the electrical conductivity of the layers is different. Also disclosed are a connectable resistor structure having at least one Schottky contact at two adjoining piezo- or ferroelectric layers, a polycrystalline piezo- or ferroelectric layer comprising modified crystallites, and a method and circuits for encrypting and decrypting a bit sequence.
US09583703B2 Tunable variable resistance memory device
A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The device may also include a metal ion source structure between the chalcogenide glass layer and the second electrode. The device may include a buffer layer between the first electrode and the chalcogenide glass layer.
US09583702B2 Graphene-inserted phase change memory device and method of fabricating the same
Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.
US09583701B1 Methods for fabricating resistive memory device switching material using ion implantation
A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.
US09583697B2 Magnetic memory devices and methods of forming the same
The inventive concepts provide magnetic memory devices and methods forming the same. The method includes sequentially forming a first magnetic conductive layer and a capping layer on a substrate, patterning the capping layer and the first magnetic conductive layer to form a first magnetic conductive pattern and a capping pattern, forming an interlayer insulating layer exposing the capping pattern on the substrate, removing the capping pattern to expose the first magnetic conductive pattern, forming a tunnel barrier layer and a second magnetic conductive layer on the first magnetic conductive pattern and the interlayer insulating layer, and patterning the second magnetic conductive layer and the tunnel barrier layer to form a second magnetic conductive pattern and a tunnel barrier pattern.
US09583696B2 Reference layer for perpendicular magnetic anisotropy magnetic tunnel junction
An apparatus includes a perpendicular magnetic anisotropy magnetic tunnel junction (pMTJ) device. The pMTJ device includes a storage layer and a reference layer. The reference layer includes a portion configured to produce a ferrimagnetic effect. The portion includes a first layer, a second layer, and a third layer. The second layer is configured to antiferromagnetically (AF) couple the first layer and the third layer during operation of the pMTJ device.
US09583691B2 Thermal management in electronic devices with yielding substrates
In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.
US09583688B2 Light emitting device mount, leadframe, and light emitting apparatus
A light emitting device mount includes a positive lead terminal, a negative lead terminal, and a resin portion. Each of the positive and negative lead terminal includes a first main surface, a second main surface, and an end surface. The end surface is provided between the first main surface and the second main surface. The end surface includes a first recessed surface area and a second recessed surface area. The first recessed surface area is extending from a first point of the first main surface in cross section. The second recessed surface area is extending from a second point of the second main surface in cross section. The first and second recessed surface areas define a protruding portion protruding outwardly. The resin portion is positioned at least between the end surface of the positive lead terminal and the end surface of the negative lead terminal.
US09583686B2 Light-emitting-device package and production method therefor
A light-emitting-device package according to one aspect of the present invention includes: a metal substrate; a light emitting device disposed on a first surface of the metal substrate and configured to emit at least ultraviolet light; a pair of electrodes disposed to be spaced apart from each other on at least the first surface of the metal substrate, and electrically connected to the light emitting device; and an insulating layer provided between the metal substrate and the pair of electrodes. UV reflectance of the first surface of the metal body is higher than UV reflectance of the pair of electrodes.
US09583676B2 Low warpage wafer bonding through use of slotted substrates
In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.
US09583673B2 Semiconductor light emitting device including GaAs substrate
A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 μm.
US09583672B2 Nano-structured light-emitting device and methods for manufacturing the same
A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized. A conductive layer surrounds sides of the nano structure, a first electrode is electrically connected to the first semiconductor layer and a second electrode is electrically connected to the conductive layer.
US09583670B2 Luminescence conversion element and optoelectronic semiconductor component comprising such a luminescence conversion element and method of producing same
A luminescence conversion element for wavelength conversion of primary electromagnetic radiation into secondary electromagnetic radiation includes first luminescent material particles that, when excited by the primary electromagnetic radiation, emit a first electromagnetic radiation, a peak wavelength of which is at least 515 nm to at most 550 nm of a green region of the electromagnetic spectrum; second luminescent material particles that, when excited by the primary electromagnetic radiation, emit a second electromagnetic radiation, a peak wavelength of which is at least 595 nm to at most 612 nm of a yellow-red region of the electromagnetic spectrum; and third luminescent material particles that, when excited by the primary electromagnetic radiation, emit a third electromagnetic radiation, a peak wavelength of which is at least 625 nm to at most 660 nm of a red region of the electromagnetic spectrum.
US09583669B2 Inkjet printable etch resist
The methods involve selectively depositing a resist containing a solid hydrogenated rosin resin and a liquid hydrogenated rosin resin ester as a mixture on a semiconductor followed by etching uncoated portions of the semiconductor and simultaneously inhibiting undercutting of the resist. The etched portions may then be metallized to form current tracks.
US09583654B2 Light receiving device and image sensor
A light receiving device includes a substrate having a principal surface and a back surface, the substrate containing GaSb semiconductor co-doped with a p-type dopant and an n-type dopant; a stacked semiconductor layer disposed on the principal surface of the substrate, the stacked semiconductor layer including an optical absorption layer; and an incident surface provided on the back surface of the substrate that receives an incident light. The optical absorption layer includes a super-lattice structure including a first semiconductor layer and a second semiconductor layer that are alternately stacked. In addition, the first semiconductor layer contains gallium and antimony as constituent elements. The second semiconductor layer is composed of a material different from a material of the first semiconductor layer.
US09583648B2 Solar cell
A solar cell includes a substrate of a first conductive type, a plurality of first electrodes positioned on one surface of the substrate in parallel with one another, and a plurality of back surface field regions which are positioned respectively correspondingly to the plurality of first electrodes, are separated from one another, and are doped with impurities of the first conductive type at a concentration higher than the substrate. Each back surface field region includes discontinuous regions in a longitudinal direction of the first electrodes. An impurity concentration of the discontinuous regions is lower than an impurity concentration of the back surface field region.
US09583645B2 Photovoltaic system
Disclosed is a photovoltaic system including a power optimizer, capable of minimizing noise occurring due to shading, an error in an output power of a photovoltaic module, etc. while a maximum power point tracking (MPPT) algorithm is performed. The photovoltaic system includes a photovoltaic module; a power optimizer; and an inverter, wherein the power optimizer includes: an input unit configured to receive an output power of the photovoltaic module; a sensing unit configured to sense an output voltage and an output current of the photovoltaic module; and a controller configured to control an output of the power optimizer, by comparing the presently-sensed current with a previously-sensed current.
US09583638B2 Transistors, methods of manufacturing a transistor and electronic devices including a transistor
A transistor, a method of manufacturing a transistor, and an electronic device including a transistor are provided, the transistor may include a channel layer having a multi-layer structure. The channel layer may have a double layer structure or a triple layer structure. At least two layers of the channel layer may have different oxygen concentrations.
US09583637B2 Amorphous oxide and field effect transistor
A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals.
US09583632B2 Oxide semiconductor film, method for forming oxide semiconductor film, and semiconductor device
A crystalline oxide semiconductor film and a semiconductor device including the oxide semiconductor film are provided. One embodiment of the present invention is an oxide semiconductor film including a plurality of flat-plate particles each having a structure in which layers including a gallium atom, a zinc atom, and an oxygen atom are provided over and under a layer including an indium atom and an oxygen atom. In the semiconductor film, the plurality of flat-plate particles face in random directions, and a crystal boundary is not observed using a transmission electron microscope.
US09583628B2 Semiconductor device with a low-K spacer and method of forming the same
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.
US09583620B2 Shaped cavity for SiGe filling material
The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a diamond-shaped cavity, and the shaped cavity is filled with silicon and germanium material. There are other embodiments as well.
US09583616B2 Semiconductor structure including backgate regions and method for the formation thereof
A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and the plurality of transistors, and a trench isolation structure including a portion between a first and a second island of the semiconductor structure and extending into the substrate to a first depth. The substrate includes a bottom region having a first type of doping and extending at least to a second depth greater than the first depth, and a deep well region having a second type of doping and extending to a third depth greater than the first depth and smaller than the second depth. Each of the first and second islands includes a first backgate region having the first type of doping and being continuous with the bottom region and a second backgate region having the second type of doping and being continuous with the deep well region.
US09583614B2 Insulated gate field effect transistor having passivated schottky barriers to the channel
A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.
US09583612B1 Drift region implant self-aligned to field relief oxide with sidewall dielectric
An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.
US09583606B2 Semiconductor device
An improvement is achieved in the reliability of a semiconductor device having an IGBT. In an active cell region, in a portion of a semiconductor substrate which is interposed between first and second trenches in which first and second trench gate electrodes are embedded, an n+-type emitter region, a p-type body region located thereunder, and a first n-type hole barrier region located thereunder are formed. In a hole collector cell region, in a portion of the semiconductor substrate which is interposed between third and fourth trenches in which third and fourth trench gate electrodes are embedded, the p-type body region and a second n-type hole barrier region located thereunder are formed, but an n-type semiconductor region equivalent to the n+-type emitter region is not formed. Under the first and second n-type hole barrier regions, an n−-type drift region having an impurity concentration lower than those thereof is present. The impurity concentration of the second n-type hole barrier region is higher than the impurity concentration of the first n-type hole barrier region.
US09583600B1 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and shallow trench isolation (STI) around the fin-shaped structure; forming a gate line across the fin-shaped structure and on the STI; performing a first cutting process to remove the part of the gate line directly above the fin-shaped structure and the fin-shaped structure directly under the gate line; and performing a second cutting process to remove part of the gate line on the STI.
US09583598B2 FETs and methods of forming FETs
An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.
US09583597B2 Asymmetric FinFET semiconductor devices and methods for fabricating the same
Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.
US09583593B2 FinFET and method of manufacturing the same
A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first region, the first region being one of a source region and a drain region. The method further includes forming a sacrificial spacer. The method further includes forming a second region with the sacrificial spacer as a mask, the second region being the other one of the source region and the drain region. The method further includes removing the sacrificial spacer. The method further includes replacing the sacrificial spacer with a gate stack comprising a gate conductor and a gate dielectric that separates the gate conductor from the semiconductor fin.
US09583590B2 Integrated circuit devices including FinFETs and methods of forming the same
Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.
US09583588B2 Method of making high electron mobility transistor structure
A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.
US09583587B2 Method for manufacturing injection-enhanced insulated-gate bipolar transistor
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.
US09583585B2 Gate structure integration scheme for fin field effect transistors
In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.
US09583582B2 Semiconductor integrated device
According to one embodiment, a semiconductor integrated device includes a first node that receives a first voltage, a second node that receives a second voltage, and an electrode. A PMOS transistor is coupled between the first node and the electrode. An NMOS transistor is coupled between the second node and the electrode. A control signal at a voltage lower than the second voltage is supplied to a gate electrode of the PMOS transistor. A control signal at a voltage higher than the first voltage is supplied to a gate electrode of the NMOS transistor.
US09583581B1 Discontinuities in a semiconductor device to accommodate for manufacturing variations and/or misalignment tolerances
An integrated circuit is described as having one or more contact regions to provide one or more interconnections between one or more transistors of the integrated circuit and another integrated circuit. The one or more contact regions represent a self-aligned contact (SAC) whose positioning is determined through one or more patterning processes of a semiconductor fabrication process. The one or more contact regions include one or more contact discontinuities to allow the integrated circuit to accommodate for a wide range of the manufacturing variations and/or the misalignment tolerances by preventing the one or more contact regions from physically contacting other regions, such as gate regions to provide an example, of the one or more transistors. As such, the one or more contact discontinuities have a dynamic size, such as a dynamic area to provide an example, which is dependent upon the manufacturing variations and/or the misalignment tolerances.
US09583580B2 Manufacturing method of the semiconductor device electrode having three metal layers
A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.
US09583576B2 Semiconductor device and method for driving the same
Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
US09583575B2 Semiconductor substrate
Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
US09583573B2 Compound semiconductor device and method of fabricating the same
A compound semiconductor device is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region; a semiconductor layer disposed on the substrate; and a buffer layer located between said substrate and said semiconductor layer; wherein doping conditions of said first doped region and said second doped region are different from each other; wherein said semiconductor layer has different thicknesses on locations corresponding to said first doped region and said second doped region respectively, and is formed as a structure with difference in thickness.
US09583570B2 Oxide semiconductor stacked film and semiconductor device
An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.
US09583567B2 III-V gate-all-around field effect transistor using aspect ratio trapping
A field effect transistor includes a trench in a field dielectric material on a crystalline silicon substrate and source/drain features inside the trench. The field effect transistor further includes a channel feature comprising a III-V material in the trench and spanning between the source/drain features, and gate dielectric layers and a gate feature surrounding a portion of the channel feature.
US09583564B2 Isolation structure
A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.
US09583563B1 Conformal doping for punch through stopper in fin field effect transistor devices
A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.
US09583555B2 Semiconductor device having inductor
A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.
US09583551B2 OLED array substrate, method for fabricating the same, and display device
Embodiments provide an OLED array substrate, a method for fabricating the same, and a display device. The present invention relates to the field of display technology, can decrease resistivity of an electrode, and avoid increase in patterning process. The OLED array substrate comprises an effective pixel display area and a peripheral wiring area. The effective pixel display area comprises a TFT which is arranged on a base plate. The array substrate further comprises a plurality of conductors which are arranged between the base plate and the first electrode; wherein, in the peripheral wiring area, the plurality of conductors are connected with the second electrode.
US09583549B2 Organ light emitting display device
An organic light emitting display device includes a substrate including a plurality of pixel regions each including a light emitting region and a transparent region, a gate electrode in the light emitting region, a first insulating interlayer covering the gate electrode and extending from the light emitting region to the transparent region, a drain electrode on the first insulating interlayer and constituting a transistor in conjunction with the gate electrode, a planarization layer covering the transistor and exposing a top surface of the first insulating interlayer in the transparent region, and a first electrode on the planarization layer.
US09583546B2 Organic light emitting device and method of fabricating the same
An organic light emitting device and a method of fabricating the same includes a first substrate; a thin film transistor (TFT) on the first substrate; a planarization layer on the TFT; an organic light emitting diode (OLED) on the planarization layer; a passivation layer on the OLED; a second substrate on the passivation; and a hydrogen capturing material between the first and the second substrates to prevent oxidation of materials forming the TFT.
US09583544B2 Organic EL display device
A bank partitions a plurality of pixels and has an opening in each of the plurality of pixels. An organic layer includes a light emitting layer, and covers the bank opening. A first inorganic barrier layer is formed of an inorganic material, and covers the bank and the organic layer. A plurality of organic barrier portions are formed of organic materials, and are disposed on the first inorganic barrier layer. A second inorganic barrier layer is formed of the inorganic material, and covers the first inorganic barrier layer and the plurality of organic barrier portions. A recessed portion is formed on the bank and the first inorganic barrier layer (for example, the recessed portion is formed in an area which covers a contact hole), and a portion of the organic barrier portion is formed in the recessed portion.
US09583542B2 Organic light emitting display apparatus
An organic light emitting display apparatus includes: a plurality of pixels at a display area; a plurality of dummy pixels at a dummy area; and a plurality of repair lines that are connected to the plurality of dummy pixels and connectable to the plurality of pixels, wherein each of the plurality of dummy pixels includes: a compensation capacitive element; a driving transistor configured to output a driving current corresponding to a data signal applied to a gate electrode of the driving transistor; and a connection portion between a first electrode of the compensation capacitive element and the gate electrode of the driving transistor, and that is configured to electrically connect or separate the first electrode of the compensation capacitive element and the gate electrode of the driving transistor to or from each other based on a physical quantity applied to the connection portion.
US09583538B2 Semiconductor memory device having crossing interconnects separated by stacked films
According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
US09583533B2 LED device with embedded nanowire LEDs
A nanowire device and a method of forming a nanowire device that is poised for pick up and transfer to a receiving substrate are described. In an embodiment, the nanowire device includes a base layer and a plurality of nanowires on and protruding away from a first surface of the base layer. An encapsulation material laterally surrounds the plurality of nanowires in the nanowire device, such that the nanowires are embedded within the encapsulation material.
US09583531B2 Process for transferring circuit layer
A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, the routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.
US09583530B2 X-ray detector
To provide an X-ray detector facilitating the installing and replacement work of a module while reducing the possibility of breakage. An X-ray detector 50 detecting X-ray image data for each detection module includes: a detection module 7 provided with a protruding frame on a back side of a detection device detecting X-rays; and a guide frame 12 fitting into the protruding frame and removably supporting the detection device, wherein the guide frame 12 fixes the position of the detection device relative to the guide frame 12 by fitting. Therefore, fitting the protruding frame 8 into the guide frame 12 enables precise and easy installation/removal of the detection module. That is a detection module can be newly installed onto the guide frame without interfering each other with adjacent detection modules already installed while minimizing a space therebetween.
US09583528B2 Solid-state imaging device
A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.
US09583526B2 Solid-state image pickup element and solid-state image pickup element mounting structure
A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.
US09583519B2 Manufacturing method of a thin film transistor and pixel unit thereof
The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate, wherein the metal oxide layer is in a thin film transistor region; through a same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate for forming a gate region, source and drain regions for forming contact vias, a gate interface region, and a storage capacitor region, respectively. Through additional steps including etching, metallizing, and filling, a source contact via is formed in the source region, a drain contact via is formed in the drain region, and a connecting contact via is formed in the gate interface region, respectively.
US09583518B2 Display device and method of manufacturing the same
A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced.
US09583517B2 Polycrystalline oxide thin-film transistor array substrate and method of manufacturing same
This invention provides a polycrystalline oxide thin-film transistor (TFT) array substrate and a method of manufacturing the same. As the polycrystalline oxide thin film layer of the polycrystalline oxide TFT array substrate is formed by a two-step process according to the present invention, the ultra-high temperature annealing process required in the prior art is obviated, and the object of producing a polycrystalline oxide TFT array substrate by the existing manufacturing facilities of the amorphous oxide TFT array substrates is achieved without adding any special equipment or special operation, and it is easy to implement; meanwhile, the energy consumption is reduced as the high temperature annealing is no longer needed.
US09583515B2 Semiconductor device including substrate which is used in display devices
A semiconductor device (100T, 100B) includes: a substrate (30); a first metal layer (10) supported on the substrate (30), the first metal layer (10) including a plurality of first wires (12); an insulating layer (70) provided on the first metal layer (10); a second metal layer (20) provided on the insulating layer (70), the second metal layer (20) including a plurality of second wires (22); an insulative protection layer (80) covering part of each of the plurality of second wires (22), and an electrically-conductive layer (90) provided on the insulative protection layer (80). In a cross section including a boundary between a first region (R1) in which the insulative protection layer (80) is provided and a second region (R2) in which the insulative protection layer (80) is not provided, a surface of the insulating layer (70) which is on the insulative protection layer (80) side has a step between two of the second wires which adjoin each other.
US09583514B2 Thin film transistor array substrate
The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. The thin film transistor array substrate may comprise a substrate which has a plurality of gate lines extending in a column direction along a boundary of pixels, a plurality of data lines extending in a row direction along the boundary of the pixels, and at least one thin film transistor formed in the pixel region; a first insulating film which covers the thin film transistor; a color organic film which is disposed on the first insulating film and has a valley area formed with a valley by partial superimposition of organic films of different colors based on the data lines; a second insulating film which covers the color organic film and the valley area; and a pixel electrode which is disposed on the second insulating film and connected to the thin film transistor via a contact hole, wherein the thin film transistor array substrate is provided with a separating organic film which extends from the color organic film and is disposed between the valley area and the contact hole.
US09583511B2 Array substrate having integrated gate driver and method of fabricating the same
An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.
US09583510B2 Semiconductor device, display device, and method for manufacturing semiconductor device
A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion. The transparent conductive layer (Tc) is in contact with the end of the drain electrode and the second portion of the oxide semiconductor layer in the contact hole.
US09583504B2 Non-volatile storage device and method of manufacturing the same
According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
US09583500B2 Multilevel memory stack structure and methods of manufacturing the same
A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.
US09583498B2 Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
US09583495B2 Method for fabricating memory device
Provided is a method for fabricating a memory device including forming a stack layer on a substrate, and embedding a plurality of gate pillar structures and a plurality of dielectric pillars in the stack layer. The plurality of gate pillar structures and the plurality of dielectric pillars extend along a same direction and are alternately arranged, so that the stack layer is divided into a plurality of stack structures.
US09583492B2 Structure and method for advanced bulk fin isolation
A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.
US09583491B2 CMOS nanowire structure
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
US09583489B1 Solid state diffusion doping for bulk finFET devices
A method of forming a semiconductor device comprises forming a first fin on a substrate, depositing an insulator layer on the substrate adjacent to the first fin, removing a first portion of the insulator layer to expose a first portion of a sidewall of the first fin, depositing a layer of spacer material over the first portion of the sidewall of the first fin, removing a second portion of the insulator layer to expose a second portion of the sidewall of the first fin, depositing a first glass layer including a first doping agent over the exposed second portion of the sidewall of the first fin, and performing a first annealing process to drive the first doping agent into the first fin.
US09583488B2 Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
US09583484B2 Tipless transistors, short-tip transistors, and methods and circuits therefor
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
US09583483B2 Source and drain stressors with recessed top surfaces
An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
US09583482B2 High voltage semiconductor devices and methods of making the devices
A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.
US09583479B1 Semiconductor charge pump with imbedded capacitor
A charge pump for an integrated circuit includes a substrate, first and second transistors and a capacitor. The first transistor includes first source and first drain regions disposed within the substrate and defining a first channel therebetween. The first source and first drain regions are implanted with one of an n-type and a p-type dopant. The second transistor includes second source and second drain regions disposed within the substrate and defining a second channel therebetween. The second source and second drain regions implanted with the same type dopant as the first source region. The capacitor includes a metal terminal and a substrate terminal with a dielectric therebetween. The substrate terminal is disposed within the substrate and implanted with the same type dopant as the first source region. The substrate terminal contacts the first drain region and second source region within the substrate to provide electrical continuity therebetween.
US09583476B2 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
US09583475B2 Microelectronic package with stacked microelectronic units and method for manufacture thereof
A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
US09583470B2 Electronic device with solder pads including projections
An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.
US09583466B2 Etch removal of current distribution layer for LED current confinement
A method and structure for forming an array of LED devices is disclosed. The LED devices in accordance with embodiments of the invention may include a confined current injection area in which a current spreading layer protrudes away from a cladding layer in a pillar configuration so that the cladding layer is wider than the current spreading layer pillar.
US09583465B1 Three dimensional integrated circuit structure and manufacturing method of the same
Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
US09583461B2 Probing chips during package formation
A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.
US09583460B2 Integrated device comprising stacked dies on redistribution layers
Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.
US09583455B2 Semiconductor device
Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.
US09583451B2 Conductive pillar shaped for solder confinement
Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.
US09583445B2 Metal electromagnetic interference (EMI) shielding coating along an edge of a ceramic substrate
An electrical component may be mounted on a substrate such as a ceramic substrate. Contacts may be formed on upper and lower surfaces of the substrate. The electrical component may be soldered to the contacts on the upper surface. The contacts on the lower surface may be used to solder the substrate to a printed circuit. During manufacturing, it may be desirable to use metal traces on a ceramic panel to make connections to contacts on the substrate. Following singulation of the ceramic panel to form the ceramic substrate, some of the metal traces may run to the edge of the ceramic substrate. A folded tab of the printed circuit may form a shield that covers these exposed traces. A divided metal-coated groove or a row of divided metal-coated vias running along each edge of the substrate may also provide shielding.
US09583438B2 Interconnect structure with misaligned metal lines coupled using different interconnect layer
In some embodiments, an interconnect structure includes a first metal line, a second metal line and a first connection structure. The first metal line is formed in a first interconnect layer, extends in length substantially along a first direction and ends at a first end portion. The second metal line is formed in the first interconnect layer, starts from a second end portion and extends in length substantially along the first direction. The second metal line is misaligned with the first metal line in the first direction. The first connection structure couples the first metal line to the second metal line. The first connection structure includes a first end-to-end portion formed in a second interconnect layer different from the first interconnect layer, and is overlapped with the first end portion and the second end portion.
US09583437B2 Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
US09583434B2 Metal line structure and method
A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.
US09583433B2 Integrated device package comprising conductive sheet configured as an inductor in an encapsulation layer
An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.
US09583426B2 Multi-layer substrates suitable for interconnection between circuit modules
An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.
US09583424B2 Integrated circuit structure and method for reducing polymer layer delamination
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
US09583421B2 Recessed lead leadframe packages
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip.
US09583420B2 Semiconductor device and method of manufactures
A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.
US09583419B2 Semiconductor constructions having through-substrate interconnects
Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
US09583418B2 Chip embedded package method and structure
A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.
US09583415B2 Packages with thermal interface material on the sidewalls of stacked dies
A package includes a die stack that includes at least two stacked dies, and a Thermal Interface Material (TIM). The TIM includes a top portion over and contacting a top surface of the die stack, and a sidewall portion extending from the top portion down to lower than at least one of the at least two stacked dies. A first metallic heat-dissipating feature is over and contacting the top portion of TIM. A second metallic heat-dissipating feature has a sidewall contacting a sidewall of the sidewall portion of the TIM.
US09583413B2 Semiconductor device
A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator and the first chip.
US09583411B2 Fine pitch BVA using reconstituted wafer with area array accessible for testing
A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly, into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.
US09583400B1 Gate stack with tunable work function
A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
US09583399B1 Semiconductor device and manufacturing method thereof
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the first source/drain region. The semiconductor wire in the first source/drain regions is wrapped around by a second semiconductor material.
US09583398B2 Integrated circuit having FinFETS with different fin profiles
An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.
US09583394B2 Manufacturing method of semiconductor structure
The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.
US09583391B2 Wafer processing method
There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the modified layer forming step is set to a power that forms modified layers and cracks in such a manner that a wafer is allowed to be divided into individual device chips before the thickness of the wafer reaches a finished thickness and, after the wafer is divided into the individual device chips, the time until the thickness of the wafer reaches the finished thickness is such a time that damage due to rubbing of the individual device chips against each other is not caused through grinding under a predetermined grinding condition set in a back surface grinding step.
US09583389B2 Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
US09583388B2 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.
US09583387B2 Multilevel mask circuit fabrication and multilayer circuit
Circuit fabrication uses a multilevel mask to pattern a first conductor layer of a multilayer circuit. The first conductor patterning is to provide electrical isolation between the first conductor layer and a second conductor layer that one of overlies the multilevel mask and underlies the multilevel mask. With the second conductor layer overlying the multilevel mask, the electrical isolation is provided by undercutting the multilevel mask. Alternatively, with the second conductor underlying the multilevel mask, the first conductor includes a bridged gapped conductor and the electrical isolation may be provided by both the bridged gapped conductor and an insulating layer between the second conductor layer and the first conductor layer.
US09583386B2 Interlevel conductor pre-fill utilizing selective barrier deposition
A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
US09583383B2 Air gap forming techniques based on anodic alumina for interconnect structures
An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.
US09583382B2 Interconnection structure including air gap, semiconductor device including air gap, and method of manufacturing the same
A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.
US09583381B2 Methods for forming semiconductor devices and semiconductor device structures
Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of a second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.
US09583379B2 Inverted trapezoidal recess for epitaxial growth
A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.
US09583375B2 Water soluble mask formation by dry film lamination
Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
US09583373B2 Wafer carrier having cavity
A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.
US09583372B2 Structure for joining ceramic plate to metal cylindrical member
A member for semiconductor manufacturing device includes a susceptor which is a ceramic plate formed of AlN and a gas introduction pipe which is joined to the susceptor. An annular pipe joining bank is provided at a position of the susceptor facing a flange of the gas introduction pipe. In addition, a pipe brazed part is formed between the flange and the pipe joining bank. The flange has a width of 3 mm or more and a thickness of from 0.5 to 2 mm. It is preferable that the height of the pipe joining bank be 0.5 mm or more, the edge of the bank facing the outer edge of the flange. be chamfered as designated by C0.3 or more or rounded as designated by R0.3 or more.
US09583365B2 Method of forming interconnects for three dimensional integrated circuit
A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
US09583364B2 Processes and apparatus for preparing heterostructures with reduced strain by radial compression
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
US09583363B2 Processes and apparatus for preparing heterostructures with reduced strain by radial distension
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
US09583362B2 Metal gate structure and manufacturing method thereof
The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer. A thickness of a first portion of the barrier layer at the sidewall of the metal gate is substantially thinner than a thickness of the barrier layer at the bottom of the metal gate. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate trench in an ILD, forming a barrier layer in a bottom and a sidewall of the metal gate trench, removing a first portion of the barrier layer at the sidewall of the metal gate trench, and forming a work function metal layer conforming to the barrier layer.
US09583360B2 Substrate processing apparatus and substrate processing method
In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.
US09583354B2 Systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same
Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to light and/or heat. The freestanding film is then exposed to a laser beam in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.
US09583353B2 Lateral electrochemical etching of III-nitride materials for microfabrication
Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.
US09583348B2 Silane and borane treatments for titanium carbide films
Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.
US09583340B2 Semipolar nitride semiconductor structure and method of manufacturing the same
Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
US09583335B2 Method of forming dielectric films, new precursors and their use in semiconductor manufacturing
Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe2)3, Zr(EtCp)(NMe2)3, ZrCp(NMe2)3, Zr(MeCp)(NEtMe)3, Zr(EtCp)(NEtMe)3, ZrCp(NEtMe)3, Zr(MeCp)(NEt2)3, Zr(EtCp)(NEt2)3, ZrCp(NEt2)3, Zr(iPr2Cp)(NMe2)3, Zr(tBu2Cp)(NMe2)3, Hf(MeCp)(NMe2)3, Hf(EtCp)(NMe2)3, HfCp(NMe2)3, Hf(MeCp)(NEtMe)3, Hf(EtCp)(NEtMe)3, HfCp(NEtMe)3, Hf(MeCp)(NEt2)3, Hf(EtCp)(NEt2)3, HfCp(NEt2)3, Hf(iPr2Cp)(NMe2)3, Hf(tBu2Cp)(NMe2)3, and mixtures thereof; and depositing the dielectric film on the substrate.
US09583334B2 Gallium lanthanide oxide films
Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.
US09583333B2 Low temperature silicon nitride films using remote plasma CVD technology
Embodiments of the present invention generally provide methods for forming a silicon nitride layer on a substrate. In one embodiment, a method of forming a silicon nitride layer using remote plasma chemical vapor deposition (CVD) at a temperature that is less than 300 degrees Celsius is disclosed. The precursors for the remote plasma CVD process include tris(dimethylamino)silane (TRIS), dichlorosilane (DCS), trisilylamine (TSA), bis-t-butylaminosilane (BTBAS), hexachlorodisilane (HCDS) or hexamethylcyclotrisilazane (HMCTZ).
US09583332B2 Low temperature cure modulus enhancement
Implementations described herein generally relate to methods for dielectric gap-fill. In one implementation, a method of depositing a silicon oxide layer on a substrate is provided. The method comprises introducing a cyclic organic siloxane precursor and an aliphatic organic siloxane precursor into a deposition chamber, reacting the cyclic organic siloxane precursor and the aliphatic organic siloxane precursor with atomic oxygen to form the silicon oxide layer on a substrate positioned in the deposition chamber, wherein the substrate is maintained at a temperature between about 0° C. and about 200° C. as the silicon oxide layer is formed, wherein the silicon oxide layer is initially flowable following deposition, and wherein a ratio of a flow rate of the cyclic organic siloxane precursor to a flow rate of the aliphatic organic siloxane precursor is at least 2:1 and curing the deposited silicon oxide layer.
US09583326B2 Focusing ionization device and mass spectrometer using the same
A focusing ionization device includes a ball having a surface with a plurality of dimples and a metal needle located at one side of the ball and capable of generating corona discharge. The focusing ionization device is adapted for being disposed in a mass spectrometer in a way that the ball is located at a spray path of gaseous analytes and the metal needle is located adjacent to a sample inlet of a mass analyzer. When the gaseous analytes pass through the ball, the gaseous analytes can be gathered around the metal needle, which in turn are ionized to produce analyte ions to be transmitted into the mass analyzer by a potential difference. Therefore, the focusing ionization device of the present disclosure can effectively enhance the amount of the analyte ions entering into the mass analyzer, thereby improving ion transmission efficiency. As a result, a mass spectrometer equipped with the focusing ionization device may have increased signal intensity of analyte, lowered limit of detection (LOD), and minimized detection error.
US09583325B2 System and method of delicate membrane condensed phase membrane introduction mass spectrometry (CP-MIMS)
Systems and methods for analyzing a sample comprising an analyte selected from a volatile organic compound, a semi-volatile organic compound, a non-volatile organic compound, a polar organic compound and a halogenated non-volatile organic compound are provided. The systems comprises an ionization source, a flow cell or an immersion probe with a delicate membrane, the flow cell or immersion probe for accepting the sample, and the delicate membrane interface in fluid communication with the ionization source and a mass spectrometer. The flow cell system further comprises a simultaneously matched pumping in and out delivery (SMPIOD) system for delivering an acceptor phase comprising the analyte from the delicate membrane interface to the mass spectrometer at a constant acceptor flow pressure and a constant acceptor flow rate.
US09583321B2 Method for mass spectrometer with enhanced sensitivity to product ions
A mass spectrometry method comprises: introducing a first portion of a sample of ions including precursor ions comprising a first precursor-ion mass-to-charge (m/z) ratio into a first mass analyzer; transmitting the precursor ions from the first mass analyzer to a reaction or fragmentation cell such that a first population of product ions are continuously accumulated therein over a first accumulation time duration; initiating release of the accumulated first population of product ions from the reaction or fragmentation cell; continuously transmitting the released first population of product ions from the reaction cell to a second mass analyzer; transmitting a portion of the released first population of product ions comprising a first product-ion m/z ratio from the second mass analyzer to a detector; and detecting a varying quantity of the product ions having the first product-ion m/z ratio for a predetermined data-acquisition time period after the initiation of the release.
US09583316B2 Inert-dominant pulsing in plasma processing systems
A method for processing substrate in a processing chamber, which has at least one plasma generating source and a gas source for providing process gas into the chamber, is provided. The method includes exciting the plasma generating source with an RF signal having RF frequency. The method further includes pulsing the gas source, using at least a first gas pulsing frequency, such that a first process gas is flowed into the chamber during a first portion of a gas pulsing period and a second process gas is flowed into the chamber during a second portion of the gas pulsing period, which is associated with the first gas pulsing frequency. The second process gas has a lower reactant-gas-to-inert-gas ratio relative to a reactant-gas-to-inert-gas ratio of the first process gas. The second process gas is formed by removing at least a portion of a reactant gas flow from the first process gas.
US09583315B2 Plasma etching apparatus and plasma etching method
A plasma etching apparatus of the present disclosure etches a substrate by plasma of a processing gas. The plasma etching apparatus includes a processing container; a holding unit configured to hold a substrate; and an electrode plate. The plasma etching apparatus further includes configured to supply the processing gas to a space between the holding unit and the electrode plate and disposed in n (n is a natural number of two or more) regions of the substrate divided concentrically in a radial direction, respectively. In addition, the plasma etching apparatus further includes a high frequency power source configured to supply a high frequency power to at least one of the holding unit and the electrode plate so as to generate plasma. The plasma etching apparatus controls a flow rate of the processing gas.
US09583313B2 Plasma processing apparatus and plasma processing method
The plasma processing apparatus includes a dielectric member for defining a chamber, a gas introducing part for introducing a gas into the chamber, a discharge coil disposed on one side of the dielectric member and supplied with AC power to generate a plasma in the chamber into which the gas has been introduced, a conductor member disposed on the other side of the dielectric member and facing the discharge coil with the chamber of the dielectric member interposed therebetween, an AC power source for supplying AC voltage to the discharge coil, an opening communicating with the chamber and serving for applying the plasma to a substrate to be processed, and a moving mechanism for moving the substrate relative to the chamber so that the substrate passes across a front of the opening. The discharge coil is grounded or connected to the conductor member via a voltage generating capacitor or a voltage generating coil.
US09583312B2 Film formation device, substrate processing device, and film formation method
A film formation device to conduct a film formation process for a substrate includes a rotating table, a film formation area configured to include a process gas supply part, a plasma processing part, a lower bias electrode provided at a lower side of a position of a height of the substrate on the rotating table, an upper bias electrode arranged at the same position of the height or an upper side of a position of the height, a high-frequency power source part connected to at least one of the lower bias electrode and the upper bias electrode and configured to form a bias electric potential on the substrate in such a manner that the lower bias electrode and the upper bias electrode are capacitively coupled, and an exhaust mechanism.
US09583305B2 Exposure method using control of settling times and methods of manufacturing integrated circuit devices by using the same
An exposure method may include: radiating a charged particle beam in an exposure system comprising a beam generator, radiating the beam, and main and auxiliary deflectors deflecting the beam to determine a position of a beam shot; determining whether a deflection distance from a first position of a latest radiated beam shot to a second position of a subsequent beam shot is within a first distance in a main field area of an exposure target area, the main field area having a size determined by the main deflector; setting a settling time according to the deflection distance so that a settling time of the subsequent beam shot is set to a constant minimum value, greater than zero, when the deflection distance from the first position to the second position is within the first distance; and deflecting the beam using the main deflector based on the set settling time.
US09583303B2 Aligning a featureless thin film in a TEM
When preparing a Hole-Free Phase Plates (HFPP) a preferably featureless thin film should be placed with high accuracy in the diffraction plane of the TEM, or a plane conjugate to it. Two methods for accurately placing the thin film in said plane are described. One method uses a Ronchigram of the thin film while the TEM is in imaging mode, and the magnification of the Ronchigram is tuned so that the magnification in the middle of the Ronchigram is infinite. The second method uses electrons scattered by the thin film while the TEM is in diffraction mode. When the thin film does not coincide with the diffraction plane, electrons scattered by the thin film seem to originate from another location than the cross-over of the zero beam. This is observed as a halo. The absence of the halo is proof that the thin film coincides with the diffraction plane.
US09583299B2 Iridium tip, gas field ion source, focused ion beam apparatus, electron source, electron microscope, electron beam applied analysis apparatus, ion-electron multi-beam apparatus, scanning probe microscope, and mask repair apparatus
There is provided an iridium tip including a pyramid structure having one {100} crystal plane as one of a plurality of pyramid surfaces in a sharpened apex portion of a single crystal with <210> orientation. The iridium tip is applied to a gas field ion source or an electron source. The gas field ion source and/or the electron source is applied to a focused ion beam apparatus, an electron microscope, an electron beam applied analysis apparatus, an ion-electron multi-beam apparatus, a scanning probe microscope or a mask repair apparatus.
US09583297B2 Remote fuse operation indicator assemblies and related systems and methods
A fuse operation indicator assembly includes an elongate tube having first and second ends, a fuse striker receiving member at the first end of the tube and configured to receive a fuse striker, an actuating member at the second end of the tube and configured to be actuated responsive to the fuse striker member, and a detector configured to detect actuation of the actuating member.
US09583295B2 Circuit breaker contact arm
A contact arm for a circuit breaker includes a body extending along a body axis between a first end and a second end. The body includes an interior surface, an exterior surface, and a fin extending between the interior surface and the exterior surface. The body defines a fin opening adjacent the fin. The fin opening extends between the interior surface and the exterior surface. The interior surface defines a substantially hollow interior. A body opening is located at the first end in fluid communication with the interior. Air flows through the body opening, into the interior, and from the interior out through the fin opening to reduce a temperature of the contact arm.
US09583294B2 MEMS swtich with internal conductive path
A MEMS switch has a base formed from a substrate with a top surface and an insulator layer formed on at least a portion of the top surface. Bonding material secures a cap to the base to form an interior chamber. The cap effectively forms an exterior region of the base that is exterior to the interior chamber. The MEMS switch also has a movable member (in the interior chamber) having a member contact portion, an internal contact (also in the interior chamber), and an exterior contact at the exterior region of the base. The contact portion of the movable member is configured to alternatively contact the interior contact. A conductor at least partially within the insulator layer electrically connects the interior contact and the exterior contact. The conductor is spaced from and electrically isolated from the bonding material securing the cap to the base.
US09583293B2 Electromagnetic relay
An electromagnetic relay includes a coil, an armature, an iron core, a card, a first contact, and a second contact. The card is connected to the armature and formed of an insulating material. The first contact and the second contact are in contact when there is no flow of electric current through the coil. The first contact and the second contact are separated with the armature being attracted to the iron core to interpose the card between the first contact and the second contact when there is a flow of electric current through the coil.
US09583292B2 Modular electrical switch device comprising at least one unipolar cut-off unit and a switch assembly comprising such devices
A modular electrical switch device including: a cut-off unit including unitary cut-off units; an actuating unit of the unitary cut-off units including an electromagnetic actuator including a fixed cylinder head and a movable reinforcement; a mechanism allowing the actuating unit to be fixed to the cut-off unit; a quick attachment mechanism allowing removable fixing of the actuating unit on the cut-off unit, and including at least one coupling hook configured to fix and hold the cut-off unit to the actuating unit, and to engage with an actuating device of the unitary cut-off unit to transmit movement of the actuator.
US09583290B2 Solenoid device
A solenoid device includes at least one electromagnetic coil for generating a magnetic flux when energized, a fixed core constituting part of a magnetic circuit through which the magnetic flux passes, and plungers constituting the magnetic circuit together with the fixed core and configured to advance to and retract from the fixed core depending on whether the magnetic coil is energized or de-energized. The magnetic circuit is provided with a magnetic resistance part as a resistance for the magnetic flux. The plungers are configured to be attracted to the fixed core by energizing the electromagnetic coil.
US09583289B2 Electrical switching device
An electrical switching device including an electric power switching module including a block of three input terminals and three output terminals, each input or output terminal being connected to a stationary contact of an electrical switch also including a mobile contact, configured to switch between an open position and a closed position, the mobile contact configured to be moved by an electromagnetic drive mechanism, and a control module, including at least one control input terminal and at least one control output terminal. The control module includes the electromagnetic drive mechanism configured to be supplied by the control terminals to control a position of one of the mobile contacts. A supervision module includes an auxiliary input contact terminal and two auxiliary output contact terminals, the auxiliary input contact terminal being shared by the two auxiliary output contact terminals, the power module being removable separately from the control and supervision modules.
US09583283B2 Electrical contactor with movable arm
An electrical contactor has a first terminal having a fixed member with at least one fixed electrical contact, a second terminal, and at least one movable electrical contact in electrical communication with the second terminal. A dual-coil actuator is also provided and has a first drive coil drivable to open and close the movable and fixed electrical contacts, and a second non-drive coil feedback connected to induce a reverse flux to temper and stabilize a net flux. Control of a delay time of the opening and closing electrical contacts is thus possible, so as to be at or adjacent to a subsequent or next zero-crossing of an associated AC load current waveform.
US09583282B2 Clutch mechanism for energy storage device and gas insulated circuit breaker thereof
A clutch mechanism for an energy storage device is disclosed. In an embodiment, the clutch mechanism includes a loading gear, a driving gear, a one-way bearing, a sleeve, and a gear shaft comprising a gear portion and a clutch portion. The gear shaft includes multiple spheres, and a push rod and an elastic element which are located in a cavity of the gear shaft. The push rod includes a groove and can slide in the axial direction of the gear shaft. A pressure block is fixed to the driving gear, the pressure block being able to push the push rod to slide in the axial direction of the gear shaft, so as to unlock or lock the sleeve and the gear shaft. A gas insulated circuit breaker employing such a clutch mechanism is also disclosed.
US09583280B2 Electricity storage device
An electricity storage device maintains low internal resistance and high electric capacity. The nonaqueous-electrolytic-solution hybrid electricity storage device employs an anode into/from which lithium can be intercalated and deintercalated and a cathode including activated carbon, even after high-temperature storage and/or high-temperature charging/discharging. Specifically, this electricity storage device includes an anode into/from which lithium can be intercalated and deintercalated, a cathode that includes activated carbon, and a nonaqueous electrolytic solution, wherein the electricity storage device employs a nonaqueous electrolytic solution that includes at least one type of compound represented by one of general formulas (1) to (5). Details on the general formulas (1) to (5) are as described in the Description.
US09583277B2 Ultra-capacitor structures and electronic systems with ultra-capacitor structures
Ultra-capacitor structures and electronic systems and assemblies are provided. In one aspect, the ultra-capacitor structure is configured to selectively power and at least partially house electronic component(s) therein. In one embodiment, the ultra-capacitor structure includes a thermally conductive material facilitating dissipation of heat generated. In another embodiment, the ultra-capacitor structure includes an electrically conductive sheet facilitating electromagnetic shielding. In another aspect, an electronic system includes: an electronic device including electronic component(s); and a support structure physically receiving and electrically coupling to the electronic device, and including an ultra-capacitor structure configured to selectively power the electronic component(s) of the electronic device when electrically coupled to the support structure. In another aspect, an electronic assembly has a first region including electronic component(s), and a second region including an ultra-capacitor structure configured to selectively power the electronic component(s) of the electronic assembly, where the first region is spaced apart from the second region.
US09583276B2 Ionic liquid and power storage device including the same
An ionic liquid having high electrochemical stability and a low melting point. An ionic liquid represented by the following general formula (G0) is provided. In the general formula (G0), R0 to R5 are individually any of an alkyl group having 1 to 20 carbon atoms, a methoxy group, a methoxymethyl group, a methoxyethyl group, and a hydrogen atom, and A− is a univalent imide-based anion, a univalent methide-based anion, a perfluoroalkyl sulfonic acid anion, tetrafluoroborate, or hexafluorophosphate.
US09583274B2 Solid electrolytic capacitor, and method of manufacturing the same
Provided is a method of manufacturing a solid electrolytic capacitor that suppresses spreading up of a solution. The method includes forming a porous sintered body made of a valve metal and having an anode wire sticking out therefrom; forming an insulating layer made of a fluorine resin, so as to surround the anode wire; and forming a dielectric layer on the porous sintered body; forming a solid electrolyte layer on the dielectric layer, after forming the insulating layer. The process of forming the insulating layer includes melting granular particles made of a fluorine resin.
US09583268B2 Ceramic multi-layer capacitor based on BaTi(1-y)ZryO3
A ceramic multi-layer capacitor is disclosed. In an embodiment, the capacitor includes a main body having ceramic layers and first and second electrode layers arranged therebetween, wherein the ceramic layers includes a ceramic material on the basis of BaTi1-yZryO3 where 0≦y≦1, which has a temperature-dependent capacitance anomaly.
US09583267B2 Multilayer ceramic capacitor and board having the same
There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more.
US09583266B2 Dielectric ceramic composition, dielectric material and multilayer ceramic capacitor including the same
There is provided a dielectric ceramic composition including: a major component (a barium titanate-based base material); and a minor component, wherein the dielectric ceramic composition is sintered to form a sintered body having a fine structure, the fine structure includes first crystal grains in which a Ca content is lower than 2.5 mol % and second crystal grains in which a Ca content is between 2.5 mol % to 13.5 mol %, and the second crystal grains have a cross-sectional area ratio of 30% to 80% on the basis of 100% of an overall cross-sectional area of the fine structure.
US09583264B2 Capacitor device and electrical power conversion device
A capacitor device includes: a film capacitor element that has a coiled body in which an insulating layer and an electrification layer are laminated and wound together, and a pair of collector electrodes that are formed upon two opposite end faces of the coiled body; a case that has a capacitor housing portion within which the film capacitor element is received; a pair of inserts having insulation properties, one of which is inserted between one of the pair of collector electrodes and one of inner walls of the capacitor housing portion; and a mass of sealing and insulating material that is charged between the film capacitor element and the one of the inner walls of the capacitor housing portion.
US09583261B2 Iron powder for powder magnetic core and process for producing powder magnetic core
A powder magnetic core which exhibits a high compact density and a reduced iron loss can be obtained by compacting a soft magnetic powder in which the mass ratio of soft magnetic powder particles that pass through a filter having an opening of 75 μm is 95 mass % or higher relative to the whole amount of the soft magnetic powder and which has a mean strain of less than 0.100%.
US09583259B2 Wireless power transfer device and method of manufacture
Methods and apparatuses for wireless power transfer, and particularly, wireless power transfer to remote systems such as electric vehicles are disclosed. In one aspect, a wireless power transfer device is provided comprising a casing housing at least one component, with a first portion of the casing containing a set first flowable medium, and a second portion of the casing containing a second set flowable medium having a different density to that of the first set flowable medium. The casing can include a locating portion, with the locating portion in contact with a flowable medium set within the casing. In another aspect, a method of manufacturing a wireless power transfer device is provided. During manufacturing, a casing of the device may be loaded to maintain a desired shape while at least one component and a settable flowable medium are introduced into the casing.
US09583258B2 Device for limiting current having variable coil impedance
A device for limiting current with variable coil impedance includes a choke coil and a cooling device. An additional coil is made of a high-temperature superconducting material and is disposed in the choke coil such that the current is limited by the device without using an iron core.
US09583248B2 Solenoid and hydraulic pressure control apparatus having the same
In a solenoid of a hydraulic pressure control apparatus, a region adjacent to an oil flow guide portion of a stopper breathing passage is formed in a magnetism application region, through which a leakage magnetic flux leaking from a magnetic circuit at a time of turning on of a coil passes. Thereby, magnetic foreign objects made of iron or iron containing material are magnetically attracted to the leakage magnetic flux, so that intrusion of the foreign objects from an outside of the solenoid into a second volume variable chamber through the stopper breathing passage is limited.
US09583239B2 Electrode component with electrode layers formed on intermediate layers
An electrode component with electrode layers formed on intermediate layers includes a ceramic substrate, two intermediate layers formed on two opposite surfaces of the ceramic substrate, two electrode layers respectively formed on the two intermediate layers, two lead wires respectively connected to the electrode layers, and an insulating layer enclosing the ceramic substrate, the intermediate layers, the electrode layers, and portions of the two lead wires. The intermediate layer formed between the ceramic substrate and the electrode layer replaces the fabrication means for conventional silver electrode layer to provide good binding strength between the ceramic substrate and the electrode layer. Besides same electrical characteristics for original products, the electrode component can get rid of the use of precious silver in screen printed silver electrode and avoid pollution caused by evaporation and thermal dissolution of organic solvent while lowering the ohmic contact resistance between the electrode layer and the ceramic substrate.
US09583236B2 Method for manufacturing an improved overhead and underground cable lead-in cable for voice, data and video transmission services
A method of manufacturing an improved overhead or underground telephone lead-in cable for transmission services VVDL (voice, video, data and lead-in) that permits the connection of the users to the public telephone system with a high speed digital service link, besides the analog services required. The cable has at least one or a plurality of transmission circuits. One of the transmission circuit is formed by two metal conductor elements cooperating in turn to self-support the cable or a conventional type of impregnated fibers or kevlar tape. The second circuit which is formed by a stranded pair of conductors is impregnated with a swelling powder preventing moisture penetration.
US09583234B2 Insulated electric wire for automobile
The present invention relates to an insulated electric wire for an automobile containing a conductor and an insulating coating layer which coats the conductor, the insulating coating layer being formed of a non-crosslinkable resin composition containing 65 to 90 parts by weight of a polypropylene-based resin, 10 to 40 parts by weight of a metal hydroxide, 20 to 50 parts by weight of a bromine-based flame retardant, 5 to 30 parts by weight of antimony trioxide, and 2 to 15 parts by weight of a maleic acid-modified resin in the ratio and further containing at least one of 3 to 10 parts by weight of a polyethylene resin and 2 to 10 parts by weight of an ethylene-based copolymer.
US09583232B2 Electrically conductive rubber composition, transfer roller, and image forming apparatus
An electrically conductive rubber composition which can be efficiently and sufficiently foamed and crosslinked by means of a continuous crosslinking apparatus including a microwave crosslinking device and a hot air crosslinking device without generation of ammonia and carbon monoxide. The electrically conductive rubber composition comprises a rubber component, a crosslinking component for crosslinking the rubber component, and a foaming component including sodium hydrogen carbonate and citric acid.
US09583229B2 X-ray laser microscopy system and method
Improved system and method of X-ray laser microscopy that combines information obtained from both X-ray diffraction and X-ray imaging methods. The sample is placed in an ultra-cold, ultra-low pressure vacuum chamber, and exposed to brief bursts of coherent X-ray illumination further concentrated using X-ray mirrors and pinhole collimation methods. Higher resolution data from a sample is obtained using hard X-ray lasers, such as free electron X-ray lasers, and X-ray diffraction methods. Lower resolution data from the same sample can be obtained using any of hard or soft X-ray laser sources, and X-ray imaging methods employing nanoscale etched zone plate technology. In some embodiments both diffraction and imaging data can be obtained simultaneously. Data from both sources are combined to create a more complete representation of the sample.
US09583226B2 Cooling duct assembly for control element drive mechanism
The cooling duct assembly for a control element drive mechanism (CEDM) includes a skirt that is combined on a circumference of a reactor head and has first air channels in an inner side thereof; a lower duct that is combined with an upper side of the skirt, has second air channels that are connected to the first air channels, and is disposed to surround a circumference of the CEDM; and an upper duct, an edge of which is combined with the cooling air handling device, and other edge of which is detachably combined with the lower duct, wherein air that cools the CEDM is discharged to the outside after sequentially passing the first air channels, the second air channels, the upper duct, and the cooling air handling device, and the upper duct separated from the lower duct is lifted together with the cooling air handling device.
US09583224B2 Passive safety system of integral reactor
A passive safety system includes a containment, a reactor in the containment, a plurality of safety injection tanks connected with the reactor and having water and nitrogen gas to supply water thereof into the reactor through a safety injection line communicating to the first safety injection line upon a loss of coolant accident, a plurality of core makeup tanks connected with the reactor to supply water thereof into the reactor through a second safety injection line communicating to a safety injection line upon the loss of coolant accident, and a plurality of passive residual heat removal systems to remove residual heat from the reactor upon the loss of coolant accident or a non-loss of coolant accident. The water in each of the safety injection tank is stably supplied to the reactor for many hours by a differential head resulting from gravity or gas pressure.
US09583220B2 Centralized variable rate serializer and deserializer for bad column management
A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.
US09583217B2 Decoding method, memory storage device and memory control circuit unit
A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.
US09583214B2 Semiconductor circuit and leakage current test system
A semiconductor circuit includes a test control unit configured to generate a driving activation signal and a sensing activation signal in response to a command and an address; a pad; a driver configured to drive the pad to a predetermined level in response to activation of the driving activation signal; and a sensing unit configured to compare a voltage level of the pad with a reference voltage in response to activation of the sensing activation signal, and output a sensing signal.
US09583212B2 Domain wall injector device using fringing fields aided by spin transfer torque
A domain wall injector device uses electrical current passed across an interface between two magnetic regions whose magnetizations are aligned non-collinearly to create a domain wall or a series of domain walls in one of the magnetic regions. The method relies on a combination of innate fringing fields from the magnetic regions and the spin-transfer torque derived from the charge current. The device may be used to store data that are subsequently read out.
US09583210B1 Fuse-based integrity protection
Various systems and methods for implementing fuse-based integrity protection are described herein. A system for validating a read-only memory (ROM), the system comprising a ROM reader logic, implemented at least partly in hardware, to: access a read-only memory (ROM) having a plurality of permanently programmable electric couplings (PPECs), the PPECs having been programmed; survey a number of permanently altered PPECs in the set of PPECs to produce a counter value; read a binary representation of the counter value from PPEC values stored as a PPEC signature; and read a binary representation of the binary complement of the counter value from PPEC values in the PPEC signature; and a ROM validation logic, implemented at least partly in hardware, to verify the integrity of the ROM using a combination of at least two of: the counter value, the binary representation of the counter value, and the binary representation of the binary complement of the counter value.
US09583209B1 High density memory architecture
Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.
US09583206B2 Data storage device having reflow awareness
A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value.
US09583205B2 Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory
In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVSΔ) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVSΔ values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.
US09583203B2 Semiconductor memory device and operation method thereof
A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.
US09583200B2 Non-volatile semiconductor memory device and memory system in which write operation is resumed after being suspended for an interrupt operation
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
US09583195B2 Systems, methods and devices for a memory having a buried select line
Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.
US09583193B2 Compact memory device of the EEPROM type with a vertical select transistor
Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.
US09583192B1 Matchline precharge architecture for self-reference matchline sensing
The present disclosure relates to content addressable memories (CAM), and more particularly, to a searchable CAM structure having self-reference matchline precharge and local feedback control and method of use. The present disclosure includes a structure which includes: a sense line connected to a sensing device; a feedback line connected to the sense line at a tap point between a first end and a second end of the sense line; and a local precharge controller connected to the tap point by the feedback line to control precharging of the sense line according to a state of the feedback line.
US09583188B2 Semiconductor memory device including rewriting operation for improving the long-term reliability of the resistance variable element
A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.
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