| Document | Document Title |
|---|---|
| US09571237B2 |
Wireless transfer device and method for control of wireless transfer band
A wireless transfer device (100) is provided with: a transfer band control unit (13) for deciding upon a transfer band, on the basis of the result of a comparison of communication quality information pertaining to wireless communication, and a predetermined band control threshold value; a modulation scheme control unit (14) for deciding on a modulation scheme, on the basis of the result of a comparison of communication quality information and a predetermined modulation control threshold value; a transmission process unit (11) for controlling the transfer band for packet signals on the basis of the transfer band decided upon by the transfer band control unit (13), and outputting packet signals; and a wireless transceiver unit (12), for performing a modulation process on the packet signals output by the transmission process unit (11), doing so on the basis of the modulation scheme decided upon by the modulation scheme control unit (14). The band control threshold value and the modulation control threshold value are different values. In so doing, loss of high-priority packet signals, as well as transient fluctuations of transfer delay time, are avoided. |
| US09571234B2 |
Retransmission of data lost between a sender and a receiver
A method is provided for receiving a realtime data stream transmitted at a given speed in the form of packets between a transmitter and a receiver in a telecommunication network. The receiver has a buffer memory for storing the received packets. The method includes the following steps after detection of a loss of packets: requesting retransmission of the lost packets at a speed that is higher than the given speed; receiving retransmitted packets and realtime packets, the retransmitted packets having been transmitted with priority in relation to the realtime packets; and storing the retransmitted packets in the buffer memory. |
| US09571232B2 |
System and method for faster than Nyquist transmission
A method for operating a receiving device includes determining reliability ratings for undecoded data streams in a received transmission, selecting an undecoded data stream in the received transmission in accordance with the determined reliability ratings, thereby producing a selected data stream, and decoding the selected data stream with a decoding trellis, thereby producing a data symbol. The method also includes updating the decoding trellis in accordance with the data symbol, and repeating the selecting, the decoding, and the updating for remaining undecoded data streams in the received transmission. |
| US09571223B2 |
System and method for wavelength conversion and switching
A network component comprising at least one processor configured to implement a method comprising collecting wavelength availability information associated with a wavelength switched optical network (WSON), receiving a path computation request to transport a signal through the WSON, calculating at least one route through the WSON for the signal, and assigning at least one wavelength for the signal to use along the route. Also disclosed is a network comprising a first path computation element (PCE) configured to compute at least one route for a signal between a source and a destination, and a second PCE in communication with the first PCE, wherein the second PCE is configured to receive the route from the first PCE and assign at least one wavelength to the route. |
| US09571218B2 |
Power efficient subcarrier aggregator and subcarrier combiner for multi-direction variable optical transceiver
A multi direction variable transceiver including a transmitter comprising a subcarrier aggregator including at least one variable transmitter splitter and at least one variable transmitter coupler. The transceiver typically includes a receiver having at least one variable receiver splitter and at least one variable receiver coupler. In some examples, each of the transmitter and the receiver may include a controller for dynamically adjusting a splitting ratio for at least one of the variable receiver splitter, variable receiver coupler, variable transmission splitter and variable transmission coupler. |
| US09571217B2 |
Method and apparatus for detecting inter-cell interference in mobile communication system
A method and an apparatus for detecting inter-cell interference in a mobile communication system are provided. A base station receives a reference signal (RS) from a terminal, generate one or more interference candidate RSs, calculate a cross correlation of the one or more interference candidate RSs and the received RS, estimate at least one of a size of a Resource Block (RB) an offset of the RB, a group index (U), and a cyclic shift (CS) by using a preset number of interference candidate RSs in an order of the large cross correlation. The base station further removes an interference signal or performs a direct reduction by using at least one of the estimated RB size, the RB offset, the timing offset, and the group index (U). According to the present disclosure, it is beneficial to mitigate or cancel inter-cell interference problem on an uplink transmission without any assistance of neighbor base stations and/or adjacent cells in a wireless communication system. |
| US09571213B2 |
Tag generation method in broadcast encryption system
A tag generation method for generating tags used in data packets in a broadcast encryption system is provided. The method includes detecting at least one revoked leaf node; setting a node identification (node ID) assigned to at least one node among nodes assigned node IDs at a layer 0 and to which the at least one revoked leaf node is subordinate, to a node path identification (NPID) of the at least one revoked leaf node at the layer 0; generating a tag list in the layer 0 by combining the NPID of each of the at least one revoked leaf nodes at the layer 0 in order of increment of node IDs of the corresponding at least one revoked leaf nodes; and generating a tag list in a lowest layer by repeatedly performing the setting and generation operation down to the lowest layer. |
| US09571207B2 |
Electronic quantum information probability transfer
Digital communication systems utilizing entangled qubits are disclosed. The disclosed systems and component sending devices and receiving devices exploit selective entanglement swapping to transfer an entangled state between the sending device and the receiving device. Each device includes pairs of qubits that are independently entangled with pairs of qubits in the other device. By selectively entangling the qubits within a pair in the sending device, the qubits of the corresponding pair in the receiving device also are selectively entangled. When the qubits are entangled, they are projected onto a particular entangled state type. Though no information may be transferred through selective entanglement of one qubit pair, systems of the present disclosure determine whether a set of pairs of qubits are entangled by determining whether the distribution of pairs is a correlated or uncorrelated distribution (a probabilistic approach) and transform the distribution type to a classical bit of data. |
| US09571203B2 |
Optical modulator and optical transmitter
An optical modulator includes a package that accommodates therein a first substrate and a second substrate different from the first substrate, and outside the package, a flexible circuit board. The first substrate has plural optical modulating units disposed thereon in parallel and each including a Mach-Zehnder optical waveguide. Plural first signal line paths corresponding to the optical modulating units are disposed on the second substrate. Plural second signal line paths corresponding to the optical modulating units are disposed on the flexible circuit board. Electrical lengths of the second signal line paths are different from one another. Electrical lengths of signal paths that span from input ends of the second signal line paths corresponding to the optical modulating units to base points on signal electrodes, via the first signal line paths, are equal to one another. |
| US09571200B2 |
Transmitter optical signal to noise ratio improvement through receiver amplification in single laser coherent systems
A transceiver having an improved transmitter optical signal to noise ratio, and methods of making and using the same. |
| US09571198B2 |
Compensation of non-linear transmitter impairments in optical communication networks
An optical transceiver comprises a transmitter configured to transmit a first signal, and a receiver coupled to the transmitter and configured to receive a first compensation, wherein the first compensation is based on a pattern-dependent analysis of the first signal, and provide the first compensation to the transmitter, wherein the transmitter is further configured to compensate a second signal based on the first compensation to form a first compensated signal, and transmit the first compensated signal. An optical transmitter comprises a digital signal processor (DSP) comprising a compensator, a digital-to-analog converter (DAC) coupled to the DSP, a radio frequency amplifier (RFA) coupled to the DAC, and an electrical-to-optical converter (EOC) coupled to the RFA. An optical receiver comprises an optical-to-electrical converter (OEC), an analog-to-digital converter (ADC) coupled to the OEC, and a digital signal processor (DSP) coupled to the ADC and comprising a calibrator. |
| US09571197B2 |
Mobile communication repeater integrated monitor device, and method and system for mobile communication relay and information provision
An integrated mobile communication repeater monitoring device, and method and system for mobile communication relay and information provision, is provided. Signals received from communication networks are divided into signals of mobile communication channels and signals of data channels, mobile communication services are provided to on the basis of the signals of the mobile communication channels, and data is displayed on the basis of the signals of the data channels. |
| US09571194B2 |
Near-field connectivity for hosted payloads
A system and method for wirelessly communicating between a host bus of a spacecraft and a secondary payload. In one configuration, the host bus and secondary payload each include a wireless interface for establishing a radio or optical communications link thereby allowing for the elimination of a complex wiring harness connected between the host bus and the secondary payload. |
| US09571191B2 |
Information communication method
An information communication method of transmitting a signal using a change in luminance is provided. The information communication method includes: determining a pattern of the change in luminance, by modulating the signal to be transmitted; and transmitting the signal, by at least one light emitter changing in luminance according to the determined pattern of the change in luminance. In the determining, a first luminance change pattern corresponding to a body, a second luminance change pattern indicating a header for specifying the body, and a third luminance change pattern indicating another header different from the header are determined. In the transmitting, the header, the body and the other header are transmitted by the at least one light emitter changing in luminance according to the first luminance change pattern, the second luminance change pattern, the first luminance change pattern and the first luminance change pattern in the stated order. |
| US09571189B2 |
In-service monitoring of a fiberoptic network
An optical fiber breakage point may be located by coupling to the optical fiber an out-of-band optical test signal modulated at a periodic modulation pattern. A distance to the breakage point may be determined from a difference between modulation patterns of transmitted and received test signals. |
| US09571186B2 |
Multiple-acquisition OTDR method and device
An OTDR device and method for characterizing one or more events in an optical fiber link are provided. A plurality of light acquisitions is performed. For each light acquisition, test light pulses are propagated in the optical fiber link and the corresponding return light signals from the optical fiber link are detected. The light acquisitions are performed under different acquisition conditions, for example using different pulsewidths or wavelengths. Parameters characterizing the event are derived using the detected return signal from at least two of the plurality of light acquisitions. |
| US09571179B2 |
System and method for multi-user multiplexing
A relay node is described herein, the relay node comprising a network connectivity device configured to receive a plurality of medium access control layer (MAC) packet data units (PDUs) from a plurality of user agents; a processor configured to multiplex the plurality of MAC PDUs to form a Super-MAC PDU; and wherein the network connectivity device is further configured to transmit the Super-MAC PDU to an access node. |
| US09571173B2 |
Enforcing constant modulus and finite alphabet properties in adaptive and dual-stage codebooks
Methods and apparatus for enforcing codebook properties (e.g., constant modulus and/or finite alphabet) in adaptive and dual-stage codebooks are described. One example method generally includes receiving multiple feedback aspects of a channel for wireless communications determining multiple codewords based on the multiple feedback aspects, determining a final precoding matrix based on the multiple codewords, enforcing at least one codebook property in at least one of the multiple codewords or the final precoding matrix, applying the final precoding matrix to a plurality of spatial streams to form precoded spatial streams, and transmitting the precoded spatial streams. For certain aspects, enforcing the at least one codebook property includes quantizing elements in each of the multiple codewords and/or the final precoding matrix to the nearest value in a finite alphabet or to increase a performance metric. |
| US09571170B2 |
Method for mapping and demapping resource in a wireless communication system and an apparatus thereof
A method and apparatus for mapping/demapping a resource efficiently in a wireless communication system are provided. A resource mapping method of a transmitter in a wireless communication system includes precoding pairs of symbols, arranging the pairs of precoded symbols adjacently in a resource block, and transmitting the pairs of precoded symbols in the resource block. |
| US09571169B2 |
Mobile device assisted coordinated multipoint transmission and reception
Idle mobile devices are used as cooperating devices to support coordinated multipoint transmission and reception for uplink and downlink communications between a primary mobile device and its serving base station. For uplink communications, the cooperating mobile devices receive the uplink transmission from the primary mobile device and retransmit the received data signal to the serving base station for the primary mobile device. For downlink communications, the cooperating mobile devices receive the downlink transmission from the serving base station and retransmit the received data signal to the primary mobile device. |
| US09571164B1 |
Remote authentication using near field communication tag
An apparatus comprises a processing device comprising NFC interface circuitry, network interface circuitry, a memory and a processor coupled to the memory. The processing device is configured to establish an NFC connection with an NFC tag using the NFC interface circuitry, establish a network connection with an authentication server using the network interface circuitry, and forward one or more messages between the NFC tag and the authentication server, the one or more messages comprising messages of a challenge/response authentication protocol performed between the NFC tag and the authentication server. Responsive to a successful completion of the challenge/response authentication protocol between the NFC tag and the authentication server, the processing device is authenticated to the authentication server. |
| US09571163B1 |
Methods and apparatus for determining nearfield localization using phase and RSSI diversity
Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength. |
| US09571159B2 |
Data communication over power supply lines of an electronic system
Disclosed are various embodiments for communicating information between various electronic components. A local device may comprise a transmitter to convert communication signals into modulated signals. Modulated signals are injected into a shared power supply line. The remote device may comprise a receiver for identifying the injected signal, demodulating the injected signal, and processing the demodulated signal. |
| US09571156B2 |
Burst triggered signal analysis
An apparatus can include a detector configured to detect a burst event for a selected frequency of a digital input signal having a predetermined bandwidth. The detector can provide a burst trigger, in response to detecting the burst event relative to a threshold, and provide other burst data for the detected burst event. A signal analyzer can be configured to measure signal information for another selected frequency of the digital input signal in response to the burst trigger. The signal analyzer can provide corresponding analysis data based on the measured signal information, the burst trigger, the other burst data, and the corresponding analysis data can be stored in memory. |
| US09571155B2 |
Method of startup sequence for a panel interface
A system for starting a point-to-multi-point serial communications system. The system includes a transmitter having a sync connection and a plurality of data outputs and a plurality of receivers, each of the plurality of receiver having a sync connection and a data input; the data input of each of the plurality of receivers being connected to a respective one of the plurality of data outputs of the transmitter; and the sync connection of the transmitter being connected, by a conductor, to the sync connection of each of the plurality of receivers, each of the plurality of receivers comprising a first impedance and a first switch, the first impedance and the first switch configured to establish, when the first switch is closed, a current path between the sync connection of the receiver and a first voltage source in the receiver. |
| US09571150B2 |
Screen protection using actuated bumpers
An electronic device includes at least one screen. One or more bumpers are moveable between at least a stowed position where the bumper is flush or below the screen and a deployed position where at least a portion of the bumper projects above the screen. One or more sensors detect when the electronic device is subject to one or more drop events. When a drop event is detected, the bumper moves to the deployed position, protecting the screen. In various implementations, the bumper may be moveable by a push-push mechanism or a magnet assisted actuator mechanism. In other implementations, the bumper may include piezoelectric material to which voltage can be applied to move the bumper. |
| US09571148B2 |
Communications control between mobile device and peripheral device
A non-transitory computer-readable medium can include instructions for performing a method that includes docking a mobile device with a docking station using at least one physical connection and at least one wireless connection to provide communication between the mobile device and the docking station. One of the physical or wireless connections can be selected for providing a signaling channel for communication of signaling data between the mobile device and the docking station. Independently of the signaling channel, one of the physical or wireless connections can be selected for providing a media channel for communication of media data between the mobile device and the docking station. |
| US09571146B2 |
Detection and assessment of radio frequency emissions
A device adapted to fit within, or to be positioned adjacent to, a cellular handset or other personal communication device, for remedying the potentially harmful effect on humans or animal life of RF transmissions, and including an antenna responsive to the presence of RF radiation generated by the handset, signal analysis means for identifying the type of RF transmissions detected which is coupled to activate remedial signal generation means, which is arranged to provide a noise signal to a coil for providing an electromagnetic field in the vicinity of the handset, to disrupt the potentially harmful effects of the RF transmissions. |
| US09571139B2 |
Reference circuits for biasing radio frequency electronics
Reference circuits for biasing radio frequency electronics are provided herein. In certain implementations, a gallium arsenide die includes a power amplifier configured to provide amplification to a signal, a reference voltage circuit including an output terminal that provides a reference voltage, and a mirror circuit configured to bias the power amplifier based on the reference voltage. The reference voltage circuit includes a bipolar transistor, a field effect transistor, and a circuit portion that generates a voltage that is proportional to absolute temperature. The reference voltage circuit generates the reference voltage based on a sum of a base-to-emitter voltage of the bipolar transistor, a turn-on voltage of the field effect transistor, and the voltage that is proportional to absolute temperature. |
| US09571137B2 |
Single tone RF signal generator
A single tone RF signal generator and a method of generating a single tone RF signal. The single tone RF signal generator includes an output and a power amplifier that has an input. The power amplifier is operable to receive an RF signal including a first harmonic corresponding to a single tone signal to be produced by the signal generator. The power amplifier is also operable to amplify the RF signal. The power amplifier is further operable to provide the amplified RF signal to the output of the signal generator. The single tone RF signal generator further includes a feedback circuit connected between the output of the signal generator and the input of the power amplifier. The feedback circuit is configured to add one or more predistortion harmonics to the RF signal received by the power amplifier for cancelling harmonics in the amplified RF signal provided by the power amplifier. |
| US09571136B2 |
Apparatus for transmitting and receiving signals in radio frequency system
An apparatus for receiving signals in a radio frequency system includes a low noise amplifier that amplifies and filters a signal received from an antenna; a first frequency mixer that mixes the signal output from the low noise amplifier and an oscillation signal supplied from a local oscillator to create a signal of an intermediate frequency; a second frequency mixer that mixes the signal of an intermediate frequency and one or more oscillation signals that have an offset added to have different frequency channels, which have a predetermined bandwidth, to create one or more signals of a baseband frequency; a channel selection filter that divides one or more signals generated in the second frequency mixer into one or more different frequency channels having a predetermined bandwidth using the offset; and an amplifier that amplifies the signals that have been filtered in the channel selection filter. |
| US09571131B2 |
Signal generating method and signal generating device
A transmission method of simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals. One of signal generation processing in which phase change is performed and signal generation processing in which phase change is not performed is selectable, thereby improving general versatility in signal generation. |
| US09571130B2 |
Method and apparatus for encoding and decoding in electronic device
A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy matrix is generated using the at least one parity symbol. A Cauchy submatrix is configured from the Cauchy matrix based on the number of at least one lost data symbol and an inverse matrix of the Cauchy submatrix is calculated. At least one parity symbol corresponding to the at least one lost data symbol is updated. The at least one lost data symbol is recovered using the updated at least one parity symbol. |
| US09571129B2 |
Method and arrangement for decoding a signal encoded by a tail-biting code
A method of decoding a signal that has been encoded by a tail-biting code based on at least one encoding parameter is disclosed. The at least one encoding parameter may be a trellis size or a quantity of aggregated encoding elements or a code rate. The method is suitable for use in a communication device and comprises receiving the signal, performing a first decoding attempt of the signal based on a first set of starting state metrics and a first encoding parameter hypothesis, the first decoding attempt resulting in a first set of ending state metrics. The method further comprises performing, if the first decoding attempt fails, a second decoding attempt of the signal based on a second set of starting state metrics based on the first set of ending state metrics and a second encoding parameter hypothesis different from the first encoding parameter hypothesis. |
| US09571128B2 |
Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration and flash age
A data retention methodology for use in electrically rewritable nonvolatile storage systems is disclosed. The methodology collects characteristic data of the storage system (e.g., time stamps, program/erase cycles, sensed temperature over time, and others) and uses at least a portion of that data to associate various data retention schemes with the collected characteristic data. At power-on, the methodology determines a duration of a time during which power was not supplied to the storage system. The methodology also uses the power-on time to trigger the selection of an appropriate data protection scheme (e.g., enhanced ECC and/or read/scrub frequency). Dynamic selection and adjustment of the applied protection scheme may be based on the predetermined and/or calculated association between various protection schemes and the collected characteristic data of the storage system. |
| US09571125B2 |
Systems and methods of vector-DMA cache-XOR for MPCC erasure coding
System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two. |
| US09571122B2 |
Enhanced data compression for sparse multidimensional ordered series data
Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format. |
| US09571121B2 |
Electrochemical sensing module
A sensing circuit for an electrochemical sensor includes a digital-to-analog converter (DAC), an operational amplifier, an instrumentation amplifier, and an analog-to-digital converter (ADC). The DAC generates a biased ground voltage signal which is received by the operational amplifier. The operational amplifier creates a high current biased voltage on one of a pair of terminals connected to the electrochemical sensor. The instrumentation amplifier receives a signal from the pair of terminals, and generates an output representative of a voltage across the pair of terminals with reference to the high current biased ground voltage signal. The ADC converter receives the output and derives an actual voltage reading taken by the electrochemical sensor. |
| US09571119B2 |
Defeat of aliasing by incremental sampling
A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably. |
| US09571117B2 |
Digital-analog conversion apparatus and method
An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier. |
| US09571116B2 |
Circuit and method of adaptive filtering digital calibration of ADC
An adaptive filtering digital calibration circuit of ADC, which includes a control module, a fixed-point adder, and a fixed-point multiplier; the control module includes a finite-state machine, a shift register, and a register array; the fixed-point adder allows an addend and an augend to be added together after being encoded; the control module controls to complete all the calibration algorithmic operation, which includes the following steps: the control module controls to obtain an original binary value from an external ADC; calculating an error value according to weight and disturbance signals, and carrying out the weight updating operation and the disturbance signal updating operation according to the error value; carrying out the gain calibration operation; and carrying out the final result operation. The present invention also discloses a method of the adaptive filtering digital calibration of ADC. |
| US09571115B1 |
Analog to digital converter with high precision offset calibrated integrating comparators
An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples. |
| US09571114B1 |
SAR ADC performance optimization with dynamic bit trial settings
An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits. |
| US09571111B1 |
System and method to speed up PLL lock time on subsequent calibrations via stored band values
A method and apparatus and computer program product for calibrating a Phase Lock Loop (PLL) that reduces a PLL lock time for subsequent calibrations to thereby improve an overall system time and latency. The system and method for calibrating obviates effect of Process, Voltage and Temperature to achieve a faster PLL lock. |
| US09571103B2 |
Lookup table and programmable logic device including lookup table
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of a capacitor and the input of an inverter, and a source is connected to a first wiring. The other electrode of the capacitor is connected to a second wiring. In such a memory element, the potential of the second wiring is complementary to the potential of the first wiring when writing data; accordingly, the potential of the drain of the transistor, i.e., the potential of the input of the inverter can be higher than the high potential of the inverter. Thus, shoot-through current of the inverter at this time can be significantly reduced. As a result, power consumption in a standby state can be significantly reduced. |
| US09571096B2 |
Touch panel based switch
A touch panel-based switch includes a control circuit layer, a sensing layer, a dielectric layer, and a touch operation layer, stacked in the order. The sensing layer electrically connected to the control circuit layer includes plural sensing cell, and the dielectric layer is flexible. The touch operation layer is flexible as well and includes a button area and an adjacent non-button area. The button area includes a ground plane stacked on the dielectric layer and a first touch cover stacked on the ground plane, and the non-button area includes a second touch cover stacked on the dielectric layer. Plural though openings are provided in the button area corresponding to the sensing cells such that a portion of the dielectric layer is exposed. |
| US09571094B2 |
Switch circuit
To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even when a positive or negative voltage is inputted to an input terminal, and thereby reduces the risk of latch-up. A switch circuit is comprised of NMOS transistors, and the gates of the NMOS transistors are controlled by an output voltage of a boosting circuit, thereby making it possible to reliably control transmission or shut-off of a voltage from GND to VDD. |
| US09571093B2 |
Half bridge driver circuits
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. |
| US09571092B2 |
Cascaded high voltage switch architecture
Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line. |
| US09571090B2 |
Method for compensating thin film transistor threshold voltage drift
A method for compensating a threshold voltage drift of a thin film transistor comprises: controlling a drain and a gate of the thin film transistor to have a same voltage; and keeping the voltage at the gate of the thin film transistor unchanged and controlling the voltage at the drain of the thin film transistor to be equal to a voltage at a source of the thin film transistor. |
| US09571088B2 |
Semiconductor device
A semiconductor device includes a transistor; a diode configured to be connected in reverse-parallel with the transistor; a sense transistor configured to generate a sense current depending on a current flowing in the transistor; a sense diode configured to generate a sense diode current depending on a current flowing in the diode; a resistor part configured to have one terminal connected with an emitter of the sense transistor and an anode of the sense diode, and another terminal connected with an emitter of the transistor and an anode of the diode, and to have the sense current or the sense diode current flow in the resistor part; and a resistance value control unit configured to differentiate a resistance value of the resistor part for a case where the sense current flows in the resistor part, and for a case where the sense diode current flows in the resistor part. |
| US09571086B1 |
Bi-directional switch
A bi-directional switch that includes a first terminal, a second terminal, and a plurality of ballast circuits is provided. Each ballast circuit includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a first input connector, a first output connector, a first body, and a first body diode, and a second MOSFET comprising a second input connector, a second output connector, a second body, and a second body diode. Each first input connector is coupled to the first terminal, each second input connector is coupled to the second terminal, and each first output connector is coupled only to the second output connector of the second MOSFET that is in a same ballast circuit. |
| US09571085B2 |
High voltage driver
The invention concerns a high voltage driver comprising: first and second cascoded transistors (102, 104) adapted to generate an output signal (VOUT) based on a first voltage signal (VSL) having a first voltage range and on a second voltage signal (VSH) having a voltage range shifted with respect to the first voltage range, the output signal having a second voltage range greater than the first voltage range; and a pulse generator (128) comprising a passive high-pass filter adapted to generate voltage pulses based on at least one of the first and second voltage signals and to provide the voltage pulses to a control node of at least one of the first and second transistors. |
| US09571083B2 |
All-digital delay-locked loop tuning method with randomized LSB-tuning
In some example embodiments, there may be provided an apparatus. The apparatus may include a delay line including a plurality of cells; and tuning circuitry coupled to the delay line and configured to generate a first output and a second output to tune the delay of the delay line, wherein the first output tunes in aggregate the plurality of cells of the delay line, and wherein the second output tunes each of the plurality of cells separately. Related methods, systems, and articles of manufacture are also disclosed. |
| US09571082B2 |
High resolution time-to-digital convertor
A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal. |
| US09571080B2 |
Delay-locked loop arrangement and method for operating a delay-locked loop circuit
Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal. |
| US09571076B2 |
Bidirectional delay circuit and integrated circuit including the same
A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal. |
| US09571075B1 |
Input voltage clamp with signal splitting and cross-over capabilities
An integrated circuit with input voltage clamping circuitry for receiving an input signal from external devices is provided. The input voltage clamping circuitry may include a voltage splitting and clamping circuit, a selectively enabled transmission gate circuit, and a digitization and clamping circuit. The voltage splitting and clamping circuit may be configured to split the input signal into at least two separate components each of which is limited to a predetermined voltage swing. The transmission gate circuit may be selectively enabled to provide full rail signaling when the input signal has a power supply level that is below a predefined threshold. The digitization and clamping circuit may include a Schmitt trigger translation for converting the split signal components to a digitized signal that is clamped down to the predefined threshold. |
| US09571074B2 |
Efficient skew scheduling methodology for performance and low power of a clock-mesh implementation
According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model. |
| US09571072B2 |
Frequency multiplication circuit, electronic device and moving object
A frequency multiplication circuit includes a delay circuit that has a clock signal having a period input thereto and delays the signal by a time, an exclusive OR circuit that has the clock signal and a signal from the delay circuit input thereto and outputs a signal serving as an exclusive OR between the clock signal and the signal from the delay circuit, and a signal correction circuit that has a signal from the exclusive OR circuit input thereto and corrects the input signal to output the resultant. The length of the time is a length other than n×T/4 (n is an integer). The signal correction circuit attenuates a signal having a second frequency based on T/2, rather than a signal having a first frequency based on the time τ. |
| US09571071B2 |
Frequency synthesizer circuit
The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer. |
| US09571069B2 |
Implementing clock receiver with low jitter and enhanced duty cycle
A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry. |
| US09571068B1 |
Power gating circuit and control method for power gating switch thereof
A power gating circuit and a control method for power gating switch thereof are provided. The power gating circuit includes a first switch, the power gating switch, a pre-charge circuit, and a control circuit. A first terminal and a second terminal of the first switch are coupled to a first voltage and the control terminal of the power gating switch, respectively. A first terminal and a second terminal of the power gating switch are coupled to a second voltage and a function circuit, respectively. An input signal defines a powered period of the function circuit. According to the input signal, the pre-charge circuit pre-charges the control terminal of the power gating switch during the first sub-period of the powered period, and the control circuit controls the first switch to charge the control terminal of the power gating switch by the first voltage during the second sub-period of the powered period. |
| US09571067B2 |
Semiconductor device with clock-based signal input circuit
A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a clock signal and receiving the clock signal as a power source when the input signal has a first phase, where the signal input circuit amplifies a swing width of the input signal based on a swing width of the clock. |
| US09571066B2 |
Digital filter circuit, digital filter processing method and digital filter processing program storage medium
Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized. The digital filter circuit includes: a complex conjugate generation unit for generating a second complex number signal including conjugate complex numbers of all complex numbers included in a first complex number signal of the frequency domain generated by converting a complex number signal of a time domain by Fourier transform; a filter coefficient generation unit for generating a first and a second frequency domain filter coefficient of a complex number from a first, a second and a third input filter coefficient of a complex number having been inputted; a first filtering unit for performing filtering processing to the first complex number signal by the first frequency domain filter coefficient, and outputting a third complex number signal; a second filtering unit for performing filtering processing to the second complex number signal by the second frequency domain filter coefficient, and outputting a fourth complex number signal; and a complex conjugate combining unit for combining the third complex number signal and the fourth complex number signal, and generating a fifth complex number signal. |
| US09571062B2 |
Module
A module includes: a duplexer including an antenna terminal; a first wiring connecting the antenna terminal to an antenna; a second wiring coupled to the antenna terminal without the first wiring; and an inductor coupled to the second wiring. |
| US09571061B2 |
Integrated circuit configured with two or more single crystal acoustic resonator devices
A configurable single crystal acoustic resonator (SCAR) device integrated circuit. The circuit comprises a plurality of SCAR devices numbered from 1 through N, where N is an integer of 2 and greater. Each of the SCAR device has a thickness of single crystal piezo material formed overlying a surface region of a substrate member. The single crystal piezo material is characterized by a dislocation density of less than 1012 defects/cm2. |
| US09571059B2 |
Parallel via to improve the impedance match for embedded common mode filter design
A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced. |
| US09571057B2 |
Altering audio signals
A system of altering an audio signal presented to a user may include an input configured to receive data indicating a status of an environment outside of an audio device, where the audio device is configured to present an audio signal to a user. The system may also include a detection unit configured to detect a condition based on the received data and an audio altering unit configured to direct altering of the audio signal presented to the user based on the detection of the condition. |
| US09571053B1 |
Receiver dynamic power management
A method of adjusting signal processing in a receiver based on signal strength includes determining a received signal strength indicator (RSSI) level, defining an RSSI value to be high when the RSSI level is above a first threshold or defining the RSSI value to be low when the RSSI level is below the first threshold, determining an automatic gain control (AGC) gain level, defining an AGC value to be high when the AGC gain level is above a second threshold or defining the AGC value to be low when the AGC gain level is below the second threshold, and adjusting power consumption of one or more receiver stages based on the RSSI value and the AGC value. |
| US09571050B2 |
Implementing enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifier
A method and circuit are provided for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs). An operational amplifier is provided in a feedback configuration that forces an input of the CMOS inverter to a set voltage level by regulation of the inverter power supply. A photo-detector sees a more stable bias voltage, and the responsivity of the photo-detector is more robust and the TIA has improved performance across process corners. |
| US09571047B2 |
Switching regulator power supply with constant current option
A dual mode regulator provides power to a tower mounted low noise amplifier (LNA) and operates in either one of two modes. The dual mode regulator comprises a microcontroller that controls the amplifier and two regulators to operate in an Antenna Interface Standards Group (AISG) mode when the microcontroller is detecting AISG protocol information or in a current window alarm (CWA) mode when the microcontroller is not receiving AISG protocol information. In the CWA mode the total current to the two regulators and associated circuitry is maintained at a constant amplitude. Further in the CWA mode, the microcontroller is able to generate an alarm signal and deactivate the amplifier when it detects improper operation by the amplifier. In the AISG mode, a single regulator is used and the other regulator is de-activated by the microcontroller. |
| US09571046B2 |
Amplifier circuit for a two-wire interface
The invention relates to an amplifier circuit (10a, 10b) for a two-wire interface, comprising a first current path (1), comprising a voltage-controlled current source (T1) having a gate (GT1), which is connected to an input connection (E1) of the amplifier circuit. A second current path (2) of the amplifier circuit comprises a voltage-controlled current source (T2), which is connected in series with the second resistor (R2). The first resistor (R1) and a parallel connection of the first and second current paths (1, 2) are connected in series between an output connection (A) and a reference voltage connection (B) of the amplifier circuit. The amplifier circuit (10a, 10b) makes it possible to adjust the gain and to provide a supply voltage and a useful signal over a common conducting track (L). |
| US09571045B2 |
Implementing enhanced CMOS inverter based optical transimpedance amplifier
A method and circuit are provided for implementing enhanced CMOS inverter based optical Transimpedance Amplifiers (TIAs). A transimpedance amplifier (TIA) includes a photo-detector, and the TIA is formed by a first TIA inverter and a second TIA inverter. The first TIA inverter has an input from a cathode side of the photo-detector and the second inverter has an input from an anode side of the photo-detector. A replica TIA is formed by two replica inverters, coupled to a respective input to a first operational amplifier and a second operational amplifier. The first operational amplifier and the second operational amplifier have a feedback configuration for respectively regulating a set voltage level at the cathode side of the photo-detector input of the first inverter and at the anode side of the photo-detector input of the second inverter. |
| US09571043B1 |
Auxiliary control of system offsets
An amplification system, circuit, and method of performing offset cancellation are described. The disclosed amplification system is described as including a main amplifier circuit that receives an input signal and produces an output signal, a two-phase output sampler, and an offset correction circuit. The two-phase output sample samples the output signal of the main amplifier circuit in two different clock domains and determines a delta between the samples. The delta is used to assist the offset correction circuit in generating an offset correction feedback for the main amplifier circuit. |
| US09571039B2 |
Group aware current-limited amplifier and system
A group-aware, current limited amplifier system including a group brownout control bus and a number of current-limited amplification channels coupled to the group brownout control bus. In an example embodiment, each current-limited amplification channel includes an amplifier, an amplifier power supply developing a current level signal that represents the amount of current being drawn by the amplifier, a brownout controller responsive to a digital audio input, the group brownout control bus, and the current level signal, and operative to develop a control signal; and an audio digital-to-analog (D/A) converter responsive to the digital audio input and to the control signal and operative to develop an analog audio output that is coupled to an input of the amplifier. |
| US09571032B2 |
Junction box for solar cell module and method for driving same
The present invention relates to a junction box for a solar cell module which receives a command of a manager from the outside, controls the solar cell module, displays an operating state of the solar cell module, and implements an anti-theft function, a fire prevention function, etc. of the solar cell module, and a method for driving the same. The junction box for a solar cell module according to the present invention comprises: a relay installed between a solar cell module and a combiner for connecting the solar cell module and the combiner for blocking the connection therebetween according to a control signal transmitted from the outside; an RF communication module for signal-processing a data signal transmitted from the outside and extracting solar cell module information and a command of a manager; and a microprocessor for controlling an operation of the relay so that the relay connects the solar cell module and the combiner or blocks the connection therebetween according to the command of the manager extracted from the RF communication module. |
| US09571029B2 |
Solar array column cap
Disclosed herein is a solar array column cap that includes a main body extending between a left side and a right side to define a channel, the channel configured to at least partially receive a vertical column of a solar array support structure such that the main body surrounds the vertical column. The main body further includes a left flange extending radially outwardly from the left side of the channel and right flange extending radially outwardly from the right side of the channel. Further, the main body includes an left upper flap extending from a top edge of the left flange, and a right upper flap extending from a top edge of the right flange, the right upper flap and left upper flap being co-planar. In another embodiment, a body has an opening extending along a center axis from a bottom to a top, the opening configured to receive the vertical column such that the body surrounds the vertical column, and an upper support surface configured to receive a horizontal beam, the upper support surface being located in a plane that is non-perpendicular with the center axis. |
| US09571028B2 |
Methods and systems for selecting and programming replacement motors
Methods and systems for replacing HVAC blower motors and other electric motors are disclosed including systems and methods for gathering and storing information about motors that may need to be replaced, systems and methods for selecting replacement motors, and systems and methods for programming the replacement motors. The systems and methods allow a select few replacement motors to be programmed to replace nearly any original motor. |
| US09571021B2 |
Motor control device and method for detecting out-of-step
There is provided a motor control device for controlling a stepping motor having at least two coils. The motor control device includes a controller applies a pulse voltage being subjected to pulse width modulation to each of the coils and provides a stop period to a target coil being subjected to switching of a direction of the coil current, during which the application of the pulse voltage to the target coil is temporarily stopped. The controller also performs a control to set on-duty of the pulse voltage applied to all of the coils except the target coil to be either 100% or 0% during the stop period. An out-of step of the stepping motor is detected when a back electromotive voltage induced in the target coil during the stop period satisfies a predetermined out-of-step determination criterion. |
| US09571019B2 |
Control device of motor, electronic apparatus, recording apparatus, robot, and control method of motor
A control device of a motor includes detection section that detect counter-electromotive voltages induced in coils by rotation of a rotor, a counter-electromotive voltage normalizing section that normalizes a value of the counter-electromotive voltage using a normalization coefficient according to a speed of the rotation of the rotor, and a rotor position specifying section that specifies the position of the rotor based on values of the counter-electromotive voltage normalized by the counter-electromotive voltage normalizing section. |
| US09571016B2 |
Motor control system and method
A motor control system is disclosed. The motor control system includes a level-shifting unit, a motor unit and a control unit. The level-shifting unit receives an original pulse width modulation (PWM) signal to generate an output PWM signal. When a first high level of the original PWM signal is larger than a first reference value, the level-shifting unit shifts a second high level of the output PWM signal to a set high level. When a first low level of the original PWM signal is lower than a second reference value, the level-shifting unit shifts a second low level of the output PWM signal to a set low level. The control unit controls the speed of the motor according to the output PWM signal. |
| US09571012B2 |
Energy-harvesting conveyor belts and methods
Energy-harvesting and -storage devices in conveyor belts and methods for molding those devices integrally into modular belt links and for enhancing energy harvesting through resonance tuning. Piezoelectric materials, electro-active polymers, thermoelectric generators, RF receivers, photovoltaic devices, linear induction generators, and inductive transformer coupling are used to harvest energy to power belt on-board devices. |
| US09571010B2 |
Varying capacitance rotating electrical machine
A varying capacitance rotating electrical machine provides capacitor elements, such as capacitor plates, that move with respect to each other as separated by a thin film of fluid, for example, air, on which one capacitor element floats. In one embodiment, multiple plates provide for three-phase operation. Narrow gaps provided by the floating capacitor elements increase the power density of the rotating electrical machine. |
| US09571008B2 |
Out-of plane travel restriction structures
The present disclosure includes structures and methods of forming structures for restricting out-of-plane travel. One example of forming such structures includes providing a first wafer 100, 220 comprising a bond layer of a particular thickness 101, 221 on a surface of a substrate material 105, 225, removing the bond layer 101, 221 in a first area 103-1, 103-2, 223 to expose the surface of the substrate material 105, 225, applying a mask to at least a portion of a remaining bond layer 109-1, 109-4, 229-1, 229-3 and a portion of the exposed surface of the substrate material in the first area 109-2, 109-3, 229-2 to form a second area exposed on the surface of the substrate material 105, 225, etching the second area to form a cavity 110, 230 in the substrate material 105, 225 and the bond layer 101, 221, and forming by the etching, in the cavity 110, 230, a structure 113-1, 113-2, 233 for restricting out-of-plane travel, where the structure 113-1, 113-2, 233 has a particular height from a bottom of the cavity 115, 235 determined by the particular thickness of the bond layer 101, 221. |
| US09571007B2 |
Method for reducing a number of switching cycles when controlling a multiphase converter
A method for controlling a polyphase inverter that includes a number of half bridges connected into an intermediate voltage circuit and center taps between switching elements. By cyclically switching the switching elements, the respective center taps of the half bridges are connected to an upper intermediate circuit rail or to a lower intermediate circuit rail of the intermediate voltage circuit according to the principle of pulse width modulation. The switching elements of at least one half bridge are driven in a modified manner, at least in some time intervals, in that the switching pulses of at least two consecutive periods of the pulse width modulation are concatenated directly in time as one switching pulse. In this way, the switching frequencies of the correspondingly driven switching elements and thus the switching losses of the latter can be further reduced. |
| US09570998B2 |
Capacitor arrangement for an intermediate circuit of a voltage converter
The disclosure relates to a capacitor arrangement for an input circuit or intermediate circuit of a voltage transformer comprising at least two capacitors and two connection nodes. Switching elements are provided, by means of which the at least two capacitors are connected in parallel with each other in a first operating state and are connected in series with each other in a second operating state. The disclosure also relates to a voltage transformer arrangement comprising such a capacitor arrangement and an operating method for a capacitor arrangement. |
| US09570996B2 |
Forward-based power conversion apparatus
A forward-based power conversion apparatus is provided. When the forward-based power conversion apparatus supplies a plurality of (at least two of) output voltages to a load, a reverse voltage, corresponding to a lower output voltage, of a secondary winding of a transformer is captured through an equipped output auxiliary unit, so as to assist an output of a higher output voltage. Accordingly, compared to that described in the related art, the reverse voltage of the secondary winding of the transformer described herein can be converted into an effective power output, so that overall power loss of the power conversion apparatus can be reduced, and conversion efficiency of the power conversion apparatus can be improved. |
| US09570994B1 |
Adjustable blanking time for overload protection for switch-mode power supplies
A blanking time for a switch-mode power supply controller includes a first blanking time interval and a second blanking time interval. During the first blanking time interval, the time to charge the feedback voltage at the feedback input of the switch-mode power supply is measured, and a timer setting time is stored based on the measured time. During the second time interval, a series of charge cycles is used. At each charge cycle, the feedback voltage is discharged and then allowed to charge. If, after being discharged, the feedback voltage reaches a voltage threshold during the timer setting time, a counter value is incremented and the next cycle begins. If the feedback voltage does not reach the voltage threshold within the timer setting time, the blanking time ends. If the counter value reaches a count threshold, a shutdown mode is initiated. |
| US09570993B2 |
DC-DC converter
A DC-DC converter wherein a series reactor and primary-side terminals of a transformer are connected between output terminals of a full-bridge inverter in which each of an upper arm and a lower arm includes a switching element and a freewheel diode, and a rectifier circuit and a filter circuit are connected to secondary-side terminals of the transformer. The DC-DC converter includes a circulation current generation mode in which a circulation current flowing between the transformer and the switching element is generated in a power non-transmission period, and a circulation current interruption mode in which the circulation current is interrupted. |
| US09570991B2 |
Bidirectional DC/DC converter
During a dead time, a resonance current generated by a load current that flows in a resonance inductor and a resonance current generated by an excitation current of a transformer flow in a resonance circuit constituted by the resonance inductor and capacitors that exist in parallel to respective switching elements. A controller performs a turning off operation on the switching elements at a timing that the resonance current generated by the load current and the resonance current generated by the excitation current are cancelled each other during the dead time. |
| US09570986B2 |
Systems and methods for regulating output currents of power conversion systems
Systems and methods are provided for regulating a power conversion system. An example system controller includes a first controller terminal and a second controller terminal. The first controller terminal is configured to receive a first signal associated with an input signal for a primary winding of a power conversation system. The second controller terminal is configured to output a drive signal to a switch to affect a first current flowing through the primary winding of the power conversion system, the drive signal being associated with an on-time period, the switch being closed during the on-time period. The system controller is configured to adjust a duration of the on-time period based on at least information associated with the first signal. |
| US09570980B2 |
System and method for switched power supply current sampling
According to an embodiment, a method of operating a switching power supply includes applying a periodic switching signal to a first switch that is coupled to an output node, detecting an offset delay between applying the periodic switching signal and a change in voltage of the output node, calculating a corrected midpoint of a half phase of the periodic switching signal based on the offset delay, generating a sampling pulse based on the corrected midpoint, and sampling a current at the output node according to the sampling pulse. |
| US09570979B2 |
Voltage regulator with power stage sleep modes
A power stage of a voltage regulator includes a first switch for connecting a load to a supply voltage in a first switching state of the power stage, a second switch for connecting the load to ground in a second switching state of the power stage and driver circuitry for setting the power stage in the first switching state, the second switching state or a non-switching state in which both switches are off responsive to a switching control signal received by the power stage. A power management unit moves the power stage from a nominal power mode to a first low power mode if the power stage is in the non-switching state for a predetermined time period. |
| US09570976B2 |
Switched capacitor power converter
A switched capacitor power converter comprising a set of at least two capacitors; an input for receiving an input voltage an output for outputting an output voltage different to the input voltage, a plurality of switches configured to arrange the set of capacitors into a plurality of different subcircuit arrangements between the input and output for converting the input voltage to the output voltage; wherein the set of capacitors is configured to adopt a first subcircuit arrangement in which the set is connected to the input, a second subcircuit arrangement different to the first subcircuit arrangement and a third subcircuit arrangement, different to the first and second arrangements, in which the set is connected to the output, the subcircuit arrangements configured such that each of the capacitors in the set acts as a floating capacitor. |
| US09570973B2 |
Bridgeless power factor correction circuit and control method utilizing control module to control current flow in power module
A bridgeless power factor correction (PFC) circuit, which includes an alternating current power supply module, a power module, and a control module; the power module includes one or more interleaved PFC circuits, each interleaved PFC circuit includes one inductor, one pair of first switching components, and at least one capacitor, a first end of the inductor is connected to the alternating current power supply module, and a second end of the inductor is connected to one end of each capacitor through one of the first switching components and is also connected to the other end of each capacitor through the other one of the first switching components; and the control module samples a current of each first switching component in the power module, and turns off a first switching component through which a negative current flows. |
| US09570970B1 |
Method and apparatus for use with grid connected inverters in distributed power generation
Systems, methods, and devices relating to the controlling of a grid-connected inverter. A grid connected inverter is controlled by a proportional-resonant controller which tracks the grid current. To adjust for changes in grid conditions, an update block dynamically and continuously adjusts coefficients used by the controller to ensure high gains provided by the controller at the grid frequency. A harmonic compensator is also provided to ensure that high loop gains at harmonic frequencies of the grid frequency are also provided for. To also adjust for changing grid conditions, a second update block also continuously adjusts the coefficients used by the harmonic compensator. |
| US09570964B2 |
Rotor core of dynamoelectric machine and method of manufacturing the same
A rotor core includes a rotor core includes a plurality of rotor core blocks each of which is constituted by stacking annular sheet-like core materials in a direction of sheet thickness of each core material and a plurality of catch recesses circumferentially disposed in an inner circumference of each core material at an interval of a predetermined angle so as to extend radially outward, the catch recesses having respective circumferential dimensions equal to each other and different radial depths. In each rotor core block, a plurality of the core materials is stacked while the catch recesses having an identical configuration are aligned. The rotor core blocks have respective outer peripheries which are shifted from each other according to the depths of the catch recesses caught by a bar-shaped aligning jig when the catch recesses of the rotor core blocks are caught by the aligning jig. |
| US09570963B2 |
Brush cover for a brush-commutated electric motor and electric motor
The present invention relates to a brush cover for a brush-commutated electric motor. The brush cover comprises at least one lever brush which is mounted rotatably about an axis at the brush cover by means of a bolt. According to the invention, the bolt is surrounded, at least in sections, by at least one damping sleeve of an elastomer. |
| US09570962B2 |
Controller-integrated rotating electrical machine
An inverter device is provided with a hollow portion in a center portion of a rotation shaft of a rotating electrical machine. The rotating electrical machine has a first cooling air passage for cooling air generated by a cooling fan to flow in from an outer side in a radial direction of the rotating electrical machine, then to cool a heat sink, and to be discharged through ventilation holes provided to a rear bracket on an outer peripheral side by passing an inner periphery of the rear bracket, and a second cooling air passage for cooling air to flow into the hollow portion from the rear in the axial direction, then to cool a brush holder and a magnetic pole position detection sensor, and to be discharged through the ventilation holes by passing the inner periphery of the rear bracket. |
| US09570957B2 |
Gearbox, and method for manufacturing the same
A gear box includes a gear box body of a reducer to which a motor is mounted. The gear box body includes a worm, wheel holding section where a worm wheel of the reducer is held, and a motor holding section, where a part of the motor is contained, the motor holding section having a motor mounting opening. The motor holding section is configured such that a bottom of the motor holding section is provided in a region between a line L1 and a line L2. Here, the line L1 passes through the center C of the worm wheel holding section and is perpendicular to the axis line X of a motor shaft. The line L2 is a tangent line passing through an outer edge portion located near a circular outer peripheral wall of the worm wheel holding section on a motor side and is perpendicular to the axis line X of the motor shaft. |
| US09570956B2 |
Planetary, push-pull electromagnetic motor
A planetary push-pull electric motor comprising a ring stator fixedly mounted on the central axis of the planetary push-pull electric motor; a planetary rotor arranged to be magnetically movable around an inner circumference of the ring stator, the planetary rotor rotatably mounted on an eccentric rotor axis in respect to the central axis of the ring stator; a series of electromagnets radially mounted about the ring stator for generating magnetic fields; and a means for transferring rotation of the eccentric planetary rotor axis to directly power an output shaft, wherein when the series of electromagnets are activated, the planetary rotor is magnetically impelled to pivot and roll from one temporary, moving contact line to an adjacent one, creating a rotary moment upon each of the temporary, moving contact lines, providing a power output. |
| US09570955B2 |
Overmold protection for vibration motor
A vibration motor assembly includes a vibration motor, an end cap having electrical contacts configured for supplying electrical power to the vibration motor, the end cap having a first connecting structure connecting the end cap to the vibration motor, and a capsule connected to the end cap to define a cavity. The vibration motor further has a shaft, and an eccentric mass is connected to the shaft. The vibration motor is configured to use electrical power to rotate the shaft and the eccentric mass to create a vibration effect. The end cap further has a second connecting structure connecting the capsule to the end cap. The vibration motor and eccentric mass are enclosed by the so-connected end cap and capsule, so as to enable the vibration motor assembly to withstand fabrication conditions. |
| US09570954B2 |
Control device-integrated rotating electric machine which prevents entrance of drive belt abrasion powder
A control device-integrated rotating electric machine includes: a rotor integrally supported by a rotary shaft; a stator; a front case and a rear case; a pulley provided on a part of the rotary shaft, the part being protruded from the front case; a control circuit portion provided outside the rear case; a cover for covering the control circuit portion; and a rotating electric machine-side connector provided for the control circuit portion, the rotating electric machine-side connector being provided outside the cover. The rotating electric machine-side connector has a connection side that is oriented so as to be inclined on a side separating from the pulley with respect to a direction orthogonal to a width direction of the pulley, in which a belt is looped. |
| US09570949B2 |
Electric motor with permanent magnet having curved outer wall and flat rear wall
An electric motor includes: a ring-shaped stator including a field coil; and a rotor holding a permanent magnet in a magnet holding portion on an outer circumference thereof in an exposed state and being supported to be rotatable about a rotary shaft core in an inner space of the stator, wherein the magnet holding portion is configured to have a magnet insertion portion and a pair of regulation bodies, and the permanent magnet is configured to include a cylindrical outer wall surface, a rear wall surface, a pair of side wall surfaces, and a pair of engaged surfaces. |
| US09570947B2 |
Electric rotating machine
The electric rotating machine includes a stator having an inner hole, a rotor disposed in the inner hole of the stator with a gap with an inner periphery of the stator and formed with magnet housing holes each housing a permanent magnet as a magnetic pole embedded in the outer periphery of the rotor, and a shaft pressure-inserted into a center hole of the rotor. The rotor includes, for each adjacent two of the magnet housing holes, a beam portion formed radially outside the magnet housing holes, a projecting portion projecting radially inward to define the center hole, an extension portion formed radially outside the projecting portion and radially outside the magnet holes, and a plate-shaped bridge portion connecting the beam portion and the extension portion. |
| US09570946B2 |
Stator arrangement for an electrical machine
A stator arrangement for an electrical machine includes a casing element as one component and at least two stator segments, which are arranged in the casing element as further components. One of the components has a feather key groove and another one of the components has a feather key, which corresponds with the feather key groove, for bracing the one component against the other component. |
| US09570945B2 |
Electric motor
An electric motor includes a stator, a rotor and a can arranged between the stator and the rotor, wherein the stator exhibits several stator pole pairs, which are each formed by two adjacent stator poles, which are designed in such a way as to generate oppositely polarized magnetic fields, and wherein the rotor exhibits a plurality of magnetic rotor poles distributed over the circumference, and is configured in such a way as to enable a magnetic flux between two adjacent rotor poles, as well as a pumping set with such an electric motor. |
| US09570944B2 |
Power consumption measurement and control apparatus, method, and non-transitory computer readable storage medium thereof
A power consumption measurement and control apparatus, method, and non-transitory computer readable storage medium thereof are provided. The power consumption measurement and control apparatus includes a power input line, a power output line, a sensing interface, a processing unit, a button, and a power consumption measurement and control unit. The power consumption measurement and control unit has a logic switch. When the logic switch is off and the processing unit receives an identification signal from the sensing interface, the logic switch is turned on. When the logic switch is on and one of the following conditions happens, the logic switch is turned off: (a) another identification signal from the sensing interface is received, and (b) the power consumption amount flowing out the power output line is below a predetermined threshold over a predetermined time interval. |
| US09570943B2 |
Electrical accumulator unit for providing auxiliary power to an electrical network
An electrical accumulator unit wherein an energy storage device is utilized in conjunction with an actively controlled bidirectional power converter to provide auxiliary power to an electrical network is disclosed. |
| US09570941B2 |
Autonomous power supply
Aspects of the present disclosure are directed to providing power from two or more power sources. As may be implemented in accordance with one or more embodiments, a switching circuit includes a switching transistor connected between a backup power supply and both a primary power supply and an internal power rail. When power is provided via the primary power supply, the switching circuit operates in a blocking state in which back current is prevented from flowing to the backup power supply while the primary power supply couples power to the internal power rail. When the primary power supply is disconnected or interrupted, a voltage coupled to a gate/control terminal of the switching circuit drops and the switching circuit automatically switches to another state in which the internal power rail is powered by the backup power supply. |
| US09570935B2 |
Magnetic coupling unit and magnetic coupling system
There are provided a magnetic coupling unit and a magnetic coupling system which are capable of reducing energy loss when operations using magnetic coupling between magnetic devices are performed. The magnetic coupling unit includes: one or more magnetic devices each capable of being magnetically coupled with other magnetic device in other unit; and one or more coupling reinforcing sections each reinforcing the magnetic coupling. |
| US09570934B2 |
Lithium battery auto-depassivation system and method
A battery depassivation system includes a depassivation circuit, a battery connect/disconnect circuit, and a processor. The depassivation circuit is adapted to be electrically coupled in series with a battery. The depassivation circuit is also coupled to receive an ENABLE signal and is configured, upon receipt thereof, to draw current from the battery. The battery connect/disconnect circuit is adapted to be electrically coupled in series between the battery and one or more battery-powered electronic circuits. The battery connect/disconnect circuit is coupled to receive an ISOLATE signal and is configured, upon receipt thereof, to electrically disconnect the one or more battery-powered electronic circuits from the battery. The processor is adapted to couple to the battery and is configured, upon being coupled thereto, to determine if the battery needs depassivation and implement a depassivation routine if the battery is determined to need depassivation. |
| US09570932B2 |
Charging current setting method and charging module
A charging current setting method for a charging module includes detecting at least two voltage values associated with two input current values of an input voltage signal at an input terminal of the charging module to calculate an input resistance; setting a lower limit voltage value of the input voltage signal according to the input resistance; controlling an input current to increase its magnitude, so that voltage level of the input voltage signal decreases in accordance with increasing level of the input current; controlling the input voltage signal to remain on the lower limit voltage value when the input voltage signal is decreasing and reaches the lower limit voltage value, and recording a magnitude of the input current as an upper limit current value when the input voltage signal is on the lower limit voltage value and the input current becomes stable; and determining a charging current value of the charging module according to the upper limit current value. |
| US09570931B2 |
Electronic device and electronic device charging system
An electronic device includes a power receiving unit and a secondary battery. The electronic device can send an instruction to an outside to stop power transmission, and operates by a discharge current of the secondary battery. In a case where the secondary battery is charged and a voltage of the secondary battery becomes higher than a first threshold and lower than a second threshold larger than the first threshold, charging of the secondary battery is stopped without sending the instruction to stop the power transmission, and after an elapse of a predetermined period of time, the charging of the secondary battery is restarted. When the voltage of the secondary battery thereafter becomes higher than the second threshold, the instruction to stop the power transmission is sent, and the charging of the secondary battery is stopped. |
| US09570927B2 |
Integrated level shifter
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. |
| US09570923B2 |
Adjusting device, battery pack, and adjusting method
An adjusting device that is connected to a load and to a plurality of storage battery units that are connected together in parallel and that adjusts voltage differences among the plurality of storage battery units includes: for each of the storage battery units, a switch that is provided between a storage battery unit and the load that is turned ON during detection intervals for detecting current from the storage battery unit, a detection means that detects the current supplied from each of the storage battery units during the detection interval, and an adjusting means that, based on the detection results of the detection means, controls the ON/OFF states of switches during the adjustment intervals for adjusting voltage differences such that the voltage differences among the plurality of storage battery units are decreased. |
| US09570921B2 |
Power feeding coil unit and wireless power transmission device
A power feeding coil unit includes a power feeding coil, and first and second auxiliary coils arranged so that a wire of the first auxiliary coil and a wire of the second auxiliary coil do not overlap a wire of the a power feeding coil when viewed from a direction perpendicular to an axial direction of the power feeding coil. A direction of circulation of a magnetic flux generated by the first auxiliary coil and a magnetic flux generated by the second auxiliary coil are opposite to a direction of circulation of a magnetic flux generated by the power feeding coil. An axes of the first and second auxiliary coils are substantially perpendicular to a power feeding direction of the power feeding coil, and are not aligned with the axis of the power feeding coil. |
| US09570916B2 |
Inertial response function for grids with high turbine penetration
A method for compensating at least partially a frequency deviation in a grid is provided in which a grid frequency is determined and the grid frequency is applied to a grid frequency criterion. If the grid frequency meets the grid frequency criterion, a determination is made as to a set of wind turbines from a wind turbine power plant fleet based on the grid frequency criterion, and a command for a transient frequency response is transmitted to the set of wind turbines. |
| US09570913B2 |
Generator for producing electric power
A generator for producing electric power, the generator including a generator unit including a stator) and a rotatably supported rotor, wherein the stator includes a first set of windings and a second set of windings, and the rotor is adapted to induce electrical voltage in the first set of windings and in the second set of windings when the rotor is rotated relative to the stator, the generator further includes a first converter coupled to the first set of windings, the first converter being adapted to convert alternating voltage in the first set of windings into an output DC voltage, a DC output coupled to the first converter to receive the output DC voltage, and a second converter coupled to the second set of windings and to the DC output, the second converter being adapted to generate control voltages and/or control currents in the second set of windings, is provided. |
| US09570907B2 |
Input rail dynamic power balancing and merging
A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided. |
| US09570906B2 |
Voltage clamping circuit
A voltage supply for providing a clamped voltage to a circuit element to be protected against electrical overstress (EOS) has a reference voltage module and a voltage clamp module. The reference voltage module has a first field-effect transistor (FET) whose source and drain are connected in series between a programmable reference current source and a first resistor across a power supply. The gate of the first FET is connected to its drain to provide a reference voltage defined by the reference current flowing in the first resistor. The voltage clamp module has a second FET whose gate receives the reference voltage and whose source is connected to provide to the protected circuit element the clamped voltage whose variation is limited by the reference voltage. |
| US09570905B2 |
Semiconductor drive apparatus
A semiconductor drive apparatus includes a first control unit configured, when an overcurrent is detected flowing between a first main electrode and a second main electrode of a switching element, to make a gate of the switching element conductive with a predetermined reference potential, to make a control voltage applied between the gate and the first main electrode lower, and to turn off the switching element; a detection unit configured to detect a current generated accompanying charge or discharge of a feedback capacitance between the gate and the second main electrode; and a second control unit configured, when the overcurrent and the current generated accompanying the charge or discharge of the feedback capacitance are detected, to make a resistance between the gate and the reference potential lower. |
| US09570901B2 |
Electronic circuit and low voltage arc flash system including an electromagnetic trigger
An electronic circuit includes a number of sensors structured to detect an arc flash from an uncontrolled arcing fault, and a trigger circuit, responsive to the detected arc flash, structured to trigger a triggering mechanism and cause a breakdown of a number of gaps within a low voltage arc flash switch. |
| US09570900B2 |
Low voltage arc flash switch
A low voltage arc flash switch includes a sealed housing and gas insulation within the sealed housing. A plurality of conductors include a number of gaps therebetween within the sealed housing. A triggering mechanism is structured to cause a breakdown of the number of gaps. |
| US09570892B2 |
Photogrammetric methods and apparatus for measurement of electrical equipment
A method is disclosed comprising: imaging a feature of a component of an electrical power transmission system for example in combination with a reference component or feature of known dimensions, the reference component or feature comprising a reference, to produce one or more images; analyzing the one or more images with a photogrammetry algorithm to measure the feature of the component; and placing a protector at least partially over the component, the protector being selected to fit the component based on the measurement of the feature. In some embodiments the method may further comprise making the protector based on the measurement of the feature. A method is also disclosed comprising: remotely placing a reference object into a position that is inside a safe Limit of Approach and in the vicinity of a feature of a component of an energized live electrical power transmission system, the reference object comprising a reference; imaging a combination of the reference and the feature of the component to produce one or more images; and analyzing the one or more images with a photogrammetry algorithm to measure the feature of the component. |
| US09570888B1 |
Method of strain engineering and related optical device using a gallium and nitrogen containing active region
An optical device has a gallium and nitrogen containing substrate including a surface region and a strain control region, the strain control region being configured to maintain a quantum well region within a predetermined strain state. The device also has a plurality of quantum well regions overlying the strain control region. |
| US09570887B2 |
Vertical cavity surface emitting laser device, vertical cavity surface emitting laser array, optical scanning apparatus, image forming apparatus, optical transmission module and optical transmission system
A disclosed vertical cavity surface emitting laser device emits light orthogonally in relation to a substrate and includes a resonator structure including an active layer; and semiconductor multilayer reflectors disposed in such a manner as to sandwich the resonator structure between them and including a confinement structure which confines an injected current and transverse modes of oscillation light at the same time. The confinement structure has an oxidized region which surrounds a current passage region. The oxidized region is formed by oxidizing a part of a selective oxidation layer which includes aluminum and includes at least an oxide. The selective oxidation layer is at least 25 nm in thickness. The semiconductor multilayer reflectors include an optical confinement reducing section which reduces optical confinement in a transverse direction. The optical confinement reducing section is disposed on the substrate side in relation to the resonator structure. |
| US09570886B2 |
Tunable laser and method of tuning a laser
The invention relates to a tunable laser, the tunable laser comprising a first waveguide, a second waveguide and a semiconductor layer being arranged to separate the first waveguide from the second waveguide. The first waveguide comprises a first coupling portion and an active portion for generating a laser signal. The second waveguide comprises a second coupling portion and a tuning portion for tuning the wavelength of the laser signal. The first coupling portion and the second coupling portion are configured to couple the laser signal between the first waveguide and the second waveguide through the semiconductor layer. |
| US09570884B2 |
Laser apparatus, extreme ultraviolet light generation system, method for controlling the laser apparatus, and method for generating the extreme ultraviolet light
A laser apparatus may include: a master oscillator configured to output a pulsed laser beam at a repetition rate, the master oscillator including at least one semiconductor laser apparatus; at least one amplifier configured to amplify the pulsed laser beam from the master oscillator, the at least one amplifier being configured to include at least one gain bandwidth; and a controller for controlling a parameter affecting an output wavelength of the pulsed laser beam from the master oscillator such that a wavelength chirping range of the pulsed laser beam from the master oscillator overlaps at least a part of the at least one gain bandwidth. |
| US09570883B2 |
Photonic package architecture
A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described. |
| US09570880B2 |
Multi-mode fiber amplifier
A laser utilizes a cavity design which allows the stable generation of high peak power pulses from mode-locked multi-mode fiber lasers, greatly extending the peak power limits of conventional mode-locked single-mode fiber lasers. Mode-locking may be induced by insertion of a saturable absorber into the cavity and by inserting one or more mode-filters to ensure the oscillation of the fundamental mode in the multi-mode fiber. The probability of damage of the absorber may be minimized by the insertion of an additional semiconductor optical power limiter into the cavity. |
| US09570873B2 |
Short pulsed IR fiber laser at wavelength > 2 μm
A method of generating ultrashort pulses with wavelengths greater than 2 μm comprising a short pulse diode laser or fiber laser operating at a wavelength of 1 μm or greater with a pulse width of 10 ps or greater, one or more amplification stages to increase the peak power of the pulsed source, a nonlinear fiber stage whereby the dispersion of the nonlinear fiber is anomalous at the pulsed source wavelength such that the fiber breaks up the pulse into a series of sub-ps pulse train through modulation instability which may be seeded by spontaneous noise which are then wavelength shifted in one or more stages by soliton self frequency shift in anomalous dispersion fiber or Raman in normal dispersion fiber and amplified in one or more stages to generate a high peak power ultrashort pulse (<1 ps) source at a wavelength of 2.4 μm or greater. |
| US09570867B2 |
Notched contact for a modular plug
A metallic contact for insertion into a modular telecommunications plug includes a generally planar body defining a top end, a bottom end, a front end, a rear end, and a length extending from the front end to the rear end. The bottom end is at least partially defined by a blade for piercing an insulation of a wire positioned within the plug. At least a portion of the top end is configured to electrically contact a conductor of a jack that receives the plug. The top end is defined at least in part by a first engagement surface that is separated from a second engagement surface by a notch. An uppermost portion of the first engagement surface defines a first push surface that is generally at the same height as a second push surface defined by an uppermost portion of the second engagement surface. The notch is defined by a front vertical wall spaced from a rear vertical wall, wherein the front vertical wall is positioned at a distance of at least half the length of the contact from the front end of the contact. |
| US09570865B1 |
Electrical box having a removable module with a charging connector
This invention disclosure is an electrical outlet receptacle containing the high voltage AC side and low voltage DC power supply used typically for charging and/or powering portable electronic devices. The charge connector for interfacing with the portable device is contained in a removable module. Furthermore the removable module may contain a retractable charge cord or charge cords, charge status indicator lights, power supply switches, and it also may contain a portion of the power supply control circuitry to provide the particular power and signaling required to interface with the specific portable device. The other portion of the power supply and control circuitry would be contained in the fixed portion of the receptacle and/or the electrical box. Finally there may be additional heat sinks to provide enough thermal dissipation from the power supply. |
| US09570862B2 |
Terminal and charging connector
In a terminal including: a terminal body that has a mating terminal contact part with which a mating terminal is brought into contact, and a sensor fixing part; and a thermistor fixed to the sensor fixing part, and a charging connector using the terminal, the sensor fixing part has a cylindrical shape in which the thermistor is inserted, the thermistor has a lock part, and is allowed to be inserted in the sensor fixing part by elastic deformation of the sensor fixing part, and at an insertion completion position, the lock part is locked to the sensor fixing part. |
| US09570860B1 |
Electrical connector providing secured plugging and convenient unplugging
The connector contains a main member, a casing member housing the main member, and a sliding member slidably configured on the casing member. The main member contains a flexible locking element along a lateral side. The sliding member has a second bulge element along a lateral side's internal wall for engaging the locking element. When a user holds and pulls the sliding member backward, the second bulge element presses the locking element, and the locking element is pushed to escape the detainment by a female connector. The present invention therefore achieves secured and convenient plugging and unplugging. |
| US09570854B2 |
Terminal fitting with stabilizers and connector
First and second stabilizers (26, 33) project on a main body (11) of a terminal fitting (10) while being spaced apart in a direction intersecting with a front-back direction. The first stabilizer (26) has a front end extending steeply in a direction substantially perpendicular to the front-back direction and the second stabilizer (33) has a front end part (38) inclined to recede. The front end part (38) of the second stabilizer (33) is more forward than the first stabilizer (26) so that the front end of the second stabilizer contacts a facing wall surface of a connector housing (60) before the first stabilizer (26) when an insertion posture is incorrect. |
| US09570851B2 |
Connector technology for embedded electronic equipment with two connectors
The general field of the invention is that of the devices for connecting an electronic module in a rack comprising an opening of dimensions close to those of the front face of the module and a seat for fixing and connecting said module, said connection device comprising a first and a second male connector mounted on the rear face of the electronic module; and a first and a second female connector mounted on the fixing seat. In the device according to the invention, the second female connector is mounted in a structure comprising mechanical means for self-centring said second female connector within a clearance range greater than the mechanical positioning tolerances and elastic means arranged so as to hold said second female connector in position. These various means are arranged in such a way as to be able to ensure the blind electrical connection of the electronic module in the rack, its front face resting on the opening. |
| US09570849B2 |
Float plate for blind matable electrical cable connectors
A float plate for a connector interface includes: at least one substantially planar body panel; at least one opening in the body panel, the opening having a perimeter; and a plurality of fingers extending from the perimeter of the opening within a plane defined by the body panel, each finger extending from the perimeter at an oblique angle to a diameter of the opening originating at a fixed end of the finger. |
| US09570848B1 |
Electrical plug and cord kit for hair clippers
The electrical plug and cord kit for hair clippers is adapted for use with electrically powered hair dressing equipment. Specifically, the electrical plug and cord kit for hair clippers is a plug and cable designed to provide electric power for use by electrically powered hair dressing equipment and especially for use by clippers. The use of a pluggable power system reduces the station requirements for electrical outlets and further reduces the need for organizing a plurality of cables at the station. The electrical plug and cord kit for hair clippers comprises a plug housing, a plug connector, a handle housing, and a hanging loop. |
| US09570847B2 |
Fixed structure for interface card
The invention provides a fixed structure for an interface card. The interface card is fixed within an interface slot by the fixed structure. The interface slot is provided on a front side therefore with at least one protruding block. The fixed structure comprises a metal shell, which is assembled to a surface of the interface card, and comprises a pressing portion and an engaging portion. When the interface card is to be inserted into the interface card, the user presses the pressing portion of the metal shell so as to expand the engaging portion. When the interface card has been inserted into the interface card, the user will release the pressing portion of the metal shell so that the engaging portion can engage with the protruding block of the interface slot. Therefore, the interface card is steady fixed within the interface slot by means of the fixed structure. |
| US09570846B2 |
Plug-type connector having plug-in force limitation
Disclosed is a plug connector, known as a push-pull type of plug connector, wherein the plug connector is embodied from a base body for receiving a contact, a latch and also a first actuator for actuating the latching means. The first actuator is provided on the plug connector in such a manner that it can be displaced axially along the plugging direction. The first actuator is used for transferring the plugging force by the user to the plug connector, wherein the strengths of the force is limited to a defined maximum in order to prevent damage to components. Furthermore, the latch is actuated by displacing the first actuator in the opposite direction to the plugging direction and the latching arrangement with respect to the mating plug connector is released. |
| US09570844B1 |
Lug terminals block for quick connection and disconnection
A terminal block is disclosed. The terminal block includes a body that forms a chamber and an opening configured to facilitate passage of a lug terminal from an exterior environment into the chamber. A movable first ferromagnetic object is positioned in the chamber. An electrical contact is exposed to the chamber, and a second ferromagnetic object is configured to magnetically attract the movable first ferromagnetic object in a direction toward the electrical contact. |
| US09570838B2 |
Structure of highly waterproof connector for easy conduction between ground pin and body
A connector for power or braking attached to an electric motor is based on resin molding around a ground pin and a power supply pin. In this connector, an electrical junction between the ground pin and the body of the electric motor or of a brake is disposed in a predetermined position on the inner peripheral side of a sealing portion which seals the interior of the brake or electric motor body from the air. |
| US09570829B2 |
Plug connector and mating connector
A plug connector may comprise an expanding ring, a plug contact element, a first connector housing stop, and a locking ring. The plug contact element may comprise a coil spring with a first end and a second end, where the second end of the coil spring may be coupled to the expanding ring. The first connector housing stop may be configured to absorb a pressure in a first rotational direction and block the first end of the coil spring from rotating in the first rotation direction. The locking ring may be configured to absorb a pressure in a second rotational direction opposite the first rotational direction. The locking ring may be configured to block the expanding ring when the plug connector is in an open state and unblock the expanding ring when the plug connector is in a closed state. |
| US09570827B2 |
Contact member
A contact member according to one aspect of the present disclosure comprises: a thin plate member having spring characteristics and electrical conductivity. The thin plate member comprises: a joint portion having a joint surface to be joined to a first member; a contact portion contactable with a second member; and a connecting portion having a length component in a direction intersecting the joint surface, and having a first end continuous to the joint portion and a second end continuous to the contact portion. The connecting portion comprises a narrow portion having a smaller dimension in a width direction than a dimension around the narrow portion. |
| US09570821B2 |
Connector and connector unit
A connector connectable to another connector includes a connector card including a first surface and a second surface, a cable pad provided on the first surface and configured to be connected to a cable core wire, a contact that is provided on the second surface and corresponds to the cable pad, wherein the contact is positioned across the connector card from the corresponding cable pad and is configured to come into contact with the other connector, and an electrically conductive part provided through the connector card, wherein the conductive part electrically connects the cable pad and the corresponding contact. |
| US09570818B2 |
Contacting device for connecting an electrical conductor
A contacting device (100) for connecting an electrical conductor (11) comprises a connection contact (101) for fixing the electrical conductor (11) to the contacting device (100), wherein the connection contact (101) has a retainer (110). The retainer (110) has an accommodating region (112) for accommodating the electrical conductor (11). The accommodating region (112) tapers between an inlet opening (E112) and a base surface (B112) of the accommodating region (112) in such a way that a cross section (A11) of the electrical conductor (11) is deformed when the electrical conductor (11) is inserted into the accommodating region (112), whereby the electrical conductor is retained on the connection contact (101) in the clamping seat. The electrical conductor (11) can thus be fixed to the connection contact (101) without bending of the retainer (110). |
| US09570816B2 |
Miniature antenna and antenna module thereof
An antenna includes a feed segment for transmitting a radio-frequency signal, a first radiator electrically connected to the feeding segment and formed on a first surface of a substrate, and a second radiator electrically connected to the feeding segment and formed on a second surface of the substrate, wherein the first radiator includes a first arm electrically connected to the feeding segment, a first branch and a second branch, and a second arm electrically connected to the feeding segment, a third branch and a fourth ranch, and the second radiator includes a third arm electrically connected to the feeding segment, a fifth branch and a sixth branch, and a fourth arm electrically connected to the feeding segment, a seventh branch and an eighth branch. |
| US09570815B2 |
Antenna apparatus and method for handover using the same
There are provided an antenna apparatus and a method of handover using the antenna apparatus. The antenna apparatus may comprise a plurality of antenna elements forming a plurality of beams in a predetermined service area. The plurality of antenna elements are arranged in a plurality of rows, and a number of antenna elements included in an uppermost row of the plurality of rows is smaller than a number of antenna elements included in a downmost row of the plurality of rows, and differences between center angles of beams formed by the antenna elements included in the downmost row are larger than differences between center angles of beams formed by the antenna elements included in the uppermost row. |
| US09570813B2 |
Reflectors for reflecting electromagnetic energy away from a user device in a first direction
A user device having a dielectric carrier, a multi-band slot antenna, a reflector and a feed line connector is described. The multi-band slot antenna has slot openings in a second portion of conductive material disposed on a second side of the user device and is operable to radiate electromagnetic energy. The reflector is additional conductive material disposed on the second side and is operable to reflect a majority of the radiated electromagnetic energy away from the user device in a first direction. |
| US09570810B2 |
Vehicle antenna
The invention provides an antenna which has two feed ports and two conductor areas. Where the two areas face each other, there is a set of interdigitated arms and slots. These define a shape with two open slots (one on each side) extending from the two feed points, and a central closed slot. |
| US09570809B2 |
Techniques for designing millimeter wave printed dipole antennas
A printed millimeter wave dipole antenna and techniques for designing such an antenna are disclosed. In one embodiment, the dipole antenna comprises: a signal wing and at least one ground wing for propagating signals in a millimeter wave band; and an unbalanced feeding structure directly coupled to the signal wing. The unbalanced feeding structure is boarded by a plurality of escorting vias to ensure equipotential grounds. |
| US09570807B2 |
Antenna module and terminal apparatus
An antenna module includes an antenna line disposed annularly, a magnetic body formed annularly along the antenna line, having a bottom part and a pair of side parts to accommodate the antenna line, and provided with end faces of the pair of side parts disposed in a same direction, and an insulator disposed between the magnetic body and the antenna line. |
| US09570802B2 |
Radar antenna and radar antenna manufacturing method
A radar antenna is provided. The radar antenna includes an antenna unit provided with dielectric bodies in a front part thereof in a radio wave radiating direction, a pedestal, a supporting bar attached between the antenna unit and the pedestal to separate the antenna unit from the pedestal, and formed with a hollow section therein, and one of a cable and a waveguide passing through the hollow section and connected with the antenna unit. |
| US09570800B2 |
Ground antenna and ground radiator using capacitor
By providing a radiator configuration circuit and a feeding circuit each having a simple structure, a ground radiation antenna having a more simplified fabrication process as well as a remarkably reduced fabrication cost is provided herein. Additionally, a ground radiation antenna having an excellent radiation performance, even when one side of a mobile communication terminal is covered with a conductive substance, such as an LCD panel, is also provided herein. |
| US09570797B2 |
Thin flat panel style digital television antenna
A thin flat panel style digital television antenna has a radiation layer, a front insulation layer, a rear insulation layer and a connection cable. The radiation layer has a triangular hollow area and an opening formed in one edge thereof to communicate with one angle of the hollow area. The front insulation layer and the rear insulation layer are respectively overlapped on a front surface and a rear surface of the radiation layer to protect and electrically insulate the radiation layer. The radiation layer further has multiple connection holes adjacent to the opening thereof for multiple connection terminals of the connection cable to be respectively connected thereto. Given the foregoing structure, the digital television antenna has a wide frequency band, is thin and lightweight, is cost-effective in production, and is good for mounting and storage. |
| US09570795B1 |
Multi-functional skin incorporating a photo-voltaic array and a RF antenna
A multi-functional, multi-layer film or skin which may be used as a covering for a structure or platform incorporates an integrated photovoltaic element and an integrated RF antenna element. The film or skin is suitable for use in various applications, including those involving autonomous, self-powered, mobile communication systems and especially for use as a skin or covering for solar powered aircraft and UAVs. Planar PV cells and planar RF antenna are used to facilitate their integration into the film or skin. The PV cells and RF antenna are configured to face operate outward from opposite faces of the skin. The film or skin addresses potential problems arising from conflicting directional requirements for PV orientation and antenna pointing on mobile platforms. This is accomplished by employing wide angle AR coatings on the PV elements and electrical controls to steer the RF antenna. |
| US09570786B2 |
High-frequency transmission line
A transmission line portion of a high-frequency transmission cable includes a dielectric body in which a first ground conductor, a signal conductor, and a second ground conductor are arranged along a thickness direction of the dielectric body from a first principle surface side. The second ground conductor is arranged at a position that does not overlap the signal conductor when viewed in a direction perpendicular or substantially perpendicular to the first principle surface. The third ground conductor and the signal conductor are located at the same position in the thickness direction of the dielectric body. The second and third ground conductors are connected to the first ground conductor via interlayer-connector conductors. The width of the second and third ground conductors is narrower than the width of the signal conductor, but a sum of the widths of the second and third ground conductors is larger than the width of the signal conductor. |
| US09570781B2 |
Optical waveguide methods for detecting internal faults in operating batteries
Light is transmitted from a light source through or from a separator of a battery cell and received by one or more light detectors. The light that is normally transmitted through the separator is scattered, absorbed, wavelength-shifted or otherwise distorted by an impending fault in the vicinity of or within the separator. The change in light due to the impending fault is measured by a detector and a signal from the detector is processed to identify the impending fault so that a warning can be generated indicative of the impending fault. In particular, the separator and a battery cell electrolyte can be selected to provide waveguide properties. |
| US09570779B2 |
Flooded lead-acid battery
A flooded lead-acid battery, including a negative electrode plate holding a negative active material, a positive electrode plate holding a positive active material, and a flowable electrolyte solution in which these plates are immersed, and allowing the electrolyte solution to have a utilization factor greater than or equal to 75%, wherein the concentration of an alkali metal ion or an alkaline earth metal ion in the electrolyte solution is allowed to be 0.07 to 0.3 mol/L, and the pore volume of the negative active material after formation is allowed to be 0.08 to 0.16 mL/g. |
| US09570777B2 |
Lithium secondary battery
A lithium secondary battery of the present invention includes: a positive electrode; a negative electrode; a nonaqueous electrolytic solution; and a separator. The positive active material contains a lithium-containing composite oxide containing nickel. A molar ratio of a total nickel amount with respect to a total lithium amount contained in the entire positive active material is 0.05 to 1.0. The nonaqueous electrolytic solution contains 0.5 to 5.0 mass % of a phosphonoacetate-based compound represented by the following General Formula (1). In the Formula, R1, R2, and R3 independently represent an alkyl group, an alkenyl group, or an alkynyl group having 1 to 12 carbon atoms, which may be substituted by a halogen atom, and “n” represents an integer of 0 to 6. |
| US09570776B2 |
Lithium-ion secondary battery and method of producing the same
Provided is a battery in which collector foil is unlikely to break.In a lithium-ion secondary battery, as for a distance from a connection section between a positive electrode tab and the positive electrode terminal to a boundary section between applying and non-applying sections of positive-electrode active material in a direction perpendicular to a stacking direction, compared with a reference positive electrode having the boundary section that is located farthest to the connection section by straight-line distance, a layer of a positive electrode that is stacked in such a way as to be farthest from the reference positive electrode has a smaller distance from a boundary of the applying and non-applying sections of the positive-electrode active material to a connection section with the positive electrode tab in a direction perpendicular to a stacking direction. |
| US09570774B2 |
Battery having enhanced electrical insulation capability
Disclosed is a battery including a cathode in which cathode active-material coating layers provided on both surfaces of a cathode collector are longitudinally deviated from each other, and an anode having at least one anode active-material coating layer provided on an anode collector, the cathode and anode being wound to face each other with a separator interposed therebetween. At least one of a winding beginning portion and winding ending portion of the cathode is provided with a cathode uncoated part for installation of a cathode lead. An insulator tape is attached to the boundary of the cathode active-material coating layer at a position where the anode active-material coating layer faces a non-coating part of the cathode not containing the cathode active-material coating layer, achieving enhanced electrical insulation capability and consequential safety of the battery. |
| US09570768B2 |
Fuel cell system and control method thereof
A fuel cell system 100 includes a fuel cell 10, a cathode gas supply system 30, a supply valve 34, an exhaust valve 43 and a controller 20. The fuel cell 10 has a supply manifold M1, an exhaust manifold M2, and a power generation area GA connected with these manifolds M1 and M2. The cathode gas supply system 30 causes a gas to be flowed into the supply manifold M1. The supply valve 34 is operable to seal the supply manifold M1, whereas the exhaust valve 43 is operable to seal the exhaust manifold M2. The controller 20 closes the supply valve 34 and the exhaust valve 43 after operation stop of the fuel cell 10 to seal the fuel cell 10 under a specified pressure and then waits for a predefined time. The controller 20 subsequently opens the supply valve 34 to move water remaining in the power generation area GA on the flow of the gas toward outside of the power generation area GA. |
| US09570765B2 |
Fuel supply unit
A hydrogen supply unit is configured to inject hydrogen gas having flowed in an inflow passage into an outflow passage by use of an injector to reduce the pressure of the hydrogen gas. The hydrogen supply unit includes a primary-side relief valve for releasing the hydrogen gas from inside to outside of the inflow passage when the internal pressure of the inflow passage rises to a first predetermined value, and a secondary-side relief valve for releasing the hydrogen gas from inside to outside of the outflow passage when the internal pressure of the outflow passage rises to a second predetermined value. The primary-side relief valve and the secondary-side relief valve are held between the inflow block and the outflow block. |
| US09570758B2 |
Manufacturing method and manufacturing apparatus for gas diffusion layer of fuel cell, and fuel cell
A method of manufacturing a fuel cell. An insulating member has a plurality of communication holes disposed on a side of a gas diffusion layer, which is formed by stacking a layer made of a carbon fiber and a water-repellent layer, where the water-repellent layer is provided. The gas diffusion layer and the insulating member are sandwiched by a pair of electrodes, and a pair of contact pressure plates are disposed on respective rear surfaces of the pair of electrodes so as to sandwich the pair of electrodes so that the gas diffusion layer is pressurized by the pair of contact pressure plates. When a voltage is applied to the pair of electrodes while maintaining the pressurized state, the protrusion portion of the carbon fiber is burned and removed by Joule heat. |
| US09570757B2 |
Fuel cell catalyst layer and uses thereof
Provided is a fuel cell catalyst layer which has a catalytic performance equivalent to or higher than fuel cell catalyst layers containing platinum alone and which is inexpensive. The fuel cell catalyst layer of the present invention includes a metal oxycarbonitride-containing layer (I) and a platinum-containing layer (II). It is preferable that the mass ratio per unit area of the metal oxycarbonitride in the layer (I) to platinum in the layer (II) (metal oxycarbonitride/platinum) is 2 to 500. It is preferable that the mass per unit area of platinum in the layer (II) is 0.005 to 0.2 mg/cm2. |
| US09570748B2 |
Lipon coatings for high voltage and high temperature Li-ion battery cathodes
A lithium ion battery includes an anode and a cathode. The cathode includes a lithium, manganese, nickel, and oxygen containing compound. An electrolyte is disposed between the anode and the cathode. A protective layer is deposited between the cathode and the electrolyte. The protective layer includes pure lithium phosphorus oxynitride and variations that include metal dopants such as Fe, Ti, Ni, V, Cr, Cu, and Co. A method for making a cathode and a method for operating a battery are also disclosed. |
| US09570746B2 |
Olivine-type cathode active material precursor for lithium battery, olivine-type cathode active material for lithium battery, method for preparing the same and lithium battery with the same
The present invention provides an olivine-type positive active material precursor for a lithium battery that includes MXO4-zBz (wherein M is one element selected from the group consisting of Fe, Ni, Co, Mn, Cr, Zr, Nb, Cu, V, Ti, Zn, Al, Ga, Mg, B, and a combination thereof, X is one element selected from the group consisting of P, As, Bi, Sb, and a combination thereof, B is one element selected from the group consisting of F, S, and a combination thereof, and 0≦z≦0.5) particles, and the precursor has a particle diameter of 1 to 20 μm, a tap density of 0.8 to 2.1 g/cm3, and a specific surface area of 1 to 10 m2/g. The olivine-type positive active material prepared using the olivine-type positive active material precursor has excellent crystallinity of particles, a large particle diameter, and a high tap density, and therefore shows excellent electrochemical characteristics and capacity per unit volume. |
| US09570744B2 |
Lithium ion secondary battery
[Problem] To provide a lithium ion secondary battery having excellent high-rate discharge characteristics. [Solution] Excellent high-rate discharge characteristics are obtained by a lithium ion secondary battery in which a compound represented by Lia(NixCoyAl1-x-y)O2 (where 0.95≦a≦1.05, 0.5≦x≦0.9, 0.05≦y≦0.2, and 0.7≦x+y≦1.0) is used as a positive electrode active material in a positive electrode, the positive electrode has an electrode density of 3.75 to 4.1 g/cm3, and the positive electrode has a BET specific surface area of 1.3 to 3.5 m2/g as an electrode. |
| US09570743B2 |
Positive active material precursor for rechargeable lithium battery, method of preparing positive active material for rechargeable lithium battery using the same, and rechargeable lithium battery including the prepared positive active material for rechargeable lithium battery
Provided are a positive active material precursor for a rechargeable lithium battery including a metal oxide represented by Chemical Formula 1, a positive active material for a rechargeable lithium battery that is obtained by using the positive active material precursor for a rechargeable lithium battery and includes a compound represented by a Chemical Formula 2, and a rechargeable lithium battery including the positive active material for a rechargeable lithium battery. |
| US09570738B2 |
Positive active material, positive electrode and lithium battery including the positive active material, and method of manufacturing the positive active material
A positive active material, a positive electrode and a lithium battery containing the positive active material, and a method of manufacturing the positive active material are disclosed. The positive active material includes: a positive active material core particle for intercalating and deintercalating lithium ions; and a coating layer at least partially surrounding the positive active material core particle and including a ceramic composite represented by Formula 1. Li7+aLa3−bZr2−cMdO12+e Formula 1 In Formula 1, M comprises at least one selected from aluminum (Al), titanium (Ti), scandium (Sc), vanadium (V), yttrium (Y), niobium (Nb), hafnium (Hf), tantalum (Ta), silicon (Si), gallium (Ga), and germanium (Ge), and −1≦a≦1, 0≦b≦2, 0≦c≦2, 0≦d≦2, and 0≦e≦1. |
| US09570735B2 |
Degassing method for electrode paste
Provided is a degassing method for an electrode paste that introduces the electrode paste formed by kneading a solid content containing an electrode active material and a dispersion medium into a decompressed container and degassing the electrode paste while a shear force is applied to the electrode paste. A ratio of the solid content in the electrode paste is set to be 55 mass % or more, and a pressure in the decompressed container is set to be −50 kPa or more. It is possible to suppress both remaining bubbles and dry of the electrode paste, thus enhancing a product yield. |
| US09570733B2 |
Rechargeable battery
A rechargeable battery includes an electrode assembly including a first electrode tab protruded at a first end, and a second electrode tab protruded at a second end; a case having an open side and receiving the electrode assembly; a cap assembly including a cap plate covering the open side of the case, a first current collecting member coupled to a lower side of the cap plate and electrically connected to the first electrode tab, and a second current collecting member coupled to the lower side of the cap plate; and a safety member arranged on an outer surface of the electrode assembly, and the first electrode tab is protruded at the first end toward the cap plate, the second electrode tab is protruded at the second end away from the cap plate, and the second electrode tab is electrically connected to the second current collecting member through the safety member. |
| US09570732B2 |
Battery system safety shield and method
Storage batteries connected in series in an uninterruptible or back-up power supply system may have voltage potential differences between exposed terminals or conductors that exceed safety limits. A demountable insulating shield having apertures may be positioned so that the series string may be broken into a plurality of series sub-strings having a lesser potential difference has a cover over the aperture through which the series string configuration may be connected and disconnected. The cover may be an insulating material removably fastened to the insulating shield or a sliding cover that is captivated to the insulating shield. When the series string has been divided in to the sub-strings, the insulating shield may be demounted from the structure housing the batteries so that the batteries or their connections may be serviced. |
| US09570730B2 |
Bridge power connector
A bridge power connector includes upper and lower connector assemblies. The upper connector assembly has an upper housing holding an upper power conductor connected to a first electrical component. The lower connector assembly has a lower housing holding a lower power conductor electrically connected to a second electrical component. The upper housing is removably coupled to the lower housing using securing mechanisms to form a low-profile housing. The upper power conductor extends from a first side of the low-profile housing while the lower power conductor extends from a second side of the low-profile housing. The upper and lower power conductors extend along a mating plane of the low-profile housing. The upper power conductor is separable from the lower power conductor when the upper housing is removed from the lower housing. |
| US09570729B2 |
Electrical energy storage module and method for producing an electrical energy storage module
The invention relates to an electrical energy storage module, comprising at least one storage cell stack (7) that has a plurality of groups of first planar parallel energy storage cells (1), each having first electrode elements (1a), and a plurality of groups of second planar parallel energy storage cells (2) arranged planar parallel to the group of first energy storage cells (1), said second groups each having second electrode elements (2a). The groups of first and second energy storage cells (1; 2) are arranged alternately along a first direction of extension of the storage cell stack (7) and the first electrode elements (1a) have a polarity on a side face of the storage cell stack (7) that is different from the second electrode elements (2a) on the side face of the storage cell stack (7). The energy storage module further comprises a plurality of flat contact elements (5) that are arranged on the side faces of the storage cell stack (7), galvanically connect adjacent groups of first and second energy storage cells (1; 2), and contact substantially all first or second electrode elements (1a; 2a) of the adjacent groups of first and second energy storage cells (1; 2) across the width of the storage cell stack (7) in each case. |
| US09570725B2 |
Separator for nonaqueous electrolyte battery, and non-aqueous electrolyte secondary battery
Disclosed is a separator for a non-aqueous electrolyte battery, the separator including a polyolefin microporous substrate in which a content of polyolefin having a molecular weight of 100,000 or less is from 10% by mass to 25% by mass relative to a total amount of polyolefin, and a heat resistant porous layer that is formed on one or both sides of the polyolefin microporous substrate and that includes a heat resistant polymer, wherein a maximum value of S, which is represented by the following formula (1), is 0.8 or more, and a temperature exhibiting the maximum value of S is from 130° C. to 155° C.: S=d(log R)/dT Formula (1): wherein R represents a resistance (ohm·cm2) of a cell, and T represents a temperature (° C.), in a measurement using a battery that includes the cell that is provided with a separator for a non-aqueous electrolyte battery, at a temperature rising rate of 1.6° C./min. |
| US09570718B2 |
Packaging material for batteries
A packaging material for batteries, which is formed of a laminate that sequentially includes a base layer, an adhesive layer, a barrier layer and a sealant layer in this order. By having the adhesive layer formed of a cured product of a resin composition that contains a thermosetting resin and (A) a curing accelerator and an elastomer resin or (B) reactive resin beads, the adhesive layer arranged between the base layer and the barrier layer can be cured in a short time, thereby reducing the lead time. In addition, by providing the adhesive layer between the base layer and the barrier layer, the adhesion strength between the base layer and the barrier layer is increased and excellent formability can be achieved. |
| US09570717B2 |
Organic luminescent materials, coating solution using same for organic
It is an object of the present invention to provide an organic light-emitting device which can emit white light by easily controlling dopant concentrations. The organic light-emitting device has a first electrode (112) and second electrode (111) which hold a light-emitting layer (113) in-between, wherein the light-emitting layer contains a host material (104), red-light-emitting dopant (105), green-light-emitting dopant (106) and blue-light-emitting dopant (107), the red-light-emitting dopant containing a first functional group for transferring the dopant toward the first electrode and the green-light-emitting dopant containing a second functional group for transferring the dopant toward the second electrode. |
| US09570715B2 |
Mask and mask assembly
A mask supported at a frame when a tensile force is applied in a first direction is provided. The mask includes a mask main body in a band shape extended in the first direction, and a plurality of pattern openings formed in the mask main body. the mask main body has ends supported by the frame, and the pattern opening are arranged in the first direction. The mask further includes a dummy opening provided between the pattern openings and one of the ends of the mask main body. The dummy opening has a form that is different from forms of the pattern openings. |
| US09570714B2 |
Organic layer deposition assembly, organic layer deposition apparatus, organic light-emitting display apparatus and method of manufacturing the same
An organic layer deposition assembly, an organic layer deposition apparatus, an organic light-emitting display apparatus, and a method of manufacturing the organic light-emitting display apparatus, in order to improve a characteristic of a deposited layer, the organic layer deposition assembly including a deposition source for discharging a deposition material; a deposition source nozzle unit disposed at a side of the deposition source, and including a plurality of deposition source nozzles; and a patterning slit sheet disposed while facing the deposition source nozzle unit, and including a plurality of patterning slits and one or more alignment confirmation pattern slits that are formed at edge portions of the plurality of patterning slits, wherein the deposition material that is discharged from the deposition source passes through the patterning slit sheet and then is formed on the substrate, while a deposition process is performed. |
| US09570710B2 |
Organic light-emitting display apparatus and method of manufacturing the same including RGB insulating layer configuration
An organic light-emitting display apparatus, including a substrate; a first reflective layer, a second reflective layer, and a third reflective layer that are separately disposed on the substrate; a first insulating layer on the first reflective layer, but not on the second reflective layer and the third reflective layer; a second insulating layer on the first insulating layer and the second reflective layer, but not on the third reflective layer; and a first pixel electrode for red emission on the second insulating layer and corresponding to the first reflective layer, a second pixel electrode for green emission on the second insulating layer and corresponding to the second reflective layer, and a third pixel electrode for blue emission on the third reflective layer. |
| US09570709B2 |
Method for manufacturing ultrathin organic light-emitting device
The present invention relates to a method for manufacturing an ultrathin organic light-emitting device and, more specifically, to a method for manufacturing an ultrathin organic light-emitting device capable of dramatically reducing the thickness thereof, in addition to improving light extraction efficiency. To this end, the present invention provides a method for manufacturing an ultrathin organic light-emitting device, comprising: a polymer material coating step for coating a polymer material onto a support; a frit coating step for coating a frit paste onto the polymer material; a heat treatment and separation step for conducting heat treatment at a temperature at which the polymer material breaks down, thereby separating the support and a frit substrate which has been formed by heat-treating the frit paste; and a device layer forming step for forming, in sequence, a device layer comprising a first electrode, a device layer comprising an organic light-emitting layer, and a device layer comprising a second electrode, on one side of the frit substrate which has been in contact with the polymer material. |
| US09570703B2 |
Organic light emitting display with reinforced sealing structure
An organic light emitting display includes a first substrate; a second substrate opposing the first substrate; and an array of pixels disposed between the first substrate and the second substrate. The display further includes a seal member interposed between and bonded to the first and second substrates to seal a gap between the first and second substrates; a plurality of pillar members positioned between and bonded to the first and second substrates, the plurality of pillar members being positioned outside and spaced from the seal member when viewing in a direction perpendicular to a major surface of the first mother substrate; and a reinforcement member disposed between the first and second substrates, and comprising portions disposed between the seal member and the pillar members. The plurality of pillar members are spaced apart from each other. |
| US09570696B2 |
White organic light emitting device
Provided is a white organic light emitting device which can improve abnormal light emission and efficiency and reliability of the device.A white organic light emitting device according to an exemplary embodiment of the present invention includes: a first light emitting unit including a first emitting layer between a first electrode and a second electrode; a second light emitting unit including a second emitting layer on the first light emitting unit; and a charge generation layer between the first light emitting unit and the second light emitting unit, and a volume of a metal in the charge generation layer is 1.0% or less of the total volume of the charge generation layer. |
| US09570693B2 |
Display device and method of manufacturing the same
A display device includes a display panel, a top member, and a bottom member. The top member is disposed on the display panel, and has a first groove region where at least a portion of an upper surface of the display panel is exposed. The bottom member is disposed under the display panel, and has a second groove region where at least a portion of a lower surface of the display panel is exposed. The first and second groove regions are located at a bending region of the display device. |
| US09570688B2 |
Semiconductor materials prepared from bridged bithiazole copolymers
The present invention provides semiconducting compounds, oligomers and polymers of formula wherein A1 and A2 can be the same or different and are S or Se, E is selected from the group consisting of The compounds, oligomers and polymers of formula of formula (1) are suitable for use in electronic devices such as organic field effect transistors. |
| US09570680B2 |
Method for fabricating electronic devices having semiconductor memory unit
Devices and method based on disclosed technology include, among others, a method for capable of providing asymmetrical arrangement of hole patterns while improving non-uniformity of an electronic device. Specifically, a method for fabricating hole patterns in one implementation includes forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over a layer to be etched; and etching the layer to be etched, using the mask pattern as an etch barrier. |
| US09570679B2 |
Nanodevice assemblies
A semiconductor structure is described containing a deflector between a first nanoscale device and a second nanoscale device. The deflector is designed to deflect near-field radiation from emanating from the first nanoscale device to the second nanoscale device. In some embodiments, this may be accomplished using at least one nanoscale element located between the first and second nanoscale device, where the nanoscale element is tuned to the proper plasmon-polariton frequency to deflect the near field radiation. |
| US09570678B1 |
Resistive RAM with preferental filament formation region and methods
A non-volatile memory device includes a first dielectric on a substrate, a first electrode disposed on the first dielectric, a second dielectric material disposed next to the first electrode, a patterned material disposed upon the second dielectric material and in contact with part of the first electrode, a third dielectric material disposed next to the patterned material and in contact with another part of the first electrode, wherein the patterned material and the third dielectric material contact at an interface region, wherein the interface region is characterized by a plurality of defects, a second electrode disposed on the patterned material, on the third dielectric, and on the interface region, wherein the second electrode comprises metal particles that are configured to be diffused within the interface region upon application of a bias voltage, and wherein metal particles are disposed within the plurality of defects in the interface region. |
| US09570672B2 |
Method of making current sensors
The invention relates to a method for the production of current sensors which comprise a plastic housing made in an IC technology. The key steps are to mount on a leadframe and wire bond semiconductor chips having Hall sensors, to place the leadframe in an injection mold, to close the injection mold with a first mold insert and to inject plastic material, wherein each semiconductor chip is packed into an intermediate casing including a flat surface having alignment structures. Then the injection mold is opened and a current conductor section is placed on the flat surface of each intermediate casing, the current conductor section having counter structures matching the alignment structures so that it is automatically aligned and held. Then the injection mold is closed with a second mold insert and plastic material injected to form the final housing of the current sensors. It is also possible to use two different injection molds. |
| US09570669B2 |
Piezoelectric component and method for producing a piezoelectric component
A piezoelectric component has at least one piezoelectric ceramic layer and at least one electrode adjacent the piezoelectric ceramic layer. The piezoelectric ceramic layer has a piezoelectric ceramic material of the general formula Pb1-x-y-[(2a-b)/2]-p/2V[(2a-b)/2-p/2]″CupBaxSry[(TizZr1-z)1-a-bWaREb]O3, where 0≦x≦0.035, 0≦y≦0.025, 0.42≦z≦0.5, 0.0045≦a≦0.009, 0.009≦b≦0.011, 2a>b, p≦2a−b, RE is a rare earth metal, and V″ is a Pb vacancy. |
| US09570668B2 |
Piezoelectric device and method for manufacturing piezoelectric device
In a method for manufacturing a piezoelectric device while stably achieving strong bonding, a moisture-absorbing layer is formed on a bonding surface side of a piezoelectric single-crystal substrate. The moisture-absorbing layer is allowed to absorb moisture. A binder layer is formed on a bonding surface side of a supporting substrate. The moisture-absorbing layer is placed on the binder layer. A silica precursor in the binder layer is converted into silica through a hydrolysis reaction with moisture in the moisture-absorbing layer. |
| US09570664B2 |
Light emitting device package, backlight unit, lighting device and its manufacturing method
Provided are a light emitting device package, a backlight unit, a lighting device and its manufacturing method. The light emitting device package may include a flip chip type light emitting device having a first pad and a second pad, a lead frame that includes a first electrode disposed at one side of an electrode separation space, and a second electrode disposed at the other side of the electrode separation space, and on which the light emitting device is mounted, a first bonding medium formed between the first pad of the light emitting device and the first electrode of the lead frame to electrically connect the first pad and the first electrode, and a second bonding medium formed between the second pad of the light emitting device and the second electrode of the lead frame to electrically connect the second pad and the second electrode, wherein at least one first accommodating cup capable of accommodating the first bonding medium is formed in the first electrode of the lead frame, wherein at least one second accommodating cup capable of accommodating the second bonding medium is formed in the second electrode of the lead frame, and wherein at least one air discharge path is formed on each of the first and second accommodating cups. |
| US09570659B2 |
Semiconductor device for emitting frequency-adjusted infrared light
A semiconductor device for emitting frequency-adjusted infrared light includes a lateral emitter structure and a lateral filter structure. The lateral emitter structure is configured to emit infrared light with an emitter frequency distribution. Further, the lateral filter structure is configured to filter the infrared light emitted by the lateral emitter structure so that frequency-adjusted infrared light is provided with an adjusted frequency distribution. The frequency range of the adjusted frequency distribution is narrower than a frequency range of the emitter frequency distribution. Further, a lateral air gap is located between the lateral emitter structure and the lateral filter structure. |
| US09570656B2 |
Group III nitride semiconductor light-emitting device
The present invention provides a Group III nitride semiconductor light-emitting device having a flat semiconductor layer, in which the stress applied to the light-emitting layer is relaxed. The light-emitting layer of the light-emitting device includes a well layer and a barrier layer comprising an AlGaN layer containing In. The light-emitting device has a pit extending from an n-type semiconductor layer to layers above the light-emitting layer. A pit diameter at an interface between the light-emitting layer and the n-type semiconductor layer is 120 nm to 200 nm. The barrier layer has an In concentration of 6.0×1019 cm−3. |
| US09570655B2 |
Semiconductor light-emitting device
Provided is a light-emitting device that has a high emission efficiency, excellent stability and temperature properties, and that generates light having a high color rendering property sufficient for practical use. This semiconductor light-emitting device (1) comprises a semiconductor light-emitting element (2) that emits blue light, a green phosphor (14) that absorbs the blue light and emits green light, and an orange phosphor (13) that absorbs the blue light and emits orange light, and is characterized in that the orange phosphor is an Eu-activated α-SiAlON phosphor having an emission spectrum peak wavelength within a range of 595 to 620 nm. |
| US09570653B2 |
Light-emitting semiconductor structure and method for fabricating light-emitting diode device
A method for fabricating a light-emitting device is provided. The method includes: providing a substrate; forming a sacrificial dielectric layer on the substrate, wherein the sacrificial dielectric layer is a structure containing voids; forming a buffer layer on the sacrificial dielectric layer; forming an epitaxial light-emitting structure on the buffer layer; forming a metal bonding layer on the epitaxial light-emitting structure; bonding the metal bonding layer to a thermally conductive substrate; and wet etching the sacrificial dielectric layer for to remove the substrate. |
| US09570651B2 |
Coalesced nanowire structures with interstitial voids and method for manufacturing the same
A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer. |
| US09570648B2 |
Wafer level optical proximity sensors and systems including wafer level optical proximity sensors
Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint. |
| US09570645B2 |
Photodiode and method of manufacturing the same, and X-ray detector and method of manufacturing the same
A photodiode and a method of manufacturing the same, and an X-ray detector and a method of manufacturing the same are provided. The PIN photodiode includes a first doped layer, a second doped layer and an intrinsic layer between the first and second doped layers, the first doped layer is provided on a source/drain electrode layer of a thin film transistor of the X-ray detector. A heavily-doped region is provided in the second doped layer, has a dosage concentration larger than that of the second doped layer, and is electrically connected with a cathode of the PIN photodiode. |
| US09570644B2 |
Conversion of high-energy photons into electricity
Systems and methods for the conversion of energy of high-energy photons into electricity which utilize a series of materials with differing atomic charges to take advantage of the emission of a large multiplicity of electrons by a single high-energy photon via a cascade of Auger electron emissions. In one embodiment, a high-energy photon converter preferably includes a linearly layered nanometric-scaled wafer made up of layers of a first material sandwiched between layers of a second material having an atomic charge number differing from the atomic charge number of the first material. In other embodiments, the nanometric-scaled layers are configured in a tubular or shell-like configuration and/or include layers of a third insulator material. |
| US09570643B2 |
System and method for enhanced convection cooling of temperature-dependent power producing and power consuming electrical devices
A cooling system for cooling a temperature-dependent power device includes an active cooling device and a controller to generate and transmit a drive signal thereto to selectively activate the device. The controller receives an input from sensors regarding the cooling device power consumption and measured operational parameters of the power equipment—including the power device output power if the device is a power producing device or the power device input power if the device is a power consuming device. The controller generates and transmits a drive signal to the cooling device based on the cooling device power consumption and the measured power device input or output power in order to cause the active cooling device to selectively cool the heat producing power device. A net system power output or total system power input can be maximized/minimized by controlling an amount of convection cooling provided by the cooling device. |
| US09570640B2 |
Method of manufacturing solar cell module, and solar cell module
A method of manufacturing a solar cell module includes preparing a solar cell substrate including a support substrate, an electric power generating layer that receives light beams and generates electric power, and a conductive layer that is formed on the electric power generating layer, forming a resist layer on the conductive layer in such a manner that an exposed portion at which the conductive layer is exposed is formed, forming an electric conduction portion at a part of the exposed portion, and etching the conductive layer by using the resist layer and the electric conduction portion as a mask. |
| US09570639B2 |
System with gradual change of light distribution or shadow distribution on a surface comprising light elements or photovoltaic elements
The present invention refers to a system including light processing elements, arranged in a respective installation area and combined with a respective construction, at least partially above and/or next to an occupational or passage space, whereby said light processing elements or respective constructions produce a general light distribution over said occupational or passage space, that is more favorable in terms of visual performance and comfort, and that may assist and adjust to activities requiring different levels thereof. The inventive system is used for energy and/or information conversion and distribution, as part of one construction or clusters of constructions, for example disposed along traffic ways. |
| US09570631B2 |
Oxide semiconductor substrate and schottky barrier diode
A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component. |
| US09570628B2 |
Semiconductor device
An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths. |
| US09570626B2 |
Insulating film, method for manufacturing semiconductor device, and semiconductor device
In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber. |
| US09570622B2 |
Semiconductor device and method for manufacturing the same
To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer. The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion. |
| US09570618B1 |
TFT substrate manufacturing method and TFT substrate
The present invention provides a TFT substrate manufacturing method and a TFT substrate. The TFT substrate manufacturing method of the present invention applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer. Further, due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability. |
| US09570611B2 |
Method and device for high k metal gate transistors
A method of manufacturing a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a dummy gate structure formed thereon and an offset spacer formed on a sidewall of the dummy gate structure. The method further includes removing the dummy gate structure to form a gate trench, forming a high-k dielectric layer on the bottom and the sidewall of the gate trench, and forming a cover layer over the high-k dielectric layer. The cover layer has a thickness that is greater at the corners of the bottom of the gate trench than in the middle region of the bottom of the gate trench. |
| US09570610B2 |
Method of manufacturing semiconductor device
To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film. |
| US09570609B2 |
Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed. |
| US09570599B2 |
Transistor having nitride semiconductor used therein and method for manufacturing transistor having nitride semiconductor used therein
A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode. |
| US09570593B2 |
Semiconductor device and method for manufacturing the same
A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode. |
| US09570591B1 |
Forming semiconductor device with close ground rules
A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack. |
| US09570588B2 |
Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure. |
| US09570586B2 |
Fabrication methods facilitating integration of different device architectures
Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor. |
| US09570584B2 |
Semiconductor structure and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region. |
| US09570582B1 |
Method of removing dummy gate dielectric layer
A method of removing a dummy gate dielectric layer is provided. Firstly a first plasma containing F is utilized to remove the dummy dielectric layer which contains Si and O. Then a second plasma containing H2 is utilized to remove fluorine compound on the surface of the semiconductor substrate. Since the fluorine residue formed after the first plasma treatment reacts with the second plasma to form a gaseous product HF, the fluorine element can be taken away from the semiconductor device with the HF, which prevents inversion layer offset and gate current leakage occurred in the subsequent processing steps due to the fluorine element. |
| US09570580B1 |
Replacement gate process for FinFET
A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin. |
| US09570579B2 |
Semiconductor structures and methods for multi-level work function
Semiconductor devices that each include a channel region and a gate stack are disclosed. The gate stack includes a gate insulator, a pair of spaced apart first metal gate layers, and a second metal gate layer. The gate insulator extends along the length of the channel region. The first metal gate layers have a first workfunction and extend from the gate insulator. The second metal gate layer is disposed between the first metal gate layers, has a second workfunction different from the first workfunction, and extends from the gate insulator. Methods of fabricating the gate stack are also disclosed. |
| US09570578B2 |
Gate and gate forming process
A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors. |
| US09570568B2 |
Semiconductor component and method for fabricating the same
A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer. |
| US09570566B2 |
Semiconductor device including a trench at least partially filled with a conductive material in a semiconductor substrate
A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided. |
| US09570564B2 |
Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor. |
| US09570562B1 |
Method of planarizing polysilicon gate
A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes. |
| US09570559B2 |
Graphene device including angular split gate
An electronic device can include a dielectric layer, and a graphene layer including a first surface located upon the dielectric layer. The electronic device can include a first electrode, a second electrode, and a third electrode each located upon the dielectric layer on a surface opposite the graphene layer. The first and second electrodes can be spaced apart along a longitudinal axis of the electronic device to define a first gap between the first and second electrodes, and the second and third electrodes are spaced apart along the longitudinal axis of the electronic device to define a second gap between the second and third electrodes. At least one of the first gap or the second gap can be angled so as to be neither parallel nor perpendicular to the longitudinal axis of the electronic device. |
| US09570556B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure, and a second void is formed in the source/drain structure and located above the first void. |
| US09570550B1 |
Stacked nanowire semiconductor device
A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions. |
| US09570548B2 |
Deep trench isolation structures and systems and methods including the same
Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures. |
| US09570547B2 |
Monolithic DMOS transistor in junction isolated process
A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon. |
| US09570538B2 |
Methods of manufacturing polyresistors with selected TCR
Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR. |
| US09570534B2 |
Organic light emitting diode display
An organic light emitting diode display includes: a substrate including a first and a second gate electrode formed over a first and a second region, respectively, a first and a second gate insulator formed on the first and the second gate electrode, respectively, a first and a second semiconductor layer formed on the first and the second gate insulator, respectively, the first semiconductor layer including a first channel region, the second semiconductor layer including a second channel region, an interlayer insulator formed over the substrate and over at least part of the first and second semiconductor layers, a first and a second etching stop layer formed over the first and second channel regions, respectively, and surrounded by the interlayer insulator, and a first and a second source electrode and a first and a second drain electrode contacting the first and the second semiconductor layer, respectively, through the interlayer insulator. |
| US09570530B2 |
Active matrix organic light-emitting-diode display backboard and manufacturing method thereof, display device
An AMOLED display backboard, a display device and a manufacturing method of an AMOLED display backboard are provided. In the AMOLED display backboard, the number of VDD lines (601) is less than that of sub-pixels in one row, thus reducing area occupied by the VDD lines (601), lessening occupation of VDD lines (601) on the area of circuit board, while realizing connection of circuit input terminals (603) of respective sub-pixels and VDD lines (601) by the VDD connecting line (602). |
| US09570524B2 |
Flexible organic light emitting diode display panel
Provided is a flexible organic light emitting diode display panel including: a substrate in which an opening region and a non-opening region are defined; an organic light emitting diode disposed on the substrate; a bank layer disposed in the non-opening region; and a peeling reduction layer having a reverse-tapered shape disposed in the non-opening region. |
| US09570523B2 |
Organic light emitting display
A method of making a display device includes forming first electrodes of organic light emitting diodes in respective pixel areas on a substrate, forming a first common layer on the first electrodes in the pixel areas, forming emission layers in the pixel areas on the first common layer, forming a second electrode of the organic light emitting diodes on the emission layer, and applying physical pressure to divide the first common layer. |
| US09570520B2 |
Light emitting device
A light emitting device, including a first electrode; a hole transport area on the first electrode; a first light emitting layer on the hole transport area, the first light emitting layer emitting a first color, and having a first thickness; a second light emitting layer adjacent to one side of the first light emitting layer, the second light emitting layer emitting a second color, and having a second thickness; a first shadow layer on the first light emitting layer, the first shadow layer including a same material as the second light emitting layer, and first shadow layer having a thickness corresponding to about 1% of the second thickness; an electron transport area on the first light emitting layer, the second light emitting layer, and the first shadow layer; and a second electrode on the hole transport area. |
| US09570517B2 |
Organic light emitting display device and method of manufacturing the same
An organic light emitting display device includes a substrate and a plurality of pixels defined in the substrate. A pixel includes red subpixel, green subpixel, blue subpixel, and white subpixel. The organic light emitting display device includes an anode electrode formed on the substrate, a cathode electrode opposing the anode electrode, and a red common emission layer, a green common emission layer, and a blue common emission layer formed across each of the red, green, blue and white subpixel areas. The blue common emission layer is disposed above and adjacent to the anode electrode, the green common emission layer is disposed above the blue common emission layer, and the red common emission layer is disposed above the green common emission layer and adjacent to the cathode electrode. |
| US09570516B2 |
Method for forming PCM and RRAM 3-D memory cells
A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies. |
| US09570515B2 |
Memory element with a reactive metal layer
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays. |
| US09570512B2 |
High density resistive random access memory (RRAM)
A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line. |
| US09570510B2 |
Magnetoresistive random access memory devices and methods of manufacturing the same
An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other. |
| US09570509B2 |
Magnetic tunnel junction (MTJ) device array
A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device. |
| US09570506B2 |
Photoelectric conversion device and manufacturing method of the same
A photoelectric conversion device includes a pixel circuit section including: a first semiconductor region containing a first conductivity type impurity; a second semiconductor region formed in the first semiconductor region by using the first conductivity type impurity; a third semiconductor region formed in the second semiconductor region by using a second conductivity type impurity; and a contact plug formed on the third semiconductor region. A net concentration of the first conductivity type impurity is higher in the second semiconductor region than in the first and third semiconductor regions. In the second and third semiconductor regions, a distance between the contact plug and a position where the concentration of the second conductivity type impurity is maximum is equal to or less than a distance between the contact plug and a position where the concentration of the first conductivity type impurity is maximum. |
| US09570496B2 |
Solid-state imaging element and electronic device
The present disclosure relates to a solid-state imaging element and an electronic device capable of suppressing occurrence of a dark current and acquiring higher image quality.The solid-state imaging element includes a high-concentration diffusion layer configured to serve as a connection portion by which a wiring is connected to a semiconductor substrate, and a junction leak control film formed to cover a surface of the diffusion layer. Also, to connect the wiring to the diffusion layer, a width of an opening formed in an insulation film stacked on the semiconductor substrate is greater than a width of the diffusion layer. Further, in a charge accumulation portion configured to accumulate a charge generated by a photoelectric conversion portion generating the charge according to an amount of received light, the junction leak control film is also used as a capacitor film of the charge accumulation portion. Furthermore, a stack structure in which a silicon oxide or low interface state oxide film is formed is included between the diffusion layer and the junction leak control film. The present technology can be applied to, for example, a CMOS image sensor. |
| US09570489B2 |
Solid state imaging device having impurity concentration on light receiving surface being greater or equal to that on opposing surface
A solid-state imaging device includes: a first photodiode made up of a first first-electroconductive-type semiconductor region formed on a first principal face side of a semiconductor substrate, and a first second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the first first-electroconductive-type semiconductor region; a second photodiode made up of a second first-electroconductive-type semiconductor region formed on a second principal face side of the semiconductor substrate, and a second second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the second first-electroconductive-type semiconductor region; and a gate electrode formed on the first principal face side of the semiconductor substrate; with impurity concentration of a connection face between the second first-electroconductive-type semiconductor region and the second second-electroconductive-type semiconductor region being equal to or greater than impurity concentration of a connection face of an opposite layer of the second first-electroconductive-type semiconductor region of the second second-electroconductive-type semiconductor region. |
| US09570488B2 |
Image sensor bending by induced substrate swelling
In some examples, techniques and architectures for fabricating an image sensor chip having a curved surface include placing a substrate on a first surface of an image sensor chip, wherein the first surface of the image sensor chip is opposite a second surface of the image sensor chip, and wherein the second surface of the image sensor chip includes light sensors to generate electrical signals in response to receiving light. Fabricating also includes modifying a volume of the substrate so as to impart forces on the image sensor chip to produce a curved image sensor chip. |
| US09570486B2 |
Solid-state imaging device and switching circuit
A solid-state imaging device includes: a photoelectric conversion unit which converts light into signal charges; an accumulation unit which accumulates the signal charges; a transfer transistor connected between the photoelectric conversion unit and the accumulation unit for transferring to the accumulation unit, the signal charges obtained through the conversion by the photoelectric conversion unit; an amplification transistor for amplifying the signal charges accumulated in the accumulation unit to generate a voltage signal, the amplification transistor having a gate connected to the accumulation unit; a reset transistor for resetting a voltage of the accumulation unit; a first amplification circuit for negatively feeding back the voltage signal generated by the amplification transistor to the reset transistor; and a second amplification circuit for positively feeding back the voltage signal generated by the amplification transistor to the amplification transistor. |
| US09570485B2 |
Solar-powered energy-autonomous silicon-on-insulator device
A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. |
| US09570482B2 |
Manufacturing method and manufacturing equipment of thin film transistor substrate
A manufacturing method and a manufacturing equipment of a thin film transistor substrate are provided. In the manufacturing method, after forming a gate and a gate insulating layer of a thin film transistor, a semiconductor layer and a first protection layer are sequentially deposited. After patterning the first protection layer, the patterned first protection layer is used as a mask to pattern the semiconductor layer to form a semiconductor channel of the thin film transistor. By the above solution, the invention can reduce the number of mask and therefore is beneficial to reduce the cost. |
| US09570478B2 |
Narrow bezel flat panel display
Provided is a flat panel display. A flat panel display includes: a lower panel defining a display area and a non-display area, a driver element and a line within the non-display area, a planar layer covering the lower panel, a first trench at the planar layer over the driver element and the line, a lower alignment layer on an upper surface of the planar layer and a lower surface of the first trench, the lower alignment layer exposing some upper surface of the planar layer at the first trench, and a sealant at the first trench. |
| US09570477B2 |
Thin film transistor array panel and manufacturing method of the same
A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer. |
| US09570475B2 |
Array substrate and manufacture method thereof
Embodiments of the disclosure provide an array substrate and a manufacture method thereof. The array substrate comprises a display region and a non-display region, the display region comprises a transistor, the transistor comprises a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are provided on the active layer and are respectively provided at two ends of the active layer. The non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer and is configured for aligning the source electrode and the drain electrode with the active layer in the case of re-fabricating the source electrode and the drain electrode. |
| US09570474B2 |
Display device and manufacturing method thereof
A display device includes a substrate including a plurality of pixel areas, a thin film transistor disposed on the substrate, a color filter and a light blocking member disposed on the thin film transistor, an insulating layer which is disposed on the color filter and the light blocking member and includes an exposed region through which the light blocking member is exposed, a pixel electrode which is disposed on the insulating layer and is connected to the thin film transistor through a contact hole, a common electrode which is spaced apart from the pixel electrode with a microcavity therebetween, a roof layer disposed on the common electrode, a liquid crystal layer which is filled in the microcavity, and an overcoat which is disposed on the roof layer and configured to seal the microcavity. |
| US09570471B2 |
Organic light emitting display device and method of manufacturing the same
Provided is an organic light emitting display device including: a substrate; a first anode and a second anode formed on the substrate; a first auxiliary electrode formed between the first anode and the second anode; a first organic light emitting layer and a second organic light emitting layer; a first bank including an undercut formed on an upper part of a first edge of the first auxiliary electrode; a second bank including an undercut formed on an upper part of a second edge of the first auxiliary electrode; a second auxiliary electrode disposed between the undercut of the first bank and the first auxiliary electrode; a third auxiliary electrode disposed between the undercut of the second bank and the first auxiliary electrode; a first cathode electrically connected with the second auxiliary electrode; and a second cathode electrically connected with the third auxiliary electrode. |
| US09570468B2 |
Semiconductor device with three or four-terminal-FinFET
Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate. |
| US09570466B2 |
Structure and method to form passive devices in ETSOI process flow
Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon. |
| US09570459B2 |
Vertical gate NAND memory devices
In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line. |
| US09570456B1 |
Semiconductor integrated device including capacitor and memory cell and method of forming the same
A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation. |
| US09570455B2 |
Metal word lines for three dimensional memory devices
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions. |
| US09570443B1 |
Field effect transistor including strained germanium fins
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium. |
| US09570441B2 |
Semiconductor device with thermally grown oxide layer between field and gate electrode and method of manufacturing
A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material. |
| US09570437B2 |
Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit. |
| US09570436B2 |
Semiconductor device
The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur. |
| US09570433B2 |
Semiconductor device and method for manufacturing a semiconductor device
A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner. |
| US09570429B2 |
Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies. |
| US09570426B2 |
Semiconductor light-emitting device having matrix-arranged light-emitting elements and transparent plates
A semiconductor light-emitting device includes a support body multiple, multiple light-emitting elements arranged in a matrix on the support body, a transparent resin layer provided on the light-emitting elements, multiple transparent plates provided on the transparent resin layer, each of the transparent plates being provided over one of the multiple light-emitting elements, and multiple optical shield layers each provided at one of a first side face of a first one of the transparent plates and a second the face of a second one of the transparent plates opposing the first the face of the first transparent plate. |
| US09570422B2 |
Semiconductor TSV device package for circuit board connection
An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. |
| US09570421B2 |
Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures. |
| US09570418B2 |
Structure and method for package warpage control using dummy interconnects
Presented herein is a package comprising a molding compound layer and an active device in the molding compound layer. A conductive via passes through the molding compound layer and is adjacent to the active device. A passivation layer is disposed on the molding compound layer. An active PPI is disposed on the passivation layer and is electrically connected to the conductive via. A dummy PPI is disposed on the passivation layer and is electrically isolated from the conductive via and the active device. |
| US09570415B2 |
Chip packaging method and chip package using hydrophobic surface
A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other. |
| US09570412B2 |
Semiconductor device
A semiconductor device includes a first metal wiring formed on a semiconductor substrate, a first organic insulating film formed on the first metal wiring, and a second metal wiring formed to cover the first organic insulating film and having a via connected to the first metal wiring. The semiconductor device further includes a second organic insulating film formed on the first organic insulating film and having an opening to expose the second metal wiring, a bump formed on an exposed portion of the second metal wiring in the opening, and a tunnel portion formed in contact with the second metal wiring or the first organic insulating film. The tunnel portion overlaps with the second metal wiring in planar view. |
| US09570411B2 |
Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure
A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection. |
| US09570409B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs. |
| US09570408B2 |
Resin-sealed semiconductor device and method of manufacturing resin-sealed semiconductor device
A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100, wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device. |
| US09570405B2 |
Semiconductor device and method for manufacturing same
One semiconductor device includes a wiring substrate, a semiconductor chip layered on one face of the wiring substrate and having a first face facing the wiring substrate and a second face positioned on a reverse side from the first face, a circuit being formed on at least the second face, a non-circuit-incorporating chip in which a circuit is not formed, the non-circuit-incorporating chip being layered on the second face of the semiconductor chip, and a sealing resin disposed between at least the wiring substrate and the non-circuit-incorporating chip. |
| US09570403B2 |
Secure chip with physically unclonable function
A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device. |
| US09570402B2 |
Alignment key of semiconductor device and method of fabricating the same
An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer. |
| US09570401B2 |
Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads. |
| US09570400B2 |
Semiconductor package
Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient. |
| US09570398B2 |
Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening. |
| US09570391B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance. |
| US09570389B1 |
Interconnect structure
An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner layers. Each interconnect line is positioned within a trench. At least one first liner layer is affixed between the trench bottom surface and the interconnect bottom surface. The interconnect structure further includes one or more second liner layers. At least one of the second liner layers is affixed directly to the interconnect top surface and at least one interconnect side surface. The interconnect structure further includes at least one air gap. Each air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product of a method of manufacture are also disclosed. |
| US09570387B1 |
Three-dimensional integrated circuit systems in a package and methods therefor
A method for making a packaged semiconductor device includes dispensing a first adhesive into a first cavity of a substrate having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. The method further includes placing a first component having a thickness less than a thickness of the substrate into the first cavity such that the first adhesive physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate. |
| US09570386B2 |
Flexible package-to-socket interposer
A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate. |
| US09570382B2 |
Stackable molded microelectronic packages
A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts. |
| US09570381B2 |
Semiconductor packages and related manufacturing methods
Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion. |
| US09570375B2 |
Semiconductor device having silicon interposer on which semiconductor chip is mounted
Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips. |
| US09570374B2 |
Systems and methods for coupling a semiconductor device of an automation device to a heat sink
A system includes a heat sink, a semiconductor device, and a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink. The system also includes a fastener system that couples the semiconductor device to the heat sink about the layer of TIM. The system also includes one or more washers of the fastener system that maintain a coupling force between the semiconductor device and the heat sink after the TIM flows. |
| US09570373B1 |
Near-chip compliant layer for reducing perimeter stress during assembly process
A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material. |
| US09570368B2 |
Method of manufacturing semiconductor package including forming a recessed region in a substrate
A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region. |
| US09570366B2 |
Passivation layer for packaged chip
A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm. |
| US09570355B1 |
Methods for contact formation for 10 nanometers and beyond with minimal mask counts
A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings. |
| US09570348B2 |
Method of forming contact strucutre
A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening. |
| US09570347B2 |
Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. |
| US09570345B1 |
Cobalt resistance recovery by hydrogen anneal
Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer. |
| US09570341B2 |
Semiconductor device having air gap structures and method of fabricating thereof
One method includes forming a conductive feature in a dielectric layer on a substrate for a semiconductor device. A hard mask layer and an underlying etch stop layer are formed on the substrate. The hard mask layer and the underlying etch stop layer are then patterned. The patterned etch stop layer is disposed over the conductive feature. At least one of the patterned hard mask layer and the patterned etch stop layer are used as a masking element during etching of a trench in the dielectric layer adjacent the conductive feature. A cap is then formed over the etched trench. The cap is disposed on the patterned etch stop layer disposed on the conductive feature. |
| US09570337B2 |
Film formation apparatus and film formation method
At the time of transporting a substrate into or from a space where a film formation process is performed, the space where the film formation process is performed, a space where a lower heater 16 is provided, and a space where an upper heater 19 is provided are made in an inert gas atmosphere. |
| US09570336B2 |
Substrate transfer system and substrate processing system
A substrate transfer system includes a substrate transfer robot. The substrate transfer robot is provided between a first apparatus and a second apparatus which has a wall provided opposite to the substrate transfer robot and having an opening on the wall. The substrate transfer robot is configured to transfer a substrate from the first apparatus to the second apparatus via the opening and includes a base having a first axis, an arm body, and a hand. The arm body has a proximal end and a distal end and is connected to the base at the proximal end to rotate around the first axis. The substrate transfer robot includes a minimum distance from the first axis to an outermost portion of the arm body and the hand in a radius direction from the first axis being larger than a distance between the first axis and the opening on the wall. |
| US09570335B2 |
Dicing film
According to the invention, a dicing film, which generates a small amount of scrapes and beard-like burrs during dicing and furthermore has desirable strength and external appearance, is provided. The dicing film according to the invention has an adhesive layer on at least one surface of a base film, wherein the base film contains a copolymer (A) of at least two kinds of alkyl(meth)acrylates and styrene; and a styrene-based elastomer (B). The copolymer (A) of at least two kinds of alkyl(meth)acrylates and styrene is a styrene-alkyl methacrylate-alkyl acrylate copolymer. |
| US09570329B2 |
Peeling apparatus and manufacturing apparatus of semiconductor device
To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid. |
| US09570327B2 |
Substrate liquid treatment apparatus and substrate liquid treatment method
A substrate liquid treatment apparatus comprises a chuck (13) that holds and rotates a wafer, a back surface purging nozzle (15) that discharges a purge gas toward the back surface of the wafer, and a periphery purging nozzle 16 that discharges the purge gas onto the back surface of the wafer. The back surface purging nozzle has a slit-like opening part extending from a central side to a peripheral side of the substrate in a plan view. Vertical distance between the slit-like opening part and the substrate held by the substrate holding unit increases as approaching an end of the opening part on the central side of the substrate. The periphery purging nozzle discharges the purge gas, toward a central part of the substrate, toward a region on the back surface of the substrate, which region is located radially outside an end of the slit-like opening part of the back surface purging nozzle and radially inside an peripheral edge of the substrate. |
| US09570325B2 |
Packaged semiconductor devices having ribbon wires
A packaged semiconductor device, such as a power QFN device, has (rectangular) ribbon wires, instead of circular bond wires. A proximal end of each ribbon wire is connected to a pad on an IC die, and a distal end of each ribbon wire forms a device lead. The die and the ribbon wires are encapsulated in a molding compound with a side of each device lead exposed. Such devices can be assembled without using lead frames. The omission of lead frames and the use of ribbon wires enable assembly of smaller devices having enhanced thermal dissipation capabilities. |
| US09570317B2 |
Microelectronic method for etching a layer
A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film. |
| US09570316B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures. |
| US09570314B2 |
Methods for singulating semiconductor wafer
Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies. |
| US09570311B2 |
Modular grinding apparatuses and methods for wafer thinning
Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer. |
| US09570308B2 |
Method of forming regions with hot and cold implants
A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region. |
| US09570306B2 |
Surface treatment method for single crystal SiC substrate, and single crystal SiC substrate
The present application aims to provide a surface treatment method that is able to accurately control the rate of etching a single crystal SiC substrate and thereby enables correct understanding of the amount of etching. In the surface treatment method, the single crystal SiC substrate is etched by a heat treatment performed under Si vapor pressure. At a time of the etching, inert gas pressure in an atmosphere around the single crystal SiC substrate is adjusted to control the rate of etching. Accordingly, correct understanding of the amount of etching is obtained. |
| US09570305B2 |
Self-aligned double patterning
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material. |
| US09570304B2 |
Method of forming fine patterns in an anti-reflection layer for use as a patterning hard mask
Provided is a method of fabricating a semiconductor device. The method includes forming an anti-reflection layer on a lower layer, forming photoresist patterns on the anti-reflection layer, forming protection patterns to cover the photoresist patterns, respectively, etching the anti-reflection layer using the photoresist patterns covered with the protection patterns as an etch mask to form anti-reflection patterns, forming spacers to cover sidewalls of the anti-reflection patterns, and removing the anti-reflection patterns. |
| US09570302B1 |
Method of patterning a material layer
A method of fabricating a semiconductor device is disclosed. The method includes forming a radiation-removable-material (RRM) layer over a substrate and removing a first portion of the RRM layer in a first region of the substrate by exposing the first portion of the RRM layer to a radiation beam. A second portion of the RRM layer in a second region of the substrate remains after the removing of the first portion of the RRM layer in the first region. The method also includes forming a selective-forming-layer (SFL) over the second portion of the RRM layer in the second region of the substrate and forming a material layer over the first region of the substrate. |
| US09570297B1 |
Elimination of defects in long aspect ratio trapping trench structures
A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench. |
| US09570295B1 |
Protective capping layer for spalled gallium nitride
Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing. |
| US09570293B2 |
Method for making epitaxial base
A method for making an epitaxial base includes the following steps. A plurality of grooves and a plurality of bulges are formed on an epitaxial growth surface of a substrate by etching the epitaxial growth surface. A carbon nanotube layer is located on the epitaxial growth surface, wherein the carbon nanotube layer defines a first part attached on top surface of bulges, and a second part suspended on the grooves. The second part of the carbon nanotube layer is attached on bottom surface of the grooves by treating the carbon nanotube layer. |
| US09570291B2 |
Semiconductor substrates and methods for processing semiconductor substrates
Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate. |
| US09570289B2 |
Method and apparatus to minimize seam effect during TEOS oxide film deposition
A method of minimizing a seam effect of a deposited TEOS oxide film during a trench filling process performed on a semiconductor substrate in a semiconductor substrate plasma processing apparatus comprises supporting a semiconductor substrate on a pedestal in a vacuum chamber thereof. Process gas including TEOS, an oxidant, and argon is flowed through a face plate of a showerhead assembly into a processing region of the vacuum chamber. RF energy energizes the process gas into a plasma wherein TEOS oxide film is deposited on the semiconductor substrate so as to fill at least one trench thereof. The argon is supplied in an amount sufficient to increase the electron density of the plasma such that the deposition rate of the TEOS oxide film towards the center of the semiconductor substrate is increased and the seam effect of the deposited TEOS oxide film in the at least one trench is reduced. |
| US09570287B2 |
Flowable film curing penetration depth improvement and stress tuning
Methods for depositing and curing a flowable dielectric layer are disclosed herein. Methods can include forming a flowable dielectric layer, immersing the flowable dielectric layer in an oxygen-containing gas, purging the chamber and curing the layer with UV radiation. By curing the layer after an oxygen-containing gas pre-soak, the layer can be more completely cured during the UV irradiation. |
| US09570283B2 |
Electrostatic trap
An electrostatic trap such as an orbitrap is disclosed, with an electrode structure. An electrostatic trapping field of the form U′(r, φ, z) is generated to trap ions within the trap so that they undergo isochronous oscillations. The trapping field U′(r, φ, z) is the result of a perturbation W to an ideal field U(r, φ, z) which, for example, is hyperlogarithmic in the case of an orbitrap. The perturbation W may be introduced in various ways, such as by distorting the geometry of the trap so that it no longer follows an equipotential of the ideal field U(r, φ, z), or by adding a distortion field (either electric or magnetic). The magnitude of the perturbation is such that at least some of the trapped ions have an absolute phase spread of more than zero but less than 2 π radians over an ion detection period Tm. |
| US09570275B2 |
Heated showerhead assembly
The present disclosure generally comprises a heated showerhead assembly that may be used to supply processing gases into a processing chamber. The processing chamber may be an etching chamber. When processing gas is evacuated from the processing chamber, the uniform processing of the substrate may be difficult. As the processing gas is pulled away from the substrate and towards the vacuum pump, the plasma, in the case of etching, may not be uniform across the substrate. Uneven plasma may lead to uneven etching. To prevent uneven etching, the showerhead assembly may be separated into two zones each having independently controllable gas introduction and temperature control. The first zone corresponds to the perimeter of the substrate while the second zone corresponds to the center of the substrate. By independently controlling the temperature and the gas flow through the showerhead zones, etching uniformity of the substrate may be increased. |
| US09570274B2 |
Plasma activated conformal dielectric film deposition
Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction. |
| US09570270B2 |
Method of using an environmental transmission electron microscope
An environmental transmission electron microscope (ETEM) suffers from gas-induced resolution deterioration. Inventors conclude that the deterioration is due to ionization of gas in the sample chamber of the ETEM, and propose to use an electric field in the sample chamber to remove the ionized gas, thereby diminishing the gas-induced resolution deterioration. The electric field need not be a strong field, and can be caused by, for example, biasing the sample with respect to the sample chamber. A bias voltage of 100 V applied via voltage source is sufficient for a marked improvement the gas-induced resolution deterioration. Alternatively an electric field perpendicular to the optical axis can be used, for example by placing an electrically biased wire or gauze off-axis in the sample chamber. |
| US09570269B2 |
Method for manufacturing a TEM-lamella and assembly having a TEM-lamella protective structure
A method for manufacturing a TEM-lamella is disclosed. The method includes: disposing a self-supporting protective structure on a surface of a substrate; bonding the protective structure to the substrate; cutting out a lamella from the substrate using a particle beam so that the lamella remains bonded to at least a portion of the protective structure; fastening a first tool to the lamella; and moving away the lamella from a residual portion of the substrate by moving the first tool relative to the substrate. |
| US09570267B2 |
Multi charged particle beam writing method and multi charged particle beam writing apparatus
A multi charged particle beam writing method includes performing ON/OFF switching of a beam by an individual blanking system for the beam concerned, for each beam in multi-beams of charged particle beam, with respect to each time irradiation of irradiation of a plurality of times, by using a plurality of individual blanking systems that respectively perform beam ON/OFF control of a corresponding beam in the multi-beams, and performing blanking control, in addition to the performing ON/OFF switching of the beam for the each beam by the individual blanking system, with respect to the each time irradiation of the irradiation of the plurality of times, so that the beam is in an ON state during an irradiation time corresponding to irradiation concerned, by using a common blanking system that collectively performs beam ON/OFF control for a whole of the multi-beams. |
| US09570266B2 |
X-ray generating apparatus
An x-ray generating apparatus comprises: a vacuum container having a main body, and a moving member coupled movably and airtightly to the main body via a vacuum bellows; and a guide mechanism, provided on an outer side of the vacuum container, for regulating the movement and inclination of the moving member in an approaching/separation direction with respect to an electron gun. The guide mechanism includes a guide portion where a guide flat surface along a plane orthogonal to a central axis of the electron beam is formed, the guide portion being provided on the main body side, a guided portion where a guided flat surface facing the guide flat surface is formed, the guided portion being provided on the moving member side, and at least three rolling elements placed between the guide flat surface and the guided flat surface. |
| US09570265B1 |
X-ray fluorescence system with high flux and high flux density
We present a micro-x-ray fluorescence (XRF) system having a high-brightness x-ray illumination system with high x-ray flux and high flux density. The higher brightness is achieved in part by using x-ray target designs that comprise a number of microstructures of x-ray generating materials fabricated in close thermal contact with a substrate having high thermal conductivity. This allows for bombardment of the targets with higher electron density or higher energy electrons, which leads to greater x-ray flux. The high brightness/high flux x-ray source may then be coupled to an x-ray optical system, which can collect and focus the high flux x-rays to spots that can be as small as one micron, leading to high flux density at the fluorescent sample. Such systems may be useful for a variety of applications, including mineralogy, trace element detection, structure and composition analysis, metrology, as well as forensic science and diagnostic systems. |
| US09570260B2 |
Thermal metal oxide varistor circuit protection device
A circuit protection device including a housing, a metal oxide varistor disposed within said housing, a terminal having a contact lead at a first end electrically attached to said metal oxide varistor by solder and having a second end extending outside of said housing, an arc shield disposed within said housing between said contact lead and said metal oxide varistor, a micro switch housed in a pocket portion of the housing, said micro switch having a trigger portion and an indicator portion disposed at least partially outside of said housing, said arc shield positioned against said trigger portion, and a spring configured to bias said arc shield away from said pocket portion and to move said arc shield away from said trigger portion when said solder is melted to provide a barrier between said metal oxide varistor and said contact lead, whereby the indicator portion is retracted into the housing. |
| US09570259B2 |
Electromagnetic relay
An electromagnetic relay includes: a pair of fixed contact terminals, each of which has a fixed contact; a movable contact spring having a pair of movable pieces and a coupler coupling the pair of movable pieces, each of the movable pieces having a movable contact that contacts and is separated from the fixed contact; an armature having a flat plate to be adsorbed to an iron core and a hanging portion bent from the flat plate and extending downward, and moves the movable contact spring by a rotation operation; and an electromagnetic device driving the armature, wherein the hanging portion has a projection to fix the movable contact spring on a face thereof facing the electromagnetic device and a pulling portion that extends downward more than the projection and pulls the movable contact spring when a current flows between the fixed contact and the movable contact. |
| US09570250B2 |
Gas insulated switching device and camera system for optical check of switching position in the switching device
A gas insulated switching device with a gastight housing, with switching elements mounted in the housing, having an optical window on which an external camera can be positioned outside the housing on a support element in such, that the contacts and/or the contact positions of one or more switches can be displayed by this camera on a display screen, and with a switchable light source, which illuminates the area the camera is focused on to display the contact positions of one or more switches, as well as a camera system having the switching device. For easier and more cost effective use of a camera system, considering that direct optical control of specific switch positions are often not desired, the camera may be portable and/or positionable only temporarily, and the support element and the camera itself are provided with complementary elements for temporarily positioning the portable camera to the support. |
| US09570244B2 |
Solid-state supercapacitor
Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode. |
| US09570238B2 |
Ultra-wideband assembly system and method
An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board. |
| US09570229B2 |
Power feeding coil unit and wireless power transmission device
A power feeding coil unit includes a power feeding coil, and first and second auxiliary coils located outside of the region defined by a wire of the power feeding coil. The axis of the first auxiliary coil and the axis of the second auxiliary coil are substantially perpendicular to the axis of the power feeding coil. The power feeding coil and the first and second auxiliary coils simultaneously generate respective magnetic fluxes, each of which interlinks the corresponding one of the power feeding coil and the first and second auxiliary coils in a direction from the center to the outside of the power feeding coil unit. |
| US09570228B1 |
Transfomer structure
A transformer structure includes a winding cylinder which is a hollow tube, at least one limiting ring which is a ring sheet, multiple conductive sheets and at least one winding. The limiting ring is able to slide along the winding cylinder and to sleeve on the outside of the winding cylinder. The conductive sheets are sleeved on the outside of the winding cylinder. Two conductive sheets of the conductive sheets are attached to two end surfaces of the limiting ring while the two conductive sheets and the limiting ring form a winding space. The at least one winding is correspondingly disposed in the winding space. Thereby, the assembly of the transformer is simplified, and the winding area, as well as the voltage ratio of the transformer, is increased. |
| US09570225B2 |
Magnetoelectric device capable of storing usable electrical energy
A magnetoelectric device includes at least one reluctance component, at least one damping capacitor, and a switching circuit. The reluctance component includes a capacitive and inductive magnetic core unit having a loop-shaped first segment and a second segment connected to the first segment, and at least one coil wound around and loosely coupled to the magnetic core unit. The damping capacitor cooperates with the coil to form a resonant circuit. The switching circuit makes and breaks electrical connection between the coil and a DC power source so that an eddy current flowing through the resonant circuit may be generated for storing energy in the damping capacitor. |
| US09570224B2 |
Pressure compensation system
A pressure compensation system is provided. A subsea enclosure of the subsea device encloses the chamber. A first pressure compensator has a first compensation volume and provides pressure balancing between ambient medium surrounding the subsea device and the first compensation volume. A first biasing device is configured to bias the first pressure compensator such that the pressure in the first compensation volume is higher than the pressure in the ambient medium surrounding the subsea device. A second pressure compensator has a second compensation volume and provides pressure balancing between the ambient medium and the second compensation volume. A second biasing device biases the second pressure compensator such that the pressure in the second compensation volume is higher than the pressure in the ambient medium. A control unit is connected to control first and second valves arranged in flow connections between the first and second compensation volumes and the chamber. |
| US09570221B2 |
Permanent magnetic chucking device with large force differential
An apparatus usable as a chucking device to temporarily couple two mechanical objects together. In one embodiment, the apparatus includes an arbor configured to receive an at least partially ferromagnetic object; and a magnet assembly. The magnet assembly includes multiple permanent magnets mounted in a soft ferromagnetic enclosure. The magnet assembly is rotatably coupled to the arbor such that the magnet assembly and the arbor are positionable relative to one another in locking and unlocking positions upon relative rotation therebetween. The magnet assembly is configured to exert a pulling force on the object in the locking position and a lesser force in the unlocking position. |
| US09570219B2 |
Non-oriented electrical steel sheet and method of manufacturing non-oriented electrical steel sheet
This oriented electrical steel sheet is a non-oriented electrical steel sheet consisting of, in mass %: C: not less than 0.0001% and not more than 0.0040%, Si: more than 3.0% and not more than 3.7%, sol.Al: not less than 0.3% and not more than 1.0%, Mn: not less than 0.5% and not more than 1.5%, Sn: not less than 0.005% and not more than 0.1%, Ti: not less than 0.0001% and not more than 0.0030%, S: not less than 0.0001% and not more than 0.0020%, N: not less than 0.0001% and not more than 0.003%, Ni: not less than 0.001% and not more than 0.2%, P: not less than 0.005% and not more than 0.05%, with a balance consisting of Fe and impurities, in which a resistivity ρ at room temperature ≧60 μΩcm, and saturation magnetic flux density Bs at room temperature ≧1.945 T are established, and the components contained satisfy 3.5≦Si+(⅔)×sol.Al+(⅕)×Mn≦4.25. |
| US09570218B2 |
Paste for NFC magnetic sheet, method of preparing the same, and NFC magnetic sheet
A paste for an NFC magnetic sheet is provided, which comprises: a magnetic powder; an organic carrier; and a nanoscale alumina powder; wherein a weight ratio of the nanoscale alumina powder to the magnetic powder ranges from about 0.0005 to about 0.005. A method of preparing the paste for the NFC magnetic sheet and an NFC magnetic sheet are also provided. |
| US09570217B2 |
Process for preparing a magnetic talcous composition, and magnetic talcous composition
A process for preparing a magnetic talcous composition including mineral particles, referred to as magnetic talcous particles, having a non-zero magnetic susceptibility, in which, during an oxidative contacting step, talcous particles chosen from the group formed from 2:1 lamellar silicates having a zero electric charge are brought into contact with particles including at least one magnetic iron oxide chosen from the group formed from magnetite and maghemite, the magnetic particles having a mean equivalent diameter of between 1 nm and 50 nm. A magnetic talcous composition including mineral particles, referred to as magnetic talcous particles, having a non-zero magnetic susceptibility, at least 20% by weight of talcous particles and at least 0.5% by weight of magnetic particles is also described. |
| US09570215B2 |
Method for manufacturing precursor, method for manufacturing superconducting wire, precursor, and superconducting wire
A method for manufacturing a superconducting wire includes the following steps. A laminate metal having a first metal layer and a Ni layer formed on the first metal layer is prepared. An intermediate layer (20) is formed on the Ni layer of the laminate metal. A superconducting layer (30) is formed on the intermediate layer (20). By subjecting the laminate metal to a heat treatment after at least either of the step of forming a intermediate layer (20) and the step of forming a superconducting layer (30), a nonmagnetic Ni alloy layer (12) is formed from the laminate metal. |
| US09570214B2 |
Superconducting cable line
In a superconducting cable line in which a superconducting cable is connected to a terminal connecting part or an intermediate connecting part, an offset part in which a superconducting cable is laid in a curved-shape is provided near the terminal connecting part or the intermediate connecting part. Further, when it is assumed that the superconducting cable is movable in the offset part, an external tube of the superconducting cable is fixed such that a maximum amplitude part which maximizes the amount of movement of the superconducting cable following thermal expansion and contraction of a cable core becomes immovable. |
| US09570212B2 |
Wire harness and method for manufacturing wire harness
An object is to make it possible to hot-press a nonwoven member that covers a branching portion of a wire harness main body even when there is an error in the position of the branching portion. A wire harness includes a wire harness main body and a branching portion protection portion. The wire harness main body includes a trunk line portion and a branch line portion branching off from the trunk line portion. The branching portion protection portion is formed by hot-pressing a nonwoven member in a state in which the nonwoven member covers the branching portion where the branch line portion branches off from the trunk line portion. The branching portion protection portion includes a branch line side protection portion that is tapered from a base end side toward a distal end side of the branch line portion. |
| US09570211B2 |
Transparent thermoplastic composition with improved electrical conductivity in the melt
The present invention provides a transparent thermoplastic molding composition made from a transparent blend of a polycarbonate resin with a polyester resin, 0.005 to 2 weight percent, based on the weight of the composition, of a perfluoroalkylsulfonic acid salt of the formula (I): (RA—SO3−)nXn+ (I), wherein R denotes perfluorinated linear or branched carbon chain having 1 to 30 carbon atoms, A denotes a direct bond or an aromatic nucleus, n denotes an integer of 1 or 2, and X denotes a metal element selected from the first or the second column in the Periodic Table of the Elements, and 0 to 5 weight percent, based on the weight of the composition, of a glycerol monostearate. The inventive composition has a total transmittance according to ASTM D-1003 of greater than 84% and an electric resistivity according to ASTM D-257 of less than about 2.5E+06 ohm-m. |
| US09570210B2 |
Transparent conductive film and production method therefor
The transparent conductive film of the invention includes a transparent conductive coating provided on at least one surface of an organic polymer film substrate, wherein the transparent conductive coating is a crystalline coating of an indium-based complex oxide having a tetravalent metal oxide content of 7 to 15% by weight as calculated by the formula {(the amount of the tetravalent metal element oxide)/(the amount of the tetravalent metal element oxide+the amount of indium oxide)}×100 (%), has a thickness of 10 to 40 nm and a specific resistance of 1.3×10−4 to 2.8×10−4 Ω·cm, has main X-ray diffraction peaks corresponding to (222) and (440) planes, and has a ratio (I440/I222) of (440) peak intensity to (222) peak intensity of less than 0.2. The transparent conductive film of the invention has a crystalline thin coating with a low level of specific resistance and surface resistance. |
| US09570208B2 |
Carbon nanotube composite wire
A carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire includes a plurality of carbon nanotubes spirally arranged along an axial direction of the carbon nanotube wire. The diameter of the carbon nanotube wire ranges from about 1 micrometer to about 30 micrometers. The twist of the carbon nanotube wire ranges from about 250 t/cm to about 300 t/cm. The metal layer is coated on a surface of the carbon nanotube wire. The thickness of the metal layer ranges from about 1 micrometer to about 5 micrometers. |
| US09570205B2 |
Radiation monitoring device
A radiation monitoring device comprises a radiation monitor and a test unit for testing the radiation monitor. The radiation monitor includes a radiation detector and a measurement unit. The test unit includes a test pulse generator and a test pulse controller. The measurement unit includes a counter circuit, a computing part that computes a count rate with the standard deviation kept constant, an input switching circuit. When a test mode is selected in the radiation monitor, the test pulse controller changes the repetition frequency of test pulses in a step-function manner to the same repetition frequency of a start count rate specified as reference, replaces a count rate in the computing part at current computing cycle with the start count rate, switches the input switching circuit to the test pulse input at next computing cycle to start the test, and then finishes the test after a predetermined time elapses. |
| US09570204B2 |
Completely passive cooling system for reactor core after accident of large-scale pressurized water reactor nuclear power plant
A passive cooling system for a reactor core of a large-scale pressurized water reactor nuclear power plant includes a shield building having an outer wall and a through air inlet arranged on an upper part of the outer wall, a water tank arranged at an upper part of the shield building, a cooling water distribution plate arranged above a top of a containment within the shield building, a spray pipe arranged at an inside of the top of the shield building and having a water inlet end and a water outlet end, wherein the water inlet end is connected to a bottom of the water tank and the water outlet end is extended to be above the cooling water distribution plate, and an air deflector arranged between the shield building and the containment and having an upper end connected to an inside of the top of the shield building. |
| US09570202B2 |
Methods of fine forming sapphire tubes and joining sapphire components for nuclear reactor fuel elements and assemblies
A method of fine surface finishing a cladding tube for a nuclear fuel element comprising a cladding tube containing fuel pellets, comprises heating the tube to thermal creep temperatures (e.g., 1750-2000 degrees Celsius) for sapphire and forming inner and outer surfaces of the tube to reduce ridge heights while limiting changes in the crystalline structure of the bulk of the tube. Alternatively, the tube may be placed in a mould and heating the tube-mould assembly to the range of the creep temperature of the sapphire at which differential thermal expansion of the mould and tube cause pressure at an interface between the sapphire and the mould. Maintaining the assembly at an upper end of the creep temperature range allows creep to progress and relieve stresses resulting from the pressure; and cooling the assembly to allow the sapphire tube to part from the mould and be withdrawn. |
| US09570201B2 |
Repair of memory devices using volatile and non-volatile memory
Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory. |
| US09570199B2 |
Traffic and temperature based memory testing
The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range. |
| US09570197B2 |
Information processing device, computer-readable recording medium, and method
An information processing device includes a plurality of memories, and a processor coupled to the plurality of memories and configured to carry out a first test to determine whether a first error is detected when first and second memories of the plurality of memories are concurrently operated, and when the first error is detected from the first test, carry out a second test to determine whether a second error is detected when the first and second memories are separately operated. |
| US09570189B1 |
Data storage device and operating method thereof
A data storage device includes a nonvolatile memory device including a target memory cell and one or more adjustment memory cells sharing bit lines with the target memory cell, one or more of the adjustment memory cell are adjacent memory cells adjacent to the target memory cells, and suitable for reading out data therefrom or storing data therein; and a controller suitable for adjusting threshold voltages of the adjustment memory cells based on threshold voltages it of the target memory cell and the adjacent memory cells. |
| US09570185B2 |
Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. |
| US09570183B1 |
Method and controller for managing memory device
A method for managing a memory device includes: sending a last writing command to a specific non-volatile (NV) memory element in the memory device to write a set of data to a specific block of the specific NV memory element, rather than sending either a first writing command or a second writing command to the specific NV memory element, where these writing commands are utilized for writing to the same location at different times, respectively, in order to guarantee data correctness; and after writing the set of data to the specific block, sending a read command to the specific NV memory element to read stored data of the set of data from the specific block, and checking whether the stored data match the set of data to determine whether the specific block is a bad block. |
| US09570180B2 |
Semiconductor memory device
A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period. |
| US09570179B2 |
Non-volatile memory with two phased programming
Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming. |
| US09570174B2 |
Coding method and decoding method in memory system
Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern. |
| US09570173B2 |
Semiconductor storage device and memory system
A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense amplifier electrically connected to the bit line. The sense amplifier has a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node, a second transistor electrically connected between the second node and a sense node, and a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted. |
| US09570171B2 |
Resistance change memory cell circuits and methods
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor. |
| US09570155B2 |
Circuit to improve SRAM stability
Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential. |
| US09570152B1 |
High reliability non-volatile static random access memory devices, methods and systems
A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to the second data node during the first read mode. |
| US09570151B1 |
Semiconductor device and semiconductor system
A semiconductor device may include a data output circuit configured to sense and amplify data of an input/output line and a complementary input/output line based on the sense amplification control signal. The semiconductor device may include a data output control circuit configured to delay a point of time that the input/output line and the complementary input/output line are sensed and amplified. |
| US09570141B2 |
Memory device having a transistor including a semiconductor oxide
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor. |
| US09570140B2 |
Circuit for mixed memory storage and polymorphic logic computing
A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes. |
| US09570139B2 |
Magnetic state element and circuits
Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices. |
| US09570138B2 |
Magnetic memory cells with fast read/write speed
Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector. |
| US09570137B2 |
Magnetic memory and semiconductor-integrated-circuit
A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state. |
| US09570133B2 |
Local word line driver
A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. |
| US09570132B2 |
Address-remapped memory chip, memory module and memory system including the same
A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit. |
| US09570131B2 |
Method and apparatus for timing adjustment
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section. |
| US09570129B2 |
On-die termination of address and command signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device. |
| US09570127B1 |
Semiconductor memory device with cut-off voltage and operating method thereof
A semiconductor memory device and an operating method of the semiconductor memory device may be provided. The semiconductor memory device may include a plurality of memory strings each having a plurality of memory cells coupled in series between a bit line and a source line. The semiconductor memory device may include a peripheral circuit configured to apply a program voltage, a pass voltage, and a cut-off voltage to the plurality of memory strings and perform a program operation. The semiconductor memory device may include control logic configured to control the peripheral circuit so that the cut-off voltage is applied to memory cells adjacent to a selected memory cell among the plurality of memory cells, wherein the peripheral circuit is controlled such that the cut-off voltage increases. |
| US09570126B2 |
Memory with deferred fractional row activation
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. |
| US09570125B1 |
Apparatuses and methods for shifting data during a masked write to a buffer
Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality of data words is received by the multiplexer and identified as unmasked based on a data mask. The multiplexer is also configured to determine whether each sum of the plurality of sums indicates that a corresponding data word of the plurality of data words is masked. The multiplexer is further configured to shift the plurality of data words to remove the corresponding masked data word from the plurality of data words. The multiplexer is also configured to output only the data words identified as unmasked based on the data mask. |
| US09570124B2 |
High speed logging system
A method of storing log entries of events from a plurality of network elements in a communication network, comprising the steps of: a) receiving log entries at a control processor of events from a plurality of different elements positioned, the log entries grouped into threads based on a common purpose; b) converting each log entry into a compact log record in a logging module, and c) storing the compact log records in a first memory buffer in random access memory (RAM) forming a first log file. |
| US09570121B1 |
Semiconductor devices and semiconductor systems including the same
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals, data and a test mode signal. The first semiconductor device receives output data from the second semiconductor device. The second semiconductor device buffers the data inputted through a first pad to write the buffered data according to a combination of the command/address signals or inversely buffers the data to write the inversely buffered data if a control signal enabled in response to the test mode signal inputted through a second pad is inputted through a third pad. |
| US09570115B2 |
Memory device, related method, and related electronic device
A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor. |
| US09570114B1 |
Laminated film-packed hard disk drive for hermetic sealing
A hermetically-sealed hard disk drive (HDD) utilizes a laminated film enclosure to hermetically seal an HDD within. The laminated film enclosure may be constructed of a heat sealant layer hermetically-sealed around the HDD, a barrier layer which inhibits gas from escaping from inside the laminated film enclosure, and a film surface protective layer which protects the heat sealant and barrier layers. Embodiments may include a heat sealant layer comprising a thermoplastic polymer such as polypropylene, a barrier layer comprising a metal such as aluminum, and a film surface protective layer comprising a thermoplastic polymer such as polyethylene terephthalate. |
| US09570111B2 |
Clustering crowdsourced videos by line-of-sight
A method for clustering images includes acquiring initial image data including a scene of interest. A 3D model is constructed of the scene of interest based on the acquired initial image data. Additional image data including the scene of interest is acquired. The additional image data is fitted to the 3D model. A line-of-sight of the additional image data is estimated based on the fitting to the 3D model. The additional image data is clustered according to the estimated line-of-sight. |
| US09570108B2 |
Mapping pixels to underlying assets in computer graphics
A system for presenting video and methods for manipulating and delivering the video are presented. An interface may be implemented to access data related to the creation and animation of the video, a reference to the creation data stored with the video itself. Upon selection a portion of the video, using the references stored with the video, the tools needed to edit the selected portion of the video may be presented. The objects and illustration assets utilized to animate a scene may be stored in a memory device such that the objects and assets may be retrieved using a hierarchy of references initially accessed via the reference stored with the selected portion of the video. According to an embodiment, the selected portion may be a frame or a pixel and the reference stored with the frame metadata, pixel value, or image channel or image layer. |
| US09570106B2 |
Sensor configuration switching for adaptation of video capturing frame rate
On the basis of a first configuration of one or more imaging sensors, first video data is captured at a first frame rate and a first resolution and second video data is captured at a second frame rate and a second resolution. The second frame rate is higher than the first frame rate and the second resolution is lower than the first resolution. Further, an amount of motion is detected in the captured second video data. On the basis of the detected amount of motion, the at least one imaging sensor is switched to a second configuration. On the basis of the second configuration, third video data is captured at a third frame rate and a third resolution. The third frame rate is higher than the first frame rate and the third resolution is higher than the second resolution. |
| US09570104B1 |
Read head with co-planar readers offset from a third reader
A combination user data signal is read from two or more inner tracks of a recording medium via a first reader that encompasses the inner tracks. First and second data signals are read from respective first and second outer tracks that surround the inner tracks via second and third co-planar readers that are on a same head-gimbal assembly as the first reader. The first reader is centered between and downtrack from the first and second co-planar readers on the read head. User data is recovered based on the combination user data signal and the first and second data signals. |
| US09570093B2 |
Unvoiced/voiced decision for speech processing
In accordance with an embodiment of the present invention, a method for speech processing includes determining an unvoicing/voicing parameter reflecting a characteristic of unvoiced/voicing speech in a current frame of a speech signal comprising a plurality of frames. A smoothed unvoicing/voicing parameter is determined to include information of the unvoicing/voicing parameter in a frame prior to the current frame of the speech signal. A difference between the unvoicing/voicing parameter and the smoothed unvoicing/voicing parameter is computed. The method further includes generating an unvoiced/voiced decision point for determining whether the current frame comprises unvoiced speech or voiced speech using the computed difference as a decision parameter. |
| US09570091B2 |
Music playing system and music playing method based on speech emotion recognition
A music playing system and a music playing method suitable for playing music based on speech emotion recognition are provided. The music playing method includes following steps. A plurality of songs and song emotion coordinates of the songs mapping on an emotion coordinate graph are stored in a first database. Emotion recognition parameters are stored in a second database. A voice data is received and analyzed, and a current emotion coordinate of the voice data mapping on the emotion coordinate graph is obtained according to the second database. The setting of a target emotion coordinate is received. At least one specific song emotion coordinate closest to a cheer-up line connecting the current emotion coordinate and the target emotion coordinate is found. Songs corresponding to aforementioned emotion coordinates are sequentially played. |
| US09570088B2 |
Signal processor and method therefor
A signal processor is configured to suppress a noise component contained in an input voice signal by means of coherence filtering. The processor includes an iterative coherence filtering function for repeatedly conducting the coherence filtering on a signal, which has been subjected to the coherence filtering and then input to the processor again as input signal, and performs the iteration processing on the signal obtained by the coherence filtering until a condition for terminating the iteration is satisfied, thereby preventing musical noise from generating while a noise component is suppressed. |
| US09570081B2 |
Backwards compatible audio representation
It is inter alia disclosed to provide a left signal representation associated with a left audio channel and a right signal representation associated with a right audio channel, each of the left and right signal representations being associated with a plurality of subbands of a frequency range, and to provide directional information associated with at least one subband of the plurality of subbands associated with the left and the right signal representation, the directional information being at least partially indicative of a direction of a sound source with respect to the left and right audio channel. |
| US09570080B2 |
Apparatus and method for encoding a multi-channel audio signal
An encoding apparatus comprises a frame processor (105) which receives a multi channel audio signal comprising at least a first audio signal from a first microphone (101) and a second audio signal from a second microphone (103). An ITD processor 107 then determines an inter time difference between the first audio signal and the second audio signal and a set of delays (109, 111) generates a compensated multi channel audio signal from the multi channel audio signal by delaying at least one of the first and second audio signals in response to the inter time difference signal. A combiner (113) then generates a mono signal by combining channels of the compensated multi channel audio signal and a mono signal encoder (115) encodes the mono signal. The inter time difference may specifically be determined by an algorithm based on determining cross correlations between the first and second audio signals. |
| US09570074B2 |
Behavior adjustment using speech recognition system
Methods, systems, and apparatus are described for inducing a user of a speech recognition system to adjust their own behavior. For example, in one implementation, a speech recognition system that allows children to control electronic devices can improve the child's speech development, by encouraging the child to speak more clearly. To do so, the speech recognition system can generate a phonetic representation of a term spoken by the child, and can determine whether the phonetic representation matches a particular canonical pronunciation of the particular term that is deemed age-appropriate for the child. Upon determining that the particular canonical pronunciation that matches the phonetic representation of the term spoken by the child is not age-appropriate, the speech recognition system can select and implement a variety of remediation strategies for inducing the child to repeat the term using a pronunciation that is considered age-appropriate. |
| US09570071B1 |
Audio signal transmission techniques
A voice interaction architecture that compiles multiple audio signals captured at different locations within an environment, determines a time offset between a primary audio signal and other captured audio signals and identifies differences between the primary signal and the other signal(s). Thereafter, the architecture may provide the primary audio signal, an indication of the determined time offset(s) and the identified differences to remote computing resources for further processing. For instance, the architecture may send this information to a network-accessible distributed computing platform that performs beamforming and/or automatic speech recognition (ASR) on the received audio. The distributed computing platform may in turn determine a response to provide based upon the beamforming and/or ASR. |
| US09570066B2 |
Sender-responsive text-to-speech processing
A method of speech synthesis including receiving a text input sent by a sender, processing the text input responsive to at least one distinguishing characteristic of the sender to produce synthesized speech that is representative of a voice of the sender, and communicating the synthesized speech to a recipient user of the system. |
| US09570065B2 |
Systems and methods for multi-style speech synthesis
Techniques for performing multi-style speech synthesis. The techniques include using at least one computer hardware processor to perform: obtaining input comprising text and an identification of a first speaking style to use in rendering the text as speech; identifying a plurality of speech segments for use in rendering the text as speech, the identified plurality of speech segments comprising a first speech segment having the first speaking style and a second speech segment having a second speaking style different from the first speaking style; and rendering the text as speech having the first speaking style, at least in part, by using the identified plurality of speech segments. |
| US09570062B2 |
Method and device for self-adaptively eliminating noises
The present invention discloses a method and device for self-adaptively eliminating noises. Said method comprises: filtering the signal received by a first microphone using a first filter, filtering the signal received by a second microphone using a second filter, and obtaining a signal with noises reduced by subtracting the filtered signals; wherein, in a noise segment, the coefficients of the first filter the second filter are updated respectively using the signal with noises reduced such that the noise component contained in the signal filtered by the first filter tends to be the same with the noise component contained in the signal filtered by the second filter; and in a noisy voice segment, the coefficients of the first filter and the second filter are remained unchanged respectively, the first filter and the second filter respectively use a coefficient updated in the noise segment last time to filter the signals received by the first microphone and the second microphone. The present invention can address the problem that noise eliminating effect is poor in the prior art caused by the fact that FIR filter cannot approach the optimal solution for eliminating noises. |
| US09570058B2 |
Audio signal processing device and parameter adjusting method
An audio signal processing device and a parameter adjusting method, configured such that: a two-channel screen displaying a plurality of parameters for each of two channels allocated to any two channel strips, in accordance with operation of edit buttons of the two channel strips, is displayed on a display; each of a plurality of parameters for one channel, out of the two channels displayed in the two-channel screen, are allocated to a control of each channel strip in a first group; each of a plurality of parameters for the other channel are allocated to a control of each channel strip in a second group; and values of the parameters allocated to the controls are adjusted in accordance with operation of the controls. |
| US09570056B2 |
Audio data synthesis method, audio output method, and program for synthesizing audio data based on a time difference
An audio data synthesis method including a time of a plurality of audio data is adjusted without using a device which can acquire the standard time. Specifically, audio data is obtained based on synchronized recording of the first and second recorders without using standard time. A time difference is calculated between an own terminal and another terminal, based on the time at which output of a first sound from the audio output module is started, a time at which input of a sound corresponding to the audio data to the audio input module is started, a time indicated by the first information, and a time indicated by the second information. Second and third audio data is synthesized after a time difference between the second and third audio data based on the third sound which is input to the audio input module is adjusted, based on the time difference. |
| US09570051B1 |
Organic sound texture enhancement and bridge strengthening system for acoustic guitars and other stringed instruments
A sound resonator device for internal connection to a guitar or other musical instrument that has strings tensioned over any type of bridge piece. The resonator device includes a torsion arm affixed to a sound board of the instrument from which is connected a plurality of involute coil sets, each made from a harmonically predetermined thickness (or gauge) of metal wire secured at its opposite end to the instrument interior. |
| US09570048B2 |
Image display
Herein disclosed an image display including: row scan lines configured to supply a control signal; column signal lines configured to supply a video signal; and pixel circuits configured to be disposed at intersections between the scan lines and the signal lines, wherein each of the pixel circuits has at least a drive transistor, a sampling transistor connected to a gate of the drive transistor, a capacitive part connected between the gate and a source of the drive transistor, and a light-emitting element connected to the source of the drive transistor. |
| US09570045B2 |
Terminal apparatus and display control method
A terminal apparatus includes a display, a display control unit configured to display a screen on the display in a given display mode, a first selection operation detection unit configured to detect that a first selection operation concerning the given display mode has been performed in a given area of the screen, and a second selection operation detection unit configured to detect that a second selection operation concerning given processing has been performed in the given area of the screen. The display control unit displays a screen by changing to a second display mode based on detection of the first selection operation in the screen displayed in a first display mode, performs the given processing based on detection of the second selection operation, and performs display control processing for displaying a screen in the first display mode after the given processing. |
| US09570044B2 |
Image adjusting method, light source module and electronic device
An image adjusting method, a light source module, and an electronic device are provided. The image adjusting method includes the following steps. A first set of light source and a second set of light source of the light source module are driven independently by corresponding driving intensity respectively. An image display command is received. The driving intensity corresponding to the first set of light sources and the second set of light sources respectively are adjusted according to the image display command, wherein a gamut of the first set of light sources is wider than that of the second set of light sources, and luminous efficacy of the second set of light sources is higher than that of the first set of light sources. |
| US09570038B2 |
Mobile device and control method thereof
A mobile device and a method for controlling the mobile device are provided. The mobile device includes a flexible display unit that has a first longitudinal edge and a second longitudinal edge and is configured to be wound in spiral turns and thereby to create at least two display regions with respect to a boundary between the first longitudinal edge in one turn and the second longitudinal edge in a next turn. The mobile device further includes a sensor unit configured to sense the boundary and to determine a display region, and a control unit configured to control the determined display region. |
| US09570036B2 |
Method and device for processing video image
A method and device for processing a video image are provided. The method comprises: receiving an original video image; adjusting a signal clock frequency of the original video image to acquire a processed video image; after a command signal input by a user is received, capturing the processed video image according to a preset size to acquire a video image corresponding to a display window of the preset size; and encoding the video image corresponding to the display window of the preset size to acquire an encoded video image. According to the method and device for processing the video image disclosed by the disclosure, new line, field and blanking synchronization signals are acquired through adjusting the clock frequency of an input image, and then, the corresponding capturing operation and outputting operation are performed according to the image display requirements of the user, so that the effect that video images with any resolution are reliably and stably displayed in the best display area range is realized. |
| US09570031B2 |
Apparatus and method for monitoring pixel data and display system adopting the same
An apparatus for monitoring pixel data includes a multiplexer configured to select pixel data applied to at least one of function blocks which is configured to convert the pixel data provided from an external device and adjust characteristics of a display device, a monitoring module configured to store the pixel data selected by the multiplexer, and an analyzing module configured to output a location selection signal to the multiplexer which provides the monitoring module with the pixel data based on the location selection signal, to read out the pixel data stored in the monitoring module by applying a pixel position signal to the monitoring module, and to analyze a variation of the read out pixel data. |
| US09570023B2 |
Display panel having a boosting voltage applied to a subpixel electrode, and method of driving the same
A display panel including a plurality of pixels. A first pixel among the plurality of pixels includes a first subpixel, which further includes a first subpixel electrode, a first switching element configured to apply a data voltage to the first subpixel electrode, and a second switching element applying a boosting voltage to the first subpixel electrode. The first pixel further includes a second subpixel including a second subpixel electrode and a third switching element applying the data voltage to the low pixel electrode. Accordingly, display quality and reliability of the display panel may be improved. |
| US09570022B2 |
Liquid crystal display device
A liquid crystal display device includes a liquid crystal panel of a normally black type which receives a plurality of scan signals and a common voltage having a voltage level which periodically varies, and a backlight unit which provides backlight to the liquid crystal panel, where the plurality of scan signals sequentially has a scan-on voltage along a first direction, and the backlight has a luminance which is increased or decreased along the first direction. |
| US09570019B2 |
System and method for coordinating image capture in a camera hidden behind a display device
An information handling system includes a thin panel display device with a camera oriented behind an outer liquid crystal (LCD) layer of the thin panel display device. The outer LCD layer of the thin panel display device having a camera zone through which the aperture of the camera receives light and a processor or set of processors determines camera usage a software application operating on the information handling system and coordinating camera operation and thin panel display device operation through the outer LCD layer in accordance with the camera usage by modifying a display refresh rate at the outer LCD layer camera zone. |
| US09570013B2 |
Dimming control device, image display device, and dimming control method
A light control device adjusts light intensity. The light control device determines whether or not the image based on an image signal is a correction object based on an image feature quantity of the image signal, and set adjustment information for adjusting intensity of light based on the determined result. Then, the light control device adjusts the light intensity of the light for the image display based on the adjustment information. |
| US09570012B2 |
Data compensator and display device including the same
A data compensator includes first logic, second logic, third logic, fourth logic, and fifth logic. The first logic calculates block compensation coefficients for blocks in a first frame based on first pixel data of the first frame. The second logic generates first gamma applied pixel data based on the first pixel data of the first frame and to generate second gamma applied pixel data based on the first gamma applied pixel data and second pixel data of a second frame adjacent the first frame. The third logic selects a number of the block compensation coefficients based on a pixel coordinate. The fourth logic generates a pixel compensation coefficient corresponding to the second pixel data by interpolating the selected block compensation coefficients based on the pixel coordinate. The fifth logic generates output pixel data based on the second gamma applied pixel data and the pixel compensation coefficient. |
| US09570011B2 |
Source driver IC chip
A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part (220) configured to generate a reference gradation voltage based on a first or second gamma characteristic of the display panel, using first and second power supply voltages (VH) and (VL) inputted through first and second external terminals (PA2, PA3); and a third external terminal (PA4) for externally outputting said reference gradation voltage. The source driver IC chip further includes first and second gradation voltage generating parts configured to generate first and second gradation voltages respectively, using a reference gradation voltage based on a first gamma characteristic inputted through a fourth external terminal and a reference gradation voltage having a second gamma characteristic inputted through a fifth external terminal respectively. |
| US09570005B2 |
Pixel circuit, driving method therefor and display device
Provided are a pixel circuit, a driving method for the pixel circuit and a display device including the pixel circuit. In the pixel circuit, when the data is written to the storage capacitor, the threshold voltage of the driving transistor and the data voltage are pre-stored in the storage capacitor by means of a diode connection formed by the driving transistor, so that the drift of the threshold voltage can be compensated effectively, and thus the uniformity and the stability of the driving current are maintained. Further, in the embodiment of the present disclosure, the scan signal for the pixel circuit is multiplexed in the touch circuit, and the coupling capacitor in the touch circuit is charged simultaneously while the storage capacitor is charged, and thus, the integration of the touch circuit into the pixel circuit can be realized perfectly without increasing the complexity of the circuit structure and the operation thereof. |
| US09570004B1 |
Method of driving pixel element in active matrix display
A method of driving a pixel element in a matrix of pixel elements includes (1) setting the bias voltage of a first transistor to a value that is substantially close to a threshold voltage of the first transistor by changing a voltage across a first capacitive element with a current passing through the first transistor; (2) setting the bias voltage of the first transistor to a value that is different from the threshold voltage of the first transistor; and (3) causing a change of the bias voltage of the first transistor. |
| US09569994B2 |
Digital display device and image arrangement method using the same
A digital display device that implements a digital photo frame function. The digital display device includes a user input unit to receive control signals corresponding to a user operation, the control signals to control a plurality of images to be continuously displayed, a display controller including an image arrangement unit, the display controller to output display signals by storing image files or processing the stored image files according to the control signals, a storage unit having image files stored therein and a display unit to display the plurality of images on a screen according to the display signals, the image arrangement unit to arrange the plurality of images in an arrangement order for display based on comparison results that compare data for pairs of images selected from the plurality of images upon the control signals being input. |
| US09569988B2 |
Display apparatus and electronic equipment
Disclosed herein is a display apparatus including: a first pixel including three sub-pixels for displaying three primary colors respectively; and a second pixel including three sub-pixels for displaying two colors selected among the three primary colors and a predetermined color other than the three primary colors, wherein, in the first pixel, the size of the display surface of a sub-pixel for displaying a specific color included in the three primary colors as a specific color missing from the second pixel is larger than each of the sizes of the display surfaces of the two other sub-pixels for displaying the two other primary colors respectively. |
| US09569987B2 |
Label for vegetables, fruit and house plants
A label with which, among other things, vegetables, for instance vine tomatoes, fruit and house plants, can be supplied with information. The label is a three-dimensional object obtained by folding and gluing a punched or cut piece of paper, cardboard or another type of thin-walled material, which object can be attached to one or more branches of a vine of tomatoes and whereby at least one surface area of the three-dimensional object is visible in such a way that it can serve as an information-bearing surface. |
| US09569977B2 |
Responsive book system and method therefor
In one aspect, the present invention is directed to a responsive book system comprising: a book comprising a detecting system, for detecting a current page from a plurality of detectable pages of the book (i.e., the opened page); a storage, for storing content associated with each of the detectable pages; and one or more remote responders, for playing and/or displaying the content associated with the current page. In another aspect, the present invention is directed to a responsive book method comprising the steps of: detecting the current page in a book from a plurality of pages; and playing and/or displaying, by a remote responder, content associated with the current page. |
| US09569976B2 |
Methods circuits, devices and systems for personality interpretation and expression
The present invention includes methods circuits, devices and systems for personality interpretation and expression. A personality interpretation and expression system may include central processing logic in addition to a personality engine. The central processing logic may be adapted to generate a data set corresponding to collected user and/or environment information. The personality engine may be adapted to evaluate a data set received from the central processing logic and generate at least one interaction instruction corresponding to the data set. Generating an interaction instruction is at least partially based on a comparison between the data set and a data set in a personality database functionally associated with or otherwise integral to the personality engine. |
| US09569967B2 |
Collision warning for a vehicle
A method and apparatus for warning a driver of a motor vehicle of a predicted collision with a stationary object. A proximity sensor is used to determine a position of an obstacle relative to the vehicle. A steering angle of the vehicle is determined and used to predict a trajectory of the vehicle. A collision zone on the vehicle is identified based on the vehicle trajectory, the collision zone being that spot or location on the vehicle which is predicted to contact the obstacle. A visual display within the vehicle (on the control panel, for example) provides a visual indication to the driver of the position of the collision zone on the vehicle and a predicted trajectory of the collision zone as the vehicle moves in accordance with the steering angle. |
| US09569961B2 |
System and method for using cellular network components to derive traffic information
A traffic reporting system and method for geographic area of interest. The system includes standard wireless telecommunication components configured to establish search criteria, determine a sample size, collect traffic information, calculate additional traffic information, and generate reports. |
| US09569960B2 |
Method and apparatus for providing traffic jam detection and prediction
An approach is provided for predicting starting points and/or ending points for traffic jams in one or more travel segments. The approach involves processing and/or facilitating a processing of probe data associated with at least one travel segment to cause, at least in part, a generation of at least one speed curve with respect to a distance dimension and a time dimension, wherein the probe data includes speed information, and wherein the at least one speed curve indicates at least one previous starting point, at least one previous ending point, or a combination thereof for one or more previous traffic jams based, at least in part, on the speed information. The approach also involves processing and/or facilitating a processing of the at least one previous starting point, the at least one previous ending point, or a combination thereof to determine at least one starting point trend curve, at least one ending point trend curve, or a combination thereof with respect to the distance dimension and the time dimension. The approach further involves determining at least one predicted evolution of at least one starting point, at least one ending point, or a combination thereof for at least one traffic jam in the at least one travel segment based, at least in part, on the at least one starting point trend curve, the at least one ending point trend curve, or a combination thereof. |
| US09569958B2 |
Prioritization of power system related data
A method for prioritizing events on an electrical power system, including: (a) acquiring at least one data portion representative of the behavior of the electrical power system, the at least one data portion containing at least one power system event; (b) assigning at least one rank value to the at least one data portion based on the type of power system event, the rank value indicative of a priority of the event; and (c) conducting subsequent operations on the at least one data portion in accordance with the at least one rank value. |
| US09569956B1 |
Remote monitoring and control system and method
The remote monitoring and control system contains at least a control device, a server device, and a mobile device. The control device periodically collects status/environmental data and delivers these data to the mobile device via the server device. An operator can set up control data on the mobile device. The server device automatically converts the control data set by the operator into appropriate control command by a conversion table corresponding to a specific control device. Therefore, the present invention achieves the goal of using a single mobile device to control multiple devices without mistakenly issuing a false command to a wrong device. |
| US09569955B2 |
Universal multi-function wall switch
An apparatus in accordance with the invention includes a directional switching device configured to provide directional control along multiple axes (e.g., perpendicular axes). Directional control along a first axis enables selection of a current function from a plurality of functions. Similarly, directional control along a second axis increases or decreases an amount associated with the current function. In certain embodiments, an indicator, such as colored light, may indicate the current function of the directional switching device. Selection of a first function from the plurality of functions may enable the directional switching device to wirelessly control a first device, while selection of a second function from the plurality of functions may enable the directional switching device to wirelessly control a second device. A corresponding method is also disclosed herein. |
| US09569953B2 |
Motion sensor
A motion sensor includes an infrared detector with a first set of detector elements and a second set of detector elements. The motion sensor also includes an optical system to direct electromagnetic energy from a first set of monitored volumes spaced at a pitch in a first direction onto the first set of detector elements and to direct electromagnetic energy from a second set of monitored volumes spaced at the pitch in the first direction onto the second set of detector elements. The second set of monitored volumes have an offset from the first set of monitored volumes in the first direction. |
| US09569948B1 |
Child detection and alert system for a vehicle
A child detection and alert system for a vehicle is an easily installed alert system for the driver of a motor vehicle that uses the vehicle's anti-theft system to notify the driver, after leaving the vehicle that a child has been left behind in a child car seat. The system has a sensor mat having two different types of sensors that is placed in the child car seat before the child is seated. The sensor mat has a battery, a transmitter for wirelessly transmitting a signal from the processor in the housing with the transmitter, and a charge cord. A second part of the system has a wireless receiver that plugs into the vehicle's computer and accesses the on-board vehicle anti-theft system to utilize the alarm functions that honk the horn and flash the lights if alarm conditions are met. |
| US09569947B2 |
Forewarning of risks when working on an aircraft
Automating the forewarning of risks incurred when working on an aircraft, and a forewarning system. The system comprises an identification module configured to identify a set of risky zones in the aircraft and its environment during current work on the aircraft by a set of operatives, a location module configured to locate a position of each operative during the current work, and an alert module configured to generate an alert when an operative is situated in a risky zone. |
| US09569946B2 |
Smoke alarm according to the scattered light principle having a two-color light-emitting diode with different sizes of LED chips
An optical smoke alarm contains a detector unit that works according to the scattered light principle with a light-emitting diode to irradiate particles to be detected and a photo sensor which is spectrally sensitive thereto to detect the light scattered by the particles. The light-emitting diode contains a first LED chip being a surface-emitting radiator for emitting a first light bundle with light in a first wavelength range of from 350 nm to 500 nm. It contains a second LED chip being a surface-emitting radiator for emitting a second light bundle with light in a second wavelength range of from 665 nm to 1000 nm. The two LED chips are arranged next to each other. A ratio of the optically active surface of the first LED chip to the optically active surface of the second LED chip is within a range of from 2 to 20. |
| US09569945B2 |
System and method for fire progress monitoring
A system is provided that includes a plurality of fire detectors distributed throughout a secured geographic area, a monitoring panel that detects a status of each of the plurality of fire detectors and saves a status indicator of the fire detector indicating one of normal, alarm, and fault into a memory along with a time value, an alarm processor of the monitoring panel that detects alarm signals from the plurality of fire detectors and presents respective indicators of the activated fire detectors on a geographic map of the secured area shown on a display, and a fire progression processor that displays an indicator of a progression of a fire on the map of the display based upon the status indicators saved in memory and upon a correlation between a status indicator of alarm in a previous time period and a status indicator of fault in a more recent time period. |
| US09569941B1 |
Announcing the selection of merchandise at a point-of-purchase
An improvement in an apparatus and a method provide an audible signal for announcing a selection, by a purchaser, of an item of merchandise placed at a dispensing location at a point-of-purchase. An annunciator emits an audible signal of limited duration for announcing the selection. A motion-responsive activator is coupled with the annunciator for activating the annunciator to emit the audible signal in response to imparting an activating motion to the activator. A selection-responsive component is coupled with the activator and is movable in response to the purchaser making a selection at the dispensing location, to impart an activating motion to the activator and, consequently, to activate the annunciator to emit the audible signal of limited duration announcing the selection. |
| US09569939B2 |
Event detector and medicament dispenser having such an event detector
A compact battery-free event detector having a switching element, which can be remagnetized in a bistable manner by a magnet in a sensor coil which then provides an event pulse and supplies a non-volatile memory circuit with a downstream non-volatile display, is designed to detect recurring movements by virtue of the switching element being able to be moved back and forth relative to the magnet between the activation and regeneration fields of its two poles. The manual operation of an inhalation or injection piston in a medicament dispenser can therefore be detected, in particular, and a dose of medicament, for instance, can be monitored thereby. The display is preferably created using e-paper or e-ink technology which, like the memory circuit which is operated only sporadically, obtains its energy needed to change the indication from the event pulse from the sensor coil. |
| US09569938B1 |
Video content analysis using point of sale data
In an embodiment, a method of performing video content analysis using transactional data is provided. The method comprises identifying and receiving the transactional data and a segment of video corresponding to a transaction, integrating the transactional data with the segment of video, and analyzing the integrated video to determine an action to take in relation to the transaction. |
| US09569935B2 |
Method and apparatus for combining symbols in gaming devices
Embodiments of the present invention set forth systems, apparatuses and methods for combining symbols in gaming devices. Accordingly, a gaming device can be configured to display a plurality of game elements each including a game symbol on a game display in response to a game initiation signal. When one or more predefined game conditions are satisfied, the method further includes combining two or more of the game symbols in a single game element. In some instances, one or more of the symbols that left their respective game elements are replaced with additional game symbols. The resulting game grid may then be evaluated to determine prizes associated with winning symbol combinations, including using one or both of the symbols combined in the single game element in the winning symbol combinations. |
| US09569933B2 |
Method and apparatus for conducting an electronic card game tournament
Systems and methods for conducting a localized, electronic card game tournament adaptable for play in private homes and public venues with no equipment or system modifications are disclosed. In one embodiment the tournament players' identities are verified. Once the players identities are identified, they are provided with handheld electronic game units and tournament entry credentials. Players will enter their tournament entry credentials into the respective handheld electronic game units. Once the tournament entry credentials have been entered into the handheld electronic game unit, game events are transmitted to the handheld electronic game unit from a single remote server. Furthermore, in this embodiment, the tournament entry fee, if any, is maintained separately from the remote game server and the handheld electronic game units. The fees may be collected and/or winnings may be paid in case, through electronic transfer or through electronic currency. |
| US09569930B2 |
Gaming system and method for providing an additional gaming currency
A gaming system including a central server linked to a plurality of gaming machines. The gaming system includes a point or count based system to provide one or more awards to one or more players. Such points are accumulated by a player based on one or more events associated with the player's gaming experience. The points or counts utilized in the gaming system are selectively redeemed by the player in exchange for one or more opportunities to win an award. It should be appreciated that in one embodiment, the equalizing units disclosed herein are different, separate and independent from any monetary based points or credits, any promotional based points or credits, or any player tracking points. |
| US09569929B2 |
Systems for an intermediate value holder
Systems for providing an intermediate value holder in a gambling hybrid game are disclosed. The intermediate value holder may be used to change a set of variables in an entertainment game provided the gambling hybrid game. The intermediate value holder may be obtained as the result of a gambling event or by the expenditure of a form of credit by the player. |
| US09569928B2 |
Method for providing reward item of online game and apparatus for the same
A reward item providing method of an online game includes: generating at least one reward item table corresponding to one mode that can be provided in a game and storing at least one reward item available in the other modes; setting each win probability of at least one reward item of at least one reward item table; drawing a won item among at least one item according to the win probability in the reward item table corresponding to the executed mode if the character of the user wins the match in the one mode; displaying a reward item providing screen providing the won item to the character and including a mode entry button to enter an item display mode as a mode using the won item; and entering the item display mode when receiving a selection input for the mode entry button. |
| US09569927B2 |
Cashless reservation system
A gaming machine and a gaming system is described. Gaming machines may be reserved by operating a button panel. In certain embodiments the reserved gaming machine or a head system causes the printing of a ticket and when that ticket is read by a bill acceptor, the gaming machine unlocks. In other embodiments, reservation is made by other means, including player cards. |
| US09569925B1 |
Distributed secrets for validation of gaming transactions
Nested commit/reveal sequences using randomized inputs from each participant in a gaming transaction (e.g., the house and each player) may be employed to provide a selection of outcome or outcomes that can be verified by each participant as free from cheating. In general, techniques may be employed in a variety of distributed gaming transaction environments and as a verification facility for any of a wide variety of games in which the risk of player collusion can be eliminated. Nonetheless, several variations on a distributed card dealing method are illustrative and will be appreciated by persons of ordinary skill in the art as applicable in other gaming environments, including games employing outcomes denominated in die (or dice) rolls, coin toss, wheel spins, blind selection or other ostensibly random selection of an outcome from a predefined set thereof. |
| US09569923B1 |
Mobile gaming systems for noise suppression and selective sound amplification
A mobile gaming device is configured for dynamic and location-specific noise suppression. The device samples ambient sounds via a sound receiver, and identifies a profile of ambient sounds and exception sound signatures for a current location. Resident sound emitters are directed to emit sound waves which locally suppress ambient sounds, but local suppression may be disabled for sounds associated with the exception sound signatures. The device may further locally amplify sounds associated the gaming application, and in some embodiments may locally amplify sounds associated with the exception sound signatures, such as for example location-specific alerts. In various embodiments, a plurality of mobile gaming devices in a common location may exchange ambient sound information. In various embodiments, the mobile gaming devices are coupled to a central server which generates a baseline profile for each gaming zone and directs local noise suppression. |
| US09569918B2 |
Computer and method for game control
A server apparatus provides a game which accompanies a resource increasing or decreasing in a game space to a plurality of terminal apparatuses via a network. The server apparatus collects and accumulates the resources from the plurality of terminal apparatuses in the first mode and releases the accumulated resource in the second mode. The server apparatus selectively switches between the first mode and the second mode so as to distribute the resources upon reception of a request from a terminal apparatus. |
| US09569917B2 |
Gaming method and apparatus for facilitating a game involving specialty functionality
Various embodiments concern a method for facilitating a gaming activity having specialty functionality comprising providing a grid formed by a plurality of elements and marking elements of the plurality with markings selected from a plurality of marking-types, the plurality of marking-types including a feature marking-type. A plurality of feature indicators can be positioned in the grid. Then, for each element of the plurality that is marked with the feature marking-type and positionally associated with a feature indicator of the plurality, the feature marking-type can be re-marked to a respective element of the plurality that is adjacent to the element marked with the feature marking-type and positionally associated with the feature indicator. An outcome can then be determined based on one or more combinations of the markings. |
| US09569914B2 |
Gaming machine with a predetermined number of symbols scrolled for display prior to wild symbol and having a predetermined background color and control method thereof
A slot machine includes a display on which symbols are rearranged in partitioned regions arranged in a matrix pattern including a plurality of columns and rows. The display includes a plurality of display windows corresponding to the respective columns for each unit game. In each of the display windows, for each slot game, executed is video display in which a symbol array having a plurality of symbols arranged therein is scrolled in an arrangement direction of the symbols. By this video display, the symbols arranged in the partitioned regions are rearranged in the slot game. When a feature game trigger is established during the slot game, an additional “WILD” symbol is inserted into the symbol array. The symbols in each symbol array have background images, respectively. The background images of a predetermined number of consecutive symbols immediately upstream of the “WILD” symbol are displayed in a predetermined color, and the background images of the other symbols are displayed in a normal color. |
| US09569913B2 |
Self-aligning termination for memory alloy wire
A self-aligning memory alloy wire actuator has a memory alloy wire having first and second ends with at least one terminal coupled to one end of the memory alloy wire. The terminal includes two wings and an extended piece connected in the shape of a T. The two wings are disposed on opposite sides of the extended piece and perpendicular to the extended piece. Each wing comprises top and bottom surfaces, a front surface, and an outside end. The top surfaces of the two wings lie on a common top plane and the front surfaces of the two wings lie on a common front plane. The memory alloy wire is coupled to the extended piece of the terminal. |
| US09569912B2 |
Article storage and retrieval apparatus and vending machine
A apparatus for moving an article that contains a first telescoping tube movably connected to a second telescoping tube, a suction cup connected to said first telescoping tube, and a drive assembly connected to the first telescoping tube. |
| US09569911B2 |
Secondary media return system and method
A method for facilitating a rapid return of a article to an article dispensing machine is provided. The article dispensing machine comprises a first user interface portion having the first user interface, a second user interface portion having a second user interface, and an article transfer portion for vending and returning articles. The method includes receiving from a first user interface a first request to return the article, determining whether the article transfer portion is available to enable the return of the article, and based on the availability determination, displaying through a first user interface screen associated with the first user interface portion information indicating whether to proceed with the return of the article or to wait for a notification to proceed with the return. |
| US09569907B2 |
System and method for the automated processing of physical objects
Methods and systems for verifying authenticity of a physical object and/or for verifying possession of the object by an individual are described. In one embodiment, the object is registered with a remote processing system. Data representing at least one characteristic of the object is obtained and stored in the remote system and the identity of the individual or entity possessing the object is authenticated. After authenticating the individual, an identifier is collocated (or an existing mechanism is activated or modified to replicate the identifier) with the object, where the identifier uniquely identifies the object and the individual possessing the object. The object and the identity of the individual possessing the object can be authenticated at a future time by sensing the collocated identifier and sending the sensed identifier to the remote system. The remote system can send instructions to an entity wishing to authenticate the object and its association with the individual possessing the object. The instructions can be set up at the time the object is registered in the remote system. The remote system can perform an interactive or automated session with the entity wishing to authenticate the object, thereby saving time and providing a robust method of authentication and means for carrying out additional processing functions. |
| US09569893B2 |
Hybrid display system displaying information by superimposition on the exterior
The general field of the invention is that of Instrument panel or cockpit display systems. The system according to the invention comprises: a first display device comprising a semi-transparent screen upon which a first image is displayed; a second mobile display device mounted on a helmet or augmented reality glasses, the said second device comprising means of displaying a second image collimated in a predetermined visual field; a detection of the orientation and of the position of the helmet in a predetermined reference system; first means making it possible to determine the zone of intersection of the predetermined visual field with the semi-transparent screen; second means making it possible to display in the said zone of intersection of the semi-transparent screen a first specific image, and/or to display in the second display device a second specific image, which are functions of the first image and of the second image. |
| US09569890B2 |
Method and device for generating a simplified model of a real pair of spectacles
A method and device for generating a simplified geometric model of a real pair of spectacles. The model includes a frame, lenses, and a predefined number of surfaces and normals thereof. An orientation of these normals is taken as an exterior of a convex envelop to the real pair of spectacles. The model is obtained in a phase. A set of shots of the real pair of spectacles to be modeled is produced with different angles-of-view and using different screen backgrounds with and without the real pair of spectacles. The simplified geometric model is constructed, consisting of a predefined number of surfaces and their normal beginning with a non-dense surface mesh and using an optimization algorithm that deforms the model's mesh so that the projections of its silhouette in each of the views best match the silhouettes detected in the images. |
| US09569888B2 |
Depth information-based modeling method, graphic processing apparatus and storage medium
A depth information-based modeling method, a graphic processing apparatus and a storage medium are provided. The depth information-based modeling method includes receiving a plurality of depth image data, each of which has depth information, and a plurality of color images, each of which color information. In the method, a plurality of 3D grids is obtained according to the color information, depth information and a plurality of uniform sampling grids. Each of the uniform sampling grids is further divided into a plurality of sub-grids. At least one point on each of the 3D grids is determined by the depth information, and the triangle meshes are generated according to the points. |
| US09569886B2 |
Variable shading
In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. An algorithm may be used to determine how the shading rate changes across the frame. |
| US09569883B2 |
Decoupled shading pipeline
In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region. |
| US09569880B2 |
Adaptive anisotropic filtering
A method, graphics processing unit, and system are described herein. The method for adaptive anisotropic filtering includes calculating a number of ways of anisotropy based on a computed level of detail of a texture map and applying a bilinear low pass filter to a texture map's closest two MIP maps using a processor. An effective number of ways and filter sizes may be computed on each of the closest two closest MIP maps. Additionally, the closest two MIP maps may be sampled at their respective effective number of ways. The method also includes applying a corresponding sized low pass filters to each of the closest two MIP maps, and combining the filtered closest two MIP maps using a weighted sum based on a fractional part of a computed level of detail. |
| US09569879B2 |
Culling using linear bounds for stochastic rasterization
We present a new culling test for rasterization of simultaneous depth of field and motion blur, which efficiently reduces the set of (x, y, u, v, t) samples that need to be coverage tested within a screen space tile. The test finds linear bounds in u, t space and v, t space respectively, using a separating line algorithm. This test is part of the foundation for an efficient 5D rasterizer that extracts coherence in both defocus and motion blur to minimize the number of visibility tests. |
| US09569872B2 |
Method and apparatus for rasterization
The application provides a method for rasterization. According to the method, a primitive may be divided, at a position where a color abruptly changes in the primitive, into a plurality of sub-primitives with continuously and gradually changing colors. Each of the sub-primitives is then rasterized. The present application further provides an apparatus for rasterizing an image. The apparatus may comprise a dividing module configured to divide a primitive at a position where a color abruptly changes into a plurality of sub-primitives with continuously gradually changing colors. Furthermore, the apparatus may comprise a rasterizing module configure to rasterize each of the sub-primitives. The application may improve the speed of the rasterization and the quality of the processed image. |
| US09569871B2 |
Visualization of relationships and strengths between data nodes
One or more processors receive a dataset that includes a plurality of nodes. One or more processors identify relationships between a plurality of interacting nodes within the dataset. One or more processors determine relationship strength values between a plurality of interacting node pairs within the dataset. One or more processors generate a graphical representation that represents the relationship strength values between the plurality of interacting nodes within the dataset. Interacting node pairs are connected by edges and the edges have a length that correlates with the relationship strength value between the interacting node pairs. |
| US09569867B2 |
Vector graph graphical object
Various embodiments are generally directed to techniques for increasing the amount of information conveyed per graphical object in graphical presentations of data. A non-transitory machine-readable storage medium includes instructions, that when executed, cause a computing device to determine a major range of values occurring during a major period, the major period including a shorter minor period; and generate a vector graph including a graphical object and an axis indicating a scale. The graphical object may include a major period line parallel to the axis and indicating the major range; and a minor period arrow overlying and pointing in a direction parallel to the length of the major period line, the point and base of the minor period arrow overlying the major period line at locations indicating values at an end and at a start, respectively, of the minor period. Other embodiments are described and claimed. |
| US09569866B2 |
Flexible video object boundary tracking
Techniques involving flexible video object boundary tracking are described. One or more curves, such as Bezier curves, are received as drawn by a user on an initial frame of video to define a boundary of an object in the frame. The curves are then mapped to a subsequent or previous frame of the video where the object is included but has a new or changed boundary. A segmentation boundary is determined for the object in the subsequent frame and endpoints of segments of the curves are snapped to the segmentation boundary. Additionally, confidence values are determined for subregions of the frame that include portions of the curves. These confidence values are used to update control points on the curve segments to fit the curve segments to the new or changed boundary of the object in the frame. |
| US09569860B2 |
Method and apparatus for compressing and decompressing data
Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. These index values are stored for use in deriving modulation data more accurately when decompressing the image data. |
| US09569856B2 |
Variable blocking artifact size and offset detection
An aspect of the invention includes a system and method for determining a block size and offset for a block artifact. A content is identified. The content can be an image, a frame of video, or any other appropriate content. Edge differences are calculated in each dimension of the content based on the pixel values. The edge differences are filtered. From the filtered edge differences, block attributes, such as block size and offset, can be determined. |
| US09569854B2 |
Image processing method and apparatus
The present disclosure discloses an image processing method and apparatus. The image processing method comprises: obtaining a two-dimensional image; determining a target area on the two-dimensional image, wherein the two-dimensional image includes a background area and a target area, and the background area is an area outside of the target area; detecting a location of the target area on the two-dimensional image; selecting, according to the location of the target area on the two-dimensional image, a default processing manner used to perform blurring processing on pixels of the background area; and performing the blurring processing on the pixels of the background area according to the default processing manner. The present disclosure solves a problem that in the prior art, the blurring processing manner cannot be adjusted accordingly depending on different target areas on the an image. Therefore, for different target areas, corresponding blurring processing manners thereof are adopted. |
| US09569853B2 |
Processing of light fields by transforming to scale and depth space
Light field images of a three-dimensional scene are transformed from an (image,view) domain to an (image,scale,depth) domain. Processing then occurs in the (image,scale,depth) domain. |
| US09569850B2 |
System and method for automatically determining pose of a shape
This invention provides a system and method for determining the pose of shapes that are known to a vision system that undergo both affine transformation and deformation. The object image with fiducial is acquired. The fiducial has affine parameters, including degrees of freedom (DOFs), search ranges and search step sizes, and control points with associated DOFs and step sizes. Each 2D affine parameter's search range and the distortion control points' DOFs are sampled and all combinations are obtained. The coarsely specified fiducial is transformed for each combination and a match metric is computed for the transformed fiducial, generating a score surface. Peaks are computed on this surface, as potential candidates, which are refined until a match metric is maximized. The refined representation exceeding a predetermined score is returned as potential shapes in the scene. Alternately the candidate with the best score can be used as a training fiducial. |
| US09569848B2 |
Advanced aircraft vision system utilizing multi-sensor gain scheduling
An enhanced vision system is provided for an aircraft performing a landing maneuver. Accordingly to non-limiting embodiments, a processor onboard the aircraft receives data from sensors or systems onboard the aircraft and determines a position of the aircraft relative to a runway using the data. Responsive to this determination, the processor adjusts the gain of a first vision system and a second vision system. Images from the first vision system and the second vision system are merged and displayed to the pilot until the completion of the landing maneuver. |
| US09569847B1 |
General and nested Wiberg minimization
One of the described methods includes receiving a plurality of images from a camera, the plurality of images comprising a sequence; identifying one or more two-dimensional features in each of a plurality of images in the received sequence of images; associating a three-dimensional point with each of the identified one or more two-dimensional features; tracking each of the one or more two-dimensional features through successive images in the plurality of images; and iteratively minimizing a two-dimensional image error between the tracked each of the one or more two-dimensional features and an image reprojection with respect to the three-dimensional point corresponding to the one or more two-dimensional features and a three-dimensional position of the camera corresponding to one or more of the plurality of images. |
| US09569844B2 |
Method for determining at least one applicable path of movement for an object in tissue
The invention relates to a method for determining at least one applicable path (32) for the movement of an object, especially of a surgical and/or diagnostical device, in human tissue (14) or animal tissue by means of a data set of intensity data obtained by a 3D imaging technique, the applicable path (32) of movement connecting a starting position (28) of the device with a defined target location (30). According to the invention the method comprises the steps: defining the target location (30) of a reference point of the device and choosing at least one possible starting position of the reference point of the device; determining a candidate path of movement (18, 20, 22) between the corresponding possible starting position (24,26, 28) and the defined target location (30); and evaluating the candidate path of movement (18, 20, 22) as being an applicable path (32) depending on information about local intensity extrema and/or intensity variation resulting from the intensity data along the candidate path of movement (18, 20, 22). The invention further relates to a corresponding computer-readable medium, a corresponding computer program product, and a corresponding computerized system. |
| US09569843B1 |
Parameter-free denoising of complex MR images by iterative multi-wavelet thresholding
A method for denoising Magnetic Resonance Imaging (MRI) data includes receiving a noisy image acquired using an MRI imaging device and determining a noise model comprising a non-diagonal covariance matrix based on the noisy image and calibration characteristics of the MRI imaging device. The noisy image is designated as the current best image. Then, an iterative denoising process is performed to remove noise from the noisy image. Each iteration of the iterative denoising process comprises (i) applying a bank of heterogeneous denoisers to the current best image to generate a plurality of filter outputs, (ii) creating an image matrix comprising the noisy image, the current best image, and the plurality of filter outputs, (iii) finding a linear combination of elements of the image matrix which minimizes a Stein Unbiased Risk Estimation (SURE) value for the linear combination and the noise model, (iv) designating the linear combination as the current best image, and (v) updating each respective denoiser in the bank of heterogeneous denoisers based on the SURE value. Following the iterative denoising process, the current best image is designated as a final denoised image. |
| US09569836B2 |
Defect observation method and defect observation device
Cases in which defects are analyzed in a manufacturing process stage in which a pattern is not formed or in a manufacturing process in which a pattern formed on a lower layer does not appear in the captured image are increasing. However, in these cases, there is a problem of not being able to synthesize a favorable reference image and failing to detect a defect when a periodic pattern cannot be recognized in the pattern. In the present invention, a defect occupation rate, which is the percentage of an image being inspected occupied by a defect region, is found, it is determined whether the defect occupation rate is higher or lower than a threshold, and, in accordance with the determination results, it is determined whether to create, as the reference image, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected. In particular, when the defect occupation rate is low, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected is used as the reference image. |
| US09569835B2 |
Pattern extracting apparatus and method
A pattern extracting apparatus includes a first storing section storing plural target information pieces, a candidate pattern producing section producing candidate patterns each including two or more items different from each other based on each of the items included in the plural target information pieces, a candidate evaluation value calculating section calculating an extraction evaluation value of the candidate pattern based on a frequency of appearance at which the produced candidate pattern appears in the plural target information pieces, a pattern extracting section determining and extracting any of the candidate patterns having the calculated extraction evaluation value satisfying a predetermined threshold value, and a second storing section storing an association degree between the items. The candidate evaluation value calculating section calculates the extraction evaluation value based on a weight based on an identified association degree between the items included in the candidate pattern and the frequency of appearance. |
| US09569833B2 |
Method and apparatus for checking a screw closure torque without contact
The torque which is required to open a plastic screw closure which is screwed onto a bottle is determined without contact by the rotation position of the screwed-on plastic screw closure in relation to the bottle being established. The rotation position is established by evaluating an image on the basis of a mark on the bottle and a mark on the screw closure. Ventilation slots which interrupt the turns of the screw thread on the bottle neck can be used as the mark on the bottle, and a predetermined breaking point on a securing ring of the screw closure can be used as the mark on the screw closure. |
| US09569831B2 |
Image processing apparatus, image processing method, and non-transitory computer-readable storage medium for extracting information embedded in a printed material
A plurality of images obtained by capturing, dividing over a plurality of times, a printed material in which additional information is embedded are input. Feature information concerning each of the inputted plurality of images is extracted. A poor quality area in the images is evaluated. An overlapping area of the plurality of images is specified based on the feature information. Additional information embedded in the printed material is extracted based on a result of the evaluating and a result of the specifying. |
| US09569829B2 |
Image processing apparatus, radiation imaging apparatus, control methods for them, gain image creation method, radiation imaging system, and storage medium
An image processing apparatus comprising: an obtaining unit configured to obtain a plurality of radiation images that have been sensed without arranging an object and include a defect, and information about the defect included in the radiation images; and a generation unit configured to generate a sensitivity correction image not including the defect based on the plurality of radiation images and the information about the defect. |
| US09569828B2 |
Method and apparatus for the imaging of a labeled biological sample
A method and apparatus for the imaging of a labeled biological sample. The method comprises illuminating the labeled biological sample, generating members of a time series of images if the labeled biological sample, generating a plurality of difference images between later members of the time series of images of earlier members of the time series of images and combining the plurality of difference images to generate a final image of the labeled biological sample. |
| US09569827B2 |
Image processing apparatus and method, and program
The present invention relates to an image processing apparatus and method, and a program that are capable of displaying images more easily and effectively.A degree-of-blur detecting unit 21 detects the degree of blur of an input image. The selecting unit 22 selects an image processing operation to be performed on the input image on the basis of a detection result of the degree of blur, and supplies the input image to a block that performs the selected image processing operation among a comic-style conversion unit 23 to a sharpness processing unit 28. The block supplied with the input image among the comic-style conversion unit 23 to the sharpness processing unit 28 performs the image processing operation on the input image and outputs it to an output unit 29. The present invention can be applied to an image processing apparatus. |
| US09569824B2 |
Distorted image correction apparatus and method
With regard to a distortion correction apparatus and method which are applicable to hardware for real-time distortion correction, provided are a distorted image correction apparatus and method for correcting a distortion of an image by using a non-polynomial estimation function suitable for a hardware operation, and for correcting the distortion of the image by utilizing a morphing form. |
| US09569823B2 |
Image processing device and method, and program for correcting a blurred moving image
Provided is an image processing device including an acquisition unit configured to acquire information on an imaging position and an imaging direction in units of frame images that constitute a moving image obtained through capturing by an imaging unit, a converted image generation unit configured to generate converted images having different imaging directions for each frame image that constitutes the moving image based on the frame image itself and preceding and succeeding frame images of the frame image, an evaluation value calculation unit configured to calculate an evaluation value for each converted moving image constituted by combining the converted image and the original frame image, the evaluation value being used to evaluate a blur between the converted images or between the original frame images, and a selection unit configured to select a converted moving image with less blur based on an evaluation value calculated by the evaluation value calculation unit. |
| US09569821B2 |
Image processing device, image processing method, and program
An image on which a noise reduction and a dynamic range expansion process have been performed is generated by a sequential synthesis process using continuous-photographed images of different exposure conditions. The continuous-photographed images of different exposure conditions are input, configuration pixels of an input image and an intermediate synthetic image are classified into a noise pixel, an effective pixel, or a saturation pixel, a synthesis processing method of a pixel unit is decided according to a combination of pixel classification results of the corresponding pixels, and the intermediate synthetic image is updated according to the decided method. A 3DNR process is performed when at least one of the corresponding pixels of the input image and the intermediate synthetic image is the effective pixel, the pixel value of the intermediate synthetic image is output without change when both of the corresponding pixels of the input image and the intermediate synthetic image are the saturation pixel or the noise pixel, and the 3DNR process is performed or the pixel value of the intermediate synthetic image is output when one is the saturation pixel, and the other is the noise pixel. |
| US09569817B2 |
Image processing apparatus, image processing method, and non-transitory computer readable storage medium
An image processing apparatus, determines, using a pixel signal included in a region referenced on a pixel of interest of a target image, a direction having a high signal correlation in the region, performs, using pixel signals from neighboring pixels of the pixel of interest based on a determination result, interpolation processing for interpolating a pixel signal of the pixel of interest, and performs reduction by reducing the number of pixels of the interpolated image, wherein the interpolation processing is executed according to a reduction rate used in the reduction, such that a high frequency component of the image decreases as a degree of reduction increases, while applying a weight to the pixel signal of a pixel, among the neighboring pixels, located in the direction determined as having the high correlation based on the determination result. |
| US09569816B2 |
Debanding image data using bit depth expansion
An image signal processing system may include processing circuitry that may reduce banding artifacts in image data to be depicted on a display. The processing circuitry may receive a first pixel value associated with a first pixel of the image data and detect a first set of pixels located in a first direction along a same row of pixels or a same column of pixels with respect to the first pixel. The first set of pixels is associated with a first band. The processing circuitry may then interpolate a second pixel value based on an average of a first set of pixel values that correspond to the first set of pixels and a distance between the first pixel and a closest pixel in the first band. The processing circuitry may then output the second pixel value for the first pixel. |
| US09569813B2 |
Method and apparatus for tile-based rendering
A method for tile-based rendering may include verifying a size of a memory available in an apparatus for rendering, and determining a number of buffers required for performing a rendering based on graphics data input, and may further include determining a size of a tile to be used for performing the rendering based on the determined number of buffers and the size of the memory available. |
| US09569807B2 |
Memory card for providing menu items to a remote wireless-enabled apparatus
A memory card (103) for use in an electronic apparatus (101) is proposed. In order to control an electronic apparatus (101) with an inbuilt processor (301) incapable of exporting digital data externally of the electronic apparatus (101), a user local at the electronic apparatus (101) is required to operate the electronic apparatus (101). This is not always convenient. The proposed memory card (103) has a wireless module (207) for receiving an instruction wirelessly from a remote wireless-enabled apparatus (105), and also a central processor (201) for controlling the inbuilt processor (301) of the electronic apparatus (101) in accordance with the received instruction. |
| US09569805B2 |
Intelligent routing of electric power
A method and system for dynamically routing electric power in real time in accordance with parameters submitted by buyers and sellers of electric power using a feedback control scheme. A control node is arranged for receiving the parameters via a wide area network and to generate a route plan based on the parameters as well as current supply and demand in a network. The control node is also connected to the transmission and distribution systems to dynamically route electric power between matched buyers and sellers to effect the route plan. |
| US09569800B2 |
Paperless receipt device
A process and apparatus provide a paperless electronic receipt. A storage device stores a communication identifier prior to a transaction at a point of transaction. Further, a transmitter sends the communication identifier to a point of transaction receipt transmission device at a point of transaction so that the point of transaction receipt transmission device sends an electronic receipt of a transaction at the point of transaction to the communication identifier based upon a selection being received at the point of transaction receipt transmission device to send the electronic receipt to the communication identifier. In addition, the electronic receipt is received and stored at the storage device based upon a selection being received at the point of transaction receipt transmission device to store the electronic receipt at the storage device. |
| US09569799B2 |
Risk unit based policies
Methods, computer-readable media, systems and apparatuses for determining and implementing risk unit based insurance policies are presented. A user may receive a plurality of risk units associated with an insurance policy. The risk units may be stored in a risk unit account associated with the user, the vehicle, etc. During operation of the vehicle, sensor data may be received. The sensor data may provide information associated with driving behaviors of the user, environmental conditions in which the vehicle is being operated, and the like. A consumption rate of the risk units may be determined based, at least in part, on the received sensor data. If a number of risk units in a risk unit account is below a predetermined threshold, a notification may be transmitted to the user and/or a predetermined number of risk units may be automatically added to the risk unit account. |
| US09569790B1 |
Resource allocation for advertising content on wireless communication devices
Systems, methods, and software for operating a wireless communication device are provided herein. In a first example, a method of operating a wireless communication device is provided. The method includes receiving user content and advertising content over a wireless link from a wireless communication network, and responsive to user input on the wireless communication device, altering a first resource portion associated with the wireless communication device for handling of the advertising content and altering a second resource portion associated with the wireless communication device for handling of the user content. |
| US09569786B2 |
Methods and systems for excluding individuals from retail analytics
Systems and methods are described for excluding individuals from retail analytics. Pedestrian traffic within a predetermined area is monitored via a video sensor to determine a video entrance. The video entrance may correspond to entrances of the predetermined area by a first set of individuals. The pedestrian traffic may also be monitored via a plurality of wireless sensors to determine a wireless entrance. The wireless entrance may correspond to entrances by a second set of individuals. The video entrance and the wireless entrance are compared to determine if any of the entrances associated with a video timestamp match any of the entrances with a wireless timestamp. An overall entrance count corresponding to the number of customers entering the predetermined area is determined. Retail analytics excluding employees may subsequently be calculated using the overall entrance count. |
| US09569784B2 |
Efficiently resolving the values for the tag parameters thereby syndicating the tag data as early as possible
A method, system and computer program product for resolving values of parameters of tags. A map is created which includes the number of times each parameter is referenced by the tags in a web page requested by a client device. The parameters in the map are then sorted in a list in descending order based on the number of times referenced by the tags. The value for the parameter listed at the top of the list is looked up. If the value cannot be located, then those tags that are associated with this parameter are added to a list of tags to be ignored. By ignoring such tags in this list, the resolving of tag values for tags to be syndicated can occur more quickly and efficiently, including syndicating the tag data before the web page is completely loaded. |
| US09569779B2 |
Fraud detection employing personalized fraud detection rules
Detection of fraud in financial transactions is facilitated. A financial transaction is initiated by a user, and based on the financial transaction, information is obtained by an electronic device of the user. Using the information, the electronic device evaluates a set of rules personalized for the user; the set of rules to be used to determine whether the financial transaction is to be approved for the user. The electronic device provides an initial indication, based on the evaluating, of whether the financial transaction is to be approved. |
| US09569778B2 |
Efficient prevention of fraud
This disclosure is directed to methods and systems for managing difficulty of use and security for a transaction. A transaction manager operating on a computing device may determining a range of possible steps for a transaction comprising security measures available for the transaction. The transaction manager may identify a threshold for a security metric to be exceeded for authorizing the transaction, the security metric to be determined based on performance of steps selected for the transaction. The transaction manager may select for the transaction at least one step from the range of possible steps, based on optimizing between (i) a difficulty of use quotient of the transaction from subjecting a user to the at least one step, and (ii) the security metric relative to the determined threshold. |
| US09569776B2 |
Secure authorizations using independent communications and different one-time-use encryption keys for each party to a transaction
A registered provider device encrypts provider input related to a transaction between the provider device and one of many registered user devices to create an encrypted one-time-use provider code (the encryption is performed using an encryption key produced, in part, using a uniquely sequenced number generated by a sequencer maintained by the provider device). Similarly, the user device encrypts user input to create an encrypted one-time-use user code using an encryption key produced, in part, using a uniquely sequenced number generated by a user sequencer maintained by the user device. The provider and user devices independently transmit their different encrypted one-time-use codes to an intermediate entity, which decrypts the encrypted codes. This decryption is performed using one-time-use encryption keys produced using sequencers maintained by the intermediate entity, and this decryption generates an authorization request. The intermediate entity obtains an authorization decision regarding the authorization request from the authorization entity. |
| US09569770B1 |
Generating constructed phrases
Techniques for generating and providing phrases are described herein. These techniques may include analyzing one or more sources to generate a first corpus of phrases, each of the phrases for use as an identifier and/or for association with a user. Once a first corpus of phrases has been generated, these phrases may be filtered to define a second corpus of phrases. Phrases of this second corpus may then be suggested to one or more users. In some instances, the phrases suggested to a particular user are personalized to the user based on information previously known about the user or based on information provided by the user. |
| US09569769B2 |
Composite activation indicia substrate
The present invention is generally directed towards a card and package assembly and methods of making the same. Card and package assemblies in accordance with some embodiments of the present invention may include a package, a data card, the data card packaged at least in part within the package, and an activation indicia, the activation indicia comprising a first portion printed on the package and a second portion printed on the data card. Methods of packaging a data card in accordance with some embodiments of the present invention may include steps of manufacturing or otherwise obtaining a data card, manufacturing or otherwise obtaining a package, determining an activation indicia, packaging the data card at least in part within the package, and printing the activation indicia in part on the data card and in part on the package. |
| US09569768B2 |
Systems, methods and apparatus for selecting a payment account for a payment transaction
Systems and methods for selecting a payment account for a payment transaction are provided by certain embodiments of the invention. Data may be collected from a payment device utilized for the transaction, and a plurality of payment accounts may be associated with the payment device. A personal identification number associated with the payment device may be received. At least one of the plurality of payment accounts associated with the payment device may be selected based on a portion of the received personal identification number. The transaction may be facilitated utilizing at least one of the selected payment accounts. |
| US09569766B2 |
Auto-detection of merchant payment preferences
Systems and methods for retrieving and displaying merchant payment preferences to a user are described. When a user is at or near a merchant location, a service provider determines the type or form of electronic payment the merchant can accept. The service provider then generates the specific type or form of payment for display or communication to a user device. The user is then able to present a type of payment accepted by the merchant and pay for a purchase. |
| US09569764B2 |
Point-of-sale customization service
Concepts and technologies are disclosed herein for point-of-sale customization service. A processor executing a point-of-sale customization service can receive a unique identifier associated with a user device detected in a proximity of a computing device. The processor can query preferences stored in a data store using the unique identifier and identify point-of-sale preferences associated with the user device based upon the querying. The processor can transmit the point-of-sale preferences to the computing device to apply to a transaction. |
| US09569763B2 |
Information gathering and decoding apparatus and method of use
An information gathering and decoding apparatus includes two information gathering devices that communicate with one another, preferably wirelessly. The two information gathering devices may be used substantially simultaneously to process one, or multiple, customer orders. Customer order information is sent from one information gathering device to the other, and only one of the information gathering devices communicates with a computer system to send information from both of the information gathering devices to the computer system as if the information originated from the one information gathering device. Communication between the two information gathering devices combined with a microprocessor in at least one of the information gathering devices may allow the information gathering and decoding apparatus to be used with existing computer systems, such as point of sale systems, preferably without modifying the computer system. One information gathering device may pre-qualify customers to purchase restricted items. The second information gathering device may access the pre-qualification from the first information gathering device to process sales of restricted items to customers. |
| US09569760B2 |
Rapid checkout after payment
A user's checkout information is stored for a certain amount of time, e.g., 10 minutes, after checkout, and the user is given the option of selecting a button to add one or more items for purchase and completing the purchase by adding the additional item(s) and approving the payment, without having to go through a complete checkout flow again. |
| US09569758B2 |
Automated banking machine that operates responsive to data bearing records
In an example embodiment, there is disclosed herein an automated banking machine that includes an instrument acceptor operable to receive financial instruments. The machine is operable to cause user data obtained from a user during a user session with the machine to be sent to a transaction authorizing host computer. The machine is operable to generate an electronic deposit slip that includes a data representative of a financial account associated with the user data, and a value of value of a financial instrument received by the instrument acceptor during the user session. The electronic deposit slip to be sent to a server that is remotely located from the automated banking machine and data representative of the value of the financial instrument is sent to the authorizing host terminal to cause the financial account to be credited an amount corresponding to the value of the financial instrument. |
| US09569752B2 |
Providing parameterized actionable communication messages via an electronic communication
A method, an apparatus and computer readable storage media facilitate initiating an actionable message at a computing device in response to input of a defined sequence of characters at the computing device, and executing an action associated with the initiated actionable message in accordance with information that is specific to the actionable message. |
| US09569751B2 |
Mechanism for creation and utilization of an attribute tree in a contact center
A graph database is described for use in connection with a contact center. The graph database includes a plurality of nodes and relationships that describe the operations, entities, personnel, and attributes in the contact center. Also included in the graph database is an attribute tree that enables a work assignment engine in the contact center to make proximity-based work assignment decisions. |