最新美国发明专利第2017-02-14期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09570736B2	Electrodes with three dimensional current collectors and methods of making the same In some embodiments, the present disclosure pertains to methods of forming electrodes on a surface. In some embodiments, the formed electrodes have a three-dimensional current collector layer. In some embodiments, the present disclosure pertains to the formed electrodes. In some embodiments, the present disclosure pertains to energy storage devices that contain the formed electrodes.
US09570728B2	Electricity supply element and ceramic separator thereof An electricity supply element and the ceramic separator thereof are provided. The ceramic separator is adapted to separate two electrode layers of the electricity supply element for permitting ion migration and electrical separation. The ceramic separator is made of ceramic particulates and the adhesive. The adhesive employs dual binder system, which includes linear polymer and cross-linking polymer. The adhesion and heat tolerance are enhanced by the characteristic of the two type of polymers. The respective position of the two electrode layers are maintained during high operation temperature to improve the stability, and battery performance. Also, the ceramic separator enhances the ion conductivity and reduces the possibility of the micro-short to increase practical utilization.
US09570726B2	Base for lithium ion secondary battery separators, method for producing base for lithium ion secondary battery separators, and lithium ion secondary battery separator A base material for a lithium ion secondary battery separator provided by the present invention comprises a polyethylene terephthalate fiber, in which an average fiber diameter of the polyethylene terephthalate fiber is 9.0 μm or less, a specific X-ray diffraction intensity derived from the polyethylene terephthalate fiber is 300 cps/(g/m2) or more, and a coefficient of variation of a specific X-ray diffraction intensity is 12.0% or less, and is excellent in the workability during production and excellent in mechanical strength, uniformity and handling in a subsequent treatment step.
US09570724B2	Energy storage device to be mounted on a bicycle frame The object is providing an energy storage device that can be attached to the frame of the bicycle without the need for using tools. This device is, on the one hand, not in the way while the rider is operating the bicycle, and on the other hand, a suitable solution for easy retrofitting action of conventional bicycles. The energy storage device includes a housing that has disposed therein at least one electrical connection is available on the housing that is accessible from the outside. This connection serves, on the one hand, for connecting an electrical consumer, particularly an electrical drive, to the electrical energy storage element; on the other hand, this connection can preferably also serve for recharging the electrical energy storage element. The at least one electrical energy storage element is preferably a rechargeable accumulator.
US09570721B2	Battery module A battery module including: a plurality of battery cells arranged in a direction and each including a terminal portion on a first surface thereof; a pair of end plates each configured to face a wide surface of a battery cell at a respective outer end of the plurality of battery cells; side plates configured to support side surfaces of the battery cells at respective sides of the plurality of battery cells; and a cover configured to cover the first surfaces of the battery cells or second surfaces of the battery cells opposite the first surfaces, and a side plate of the side plates includes a bent portion that is bent to overlap with an end portion of the cover, and the cover is configured to press the bent portion.
US09570720B2	Rechargeable battery A rechargeable battery includes an electrode assembly; a case accommodating the electrode assembly; a cap plate coupled to an opening of the case; an electrode terminal connected to the electrode assembly and extending through a terminal hole of the cap plate; and a retainer having first ends contacting the case and located between the electrode assembly and the side wall to support the electrode assembly and the side wall, wherein a thickness of the retainer gradually decreases away from the first ends of the retainer.
US09570719B2	Secondary battery A secondary battery includes an electrode assembly; a case accommodating the electrode assembly; a cap plate sealing the electrode assembly within the case; a terminal plate on the cap plate and electrically connected to the electrode assembly; and an insulation member between and contacting the cap plate and the terminal plate, wherein the insulation member has a peripheral flange that extends away from the terminal plate.
US09570716B2	Deposition substrate transferring unit, organic layer deposition apparatus including the same, and method of manufacturing organic light-emitting display device by using the same A deposition substrate transferring unit that can deposit a deposition material at an exact location on a substrate, includes an electrostatic chuck that has a first surface to which a substrate is attached; and a carrier having a surface that combines with a second surface of the electrostatic chuck to move the electrostatic chuck in a first direction. The carrier includes accommodation parts disposed in empty space within the carrier, and supplementary ribs respectively formed on surfaces of the accommodation parts.
US09570713B2	Organic light emitting display device and method of manufacturing the same Disclosed is an organic light emitting display (OLED) device that may include first and second pixels on a substrate, each including a TFT region and a display region, the display region of each of the first and second pixels including a first electrode, an emission layer and a second electrode; a color filter layer in the display region of the second pixel; and a reflection preventing layer in the first and second pixels, substantially excluding the display region of the second pixel.
US09570711B2	Organic light emitting diode and manufacturing method therefor Disclosed are an organic light emitting diode and a method of manufacturing the same, the organic light emitting diode including: a light-transmitting substrate including a first region and a second region separated from the first region; a first lower electrode formed on the first region of the light-transmitting substrate and a second lower electrode formed on the second region thereof; a first organic thin film layer including a first emission material layer, formed on the first lower electrode of the first region, and a second organic thin film layer including a second emission material layer, formed on the second lower electrode of the second region; and a light-transmitting upper electrode formed on the first organic thin film layer and the second organic thin film layer and configured such that portions corresponding to the first region and the second region are connected to each other.
US09570707B2	Organic light emitting diode display and manufacturing method thereof An OLED display according to an exemplary embodiment includes: a substrate; an organic light emitting diode formed on the substrate; an overcoat covering the organic light emitting diode; and a patterned metal sheet attached on the overcoat and having a plurality of protrusion and depression portions. A plurality of protrusions may be formed in a bottom surface of the patterned metal sheet where the protrusion and depression portions of the patterned metal sheet and the overcoat face each other.
US09570705B2	Method of manufacturing organic electronic device Provided are a method of manufacturing an organic electronic device (OED), an OED manufactured thereby, and a use of the OED. During a process of manufacturing an OED, exposure of a pad region may be efficiently performed in a simple process, thereby preventing permeation of a contaminant, and an OED manufactured by the method and a use of the OED may be provided.
US09570701B2	Organic light emitting device Disclosed is an organic light emitting device which facilitates to realize a long lifespan and to satisfy a color region, wherein the organic light emitting device may include an organic emitting layer including red, green and blue emitting layers, the organic emitting layer provided between first and second electrodes; and a plurality of dopants included in at least any one of the red, green and blue emitting layers, wherein a maximum intrinsic luminescence wavelength of any one dopant among the plurality of dopants is different from a maximum intrinsic luminescence wavelength of another dopant among the plurality of dopants.
US09570692B2	Motherboard of flexible display panel and method for manufacturing flexible display panel A motherboard of flexible display panel and the method for manufacturing the flexible display panel are provided, the motherboard of flexible display panel includes a carrier substrate and at least one flexible display panel unit formed on the carrier substrate; the flexible display panel unit includes a liner layer, a flexible substrate and a display element; the liner layer includes a first zone and a second zone, the liner layer of the first zone has a laser absorptivity lower than that of the liner layer of the second zone, and the liner layer of the second zone has a critical energy no larger than that of the liner layer of the first zone; the first zone is located at the edge region of the flexible display panel unit.
US09570691B2	Ambient temperature liquid-form organic materials and use thereof An organic material consisting of a π-conjugated molecule which is in a liquid form at ambient temperature and use thereof are provided. The ambient temperature liquid-form organic material according to the present invention consists of a π-conjugated molecule having 2 or more side chains, the 2 or more side chains are same or different side chains selected from the group consisting of a branched alkyl chain, an alkyl chain having a polymerization site at a terminal, an oligosiloxane chain, a fluorocarbon chain, an oligoethylene glycol chain and derivatives thereof, and each of the 2 or more side chains is bound directly or via a substituent to the π-conjugated molecule.
US09570690B2	Heterocyclic compound Provided is a novel heterocyclic compound which can be used for a light-emitting element, as a host material of a light-emitting layer in which a light-emitting substance is dispersed. A heterocyclic compound represented by a general formula (G1) is provided. In the formula, A represents any of a substituted or unsubstituted dibenzothiophenyl group, a substituted or unsubstituted dibenzofuranyl group, and a substituted or unsubstituted carbazolyl group, R11 to R19 separately represent any of hydrogen, an alkyl group having 1 to 4 carbon atoms, and a substituted or unsubstituted aryl group having 6 to 13 carbon atoms, and Ar represents a substituted or unsubstituted arylene group having 6 to 13 carbon atoms.
US09570689B2	Compound for organic electric element, organic electric element comprising the same and electronic device thereof Provided herein are a compound of Formula 1, and an organic electric element comprised of a first electrode, a second electrode, and an organic material layer between the first electrode and the second electrode containing a compound of Formula 1, which has an improvement in driving voltage, luminous efficiency, color purity, stability, and life span.
US09570683B1	Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.
US09570682B2	Semiconductor memory device and method of manufacturing the same Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element.
US09570681B2	Resistive random access memory A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
US09570677B2	Memory cells, integrated devices, and methods of forming memory cells Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.
US09570674B2	Magnetic device A magnetic device includes a free layer including a first magnetization layer; a pinned layer including a second magnetization layer; and a tunnel barrier layer provided between the free layer and the pinned layer. At least one selected from the free layer and the pinned layer includes a synthetic antiferromagnetic (SAF) structure formed of a first ferromagnetic layer, a second ferromagnetic layer, and a ruthenium-rhodium (Ru—Rh) alloy layer provided between the first and second ferromagnetic layers.
US09570673B2	Method and processing apparatus for fabricating a magnetic resistive random access memory device Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.
US09570670B2	Magnetic device and method of fabricating the same Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure.
US09570662B2	Method of encapsulating an optoelectronic device and light-emitting diode chip A method of encapsulating an optoelectronic device includes providing a surface intended to be encapsulated, the surface containing platinum, generating reactive oxygen groups and/or reactive hydroxyl groups on the surface, and depositing a passivation layer by atomic layer deposition on the surface.
US09570661B2	Protective coating for LED lamp The present disclosure discloses a method for providing protective coatings onto one or more surfaces of a frangible enclosure of an LED lamp and a lamp prepared therefrom. More particularly, the present disclosure relates to LED lamps comprising polymer coatings on at least one or more surfaces of an enclosure of an LED lamps.
US09570660B2	Semiconductor light emitting device and semiconductor light emitting apparatus having the same Provided is a semiconductor light emitting device. The semiconductor light emitting device may include: a light emitting structure comprising a first conductivity-type semiconductor layer having an upper surface divided into first and second regions, an active layer and a second conductivity-type semiconductor layer sequentially disposed on the second region of the first conductivity-type semiconductor layer; a first contact electrode disposed on the first region of the first conductivity-type semiconductor layer; a second contact electrode disposed on the second conductivity-type semiconductor layer; a first electrode pad electrically connected to the first contact electrode and having at least a portion disposed on the second contact electrode; a second electrode pad electrically connected to the second contact electrode; and a multilayer reflective structure interposed between the first electrode pad and the second contact electrode and comprising a plurality of dielectric layers which have different refractive indices and are alternately stacked.
US09570654B2	Nitride light emitting diode and fabrication method thereof A nitride light-emitting diode including: a substrate with sub-micro patterns over the surface, which is divided into a growth region and a non-growth region; a growth blocking layer, formed in the non-growth region of the substrate for blocking epitaxial growth in the non-growth region of the substrate; a light-emitting epitaxial layer, comprising an n-type layer, a light-emitting layer and a p-type layer, formed in the growth region of the substrate, which extends to the non-growth region through lateral epitaxy and covers the growth blocking layer; wherein, the refractive index of the growth blocking layer is less than that of the light-emitting epitaxial layer and the growth blocking layer forms undulating morphology along the sub-micro patterns of the substrate, thus increasing light extraction interface of LED, generating refractive index difference between the light-emitting epitaxial layer and the light extraction interface and improving light extraction efficiency.
US09570652B2	Light emitting diodes An LED is provided. The LED includes at least two light emitting units located on a same plane. Each light emitting unit includes a first semiconductor layer, an active layer and a second semiconductor layer stacked in that order. Each light emitting unit further includes a first electrode and a second electrode electrically connected with the first semiconductor layer and the second semiconductor layer respectively. The active layer of each light emitting unit is spaced from the active layers of other light emitting units. A distance between adjacent active layer ranges from 1 micron to 1 millimeter.
US09570649B2	Methods for fabricating a plurality of optoelectronic devices from a wafer that includes a plurality of light detector sensor areas Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint.
US09570647B2	Avalanche photodiode detector An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region.
US09570646B2	Nano avalanche photodiode architecture for photon detection An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
US09570642B2	Sealing material sheet for solar cell modules Provided is a sealing material sheet for solar cell modules, which is obtained by irradiating a polyethylene resin with ionizing radiation and has high transparency, heat resistance and adhesion at the same time. This sealing material sheet for solar cell modules contains a low density polyethylene having a density of 0.900 g/cm3 or less, while having a gel fraction of from 0% to 40% (inclusive) and a degree of dispersity (Mw/Mn), which is the ratio of the weight average molecular weight (Mw) to the number average molecular weight (Mn) in terms of polystyrene, of from 2.5 to 3.5 (inclusive).
US09570641B2	Polymer and solar cell encapsulant using the polymer Provided is a polymer from which an encapsulant excellent in weather resistance and processability can be obtained when being used for an encapsulant for a solar cell. The polymer that has a main chain comprising repeating units represented by formula (1) and repeating units represented by formula (2) and satisfies requirements (a1), (a2), and (a3), (a1): the ratio of the number of the repeating units represented by formula (2) to the total number of the carbon atoms that constitute the main chain of the polymer is from 3.8% to 7.5%; (a2): the ratio X represented by formula (3) is from 82% to 100%; X=100×A/B (3) (a3): the polymer has a melting point of 42° C. to 90° C. as measured with a differential scanning calorimeter.
US09570637B2	Solar cell and manufacturing method of the same A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer. The first transparent electrode layer is separated into a primary electrode layer that is on the first semiconductor layer and a separated electrode layer that is on the second semiconductor layer in the region.
US09570636B2	Solar cell and method of fabricating the same Disclosed are a solar cell and a method of fabricating the same. The solar cell includes a molybdenum layer on a support substrate; an ohmic layer on the molybdenum layer; a light absorbing layer on the ohmic layer; and a front electrode layer on the light absorbing layer, wherein the ohmic layer comprises a first ohmic layer and a second ohmic layer having crystal structures different from each other.
US09570634B2	Sensor package with exposed sensor array and method of making same A packaged sensor assembly and method of forming that includes a first substrate having opposing first and second surfaces and a plurality of conductive elements each extending between the first and second surfaces. A second substrate comprises opposing front and back surfaces, one or more detectors formed on or in the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the one or more detectors. A third substrate is mounted to the front surface to define a cavity between the third substrate and the front surface, wherein the third substrate includes a first opening extending from the cavity through the third substrate. The back surface is mounted to the first surface. A plurality of wires each extend between and electrically connecting one of the contact pads and one of the conductive elements.
US09570632B2	Method of manufacturing the optical apparatus A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.
US09570629B2	Thin film transistor, array substrate and method of fabricating the same, and display device The embodiments of the present invention provide a thin film transistor including a gate, an upper active layer, a lower active layer, an upper source, a lower source, an upper drain and a lower drain. The upper active layer and the lower active layer are disposed at an upper side and a lower side of the gate, respectively, the lower source and the lower drain are connected to the lower active layer, respectively, and the upper source and the upper drain are connected to the upper active layer, respectively. The embodiments of the present invention also provide an array substrate including the thin film transistor, a method of fabricating the array substrate, and a display device including the array substrate.
US09570621B2	Display substrate, method of manufacturing the same The present invention discloses a thin film transistor (TFT), a method for manufacturing the TFT, and a display substrate using the TFT that may prevent degradation of the characteristics of an oxide semiconductor contained in the TFT by blocking external light from entering a channel region of the oxide semiconductor. The TFT includes an oxide semiconductor layer; a protective layer overlapping a channel region of the oxide semiconductor layer; an opaque layer disposed between the oxide semiconductor layer and the protective layer; a source electrode contacting a first side of the oxide semiconductor layer; a drain electrode contacting a second side of the oxide semiconductor layer and facing the source electrode across the channel region; a gate electrode to apply an electric field to the oxide semiconductor layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer.
US09570617B2	TFT substrate structure and manufacturing method thereof The present invention provides a TFT substrate structure and a manufacturing method thereof. A metal oxide semiconductor layer is formed on an amorphous silicon layer to replace an N-type heavily-doped layer. The potential barrier between the amorphous silicon layer and metal layer is relatively low, making it possible to form an ohmic contact and thus increasing current efficiency, without the need of doping other ions to form the N-type heavily-doped layer. Further, the metal oxide semiconductor layer comprises numerous defects that trap holes so that during the operation of the TFT, even a great negative voltage is applied to the gate terminal to thus form a hole conducting channel, the holes may hardly move from the source/drain terminals through the metal oxide semiconductor layer and the semiconductor layer to reach the conducting channel and consequently, the current leakage issue occurring in a hole conducting zone of a conventional TFT substrate structure can be improved and severe bending of the hole current curve and poor reliability are also improved.
US09570615B2	Gate stack and contact structure A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.
US09570612B2	Method and structure for straining carrier channel in vertical gate all-around device Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (140); a drain region (190) aligned substantially vertically to the source region; a channel structure (160) bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure (170) arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels (161) extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor (240) interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.
US09570606B2	FinFET LDMOS device and manufacturing methods An LDMOS (Laterally-Diffused Metal Oxide Semiconductor) device has a substrate, which includes a first doped region, a second doped region, and a shallow trench isolation (STI) region disposed in the second doped region. The first doped region and the second doped region are adjacent and have different conductivity types. The device also has a gate structure disposed on the substrate; the gate structure substantially does not overlap the second doped region.
US09570605B1	Semiconductor device having a plurality of source lines being laid in both X and Y directions A device is disclosed. The device includes a semiconductor substrate, a plurality of source lines formed on a surface of the semiconductor substrate. The plurality of source lines are laid in both X and Y directions. The device further includes a plurality of gate lines laid out over source lines in X direction in the plurality of source lines, a source contact line that connects source lines in the plurality of source lines that are terminating in Y direction, a gate contact line that connects the plurality of gate lines and a drain contact.
US09570604B2	Semiconductor device A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 Å or smaller. The interface between the source electrode and the source region is silicidized.
US09570603B2	Semiconductor device having trench gate structure and method for manufacturing the semiconductor device A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.
US09570602B2	Manufacturing method of semiconductor device and semiconductor device The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.
US09570601B2	Semiconductor device and method of manufacturing the same Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.
US09570595B2	Transistor and method of making A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
US09570592B2	Method of forming split gate memory cells with 5 volt logic devices A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.
US09570590B1	Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs A method is provided for forming an integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs. Initially, a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge) is formed. The SiGe layer is recessed to form a recessed SiGe layer in the n-type region while leaving an intact SiGe layer in the p-region. A Si layer consisting essentially of Si is formed on the recessed SiGe layer. The Si layer and recessed SiGe layer are patterned to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion. The intact SiGe layer in the p-region is patterned to form an intact SiGe fin. The recessed SiGe fin portion in the n-region is selectively oxidized utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.
US09570589B2	FINFET semiconductor device and fabrication method FinFET semiconductor devices and fabrication methods are provided. Discrete fins are formed on a substrate. An insulation layer is formed on the substrate between the discrete fins, the insulation layer having a top surface lower than a top surface of the fin and covering a portion of a sidewall surface of the fin. A sidewall spacer is formed covering the sidewall surface of the fin and exposing the top surface of the fin. A top portion of the fin is selectively nitrided to convert a thickness portion of the fin into a semiconductor nitride layer on a remainder fin. The semiconductor nitride layer is removed to form an opening on the remainder fin and between adjacent sidewall spacers. A stress layer is formed to fill the opening.
US09570587B2	Dislocation stress memorization technique for FinFET device A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.
US09570577B2	Semiconductor device and insulated gate bipolar transistor with source zones formed in semiconductor mesas A semiconductor device includes a semiconductor mesa that includes at least one body zone forming first pn junctions with source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa. At least one of the electrode structures includes a gate electrode configured to control a charge carrier flow through the at least one body zone. In a separation region between the source zones, which are arranged along an extension direction of the semiconductor mesa, the semiconductor mesa includes at least one partial or complete constriction.
US09570574B1	Recessed metal liner contact with copper fill A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a sidewall of a trench formed above the source or drain region, depositing a second liner conformally over the first liner, and stripping the first liner and the second liner from a portion of the sidewall from an opening of the trench to a height above the bottom of the trench. The method also includes depositing a third liner conformally over the second liner on the bottom and to the height above the bottom of the trench and on the portion of the sidewall, and depositing a metal fill to fill the trench.
US09570572B2	Multiple layer interface formation for semiconductor structure There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.
US09570571B1	Gate stack integrated metal resistors Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.
US09570570B2	Enhanced gate dielectric for a field effect device with a trenched gate The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.
US09570563B2	III-V compound and Germanium compound nanowire suspension with Germanium-containing release layer A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of source/drain component(s) defining a pFET (p-type field-effect transistor) region; a first suspended nanowire, at least partially suspended over the substrate layer in the nFET region and made from III-V material; and a second suspended nanowire, at least partially suspended over the substrate layer in the pFET region and made from Germanium-containing material. In some embodiments, the first suspended nanowire and the second suspended nanowire are fabricated by adding appropriate nanowire layers on top of a Germanium-containing release layer, and then removing the Germanium-containing release layers so that the nanowires are suspended.
US09570561B2	Modified channel position to suppress hot carrier injection in FinFETs Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.
US09570560B2	Diffused junction termination structures for silicon carbide devices An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm−2.
US09570555B1	Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
US09570554B2	Robust gate spacer for semiconductor devices After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process.
US09570552B1	Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer.
US09570546B2	Bipolar transistor A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.
US09570545B2	High voltage trench transistor A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
US09570544B2	Semiconductor device A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer. Respective concentrations of the first conductivity type impurities contained in the first polysilicon and in the diffusion layer are kept constant in a direction from the low-concentration layer to the high-concentration layer.
US09570543B2	Semiconductor device A semiconductor substrate has an element portion and a termination portion located on an outer side of the element portion. A first electrode layer is provided on a first surface of the semiconductor substrate. A second electrode layer is provided on a second surface of the semiconductor substrate in an upper portion of the element portion. An interlayer insulation film is provided on the second surface of the semiconductor substrate. The interlayer insulation film has: an element insulation portion that provides insulation between a part of the element portion of the semiconductor substrate and the second electrode layer; and a termination insulation portion covering a termination portion of the semiconductor substrate. The termination insulation portion includes a high dielectric constant film that is higher in dielectric constant than the element insulation portion.
US09570540B2	Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of \|d1−d2\|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 μm and the plane spacing d2 at the X-ray penetration depth of 5 μm is equal to or lower than 2.1×10−3. The above configuration provides the nitride crystal having a crystal surface layer that is evaluated directly and reliably without breaking the crystal so that it can be used in a preferred fashion as a substrate for a semiconductor device as well as the nitride crystal substrate, an epilayer-containing nitride crystal substrate, a semiconductor device and a method of manufacturing the same.
US09570537B2	Semiconductor device A semiconductor device has a field insulating film formed on a semiconductor substrate, a resistor and a fuse formed on the field insulating film, a first interlayer insulating film formed on the fuse, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film including an SOG layer and formed on the second interlayer insulating film. A passivation oxide film is formed on the third interlayer insulating film. A fuse opening is formed above the fuse and extends from the passivation oxide film to a midpoint in the second interlayer insulating film. A passivation nitride film covers the passivation oxide film and is disposed on a side surface and a bottom surface of the fuse opening. The passivation nitride film disposed on the bottom surface of the fuse opening has an opening exposing the second interlayer insulating film at the midpoint thereof.
US09570529B2	Organic light emitting diode display An organic light emitting diode (OLED) display including a display substrate; a sealing member facing the display substrate; a sealant between the display substrate and the sealing member, the sealant cohering the display substrate and the sealing member; a plurality of conductive wires on the display substrate and overlapping the sealant; and a heat blocking film between the conductive wire and the sealant, the heat blocking film including a plurality of sub-heat blocking films.
US09570526B2	Organic light emitting display device and manufacturing method thereof An organic light emitting display device and a method for manufacturing the organic light emitting display device, which includes a light emitting region and a non-light emitting region, and having an organic light emitting element including first and second electrodes disposed in the light emitting region and an organic emission layer formed between the two electrodes, a driving voltage supply line disposed in the non-light emitting region and providing a driving voltage to the first and second electrodes, and a contact part disposed in the non-light emitting region and disposed to be in contact with the first electrode to supply the driving voltage provided from the driving voltage supply line to the first electrode, wherein the contact part is formed as multiple layers patterned such that a second conductive layer covers a first conductive layer.
US09570521B2	Bidirectional display device A display device includes: a first display panel and a second display panel disposed to face each other; a backlight unit interposed between the first display panel and the second display panel; and a speaker unit including a first piezoelectric module and a second piezoelectric module sharing an enclosure and disposed to face each other, a first output unit configured to output sound produced from the first piezoelectric module, and a second output unit configured to output sound produced from the second piezoelectric module.
US09570518B2	Light emitting element A light emitting element is provided, including a first electrode layer, a second electrode layer, and an organic light emitting layer sandwiched between the first electrode layer and the second electrode layer. The organic light emitting layer is patterned to include a plurality of light emitting blocks with different densities. In an embodiment, the light emitting blocks are divided into a plurality of light emitting block groups that are arranged in an alternate manner. In another embodiment, a light emitting element includes a first electrode layer, a first organic light emitting layer, a charge generating layer, a second organic light emitting layer, and a second electrode layer sequentially stacked on one another. The first and second organic light emitting layer are patterned to form a plurality of first and second light emitting blocks with different densities, respectively. Thus, the light emitting element generates full-color, gray-scale, three-dimensional, or dynamic images.
US09570514B2	Semiconductor device According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.
US09570513B2	Vertical bipolar transistor The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
US09570511B2	Electronic device having buried gate and method for fabricating the same Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.
US09570508B2	Photoelectric conversion device and operation method for photoelectric conversion device A photoelectric conversion unit generates an amount of charges. A differential amplifier has first and second input transistors and is configured to output a current signal based on the amount of charges. A reset voltage providing unit is configured to provide a reset voltage for input nodes of the first and second input transistors. A transfer transistor is electrically connected to, and configured to transfer a charge to, the input node of the first input transistor. A reset transistor is electrically connected to one of the input nodes, and configured to control an electrical connection between the reset voltage providing unit and the input node connected to the reset transistor. A connection transistor has first and second nodes and is configured to control an electrical connection between the input nodes. The first and second nodes are connected to the input nodes of the first and second input transistors, respectively.
US09570507B2	Entrenched transfer gate An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node.
US09570505B2	Image sensors and methods of manufacturing the same In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.
US09570500B2	Solid-state imaging device, method of manufacturing the same, and electronic apparatus A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.
US09570499B2	Semiconductor device, solid-state imaging device and electronic apparatus A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
US09570493B2	Dielectric grid bottom profile for light focusing A back side illumination (BSI) image sensor with a dielectric grid opening having a curved lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the curved lower surface of the dielectric grid opening. A method for manufacturing the BSI image sensor is also provided.
US09570483B2	Flat panel display device with oxide thin film transistor and method of fabricating the same A flat panel display device with an oxide thin film transistor is disclosed which includes: an oxide semiconductor layer which has a width of a first length and is formed on a buffer film; a gate insulation film which has a width of a second length and is formed on the oxide semiconductor layer; a gate electrode which has a width of a third length and is formed on the gate insulation film; an interlayer insulation film formed on the entire surface of the substrate provided with the gate electrode; source and drain electrodes formed on the interlayer insulation film and connected to the oxide semiconductor layer; a pixel electrode formed on a passivation film and connected to the drain electrode. The first length is larger than the second length and the second length is larger than the third length.
US09570480B2	Liquid crystal display and manufacturing method thereof A liquid crystal display includes a thin film transistor on a substrate, a pixel electrode connected to a first terminal of the thin film transistor, a roof layer above the pixel electrode, a microcavity between the pixel electrode and the roof layer, the microcavity including a liquid crystal injection hole, a partition wall in the microcavity, the partition wall partitioning the microcavity into a first area and a second area, and a liquid crystal layer with liquid crystal molecules in the microcavity, the liquid crystal molecules in the first area being a different type than the liquid crystal molecules in the second area.
US09570473B2	Array substrate, manufacturing method thereof and display device An array substrate, a manufacturing method thereof and a display device are disclosed. The manufacturing method of an array substrate including: forming patterns including a thin film transistor, a gate wiring and a data wiring on the base substrate; the gate wiring and the data wiring are located in a PAD area; forming patterns of an insulating spacing layer, a first transparent electrode and a passivation layer, and forming a first via hole and a second via hole in areas corresponding to the gate wiring and the data wiring respectively to expose the gate wiring and the data wiring; a thickness of the insulating spacing layer in the PAD area on the array substrate is less than that of the insulating spacing layer in other areas. Therefore, the connection electrode can make better contact with the corresponding signal lines to avoid abnormal rubbing mura.
US09570472B2	Array substrate and manufacturing method thereof, and liquid crystal display The disclosed technology relates to an array substrate and a method of manufacturing the same, and a liquid crystal display. The array substrate comprises a base substrate. The base substrate comprises a pixel region and a peripheral region; data lines and gate lines are formed to transversely and longitudinally cross each other on the base substrate to form a plurality of pixel units, and each of the pixel units comprises a switching element, a pixel electrode and a common electrode above the pixel electrode; the common electrode has slits in each pixel unit and is a plate-shaped electrode in the pixel region, when powered on, the common electrode forms a horizontal electric field together with the pixel electrode of the pixel unit; and a common electrode line fouled in the pixel region and connected with the common electrode.
US09570465B2	Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.
US09570452B2	Flash memory A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance.
US09570449B2	Metal strap for DRAM/FinFET combination A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.
US09570447B2	Semiconductor device and production method therefor One semiconductor device includes first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction, a first semiconductor pillar positioned between the first and second trenches, a second semiconductor pillar positioned between the second and third trenches, a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor, and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The second gate electrode is shared by the first vertical transistor and the second vertical transistor.
US09570446B1	Semiconductor device A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.
US09570445B2	Semiconductor device A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
US09570442B1	Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.
US09570434B2	Semiconductor device and fabricating method thereof Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.
US09570428B1	Tiled hybrid array and method of forming A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ≦10 μm. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.
US09570427B2	Method for integrating a light emitting device Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.
US09570420B2	Wireless communicating among vertically arranged integrated circuits (ICs) in a semiconductor package Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.
US09570419B2	Method of thinning and packaging a semiconductor chip A semiconductor wafer and a plurality of semiconductor dies are provided. The wafer and the dies each include first electrically conductive terminals arranged on a main surface. The wafer is permanently attached to each of the semiconductor dies such that the first terminals are electrically connected to one another. At least one of the wafer and the semiconductor dies is thinned. The wafer is diced so as to form a plurality of chip-stacks, each of the chip-stacks comprising one of the semiconductor dies permanently attached to a diced wafer chip. At least one of the first terminals in the chip-stack is accessible by a second electrically conductive terminal arranged on a rear surface and electrically connected to the first terminal by an electrical connector that is internal to a semiconductor body of either the semiconductor die or the diced wafer chip of the chip-stack.
US09570407B2	Method for manufacturing semiconductor device and semiconductor device A method for manufacturing a semiconductor device includes: a fixing step in which semiconductor chips are mounted on and fixed to predetermined positions on an upper surface of a single starting substrate to form individual substrates; a connection step in which electrodes of the semiconductor chips and of the starting substrate are connected by wires; a sealing step in which on the upper surface of the starting substrate, the resin is potted among the semiconductor chips to seal an entire lateral circumference of each of the semiconductor chip; a bonding step in which a single starting protective cover to form individual protective covers is bonded to a surface of the resin so as to extend the semiconductor chips; and a cutting step in which an assembly of the semiconductor devices formed by bonding the starting protective cover to the starting substrate via the resin is cut to the semiconductor devices.
US09570396B2	Method of forming a damascene interconnect on a barrier layer A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer.
US09570394B1	Formation of IC structure with pair of unitary metal fins Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.
US09570393B2	Nonvolatile memory device and method for fabricating the same A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.
US09570388B2	FinFET power supply decoupling Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).
US09570385B2	Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
US09570383B2	Semiconductor package, module substrate and semiconductor package module having the same Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.
US09570380B2	Electronic device provided with an encapsulation structure with improved electric accessibility and method of manufacturing the electronic device An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which surrounds laterally and at the top the semiconductor die and, at least in part, the leadframe structure, defining a top surface, a bottom surface, and a thickness of the electronic device; and a conductive lead electrically coupled to the semiconductor die. The conductive lead is modelled in such a way as to extend throughout the thickness of the protection body for forming a front electrical contact accessible from the top surface of the electronic device, and a rear electrical contact accessible from the bottom surface of the electronic device.
US09570367B2	Ultra fine pitch PoP coreless package A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.
US09570364B2	Method of detecting focus shift in lithography process, method of analyzing error of transferred pattern using the same and method of manufacturing semiconductor device using the methods A method of detecting focus shift in a lithography process, a method of analyzing an error of a transferred pattern using the same, and a method of manufacturing a semiconductor device using the methods are provided. The focus shift detecting method of a lithography process comprises generating a first contour band of a mask pattern between a first focus and a second focus, generating a second contour of the mask pattern between the first focus and a third focus, and determining whether focus shift of the mask pattern occurs using an intersection of the first contour band and the second contour band.
US09570362B2	Method for manufacturing semiconductor device and semiconductor device A method for manufacturing a semiconductor device including a MOS transistor comprising forming a gate electrode on a first insulating film formed on a substrate, performing ion implantation into the substrate and forming a diffusion region, and forming a second insulating film on the substrate, in that order. The performing ion implantation comprises forming a first resist pattern, performing the ion implantation using the first resist pattern as a mask and removing the first resist pattern, including removing, by asking, a part of the first resist pattern hardened by the ion implantation and then removing the remaining part. In forming the gate electrode, a gate electrode material layer is patterned and a protective film is formed.
US09570361B1	Method of fabricating a semiconductor device including high-K metal gate having reduced threshold voltage variation A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer deposited in a gate trench and on a semiconductor portion of the substrate. At least one workfunction layer has an arrangement of first and second workfunction granular portions on an upper surface of the high-k layer to define a workfunction of the semiconductor device. The arrangement of first and second workfunction granular portions define a granularity of the at least one workfunction layer. A gate contact material fills the gate trench, wherein the high-k layer has a concentration of oxygen vacancies based on the granularity of the at least one work function metal layer so as to reduce the variation in the threshold voltage.
US09570359B2	Substrate structure, complementary metal oxide semiconductor device, and method of manufacturing complementary metal oxide semiconductor device A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.
US09570356B1	Multiple gate length vertical field-effect-transistors Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
US09570354B2	Asymmetric high-K dielectric for reducing gate induced drain leakage An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
US09570353B1	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.
US09570352B2	Method of dicing a wafer and semiconductor chip A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.
US09570351B2	Reusable semiconductor substrates In example implementations, a plurality of material layers and a plurality of etch stop layers are grown on a first substrate. Ions are implanted through at least one material layer of the plurality of material layers into an etch stop layer of the plurality of etch stop layers to create defects in the etch stop layer. A first material layer of the substrate is bonded to a second substrate. The etch stop layer is split to remove the first substrate from the second substrate. The first substrate is reused to bond another material layer of the plurality of material layers to a third substrate.
US09570350B2	Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.
US09570346B2	Method of manufacturing semiconductor device A barrier metal is formed from a surface of an interlayer insulating film 2 to a trench that is formed in a semiconductor portion exposed in a contact hole. After RTA treatment and a plasma nitriding process, a plug is embedded at an inner side of the barrier metal inside the trench and the contact hole. The RTA treatment is performed at a temperature range of about 500 degrees C. to 650 degrees C. The plasma nitriding process is performed at a temperature lower than that of the RTA treatment. The barrier metal is formed by a first metal film of titanium and a second metal film of titanium nitride sequentially stacked. The plug is formed from tungsten. A surface electrode formed of aluminum is formed from a surface of the second metal film on the interlayer insulating film to a surface of the plug.
US09570340B2	Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride The invention provides a method of etching a crystalline semiconductor material (114), the method being characterized in that it comprises: at least one ion implantation performed by implanting a plurality of ions (121) in at least one volume (113) of the semiconductor material (114) in such a manner as to make the semiconductor material amorphous in the at least one implanted volume (113), and as to keep the semiconductor material (114) in a crystalline state outside (112) the at least one implanted volume (113); and at least one chemical etching for selectively etching the amorphous semiconductor material relative to the crystalline semiconductor material, so as to remove the semiconductor material in the at least one volume (113) and so as to keep the semiconductor material outside (112) the at least one volume (113).
US09570339B2	Semiconductor structure and process thereof A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are etched to form a trench in the sacrificial layer and the substrate. A first isolation material fills the trench, thereby a first isolation structure being formed. The sacrificial layer is patterned to form a plurality of sacrificial patterns. A plurality of spacers are formed beside the sacrificial patterns respectively. The sacrificial patterns are removed. Layouts of the spacers are transferred into the substrate, so that a plurality of fin structures are formed in the substrate. The spacers are then removed. The present invention also provides a semiconductor structure formed by said semiconductor process.
US09570334B2	Method and system for positioning wafer in semiconductor manufacturing fabrication A method for positioning a wafer in semiconductor fabrication is provided. The method includes sending a wafer into a processing chamber by a transferring module. The method further includes producing a video image in relation to an edge of the wafer by a monitoring module. The method also includes performing an image analysis on the video image to determine if the edge of the wafer is in a correct position. If the edge of the wafer is not in a correct position a shifting value is calculated and the wafer is moved according to the shifting value.
US09570333B2	Substrate treating apparatus A substrate treating apparatus includes a pod storage unit 9 between a substrate treating unit 11 and a pod storage and transport unit 7, with a transport robot 19 transporting FOUPs 3 between a load port 5 and a rack array 33. A transport robot 31 transports the FOUPs 3 between the rack array 33, a rack array 69 and a receiver 27. The transportation between the load port 5 and rack array 33 and the transportation between the rack array 69, rack array 33 and receiver 27 can be carried out substantially in parallel. As a result, the efficiency of transporting the FOUPs 3 can be improved to improve throughput. Moreover, an increase in apparatus size can be inhibited since only the pod storage unit 9 is disposed between the pod storage and transport unit 7 and substrate treating unit 11. The capacity for storing the FOUPs 3 can be increased to make effective use of the high throughput of the apparatus.
US09570331B2	Wafer cassette with electrostatic carrier charging scheme A wafer cassette includes a main body having space to hold at least one wafer assembly. Each of the at least one wafer assembly includes a wafer and an electrostatic carrier attached to the wafer. An electrical contact structure inside the main body is arranged to contact an electrical pad of the electrostatic carrier.
US09570330B2	Substrate processing apparatus A substrate processing apparatus is presented having a transport chamber defining substantially linear substrate transport paths, a linear array of substrate holding modules, each communicably connected to the chamber. The substrate transport has at least one transporter capable of holding and moving the substrate on more than one substantially linear substrate transport paths. The transport chamber having different transport tubes at least one of which is sealable at both ends of the transport tube and configured to hold an isolated atmosphere different from that of the transport tubes, each of the different transport tubes having one of the substrate transport paths located therein different from another of the transport paths located in another of the transport tubes, and being communicably connected to each other, where at least one of the transport tubes is configured to provide uninterrupted transit of the substrate transport through the transport tubes.
US09570328B2	Substrate support for use with multi-zonal heating sources Apparatus for use with multi-zonal heating sources are provided. In some embodiments, a substrate support may have a pocket disposed in a surface of the substrate support and a lip disposed about the pocket to receive an edge of a substrate and to support the substrate over the pocket such that a gap is defined between a pocket surface and a backside surface of the substrate when the substrate is disposed on the lip; a plurality of features to operate in combination with a plurality of heating zones provided by a multi-zonal heating source to provide a desired temperature profile on a frontside surface of a substrate when the substrate is disposed on the lip, and wherein the plurality of features are alternatingly disposed above and below a baseline surface profile of the pocket surface in a radial direction from a central axis of the substrate support.
US09570326B2	Substrate cleaning method, substrate cleaning apparatus, and computer-readable storage medium A substrate cleaning method includes: a first step in which a cleaning liquid is ejected from a nozzle N2 to a central portion of a wafer W; a second step in which a dry gas is ejected from a nozzle N3 to the central portion of the wafer W to form a dry area; a third step in which the cleaning liquid is ejected from the nozzle N2 while the nozzle N2 is moved from a central side of the wafer W to a peripheral side thereof; a fourth step in which a width of an intermediate area generated between a wet area and the dry area is acquired; and a fifth step in which, when the width of the intermediate area exceeds a predetermined threshold value, a process parameter is changed such that the width of the intermediate area becomes the threshold value or less.
US09570324B2	Method of manufacturing package system A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.
US09570323B2	Semiconductor device leadframe For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
US09570318B1	High-k and p-type work function metal first fabrication process having improved annealing process flows Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.
US09570315B2	Method of interfacial oxide layer formation in semiconductor device A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).
US09570313B2	Method for etching high-K dielectric using pulsed bias power A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).
US09570310B2	Method for manufacturing semiconductor device The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.
US09570301B2	Projection patterning with exposure mask A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.
US09570299B1	Formation of SiGe nanotubes Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.
US09570294B2	Preparation method of graphene nanoribbon on h-BN A preparation method of a graphene nanoribbon on h-BN, comprising: 1) forming a h-BN groove template with a nano ribbon-shaped groove structure on the h-BN by adopting a metal catalysis etching method; 2) growing a graphene nanoribbon in the h-BN groove template by adopting a chemical vapor deposition method. In the present invention, a CVD method is adopted to directly prepare a morphology controllable graphene nanoribbon on the h-BN, which helps to solve the long-term critical problem that the graphene is difficult to nucleate and grow on an insulating substrate, and to avoid the series of problems introduced by the complicated processes of the transferring of the graphene and the subsequent clipping manufacturing for a nanoribbon and the like.
US09570286B2	Supercritical drying method for semiconductor substrate According to one embodiment, a supercritical drying method for a semiconductor substrate comprises introducing a semiconductor substrate, a surface of the semiconductor substrate being wet with a water-soluble organic solvent, to the inside of a chamber, hermetically sealing the chamber and increasing a temperature inside the chamber to not lower than a critical temperature of the water-soluble organic solvent, thereby bringing the water-soluble organic solvent into a supercritical state, decreasing a pressure inside the chamber and changing the water-soluble organic solvent in the supercritical state to a gas, thereby discharging the water-soluble organic solvent from the chamber, starting a supply of an inert gas into the chamber as the pressure inside the chamber decreases to atmospheric pressure, and cooling the semiconductor substrate in a state where the inert gas exists inside the chamber.
US09570285B2	Cleaning composition and methods thereof Provided is a cleaning solution and its applications. The cleaning solution comprises a mixture of a basic chemical compound and a solvent solution. In some embodiments, the basic chemical compound is tetramethylammonium hydroxide (TMAH) and the solvent solution includes a solution of water and at least one of propylene glycol ethyl ether (PGEE), propylene glycol monomethylether (PGME), and propylene glycol monomethylether acetate (PGMEA). The cleaning solution is effective in removing silicon-containing material off a surface of a system or a surface of a semiconductor substrate. In some embodiments, the system comprises a pipeline for delivering the silicon-containing material in semiconductor spin-coating processes. In some embodiments, the system comprises a drain for collecting waste fluid in semiconductor spin-coating processes. In some embodiments, the silicon-containing material has a first pH value, the cleaning solution has a second pH value, and the silicon-containing material is unstable at the second pH value.
US09570284B1	Method and system for controlling a semiconductor fabrication process A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.
US09570278B2	Coupling device for mass spectrometry apparatus An object of the present invention is to provide a technology that enables highly sensitive atmospheric-pressure real-time mass spectrometry of a volatile substance. The present invention provides a coupling device for a mass spectrometry apparatus that is an interface member to be connected to an atmospheric-pressure real-time mass spectrometry apparatus, the coupling device including (A) an excitation gas introducing port, a sample gas introducing port, and an ionized sample gas discharging port, (B) a channel through which the excitation gas introducing port and the ionized sample gas discharging port are in communication, and (C) a space for mixing excitation gas and sample gas being formed in a region of a portion of the channel recited in (B), by the coupling device having a structure in which the sample gas introducing port and the channel recited in (B) are in communication.
US09570271B2	Boron-containing dopant compositions, systems and methods of use thereof for improving ion beam current and performance during boron ion implantation A novel composition, system and method thereof for improving beam current during boron ion implantation are provided. The boron ion implant process involves utilizing B2H6, BF3 and H2 at specific ranges of concentrations. The B2H6 is selected to have an ionization cross-section higher than that of the BF3 at an operating arc voltage of an ion source utilized during generation and implantation of active hydrogen ions species. The hydrogen allows higher levels of B2H6 to be introduced into the BF3 without reduction in F ion scavenging. The active boron ions produce an improved beam current characterized by maintaining or increasing the beam current level without incurring degradation of the ion source when compared to a beam current generated from conventional boron precursor materials.
US09570268B2	Electron gun, charged particle gun, and charged particle beam apparatus using electron gun and charged particle gun The purpose of the present invention is to provide a charged particle gun using merely an electrostatic lens, said charged particle gun being relatively small and having less aberration, and to provide a field emission-type charged particle gun having high luminance even with a high current. This charged particle gun has: a charged particle source; an acceleration electrode that accelerates charged particles emitted from the charged particle source; a control electrode, which is disposed further toward the charged particle source side than the acceleration electrode, and which has a larger aperture diameter than the aperture diameter of the acceleration electrode; and a control unit that controls, on the basis of a potential applied to the acceleration electrode, a potential to be applied to the control electrode.
US09570264B2	X-ray generator and X-ray imaging apparatus Provided is an X-ray generator which includes:an electron path 8; a target 9c disposed on a substrate 9a, in which electrons having passed through the electron path 8 are made to emit at the target 9c and to generate an X-ray, wherein: the target 9c is disposed at the central area of the substrate 9a; at least a part of a peripheral area of the substrate 9a which is not covered with the target 9c has higher transmittance than that of the central area of the substrate 9a covered with the target 9c, with respect to the X-ray generated when electrons having reflected from the target enter an inner wall of the electron path. X-ray generation efficiency may be improved by effectively using electrons reflected off the target 9c.
US09570262B1	Apparatus and methods for a circuit breaker positive-off stop feature A circuit breaker having a positive-off stop feature includes an operating lever rotatably coupled to a side frame, a tension lever coupled to the side frame, and an upper toggle linkage and a stop link each rotatably coupled to the tension lever. The upper toggle linkage may be configured to rotate the stop link. The operating lever may be configured to move rotatably to and from an ON position and an OFF position provided the main contacts of the circuit breaker are not welded or otherwise stuck together. Should the main contacts become welded or otherwise stuck together, the upper toggle linkage may be configured to rotate the stop link to a position wherein the stop link may be configured to prevent the operating lever from moving into the OFF position. Methods of assembling a circuit breaker positive-off stop feature are also provided, as are other aspects.
US09570261B2	Electrical switching apparatus and secondary disconnect assembly with contact alignment features therefor A secondary disconnect assembly is for an electrical switching apparatus, such as a power circuit breaker. The secondary disconnect assembly includes a terminal block mount having a number of first mounting features, at least one terminal block, and at least one accessory plug. Each terminal block includes a number of receptacles and a number of second mounting features, which cooperate with the first mounting features to properly align, mount and stabilize the terminal block on the terminal block mount. Each accessory plug includes a number of contact alignment features structured to align and guide the accessory plug into a corresponding one of the receptacles.
US09570256B2	Gas circuit breaker A gas circuit breaker includes a hermetically-sealed container filled with an arc extinguishing gas, a fixed contact arranged within the container, a movable contact arranged to face the fixed contact and configured to move in an axial direction of the container, the movable contact capable of contacting or separating from the fixed contact, an insulating operation rod having one end connected to an end of the movable contact opposite to the fixed contact through a link at an angle of about 90 degrees with respect to the movable contact, and an actuator arranged in a substantially coaxial relationship with the insulating operation rod, the actuator including an output shaft transferring a driving force for the operation of the movable contact to the other end of the insulating operation rod.
US09570255B2	Electrical switching apparatus, and operating handle assembly and trip cam therefor A trip cam is for an operating handle assembly of an electrical switching apparatus. The electrical switching apparatus includes a housing and a number of poles. The operating handle assembly includes an operating handle partially extending into the housing and a cradle member cooperating with the operating handle. The trip cam includes: a mounting portion structured to be disposed in the housing, the mounting portion including a first region, a second region disposed generally opposite the first region, and a third region disposed generally between the first region and the second region; a transfer leg extending from the first region and being structured to cooperate with each of the number of poles; a driving leg extending from the third region and being structured to be driven by the cradle member; and an operating handle protrusion extending from the second region and being structured to engage the operating handle.
US09570254B2	Portable electronic user device A portable electronic user device, in the form of an electronic key, having an inherently rigid button for activation by a user. The portable electronic user device further has a flexibly deformable membrane including a first side having at least one support section on which the at least one button is supported via the plunger, and an actuating section, separate from the at least one support section, for receiving and forwarding an actuation of the button to an electrical switch element. There is a rigid frame which bears the membrane on a second side opposite the first side, wherein, in the assembled state, having the membrane in the region of the at least one support section, the frame has at least one breakout, via which the membrane is moveable by the plunger upon activating the at least one button and, in dependence on the size and/or the shape of the breakout, provides a force for resetting the button. As a result of the separation of the generating of the reset force on the support sections movable by the first breakouts and the switch function in the region of the activation section, there is great freedom in the design of the portable electronic user device, wherein reliable triggering of the switch element is always ensured.
US09570252B2	System and method for operating an on-load tap changer A system for operating an on-load tap changer (OLTC) includes a plurality of legs that include mechanical switches. At least one leg switches from a first to a second tap of the OLTC on receipt of a tap change signal. At least one mechanical switch is activated to establish an electrical connection between one of the first and the second tap and a power terminal of the OLTC. Further, the system includes semiconductor switches that are parallel to the mechanical switches and when activated electrically couple one of the first and the second tap and the power terminal. The system includes a processing unit that selectively activates and deactivates the mechanical and semiconductor switches in such a way that electrical contact is maintained between at least one of the taps and the power terminal during the transition of at least one leg from the first tap to the second tap.
US09570251B2	Electrical circuit breaker safety system A system is provided for preventing a push-pull circuit breaker from being inadvertently depressed. The system may include a clip member having a generally C-shaped collar defining a cylindrical recess therein. The clip member is configured to resiliently expand to be positioned over and receive a cylindrical portion of the circuit breaker knob in a manner that prevents the circuit breaker knob from being depressed to close the circuit breaker. The system further includes first and second tabs depending from ends of the clip member. A cable tie may be positioned through openings formed in the first and second tabs to secure the first and second ends to each other, thereby locking the clip member in position on the push-pull circuit breaker knob and preventing the circuit breaker knob from being depressed.
US09570249B1	Modular remote control mount Apparatus and methods relating to a remote control mounting system having a clip and base are disclosed herein. In various embodiments, the clip may be designed for a specific remote control, and/or the clip may be attached to the base in one or more positions, giving the remote control mounting system modularity.
US09570248B2	Linear selector The invention relates to a linear selector (1) for power-free preselection of tap contacts for a tapped transformer (100). The linear selector (1) according to the invention is cost-effective, simple and compactly constructed. The functions of a selector and a reverser are thus better connected. The linear selector (1) is constructed from a fine selector (2) and a reversing switch (3). The fine selector (2) and the reversing switch (3) are directly driven via a common gear unit (6).
US09570245B2	Method for producing electrode material for vacuum circuit breaker, electrode material for vacuum circuit breaker and electrode for vacuum circuit breaker Provided are a method for producing an electrode material for a vacuum circuit breaker, whereby withstand voltage, high current interruption performance and capacitor switching performance can be improved; an electrode material for a vacuum circuit breaker; and an electrode for a vacuum circuit breaker. A contact material for an electrode for a vacuum circuit breaker has an integral structure consisting of a central member and a Cu—Cr outer peripheral member, the central member having been produced as described above and comprising 30 to 50 wt % of Cu of a particle diameter of 20 to 150 μm and 50 to 70 wt % of Mo—Cr of a particle diameter of 1 to 5 μm, while the outer peripheral member being formed of a material, which is highly compatible with the central member, shows excellent interruption performance and had high withstand voltage, and being provided outside the central member and fixed thereto.
US09570241B2	Dye-sensitized solar cell module using thin glass substrate and method of manufacturing the same Disclosed are a dye-sensitized solar cell module and a method of manufacturing the same. The dye-sensitized solar cell module includes a working electrode formed by stacking a collector and a photo-electrode to which a dye is adsorbed on a transparent conductive substrate; a counter electrode formed by stacking a collector and a catalytic electrode on a transparent conductive substrate; and an electrolyte filled in a space between the working electrode and the counter electrode sealed by a sealant. A glass substrate for the working electrode of glass substrates forming the transparent conductive substrates for the electrodes is a thin glass plate substrate thinner than the glass substrate for the working electrode.
US09570239B2	Electrode forming film and film capacitor using the same An electrode forming film includes: a dielectric film; an electrode head part; a first common electrode connected with the electrode head part; a plurality of first split electrodes spaced apart from the first common electrode in the first direction; a second common electrode spaced apart from the first split electrodes in the first direction; a plurality of second split electrodes spaced apart from the second common electrode in the first direction; a plurality of first fuse parts formed between the first common electrode and the first split electrodes; a plurality of second fuse parts formed between the first split electrodes and the second common electrode; and a plurality of third fuse parts formed between the second common electrode and the second split electrodes.
US09570237B2	Multilayer ceramic capacitor and mounting board for multilayer ceramic capacitor There is provided multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers laminated therein, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein, an upper cover layer formed on an upper portion of the active layer, a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer, first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer, and first and second external electrodes covering the both end surfaces of the ceramic body.
US09570234B2	Multilayer ceramic capacitor In a multilayer ceramic capacitor, SG represents an average of a distance between end portions of inner electrodes in a width direction and side surfaces of a ceramic body, OT represents an average of a distance between inner electrodes closest to main surfaces and the main surfaces, ET1 represents an average of dimensions of each portion of third and fourth terminal electrodes located on the main surfaces, and ET2 represents an average of dimensions of each portion of the third and fourth terminal electrodes located on the side surfaces. A dimension of the ceramic body in the width direction is larger than a dimension of the ceramic body in the height direction and Equations (1) and (2) are satisfied: SG>OT (1) ET1>ET2 (2).
US09570232B2	Transformer for power line communication Disclosed is a transformer for power line communication, capable of performing power line communication without being influenced by voltage attenuation due to voltage conversion. The transformer for power line communication includes: a transforming unit configured to convert a high primary voltage into a low secondary voltage, or convert a low secondary voltage into a high primary voltage; a separation unit configured to separate a data signal from a primary voltage input thereto; and a coupling unit configured to couple the data signal with the low secondary voltage.
US09570227B1	Magnetic excitation coil structure Disclosed is a magnetic excitation coil structure including a magnetic coil sheet formed of a thin film and rolled as a cylindrical body with a hollow hole, and an insulation layer covering the outer surface of the cylindrical body formed by the magnetic coil sheet for protection. The magnetic coil sheet includes a flexible substrate, a dielectric layer attached to the flexible substrate, and a plurality of patterned circuit layers embedded in the flexible substrate and in contact with the dielectric layer. Each patterned circuit layer is separate, and the upper surfaces of the patterned circuit layers and the upper surface of the flexible substrate form a co-plane. The magnetic coil structure provides an electrical function of coil, which is enhanced by the patterned circuit layer due to its high aspect ratio of the electrical circuit, thereby greatly increasing the whole magnetic flux and electromagnetic effect.
US09570223B2	Transformer apparatus and method for manufacturing transformer apparatus A transformer apparatus includes: a case with a component mounting surface; an external-terminal provided on a wall adjacent to the component mounting surface of the case; a transformer provided on the component mounting surface and including a magnetic core and a winding; and a support provided in a position between the external-terminal and the core on the component mounting surface, and including a first-slit in a top surface of the support, the first-slit holding a first-conductor of the winding drawn from the core and a second-conductor drawn from the external-terminal, wherein the first-conductor is held at one end of the first-slit by a conductive member, the second-conductor is held at the other end of the first-slit by the conductive member, the first-conductor and the second-conductor are electrically connected through the conductive member, and the first-conductor and the second-conductor have surplus lengths.
US09570216B2	Elastomeric gripping member for spacer assembly A spacer assembly includes a first clamping body having first and second ends and first and second protrusions extending from the first and second ends, respectively. A second clamping body has third and fourth ends and third and fourth protrusions extending from the third and fourth ends, respectively. A first gripping member disposed between the first and third ends has first and second openings for receiving the first and third protrusions, respectively, such that the first and third protrusions pass completely through the first and second openings to contact a first conductor received by the first gripping member. A second gripping member disposed between the second and fourth ends has third and fourth openings for receiving the second and fourth protrusions, respectively, such that the second and fourth protrusions pass completely through the third and fourth openings to contact a second conductor received by the second gripping member.
US09570207B2	Electrical contact materials and method for preparing the same Disclosed are electrical contact materials and a method for preparing the same. The electrical contact material includes (i) one or more kinds of metals selected from the group consisting of silver (Ag), copper (Cu) and gold (Au), and an alloy of nickel (Ni); and (ii) carbon nano tubes (CNTs) coated with Ag nanoparticles, Ag plated CNTs, or Ag nanowires, or (i) one or more kinds of metals selected from the group consisting of Ag, Cu, Ni and Au; (ii) a metal oxide that is cadmium oxide, indium oxide, tin oxide, zinc oxide or mixture thereof; and (iii) CNTs coated with Ag nanoparticles, Ag plated CNTs, or Ag nanowires. Accordingly, it is possible to reduce the content of high-priced Ag and to obtain excellent electrical and mechanical properties.
US09570200B2	Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
US09570198B2	Read disturb detection It is determined that a read count has reached one of a set of read count thresholds. An initial test page which corresponds to the read count threshold that has been reached is selected from a set of initial test pages. There is at least one page that is not in the set of initial test pages and is victimized by an offending page that also victimizes a page in the set of initial test pages. A test read is performed on the selected test page and the results of the test read of the selected test page are evaluated for read disturb noise.
US09570196B2	Testing through-silicon-vias Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
US09570192B1	System and method for reducing programming voltage stress on memory cell devices A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to receiving a second asserted signal via a global word line and a third asserted signal.
US09570191B2	Controlling swap rate based on the remaining life of a memory A method of managing a memory in an electronic device is provided that includes calculating an indication of remaining life of a memory component that is used as a swap space by the electronic device; and adjusting the use of the memory component as a swap space based on the indication of remaining life, wherein the adjusting includes one of: (i) reducing a rate at which data is swapped in and out of the memory component, and (ii) discontinuing the use of the memory component as a swap space.
US09570190B2	Semiconductor memory device to selectively perform a single sensing operation or a multi-sensing operation A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit configured to perform a program pulse applying operation and a verification operation on the memory cell array. The semiconductor memory device may include a control logic configured to control the peripheral circuit to selectively perform a single sensing operation or a multi sensing operation during the verification operation.
US09570186B2	Memory page buffer Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
US09570178B2	Semiconductor memory device and operating method thereof The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an LSB program state or an MSB program state.
US09570177B2	Programming dummy data into bad pages of a memory system and operating method thereof A memory system includes a memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of pages each include a plurality of memory cells electrically coupled to a plurality of word lines and store write data and provide read data which are requested from a host, and a controller suitable for checking a bad page among a plurality of pages in a first memory block of the memory blocks, programming dummy data in the bad page, and process the first memory block as a normal block.
US09570175B2	Incrementally programmable non-volatile memory An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a Vt representing a particular binary logic state can be changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
US09570172B2	Apparatuses and methods for providing set and reset voltages at the same time Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.
US09570169B1	Resistive memory device A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for storing information in a plurality of resistance states, a second segment including a non-insulating material, a first terminal, a second terminal, and a third terminal. The first segment and the second segment are arranged in parallel between the first terminal and the second terminal. The control unit is configured to apply in a write mode a write voltage to the first and the second terminal for writing the resistance state, and to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state, and to apply a control signal to the third terminal for adjusting the electrical resistance of the second segment. A related method and control unit are also disclosed.
US09570168B2	Nonvolatile memory device with reduced coupling noise and driving method thereof Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.
US09570166B1	Read operations and circuits for memory devices having programmable elements, including programmable resistance elements A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
US09570165B2	1D-2R memory architecture A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.
US09570162B2	Data read method for flash memory The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code.
US09570161B2	Method of operating incrementally programmable non-volatile memory An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
US09570160B1	Non-volatile storage system with defect detetction and early programming termination A non-volatile storage system includes defect detection and early program termination. The system commences programming of a plurality of non-volatile memory cells, determines that a defect condition exists and, in response to determining that the defect condition exists, terminates the programming of the plurality of memory cells prior to completion of programming.
US09570157B1	Dynamic capacitance balancing Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.
US09570153B1	Multi-ported static random access memory A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word line, and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line.
US09570150B2	Memory device with open bit line structure which minimizes loading difference of sense amplifiers arranged outermost part A memory device may include: first to Nth cell blocks; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.
US09570149B2	Output signal generation device having a phase adjustment unit and method for adjusting a phase difference between an input and an output signal An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.
US09570147B2	Semiconductor package with PoP structure and refresh control method thereof A refresh control method of a semiconductor package, comprising: providing a semiconductor package including a first semiconductor chip and a second semiconductor chip; monitoring a temperature of each of a plurality of sensing areas of the first semiconductor chip when the first semiconductor chip operates; identifying at least one memory bank of the second semiconductor chip corresponding to an area having a lower temperature among the sensing areas; controlling the second semiconductor chip to transfer data to the identified memory bank from another memory bank of the second semiconductor chip; and controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified memory bank is greater than that of a period of a refresh operation on the other memory bank.
US09570146B1	Alternate access to DRAM data using cycle stealing A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.
US09570136B2	Semiconductor memory apparatus A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address. The semiconductor memory apparatus may include a decoding block configured to enable only one word line among a plurality of word lines or may simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address.
US09570134B1	Reducing transactional latency in address decoding Techniques for reducing latency in address decoding are described. According to one approach, a method of operating an addressing circuit comprises partitioning range of encoded addresses into a first and second subset of encoded addresses, sending a first encoded address to a address decode circuit from a controller. In response to determining that the first encoded address is contained in the first subset, decoding the first encoded address in a first duration. In response to determining that the first encoded address is contained in the second subset, decoding the first encoded address in a second duration which is longer than the first duration and simultaneously sending a halt signal to the controller to stop sending subsequent encoded addresses for decoding for the entirety of the second duration.
US09570120B2	Memory device and operation method thereof A memory device may include a plurality of cell arrays, a first interface suitable for inputting/outputting first data between the plurality of cell arrays and a host apparatus, a second interface suitable for inputting/outputting second data between the plurality of cell arrays and a device other than the host apparatus, and a data erasure circuit suitable for erasing the first data of the plurality of cell arrays when a first mode in which the first interface is used switches to a second mode in which the second interface is used.
US09570119B2	Information processing system including semiconductor device having self-refresh mode A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.
US09570118B2	Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.
US09570117B2	Integrated circuit with independent programmability An integrated circuit includes circuitry performing memory operations. The power from only one of a first power lead and a second power lead is sufficient for the circuitry to operate. A package encasing the integrated circuit. Leads on the package electrically couple power and data from an exterior of the package to the integrated circuit encased by the package, including the first power lead, the second power lead, and a ground lead. An isolation circuit electrically couples the circuitry to the first power lead but not the second lead at a first time, and electrically couples the circuitry to the second power lead but not the first power lead at a second time.
US09570116B2	Semiconductor device, memory device, and electronic device To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
US09570110B2	Multimedia-data-processing method The present invention relates to a multimedia-data-processing method which enables a media graph to always be constructed in a “connection without negotiation” manner, on the basis of an already known media graph construction, and thus provides a media framework in which procedures for connecting components are minimized, thereby improving the performance of a system and satisfying the requests of an OS platform builder and a media application developer. The multimedia-data-processing method of the present invention is performed by a multimedia framework, and comprises: (a) a step of receiving component information required for the construction of the media graph and component connection information from a media application; and (b) a step of ensuring that the media graph is constructed by the content received in step (a), and that the media graph waits for a rendering command, thereby eliminating the necessity of permitting the media application to check the construction of the media graph.
US09570109B2	Method and system for matching audio and video The present application relates to the field of media processing and more particularly to audio and video processing. The present application addresses the problem that videos collected by fans at concerts and other events generally have poor sound quality and provides a solution that matches a high quality sound to the video.
US09570103B2	Optional data encryption by partition for a partitionable data storage library Disclosed are a method and apparatus for a data storage library comprising a first and second drive, a first and second mobile medium, a first and second partition wherein the first partition comprises the first drive and the first mobile medium and the second partition comprises the second drive and the second mobile medium, and a combination bridge controller device. The combination bridge controller device is configurable to control first communication traffic between at least a first client and the first partition wherein the first communication traffic can comprise a first data package. The combination bridge controller device is further configurable to optionally encrypt the first data package for storage on the first mobile medium when the first mobile medium is in cooperation with the first drive.
US09570102B2	Information recording and reproducing apparatus and information recording and reproducing method An information recording and reproducing apparatus including: a reproducing unit which generates a digital signal from an analog signal; a recording compensation unit which generates an expectation signal from the digital signal, detects a signal difference between the digital signal and the expectation signal, and adjusts a recording condition for recording the information; and a recording unit configured to record the information based on the recording condition. First recording compensation is performed for adjusting the recording condition using first recording where lengths of a preceding space and a succeeding space of a first recording mark and lengths of a preceding space and a succeeding space of a second recording mark are not in intersymbol interference; and second recording compensation is performed for adjusting the recording condition for the first recording mark using second recording data for changing a length of the second recording mark.
US09570092B2	Real-time emotion tracking system Devices, systems, methods, media, and programs for detecting an emotional state change in an audio signal are provided. A number of segments of the audio signal are analyzed based on separate lexical and acoustic evaluations, and, for each segment, an emotional state and a confidence score of the emotional state are determined. A current emotional state of the audio signal is tracked for each of the number of segments. For a particular segment, it is determined whether the current emotional state of the audio signal changes to another emotional state based on the emotional state and a comparison of the confidence score of the particular segment to a predetermined threshold.
US09570090B2	Dialog system with automatic reactivation of speech acquiring mode Embodiments of the disclosure generally relate to a dialog system allowing for automatically reactivating a speech acquiring mode after the dialog system delivers a response to a user request. The reactivation parameters, such as a delay, depend on a number of predetermined factors and conversation scenarios. The embodiments further provide for a method of operating of the dialog system. An exemplary method comprises the steps of: activating a speech acquiring mode, receiving a first input of a user, deactivating the speech acquiring mode, obtaining a first response associated with the first input, delivering the first response to the user, determining that a conversation mode is activated, and, based on the determination, automatically re-activating the speech acquiring mode within a first predetermined time period after delivery of the first response to the user.
US09570089B2	Hearing system and transmission method A hearing system for improving intelligibility during the holding of a telephone conversation, includes a receiving device for receiving a first signal having first acoustic information and converting the first signal into electrical signals having the first acoustic information, a signal processing device for processing the electrical signals having the first acoustic information into electrical signals having second acoustic information, and an output device for outputting a second signal having the second acoustic information. A method for improving intelligibility during the holding of a telephone conversation using a hearing system is also provided.
US09570087B2	Single channel suppression of interfering sources Techniques described herein are directed to performing back-end single-channel suppression of one or more types of interfering sources (e.g., additive noise) in an uplink path of a communication device. The back-end single-channel suppression techniques may suppress types(s) of additive noise using one or more suppression branches (e.g., a non-spatial (or stationary noise) branch, a spatial (or non-stationary noise) branch, a residual echo suppression branch, etc.). The non-spatial branch may be configured to suppress stationary noise from the single-channel audio signal, the spatial branch may be configured to suppress non-stationary noise from the single-channel audio signal and the residual echo suppression branch may be configured to suppress residual echo from the signal-channel audio signal. The spatial branch may be disabled based on an operational mode (e.g., single-user speakerphone mode or a conference speakerphone mode) of the communication device or based on a determination that spatial information is ambiguous.
US09570086B1	Intelligently canceling user input Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for intelligently cancelling user inputs. In one aspect, a requests input by a user is received by a dialog engine. A prompt or notification regarding the request is output by the dialog engine. That the user has taken an action in response to the prompt or notification is determined by the dialog engine. Based on the action taken by the user, that the response corresponds to a potential cancellation command is determined by the dialog system.
US09570083B2	Stereo audio encoder and decoder The present disclosure provides methods, devices and computer program products for encoding and decoding a stereo audio signal based on an input signal. According to the disclosure, a hybrid approach of using both parametric stereo coding and a discrete representation of the stereo audio signal is used which may improve the quality of the encoded and decoded audio for certain bitrates.
US09570082B2	Method, medium, and apparatus encoding and/or decoding multichannel audio signals A method, medium, and apparatus encoding and/or decoding a multichannel audio signal. The method includes detecting the type of spatial extension data included in an encoding result of an audio signal, if the spatial extension data is data indicating a core audio object type related to a technique of encoding core audio data, detecting the core audio object type; decoding core audio data by using a decoding technique according to the detected core audio object type, if the spatial extension data is residual coding data, decoding the residual coding data by using the decoding technique according to the core audio object type, and up-mixing the decoded core audio data by using the decoded residual coding data. According to the method, the core audio data and residual coding data may be decoded by using an identical decoding technique, thereby reducing complexity at the decoding end.
US09570078B2	Techniques to provide a standard interface to a speech recognition platform Techniques and systems to provide speech recognition services over a network using a standard interface are described. In an embodiment, a technique includes accepting a speech recognition request that includes at least audio input, via an application program interface (API). The speech recognition request may also include additional parameters. The technique further includes performing speech recognition on the audio according to the request and any specified parameters; and returning a speech recognition result as a hypertext protocol (HTTP) response. Other embodiments are described and claimed.
US09570076B2	Method and system for voice recognition employing multiple voice-recognition techniques A method and system for voice recognition are disclosed. In one example embodiment, the method includes receiving voice input information by way of a receiver on a mobile device and performing, by way of at least one processing device on the mobile device, first and second processing operations respectively with respect to first and second voice input portions, respectively, which respectively correspond to and are based at least indirectly upon different respective portions of the voice input information. The first processing operation includes a speech-to-text operation and the second processing operation includes an alternate processing operation. Additionally, the method includes generating recognized voice information based at least indirectly upon results from the first and second processing operations, and performing at least one action based at least in part upon the recognized voice information, where the at least one action includes outputting at least one signal by an output device.
US09570075B1	Techniques for integrating voice control into an active telephony call Examples are disclosed for responding to voice commands within an existing telephony call between two or more end user communication devices mediated by an IP based communications server. The server is mediating a telephony call among the two or more end user communication devices where each end user communication device has its own communication link to the server. The server may detect a trigger event from one of the end user communication devices. Upon detecting the trigger event, the server may receive voice input over the communication link from the end user communication device that generated the trigger event. The received voice input may be parsed into one or more voice commands. The server may then cause the one or more voice commands to be executed. In other embodiments, much of the intelligence and processing may be carried out on the end user communication device directly.
US09570073B2	Remote control audio link One embodiment may take the form of a voice control system. The system may include a first apparatus with a processing unit configured to execute a voice recognition module and one or more executable commands, and a receiver coupled to the processing unit and configured to receive a first audio file from a remote control device. The first audio file may include at least one voice command. The first apparatus may further include a communication component coupled to the processing unit and configured to receive programming content, and one or more storage media storing the voice recognition module. The voice recognition module may be configured to convert voice commands into text.
US09570070B2	System and method for processing multi-modal device interactions in a natural language voice services environment A system and method for processing multi-modal device interactions in a natural language voice services environment may be provided. In particular, one or more multi-modal device interactions may be received in a natural language voice services environment that includes one or more electronic devices. The multi-modal device interactions may include a non-voice interaction with at least one of the electronic devices or an application associated therewith, and may further include a natural language utterance relating to the non-voice interaction. Context relating to the non-voice interaction and the natural language utterance may be extracted and combined to determine an intent of the multi-modal device interaction, and a request may then be routed to one or more of the electronic devices based on the determined intent of the multi-modal device interaction.
US09570069B2	Sectioned memory networks for online word-spotting in continuous speech Systems, methods, and computer program products to detect a keyword in speech, by generating, from a sequence of spectral feature vectors generated from the speech, a plurality of blocked feature vector sequences, and analyzing, by a neural network, each of the plurality of blocked feature vector sequences to detect the presence of the keyword in the speech.
US09570064B2	Conversation-sentence generation device, conversation-sentence generation method, and conversation-sentence generation program A conversation-sentence generation device according to the invention of this application includes: an input unit that receives, as input information, a conversation sentence given from a user to an agent, and clue information based on which a physical and psychological state of the agent is estimated; an agent state storing unit that stores the physical and psychological state of the agent as an agent state; an agent state estimating unit that estimates a new agent state based on the input information and the agent state; an utterance intention generating unit that generates, based on the input information and the agent state, an utterance intention directed from the agent to the user; a conversation sentence generating unit that generates, based on the input information, the agent state, and the utterance intention, a conversation sentence given from the agent to the user; and an output unit that outputs the conversation sentence generated by the conversation sentence generating unit.
US09570063B2	Method and system for achieving emotional text to speech utilizing emotion tags expressed as a set of emotion vectors A method and system for achieving emotional text to speech. The method includes: receiving text data; generating emotion tag for the text data by a rhythm piece; and achieving TTS to the text data corresponding to the emotion tag, where the emotion tags are expressed as a set of emotion vectors; where each emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories. A system for the same includes: a text data receiving module; an emotion tag generating module; and a TTS module for achieving TTS, wherein the emotion tag is expressed as a set of emotion vectors; and wherein emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories.
US09570061B2	Acoustic material and wire harness with acoustic material It is aimed to provide a sound-absorbing material and a wiring harness with sound-absorbing material capable of absorbing sound in a wide frequency range from a low frequency to a high frequency and avoiding a weight increase. A sound-absorbing material 1 is configured by laminating base material sheets 3 using non-woven fabrics and a skin material sheet 2 having a smaller basis weight than the base material sheets 3 such that the skin material sheet 2 is arranged between the plurality of base material sheets 3 and an air permeation amount of the sound-absorbing material is within a range of 5 to 50 cm3/cm2·s.
US09570060B2	Techniques of audio feature extraction and related processing apparatus, method, and program A music signal processing apparatus includes a frequency spectrum transform unit, a filter, a frequency feature amount generation unit, and a melody feature amount sequence acquisition unit. The frequency spectrum transform unit is configured to transform a music signal into a frequency spectrum, the music signal being a signal of a musical piece containing a part with a melody. The filter is configured to remove a steep peak of the frequency spectrum. The frequency feature amount generation unit is configured to generate, from a signal output from the filter, a frequency feature amount in which a fundamental frequency component of the part is emphasized. The melody feature amount sequence acquisition unit is configured to acquire, based on the frequency feature amount, a melody feature amount sequence that specifies a fundamental frequency of the part at each time.
US09570054B2	Musical bar for musical instrument A musical bar for a musical instrument includes a striking surface and a back surface which is a back side of the musical bar from the striking surface. When the striking surface is struck, the musical bar is vibrated to produce a musical tone with a unique pitch as a pitch of a fundamental tone. A recess is formed in the musical bar so as to be recessed from the back surface toward the striking surface. A position of a node of vibration of the fundamental tone for the musical bar is substantially aligned with an imaginary center of gravity of the recess in a longitudinal direction of the musical bar.
US09570053B2	Adjustable cajón instrument Tunable cajón devices, including tuning and adjustment during a performance, are disclosed. In an aspect, the present disclosure provides a tunable cajón device wherein internal strings or cords under tension may be tuned via the manual manipulation of tuners accessible via a top surface of the cajón. As such, a cajón player may view tuner position and adjust the tuner from the traditional playing position. Adjustments (i.e., tuning of internal strings) may be done before, during, or after a performance.
US09570052B1	Apparatus for enhancing sounds produced out of single-reed wind music instruments Apparatus for enhancing tunes produced out of single-reed wind music instrument are disclosed. Apparatus comprise one or more sound enhancing elements in form of a plurality of elongated ribs or grooves, or one or more studs affixed to a reed's table side. Patterns of the elongated ribs/grooves can be straight or wavy lines orientated in longitudinal, transverse or oblique direction with respect to the reed. Each stud contains a three-dimensional (3-D) geometric shape portion for altering sounds produced out of a single-reed wind music instrument when played by a player, and a base of the 3-D geometric shape portion for affixing the stud to the table side of a reed in an area directly opposite to the heart of the reed. Dimensions of the area are single-reed wind music instrument dependent.
US09570050B2	System and method for enhanced screen copy A computer implemented system and method provides for responding to an instruction to a print screen instruction by generating and storing an image of user interface components that had been displayed in a display area when the instruction was received; and storing in association with the image original text that had been displayed in the display area and on the user interface components when the instruction was received, where the first image does not include a representation of the original text. Output of the screen copy includes, for example, overlaying some or all of the text, or which some or all can be in modified form, over the image.
US09570049B2	Semiconductor device The semiconductor device includes: a select circuit which selects, from output signals of tiding generators, timing signals formed by one timing generator; another select circuit which is disposed in a stage after the select circuit, and selects the tiding signals selected by the first select circuit or signals regulated in polarity, and outputs the selected signals outward; and a control register provided for variably setting the polarities of the signals regulated in polarity in units of the signals. If abnormal power supply cutoff of the semiconductor device is detected, the second select circuit is switched from the state of selecting the timing signals to the state of selecting the signals regulated in polarity in response to the detection.
US09570039B2	Display device, driving method of display device and data processing and outputting method of timing control circuit A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.
US09570037B2	Remote display control Technologies are generally described for controlling remote display. In some examples, a method for controlling a remote display device using a handheld computing device includes receiving, by a handheld computing device, one or more data from one or more remote display devices over a wireless communication network, selecting a remote display device based on the received data and sending a control signal to the selected remote display device.
US09570034B2	Pixel cell circuits of compensation feedback voltage The present disclosure relates to a pixel cell circuit of compensation feedback voltage. The pixel cell circuit is provided with the compensation capacitance (C_co), one end of the compensation capacitance (C_co) electrically connects to the compensation level wirings G(m)_co, and the other end of the compensation capacitance (C_co) electrically connects to the drain of the TFT (T1) and the pixel electrode (P). A level of the compensation signals transmitted by the compensation level wirings G(m)_co is opposite to the level of the scanning signals transmitted by the scanning lines G(m). When the pixel electrode has been fully charged, the compensation capacitance generates a pull-up feedback voltage for compensating the pull-down voltage caused by the parasitic capacitance so as to eliminate the effects toward the pixel electrodes caused by the scanning signals transmitted by the scanning lines. This configuration not only decreases the flickers, but also the image sticking. In brief, the display uniformity and the display performance are enhanced.
US09570033B2	Driver, electro-optical device, and electronic device A driver, an electro-optical device, and an electronic device are provided with which a rise in a ground line voltage due to a discharge can be suppressed. The driver includes a voltage generating circuit 100 that generates a first voltage VA1 and a second voltage VA2 for driving a display panel, outputs the first voltage VA1 to a first node NA1, and outputs the second voltage VA2 to a second node NA2, and a discharge circuit 140 that performs a discharge operation if the voltage generating circuit 100 is deactivated. The discharge circuit 140 performs a first discharge operation of discharging the first node NA1, and thereafter performs a second discharge operation of discharging the second node NA2.
US09570032B2	Display device, liquid crystal display device and electronic device including the same A liquid crystal display device includes a pixel having a first to nth (n is a natural number of 2 or more) subpixels and a circuit. To the circuit, N (N is a natural number of 2 or more) wirings for supplying a digital signal with N bits and first to nth wiring groups having M (M is a natural number of 2 or more) wirings for supplying M different voltages are electrically connected. The liquid crystal display device has a function of converting the digital signal into n analog signals by using the M voltages supplied to the first to nth wiring groups and inputting the n analog signals to first to nth subpixels. The first to nth subpixels each include an electrode for driving a liquid crystal element.
US09570030B2	Display device and method of driving the same A gate driver (24) which is provided by an IGZO-GDM and a level shifter circuit (13) are connected to each other via a first through a fifth wires (OL1 through OL5). Each wire (OL) is connected to a discharge unit (190). If an electric power supply to a first through a fifth output circuits (OC1 through OC5) in the level shifter circuit (13) becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OC1 through OC5) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit (190) into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.
US09570028B2	PMOS gate driving circuit The present invention provides a PMOS gate driving circuit, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module (100), a pull-up module (200), a transmission module (300), a first pull-down module (400), a bootstrap capacitor (500) and a pull-down holding module (600); the pull-up controlling module (100) receives a constant negative voltage level (VSS1), which can reduce the influence of PMOS element leakage to the first node (Q(N)); the pull-down holding module (600) is provided with a dual inverter (F1) comprising P-type thin film transistors, and utilizes special leakage prevention design, which can reduce the leakage of the first node (Q(N)) to prevent the influence of the electrical property of the depletion-mode P-type thin film transistors to the output of the inverter, raise the stability of the gate driving circuit, and promote the integration of the panel. The frame width of the liquid crystal display panel can be decreased in advance, particularly to be suitable for small size panel which requires higher demands to the frame width.
US09570026B2	Scan driving circuit and LCD device A scan driving circuit includes a pull-up assembly, a pull-up control assembly that drives the pull-up assembly, a pull-down maintaining assembly, and a reference low-level signal. When the current scanning line is inactive, the pull-down maintaining assembly is controlled by a pull-down maintaining signal to make a reference low-level signal be sent to an output end of the pull-up control assembly and the current scanning line.
US09570025B2	Gate driving apparatus and display device A gate driving apparatus and display device are provided to settle abnormal display in a full screen caused by abnormality in signals output from a shift register when short-circuit occurs in wirings associated with gate lines within a liquid crystal panel. The apparatus comprises a plurality of gate driving units connected in cascade. Each stage of the gate driving units comprises a shift register unit and a relay unit whose pulling-up control terminal is connected to an output terminal of the shift register unit, reset signal terminal is connected to a reset signal terminal of the shift register unit, pulling-down control terminal is connected to pulling-down control node of the shift register unit, first power-supply input terminal is connected to first power voltage, second power-supply input terminal is connected to second power voltage, and output terminal is connected to the gate line as output terminal of the gate driving unit.
US09570021B2	Array substrate, flexible display device and electronic device The present disclosure provides an array substrate, a flexible display device and an electronic device. The array substrate includes a flexible substrate, and an array layer formed on the flexible substrate. The flexible substrate is bendable, and the array layer includes: signal transmission lines including a plurality of data lines and a plurality of gate lines which are arranged on the flexible substrate in a crisscross manner so as to define a plurality of subpixel regions; and a TFT arranged at each subpixel region and connected to the corresponding data line and gate line. At least portions of the signal transmission lines are formed as bending curves whose travelling direction is parallel to a side of the flexible substrate.
US09570018B2	Backlight driver of liquid crystal display device and method for driving the same to maintain stability of the duty ratio of the PWM signal driving the backlight A backlight driver and a method of driving the same are disclosed, which remove an unstable duty ratio by filtering an input PWM signal so as to prevent backlight flicker although the input PWM signal becomes unstable. The backlight driver includes a duty ratio detector for detecting a duty ratio of an input pulse width modulation (PWM) signal; a duty ratio filter for detecting a difference between a current duty ratio received from the duty ratio detector and a previous duty ratio, determining whether the detected duty ratio difference satisfies a preset reference condition, selecting one of the current duty ratio and the previous duty ratio, and outputting the selected duty ratio; and a PWM generator for generating an output PWM signal obtained when a selected duty ratio from the duty ratio filter is reflected in an input synchronization signal, and outputting the output PWM signal to a backlight unit.
US09570016B2	Light source control module, backlight module and driving method thereof The present invention provides a light source control module, a backlight module and driving method thereof which can overcome the problems of insufficient color amount, poor performance and lowered color saturation. A light source control module of the present invention is used for separately controlling illumination colors and/or brightness of each light source in the backlight module according to image information. The driving method of the backlight module comprises: calculating representative color and/or brightness of each image section based on image information, wherein each image section corresponds to a light output area on the output surface of the backlight module, each light output area is illuminated by one light source in the backlight module; adjusting the illumination colors and/or brightness of each light source such that the color and/or brightness of each light output area is in conformity with the representative color and/or brightness of corresponding image section.
US09570015B2	Signal conversion device, signal conversion method and display device The present invention discloses a signal conversion device, a signal conversion method and a display device. The signal conversion device includes a gamma conversion unit, a brightness detection unit and a brightness processing unit, wherein the gamma conversion unit is used for performing a gamma conversion process on RGB input signals and generating RGB brightness input values; the brightness detection unit is used for generating a W brightness input value based on RGB proportional coefficients and the RGB brightness input values; and the brightness processing unit is used for generating RGBW output signals based on the RGB proportional coefficients, the RGB brightness input values and the W brightness input value. With the present invention, the brightness of a displayed image can be increased without increasing the power consumption, so that the contrast of the displayed image is increased, and the display quality of the image is also improved.
US09570014B2	Field sequential color liquid crystal display device and color control method thereof A field sequential color liquid crystal display (FSC-LCD) device and a color control method thereof are provided. The FSC-LCD device includes: a liquid crystal display panel which includes a color filter of first color sub-pixel and a color filter of second color sub-pixel, and a color field period thereof is sequentially divided into a first sub-color-field period and a second sub-color-field period; and a backlight module for providing a backlight source to the liquid crystal display panel and including a red backlight and a cyan backlight. The backlight module is for providing two color backlights respectively during a first backlighting period in the first sub-color-field period and a second backlighting period in the second sub-color-field period. The present FSC-LCD device has larger aperture ratio and higher transmittance, can achieve high color gamut display, and is easily to realize the narrow border design while reducing the amount of LED.
US09570010B2	Organic light-emitting diode pixel circuit and driving method thereof The present invention can solve the problem that an existing organic light-emitting diode pixel circuit has a single function or a complicated structure. An organic light-emitting diode pixel circuit of the present invention includes: a touch fingerprint detection module configured to detect whether a touch occurs or not and whether the touch is caused by a convex portion of a fingerprint or a concave portion of the fingerprint, and send a result of the detection to a read line, under the control of a first scanning signal and a second scanning signal; and a compensation display module including an organic light-emitting diode and at least one driving transistor, and configured to eliminate a shift of a threshold voltage of the driving transistor and drive the organic light-emitting diode to display under the control of at least the first scanning signal, the second scanning signal, and a data signal.
US09570009B2	Pixel circuit of display device, organic light emitting display device and method for driving the same A pixel circuit of a display device, an organic light emitting display device and a method for driving the same are discussed. The pixel circuit of the display device in one example includes an organic light emitting device emitting light through a current; a driving transistor controlling the current flowing in the organic light emitting device; a first capacitor connected between gate and source electrodes of the driving transistor; a second capacitor in which a data voltage is previously stored; and a switching unit charging the data voltage, which is stored in the second capacitor, in the first capacitor, and allowing the organic light emitting device to emit light by driving the driving transistor in accordance with the data voltage charged in the first capacitor and at the same time charging a data voltage of next frame in the second capacitor.
US09570008B2	Pixel circuit, organic light emitting display device having the same, and method of driving an organic light emitting display device A pixel circuit of an organic light emitting display device includes an emission unit, an emission control unit, a current supply unit, and a switch unit. The emission unit emits light based on an emission current. The emission control unit controls an emission operation of the emission unit based on a scan signal and a data signal. The current supply unit adjusts the emission current based on a current sinking operation performed based on an external constant current source, where the current supply unit is connected to the external constant current source. The switch unit controls an electrical connection operation between the emission control unit and the current supply unit.
US09570007B2	Pixel circuit and display device A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a TFT serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the TFT, and a source potential of the TFT is connected to a fixed potential through a TFT serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.
US09570006B2	Organic light-emitting display device An organic light-emitting display device which divides each frame into a plurality of sub-frames and represents gray levels based on the sum of the lengths of one or more sub-frames during which light is emitted, the organic light-emitting display device comprising a display unit including a plurality of pixels arranged in a matrix, a scan driver configured to provide a scan signal to the display unit during each sub-frame period and a precharge voltage unit configured to provide a precharge voltage to the pixels, wherein the pixels are divided into a first pixel column block including a pixel receiving the scan signal before the other pixels and a second pixel column block next to the first pixel column block in a direction of the application of the scan signal and the precharge voltage is selectively provided to pixels included in the first pixel column block.
US09570003B2	External compensation sensing circuit and sensing method thereof, display device An external-compensation sensing circuit, sensing method, and display device. The circuit includes fully-differential operational amplifier, first capacitor, second capacitor and outputting circuit for amplifying induced current; negative input of the amplifier is connected to display screen, positive input thereof is connected to reference voltage, negative output thereof is connected to first control terminal of the outputting circuit, positive output thereof is connected to second control terminal of the outputting circuit; two terminals of the first capacitor are connected to the negative input of the amplifier and an input of the outputting circuit respectively; one terminal of the second capacitor is connected to the output of the outputting circuit and the other terminal is grounded. The invention enables the output voltage to respond rapidly by amplifying induced current with dual outputting stages in the sensing circuit to raise the speed of the external-compensation.
US09570002B2	Interactive display panel with IR diodes Exemplary methods and systems use a micro light emitting diode (LED) in an active matrix display to emit light and a sensing IR diode to sense light. A display panel includes a display substrate having a display region, an array of subpixel circuits, and an array of selection devices. Each subpixel circuit includes a driving circuit to operate a corresponding infrared (IR) emitting LED in a light emission mode. Each selection device may be coupled to a corresponding sensing IR diode to operate the corresponding sensing IR diode in a light sensing mode.
US09569999B2	Signal generation apparatus, signal generation program, signal generation method, and image display apparatus There is provided a signal generation apparatus for generating an output video signal based on an input video signal provided corresponding to an image to be displayed, the output video signal being a signal for driving an image display section including a display area, the display area including a plurality of pixels arranged in a two-dimensional matrix. At a change of the input video signal from low-brightness display to high-brightness display for a portion of the display area including one or more of the pixels, during a period for the signal change, the output video signal being generated for each of the one or more of the pixels in the portion of the display area to obtain a higher brightness than usual for the portion of the display area.
US09569997B2	Display device including DC voltage conversion circuit A display device includes a timing control circuit, a driving circuit, a display panel, and a DC voltage converter. The timing control circuit generates a data signal based on an image signal. The driving circuit generates a first conversion control signal and a second conversion control signal representing a status of the first conversion control signal. The driving circuit generates a driven signal based on the data signal and is powered by a first DC voltage. The display panel is powered by a second DC voltage. The DC voltage converter includes first and second DC voltage conversion circuits. The first DC voltage conversion circuit generates the first DC voltage based on an external voltage. The second DC voltage conversion circuit generates the second DC voltage based on the external voltage. The DC voltage converter executes time-shared control of the first and second DC voltage conversion circuits based on the first and second conversion control signals.
US09569996B2	Semiconductor device, display device, and electronic device A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided.
US09569995B2	Methods, systems, and media for detecting a presentation of media content on a display device Methods, systems, and media for detecting a presentation of media content on a display device are provided. In accordance with some implementations, methods for detecting a presentation of media content on a display device are provided, the methods comprising: detecting, using a light sensor, light levels in the light sensor's surroundings; generating a signal representing the light levels; detecting, using a hardware processor, at least one variation in light levels indicative of a presentation of a video scene based on the signal; detecting at least one variation in light levels indicative of a scene change subsequent to the video scene based on the signal; and determining that media content is being presented on a display device in response to detecting the variation in light levels indicative of the presentation of the video scene and the variation in light levels indicative of the scene change.
US09569993B2	Pixel array comprising selection lines A pixel array including first and second signal lines, an active device, a pixel electrode and selection lines is provided. The second signal lines are intersected with the first signal lines to drive the active device, and the pixel electrode is connected to the active device. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines, where at least one selective line is disposed between the adjacent two second signal lines. An amount ratio of the first signal lines and the selection lines is a1/a2, where a1≦a2, and when a1 and a2 are mutually prime numbers, the selection lines are divided into a plurality of groups, and each group includes a1 selection lines electrically connected to the first signal lines, and (a2−a1) selection lines not electrically connected to the first signal lines.
US09569992B2	Method for driving information processing device, program, and information processing device An information processing device including a display unit and an input unit is driven by a first step of inputting an input signal from the input unit, a second step of starting to move an image displayed on the display unit, a third step of lowering luminance of the image, a fourth step of checking whether the image reaches a position of predetermined coordinates, a fifth step of increasing the luminance of the image in the case where the image reaches the position of the predetermined coordinates, and a sixth step of stopping moving the image so as to perform eye-friendly display with the display unit.
US09569990B2	System and method for controlling smart LED display board capable of compensating for luminance of LED A system for controlling a smart LED display board capable of compensating for luminance of an LED includes a luminance measurement unit which creates first luminance measurement data obtained by digitizing measured luminance of each LED, an image data input unit which receives first input data about each LED, a comparison unit which selects at least one first LED having a luminance value greater than a preset reference value, and creates a compensation power value compensating for the luminance value of the selected first LED; an image data compensation unit which receives the first input data and the compensation power value and creates second input data in which a power value that is contained in the first input data transmitted to the first LED is changed into the compensation power value; and a drive unit which transmits the second input data to the first LED.
US09569982B2	Methods and systems for providing self-care and acclimation recommendations to a client device based on environmental conditions Computer implemented methods and systems to provide self-care and acclimation recommendations to a client device based on a unique health profile and environmental conditions.
US09569981B1	Mathematics teaching aid An aid for teaching mathematical concepts looks like a multiplication table but has separable rows of numbers. In the first row, cardinal numbers 1-n are displayed and second-N rows have cardinal numbers 2-n displayed along side one edge on the face. The remainder of the rows have the multiplication products of the cardinal numbers on the first row and the cardinal numbers of the rest of the rows arranged at the intersections of the cardinal numbers at the top and along side the edge. The rows are separable so they may be arranged in a multiplicity of pairs of fractional equivalents.
US09569980B2	Security door breach training system A security door breach training system comprising a frame member; a plurality of elongate members, each of the elongate members fixed to the frame member and having a free end spaced from the frame member, the plurality of elongate members including at least one capture member, a first clevis member, and a second clevis member fixed to the frame member opposite the first clevis member; at least one retention bar attached between two of the elongate members and spaced a distance from the frame member; and at least one retaining pin adjacent to the frame member, the at least one retaining pin comprising an elongate element at least partially adjacent to the frame member and having a first end and an opposing second end, a retaining pin socket attached to the elongate element proximal to the first end, and a stub extending from the at least one elongate element proximal to the second end.
US09569978B2	Methods and systems for virtual problem based learning A computer-implemented method includes selecting, by a virtual problem-based learning (PBL) system, information indicative of a medical profile of a patient; accessing, by the virtual PBL system, information indicative of a team of students using the virtual PBL system; generating, by the virtual PBL system and based on the medical profile, an medical PBL schema comprising a medical problem to be solved by the team of students; generating a plurality of sections in the medical PBL schema, with each section promoting solving of the medical problem, and with each section associated with (i) a private work environment for a student to privately analyze the medical problem, and (ii) a shared, anonymous work environment for the students to view analysis performed by other students in solving the medical problem; and transmitting, to one or more client systems used by the students participating in the virtual problem-based learning system, the medical PBL schema.
US09569972B2	Unmanned aerial vehicle identity and capability verification A device receives a request for a flight path for a UAV from a first location to a second location, credentials for the UAV, and component information for the UAV. The device determines, based on the credentials, whether the UAV is authenticated for utilizing the device and a network, and determines whether the UAV is capable of flight based on the component information and maintenance information. The device calculates, the flight path based on capability information for the UAV and/or other information, and determines whether the UAV is capable of traversing the flight path based on the capability information and/or the other information. The device generates flight path instructions for the flight path, and provides the flight path instructions to the UAV to permit the UAV to travel from the first location to the second location via the flight path.
US09569971B2	Satellite communication network The invention relates to a monitoring system for the air-traffic control of flight objects (5, 6), which have transmitting units for emitting air-traffic control radio signals (ADS-B), wherein the air-traffic control radio signals (ADS-B) containing flight data concerning the respective aircraft (5, 6), the monitoring system comprising a plurality of receiving units (4a to 4c), which are designed to receive the emitted air-traffic control radio signals, wherein a plurality of satellites (1a to 1c) are provided, which each have communication means for forming a common satellite communication network and on each of which at least one of the receiving units (4a to 4c) is arranged, wherein the receiving units (4a to 4c) are connected to the communication means of the respective satellite (1a to 1c) and are designed to transmit the flight data contained in the air-traffic control radio signals to at least one ground station (3, 7) having a communication connection to the satellite communication network using a common communication protocol of the satellite communication network.
US09569969B2	Track collision avoidance control system A track collision avoidance control system including a train having an onboard control system for controlling one or more characteristics of the train. The track collision avoidance control system can further include a warning indication system comprising a transmitter linked to a communication system supported about the train, the communication system comprising a receiver operable to receive a signal from the transmitter, the signal comprising information pertaining to a potentially dangerous condition. The transmitter can be operable alone or in combination with a warning indicator, an actuator and their associated logic circuitry, such that the transmitter is caused to transmit upon the warning indicator being activated. The communication system can interface with an onboard control system of the train. The communication system can receive the signal, which can be used to facilitate an avoidance action to be taken relative to the train.
US09569965B1	System and method for providing vehicle and fleet profiles Disclosed are a computer systems, methods and products including at least one computer processor and computer readable storage medium or media including computer code and at least one storage device in which is stored GPS data for a plurality of vehicles. One or more processors are programmed at least to receive GPS event data transmitted from a plurality of GPS devices, each GPS device associated a vehicle; for each vehicle, store in a memory operatively coupled to at least one of the processors, the GPS event data; analyze the GPS event data to derive a plurality of operational metrics for each vehicle; and provide, for a graphic user interface, an interactive display configured display a graphic presentation of at least one operational metric for each of a plurality of vehicles.
US09569964B2	Warning system for advising of dangerous situations in an agressive setting The present invention relates to a warning system for advising of dangerous situations in an aggressive setting. The warning system for advising of dangerous situations in an aggressive setting comprises at least one radiofrequency beacon (3-9) and at least one radiofrequency badge (11-17). The beacon comprises a means (3, 5) for emitting a magnetic field wave. The badge comprises a means (13, 15) for receiving the magnetic field wave radiated by the beacon. The badge comprises a means (17) for emitting a wave at very high frequency, activated by the means (13, 15) for receiving the magnetic field wave radiated by the beacon and the beacon comprises a means (7, 9) for receiving the very high frequency wave emitted by the badge, said means (7, 9) for receiving the very high frequency wave activating a warning facility for advising of dangerous situations.
US09569959B1	Predictive analysis for threat detection Systems and methods for threat detection include receiving data regarding a vehicle currently detected in the area. One or more characteristics of the currently detected vehicle may be compared to a model of previously detected vehicles. Based on the comparison, the one or more characteristics of the currently detected vehicle may be determined to be anomalous.
US09569954B2	Method and system for controlling a vehicle with a smartphone A remote control system for controlling a vehicle with a smart phone. The system includes the smart phone programmed with an application that can be installed in the phone via a computer or downloaded from the Internet. The system also includes the vehicle that has been equipped with a radio antenna adapted for communication with the smart phone, an electric power source, servo controller drive motor and a programmable microcontroller (including sensors) and a servo controller steering motor.
US09569950B1	Lost and found system for personal items A system for facilitating the recovery of a user's lost item is provided that makes use of tags the user applies to the item and an interactive voice response (IVR) system. When a finder of the item calls a phone number displayed on the tag, the finder is directed to the IVR system. The finder is prompted to identify the item by providing a unique code displayed on the tag. Once the finder provides the unique code, a server in the system receives the phone number and unique code from the IVR system and verifies if there is a user associated with the tag. If so, the server sends a response back to the IVR system to obtain the finder's message indicating the location of the item. After the finder leaves a message, the message is transmitted automatically to the user in real time.
US09569949B1	Smartphone charging alarm feedback device An alarm feedback circuit for alerting Smartphone users when the Smartphone internal battery is fully charged is provided. The alarm feedback circuit includes necessary circuitry sufficient to monitor the current draw of the Smartphone internal battery and provide a visual and audible alarm once the Smartphone battery is fully charged. The alarm feedback circuit is configured to be used with Smartphone chargers of the type considered to be compatible with the European Union specification for a common External Power Supply (EPS) which are used for Smartphones and adopted by the majority of the world's largest Smartphone manufacturers.
US09569944B2	Method and system for state-based power management of asset tracking systems for non-statutory assets A method and system for power consumption management for moveable assets is provided. Various states and modes are defined, in which elements of the system may operate, each state and mode having different power requirements based on different operational requirements and communication paradigms. Various triggers may indicate which state and mode to be in, with the lowest power consumption operating status being selected whenever possible based on the triggers.
US09569940B2	Identification of ports from which cables have been recently removed and that have the same physical form factor using existing visual port indicators An electronic device has a number of ports that have the same physical form factor and that are receptive to cable insertion. The electronic device also has visual indicators corresponding to the ports. Each visual indicator indicates at least link establishment when a cable has been inserted into its corresponding port and a link has been established. When a cable is removed from a port, the electronic device controls its corresponding visual indicator to identify the port as one from which cable removal has recently occurred.
US09569931B1	Incentivized task completion using chance-based awards A game provided to users of a game space may include a task to be performed by the users. A plurality of virtual chance items may be composed. Individual ones of the virtual chance items may be configured to be activated by the users in the game space to obtain virtual awards in the game space. The virtual awards may include one or more primary awards and one or more secondary awards. Composing the virtual chance items may include determining probabilities that the individual virtual chance items will provide a primary award and/or a secondary award upon activation. The virtual chance items may be distributed to the users that complete the task responsive to these users completing the task. The virtual awards may be provided to the users in accordance with the probabilities assigned to the virtual chance items in response to the users activating the virtual chance items.
US09569926B2	Discounted credits as incentive to play gaming devices In the present embodiments, offering credits for gaming machine play in excess of the cash used to purchase the credits may incentivize various player behaviors. Such behaviors may include remote enrollment in the player-tracking system—and payment for the credits—via a web browser; wagering a minimum amount; and wagering within a predefined time period.
US09569921B2	Player driven game download to a gaming machine A service window may be provided to a gaming machine, such as a video slot machine, video poker machine, or similar electronic device. The service window may include an option to request an available game for download. A request for the game may be received via the service window and the game may be provided to the gaming machine.
US09569920B2	Systems and methods for remote gaming A mobile gaming device may be a player's own personal tablet, smartphone, PDA, etc., with an application program installed via the internet for carrying out a remote gaming session. All gaming functions are carried out by a stationary gaming terminal communicating with the mobile device, such as by using WiFi. The mobile device operates as a user interface. Registration for the mobile device may be via a registration terminal connected in a network with a plurality of gaming terminals. The mobile device may communicate wirelessly with the registration terminal, and the registration terminal then communicates with the played gaming terminal via the network. The mobile device may select to play games offered by any available gaming terminal. The gaming terminals may be gaming machines. The registration terminal may also be a cashing out terminal and print a ticket.
US09569919B2	Architecture for server-based casino gaming machine system A gaming terminal has a game process layer for executing different game application and a system process layer for executing machine functions, such as controlling peripherals of the gaming terminal, wherein the game applications and system processes may be implemented using different protocols. The gaming terminal also includes a game server and a control server which may communicate with one another via an integration or translation protocol. The gaming terminal can thus execute generic game code or game code configured in accordance with varying protocols from different vendors rather than a single, proprietary protocol, and can still use a single unique system protocol for controlling the machine functions.
US09569916B2	Gaming method and apparatus for facilitating a game involving 2D and 3D play areas Various embodiments are disclosed concerning games that use both 2D and 3D play areas. Various embodiments concern representing a 3D structure composed of a plurality of 3D shapes having a plurality of faces, presenting a plurality of elements, marking the plurality of faces and the elements, identifying a first set of one or more combinations of corresponding markings, moving the shapes of the three dimensional structure relative to the elements, and identifying a second set of one or more combinations of corresponding markings, each of the combinations of corresponding markings from the first set and the second set composed of markings from at least one of the elements and multiple faces of the shapes.
US09569915B2	Gaming device having a second separate bonusing event A gaming system wherein a second game is triggered once a specific event occurs in a first game.
US09569910B2	Banknote processing device and cash-out and cash-in mechanism thereof A banknote dispensing/receiving mechanism of a banknote processing device includes a housing and a baffle, the baffle is an elastic retaining piece, the elastic retaining piece has one end fixed with respect to the housing and another end being a free end, and the elastic retaining piece is located in the discharging route of banknotes. When the banknote dispensing/receiving mechanism operates, after the banknotes being discharged by a banknote-dispensing conveying mechanism, the banknotes fall onto the elastic retaining piece, and the elastic retaining piece provides a supporting force for the banknotes. When all the banknotes are discharged, the banknotes are pushed by a banknote pushing plate to apply a pushing force to the elastic retaining piece, and at this moment the elastic retaining piece generates a plastics deformation, which makes the banknotes and the banknote pushing plate pass through the elastic retaining piece together, to further perform subsequent operations.
US09569906B2	PCDA-PHBV electrospun adherent mats as authentication feature The present invention discloses the adherent PHBV-PCDA electrospun mats on paper for use as an authentication feature. Further disclosed herein is the process for preparation of adherent PHBV-PCDA electrospun mats and use of the above product to authenticate cigarettes.
US09569905B2	Electronic voting system A method is described that involves creating a private key and a public key cryptographic key pair, generating a unique and random identifier for a voter's vote and accepting an election vote from said voter. The vote and identifier are electronically signed with the private key to create a digital signature. The vote and identifier are provided in a human readable format to the voter.
US09569904B2	Intelligent entrance guard unlocking system and unlocking method thereof An intelligent entrance guard unlocking method includes: transmitting electric energy of an intelligent entrance guard by wireless electromagnetic radiation via a transmit coil; receiving the electric energy via a receive coil of a powerless smart key; scanning an eye of a user to recognize an iris image of the user and storing the iris image in a second storage unit of the powerless smart key; controlling a wireless transmit unit of the powerless smart key to transmit a wireless signal containing the iris image to the intelligent entrance guard; obtaining a predefined iris image from a first storage unit of the intelligent entrance guard and comparing the iris image with the predefined iris image; unlocking the intelligent entrance guard when the iris image matches with the predefined iris image and not unlocking the intelligent entrance guard when the iris image does not match with the predefined iris image.
US09569903B2	Vehicle control apparatus A vehicle control apparatus is disclosed, which includes an actuator that is provided on a vehicle and performs a door closing operation of the vehicle; a reservation part; a storage part that stores reservation information; a portable terminal; a communication apparatus that is provided on a vehicle to bi-directionally communicate with the portable terminal; and a controller that causes, when the reservation information is stored in the storage part, the actuator to start the door closing operation when a distance between the communication apparatus and the portable terminal is within a first predetermined range, and causes, during the door closing operation of the door, the actuator to stop the door closing operation when the distance is within a second predetermined range that is adjacent to the first predetermined range.
US09569901B2	Electronic control unit that performs a life-extending control, and a vehicle control system that includes the electronic control unit An electronic control unit has a main controller that controls a drive of an actuator and a life-extending control instruction section that requests the main controller to change a drive condition of the actuator. The life-extending control instruction section includes a failure estimator that updates and outputs a failure rate based on a state of a control object, a life-extending control database that stores a failure rate reduction control of a monitoring object including the actuator, which reduces the failure rate of the monitoring object, when a failure of the monitoring object is estimated, and a control selector that searches the life-extending control database and selects a candidate control based on the failure rate of the monitoring object outputted from the failure estimator. The control selector requests the main control section to perform a life-extending control that changes an operation condition of the actuator.
US09569900B2	Timepiece with secondary display for showing logged event times A timepiece is presented that is adapted for recording the times of important events throughout the day. The timepiece comprises a primary display for viewing the current time of day and a secondary display for sequentially viewing one of a plurality times logged throughout the day corresponding with the important event. Interactive buttons on the timepiece facilitate the viewing and logging of the times displayed on the secondary display. A first button is a push button mechanism that records a time within the memory of the timepiece. A second button facilitates the scrolling of times on the secondary display for viewing by an individual. The timepiece can be utilized for recording the times of meaningful events throughout the day. For instance, the present invention may be utilized for recording how often a loved one is thought of or for when medication was last taken.
US09569898B2	Wearable display system that displays a guide for a user performing a workout There is provided a display control device including an action information acquisition unit that acquires, at an action position of one actor, action information regarding a past action of another actor, an object generation unit that generates a virtual object for virtually indicating a position of the other actor during an action of the one actor based on the acquired action information, and a display control unit that causes a display unit displaying a surrounding scene to superimpose and display the generated virtual object during the action of the one actor.
US09569896B2	Glass type mobile terminal A glass type mobile terminal is provided. The mobile terminal includes a band frame wearable on a user's head, a light transmissive lens coupled to the band frame to be located in front the user wearing the band frame, the light transmissive lens comprising a transparent screen where an image is focused, a projector for outputting an image toward the transparent screen from a lateral surface of the light transmissive lens, a photo shutter coupled to a front surface of the lens, with a controllable transparency, and a controller for controlling the transparency of the photo shutter, such that the visibility of the image focused on the light transmissive lens may be enhanced by controlling the transparency of the light transmissive lens, using the photo shutter, that a clear image may be seen even in a bright place.
US09569889B2	Hardware management and reconstruction using visual graphics In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.
US09569885B2	Technique for pre-computing ambient obscurance One embodiment of the present invention includes techniques for pre-computing ambient shadowing parameters for a computer-generated scene. A processing unit retrieves a reference object associated with the computer-generated scene and comprising a plurality of vertices. For each vertex in the plurality of vertices, the processing unit computes a local ambient shadowing parameter, and stores the local ambient shadowing parameter in a memory. For each instance of the reference object included in the computer-generated scene, the processing unit computes a first global ambient shadowing parameter based on the position of the instance within the computer-generated scene, and stores the first global ambient shadowing parameter in the memory. One advantage of the disclosed embodiments is that ambient obscurance is applied to instance objects in a scene in real time while reducing memory space dedicated to storing the AO parameters.
US09569877B2	Method and device for adapting a graphical effect A method in an electronic device for adapting a graphical effect used in a Graphical User Interface, GUI, comprised in the electronic device for interacting with a user of the electronic device is provided. The electronic device is associated with at least one database. At least one software application using the graphical effect is running on the electronic device. The electronic device is adapted to detect a number of times the at least one application is started, save the detected number of times in the at least one database, and change a time for the graphical effect to be shown based on the detected number of times the at least one application is started, whereby performance of the graphical effect is improved.
US09569876B2	Animation control method for multiple participants A computer system is used to host a virtual reality universe process in which multiple avatars are independently controlled in response to client input. The host provides coordinated motion information for defining coordinated movement between designated portions of multiple avatars, and an application responsive to detect conditions triggering a coordinated movement sequence between two or more avatars. During coordinated movement, user commands for controlling avatar movement may be in part used normally and in part ignored or otherwise processed to cause the involved avatars to respond in part to respective client input and in part to predefined coordinated movement information. Thus, users may be assisted with executing coordinated movement between multiple avatars.
US09569868B2	Generating Voronoi treemaps A system described herein includes a receiver component that receives a tree-structured dataset that includes multiple branches that are hierarchically related to one another. The system also includes an executor component that causes a programmable graphical processing unit to generate a Voronoi treemap based at least in part upon the tree-structured dataset, wherein the Voronoi treemap comprises a plurality of subareas that correspond to the multiple branches, and wherein the Voronoi treemap represents hierarchical relationships between the multiple branches.
US09569865B2	Supporting color fonts A system includes a computing device that includes a memory configured to store instructions. The computing device also includes a processor to execute the instructions to perform operations that include receiving information that indicates whether an asset presenter being executed by a computing device is capable of presenting one or more colored fonts of a web asset. In response to receiving the information, sending color font information to the computing device to allow content of the web asset represented in colored fonts to be presented by the computing device.
US09569864B2	Method and apparatus for projection image generation from tomographic images A method for generating a projection image from tomographic images first captures (S101) a number of stacked two-dimensional tomographic images representing a tomographic volume. The pixels of the stacked two-dimensional tomographic images are weighted (S102) along a number of projection beams through the tomographic volume with weighting factors that are chosen under the constraint that the sum of all squared weighting factors for each individual projection beam is between a given lower limit and a given upper limit. Then the weighted pixels are summed up (S103) along the number of projection beams for generating the two-dimensional projection image.
US09569863B2	System for accelerated segmented MR image data acquisition A system for accelerated segmented magnetic resonance (MR) image data acquisition includes an RF (Radio Frequency) signal generator and a magnetic field gradient generator. The RF signal generator generates RF excitation pulses in anatomy and enabling subsequent acquisition of associated RF echo data. The magnetic field gradient generator generates magnetic field gradients for anatomical volume selection, phase encoding, and readout RF data acquisition in a three dimensional (3D) anatomical volume. The RF signal generator and the magnetic field gradient generator acquire consecutive segments of k-space line data representative of an individual image slice in a gradient echo method by adaptively varying RF excitation pulse flip angle between acquisition of the consecutive segments.
US09569862B2	Bandwidth reduction using texture lookup by adaptive shading An example method of providing a solid texture map to a graphics processing unit (GPU) includes dividing a tile of renderable content into a plurality of partitions. The method also includes determining that a set of partitions of the plurality of partitions is a solid color. The method further includes generating a solid texture map indicating that the set of partitions of the plurality of partitions is a solid color. The method also includes providing access to the solid texture map to a GPU.
US09569861B2	Image processing device and image processing method for encoding a block of an image Provided is an image processing apparatus including a prediction section that generates a predicted value of a color difference component of a pixel of an image to be decoded by using a function of a value of a corresponding luminance component, a coefficient calculation section that calculates a coefficient of the function used by the prediction section by referencing a pixel around a block to which the pixel belongs, and a controller that controls a ratio of a number of reference pixels used by the coefficient calculation section to a block size of the block.
US09569859B2	System and method for redefining depth-based edge snapping for three-dimensional point selection An information handling system includes a three dimensional camera and a processor. The three dimensional camera is configured to capture a three dimensional image. The processor is configured to provide the three dimensional image to be displayed on a display screen of the information handling system, to detect a selection of a pixel within the three dimensional image, and to redefine the selected pixel to be a second pixel. The second pixel has a large disparity within the three dimensional image or its two dimensional counterpart.
US09569857B2	Conversion of digital images into digital line drawings Techniques described herein convert digital images into images suitable for use as coloring book pages and the like. The techniques include applying a smoothing operator to at least one channel image of a digital input image to form at least one smoothed image. A scaling operator is then applied to the at least one smoothed image to form at least one scaled image. A tone equalization operator is then applied to the at least one scaled image to form at least one equalized image. An edge detection operator is then applied to the at least one scaled image to form at least one edge image. In addition, a threshold operator is applied to the at least one edge image to form at least one threshold image. A digital line drawing is then created based at least in part on the at least one threshold image.
US09569852B2	Alignment method An alignment method includes: a storage step that images a first workpiece on a chuck table and stores positions of alignment marks corresponding to scheduled division lines and positional relationships of the division lines with the alignment marks; a holding step that holds a second workpiece with the chuck table; a detection step that images positions of the alignment marks on the second workpiece, the positions corresponding to the stored alignment mark positions, and detects the alignment marks of the second workpiece; and an identification step that identifies positions of scheduled division lines of the second workpiece on the basis of the detected positions of the alignment marks of the second workpiece and the stored positional relationships. If one of the alignment marks of the second workpiece cannot be detected at one of the stored alignment mark positions, the detection step detects other adjacent alignment marks.
US09569851B2	Sequencing products recognized in a shelf image A method for sequencing products on a retail shelf, or other objects, recognized in an image of the retail shelf includes detecting products in the received image and calculating a final sequence position for each detected product. The final sequence position is calculated by generating a region of interest for each detected product in the received image, generating a plurality of unique raster numbers for each region of interest using a raster number equation by varying parameters of the raster number equation based on pixel coordinates of each region of interest, determining a plurality of sequence positions for each region of interest using the plurality of unique raster numbers, and determining the final sequence position for each region of interest using the plurality of sequence positions for each region of interest. The disclosure also includes systems for implementing the method.
US09569849B2	System, method, and computer program product for indicating hostile fire A network for indicating and communicating detection of hostile fire, and systems, methods, and computer program products thereof. Hostile fire is optically detected and identified at a first vehicle and such identification is transmitted from the first vehicle to one or more other vehicles in the network. Data regarding hostile fire directed at the first vehicle can be stored at one or more of the other vehicles and even retransmitted to other vehicles or base stations.
US09569841B2	Medical image processing apparatus and medical image generation method The present invention is a medical image processing apparatus which acquires medical image data on a diagnosing object, the apparatus including: a signal enhancement processing part which performs a signal enhancement process on the medical image data; a noise removal part which performs a noise removal process on the medical image data; a first signal compression processing part which compresses the medical image data on which the signal enhancement process and the noise removal process have been performed; a second signal compression processing part which compresses the medical image data; and a synthesis processing part which synthesizes the medical image data having been compressed in the first signal compression processing part and the medical image data having been compressed in the second signal compression processing part.
US09569840B2	Method and apparatus for selecting seed area for tracking nerve fibers in brain A method for selecting a seed area for tracking nerve fibers in a brain includes performing registration of an atlas which shows a plurality of areas which are included in the brain and image data which relates to the brain, displaying a brain area list with respect to the plurality of areas, selecting a first area from the atlas based on a first user input with respect to the brain area list, extracting an area of the image data which corresponds to the first area, as a seed area, based on a result of the registration, and generating a first image which corresponds to the seed area from the image data, and displaying the generated first image.
US09569839B2	Image processing apparatus, method and medical image device An image processing apparatus according to an embodiment includes an input extraction unit, and a parameter estimation unit. The input extraction unit configured to extract, from time sequence images of medical images obtained by performing a blood perfusion imaging scan on a tissue, a region where a main vessel supplying blood input to the tissue is located as an input part and obtain, based on the input part, a time-density sequence of the blood input as an input time sequence. The parameter estimation unit configured to estimate parameters in a model representing the change of the blood flow at each point in the tissue with the input time sequence, based on the input time sequence, the model and the time sequence images, wherein the parameters include a delay undergone by the blood when flowing from the input part to each point in the tissue.
US09569838B2	Image processing apparatus, method of controlling image processing apparatus and storage medium An image processing apparatus comprises: detection means for detecting a region corresponding to a diseased part reference region other than a diseased part region in an input image; and identifying means for identifying the diseased part region based on the corresponding region detected by the detection means.
US09569834B2	Automated image-based process monitoring and control Methods and devices are disclosed for automated detection of a status of wafer fabrication process based on images. The methods advantageously use segment masks to enhance the signal-to-noise ratio of the images. Metrics are then calculated for the segment mask variations in order to determine one or more combinations of segment masks and metrics that are predictive of a process non-compliance. A model can be generated as a result of the process. In another embodiment, a method uses a model to monitor a process for compliance.
US09569832B2	Object based image processing A method includes receiving image data corresponding to an image and determining object quality values based on a portion of the image data. The portion corresponds to an object represented in the image. The method also includes accessing object category metrics associated with an object category corresponding to the object. The method includes generating a notification indicating that the image data has been altered in response to a result of a comparison of the object quality values to the object category metrics. The result indicates alteration of the portion of the image data.
US09569825B2	Image processing device, monitoring camera, and image processing method An image processing device for correcting atmospheric turbulence in a first input image included in a video includes: a determination unit which determines an atmospheric turbulence intensity which indicates an intensity of the atmospheric turbulence; and a correction unit which corrects the atmospheric turbulence in the first input image, according to the atmospheric turbulence intensity determined by the determination unit, wherein the atmospheric turbulence intensity determined by the determination unit has a value that increases with an increase in a ratio of a total number of pixels each having a difference in pixel value between the first input image and a frame temporally preceding the first input image to a total number of edge pixels included in the first input image or the frame temporally preceding, the difference being a predetermined threshold or more.
US09569822B2	Removing noise from an image via efficient patch distance computations In embodiments of removing noise from an image via efficient patch distance computations, weights are computed for patches of pixels in a digital image, and the computed weights are multiplied by respective offset values of offset images that are pixelwise shifted images of the entire digital image. The weights can be applied to the pixels in the digital image on a patch-by-patch basis to restore values of the pixels. Additionally, the digital image can be pixelwise shifted to generate the offset images of the digital image, and the digital image is compared to the offset images. Lookup tables of pixel values can be generated based on the comparisons of the digital image to the offset images, and integral images generated from the lookup tables. Distances to the patches of pixels in the digital image are computed from the integral images, and the computed weights are based on the computed distances.
US09569819B2	Coding of depth maps Various implementations are described. Several implementations relate to filtering of depth maps. According to a general aspect, a first depth picture is accessed that corresponds to a first video picture. For a given portion of the first depth picture, a co-located video portion of the first video picture is determined. A video motion vector is accessed that indicates motion of the co-located video portion of the first video picture with respect to a second video picture. A second depth picture is accessed that corresponds to the second video picture. A depth portion of the second depth picture is determined, from the given portion of the first depth picture, based on the video motion vector. The given portion of the first depth picture is updated based on the depth portion of the second depth picture.
US09569818B2	Ultrasonic image processing apparatus There is provided an ultrasound image processing apparatus which displays an ultrasonic image with a higher resolution. In a received frame, a first pixel array, a second pixel array, and a third pixel array are defined in depths different from each other. For each pixel of interest on the first pixel array, a pattern matching process is applied between the first pixel array and the second pixel array, to calculate a mapping address on the second pixel array for the pixel of interest. In addition, for each pixel of interest on the third pixel array, a pattern matching process is applied between the third pixel array and the second pixel array, to calculate a mapping address on the second pixel array for each pixel of interest. The second pixel array is re-constructed into a high-density pixel array using pixel values and mapping addresses of a plurality of pixels of interest.
US09569812B1	View rendering from multiple server-side renderings A first user input is received when a client program executed by a client computing device is in a first state. The first user input is sent to a server computing device to render a view of a virtual scene. A state change from the first state in the client program due to a second user input or a program event is identified. One or more gaps in a server-rendered current view due to the state change are determined. A rendering of the one or more gaps is selected from among the server-rendered current view, a server-rendered predicted view and one or more prior-rendered views. A current view is rendered using a simplified model of the virtual scene by rendering the one or more gaps from the selected rendering. The current rendered view is visually presented via a display of the client computing device.
US09569811B2	Rendering graphics to overlapping bins In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
US09569810B2	Apparatus and method for embedding data in object and apparatus and method for extracting embedded data According to an embodiment, a data embedding apparatus includes a data acquisition unit and an object generation unit. The data acquisition unit acquires first data formed from a first bit string to be embedded in a first object including a first line segment or a first curve. The object generation unit generates a second object, which includes a deformed line segment or a deformed curve having a displacement corresponding to the first bit string with respect to the first line segment or the first curve and in which the first data is embedded, by deforming at least one of the first line segment and the first curve of the first object based on the first bit string.
US09569808B2	Image processing apparatus, information processing method and storage medium A printing apparatus is provided with a plurality of analyzing units, and a control unit. Each of the plurality of analyzing units analyzes each of different pages of print data, and notifies an error in a case that an analysis error occurs. The control unit receives the error notification from the analyzing unit, at which the analysis error occurs, among the plurality of analyzing units. And, the control unit notifies a cancel to another analyzing unit at which the analysis error does not occur. The control unit is further configured to notify, on a condition that a printing of all pages before a page at which the analysis error occurs is completed, the cancel to the another analyzing unit.
US09569806B2	Dynamic presentation of location-specific information Improved approaches to allow a portable electronic device to dynamically present location-specific information while the portable electronic device is at a predetermined location are disclosed. In one embodiment, the portable electronic device has a display that can display the location-specific information and has wireless capabilities for use in receiving the location-specific information from the server. The location-specific information can, for example, augment other information that is to be presented on the display. In one embodiment, the location-specific information can be information pertaining to a media item being played in an establishment, such as a store, where the portable electronic device is located.
US09569802B2	Invitation management based on invitee's behavior Technologies are generally described for an invitation management scheme. In some examples, an application provider server may include an invitation request receiver unit configured to receive, from an account of a first user, a request to invite a second user to use an application; an interest determination unit configured to determine whether the second user is inclined to use the application based at least in part on behavior information regarding activity in an account of the second user that includes a number of invitations sent to the account of the second user that remain pending; a notification generation unit configured to generate an invitation to be sent to the account of the second user after the interest determination unit determines that the second user is inclined to use the application; and a notification transmitter unit configured to transmit the generated invitation to the account of the second user.
US09569798B2	Risk unit based policies Methods, computer-readable media, systems and apparatuses for determining and implementing risk unit based insurance policies are presented. A user may receive a plurality of risk units associated with an insurance policy. The risk units may be stored in a risk unit account associated with the user, the vehicle, etc. During operation of the vehicle, sensor data may be received. The sensor data may provide information associated with driving behaviors of the user, environmental conditions in which the vehicle is being operated, and the like. A consumption rate of the risk units may be determined based, at least in part, on the received sensor data. If a number of risk units in a risk unit account is below a predetermined threshold, a notification may be transmitted to the user and/or a predetermined number of risk units may be automatically added to the risk unit account.
US09569796B2	Classifying open-loop and closed-loop payment cards based on optical character recognition A user captures an image of a payment card via a user computing device camera. An optical character recognition system receives the payment card image from the user computing device. The system performs optical character recognition and visual object recognition algorithms on the payment card image to extract text and visual objects from the payment card image, which are used by the system to identify a payment card type. The system may categorize the payment card as an open-loop card or a closed-loop card, or as a credit card or a non-credit card. In an example embodiment, the system allows or prohibits extracted financial account information from the payment card to be saved in the digital wallet account based on the determined payment card category. In another example embodiment, the system transmits an advisement to the user based on the determined payment card category.
US09569795B1	Computer-implemented method of capturing transaction data associated with an online purchase A computer-implemented method of captures transaction data associated with a purchase made on a client computer running a web browser client process and coupled over the Internet to an e-commerce server system. In this embodiment, the browser client process includes a script-generated process based on an e-commerce script served to the browser client process. The e-commerce script includes a user-enterable execute command that causes sending of a consummate-purchase command to the e-commerce server system. The method of this embodiment includes serving to the browser client process a capture script, the capture script configured to cause creation of an event log and, on entry of the execute command, to cause sending of the event log to an event server system.
US09569792B2	Electronic commerce web page management Aspects of the present disclosure are directed toward a method, a system, and a computer program product for displaying a change event for a web page. The method includes receiving a change event location located on a web page in a pre-deployment environment. The method includes querying a database to return a plurality of change events for the change event location within a duration period. The duration period includes a start time and an end time. The method includes displaying the plurality of change events from the query. The method includes prioritizing the plurality of change events from the query. The method includes selecting an active change event from the plurality of change events based on the priority. The method also includes displaying the active change event to a user.
US09569791B2	Electronic commerce web page management Aspects of the present disclosure are directed toward a method, a system, and a computer program product for displaying a change event for a web page. The method includes receiving a change event location located on a web page in a pre-deployment environment. The method includes querying a database to return a plurality of change events for the change event location within a duration period. The duration period includes a start time and an end time. The method includes displaying the plurality of change events from the query. The method includes prioritizing the plurality of change events from the query. The method includes selecting an active change event from the plurality of change events based on the priority. The method also includes displaying the active change event to a user.
US09569789B2	System and method for administering marketing programs A system and method provide rewards or loyalty incentives to transaction account customers. The system includes a computing platform comprising application programming interfaces that enable users to define marketing programs. The system thus enables an efficient, automated and extensible platform for creating, managing and executing rewards and other marketing related programs.
US09569787B2	Systems and methods for displaying digital content and advertisements over electronic networks System and methods are provided for analyzing and displaying digital content and advertisements over electronic networks. In accordance with one implementation, a method is provided that calculates, using at least one processor, an engagement metric (including, for example, click probability) for a specific combination of time, promotion slot, and user segment, for an individual promotion of a set of promotions, and calculates a value of a landing page associated with the promotion. The method then can multiply the engagement metric and the value to determine the valuation of the promotion. The method can operate recursively by using previous calculations in later runs of the same method.
US09569785B2	Method for adjusting content of a webpage in real time based on users online behavior and profile The present invention discloses a method for providing adjusted content in a webpage in a website. The method comprising the steps of: tracking visitors that are visiting the monitored website to identify one or more parameters relating to visitor profile, navigation behavior and/or content usage, analyzing the parameters that were identified selecting at least one statistical algorithm, which is relevant for the type of knowledge that was identified, real time monitoring visitor behavior including: profile, navigation path and/or content usage of each visitor in the monitored website, real time analyzing the monitored behavior according to the relevant statistical algorithm and real time replacing or adding content in the webpage to be presented for a specified visitor according analysis results in a specified part of the webpage.
US09569783B2	Advertisement system based on smart card, a method thereof, and smart card applied to the same Disclosed are a system and a method for providing an advertisement service and a smart card applied to the same. The system includes the smart card to extract meta data by searching for accumulated and processed personalized information according to the request for a personalized advertisement from a user terminal, and to provide the URL information for advertisement contents by searching for the advertisement contents, which are embedded based on the SCWS function, according to the meta data to provide the URL information of the advertisement contents. Personalized information is obtained based on the SCWS function and the USIM, and a messaging advertisement service is realized based on the personalized information, so that information focusing on a use extracted through personal behavior analysis is provided.
US09569780B2	Tokenization of user accounts for direct payment authorization channel Embodiments of the present invention disclose a financial institution system maintained by a financial institution and for tokenization of user accounts for using a direct payment authorization channel, whereby a third party payment authorization network is avoided. Embodiments establish a direct channel of communication between the system and a merchant or a merchant network in communication with the merchant; wherein the direct channel of communication comprises a network communication channel without a third party payment authorization system; receive a token issued by the financial institution and associated with a user account associated with a customer of the financial institution; receive transaction data comprising an amount associated with a transaction between the customer of the financial institution and the merchant; and determine whether to authorize the transaction based on the received token and the received transaction data.
US09569777B2	EPassport including shielding method Shielding is associated with RFID tags to achieve new systems and methods having various advantages. These systems include containers configured to store RFID enabled identity documents, the use of RFID tags to monitor the state of a container, and the inclusion of shielding in identity devices. Disclosed are shielded passports, driver's licenses, and the like. Some embodiments further including reading systems for reading identity devices comprising shielding and RFID tags. Further, various switchable RFID devices are disclosed. These switchable RFID devices may include one or more RFID tags and one or more switches. Some of these one or more switches are optionally wireless. In various embodiments, the switchable RFID devices include identity devices, financial devices, remote controls, and the like.
US09569774B2	System and method for processing feedback entries received from software A method and system for processing feedback entries received from software provided by a vendor to an end user machine. The end user machine includes the software, a feedback module, and a database. The feedback module: generates an encryption Ek0 of an identification tag FE(0) using a secret key k(0) where Ek0=E(k(0),FE(0)); generates a parameter Hn0 using a secret key n(0) where Hn0=Hash(n(0)∥Ek0); generates a parameter Hs0 using a secret key s(0) where Hs0=Hash(s(0)∥Ek0); and sends Ek0, Hn0, and Hs0 to the database.
US09569762B2	Replenishing fuel cell powered portable devices Portable electronic devices such as portable telephones, portable computers and the like may obtain power from fuel cells that consume fuel from fuel reservoirs of the portable devices. A network of fueling stations permits users of portable devices to main the devices operational by frequently topping up the fuel reservoirs. Payment systems combine payments for fuel with larger payments for other transactions to avoid the overhead of processing individual payments for very small amounts.
US09569761B2	Text-to-pay for a new subscription A code is communicated between the billing server and subscription server. The billing server receives a code request text message from the user device. The billing server identifies a carrier server from the code request text message. The billing server receives an authorization text message from the user device in response to an authorization request text message and charges an account of the carrier server that has been identified. If the charge has been successful, then the billing server transmits a code redemption text message to the user device including the code and a link to a redemption page of a website of a subscription server. The subscription server processes redemption to a code and transmits an account set up page to the user device.
US09569759B2	Online quick key pay A quick pay option is provided so that a user can make a payment from a merchant site by simply entering in a user identifier in a pop-up window. Limits are set for the quick pay option and may vary between different merchants. The payment provider is able to determine the merchant, user, and transaction information automatically, such that the user may only be required to enter the identifier to process and complete the payment.
US09569757B1	Anticipatory creation of point-of-sale data structures Techniques and arrangements for analyzing previous tickets of a customer at different merchants—specifying interactions of the customer at the different merchants—to determine subsequent recommendations to send to a particular merchant in real-time when the customer is located at the particular merchant. Other techniques and arrangements facilitate annotation of merchant tickets by the merchants to enrich the data maintained by the tickets and, in some instances, to enhance the described real-time recommendations. Still other techniques and arrangements create a merchant ticket for recording interactions between a merchant and customer upon the customer creating a reservation at the merchant for a specified future time, or being added to a waitlist of the merchant. Upon the customer arriving at the merchant proximate to the specified future time, the merchant may use the created ticket to track items ordered by the merchants, track tenders used to pay for items, and the like.
US09569756B1	Systems and methods for image monitoring of check during mobile deposit An image of a check that is in the field of view of a camera is monitored prior to the image of the check being captured. When the image of the check in the field of view passes monitoring criteria, an image may be taken by the camera and provided from the mobile device to a financial institution. The image capture may be performed automatically as soon as the image of the check is determined to pass the monitoring criteria. The check may be deposited in a user's bank account based on the image. Any technique for sending the image to the financial institution may be used. Feedback may be provided to the user of the camera regarding the image of the check in the field of view.
US09569755B2	Financial management system A financial management system includes a client terminal having a financial management application and a graphical user interface. The graphical user interface is configured to display transaction data, enable user modification of the transaction data, and transmit modified transaction data to the financial management application. The financial management system additionally includes a commercial web server capable of conducting online financial transactions. The financial management application receives transaction data regarding an online financial transaction upon completion of the financial transaction.
US09569749B2	Method and system for inventory management system The present invention discloses a computer-implemented method for inventory management system including a plurality of products associated with Quick Reference (QR) codes. The method scans the QR code of a product via a scanning device being operated by a user. The method then receives an input code from the user for the corresponding QR code. The user input code is stored in a relational database and associated with the QR code in the inventory management system. The association of the user input code with QR code enables the user to locate various products in the inventory by searching with the user input code rather than the QR code. The user generated input code can be shared with other devises utilizing the same application.
US09569748B2	Systems and methods for dispensing consumable products Embodiments of the invention can include systems and methods for dispensing consumable products. One embodiment of the invention can provide a product dispenser. The product dispenser can include a controller configured to communicate with a data processing resource, determine that a recipe database update for a recipe of at least one beverage is available at the data processing resource, receive the recipe database update from the data processing resource, and update the recipe of the at least one beverage in a recipe database associated with the product dispenser, wherein an updated recipe comprises an ingredient identifier and an ingredient ratio for an ingredient associated with the ingredient identifier.
US09569741B2	Virtual management of work items Systems and methods are provided to solve these and other problems and disadvantages of the prior art. A list of work items is received. A work item can be anything that a user may work on such as an email, an incoming call in a contact center, a trouble ticket, and the like. A user is identified to work on the list of work items. A virtual setting is created based on the list of work items and the user. The virtual setting includes a virtual list of work items that represents the list of work items and a user avatar that represents the user. The user can select a work item from the virtual list of work items. The user is then presented with the work item. For example, if the work item is an email, the email will be presented. The user can then process the work item.
US09569738B2	Methods and systems for deploying a navigation tool associated with a continuous improvement approach for an enterprise A computer-based method for accessing the various individual tools from multiple continuous improvement programs from a single user interface is described. The method includes generating a user interface with a plurality of selectable icons, each icon corresponding to a predefined continuous improvement (CI) cycle step, providing, upon receiving a user selection of one of the CI cycle steps, user selectable process steps to the user interface, providing, upon receiving a user selection of one of the process steps, user selectable tool choices to the user interface, and generating, upon receiving a user selection of one of the tool choices, at least one interactive user interface that provides at least one of an example of the tool choice and instructions relating to the use of the tool choice.
US09569737B2	Methods and tools for creating and evaluating system blueprints Method and tools for creating and evaluating a set of system blueprints pertaining to the delivery of a system or a project. Each blueprint is an architecture design/specification that enables analysis of each blueprint, families of blueprints and relationships between blueprint layers. A user can create various system blueprints based on data from existing databases containing requirements, solutions, and deployments of a system or project. After creating each blueprint, users may view the blueprint to visually detect problems and further revise the blueprint. In addition, for each type of blueprint, the user can evaluate the blueprint against various metrics and criteria related to requirements, solutions, and deployments and view the evaluation results.
US09569735B1	Member communication reply score calculation In an example embodiment, a supervised machine learning algorithm is used to train a communication reply score model based on an extracted first set of features and second set of features from social networking service member profiles and activity and usage information. When a plurality of member search results is to be displayed, for the member identified in each of the plurality of member search results, the member profile corresponding to the member is parsed to extract a third set of one or more features from the member profile, activity and usage information pertaining to actions taken by the members on the social networking service is parsed to extract a fourth set of one or more features, and the extracted third set of features and fourth set of features is inputted into the communication reply score model to generate a communication reply score, which is displayed visually to a searcher.
US09569733B2	Extracting complex entities and relationships from unstructured data To extract relationships between complex entities from unstructured data, a parser parses, using an existing language model, the unstructured data to generate a parse tree. From the parse tree, a set of tokens is created. A token in the set of tokens includes a set of words found in the unstructured data. The set of tokens is inserted in the existing language model to form an enhanced language model. The unstructured data is re-parsed using the enhanced language model to create a knowledge graph. From the knowledge graph, a relationship between a subset of the set of tokens is extracted.
US09569729B1	Analytical system and method for assessing certain characteristics of organizations A computer readable medium for analyzing and predicting the future behavior of organizations is disclosed. An embodiment of this invention is comprised of one or more repositories of data which involve comments or other actions by actors with some kind of relationship to a target organization, a repository of metadata relating to this data, a repository of updatable models of organizations, a natural language parsing engine, and an engine for generating and comparing the organizational models.
US09569724B2	Using ontological information in open domain type coercion A computer-implemented system, method and program product generates answers to questions in an input query text string. The method includes determining, by a programmed processor unit, a lexical answer type (LAT) string associated with an input query; automatically obtaining a candidate answer string to the input query from a data corpus; mapping the query LAT string to a first type string in a structured resource; mapping the candidate answer string to a second type string in the structured resource; and determining if the first type string and the second type string are disjointed; and scoring the candidate answer string based on the determination of the types being disjointed wherein the structured resource includes a semantic database providing ontological content.
US09569722B2	Optimal persistence of a business process Aspects of the invention provide for automatically selecting optimal fetch settings for business processes as a function of database query load and relational context by monitoring usage of a data retrieval point with respect to a defined unit of work. A multilayer feed-forward neural network is used to predict, as a function of training sets composed of historical data generated by the monitored usage of the data retrieval point, a future value of a data size of results from an eager fetch setting for the data retrieval point. The eager fetch is automatically revised to a lazy fetch setting in response to determining that the future data size value of the eager fetch setting results is larger than a permissible memory resource threshold.
US09569718B2	Card with metal layer and electrostatic protection A metal card or a hybrid metal-plastic includes an acrylic resin protective clear-coat layer and/or a “hard” nano-particle top-coat layer overlying any exposed metal surface in order to insulate the metal and reduce the likelihood of an electrostatic discharge (ESD) or a short circuit condition. In a particular embodiment the “hard” nano-particle top-coat layer overlies the clear coat layer. The dual stage protective layers which include a clear-coat layer and a top-coat ensure that the problem associated with an ESD and/or a short circuit condition is minimized. In addition, the dual stage protection imparted to a card by forming a clear-coat layer and a top-coat layer ensures that any card surface treatment or card decoration is protected over time from excessive wear or scratching due to use in conjunction with a POS device and/or handling.
US09569714B2	System and method for automated RFID quality control A system and method is described for an automated RFID quality control process. The method may include configuring an RFID manufacturing press with quality control specifications, manufacturing a batch of RFID inlays, executing a performance test on each RFID inlay, comparing the results of the performance test to the quality control specifications, and determining a pass or fail status for the batch of RFID inlays based on the results of the performance test. The system may include an RFID manufacturing press having at least one lane, at least one interrogator antenna, and programmable control logic for the RFID manufacturing press, wherein the programmable control logic is adapted to execute a performance test on each RFID relay of a batch of RFID relays output by the manufacturing press, compare the results of the performance test to user-configurable quality control specifications, and determine whether the batch of RFID relays meets the specifications.
US09569713B2	Semiconductor device, wireless sensor, and electronic device To provide a semiconductor device that is capable of displaying data even when a radio signal is not supplied. The semiconductor device includes an antenna, a battery, a sensor, a nonvolatile memory, a first circuit, and a second circuit. Power supplied from the antenna is converted into first power via the first circuit. The battery stores the first power and supplies second power. The sensor performs sensing with the second power. The nonvolatile memory stores analog data acquired by the sensor. The second power is used to store the analog data. The second circuit converts the analog data into digital data with the use of the first power. The nonvolatile memory preferably includes an oxide semiconductor transistor.
US09569711B2	Label for barcodes, letters and images and method for forming barcodes, letters and images An image label is used to present a barcode and characters and images. The label is printed label with a pre-determined color among various colors such that the characters and images resist subsequent erasure due to friction or chemical materials, etc. A laser beam is projected onto a surface of the barcode. A loss layer is used to form an image in response to the projection of the laser beam. A loss sheet includes a transparent sheet that is placed on the loss layer. A dark sheet is attached at the lower part of the loss sheet, and includes a color ink layer that expresses a pre-determined color among various colors and is attached to the upper part of the loss layer. The color ink layer which has the pre-determined color among the various colors is furnished at the upper part of the transparent sheet.
US09569709B2	Data bearing medium An example method for forming a data-bearing medium in accordance with aspects of the present disclosure includes setting variables associated with the data-bearing medium, the variables comprising a bit length of a payload, a row-to-row offset and an interleave period, identifying a standard form of the payload, the standard form being a circularly shifted version of the payload, generating a phase code based on the variables, and arranging rows of the data-bearing medium with the standard form of the payload and the phase code based on the interleave period.
US09569705B2	Method and system for configuring print character information The size of text printed based on font data can be adjusted. A printer has: a print unit that prints an image on a recording medium; a storage unit that stores a font table containing font data for characters, and stores adjustment ratio information specifying a ratio used to scale the size of the font data stored in the font table; a first communication unit that receives print instruction data including information specifying a character; a second communication unit that receives a change instruction instructing changing a ratio specified by the adjustment ratio information; and a control unit that scales the font data of the specified character at the ratio specified by the adjustment ratio information, and controls the print unit to print the character based on the scaled font data.
US09569703B2	Data transfer apparatus and method thereof A reading process is performed to read data of each area, which is divided from image data, from a buffer storing the image data to be performed on a predetermined image process. A transmitting process is performed to transmit the read data of the area to an image processor. A reception process is performed to receive data generated in the predetermined image process from the image processor. A parameter for a writing process is set based on an area size of the received data. A writing process is performed to write the received data to the buffer by data transfer using direct memory access (DMA).
US09569701B2	Interactive text recognition by a head-mounted device A user is assisted in a real-world environment. An assistance engine receives at least one context from the user. The assistance engine also receives a video stream of the real-world environment. The assistance engine performs an optical character recognition process on the video stream based upon the at least one context. The assistance engine generates a response for the user. A microphone on a head-mounted device receives the context from the user. A camera on the head-mounted device captures the video stream of the real-world environment. A speaker on the head-mounted device communicates the response to the user. The user may move in the real-world environment based upon the response to improve the optical character recognition process.
US09569699B2	System and method for synthesizing portrait sketch from a photo The present invention discloses a system and method for synthesizing a portrait sketch from a photo. The method includes: dividing the photo into a set of photo patches; determining first matching information between each of the photo patches and training photo patches pre-divided from a set of training photos; determining second matching information between each of the photo patches and training sketch patches pre-divided from a set of training sketches; determining a shape prior for the portrait sketch to be synthesized; determining a set of matched training sketch patches for each of the photo patches based on the first and the second matching information and the shape prior; and synthesizing the portrait sketch from the determined matched training sketch patches.
US09569694B2	Detection of objects in an image using self similarities An image processor (10) has a window selector for choosing a detection window within the image, and a self similarity computation part (40) for determining self-similarity information for a group of the pixels in any part of the detection window, to represent an amount of self-similarity of that group to other groups in any other part of the detector window, and for repeating the determination for groups in all parts of the detection window, to generate a global self similarity descriptor for the detection window. A classifier (50) is used for classifying whether an object is present based on the global self-similarity descriptor. By using global self-similarity rather than local similarities more information is captured which can lead to better classification. In particular, it helps enable recognition of more distant self-similarities inherent in the object, and self-similarities present at any scale.
US09569693B2	Method and apparatus for object identification and location correlation based on received images A method, apparatus and computer program product are provided for object identification and location correlation based on received images. A method is provided including receiving identity data associated with an object derived from one or more of a plurality of images determining an identity of an object in one or more of the plurality of images, receiving location information associated with a camera which captured the plurality of images, and correlating the identified object with a location for each of the respective images of the plurality of images.
US09569688B2	Apparatus and method of detecting motion mask An apparatus for detecting a motion mask includes: an image processor configured to generate a plurality of image frames; a first motion mask detector configured to detect at least one first motion mask by calculating a local feature of each pixel included in a partial or entire area of at least one current image frame which indicates a pixel value relationship between the each pixel and at least one neighboring pixel, and comparing the calculated local feature with a local feature of a corresponding pixel of at least one previous image frame; a second motion mask detector configured to detect at least one second motion mask based on a difference between the partial or entire area of the current image frame and a corresponding area of the previous image frame; and a motion mask generator configured to generate a final motion mask comprising at least one of the first motion mask and the second motion mask.
US09569686B2	Mobile device field of view region determination A method and system for determining a field of view region on a mobile device display is provided. The method includes receiving by a mobile device from a user facing camera of the mobile device, an image of a user currently using the mobile device. Key features of the image are identified and attributes of the key features are determined. The attributes are analyzed and a specified region within a field of view of an object facing camera of the mobile device is determined. Data associated with the specified region is provided for a software application.
US09569685B2	Image processing apparatus and method for detecting partially visible object approaching from side using equi-height peripheral mosaicking image, and driving assistance system employing the same Provided are an image processing apparatus and method, and a driving assistance system employing the same. The image processing apparatus includes a peripheral region extracting unit extracting, from an image, peripheral regions corresponding to a size of a target object determined in advance, a modifying unit modifying the peripheral regions to allow a viewpoint for the peripheral regions to be changed, a mosaicking image creating unit creating a mosaicking image by stitching the modified peripheral regions together, and an object detection unit detecting an object including a part of the target object from the mosaicking image.
US09569683B2	Removable diffraction assembly for electronic device In various embodiments, a system and method for manufacturing and using an optical enhancement assembly in combination with an image-capturing device are presented. In example embodiments, the optical enhancement assembly is affixed over an aperture on the image-capturing device using a securing agent. Light is allowed to travel through the optical enhancement assembly and into the aperture of the image-capturing device such that the light can be recorded as a still image or video. The optical enhancement assembly includes at least a unique fractalized diffraction pattern that impacts light traveling into the aperture and causes a unique diffraction effect on the image or video recorded by the image-capturing device.
US09569682B2	Image processing apparatus and method to perform noise reduction on an image and determine an output pixel value In a case where a weighted mean value is calculated by calculating weights according to a degree of similarity based on a target pixel, the mean value is affected by noise included in the target pixel. The mean value thereby converges at a value different from a true pixel value without noise and this appears as a remaining noise. To solve this problem, an output value of the target pixel is determined based on a correlation established among a weighted mean value of multiple reference pixels, a pixel value of the target pixel, and the true value of the target pixel.
US09569681B2	Methods and systems for efficient image cropping and analysis A system and method for cropping a license plate image to facilitate license plate recognition by obtaining an image that includes the license plate image, dividing the image into multiple sub-blocks, computing an activity measure for each sub-block; determining an activity threshold, determining that a sub-block is an active sub-block by comparing the activity measure for the sub-block with the activity threshold, generating a second image of the license plate information, where the second image includes the active sub-block, and obtaining the license plate information based on the second image.
US09569679B1	Adaptive image sampling for text detection Various embodiments enable a device to perform an adaptive sampling method for locating text regions in images of natural scenes. Since only a fraction of pixels in an input image correspond to text regions, it is desirable to eliminate non-text regions early in the text detection process. Therefore, in at least one embodiment, an image is sampled horizontally to identify connected pixel regions indicative of text. In this example, each sampled row of the image is tested for containing Maximally Stable Extremal Regions (MSERs) in order to identify regions containing text. If a respective row contains a connected pixel region indicative of text, the neighboring rows are recursively sampled at finer levels in order to fully contain the text and sampling is terminated for regions which are unlikely to contain text. This sampling process can also be performed for the vertical dimension for regions which are determined to contain text.
US09569677B2	Device and method for directing radiation in the direction of an optical element of an image sensing device of a vehicle A device for directing radiation in the direction of an optical element of an image sensing device of a vehicle. The device includes a central area for directing at least one portion of a first incident radiation onto the optical element. The device also includes at least one border area for directing at least one portion of at least one second incident radiation onto the optical element. The at least one second incident radiation runs in the opposite direction or at an obtuse angle with respect to the first incident radiation.
US09569669B2	Centralized video surveillance data in head mounted device An apparatus includes a security location module that tracks a location of a user. The user has a heads-up display with a display that allows viewing by the user of items along with electronic display images. An object identification module identifies an object for tracking using cameras. A selection module selects the identified object for tracking, an object location module identifies a location and direction information of the selected object and an alert module sends the location and the direction information of the selected object to the heads-up display. A display module identifies the selected object in the heads-up display of the user when the object is in the field of view of the heads-up display, or provides instruction on the heads-up display to direct the user to move the heads-up display so that the selected object is in the field of view of the heads-up display.
US09569666B2	Systems and methods for measuring image recognition accuracy Systems and methods for measuring image recognition accuracy are provided. One embodiment of a method includes locating an identifier in an environment, where the identifier is configured according to a predetermined format and where the identifier identifies an actual characteristic of an object. Some embodiments of the method include locating the object in the environment, determining a perceived characteristic of the object, and determining, from the identifier, the actual characteristic of the object. Similarly, some embodiments include comparing the actual characteristic of the object with the perceived characteristic of the object, determining whether the actual characteristic of the object substantially matches the perceived characteristic of the object and, in response to determining that the actual characteristic of the object does not substantially match the perceived characteristic of the object, determining a change to make for improving image recognition.
US09569665B2	Commodity recognition apparatus In accordance with one embodiment, a commodity recognition apparatus detects, from a captured image, an object imaged in the captured image and extracts an appearance feature amount of the object from the image of the object; compares the extracted appearance feature amount with feature amount data of a dictionary file in which feature amount data indicating the surface information of a commodity is stored for each recognition target commodity to calculate a similarity degree indicating how similar the appearance feature amount is to the feature amount data for each recognition target commodity; recognizes whether or not the object is a commodity based on the calculated similarity degree; and specifies and notifies the reason in a case in which the object is not recognized as a commodity.
US09569664B2	Methods for rapid distinction between debris and growing cells Methods of rapid distinction between growing cells and debris, which determine a time-lapse movie of specimen images, track features of each entity, and categorize each entity as growing cells or debris.
US09569662B1	Image recognition and parsing Image recognition and parsing techniques are provided herein. In the described examples, an input image, such as an image of a document (e.g., a scanned document), can be received. Scan mark candidates in the input image can be identified that correspond to blueprint scan marks for a stored set of form blueprints. The blueprint scan marks can indicate form entry areas or other features of a form associated with the form blueprint. Identified scan mark candidates can be compared with the corresponding blueprint scan marks. Based on the comparing, it can be determined that at least some of the scan mark candidates are confirmed scan marks. Based on the confirmed scan marks, one form blueprint can be identified that corresponds to the input image. Information can be extracted from the input image, for example by optical character recognition, based on the form blueprint to which the input image corresponds.
US09569661B2	Apparatus and method for neck and shoulder landmark detection A device is configured to perform a method for neck and shoulder detection. The method includes receiving an image that includes a face. The method also includes performing a neck localization operation on the image. The neck localization operation is performed using results from a pre-trained regression model. The method further includes performing a shoulder localization operation on the image. The method still further includes estimating a plurality of shoulder and neck keypoints using results of the neck localization operation and the shoulder localization operation.
US09569658B2	Image sharing with facial recognition models An image sharing server provides several ways of sharing images between users. After a user contributes images to the image sharing server, the user can interact with the image sharing server to identify and tag people in the images, share the images with other users, and organize the images into memory boxes. Memory boxes can also be shared between users, and multiple users can be granted the ability to add images to a shared memory box. In addition, the image sharing server can prompt a user to share his or her images with other users who contributed related images. The image sharing server also performs facial recognition to automatically identify people in images, and facial recognition models can be shared between users.
US09569653B1	Dark field illumination system obtained in a tilted plane Systems and methods for providing machine-readable symbol readers that make reading difficult direct part marks simple for a user. A dark field illuminator may generate grazing incidence radiation (e.g., less than 45 degrees, less than 30 degrees, less than 20 degrees) in a plane which is tilted with respect to a plane which is normal to an optical axis of the machine-readable symbol reader. Such configuration provides a reading system which is relatively less affected by unwanted scattering caused by irregularities of a surface marked with a machine-readable symbol. Generally, during use users attempt to scan a machine-readable symbol by positioning the front end of the machine-readable symbol reader “head on” or parallel to the marked surface. By providing a front end which is tilted at an angle other than perpendicular with respect to the optical axis, the user is automatically guided to scan machine-readable symbols at an optimum angle.
US09569651B2	Controller for optical information reader In an optical information reader controlled by this controller, a laser beam originating in light emitted by a laser diode is reflected by a scan mirror to scan optical information of a bar code or the like, reflected light therefrom is received by a photodiode to be converted to an electrical signal, and the optical information is read by processing the signal. In the controller, a main amp having a characteristic that a gain changes according to a frequency of an input signal amplifies the electrical signal, a detector detects an analog signal resulting from the amplification, and from a. detection output thereof, a MPU (on/off frequency control circuit) detects level of the analog signal and adjusts the gain of the main amp by changing an on/off frequency of the laser diode caused by an APC circuit (light emission on/off circuit), according to the detected level.
US09569645B2	Portable electronic device The problem of the present invention is to provide a tablet-type portable electronic device that can perform payment by way of a card, as well as having a compact size. A tablet-type portable electronic device of the present invention includes a plate-shaped housing having a front surface, a touch panel and display unit provided to the front surface of the housing, and reading units that perform reading processing of a card related to payment. The reading units are configured integrally with the housing.
US09569640B2	Tamper detection and response in a memory device A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.
US09569638B2	Trusted computing A trusted computing device (TCD) includes an isolated environment, host interface, secure interface, and program instructions. The environment includes an isolated environment processor (IEP), memory (secure and non-secure partition), and an auxiliary processor (AP). Memory and AP are connected for data communication with the IEP, and communicate with a host only through the IEP. The host interface and each secure interface are connected for data communication with the IEP. The instructions provision TCD for cryptographic operations via a secure interface; present a first file system partition comprising a write file and a read file with file creation/deletion privileges allocated only to the IEP at the host interface via the IEP; present a non-secured file system partition with access to the non-secure partition via the host interface via the IEP; receive, via the write file, requests to perform trusted computing; perform requested computing using the IEP, secure memory, and AP; and write results to the read file.
US09569634B1	Fine-grained structured data store access using federated identity management A structured data store service, such as a database service, may implement fine-grained access to data maintained at the database service using federated identity. Fine grained access requests may be received at a database service for specified data maintained for an application provider from a client of the application provider. An access credential may be also be received. Verification of the access credential may be obtained, and the database service may evaluate the fine-grained access request according to a delegation policy corresponding to the access credential to determine whether the fine-grained request is authorized. If authorized, the fine-grained access request may be service. If not authorized, the fine-grained access request may be denied. In some embodiments, multiple application clients may have the same authorization for data, such as read authorization, while another one or more application clients may have different authorization for the data, such as write authorization.
US09569632B2	Information processing apparatus having wireless communication function and method of controlling the apparatus An image forming apparatus that is wirelessly connectable with an external device receives a processing request from the external device via wireless communication, and performs processing corresponding to the processing request. A determination is made whether security settings used in the wireless communication satisfy a predetermined condition, and if the security settings do not satisfy the condition, a security level in the image forming apparatus is set to a predetermined level.
US09569627B2	Systems and methods for governing content rendering, protection, and management applications System and methods are disclosed for governing digital rights management systems and other applications through the use of supervisory governance applications and keying mechanisms. Governance is provided by enabling the supervisory applications to revoke access keys and/or to block certain file system calls, thus preventing governed applications from accessing protected electronic content.
US09569624B1	Recording third party content to a primary service provider digital video recorder or other storage medium Recording of third party content on recording systems of a primary service provider is provided. Third party service providers may provide information about offered video content to a primary content service provider. The primary service provider may allow its customers/subscribers to access the third party content through the systems of the primary service provider. Upon navigation to a desired third party content item, a customer/subscriber may request a recording of the third party content. The third party content may be passed to the primary service provider for recording on one or more storage systems associated with the primary service provider, and the recorded content may subsequently be played back by the customer/subscriber in the same manner as play back of content recorded from the primary service provider.
US09569622B2	Self-measuring nonvolatile memory device systems and methods One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions and a first pointer, in which the first pointer identifies a first one or more memory addresses in the nonvolatile memory where at least a portion of the startup routine instructions are stored, and a microcontroller that retrieves the startup routine instructions from the nonvolatile memory using the first pointer and determines whether the startup routine instructions are corrupted before executing any portion of the startup routine instructions. The computing system further includes a central processor communicatively coupled to the boot device, in which the central processor executes the startup routine instructions to initialize the computing system when the microcontroller determines that the startup routine instructions are not corrupted.
US09569620B2	Method for processing UEFI protocols and system therefor A Unified Extensible Firmware Interface protocol installer utilizes and modifies a list of global unique identifiers corresponding to Unified Extensible Firmware Interface protocols to determine whether to install a UEFI protocol.
US09569619B1	Systems and methods for assessing internet addresses A computer-implemented method for assessing Internet addresses may include (1) identifying an Internet Protocol address, (2) identifying a plurality of files downloaded from the Internet Protocol address, (3) generating an aggregation of security assessments that relates to the Internet Protocol address and that may be based at least in part on a security assessment of each of the plurality of files, (4) determining a trustworthiness of the Internet Protocol address based at least in part on the aggregation of security assessments and (5) facilitating a security action based at least in part on the trustworthiness of the Internet Protocol address. Various other methods, systems, and computer-readable media are also disclosed.
US09569615B2	Cyber security Systems and methods that use probabilistic grammatical inference and statistical data analysis techniques to characterize the behavior of systems in terms of a low dimensional set of summary variables and, on the basis of these models, detect anomalous behaviors are disclosed. The disclosed information-theoretic system and method exploit the properties of information to deduce a structure for information flow and management. The properties of information can provide a fundamental basis for the decomposition of systems and hence a structure for the transmission and combination of observations at the desired levels of resolution (e.g., component, subsystem, system).
US09569614B2	Capturing correlations between activity and non-activity attributes using N-grams Identifying correlations between events recorded in a computer system log, the recorded events are generated by a plurality of processes executing on the computer. A system log is partitioned into a plurality of segments, each segment associated with a characteristic found in an event, each segment including one or more events having a same characteristic value. A plurality of attributes of the events in a segment are selected. The attributes selected do not describe an action of the event. One or more distinct n-grams are generated, each distinct n-gram including the selected attributes from successive events within the segment. A distinct n-gram is distinct from all other generated n-grams. A correlation is identified for each first selected attribute of each successive event of an n-gram with all other second selected attributes from each successive event of the n-gram, and the correlations are recorded for each first selected attribute.
US09569613B2	Techniques for enforcing control flow integrity using binary translation Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
US09569605B1	Systems and methods for enabling biometric authentication options A computer-implemented method for enabling biometric authentication options may include (1) identifying a device that includes a biometric authentication option that provides access to a protected feature of the device and that is based on a biometric trait and an initial authentication option that provides access to the protected feature and that is not based on the biometric trait, (2) detecting an authentication action that is performed by a user on the device that provides access to the protected feature via the initial authentication option, (3) capturing biometric data describing the biometric trait of the user in connection with the user performing the authentication action on the device, and (4) using the biometric data as training data for the biometric authentication option to enable the user to access the protected feature of the device via the biometric authentication option. Various other methods, systems, and computer-readable media are also disclosed.
US09569604B2	User access control to a secured application Embodiments described herein provide approaches for user access control to a secured application. Specifically, a custom authentication tool is configured to intercept a request from a user for access to a secured application and override one or more default requirements (e.g., application pre-registration, for accessing the application). That is, when credentials of the user are received at the authentication tool, they are verified against data within a user directory to generate a user profile, which is then provided to the secured application to satisfy the requirements for granting access to the user. As such, the secured application's requirements are met, yet users do not have to manually pre-register to obtain access because the registration is performed in the background by the authentication tool.
US09569600B2	Information processing apparatus with license information management A license management system including an information processing apparatus includes a detecting unit and a license update requesting unit. The detecting unit detects a status of an element involved in execution of software. The license update requesting unit requests an update of license information of the software if the status detected by the detecting unit is a status that does not satisfy a condition desired for executing the software. The license management system may be usable within an image forming apparatus and include a user interface having an IC card reader.
US09569592B2	Point-of-care medication dispensing A medication dispenser is provided, comprising a securable container configured to store one or more doses of one or more medications and an access device configured to selectably permit access to the one or more doses of the one or more medications. The medication dispenser further comprises an electronic interface configured to acquire user input from a user and a processor. The processor is configured to perform the steps of comparing the user input to a database, selecting, responsive to the comparing, an appropriate dose from the one or more doses, and permitting access through the access device to the appropriate dose. A method for dispensing medication is also provided. The method comprises the steps of locating a medication dispenser at a point-of-care, acquiring user input from a user at the point-of-care, comparing the user input to a database, selecting, responsive to the comparing, an appropriate dose from the one or more doses, and permitting access through the access device to the appropriate dose.
US09569591B2	Configurable user interface systems for hospital bed Configurable user interface systems for a patient support structure are disclosed. As described a control interface comprises the capability to allow limited impact on processes deemed important when other applications and programs are run. The configurable user interface systems described herein allow for customized display of information and display options available to a user in various environments.
US09569589B1	System, medical item including RFID chip, data collection engine, server and method for capturing medical data A system includes a plurality of RFID chips affixed to medical items, a data collection engine device, and a server device. The data collection engine wirelessly transmits power to a first one of the RFID chips and receives first medical data from the first RFID chip while the first RFID chip is activated by the power receiver. The data collection engine generates a first message indicative of the first medical data to be sent to the server device. The server device can determine aspects of the medical items such as position and consumption based upon the first medical data.
US09569588B2	Attached personal information device An information storage device may be semi-permanently attached to a wearer. The device can include an outer casing configured to be compatible with long term contact with a human body. A data storage component may store information of the wearer and a transceiver may wirelessly communicate information from the data storage component. The stored information can be, for example, the complete medical history of the wearer, “emergency” medical information, prescriptions, medical warnings (e.g., past history of coronary problems), financial information, social security numbers, or other useful information.
US09569586B2	Algorithm for modification of somatic cancer evolution Most clinically distinguishable malignant tumors are characterized by specific mutations, specific patterns of chromosomal rearrangements and a predominant mechanism of genetic instability. It has been suggested that the internal dynamics of genomic modifications as opposed to the external evolutionary forces have a significant and complex impact on Darwinian species evolution. A similar situation can be expected for somatic cancer evolution as the key mechanisms encountered in species evolution such as duplications, rearrangements or deletions of genes also constitute prevalent mutation mechanisms in cancers with chromosomal instability. The invention is an algorithm which is based on a systems concept describing the putative constraints of the cancer genome architecture on somatic cancer evolution. The algorithm allows the identification of therapeutic target genes in individual cancer patients which do not represent oncogenes or tumor suppressor genes but have become putative therapeutic targets due to constraints of the cancer genome architecture on individual somatic cancer evolution. Target genes or regulatory elements may be identified by their designation as essential genes or regulatory elements in cancer cells of the patient but not in normal tissue cells or they may be identified by their impact on the process of somatic cancer evolution in individual patients based on phylogenetic trees of somatic cancer evolution and on the constructed multilayered cancer genome maps. The algorithm can be used for delivering personalized cancer therapy as well as for the industrial identification of novel anti-cancer drugs. The algorithm is essential for designing software programs which allow the prediction of the natural history of cancer disease in individual patients.
US09569580B2	Integrated circuit design changes using through-silicon vias A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.
US09569578B1	Mask decomposition and optimization for directed self assembly A computer implemented method of mask decomposition and optimization for directed self assembly (DSA) which includes: inputting design information of an integrated circuit that is to be patterned using a DSA process; mapping the design information into a tree graph comprising nodes and edges; searching the tree graph to identify a longest path through the tree graph; identifying a branch comprising an edge on the tree graph not on the longest path and stemming from one of the nodes on the longest path; outputting the one node on the longest path that connects to the branch as a hot spot; and modifying a photomask by removing the branch from the photomask; wherein the method is performed by one or more computing devices.
US09569577B2	Identifying noise couplings in integrated circuit A method for determining the sensitivity of an analog output node of a mixed-signal module on a system on a chip (SoC) to noise coupling on the analog input nodes of the mixed-signal module includes (i) selecting an IP block for testing, (ii) selecting the output node, (iii) compiling a list of input nodes for testing, (iv) for each input node of the list, providing excitation signals at different frequencies, (v) for each provided excitation signal, determining the output node's noise sensitivity, and (vi) if any individual and/or cumulative noise sensitivity result exceeds a preset threshold, then modifying the SoC design to take corrective action.
US09569575B2	Digital circuit design method and associated computer program product A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.
US09569573B1	RAS evaluation for circuit element A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.
US09569568B2	Robot simulation system which simulates takeout process of workpiece A robot simulation system includes a model placement part which places a three-dimensional container model in a virtual space and places three-dimensional workpiece models which have any postures at initial positions above the container model and a drop operation simulation part which simulates a drop operation in which the workpieces drop from the initial positions to the inside of the container by action of gravity. The robot simulation system is configured to create a bulk stacked state of workpiece models, based on the positions and postures of the workpiece models which are obtained as a result of simulation of the drop operation.
US09569561B2	Label masked addressable memory A network device receives data packets and derives a key from headers in the packets. A search engine in the device searches, or performs a table lookup, for information based on the key and multiple programmable masks. The search engine includes a hash based search engine that comprises multiple mask modules each to mask an input key with a respective programmable mask, to produce multiple masked keys. The search engine also includes an array of hash modules each corresponding to a respective one of the masked keys and including a hash table. Each of the hash modules searches its hash table for a data value based on a hash of the corresponding masked key, and outputs a found data value, if any, resulting from the search. A selector selects among the found data values and output the selected data value.
US09569560B2	Indicators for entities corresponding to search suggestions Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically generating indicators of entity locations on an electronic map corresponding, for example, to a suggested search request. In one aspect, a method includes providing an electronic map of a geographic area for display on a user interface, receiving a character string entered into the user interface, the character string representing a partial search query, determining a suggested search request based on the character string, and identifying an entity responsive to the suggested search request and a geographic location for the identified entity. An indicator identifying the geographic location of the entity is provided for display on the electronic map.
US09569556B2	Software architecture for displaying information content from plug-in modules in a user interface A user interface application, such as a sidebar application or web page, receives content from a set of plug-in modules. The user interface handles the display of the content and manages any user interaction with the content, thus abstracting these features from the plug-in modules. The plug-in modules may thus be device-independent and possibly used to display the same or corresponding content in other interfaces and/or other devices. One or more of the plug-in modules may also be designed to obtain and populate their content automatically based on user activity, including web browsing or interactions with documents on the local system.
US09569555B2	Method for adding a user-selectable function to a hyperlink A multifunction hyperlink and method for providing an multifunction hyperlink are provided. This invention permits the user to interact with a hyperlink in a variety of ways without necessarily having to open and/or follow the hyperlink. This is accomplished by detecting the presence of a cursor near a hyperlink. After detecting the hyperlink, a toolbar is displayed containing one or more link functions that the user may select. In response to the users' selection of a particular link function, that link function would be performed without requiring any further action by the user.
US09569554B2	System and computer-implemented method for incorporating an image into a page of content for transmission over a telecommunications network A system and method provide an image data file encoding said image in accordance with a standard image format and a page of content in a markup language, said page of content being intended for transmission over a telecommunications network from a server to a client for display by a browser running on the client, said page of content including a link or reference to the image data file for incorporating the image within the page of content. The image is converted from said standard image format into a format in which the image is encoded using said markup language, and the image encoded using said markup language is incorporated into the page of content to replace said link or reference to the image data file prior to transmission of the page of content.
US09569551B2	Dynamic modeling of geospatial words in social media Dynamically modelling geospatial words in social media, in one aspect, generates a word set based on frequencies of words occurring in GPS annotated text data generated by a GPS-enabled device containing latitude and longitude coordinates. Locations are partitioned by mapping GPS coordinates in the GPS annotated text data to a set of discrete non-overlapped locations. A text stream contained in the GPS annotated text data is segmented into time windows. Footprints of locations in time windows are generated. Geospatial weights associated with words in the word set may be generated based on localness of words determined based on the footprints. Words in a text message are extracted and scores are determined for the set of discrete non-overlapped locations associated with the words.
US09569550B1	Custom search index A system includes an application programming interface, an indexer, a security unit and at least one search engine. The application programming interface uploads user-selected custom content from a first user. The indexer indexes the custom content to produce a first search index. The security unit authenticates a user and the at least one search engine receives a search query from the user, searches the first search index based on the search query, and searches a second search index based on the search query and based on results of the user authentication, where the second search index is different than the first search index.
US09569545B2	Enhancing product search engine results using user click history In an example embodiment, previous search queries and clicked-on results are retrieved. This results in one or more pairs, each pair containing a query from the search term database and a first set of search engine results from the click database. Then a score is calculated for each feature within the one or more pairs, and a second set of search queries is boosted using the scores for the features.
US09569534B2	Synchronizing HTTP requests with respective HTML context Synchronizing requests with a respective context includes, responsive to a determination that there are more pages to explore, performing regular crawling operations for a current page, recording a current page in a list of explored pages and extracting links from the current page. Responsive to a determination that there are more links to extract, a next link to analyze is selected to form a selected link and responsive to a determination that there is a new request associated with the selected link, a new request identifier is created and saved as an entry in a hashmap. Responsive to a determination that there is not a new request associated with selected link, a request associated with the selected link is updated with a new link value when the link value differs.
US09569531B2	System and method for multi-agent event detection and recognition A method and system for creating a histogram of oriented occurrences (HO2) is disclosed. A plurality of entities in at least one image are detected and tracked. One of the plurality of entities is designated as a reference entity. A local 2-dimensional ground plane coordinate system centered on and oriented with respect to the reference entity is defined. The 2-dimensional ground plane is partitioned into a plurality of non-overlapping bins, the bins forming a histogram, a bin tracking a number of occurrences of an entity class. An occurrence of at least one other entity of the plurality of entities located in the at least one image may be associated with one of the plurality of non-overlapping bins. A number of occurrences of entities of at least one entity class in at least one bin may be into a vector to define an HO2 feature.
US09569530B2	Extracting and mining of quote data across multiple languages Extracting and mining of quote data across multiple languages, including: retrieving, from a plurality of quote sources, a plurality of commentary summarizations, wherein each commentary summarization is embodied as a machine-readable data structure and wherein the plurality of commentary summarizations include information in at least two or more languages; for each commentary summarization: identifying, within the commentary summarization, quote data, wherein the quote data represents a quote from a commentator; creating a quote tuple for the quote data, the quote tuple including information associated with quantifiable aspects of the quote data; and storing, in a quote tuple repository, the quote tuple; mining, for quote analysis information, the quote tuple repository; and presenting, to a user, the quote analysis information.
US09569519B2	Client-side directed commands to a loosely coupled database Dynamically directing a command to a node in a distributed database is described. An example method includes receiving the command from a client application to access data in the distributed database, where the command contains a set of parameters. A primary key is constructed from at least some of the parameters. The client further generates routing information from a node-partition table based on a comparison of the primary key with an entry in the node-partition table, where the node-partition table maps the primary key to a node in the distributed database. Accordingly, the command is directed to the node in the distributed database based on the routing information.
US09569515B2	Facilitating distributed deletes in a replicated storage system A data storage system includes multiple zones that comprise separate geographic storage locations and store replicated copies of data items. Upon receiving a delete operation at a local zone at a time td, if a copy of the first data item exists in the local zone, the system computes a maximum last update time tmlu=td−tmin, wherein tmin is a minimum lifetime for a data item. Next, the system determines, from a local index, a time tlu that the first data item was last updated. If tlu
US09569512B2	Methods, devices and computer programs for optimizing the replication of data in computer systems The replication of data between a source system and a destination system is disclosed. After having calculated a signature for a fragment of data to be replicated, the source system transmits same to the destination system. The latter determines whether or not the signature is known, e.g., whether or not a fragment is associated with the signature. If so, the data to be replicated is reconstructed (with respect to fragment in question). If not, a message indicating that the signature is unknown is transmitted to the source system, which then transmits the corresponding fragment to the destination system. The latter stores and reconstructs the data to be replicated (with respect to the fragment in question).
US09569511B2	Dynamic data management An interface for users to gain access and manipulate unstructured data is provided. In response to receiving a user query associated with a first database format, a system can request unstructured data associated with a second database format from a second database. The unstructured data can include a set of data groups where each data group has a set of values. Each value can be associated with a different tag. To generate a structured database, some embodiments can determine the number of data groups and the number of unique tags across the data groups and populate the table with data from the unstructured data. Subsequently, the system can apply the user query to the table to obtain a query result and transmit the query result to the user device.
US09569510B2	Crowd-powered self-improving interactive visualanalytics for user-generated opinion data Embodiments relate to interacting with a collection of user opinion documents associated with a topic. One aspect includes obtaining opinion data for the collection of opinion documents associated with the topic. The opinion data includes one or more features discussed in the opinion documents, one or more key phrases included in each feature, one or more text snippets included in each feature, and at least one sentiment expressed in each text snippet. A visual interface is provided in which a feature summary view of the opinion documents acts a top level of a navigational hierarchy. The visual interface allows user navigation from the top level to a lower level of the navigational hierarchy in order to display more details about a text snippet, as compared to the feature summary view, while continuing to provide the feature summary view.
US09569505B2	Phrase-based searching in an information retrieval system An information retrieval system uses phrases to index, retrieve, organize and describe documents. Phrases are identified that predict the presence of other phrases in documents. Documents are the indexed according to their included phrases. Related phrases and phrase extensions are also identified. Phrases in a query are identified and used to retrieve and rank documents. Phrases are also used to cluster documents in the search results, create document descriptions, and eliminate duplicate documents from the search results, and from the index.
US09569503B2	Type evaluation in a question-answering system A system and method for automatically mapping LATs and candidate answers to multiple taxonomies without a need to merge these taxonomies. The method includes using a syntactic analysis of a corpus to extract all type instances of the LAT. The extracted instances are then mapped to a given taxonomy and clustered in a set of supertypes. Each supertype receives a score based on the coverage of LAT instances in the corpus. The method includes mapping the candidate answer to the same taxonomy to determine if the candidate answer is an instance of a significant supertype. Then the score of a candidate answer is obtained by aggregating or taking a maximum of the score of the matched significant supertypes. This score evaluates the type match between the LAT and candidate answer for a taxonomy. Multiple taxonomies can be used to increase the chance of LAT and candidate answer mapping.
US09569502B1	Search lift remarketing Aspects and implementations of the present disclosure are directed to methods of and systems for search lift remarketing. In general, in some implementations, a first content item is distributed to client devices and search lift attributable to the first content item is measured by examining subsequent requests received from client devices to which the first content item has been distributed as compared to requests received from similar client devices to which the first content item has not been distributed. Keywords benefiting from search-lift attributable to the first content item are used to determine when to send a second content item in response to requests from client devices in a select audience. In some implementations, requests are compared to identify a set of keywords invoked more frequently after presentation of the first content item where an increase in usage exceeds a threshold or otherwise indicates a statistical significance.
US09569499B2	Method and apparatus for recommending content on the internet by evaluating users having similar preference tendencies A recommender system includes: an input section 103 configured to receive a search request from a user; a user managing section 104 configured to manage context information representing a characteristic of the user; an index-table managing section 105 configured to output an information object related to the search request of the user; a user-authority-value managing section 106 configured to calculate, on the basis of similarity between users calculated from comparison of the context information of the user and another user and reliability from a plurality of users for the other user, an authority value representing reliability from the user for the other user; a rating calculating section 107 configured to calculate an evaluation value of the user for the information object using a value obtained by weighting an evaluation value of the other user for the information object according to the authority value of the other user; and a ranked-list creating section 108 configured to output a list of information objects ranked on the basis of the evaluation value of the user.
US09569497B2	Lock-free generation of columns with minimal dictionaries after parallel aggregation A new dictionary can be created for a result column in a query plan operation executed on a database. The result column can be generated by multiple worker jobs running in parallel to read tasks from a shared queue as part of a query plan operation that includes a group-by column within an input set of input columns. The group-by column can include an original dictionary for all values contained within the group-by column If the new dictionary has fewer entries than the original dictionary for the group-by column such that mapping is required between old value identifiers within the group-by column and new value identifiers within the result column, the old value identifiers are renamed to the new value identifiers using a mapping vector.
US09569494B2	Avoidance of intermediate data skew in a massive parallel processing environment A computer-implemented method for minimizing join operation processing time within a database system based on estimated joined table spread of the database system has been provided. The computer-implemented method includes estimating value distribution of data in a joined table, wherein the joined table is a result of join operation between two instances of tables of a database system. The computer-implemented method further includes determining boundaries for partitioning at least one range of attributes of the estimated value distribution, wherein the boundaries for partitioning at least one range of attributes of the estimated value distribution corresponds to a same number of rows of the joined table. The computer-implemented method further includes determining at least one assignment of the determined partition of the at least one range of attributes to processing units of the database system.
US09569493B2	Avoidance of intermediate data skew in a massive parallel processing environment A computer-implemented method for minimizing join operation processing time within a database system based on estimated joined table spread of the database system has been provided. The computer-implemented method includes, estimating value distribution of data in a joined table, wherein the joined table is a result of join operation between two instances of tables of a database system. The computer-implemented method further includes determining boundaries for partitioning at least one range of attributes of the estimated value distribution, wherein the boundaries for partitioning at least one range of attributes of the estimated value distribution corresponds to a same number of rows of the joined table. The computer-implemented method further includes determining at least one assignment of the determined partition of the at least one range of attributes to processing units of the database system.
US09569487B1	Using an entity database to answer entity-triggering questions An embodiment may receive a question at a computing device; obtain a search result set in response to the question; identify, using the computing device, one or more entities that are associated with at least one document referenced by the search result set; select, using the computing device, one or more relevant entities identified as being associated with (i) documents referenced by the search result set and (ii) the question; and output, using the computing device, an answer to the question based at least on the selected one or more entities.
US09569486B2	System and a method for hierarchical data column storage and efficient query processing An embodiment provides intermediate data derived in the form of column stores which are in turn based on hierarchical data stores. This intermediate data represents a reduced subset of data matched appropriately to a query (or modified query) such that the amount of data handled in a query processing task on large data is greatly reduced. An embodiment may appropriately choose column data stores and/or modify queries in order leverage parallelization techniques such as map-reduce in order to query large data. The result is the ability to query large data stores in parallel while reducing the amount of data that must be handled.
US09569475B2	Distributed consistent grid of in-memory database caches A plurality of mid-tier databases form a single, consistent cache grid for data in one or more backend data sources, such as a database system. The mid-tier databases may be standard relational databases. Cache agents at each mid-tier database swap in data from the backend database as needed. Ownership locks maintain consistency in the cache grid. Cache agents prevent database operations that will modify cached data in a mid-tier database unless and until ownership of the cached data can be acquired for the mid-tier database. Cache groups define what backend data may be cached, as well as a general structure in which the backend data is to be cached. Metadata for cache groups is shared to ensure that data is cached in the same form throughout the entire grid. Ownership of cached data can then be tracked through a mapping of cached instances of data to particular mid-tier databases.
US09569470B2	Managing sharing relationship of tables Managing a sharing relationship of tables. A super schema is formed incorporating a plurality of tables in a database according to data types of respective columns of the plurality of tables. A free storage capacity of the super schema is evaluated according to holes not occupied by any table in the super schema. A sharing relationship of the plurality of tables is determined according to the free storage capacity of the super schema. The sharing relationship of a large number of tables in a database can be managed effectively, so as to design or optimize the sharing solution among the tables.
US09569468B2	Deploying database upgrades to multiple environments in a different order A virtualization manager receives a request to install a new feature in a first virtualization environment. The virtualization manager identifies a first database upgrade script corresponding to the new feature and compares a first identification number of the first database upgrade script to a second identification number of a second database upgrade script, the second database upgrade script previously run on a management database for the first virtualization environment. If the first identification number is less than the second identification number, the virtualization manager generates a copy of the first database upgrade script and names the copy of the first database upgrade script with a third identification number that is greater than the second identification number. The virtualization manager then runs the copy of the first database upgrade script on the management database.
US09569462B2	Method and system for optimizing electronic map data and determining real property development yield Disclosed is a system method for aligning a plurality of electronic map data, which includes the steps of obtaining an electronic map file, defining an area of interest on the electronic map file, selecting a predetermined datum and providing the electronic map file in the predetermined datum. Also disclosed is a land yield method including the steps of obtaining an electronic map, storing the electronic map in a computer readable medium, defining an area of interest on the electronic map, referring to a database to determine whether the database contains at least one restriction value, referring to a remote database to determine whether the remote database contains an additional restriction value, the additional restriction value being distinct from the at least one restriction value, combining restriction values, and determining a total value of the parcel of land based on the combined restriction values.
US09569456B2	Accelerated deduplication Mechanisms are provided for accelerated data deduplication. A data stream is received an input interface and maintained in memory. Chunk boundaries are detected and chunk fingerprints are calculated using a deduplication accelerator while a processor maintains a state machine. A deduplication dictionary is accessed using a chunk fingerprint to determine if the associated data chunk has previously been written to persistent memory. If the data chunk has previously been written, reference counts may be updated but the data chunk need not be stored again. Otherwise, datastore suitcases, filemaps, and the deduplication dictionary may be updated to reflect storage of the data chunk. Direct memory access (DMA) addresses are provided to directly transfer a chunk to an output interface as needed.
US09569454B2	Selective compression of objects in a storage compute device Methods and apparatuses facilitate receiving a command via a host interface of a storage compute device to perform a computation on one or more data objects. The computations producing intermediate objects that are stored in data storage section of the storage compute device. A determination is made to compress and decompress the intermediate objects as they are moved between the data storage section and a compute section based on wear of a storage medium being reduced in response to the compression and decompression. The intermediate objects are compressed and decompressed as they are moved between the data storage section and the compute section in response to the determination.
US09569452B1	Exponential decay set pruning Disclosed are various embodiments for applying a pruning to data sets, files, logs, and/or any other information. A binning methodology may be employed to determine which data to retain or discard to determine a resulting set of data resembling an exponential decay where more recent items of data are more likely to be retained and more archaic items of data are more likely to be discarded. The resulting set of data may be associated with an average age.
US09569445B2	Dynamic asset assembly using a rule based methodology In an approach for creating an asset, a computer receives a selection of at least one asset element and determines whether one or more asset elements are associated with the selected asset element. In response to determining one or more asset elements are associated with the selected asset element, the computer determines, based, at least in part, on one or more linkage rules, whether one or more of the associated asset elements are in the asset. Furthermore, in response to determining that at least one of the associated asset elements is in the asset, the computer generates an asset map. The asset map, generated by the computer for the asset, depicts the linkage rules, the selected asset elements, and the associated asset elements in the asset.
US09569444B1	Selective operation pushdowns from an analytics platform to bulk storage A computer-implemented method for determining whether to perform a pushdown may include receiving a request for analytics to be performed by an analytics platform on data stored in bulk storage. An operation may be identified as a candidate for a pushdown, where the operation is selected from among one or more operations to be performed for fulfilling the request. The pushdown would require the operation to be performed at the bulk storage. The data may be sampled by reading one or more samples of the data, where the one or more samples are a fraction of the data. The operation may be performed, by a computer processor, on the one or more samples. It may be determined, based on performing the operation on the one or more samples, whether to perform the pushdown of the operation.
US09569438B1	Ranking content using content and content authors Methods, systems, and apparatus, including computer program products for identifying original content. In one aspect a method is described that includes identifying a first document in a collection of documents. The first document contains a content piece and the content piece does not occur in any earlier document in the collection. The first document is associated with a first author and the first author associated with a first rank. The first rank of the first author is determined using a score of the content piece. The score is a figure of merit of the content piece.
US09569431B2	Virtual participant-based real-time translation and transcription system for audio and video teleconferences The present disclosure describes a teleconferencing system that may use a virtual participant processor to translate language content of the teleconference into each participant's spoken language without additional user inputs. The virtual participant processor may connect to the teleconference as do the other participants. The virtual participant processor may intercept all text or audio data that was previously exchanged between the participants may now be intercepted by the virtual participant processor. Upon obtaining a partial or complete language recognition result or making a language preference determination, the virtual participant processor may call a translation engine appropriate for each of the participants. The virtual participant processor may send the resulting translation to a teleconference management processor. The teleconference management processor may deliver the respective translated text or audio data to the appropriate participant.
US09569430B2	Language translation and work assignment optimization in a customer support environment Approaches presented herein enable assignment of translated work to an agent in a customer support environment based on a confidence factor that measures accuracy of translation and an agent's language skill. Specifically, agent proficiencies in a set of natural languages are measured and scored. An incoming customer communication is translated into one or more natural languages and each language translation is assigned a translation score based on a confidence of translation. The skill score and translation score are utilized to calculate a confidence factor for each language. In one approach, the customer communication is assigned to an agent that has a confidence factor greater than a predetermined threshold confidence factor. In another approach, the communication is only assigned if a rule optimizing agent availability and risk of constrained resources is satisfied.
US09569429B2	Translated news Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for augmenting clusters of news articles with translated news articles. In one aspect, a method includes obtaining data characterizing a first cluster of electronically published news articles in a presentation language, wherein the data characterizing the first cluster of news articles comprises one or more terms in the presentation language and region data identifying a first geographical region associated with the first cluster; generating translated terms by translating one or more of the terms from the presentation language to a first language, wherein the first language corresponds to the first geographical region; and obtaining one or more news articles in the first language in response to a search query derived from the one or more translated terms.
US09569426B1	Selectively sending notifications to mobile devices A computer-implemented method, system, and/or computer program product selectively sends push notifications to mobile devices. One or more processors determine that a push notification of a mobile device event is to be issued to one or more mobile devices from a set of mobile devices. The processor(s) receive a status of applications running on at least one mobile device from the set of mobile devices and an extent of user engagement for at least one of the applications. The processor(s) associate a content with the push notification, and parse and evaluate the content. The processor(s) select a mobile device from the set of mobile devices based on the status of the applications, the extent of user engagement, and the parsed evaluated content, and then transmit the push notification to that mobile device.
US09569424B2	Emotion detection in voicemail Methods and apparatus for processing a voicemail message to generate a textual representation of at least a portion of the voicemail message. At least one emotion expressed in the voicemail message is determined by applying at least one emotion classifier to the voicemail message and/or the textual representation. An indication of the determined at least one emotion is provided in a manner associated with the textual representation of the at least a portion of the voicemail message.
US09569422B1	Associating one or more terms in a message trail with a task entry Methods and apparatus related to determining an association between a message trail and a task entry of a user and associating an n-gram with the task entry, wherein the n-gram is based on one or more messages of the message trail. A similarity score between the n-gram and one or more aspects of the associated task entry may be determined. The similarity score may be utilized, for example, to determine when to associate the n-gram with the task entry and/or how to utilize the associated n-gram with the task entry.
US09569419B1	Associative relationship based recommendations The systems and/or processes described herein may establish a controlled and limited vocabulary that may serve as explicit associative relationships. The explicit associative relationships may define the nature of relationships between items and/or categories of items. In response to determining that a user has interacted with or selected an item via a website, an application, etc., associated with a service provider, explicit associative relationships associated with the selected item may be parsed in order to identify additional items related to the selected item. The additional related items may then be dynamically recommended to the user via the website, the application, etc., associated with the service provider.
US09569417B2	Error correction in tables using discovered functional dependencies Mechanisms are provided for performing tabular data correction in a document. Tabular data is received and analyzed to identify at least one portion of the tabular data having an erroneous/missing data value. A functional dependency of the at least one portion of the tabular data on one or more other portions of the tabular data is determined. A correct data value for the erroneous or missing data value of the at least one portion of the tabular data is determined based on the functional dependency of the at least one portion. In addition, the tabular data is modified to replace the erroneous or missing data value with the correct data value and thereby generate a modified table data. A processing operation is then performed on the modified table data to generate a resulting output.
US09569416B1	Structured and unstructured data annotations to user interfaces and data objects The technology provides a method and system to annotate fields associated with a graphical user interface and data objects. The method and systems provide an annotation memory and annotation management system to allow saving annotations associated with fields and data objects. The annotations are fetched from the annotation memory for display along with the field as well as the data object.
US09569414B2	Method, framework, and program product for formatting and serving web content The present invention provides an approach and corresponding framework that separates data from its formatting/view by generating the dynamic JavaScript (data) as a set (e.g., at least one) of JavaScript (data) objects, without any HTML formatting. Then, a set of JavaScript functions can be created that takes the set of JavaScript objects as a parameter, and outputs all or a subset of this data object in a format determined by this JavaScript function. In general, these formatting functions can be static, rather than dynamic, JavaScript. This approach has the advantage of providing a much greater degree of formatting flexibility, without the need for each new format to establish a connection with the back-end system providing the data.
US09569413B2	Document text processing using edge detection A document is received that has a plurality of lines with text. This document includes text associated with at least one topic of interest and text not associated with the at least one topic of interest. Thereafter, it is determined, for each line in the document, a length of the line and a number of off-topic indicators with the off-topic indicators characterizing portions of the document as likely being not being associated with the at least one topic of interest. Thereafter, a density for each line can be determined based on the determined line length and the determined number of off-topic indicators. The determined densities for each line are used to identify portions of the documents likely associated with the at least one topic of interest so that data characterizing the identified portions of the document can be provided. Related apparatus, systems, techniques and articles are also described.
US09569412B1	Auto grouping browser tabs A computer implemented method and system for managing browser tabs includes identifying a plurality of URLs (Uniform Resource Locator(s)) in response to detecting the URLs in a web browser running on a computer. The plurality of URLs are organized based on each of the URLs, and each of the plurality of URLs correspond to a tab opened by the web browser. The tabs of the web browser are grouped based on the URLs.
US09569405B2	Generating correlation scores A computer-implemented method includes obtaining first and second binary vectors. For each of a plurality of vector locations in a first of j words in the first binary vector, the method includes shifting the binary values for the second binary vector so that a particular one of the binary values in the second binary vector is located at a vector location in a first of the k words in the second binary vector that matches the vector location in the first of j words in the first binary vector. For each of the j words in the first binary vector, the method includes aligning the second binary vector with the word in the first binary vector and determining a binary correlation score. A similarity of the first binary vector and the second binary vector can be determined based at least on one or more of the determined binary correlation scores.
US09569402B2	3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.
US09569399B2	Routing data communications packets in a parallel computer Routing data communications packets in a parallel computer that includes compute nodes organized for collective operations. Each compute node including an operating system kernel and a system-level messaging module that is a module of automated computing machinery that exposes a messaging interface to applications. Each compute node including a routing table that specifies, for each of a multiplicity of route identifiers, a data communications path through the compute node. Including to carry out the steps of: receiving in a compute node a data communications packet that includes a route identifier value; retrieving from the routing table a specification of a data communications path through the compute node; and routing, by the compute node, the data communications packet according to the data communications path identified by the compute node's routing table entry for the data communications packet's route identifier value.
US09569398B2	Routing data communications packets in a parallel computer Routing data communications packets in a parallel computer that includes compute nodes organized for collective operations. Each compute node including an operating system kernel and a system-level messaging module that is a module of automated computing machinery that exposes a messaging interface to applications. Each compute node including a routing table that specifies, for each of a multiplicity of route identifiers, a data communications path through the compute node. Including to carry out the steps of: receiving in a compute node a data communications packet that includes a route identifier value; retrieving from the routing table a specification of a data communications path through the compute node; and routing, by the compute node, the data communications packet according to the data communications path identified by the compute node's routing table entry for the data communications packet's route identifier value.
US09569397B2	Methods and systems for maintenance of turbomachinery In one embodiment, a system includes a condition based replacement life (CBRL) approval system configured to receive a turbomachinery component data and to approve a turbomachinery component for CBRL based on the turbomachinery component data. The system further includes a CBRL validation system configured to repair the turbomachinery component into a repaired turbomachinery component, wherein the repaired turbomachinery component is configured to operate in a turbomachinery beyond a service time of the turbomachinery component.
US09569396B2	Interface with variable data rate A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
US09569392B2	Determination of one or more partitionable endpoints affected by an I/O message A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.
US09569389B2	Semiconductor system for tuning skew of semiconductor chip A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.
US09569386B2	Method and system for single-line inter-integrated circuit (I2C) bus Embodiments of a system and method are disclosed. One embodiment is an I2C compatible device. The I2C compatible device includes an SDA interface for connection to an SDA line and a single-line I2C module configured to transmit a sync word from the SDA interface over the SDA line and following the sync word, to transmit I2C data from the SDA interface over the SDA line such that digital data is communicated via a single line. In an embodiment, the sync word is a sync byte+NACK.
US09569384B2	Conditional links for direct memory access controllers Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.
US09569376B1	Method, system, and computer program product for managing shutdown and substitution of I/O enclosures A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will perform a shutdown after a predetermined amount of time. The storage controller determines whether the I/O enclosure provides a last path to data stored in a storage device. A request is transmitted to the I/O enclosure to perform either an orderly shutdown or abort the shutdown, based on the whether the I/O enclosure provides the last path to the data stored in the storage device.
US09569374B2	Information processing apparatus, information processing method, and program There is provided an information processing apparatus including a device detection part configured to detect a second execution device that is identical or similar to a first execution device which executes a command, and an execution control part configured to perform control in a manner that the command is executed by the second execution device detected by the device detection part.
US09569368B2	Installing and managing flows in a flow table cache Some embodiments provide a physical forwarding that installs flows in a flow table cache and uses the flows to process packets. In addition, the physical forwarding element iterates through each flow and validates the flow. In some embodiments, the physical forwarding element performs the installation and validation operations in a multi-threaded manner. The physical forwarding element in some such embodiments includes a set of one or more upcall handlers to install flows in the cache, and a set of one or more revalidators to validate the flows in the cache. In its own thread, an upcall handler may run independently of each revalidator in the set of revalidators. In another thread, a revalidator may run independently of each upcall handler and each other revalidator.
US09569362B2	Programmable ordering and prefetch An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.
US09569361B2	Pre-fetch chaining According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.
US09569360B2	Partitioning shared caches Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.
US09569359B2	Methods and apparatuses for addressing memory caches A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.
US09569358B2	Electronic device and method for fabricating the same An electronic device including a semiconductor memory that includes: a selection element; a first plug and a second plug that are coupled with two different sides of the selection element, respectively; a variable resistance element formed over the first plug and configured to store data; and a dummy variable resistance element formed over the second plug and configured to include a conductive path coupled with the second plug.
US09569357B1	Managing compressed data in a storage system Systems, methods, and computer readable storage mediums for optimistically managing compressed data in a storage system. When possible, multiple input blocks are compressed into a buffer and stored in a single physical block on a storage device. The metadata of the multiple input blocks can be managed separately. A fingerprint of the compressed buffer can be generated and used as an index to the single physical block. Alternatively, fingerprints of the uncompressed input blocks can be generated, and reference counts can be maintained to track the number of input blocks which reference the compressed buffer.
US09569355B2	Memory system and control method According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.
US09569348B1	Method for automatic page table compression One embodiment of the present invention sets forth a technique for performing a method for compressing page table entries (PTEs) prior to storing the PTEs in a translation look-aside buffer (TLB). A page table entry (PTE) request is received for a PTE that is not stored in the TLB. The PTE as well as a plurality of PTEs that are adjacent to the PTE are retrieved from a memory. The PTE and the plurality of PTEs are compressed and then stored in the TLB.
US09569345B2	Architectural failure analysis Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.
US09569343B2	Integration of a software content space with test planning and test case generation A computer-implemented method for test planning and test case generation, includes collecting, by a processor, a plurality of requirements, creating, by the processor, a plurality of content space specification files that includes the plurality of requirements, processing, by the processor, the plurality of content space specification files to generate a plurality of user stories, outputting, by the processor, the plurality of user stories and integrating, by the processor, the user stories into test planning and test case generation.
US09569342B2	Test strategy for profile-guided code execution optimizers Systems, methods and computer program products are described herein for testing a system that is designed to optimize the execution of code within an application or other computer program based on profile data collected during the execution of such code. The embodiments described herein utilize what is referred to as a “profile data mutator” to mutate or modify the profile data between the point when it is collected and the point when it is used to apply an optimization. By mutating the profile data at this point, testing of a system for optimized code execution can be significantly more thorough. Furthermore, such profile data mutation leads to a more scalable and efficient testing technique for profile-guided systems for optimized code execution.
US09569336B2	System and method for managing traceability suspicion with suspect profiles A method, computer program product, and computer system for generating, at a computing device, a first suspect profile of a plurality of suspect profiles that includes one or more characteristics, wherein the first suspect profile is associated with a traceability link between at least two artifacts. A change to a first characteristic associated with a first artifact of the at least two artifacts is determined. Which of the plurality of suspect profiles includes the first characteristic is determined. The first characteristic is matched to the first suspect profile of the plurality of suspect profiles based upon, at least in part, determining that the first suspect profile includes the first characteristic. The traceability link is marked as suspect based upon, at least in part, matching the first characteristic to the first suspect profile.
US09569333B1	Method for retrieving information from presentations and meetings using a network A method and system for processing recorded communications over a network provides a communication via a network to a recording server adapted for hosting a recordable meeting. The recording server includes a processor with a memory and communicates with the network and an identification code is provided for the recordable meeting along with text related to the communication, which is stored in data storage of the recording server. At least one pointer can be inserted during or after the meeting is recorded, forming a recorded meeting with at least one pointer mapped to the text of the recorded meeting. The recorded meeting with at least one pointer is then saved into the data storage that can be accessed by an interested user.
US09569329B2	Cache control device, control method therefor, storage apparatus, and storage medium Disclosed is a cache control device which makes it possible to, even when a failure is occurred in a cache, reduce a risk that information is lost due to the failure.A cache control device 1 includes a monitor unit 2 that monitors an occurrence of a failure of a plurality of storage devices which constitute a cache; and a control unit 3 that determines superiority or inferiority of the storage devices on the basis of life-span information and failure information which are related to the storage devices, and that changes a configuration of the cache in accordance with a result of the determination.
US09569328B2	Managing application log levels in cloud environment Applications and their application components run on a cloud platform and an underlying cloud runtime infrastructure. The cloud platform provides a service that exposes an interface to remotely change log levels of logger objects defined in application components. The application logs are generated and stored for the application components on the cloud runtime infrastructure of the cloud platform. Log levels affect the content stored in the application logs. The exposed interface is instantiated to process remote requests for managing application logs and log levels for a specified application component. The application component is deployed on the cloud platform. The requested change in the log levels is performed based on the implementation of the interface. The change in the log levels is performed in the configuration data on the cloud runtime infrastructure provided by the cloud platform.
US09569327B2	System and method for labeling alert messages from devices for automated management An alert processing system and method are adapted for processing device alerts. The system includes a routing device in communication with a printer. The routing device receives at least one alert description in a source language transmitted from the printer. The routing device identifies a set of words derived from the alert description related to a condition of the associated device. The routing device compares the set of words, in a target language, to a categorization model and, based on the comparison, categorizes the set of words into to one of a predetermined set of alert categories.
US09569326B2	Rule organization for efficient transaction pattern matching Efficiently identifying transactions processed by a software application, such as a server application is disclosed. In one embodiment, transactions are identified by applying a set of rules to communications between a client and server to determine whether certain patterns are in the communications. For example, the rules may look for some combination of parameters in the transactions. As a particular example, the rules may be used to look for parameters in HTTP requests. The rules are organized in a way that allows efficient processing. For example, the rules may be organized based on the frequency with which the parameters are expected to occur in the transactions and the frequency with which each transaction is expected to occur. The rules may be updated if the expected frequencies deviate from actual frequencies, such that the rules can be organized for more efficient processing.
US09569322B2	Memory migration in presence of live memory traffic A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.
US09569319B2	Methods for improved server redundancy in dynamic networks In one embodiment, a server is assigned a candidate secondary server role such that the dynamic network employs a “make-before-break” redundancy where redundant nodes proactively synchronize replicated data and state information with a standby secondary server prior to releasing the responsibilities of active primary and/or secondary server(s). The “make-before-break” redundancy ensures relatively high availability of dynamic networks and realized services.
US09569317B2	Managing VIOS failover in a single storage adapter environment According to one exemplary embodiment, a method for VIOS failover in an environment with a physical storage adapter is provided. The method may include assigning the physical storage adapter to a first VIOS, wherein the physical storage adapter has I/O connectivity to at least one storage device. The method may include configuring a first I/O path between the first VIOS and a second VIOS. The method may include configuring a second I/O path from a client partition to the first VIOS, wherein the second I/O path is set as a primary I/O path. The method may include configuring a third I/O path from the client partition to the second VIOS. The method may include determining the first VIOS is inaccessible. The method may include unassigning the physical storage adapter from the first VIOS. The method may include assigning the physical storage adapter to the second VIOS.
US09569315B2	Modeling the topology of management servers in a distributed system Techniques disclosed herein enable efficient creation of models that represent connection topology of virtual machine (VM) management servers and site recovery manager (SRM) servers configured to provide VM recovery services across multiple locations. In operation, an SRM topology unit initializes a model to represent a VM management server. The SRM topology unit expands the model to represent a first SRM server that is logically connected to the VM management server and supports VM recovery at a first location. The SRM topology unit further expands the model to reflect a pairing relationship between the first SRM server and a second VM management server that supports VMs at a second location. Creating an easily-comprehended model in this hierarchical and automated fashion improves on conventional techniques where holistically evaluating the connection topology is predominantly a tedious and error-prone manual process.
US09569314B2	Flash copy for disaster recovery (DR) testing In one embodiment, a method for disaster recovery (DR) testing includes creating a snapshot of data based on a backup copy of data stored on one or more production clusters or a live copy of the data and storing the snapshot on more than one DR cluster within a DR family, determining which cluster within the DR family to access the snapshot from based on a consistency of the snapshot in relation to data on the one or more production clusters at a time-zero, accessing the snapshot of data stored on the determined DR cluster within the DR family only when the snapshot was made consistent with respect to data on the one or more production clusters within the DR family before the time-zero, and performing DR testing using the snapshot.
US09569312B2	System and method for high-speed data recording A system and method for high speed data recording includes a control computer and a disk pack unit. The disk pack is provided within a shell that provides handling and protection for the disk packs. The disk pack unit provides cooling of the disks and connection for power and disk signaling. A standard connection is provided between the control computer and the disk pack unit. The disk pack units are self sufficient and able to connect to any computer. Multiple disk packs are connected simultaneously to the system, so that one disk pack can be active while one or more disk packs are inactive. To control for power surges, the power to each disk pack is controlled programmatically for the group of disks in a disk pack.
US09569310B2	System and method for a scalable crash-consistent snapshot operation Described herein is a system and method for a scalable crash-consistent snapshot operation. Write requests may be received from an application and a snapshot creation request may further be received. Write requests received before the snapshot creation request may be associated with pre-snapshot tags and write requests received after the snapshot creation request may be associated with post-snapshot tags. Furthermore, in response to the snapshot creation request, logical interfaces may begin to be switched from a pre-snapshot configuration to a post-snapshot configuration. The snapshot may then be created based on the pre-snapshot write requests and the post-snapshot write requests may be suspended until the logical interfaces have switched configuration.
US09569298B2	Multi-stage failure analysis and prediction A hierarchical multi-stage model of asset failure risk for complex heterogeneously distributed physical assets is built. The hierarchical multi-stage model considers heterogeneity of failure patterns for the assets. At least one data stream is analyzed to determine whether the hierarchical multi-stage model needs to be updated due to a change in the failure patterns. If the analysis indicates that the hierarchical multi-stage model needs to be updated, the hierarchical multi-stage model is dynamically updated to obtain an updated hierarchical multi-stage model.
US09569296B2	Receiver bit alignment for multi-lane asynchronous high-speed data interface The invention uses a PRBS pattern generated by transmitter (serializer) as training. At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple lanes simultaneously. The captured data is used to calculate the PRBS distance for different lanes. After the distances are obtained, the one with largest latency is used as a reference, to calculate the relative latency with each other lane. This relative latency is further used to calculate the number of shifts for Barrel Shifter and word shifter.
US09569291B1	Systems and methods for inter-process messaging Provided are systems and methods for a first process for writing messages to a shared memory (each of the messages being written to a respective buffer of the shared memory, and the messages configured to be read in a specified sequence by a second process), determining that writing of one of the messages to the shared memory has been completed and, sending, to the second process and in response to determining that writing of one of the messages to the shared memory has been completed, an offset value corresponding to a location in the shared memory, wherein the second process is configured to read one or more messages that are stored in the portion of the shared memory before the offset value. Also the second process reads one or more messages stored in buffers that reside in the portion of the shared memory before the offset value, and commits the reads.
US09569290B1	Utilizing a profile to prevent recurring events from being transmitted to the event processing device that are not necessary to be processed by event processing device A method, system and computer program product for efficiently utilizing resources in processing recurring events. Recurring events from one or more event type sources (heart rate monitor) sensed by various sensors are detected. An event type (e.g., heart rate data) for each detected recurring event is identified. A user profile associated with the identified event type is then analyzed to determine whether the associated sensed recurring event is to be transmitted to the event processing device. The user profile contains a set of conditions which need to be satisfied before the recurring event is transmitted to the event processing device. If the set of conditions in the user profile is not satisfied, then the recurring event is not transmitted to the event processing device. In this manner, by not transmitting the recurring event, power and consumption utilization are reduced for both the event emitting device and the event processing device.
US09569288B2	Application pattern discovery API associations among a plurality of service application programming interfaces may be identified by analyzing service API call logs, which contain data associated with invocation of the plurality of application programming interfaces by a plurality of applications, wherein sets of APIs that are determined to be called together are identified. For a set of service APIs, a plurality of applications that invoke the APIs in the set is identified. A sequence of API calls by an application in the plurality of applications is identified, wherein multiples sequences of APIs are identified, one sequence of API calls identified respectively for one application in the plurality of applications. An application pattern is determined based on the multiple sequences of service APIs.
US09569285B2	Method and system for message handling A method and system for message handling wherein a structured message is transmitted as a reduced message with the structure removed. The method includes: monitoring messages to be transmitted, the step of monitoring comprising: for each message, identifying one or more elements within the message and identifying the format of content and/or structure encapsulated by those elements; determining the probability that a message will conform to a previously identified format; and using the determined probability to decide when to transmit a format template for the message, wherein the format template is for use by a destination to add the structure removed by a message source back into the message.
US09569280B2	Managing resource collisions in a storage compute device A storage compute device includes a data storage section that facilitates persistently storing host data as data objects. The storage compute device also includes two or more compute sections that perform computations on the data objects. A controller monitors resource collisions affecting a first of the compute sections. The controller creates a copy of at least one of the data objects to be processed in parallel at a second of the compute sections in response to the resource collisions.
US09569278B2	Asymmetric performance multicore architecture with same instruction set architecture A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
US09569277B1	Rebalancing virtual resources for virtual machines based on multiple resource capacities A workload of a virtualized computing environment is rebalanced by resizing and/or moving one or more virtual machines allocated resources from a shared pool of resources in the virtualized computing environment based upon multiple resource capacities specified for each virtual machine and representing different portions of the resources from the shared pool of resources, e.g., minimum and desired resource capacities.
US09569275B2	Allocation and reservation of virtualization-based resources According to one aspect of the present disclosure a method and technique for allocating and reserving virtualization-based resources is disclosed. The method includes: receiving, by a virtualization-based resource management system, a reservation request to reserve a set of computing resources; dynamically allocating the set of computing resources to the reservation request; assigning a key to the allocated set of computing resources; and maintaining the allocated set of computing resources in a reserved state until a utilization request is received to utilize the allocated set of computing resources, the utilization request including the key.
US09569272B2	Device and method for the distributed execution of digital data processing operations A method and device for digital data processing based on a data flow processing model is suitable for the execution, in a distributed manner on multiple calculation nodes, of multiple data processing operations modelled by directed graphs, where two different processing operations include at least one common calculation node. The device includes an identification processor configured to, from a valued directed multi-graph made up of the union of several distinct processing graphs and divided into several valued directed sub-multi-graphs, called chunks, and whose input and output nodes are buffer memory nodes of the multi-graph, identify a coordination module for each chunk. Furthermore each identified coordination module is configured to synchronize portions of processing operations that are to be executed in the chunk with which the respective coordination module is associated, independently of portions of processing operations that are to be executed in other chunks.
US09569269B2	Automated exploitation of virtual machine resource modifications At least one application in a distributed computing environment is deployed. At least one resource of a virtual machine is provided to the at least one application in the distributed computing environment. The at least one resource of the virtual machine provided is recorded in metadata and the at least one application receives the metadata and using the metadata the at least one application determines how much of the at least one resource of the virtual machine to utilize. A change to the at least one resource of the virtual machine is determined. Responsive to determining the change to the at least one resource of the virtual machine, the metadata is modified. The at least one application uses the modified metadata to determine how much of the changed at least one resource of the virtual machine to use.
US09569268B2	Resource provisioning based on logical profiles and objective functions Described are techniques for selecting resources for provisioning. A usage definition, including an objective function, and first set of logical profiles based on core criteria are selected. Each of the logical profiles in the first set represents a resource set characterized by a core criteria value set that specifies values for the core criteria. A second set of resulting objective function values are determined by evaluating the objective function for each of the logical profiles in the first set. A highest ranked one of the resulting objective function values in the second set is selected having a corresponding first logical profile of the first set and a corresponding core criteria value set. A third set of resources is selected which is characterized by the corresponding core criteria value set for the first logical profile. The third set of resources is any of recommended or selected for provisioning.
US09569263B2	Techniques for generating instructions to control database processing An apparatus includes a task selector to receive an indication of a database task to be performed, wherein the database task includes a set of subtasks; a source selector to receive an indication of a source device to perform the set of subtasks, and to retrieve from the source device an indication of a processing environment currently available within the source device that includes an identity and version level of a database routine of the source device; and an instruction generator to determine a set of languages able to be interpreted by the database routine based on the identity and version level, select a language of the set of languages in which to generate instructions for each subtask based on the processing environment, and generate and transmit the instructions to the source device.
US09569261B2	Multi-thread processor with rescheduling when threads are nondispatchable The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.
US09569259B2	Virtual machine migration tool Tools and techniques for migrating applications to compute clouds are described herein. A tool may be used to migrate any arbitrary application to a specific implementation of a compute cloud. The tool may use a library of migration rules, apply the rules to a selected application, and in the process generate migration output. The migration output may be advisory information, revised code, patches, or the like. There may be different sets of rules for different cloud compute platforms, allowing the application to be migrated to different clouds. The rules may describe a wide range of application features and corresponding corrective actions for migrating the application. Rules may specify semantic behavior of the application, code or calls, storage, database instances, interactions with databases, operating systems hosting the application, and others.
US09569258B1	Scheduling multiple operations in a divider unit A multiplier unit that may be configured to concurrently perform multiple division and square operations is disclosed. The multiplier unit may include multiple stages. Each stage may be configured to perform a corresponding arithmetic operation. Control circuitry coupled to the multiplier unit may be configured to schedule in a given cycle of the plurality of cycles, a respective tasks of a plurality of tasks included in a first operation for execution on a respective stage of the multiple stages. The control circuitry may be further configured to schedule execution of each tasks of a second plurality of tasks included in a second operation during a respective cycle on an unused stage of the multiple stages.
US09569252B2	Page compression strategy for improved page out process A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.
US09569247B2	Range based virtual machine functions A method performed by a physical computing system includes, with a hypervisor, determining that a multilevel guest page table includes an upper directory that maps a set of contiguous entries to privileged pages, with the hypervisor, determining that, within the multilevel page table, only the set of contiguous entries map to the privileged pages, with the hypervisor, receiving a request from the guest to execute a virtual machine function, receiving a pointer as a parameter for the virtual machine function, and in response to determining that the pointer references a memory address that is within a range associated with the set of contiguous entries, aborting the virtual machine function.
US09569242B2	Implementing dynamic adjustment of I/O bandwidth for virtual machines using a single root I/O virtualization (SRIOV) adapter A method, system and computer program product are provided for implementing dynamic adjustment of Input/Output bandwidth for Virtual Machines of a Single Root Input/Output Virtualization (SRIOV) adapter. The SRIOV adapter includes a plurality of virtual functions (VFs). Each individual virtual function (VF) is enabled to be explicitly assigned to a Virtual Machine (VM); and each of a plurality of VF teams is created with one or more VFs and is assigned to a VM. Each VF team is enabled to be dynamically resizable for dynamic adjustment of Input/Output bandwidth.
US09569241B2	Sharing devices assigned to virtual machines using runtime exclusion An example system and method of sharing a device assigned to a plurality of virtual machines includes identifying a first virtual machine in which a device is active. When a condition is satisfied, control of the device is transferred from the first virtual machine to a second virtual machine. Transferring control of the device includes sending a first communication to cause the first virtual machine to relinquish control of the device based on an indication that power will be removed from the device and further to cause the virtual machine to save first state information maintained by the first virtual machine to a first memory. The first state information is associated with the device. Transferring control of the device also includes saving second state information maintained by a host machine to a second memory. The second state information is associated with the first virtual machine and device.
US09569239B2	Using a mobile device to transfer virtual machine between computers while preserving session A method includes loading a virtual machine snapshot of a virtual machine from a first computing device to a mobile device. The virtual machine runs on the first computing device and the virtual machine snapshot includes a COW file and an image file with files from the virtual machine. The method includes launching the virtual machine on a second computing device, where the second computing device reads the virtual machine snapshot from the mobile device and the second computing device records changes to a copy of the COW file stored on the second computing device while the second computing device runs the virtual machine. The method includes terminating a virtual machine session running on the second computing device and copying the COW file to the mobile device. The COW file includes changes to the virtual machine snapshot from execution of the virtual machine on the second computing device.
US09569237B2	Virtual machine management using a downloadable subscriber identity module A method is presented of establishing communications with a Virtual Machine, VM, in a virtualized computing environment using a 3GPPcommunications network. The method includes establishing a Machine-to-Machine Equipment Platform, M2MEP, which comprises a Communications Module, CM, providing an end-point of a communication channel between the 3GPP network and the VM. A virtual Machine-to-Machine Equipment is established that comprises a VM running on the M2MEP and a downloadable Subscriber Identity Module, associated with the CM. The Subscriber Identity Module includes security data and functions for enabling access via the 3GPP network. The CM utilizes data in the Subscriber Identity Module for controlling communication over the communication channel between the VM and the 3GPP network.

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