| Document | Document Title |
|---|---|
| US09537569B2 |
Methods and apparatus for target identification
Methods and apparatus for target identification are disclosed. Example methods disclosed herein to respond to a target identification interrogation include aligning an optical transceiver based on a detected optical signal to establish an optical communication link with a target detector, receiving a first signal from the target detector using the optical communication link, extracting a first code from the first signal, and transmitting a second signal using the communication link, wherein the second signal is encoded with a second code based on the first code of the first signal. |
| US09537567B2 |
Light receiving circuit and light coupling device
A light receiving circuit includes an inverting amplification circuit, a first light receiving element, a first circuit, and a charging circuit. The inverting amplification circuit includes an input terminal and an output terminal. The first light receiving element is connected between the input terminal and a reference potential terminal. The first circuit includes a first resistor, a second resistor, a third resistor and a capacitor. The first resistor second resistor connected through a connection point. The first resistor is connected between the input terminal and the connection point, and the second resistor connected between the output terminal and the connection point. The third resistor is connected between the connection point and connection node, and the capacitor is connected between the connection node and the reference potential terminal. The charging circuit connected between the power supply terminal and the connection node. |
| US09537565B2 |
System for automatic configuration of a mobile communication system
A communication system includes a receive antenna for receiving communication signals, processing circuitry for processing the received communication signals and repeating the signals for further transmission and at least one transmit antenna for transmitting the repeated signals. The processing circuitry utilizes configurable settings for controlling the operation of the communication system and the configurable settings are variable for varying the operation of the system. The processing circuitry is further operable for receiving inputs regarding current operating conditions of the communication system and for selectively adapting the configurable settings of the system based upon the operating condition inputs. |
| US09537561B1 |
Optimization of communications with UAVS using terrestrial cellular networks
A UAV gateway may be used to assist in the optimization of communications between a UAV and a cellular wireless network. The UAV may include a steerable, multi-faceted antenna array. In one implementation, the UAV may receive, from the cellular wireless network, network description information, describing the physical state of the cellular wireless network. The network description information may include, for example, locations of base stations near the UAV, transmit power associated with the base stations (or with cells provided by the base stations), and/or the transmit antenna patterns associated with the base stations. The UAV may use this information to optimize its communications with the cellular network. |
| US09537560B2 |
Method and apparatus for cooperative wireless communications
A method and apparatus for wireless communications is disclosed. Channel state information (CSI) for a plurality of network nodes is transmitted. Grant information is received from at least one network node of the plurality of network nodes. The grant information is based on the transmitted CSI and includes an indication of a cooperative scheme. A plurality of beam-formed signals, including data from each of the plurality of network nodes, is received in response to the received grant information. The same data is received from each of the plurality of network nodes. |
| US09537559B1 |
Autonomous radio controlling method and system thereof
An autonomous radio controlling method and a system thereof are disclosed herein, in which the autonomous radio controlling method includes: antenna combinations of an antenna matrix are switched. Signal-to-interference ratios (SIRs) and received signal strength indicator (RSSI) values of the antenna combinations are respectively through a first computing process to generate first computed SIRs and first computed RSSI values. The SIRs are through a second computing process to generate second computed SIRs. A relation between a minimum of the second computed SIRs and a first threshold is determined, and further a relation between a minimum of the first computed SIRs and a first range, or a relation between a minimum of the first computed RSSI value and a second range is determined to control an autonomous radio system to operate in a first mode or a second mode. |
| US09537558B1 |
ESA phase shifter topology
A phase shifter component is described. Inputs are arranged to selectively receive an inphase component of an in-phase (I) signal or an outphase I signal 180° out of phase with the inphase I signal, and to selectively receive an inphase component of a quadrature-phase (Q) signal or an outphase Q signal 180° out of phase with the inphase Q signal. A first gain portion includes only two transistor elements arranged to amplify the received outphase or inphase I signal. A second gain portion includes only two transistor elements arranged to amplify the received outphase or inphase Q signal. The first and second gain portions are configured to control the gain of the received outphase or inphase I signal and the received outphase or inphase Q signal, respectively, to provide a composite output signal with a desired phase shift between 0° and 360°. |
| US09537554B2 |
Joint coding method based on binary tree and coder
A user equipment generates information based on a plurality of values of joint coding of a Rank Index RI and a first Precoding Matrix Index W1 and transmits the information on a physical uplink control channel. The payload size of the information is 5 bits. The first Precoding Matrix Index W1 and a second Precoding Matrix Index W2 correspond to a precoding matrix and 16 values in the plurality of values correspond to the Rank Index RI of 1 or 2 where a part of values in the plurality of values except the 16 values in the plurality of values correspond to the Rank Index RI of more than 2. |
| US09537553B2 |
Method and apparatus for adjusting transmit powers of base station antennas, and base station
A method and an apparatus for adjusting transmit powers of base station antennas, and a base station are provided. The method includes receiving an input precoding matrix of a transmit power-limited antenna set, where the precoding matrix is determined according to a scheduling result of a user equipment communicating with a base station in each layer of each subband in a system; adjusting the precoding matrix according to a transmit power limit requirement of the transmit power-limited antenna set, a system capacity improvement requirement, or a coverage performance improvement requirement to obtain an adjusted precoding matrix; and adjusting a stream transmit power of the transmit power-limited antenna set by using the adjusted precoding matrix. |
| US09537552B2 |
Method and apparatus for channel state information based on antenna mapping and subsampling
Non-zero power channel state information reference signals (CSI-RS) are transmitted only on a subsampled pattern of antennas within an antenna array. Based on the transmitted CSI-RS, channel state information is determined for all antennas within the antenna array by, for example, precoder matrix indicator (PMI) interpolation or channel quality indicator (CQI) compensation. The determination of CSI for all antennas within the antenna array may be made by a user equipment receiving the subsampled CSI-RS or a base station transmitting the subsampled CSI-RS. |
| US09537549B2 |
Method, terminal and base station for multi-user interference suppression
Embodiments of the present invention provide a multi-user interference suppression method, terminal and base station. The method includes performing layer mapping on and precoding service data of each of paired users to obtain precoded output data, mapping the precoded output data and a common pilot sequence to a port of an antenna array for sending to each user by using the antenna array. Correspondingly, the embodiments of the present invention further provide a data receiving method, base station and terminal. By using a common pilot sequence based on the paired users, the same pilot sequence is used for each user in the paired users of a cell or a collaborative area, which is different from the technical solution in the prior art where a user-specific pilot is used and pilots of different users are orthogonal. |
| US09537547B1 |
User equipment SRS selection with network node intelligence for beamforming performance improvement
User Equipment (UE) selects a Sounding Reference Signal (SRS) pattern and transmits orthogonal frequency-division multiplexing (OFDM) symbols according to the selected SRS pattern. The OFDM communication system wirelessly receives data from the UE and processes the data to detect the OFDM symbols. The detected OFDM symbols are processed to identify the selected SRS pattern. An impulse response matrix is generated based on the selected SRS pattern. Additional data based on the impulse response matrix can be transferred to the UE. |
| US09537546B2 |
Implementing MIMO in mmWave wireless communication systems
A system and method are provided to increase data rates available in mmWave wireless communication systems by adapting a multiple-input multiple-output (MIMO) in a next generation mmWave wireless communication system. The system and method advantageously employ the characteristics of mmWave antenna arrays, including multiple antenna elements in each antenna array, to implement the MIMO scheme by establishing multiple beamformed communication links between a mmWave transmitter and receiver. An outgoing signal is divided into multiple signal elements to correspond to the multiple beamformed links and each of the multiple signal elements is transmitted by the transmitter across a different one of the multiple beamformed links to be reassembled at the receiver. An antenna element allocation scheme is incorporated to assign specific numbers and configurations of antenna elements at each of the transmitted and receiver to each of the multiple beamformed communication links. |
| US09537545B2 |
Millimeter wave non-line-of-sight
A Next Generation Data Network is described. It leverages the “cloud” for data management, frequency data computation and analytics. The wireless network is a single frequency network that permits limited non-line-of-sight operation. The wireless network using packet switched beams, the beams are formed and switched electronically. It utilizes advanced signal processing to compensate for low transmit signal power and multipath reflections that can be frequency or flat fades. |
| US09537543B2 |
Techniques to simultaneously transmit and receive over the same radiofrequency carrier
An apparatus may include an antenna and a transceiver coupled to the antenna, the transceiver including a receiver operative to receive a radio-frequency (RF) signal and a transmitter operative to transmit a RF signal. The apparatus may also include an RF echo cancellation module coupled to the receiver and the transmitter, the RF echo cancellation module operative to generate an analog echo cancellation signal for the received RF signal based on a delayed version of the transmit RF signal. Other embodiments are disclosed and claimed. |
| US09537542B2 |
Method for processing information and electronic device
A method for processing information and an electronic device are provided. The method includes: sending a first instruction to a second electronic device through a radio frequency identification unit to inquire identification information of the second electronic device; acquiring the identification information of the second electronic device; and obtaining position information of the second electronic device according to the identification information of the second electronic device. With the disclosure, a more enriched usage scene for man-machine interaction is provided, and user experience is improved. |
| US09537541B2 |
Method and apparatus for activating scan function
A method and electronic device for receiving information is provided. The method includes transmitting, by the electronic device, a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and scanning, by the electronic device, during the scan time to receive the information. The electronic device includes a transmitter configured to transmit a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and a scanner configured to scan during the scan time to receive the information. |
| US09537540B2 |
Rotary transmitter for machine tools
The invention relates to a rotary transmitter (2) for machine tools, having an inductive energy transmission section (31), which is arranged between a stator part (4) fixed to the machine and a rotor part (6) fixed to the tool, and a contactless bidirectional data transmission section (35). A special feature of the invention consists in that, in order to make maximum use of the capacity of the energy transmission section (31), precautions are taken with which the optimal operating frequency (fopt) of the energy transmission operating according to the transformer principle is determined at every system start in a test run with a connected test resister (51) and a variable frequency (fp). Furthermore, for the purpose of interference-free data transmission, buffer storage of the data to be transmitted via the data transmission section (35) is proposed, which data are synchronized in predefined time windows with interference-free periods of the energy transmission. |
| US09537532B2 |
Device for power line communication, method for transmitting signals, and method for receiving signals
A device for power line communication is provided, including a transmitter adapted to transmit signals on at least two of a plurality of power line transmission paths of a power line network; a sensor adapted to determine one or a plurality of reflection parameters of one of the plurality of power line transmission paths; and a transmission impedance matching unit adapted to match the output impedance of at least two output ports of the device which each couple to one of the plurality of transmission paths to the impedance of the at least two of the power line transmission paths based on the one or the plurality of reflection parameters. Further, a device including a corresponding reception impedance matching unit is provided and corresponding methods for transmitting and receiving signals. |
| US09537531B2 |
Communication device and its control method
A communication device includes a communication circuit capable of switching a reception or a transmission of a desired frequency signal through an antenna. The circuit includes an oscillator that oscillates a first frequency signal according to the desired frequency signal at a receiving time, a first divider that outputs a second frequency signal obtained by dividing the first frequency signal into two, a second divider that outputs a third frequency signal obtained by dividing the second frequency signal into two, a first mixer that mixes the reception signal received through the antenna and the first frequency signal and outputs an intermediate frequency signal, a second mixer that mixes the intermediate frequency signal and the third frequency signal and outputs a baseband signal, a third mixer capable of mixing the output from the first divider and the output from the second divider, and a filter circuit that eliminates a signal component of the frequency of an output signal from the third mixer from the reception signal at the receiving time. |
| US09537527B2 |
User terminal apparatus
A user terminal apparatus is provided. The user terminal apparatus includes: a flexible display including: a main area; and a sub area comprising a curved portion and extending from the main area to a side portion of the user terminal apparatus; a housing configured to enclose the flexible display; a sound output hole provided between the flexible display and the housing and configured to output a sound from a call function; and a sound input hole configured to receive an input sound. |
| US09537524B2 |
Protective case
A protective case is suitable for partially wrapping an electronic device. The protective case includes a casing, a kickstand and an elastic strip. The casing is suitable for partially wrapping the electronic device. The kickstand is connected to the casing. The elastic strip is located within the kickstand and elastically deforms to change a shape of the kickstand. When the casing leans against a plane, the shape of the kickstand is changed by the elastic deformation of the elastic strip so that the kickstand supports the casing in relative to the plane. |
| US09537523B2 |
Cover of a handheld electronic device
A cover configured to be attached to, and cover a portion of, a handheld electronic device. The cover includes a shell having a first side and a second side and a wireless charging receiver module connectable to the handheld electronic device. When attached to the handheld electronic device the first side of the shell faces the handheld electronic device. The wireless charging receiver module is positioned on the first side of the shell. |
| US09537522B2 |
Wireless communications capable power distribution unit and techniques for communicating therewith
Methods, systems, and devices for wireless communication between a PDU and one or more devices within a limited communications range are described. A power distribution unit may be provided with a wireless communications module that may operate to communicate with user devices within a relatively close proximity. The wireless communications module may provide information reporting and may, in some examples, provide a user of the user device with configuration and other command capabilities. |
| US09537521B2 |
System for and method of removing unwanted inband signals from a received communication signal
A system for and method of removing one or more unwanted inband signals from a received communications signal is described. The inband signal or signals may comprise noise, interference signals, or any other unwanted signals that impact the quality of the underlying communications. A signal attenuator is configured to selectively attenuate the one or more unwanted inband signals to form a modified received signal that includes the desired communication signal and the attenuated inband signals. A signal separator processes the modified received signal to form an estimate of the desired communication signal and an estimate of the inband signals. |
| US09537519B2 |
Systems and methods for performing power amplifier bias calibration
Wireless communications circuitry in an electronic device may include power amplifier circuitry that is powered using a bias voltage supplied by adjustable power supply circuitry. The power supply circuitry may include envelope tracking circuitry that continuously adjusts the bias voltage. The wireless communications circuitry may generate test signals and may generate performance metric data from the test signals. Processing circuitry may generate bias voltage calibration data based on the performance metric data and may provide the calibration data to the envelope tracking circuitry. After the calibration data has been generated, the envelope tracking circuitry may continuously select bias voltages to provide to the amplifier based on the magnitude of signals that are transmitted and the calibration data. By actively adjusting the bias voltage in this way, power consumption may be minimized without generating undesirable harmonics or other radio-frequency performance requirement violations. |
| US09537517B2 |
Method of controlling uplink noise level in multi-RU environment
Provided is a method of controlling an uplink noise level in a multi-radio unit (RU) environment in which each RU measures an ordinary noise level using a power monitoring function thereof when there is no user traffic and then controls an uplink noise level based on the ordinary noise level. |
| US09537512B2 |
Method and a system implementing a turbo-diversity scheme for wireless OFDM systems
The method comprising passing, a base station or a user terminal, information comprising data signals and encoding, a first and a second turbo encoders, said received data signals, generating two different turbo code blocks comprising a set of systematic and parity bits. Where, in order to enhance detection the two different turbo code blocks are simultaneously transmitted through a wireless OFDM system and wherein the data signals to be encoded by said second turbo encoder are interleaved prior encoding by an external bit interleaver.The system of the invention is arranged to implement the method of the invention. |
| US09537511B2 |
Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same
Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error. |
| US09537509B2 |
Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols. |
| US09537507B2 |
Monitoring method and device of two-channel bus data in network system
The present disclosure includes: a first channel unit configured to transmit and receive a data piece with a network bus, to convert the received data piece to an MII data piece, and to transmit and receive the converted MII data piece; a second channel unit configured to transmit and receive a data piece with the network bus, to convert the received data piece to an MII data piece, and to transmit and receive the converted MII data piece; a CPU configured to recognize a carrier detection signal (CRC) of the MII data received from the first channel unit and the second channel unit, and to transmit and receive the MII data; and a monitoring unit configured to perform a data communication with the CPU, and to monitor a data piece by each channel from the MII data received from the CPU. |
| US09537500B2 |
Input circuit for processing an analog input signal in the form of an analog measurement signal with a modulated additional signal and method for operating such an input circuit
An input circuit for processing an analog input signal in the form of an analog measurement signal with a modulated additional signal and for converting the input signal into a serial bit stream having a frequency distribution of high levels which is proportional to the input signal, and a method for operating such an input circuit, the input circuit including a device for comparing an instantaneous voltage value of the input signal with a variable comparison value and a device for adapting the comparison value to an instantaneous value of the generated bit stream, is provided. |
| US09537498B2 |
Method and system for charge compensation for switched-capacitor circuits
Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground. |
| US09537497B2 |
Continuous time delta sigma modulator, analog to digital converter and associated compensation method
A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit. |
| US09537493B2 |
Phase lock loop circuit having a wide bandwidth
A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal. |
| US09537492B2 |
Sampled analog loop filter for phase locked loops
An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter. |
| US09537491B1 |
Leaf-level generation of phase-shifted clocks using programmable clock delays
Methods and apparatus for generating multiple phase-shifted clock signals from a base clock signal using programmable delays at the leaf level in a clock distribution network are described. One example method for generating and distributing multiple phase-shifted clock signals in a programmable integrated circuit (IC) generally includes generating a base clock signal, routing the base clock signal through a clock distribution network in the programmable IC to a leaf node, and applying one or more programmable delays to the base clock signal received from the leaf node to generate the multiple phase-shifted clock signals. |
| US09537489B1 |
Level shifter with dynamic bias technique under overstress voltage
A level shifter for converting a first voltage range to a second voltage range includes a latch circuit, a stack device and a dynamic bias circuit. The latch circuit is used for outputting the second voltage range. The stack device, coupled to the latch circuit, includes a stack transistor, which is used for sustaining the second voltage range of the latch circuit. The dynamic bias circuit, coupled to the stack device, is used for turning on the stack transistor to toggle the latch circuit. |
| US09537487B2 |
Data control circuit
A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit. |
| US09537485B2 |
Adaptive dynamic keeper circuit
Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit. |
| US09537484B2 |
Semiconductor device and method of controlling the same
A semiconductor device comprises a plurality of circuit blocks, each of which performs an assigned operation, and performs a reset operation when recovering from a shutdown state of power supply, and a power control unit configured to control power supply to a power domain comprising at least one circuit block. The reset operation parameters of the plurality of circuit blocks as reset operation targets, for which power supply is resumed by the power control unit, are controlled so as to meet a power condition that makes the power dissipation of the semiconductor device by the reset operation not more than a predetermined power. |
| US09537481B2 |
DC insulation semiconductor relay device
A semiconductor relay device (1) includes a signal input unit (2) for inputting an alternating current signal for relay driving purpose, a direct current insulation member (3) for blocking a direct current electricity of the alternating current signal, a voltage multiplying circuit (5) for multiplying the signal voltage, after the direct current electricity has been blocked, by an integer number, and a relay circuit (4) including two metal-oxide semiconductor field-effect transistors (6, 7) having respective sources connected with each other and connected in a reverse series with each other and also having respective gates connected with each other. Those metal-oxide semiconductor field-effect transistors (6, 7) are caused to undergo a bidirectional ON-Off operation when the respective gates of those metal-oxide semiconductor field-effect transistors (6, 7) are brought into a conducting state by a signal of which voltage has been multiplied by the voltage multiplying circuit (5). |
| US09537480B2 |
Electronic device and state switching method based on electronic device
An electronic device is provided, which includes a fixing unit, a detection unit and a control unit. The fixing unit is adapted to maintain a position of the electronic device relative to a user when the user uses the electronic device. The detection unit is adapted to detect a spatial parameter of the electronic device being moved in a space. The control unit is adapted to obtain the spatial parameter, determine whether the spatial parameter matches a predetermined parameter condition, and control the electronic device to switch from a first operation mode to a second operation mode when the spatial parameter matches the predetermined parameter condition, wherein the first operation mode is different from the second operation mode. |
| US09537478B2 |
Semiconductor device
A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit. |
| US09537477B2 |
Semiconductor apparatus capable of converting a frequency of an input clock
A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals. |
| US09537476B1 |
Level shifter with low duty cycle variation
A level shifter that shifts a voltage level of an input signal, where the input signal oscillates between a voltage level of a first supply voltage and ground. The level shifter includes a bias circuit, and first and second transistors. The bias circuit provides a bias voltage to the first transistor based on the first supply voltage. The second transistor is connected in series with the first transistor, and the series combination is connected between voltage supplies that provide second and third supply voltages. The second transistor receives the input signal at its gate, and a level-shifted version of the input signal is output at a node between the first and second transistors. The level-shifted signal oscillates between the voltage levels of the second and third supply voltages. |
| US09537475B1 |
Phase interpolator device using dynamic stop and phase code update and method therefor
A method and device for dynamically updating a phase interpolator circuit module using an update control circuit module. The method can include providing the phase interpolator with a set of input clock phases to produce a clock signal. The update control module can generate a blanking signal in response to an update signal and apply an update process that stops an old clock output signal after a last clock pulse. The update control module can then update phase select multiplexers for a rising edge integrator and falling edge integrator according to a new phase interpolator code. The update control module can determine a phase jump code and then release the blanking signal during a discharge time interval of the rising edge integrator following a phase jump duration according to the phase jump code. Afterwards, the phase interpolator module can generate the new clock output signal without producing glitches. |
| US09537474B2 |
Transforming a phase-locked-loop generated chip clock signal to a local clock signal
Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal. |
| US09537470B2 |
Semiconductor device and method for operating the same
Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock. |
| US09537469B2 |
CMOS level shifter with reduced high voltage transistor count
A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a multiple-level current source to a high current mode, operating in a low current mode at other times. The current source feeds a differential pair of high voltage transistors with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal. An active load and buffer circuit receives current from the differential pair and drives the output accordingly. |
| US09537462B2 |
Communication circuit with impedance matching
Aspects of the present disclosure are directed to addressing impedance-matching issues. As may be implemented in connection with one or more embodiments, an apparatus includes an integrated circuit (IC) chip having a signal-connection terminal and processing circuitry that passes signals along a communication path that is within the IC chip and connected to the signal-connection terminal. Impedance-matching circuitry operates to provide impedance-matching for the communication path, therein mitigating signal loss due to impedance-mismatching. A chip-mounting structure secures the IC chip and electrically connects thereto at the signal-connection terminal. |
| US09537458B2 |
Feedback amplifier
Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal. |
| US09537456B2 |
Asymmetric multilevel backoff amplifier with radio-frequency splitter
A radio frequency (RF) amplification system or transmitter includes one or more power amplifiers and a controller that is configured to adjust amplitudes and phases of RF input signals of the one or more power amplifiers and supply voltages applied to the one or more power amplifiers. The system may include a single digital-to-RF modulator and a power divider to drive multiple power amplifiers. A power combiner may also be provided to combine outputs of the power amplifiers. In at least one implementation, amplitude adjustment of the RF input signals of the one or more power amplifiers may be used to provide transmit power control and/or power backoff. |
| US09537454B2 |
Electronic device for generation of an audible alarm or music
The electronic device is arranged for generation of an audible alarm or music. It includes a coil or inductor and a buzzer provided with a capacitor connected in series with the coil. When the electronic device is actuated, the buzzer generates the audible alarm or music. The electronic device further includes, in a feedback loop, a derivative circuit connected to a connection node between the coil and the capacitor, to produce a derivative of the signal from the capacitor, and a comparator for comparing a derivative signal from the derivative circuit with a reference voltage. The comparator supplies an output signal to the coil to amplify the signal across the capacitor, so that the buzzer generates at least one audible alarm. |
| US09537451B2 |
Amplifier having enhanced power efficiency
An RF amplifier with enhance power efficiency is disclosed. The RF amplifier traces the envelope of the input RF signal and varies the supply voltage to the final FET depending on the detected envelope through a linear power supply and a switching power supply superposed on the linear power supply. The linear power supply promptly responds the change of the envelope and gradually decreases the supply current as maintaining the supply voltage. The switching power supply takes over the supplement of the supply current to the final FET. |
| US09537445B2 |
Testing of a photovoltaic panel
A method for testing a photovoltaic panel connected to an electronic module. The electronic module includes an input attached to the photovoltaic panel and a power output. The method activates a bypass to the electronic module. The bypass provides a low impedance path between the input and the output of the electronic module. A current is injected into the electronic module thereby compensating for the presence of the electronic module during the testing. The current may be previously determined by measuring a circuit parameter of the electronic module. The circuit parameter may be impedance, inductance, resistance or capacitance. |
| US09537438B2 |
Buss potential isolation module
A genset includes a generator configured to generate a power signal having a first voltage. A controller is configured to monitor and control at least one operational parameter of the generator. A buss potential isolation module is configured to receive the power signal having the first voltage from the generator, reduce the first voltage to output a second voltage, and communicate the power signal having the second voltage to the controller. The second voltage is suitable for communicating to the controller which can include electronic circuitry configured to meet an NEC Class 2 circuit requirement. The first voltage can be at least 120 volts, and the second voltage can be less than 24 volts. |
| US09537433B2 |
Motor drive device
There is provided a motor drive device including, a current detection section that detects current flowing between a power source and an inverter circuit generating voltage to be supplied to a motor, a voltage control section that outputs a first control signal to cause the inverter circuit to generate a voltage for rotating the motor at a rotation speed based on an instructed value, and a rotation speed suppression section that, in cases in which current, detected by the current detection section at a timing at which a voltage generated by the inverter circuit rises from low level to high level, is a predetermined threshold value or higher, outputs a second control signal to the voltage control section to cause the inverter circuit to generate a voltage for rotating the motor at a lower rotation speed than the rotation speed based on the instructed value. |
| US09537431B2 |
Brake diagnosis device and brake diagnosis method
This disclosure discloses a brake diagnosis device configured to diagnose a brake of a motor with a brake. The brake diagnosis device includes a brake control part, a diagnosis part, and a signal output part. The brake control part is configured to actuate or release the brake. The diagnosis part is configured to diagnose a presence or absence of an abnormality of the brake while the brake is actuated by the brake control part. The signal output part is configured to output a signal related to a brake abnormality after the brake is released by the brake control part in a case that the diagnosis part diagnoses the brake as having an abnormality. |
| US09537430B2 |
Clamp with burls-electrode
Holding apparatus (100) for electrostatically holding component (1), (e.g., a silicon wafer), includes base body (10) composed of first and second plates (11A,12), the first plate being arranged on upper side (10A) of base body (10) and second plate (12) carrying first plate (11A), and second plate (12) being an electrically insulating material, a plurality of projecting, upper burls (13A) arranged on upper side (10A) and forming a support surface for component (1), and first electrode device (20A) having first electrodes (21A) arranged on upper side (10A) for receiving a clamping voltage, wherein first plate (11A) is produced from electrically conductive, Si-based ceramic and carries upper plate insulating layer (14A) which covers upper side (10A), having upper burls (13A), and the first electrodes (21A) include electrode layers arranged on upper burls (13A) and each carry upper electrode insulating layer (15A). A method for producing the holding apparatus is also described. |
| US09537429B2 |
Ultrasonic motor and lens apparatus including the same
Provided is an ultrasonic motor, comprising: a vibrator including a piezoelectric element and a contact surface to be brought into contact with a member to be driven, the vibrator driving the member to be driven by an ultrasonic vibration excited by the piezoelectric element; a holding part configured to hold the vibrator; a pressurization unit configured to apply a bias force for biasing the holding part toward the member to be driven so as to impress the contact surface against the member to be driven; and a fixing unit configured to support the pressurization unit, in which the holding part holds the vibrator on both sides of the contact surface in a driving direction of the member to be driven. |
| US09537425B2 |
Multilevel inverters and their components
A multilevel inverter includes a first half bridge in series with a second half bridge, each comprising a switch having a channel. The switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch. The inverter may also include a third half bridge. The inverter can be configured such that in operation, switches of the third half bridge are switched at a substantially lower frequency than the switches of the first and second half bridges. |
| US09537419B2 |
Power supply system and image forming apparatus having the same
A power supply system includes: a switching power supply configured to rectify and smooth an AC voltage of an AC power supply to generate a predetermined DC voltage; a low-capacity power supply circuit that generates a zero-cross detection signal corresponding to zero-cross points of the AC power supply based on a rectified current flowing in a smoothing capacitor; and a controller configured to receive the zero-cross detection signal from the signal generating circuit and perform a determining process of determining whether it is possible to perform detection process of the zero-cross points based on a voltage value of the zero-cross detection signal. If the control unit determines that it is possible to perform the detection process of the zero-cross points, the control unit performs a zero-cross point detecting process of detecting the zero-cross points based on the zero-cross detection signal. |
| US09537416B2 |
System and method for operating power converters
An electrical circuit for a power converter includes a first switching device proximate an AC source. The circuit also includes a voltage measurement device proximate a DC link and extends between the AC source and the DC link. The circuit further includes a DC voltage source and a first capacitive device. The first capacitive device is positioned between the first switching device and the voltage measurement device. The circuit further includes a second switching device positioned between the first capacitive device and the voltage measurement device. The circuit also includes a controller operatively coupled to the DC voltage source, the voltage measurement device, and the switching devices. The controller is configured to open the second switching device when a measured voltage signal generated by the voltage measurement device is substantially representative of a reference voltage value. |
| US09537411B2 |
Flyback active clamping power converter
A flyback active clamping power converter is disclosed. The flyback active clamping power converter comprises an input inductor, a down-bridge switch, an up-bridge switch, a first energy-storing capacitor, a clamping capacitor, a resonant inductor, a magnetizing inductor, a transformer, an output diode and an output capacitor. When a resonant frequency generated by the resonant inductor and the clamping capacitor in the flyback active clamping power converter is substantially equal to a switching frequency, the output diode is able to perform a zero current switching in the whole load range. |
| US09537406B1 |
Flyback controller featuring bidirectional power control and parallelly-connected power modules
A flyback controller featuring bidirectional power control and parallelly-connected power modules is based on flyback DC-DC converters for allowing bidirectional energy flow and transformation. The flyback controller includes two bidirectional DC-DC converters that are connected in parallel. The bidirectional DC-DC converters are electrically connected with a digital-signal processor. The digital-signal processor controls the bidirectional DC-DC converters and current thereof, so that the current flows evenly across the bidirectional DC-DC converters. Thereby, the flyback controller has advantages about simplified components and increased power output, and is suitable for testing secondary batteries. |
| US09537405B2 |
Power converter with power foldback
A controller for use in a power converter includes a drive circuit coupled to control switching of a power switch of the power converter to regulate the output of the power converter. A limit sense circuit is coupled to output a limit sense signal in response to a condition of the power converter. The drive circuit is coupled to operate in a first operation mode if there is a no limit condition. The first operation mode includes regulating the output of the power converter with a regulated output voltage and a first maximum output current. The drive circuit is coupled to operate in a second operation mode if there is a limit condition. The second operation mode regulating the output of the power converter with the regulated output voltage and a second maximum output current wherein the second maximum output current is less than the first maximum output current. |
| US09537404B2 |
AC-DC power supply input voltage detection and monitoring
A power converter includes a transformer with a primary and a secondary winding and a switch. A controller of the power converter at the primary winding side of the transformer generates a control signal to turn on or turn off the switch, the switch being turned on responsive to the control signal being in a first state and the switch being turned off responsive to the control signal being in a second state. The controller determines current through the primary winding generated while the switch is turned on and indirectly detects an input voltage to the power converter based on the current through the primary winding generated while the switch is turned on. The controller in turn may detect conditions such as a loss of power or brown out at the input of the power converter based on the indirectly detected input voltage. |
| US09537403B2 |
Control circuit for a switched-mode power supply
A control circuit for a switched-mode power supply having an input side (101) connectable to an electrical power source and an output side (102) connectable to a load. The control circuit comprises: a primary control circuit (140) adapted to generate a driving signal for a switching element (110) at the input side of the power supply; a secondary control circuit (150) adapted to monitor an output signal at the output side (102) of the power supply; and an opto-coupler (300, 400), wherein the opto-coupler is arranged to receive its input from the secondary control circuit and to provide a control signal to the primary control circuit, and the primary control circuit comprises a compensation circuit (900, 1000, 1100, 1400, 2010, 2610) adapted to process the control signal to generate a compensation signal for reducing power consumption in the opto-coupler, wherein the compensation circuit is adapted to generate the compensation signal such that a current in the opto-coupler tends to return to a desired minimum value. |
| US09537402B2 |
Electric power converter
An electric power converter is equipped with a master converter and a slave converter that are connected in parallel with each other, and to a load. The master converter operates having priority over the slave converter. The slave converter includes a voltage sensor for detecting an output voltage of the electric power converter and a control unit for controlling an output of the slave converter based on a target command value. The control unit selects a current command value Ic2 received from the master converter as a target command value when a variation ΔV per predetermined time of a detected output voltage Vo2 is lower than a variation ΔVth1. The control unit selects a voltage command value Vc2a calculated so as to suppress the output voltage Vo2 from changing as the target command value when the variation ΔV exceeds the variation ΔVth1. |
| US09537400B2 |
Switching converter with dead time between switching of switches
A device and method for operating a switching power converter are disclosed. In an embodiment a circuit includes a switching power converter having a half bridge including a high-side semiconductor switch connected to a low-side semiconductor switch and an inductor coupled to a half-bridge output node. The circuit further includes a control circuit configured to generate drive signals to switch the high-side semiconductor switch and the low-side semiconductor switch on and off, wherein the drive signals are generated to ensure a dead time between a switch-off of the low-side switch and a subsequent switch-on of the high side switch, and wherein the dead time is set to a first value, when an inductor current is negative at a time of switching, and the dead time is set to a second value, which is lower than the first value, when the inductor current is positive at the time of switching. |
| US09537390B2 |
Control circuit, control method, DC-DC converter and electronic device
A control circuit (115), a control method, a DC-DC converter and an electronic device are provided. The control circuit (115) is used to control the DC-DC converter to switch its operation modes. In the control circuit (115), whether mode of the DC-DC converter is to be switched is judged according to parameters of a first duration of an active duration and a second duration of an inactive duration. Comparison of analog values is prevented, and as a result, the use of the analog comparator is reduced, thus the influence of the semiconductor processes on designing a controller can be reduced. |
| US09537384B2 |
Power supply noise reduction circuit and power supply noise reduction method
To provide a power supply noise reduction circuit and a power supply noise reduction method that do not require circuit elements to be increased in size and do not cause voltage drop in a power supply voltage. A power supply noise reduction circuit 10 that reduces noise included in a constant voltage output that is output from a power supply 2 to a load includes a first resistor 20 that is inserted into a power supply line L1 extending from the power supply 2 to the load, a filter 31 that is coupled to a load terminal of the first resistor 20 and outputs a first voltage that is obtained by reducing the noise from the constant voltage output, and a unity gain amplifier 32 that drives the first voltage output from the filter 31 and outputs the driven first voltage to the load terminal of the first resistor 20. |
| US09537381B2 |
Motor for compressor and reciprocating compressor having the same
A motor for a compressor, and a reciprocating compressor having the same, are provided. A winding coil may be formed by removing a bobbin from the winding coil, and then coating an insulating material on an outer circumferential surface of the winding coil, to allow heat and moisture generated by the winding coil to be emitted to outside and provide enhanced performance and reliability. As a bobbin is removed from the winding coil, a coil line may be wound on the removed portion of the bobbin to enhance an occupation ratio by the coil line on the same area, and thus enhance efficiency of the motor. An elastic member or an adhesive may be inserted or applied into a space between the winding coil and a coil insertion groove of an inner stator to minimize vibrations of a coil line. The insulating material, which is in the form of powder, may melt while the coil line is adhered as the self-bonding material melts, forming a coating layer. Accordingly, the winding coil may be easily fabricated, and fabrication costs of the winding coil may be reduced. |
| US09537380B2 |
Permanent-magnet type rotating electrical machine
A permanent-magnet type rotating electrical machine, including a rotor including a plurality of magnetic poles arranged at an equal interval, and a stator including a plurality of teeth and a plurality of armature windings. A high frequency voltage different in frequency and amplitude from voltages for generating a torque is applied to the armature windings. A magnetic pole position of the rotor is estimated by using a current trajectory of a measured high frequency current. When dq transform is applied to the measured high frequency current, a current trajectory forms an ellipse on d and q axes. Angular variation ranges of a major axis of the ellipse with respect to a load current and a rotor position are set so as to acquire a predetermined position estimation resolution. |
| US09537378B2 |
Audible warning system for generator system
An audible warning system for a generator system is provided. The generator system includes a surge suppressor and a rectifier assembly. The rectifier assembly rotates along with the rotor of the generator system, and generates airflow. The surge suppressor includes a face portion. The audible warning system includes a mounting plate and an acoustic alarm device. The mounting plate is attached to the rectifier assembly to mount the surge suppressor and the acoustic alarm device. The acoustic alarm device includes an air inlet portion in engagement with a face portion of the surge suppressor. In operation, this arrangement blocks fluid communication of the airflow into the air inlet portion, in an operational state. A failure of the surge suppressor allows the airflow to pass through the air inlet portion to generate an audible alarm for an operator. |
| US09537370B2 |
Hand-held machine tool with fan arrangement
Hand-held machine tool having an outer housing extending substantially along a longitudinal axis, with an electric drive unit accommodated in this outer housing, and with a tool arrangement which is disposed at a first end of the electric drive unit. The outer housing of the machine tool has a defined inner contour and the electric drive unit and the tool arrangement have a defined outer contour. The outer contour and the inner contour of the outer housing are at a predetermined minimum spacing from each other. At least one inlet opening for cooling air is disposed in an end region of the outer housing. The electric drive unit drives a fan arrangement which draws in through the at least one inlet opening cooling air which flows substantially parallel to the rotational axis of the electric drive unit through the machine tool and flows out of the outer housing to the outside at the outer contour of the machine tool. |
| US09537364B2 |
Rotary electric motor stator with thermally expanding layered slot liner
In an expansion sheet for a rotary electric machine that has a thermal expansion property and is to be arranged between a core and a coil conductor in a slot in the rotary electric machine, in which the coil conductor is housed in the slot formed in the core, the expansion sheet has a first surface and a second surface and includes: a first surface-side portion; and a second surface-side portion that is closer to the second surface than the first surface-side portion. An amount of volume increase, caused by heating, of the first surface-side portion is higher than an amount of volume increase, caused by the heating, of the second surface-side portion. |
| US09537362B2 |
Electrical machine with improved stator flux pattern across a rotor for providing high torque density
An electrical machine includes a rotor comprising a rotor core and a plurality of permanent magnets embedded radially within the rotor core to form a plurality of rotor poles. The electrical machine further includes a stator comprising a stator core disposed concentrically outside the rotor and including a plurality of stator teeth defining a plurality of stator slots there between. An arithmetic sum or difference of twice the number of stator teeth and the number of the stator poles equals the number of rotor poles. |
| US09537361B2 |
Rotor and electric rotating machine
A rotor is provided which includes a first rotor portion, a second rotor portion which is arranged at a position deviated from the first rotor portion by a predetermined skew angle so as to contact the first rotor portion, first magnets each of which is provided in a magnetic pole of the first rotor portion, and second magnets each of which is provided in a magnetic pole of the second rotor portion and is arranged at a position deviated from the first magnet of the first rotor portion by the predetermined skew angle. Coercive field strengths of the first magnets and coercive field strengths of the second magnets are different from each other. |
| US09537360B2 |
Rotor comprising interpolar regions with cooling channels
The invention relates to a rotor for a rotary electric machine, extending along a longitudinal axis and including: an assembly of electrical sheets forming projecting poles, two projecting poles defining an interpolar region therebetween; and at least two internal cooling channels formed in the assembly of electrical sheets in at least one interpolar region. |
| US09537359B2 |
Sub-apertures for wireless power transfer
A signal generator generates an electrical signal that is sent to an amplifier, which increases the power of the signal using power from a power source. The amplified signal is fed to a sender transducer to generate ultrasonic waves that can be focused and sent to a receiver. The receiver transducer converts the ultrasonic waves back into electrical energy and stores it in an energy storage device, such as a battery, or uses the electrical energy to power a device. In this way, a device can be remotely charged or powered without having to be tethered to an electrical outlet. |
| US09537358B2 |
Laptop computer as a transmitter for wireless sound charging
Configurations and methods of wireless sound power transmission using a laptop computer may include a transmitter and/or a receiver embedded in the laptop screen. The embedded transmitter may emit SW waves for the generation of pockets of energy that may be utilized by receivers in peripheral devices for charging or powering. Meanwhile, the receiver embedded in the laptop computer may collect SW waves from a separate transmitter for charging or powering the laptop computer. |
| US09537357B2 |
Wireless sound charging methods and systems for game controllers, based on pocket-forming
The present invention provides wireless charging methods and systems for powering game controllers. The methods and systems may include one or more transmitters and one or more receivers. In some embodiments the transmitters and receivers may be embedded to game console and game controllers, respectively. In other embodiments, the transmitters and receivers may be connected as a separate device to the game console and game controllers, respectively. The method may include wireless power transmission through suitable techniques such as pocket-forming utilizing sound waves. |
| US09537353B1 |
Methods for detecting mated coils
Methods and systems for improved efficiency when an inductive power transmitter associated with an inductive power transfer system experiences a low-load or no-load condition. More particularly, methods and systems for detecting when an inductive power receiver is absent or poorly connected to an inductive power transmitter. The inductive power transmitter includes, in one example, a current peak monitor coupled to an inductive power transmit coil. The current peak monitor waits for a current peak resulting from spatial displacement of a magnetic field source within the inductive power receiver, indicating to the inductive power transmitter that the inductive power receiver is moving, or has moved, toward the inductive power transmitter. Other examples include one or more Hall effect sensors within the inductive power transmitter to monitor for the magnetic field source of the inductive power receiver. |
| US09537350B2 |
Switch-mode power supply with a dual primary transformer
A switch-mode power supply that includes a transformer coupled to an alternating current (AC) power source and a direct current (DC) power source, wherein the AC power source is electrically isolated from the DC power source. The switch-mode power supply further includes a first controller configured to regulate a first voltage output from the AC power source, and a second controller configured to regulate a second voltage output from the DC power source when the transformer is not receiving power from the AC output. |
| US09537349B2 |
Power supply system having an emergency power supply cutoff function
A power supply system having a power supply cut-off function in an emergency is provided. The present system includes a power supply device for receiving and supplying external input power to a device for power supply, a remote controller for controlling an operation of the power supply device according to a remote control signal from a remote place, an uninterruptible power supply device for supplying operation power to the remote controller, a first line switch for, when a power switch is turned on, supplying the external input power to the power supply device and the uninterruptible power supply device, and a second line switch disposed between the power supply device and the first line switch and cutting off the external input power supplied to the power supply device via the first line switch when the uninterruptible power supply device does not output the power. According to the present invention, even when the remote controller is out of order in the emergency, the power supply of the power supply device can be cut off using the interrupted power supply device to thus enhance stability and reliability of the equipment. |
| US09537348B2 |
Static transfer switch
A static transfer switch is used for switching an output load from a first power source to a second power source. A first switching unit has a first pair of silicon controlled rectifiers (SCR). A second switching unit has a second pair of SCRs arranged in an anti-parallel configuration. The control circuit determines whether at least one of the SCRs is activated in accordance with the voltage between the gate and the cathode of the at least one SCR. If the voltage between the gate in the cathode is at least 150 mV, the control circuit indicates that the at least one of the SCR is activated. |
| US09537345B2 |
Wireless charger and charging method
A wireless charger charges an electronic device. The wireless charger receives radio frequency (RF) from a wireless power transmitter and generates alternating current (AC) electricity. The wireless charger coverts the AC electricity to direct current (DC) electricity and charges the electronic device using the DC electricity. |
| US09537342B2 |
Method and device for charging batteries by linearly increasing the charging voltage
A method and to a device for charging batteries, in particular lead-acid batteries, having a predetermined end-of-charge voltage (ULS). In order to charge the battery as efficiently and smoothly as possible, and in order to increase the service life of the battery, according to the invention the charge state of the battery is established before the charging process and a charging current (IL) or a charging voltage (UL) is applied to the battery during the charging process and is regulated in such a manner that the charging voltage (UL) is increased during a predetermined charging time (t′charge) between a charge starting voltage (ULA) and the end-of-charge voltage (ULS). |
| US09537338B2 |
Level shift and inverter circuits for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. |
| US09537335B2 |
Adapter for power tools, power tool system and method for wirelessly communicating maintenance information therefor
An adapter for a power tool powered by a detachable battery pack which adapter includes a connector configured to detachably connect the adapter directly to the power tool, an adapter controller, at least one memory and/or storage device in communication with the adapter controller and configured to store maintenance information concerning the battery pack or to store maintenance information concerning the battery pack and the power tool, at least one communication port configured to transmit electrical communications, including said maintenance information, from the adapter controller to a controller located in the power tool and vice versa, and a transmitter configured to wirelessly transmit the maintenance information to an external device. |
| US09537327B2 |
Battery cell balancing control system and battery management method thereof
A battery cell balancing control system and a battery management method thereof are disclosed. The battery cell balancing control system is used for managing a battery apparatus, wherein the battery apparatus has a plurality of battery cells. The battery cell balancing control system comprises a detection module, a battery management module, and an adjusting module. The detection module is used for executing a battery checking procedure on the plurality of battery cells to generate a detection result. The battery management module is used for determining whether the plurality of battery cells has a controlled cell according to the detection result. If the controlled cell has not been found among the plurality of battery cells, the battery management module controls the adjusting module to execute a battery cell balancing procedure until the controlled cell is found. |
| US09537326B2 |
Batteries, battery systems, battery submodules, battery operational methods, battery system operational methods, battery charging methods, and battery system charging methods
Batteries, battery systems, battery submodules, battery operational methods, battery system operational methods, battery charging methods, and battery system charging methods are described. According to one aspect, a battery includes a first battery terminal, a second battery terminal, and a plurality of submodules individually comprising a first submodule terminal, a second submodule terminal, a plurality of rechargeable cells electrically coupled between the first and second submodule—terminals, and switching circuitry configured to electrically couple one of the first and second battery terminals with one of the first and second submodule terminals of one of the submodules during an engaged mode of operation of the one of the submodules and to electrically isolate the one of the first and second battery terminals from the one of the first and second submodule terminals of the one of the submodules during a disengaged mode of operation of the one of the submodules. |
| US09537323B2 |
Contactless power supplying system with power limiting control
Provided is a contactless power supplying system which is efficient and can be built of small coils by appropriately limiting power to be inputted into a transmitting coil. In the contactless power supplying system, power transmitted from a transmitting coil is received by a receiving coil by means of magnetic coupling, and the contactless power supplying system includes a power control unit configured to cause power from a power source to flow through the transmitting coil and a control unit configured to perform power limiting control of limiting the power flowing through the transmitting coil by controlling the power control unit. |
| US09537320B2 |
Communication power with multi-energy-source supply and control method
The present disclosure discloses a communication power with multi-energy-source supply and a control method. The communication power includes: an inputting unit (21), configured to receive at least two kinds of electrical energy and provide the at least two kinds of electrical energy to an allocating unit (22); the allocating unit (22), configured to allocate at least one kind of electrical energy of the at least two kinds of electrical energy determined by a monitoring unit (25) to a power converting unit (23) according to the control of the monitoring unit (25); the power converting unit (23), configured to perform power conversion on the at least one kind of electrical energy allocated by the allocating unit (22), and then provide the converted power to an outputting unit (24); the outputting unit (24), configured to supply power to an external load; and the monitoring unit (25). With the present disclosure, the modules for input allocating, power converting, etc. for different energy sources may be shared, and overall management may be achieved for multiple energy sources. |
| US09537318B2 |
Modular energy storage system
An energy storage system includes modular energy storage equipment that may be connected to an external system, such as a power grid. In at least one embodiment, the energy storage system includes a power transfer control system comprising a power transfer network and a processing module or controller. The power transfer network has a first interface coupleable to one or more energy storage units and a second interface coupleable to one or more power conversion units. One or more conductors in the power transfer network are selectively coupleable to the first interface and the second interface for transferring power between the energy storage units and the power conversion units based at least in part on information indicating a power or energy supply or demand of an external system or information indicating an amount of energy stored in the energy storage units. The energy storage system is scalable for different implementations. |
| US09537316B2 |
Power management circuit for a multi-phase power supply
A power management circuit for a multi-phase alternating current (AC) power supply is provided to manage a single phase bad, connected thereto, during a brownout condition. The management circuit is configured to switch the single phase electrical bad from an affected conductor of the AC power supply and to connect the single phase electrical bad between two unaffected conductors of the AC power supply thereby ensuring continued supply of voltage to the single phase electrical load. |
| US09537315B2 |
Generator load control
A power system for an electrical system with highly fluctuating loads is powered by one or more power sources that are slow to react to load changes. The power sources are connected to electrical equipment used on the drill rig which provide active load to the generators. One or more load banks may be positioned to provide passive load to the generators to maintain generally constant generator load, while allowing for instant access to power as active load increases. Generators may be run at 100% capacity, a maximum efficient capacity, or at a high enough level to allow for a sufficiently rapid increase in power output. At least one parameter of a drilling operation may be utilized to anticipate load demand changes. |
| US09537308B2 |
ESD protection using shared RC trigger
In one embodiment, an integrated circuit includes multiple I/O banks, each bank having multiple I/O-ESD tiles, each tile having one or more I/O circuits and electrostatic discharge (ESD) protection circuitry for the one or more I/O circuits in the tile. The ESD circuitry for one tile includes at least one RC-triggered clamp, whose resistance is provided by a resistor shared by one or more other RC-triggered clamps in one or more other tiles of the same bank and whose capacitance is provided by a combination of distributed capacitors, one for each of those two or more RC-triggered clamps. Each tile may have multiple instances of such RC-triggered clamps providing ESD protection for different (e.g., power supply and/or bus) nodes. The shared resistors are variable to allow different instances of the same ESD circuitry design to be implemented with the same time constant for different banks having different numbers of tiles. |
| US09537302B2 |
Charge injection and drain-based electrical overstress (EOS) protection apparatus and method
An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal. |
| US09537300B2 |
Load driving device
A load driving device includes a driving switching element, an interrupting part, a short-circuiting switching element, and a protecting element. The driving switching element drives a load by controlling energization to the load. The interrupting part is disposed on an energizing path to the load. The interrupting part is not melted by a driving current to the load and is melted by an interrupting current larger than the driving current so as to interrupt energization to the load. The short-circuiting switching element is connected in parallel with the load and applies the interrupting current to the interrupting part. The protecting element protects the short-circuiting switching element. |
| US09537297B2 |
Automatic splice water drip nose cone
A device for preventing the intrusion of water or other liquids into the interior of an automatic splice. The device includes a series of fingers that contact the cable stranding and wick water away from the cable and out of the connector. These fingers could be integrally molded into the cable cone or molded as a separate piece and inserted. They could also be constructed of any typical brush material such as metal, plastic, rubber, or fiber. The fingers could be arranged in a variety of configurations. |
| US09537293B2 |
Wire pulling head apparatus with crimp zone indicators and method of using same
An enhanced apparatus and method for securing a wire to a pulling cable for pulling wire. Specifically, the pulling cable and wire are attached via a pulling head body. The wire is inserted into an end of the pulling head body and secured by crimping the pulling head body against the wire. Further, crimp zone indicators positioned on the outer surface of the pulling head body indicate the optimal zone of crimping to achieve substantial contact between the pulling head body and the wire. A pulling cable is secured to the pulling head body via a ball swage that comprises a tapped surface. |
| US09537291B1 |
Elevated automatic transfer switch cabinet
An elevated automatic transfer switch (ATS) cabinet provides modular and incremental power support redundancy to a set of electrical loads which reduces capital waste and increases the floor space which can be occupied by electrical loads. The cabinet includes a mounting element which can be coupled to a free-standing structure proximate to the floor space, so that the cabinet is supported by the structure in an elevated position and is freed from occupying floor space. The cabinet includes slots in which separate ATS modules can be installed via blind mate connections, thereby enabling modular and incremental installation of ATS support capacity in the cabinet based on incremental installation of electrical loads. The cabinet can physically couple with power cables extending from separate electrical loads, so that the cabinet electrically couples ATS modules to electrical loads independently of branch circuits between the cabinet and the electrical loads. |
| US09537287B2 |
Thermal compensation for burst-mode laser wavelength drift
An apparatus comprising a burst-mode laser comprising an active layer and configured to emit an optical signal during a burst period, wherein a temperature change of the burst-mode laser causes the optical signal to shift in wavelength, and a heater thermally coupled to the active layer and configured to reduce a wavelength shift of the optical signal during the burst period by applying heat to the active layer based on timing of the burst period. |
| US09537284B2 |
Semiconductor laser assembly and packaging system
A system for self-aligning assembly and packaging of semiconductor lasers allows reduction of time, cost and testing expenses for high power density systems. A laser package mounting system, such as a modified TO-can (transistor outline can), has modifications that increase heat transfer from the active laser to a heat exchanger or other heat sink. A prefabricated heat exchanger assembly mounts both a laser package and one or more lenses. Direct mounting of a fan assembly to the package further minimizes assembly steps. Components may be physically and optically aligned during assembly by clocking and other indexing means, so that the entire system is self-aligned and focused by the assembly process without requiring post-assembly adjustment. This system can lower costs and thereby enable the use of high powered semiconductor lasers in low cost, high volume production, such as consumer items. |
| US09537283B2 |
Laser with transmission and reflection mode feedback control
One embodiment is directed towards a stabilized laser including a laser to produce light at a frequency and a resonator coupled to the laser such that the light from the laser circulates therethrough. The laser also includes Pound-Drever-Hall (PDH) feedback electronics configured to adjust the frequency of the light from the laser to reduce phase noise in response to light sensed at the reflection port of the resonator and transmission port feedback electronics configured to adjust the frequency of the light from the laser toward resonance of the resonator at the transmission port in response to the light sensed at the transmission port of the resonator, wherein the transmission port feedback electronics adjust the frequency at a rate at least ten times slower than the PDH feedback electronics. |
| US09537278B2 |
Terminal group and connector
A terminal group includes: a plurality of pin terminals, each pin terminal being formed of a metal wire of a predetermined length and being to be press-fitted and held in each of a plurality of terminal insertion holes of a connector housing. Some of the plurality of pin terminals have different overall lengths. The plurality of pin terminals respectively have a pair of press-fitting supports that protrude from both side edges of each of the plurality of pin terminals in a width direction at the same distant positions from a distal end in an insertion direction, and insertion direction rear end side surfaces of the press-fitting supports receive reaction force with respect to the terminal insertion holes in press-fitting. |
| US09537272B2 |
Reinforcing structure of electrical receptacle connector
A reinforcing structure of an electrical receptacle connector includes an insulation housing, a terminal group, and a reinforcing sheet. The insulation housing includes a substrate and a tongue portion extending to one side of the substrate. The tongue portion includes a top surface, a bottom surface, and a front side surface between the top surface and the bottom surface. The terminal group is provided on the bottom surface, and includes a power supply terminal and a grounding terminal. A contact wall is formed between the power supply terminal and the front side surface, and the reinforcing sheet is provided on the top surface. The reinforcing sheet includes a front baffle and a recessed portion, the front baffle is fixed on the front side surface, and the recessed portion inwardly curves to be formed on the front baffle and corresponds to the contact wall. |
| US09537270B2 |
Method and apparatus for connectivity plug switch
In accordance with an example embodiment of the present invention, a method is disclosed. A connector plug housing member is provided. A movable member is mounted inside the connector plug housing member. A contact member is provided inside the movable member. The movable member is configured to move between a first position and a second position. The movable member is configured to be connected to ground when the movable member is moved from the first position to the second position. |
| US09537267B2 |
Connector for a safety restraint system
The present invention relates to squib connectors, for instance for airbag ignition systems, which allow the electrical or electronic monitoring of the correct coupling of a squib plug connector with its corresponding counterpart. According to the invention, a squib connector has at least two terminals having corresponding signal lines. In order to allow an electrical monitoring of the correct coupling of the plug connector, the terminals are in electrical contact with each other in the uncoupled or incorrectly coupled condition of the plug connector. This electrical contact between the terminals is configured to be separated upon correct coupling to a corresponding counter-connector either automatically or by an actuating action. The disconnecting of the terminals may then be monitored by any suitable monitoring means. |
| US09537266B1 |
Power strips with voice message playback
Power strips are provided having voice message playback capabilities, which enable a user to selectively playback stored voice messages or verbal memorandum identifying the particular electronic devices plugged into the power strip outlets. In this manner, a user need only trigger playback of a voice message to determine the identity of an electronic device plugged into a given outlet. This may be particularly beneficial when several electronic devices are plugged into the power strip, which is located underneath a desk, behind an entertainment center, or in another difficult-to-access area. In certain embodiments, the power strip enables the user to record personalized voice messages identifying the electronic devices plugged into the power strip outlets, possibly along with additional information pertaining to the plugged-in devices and considered pertinent by the user. Embodiments of the power strips described herein may also be beneficially used by the blind and visually impaired. |
| US09537265B1 |
Power connector, and electrical connection element and arc suppression method therefor
An electrical connection element is for a power connector. The power connector has an electrical component having a number of first electrical mating members. The electrical connection element includes a housing having a number of second electrical mating members structured to be electrically connected to the number of first electrical mating members, a contact assembly structured to move between an OPEN position and a CLOSED position, the contact assembly including a number of sets of separable contacts each structured to be electrically connected to at least one of the number of second electrical mating members, and an arc suppression system for redirecting current away from at least one of the sets of separable contacts in order to suppress arcing. |
| US09537262B2 |
Printed circuit boards for communications connectors having openings that improve return loss and/or insertion loss performance and related connectors and methods
Printed circuit boards for communications connectors are provided that include a dielectric substrate formed of a first insulative material having a first dielectric constant. First and second pairs of input terminals and first and second pairs of output terminals are provided on the dielectric substrate. A first differential transmission line electrically connect the first pair of input terminals to the first pair of output terminals, and a second differential transmission line electrically connect the second pair of input terminals to the second pair of output terminals. The dielectric substrate includes an opening that is positioned between the conductive paths of the first differential transmission line, the opening containing a second insulative material having a second dielectric constant. |
| US09537258B2 |
Self unplugging power connector with load current sensing
A self unplugging power connector for charging mobile devices is provided. The self unplugging power connector includes electrical contact members for an electrical outlet, a release mechanism to remove the electrical contact members from the outlet and a current sensing circuit to activate the release mechanism when the circuit senses a current reduction. |
| US09537255B2 |
Connector fitting structure
A connector fitting structure includes a female connector without a rotating member and an elastic sealing part arranged on the female member. The female connector is configured so as to be engageable with a male connector having a guide groove formed for the rotating member. The male connector is provided with a fitting recess. The guide groove is formed on an outer circumferential face of the fitting recess. The male connector is configured so as to be engageable with another female connector with the rotating member for moving at least one of the male and female connectors in a fitting direction. The female connector includes a fitting protrusion for engagement with the fitting recess. The elastic sealing part is arranged on an outer circumferential face of the fitting protrusion to continuously adhere to an inner circumferential face of a fitting-side end portion of the fitting recess along the circumferential direction. |
| US09537254B2 |
Connector having a floatable holder with a magnet
A connector including a housing, a magnet, and a holder. The holder is accommodated in the housing in a floatable manner and configured to hold the magnet. The holder includes a mounting wall. The mounting wall is disposed around and in spaced relation to the magnet and bonded to the magnet. |
| US09537251B2 |
Securing device for GIS
A fastener device for a gas-insulated substation (GIS) type installation comprising a threaded shank and a ring including a duct configured to receive the threaded shank, the ring being housed in a supporting insulator of the invention. |
| US09537250B2 |
Electrical receptacle connector
An electrical receptacle connector includes an insulated housing, plate terminals, and a metallic shell. The insulated housing includes a base portion. The plate terminals are at the insulated housing. The plate terminals include soldering segments exposed out of the bottom of the base portion. The metallic shell encloses four sides of the insulated housing and includes a top cover plate, a rear cover plate, and pins. The top cover plate is located atop the base portion. The rear cover plate is extending downwardly to the rear side of the base portion from the rear side of the top cover plate. The rear cover plate includes a bottom surface and a bent sheet substantially perpendicular to an outer wall of the rear cover plate and extended outward from the outer wall of the rear cover plate, and the pins are extending downwardly from the bottom surface. |
| US09537240B2 |
Electric connector
Provided is an electric connector mounted on a circuit board, including: a housing including a fitting portion fitted to a mating connector; a plurality of terminals disposed on the fitting portion; and lock metal fittings including an elastic portion and preventing separation of the mating connector, wherein the housing includes accommodating portions at both ends of the housing in the arrangement direction of the terminals to accommodate the lock metal fittings in the accommodating portions, and each of the lock metal fittings includes a fixed portion formed at one end of the lock metal fitting and fixed to the circuit board, a preventing surface formed at the other end of the lock metal fitting and preventing separation of the mating connector, a first folded portion extended from the preventing surface and folded in a substantially U shape, a second folded portion extended in the separation direction of the mating connector from the fixed portion, folded in a substantially U shape, and coming into contact with the first folded portion in the process of fitting of the mating connector, and a pair of projecting portions provided at the distal end of the first folded portion or in the vicinity of the distal end of the first folded portion, projecting in a direction crossing the arrangement direction of the terminals, and coming into contact with contact surfaces formed on the accommodating portion of the housing on the side in the separation direction of the mating connector. |
| US09537236B2 |
Board mount electrical connector assembly
An electrical connector includes an insulative connector housing including a longitudinal bottom wall defining a plurality of contact openings for receiving a plurality of contacts, first and second side walls extending upwardly from the bottom wall at opposing sides thereof, first and second end walls extending upwardly from the bottom wall at opposing ends thereof, first and second pairs of latch openings at opposing ends of the bottom wall, and first and second protrusions extending upwardly from the bottom wall and disposed between respective first and second pairs of latch openings. Each latch opening extends through the bottom wall and through a side wall and is configured to allow a latch to eject a mating connector by moving within the opening. Each of the protrusions is configured to engage a corresponding opening in a latch of a mating connector cover or strain relief assembled to the electrical connector. |
| US09537233B1 |
Storage device connector
Technology is provided for a connector for use with an M.2 memory module. The connector comprises a connector body including a mounting surface, first and second receptacles oriented perpendicular to the mounting surface, and a plurality of terminals extending through the mounting surface and into the first and second receptacles. |
| US09537231B2 |
Connector assembly
A connector assembly includes a center contact configured to be terminated to a center conductor of a cable. A dielectric holds the center contact. An outer contact surrounds the dielectric and the center contact. The outer contact has a mating segment extending from a mating end, a terminating segment extending from a cable end, and a middle segment between the mating and terminating segments. The terminating segment is configured to be terminated to a braid of the cable. The middle segment has a diameter that is less than the respective diameters of the mating and terminating segments. A cavity insert surrounds the middle segment of the outer contact. The cavity insert includes a receiving shell and a closing shell that are joined together at an interface. |
| US09537229B2 |
Electrical grounding device
An electrical grounding device comprises an elongate shaft with plate members projecting radially outward from a lower region of the shaft. The shaft and plate members are made of an electrically-conductive material, and are connected such that an electric current can flow between the plates and the shaft. The device is installed by boring a hole into the earth to a selected depth less than the length of shaft above the plates. The grounding device is inserted into the borehole and driven into the earth below the borehole until the upper end of the shaft projects a desired distance above the adjacent earth surface, leaving the shaft projecting sufficiently to allow connection of grounding cables. The borehole is preferably filled with gravel or other suitable fill material, and water may be added to the fill to enhance electrical conductivity between the device and the earth. |
| US09537228B2 |
Electric connection terminal
A connection terminal for connecting at least one conductor to a current bar, which is accommodated on a mount, in an electrically contacting manner, includes at least one clamping spring for applying a clamping force, the at least one clamping spring including a pivotable clamping lever for clamping the conductor. The clamping spring has a first leg and at least a second leg, is hingedly coupled to the clamping lever by the first leg, and is hingedly coupled to an auxiliary lever by the second leg, the clamping lever and the auxiliary lever being arranged pivotally on the mount. |
| US09537227B1 |
Female electrical terminal and method of manufacturing the same
A female electrical terminal includes a generally planar base member formed of a first conductive material. The base member includes a connection portion configured to electrically and mechanically contact with a corresponding male electrical terminal. The base member further includes an attachment portion configured to be attached to a wire cable. The female electrical terminal also includes a cover member that is formed of a second conductive material. The cover member longitudinally encircles the connection portion and defines a biasing member depending from the cover member and into a cavity formed by the cover member. The biasing member is configured to bias the male electrical terminal into electrical and frictional contact with the connection portion of the base member of the female electrical terminal. A method of producing such female terminal assemblies wherein the cover members are interconnected by a carrier strip is also provided. |
| US09537225B2 |
Method for use with a reflectarray antenna for wireless telecommunication
A method for use with a reflectarray antenna for wireless telecommunication is described. The method involves providing a reflectarray antenna, and adjusting a phase of a scattered field of the reflectarray antenna for generating different radiation patterns for angular mode-based multiplexing. The reflectarray antenna includes a ground plane, a dielectric substrate attached on the ground plane; and a first antenna patch formed on one side of the dielectric substrate. Further, the reflectarray antenna includes a second antenna patch formed adjacent to the first antenna patch with a separation area therebetween; and a phase adjustment member disposed in the separation area. The phase of the scattered field of the antenna is adjusted by changing a DC voltage of the phase adjustment member. |
| US09537222B2 |
Method for defining the structure of a Ka band antenna
A method is provided for defining an antenna with weak sidelobes having at least two sources, in which the sources are regularly distributed and the reflectors have suitable shapes, obtained by the implementation of a specific algorithm, the reflectors being illuminated by sources composed of a single part. The obtained antenna will offer a gain close to 0 in the direction of the array lobes, so these will be as low as possible. |
| US09537208B2 |
Dual polarization current loop radiator with integrated balun
A dual polarization current loop radiator realized with a via, probe, or exposed coaxial feed using part of a vertical metal structure of the radiator to guide current to a feed point of a horizontal metal plate capacitively coupled to the vertical metal structure is described. The vertical metal structure may be either stamped and attached to the ground plane or it can be formed along with metal backplane structure of the radiator. The top of the vertical metal piece is separated from the horizontal metal plate by a predetermined distance dielectric spacing. The spacing may be realized either a thin dielectric core or a non-conductive adhesive material. |
| US09537203B2 |
Antenna device
There is provided a conductive hollow tube (3) which is brought into tight contact with the top surface of a grounding conductor (1a) at a position where a first end having an opening plane (4a) with an inner diameter matching a diameter of a hole (2a) formed on the grounding conductor (1) overlaps with the hole (2a), and which is bent so that an opening plane (4b) of a second end faces the top surface direction and that an intermediate portion between the first end and the second end is arranged parallel to the grounding conductor (1), and a conductive liquid supplied from the opening plane (4a) of the first end is passed through the conductive hollow tube (3) and discharged to the outside from the opening plane (4b) of the second end. |
| US09537202B2 |
Booster antenna and method for producing same
A silver particle dispersing solution, which contains 50-70% by weight of silver particles having an average particle diameter of 20 nm or less, is applied on a substrate by the flexographic printing, and then, calcined to produce a booster antenna wherein a silver conductive film, which contains 10-50% by volume of a sintered body of the silver particles and which has a volume resistivity of 3-100 μΩ·cm, a surface resistivity of 0.5Ω/□ or less and a thickness of 1-6 μm, is formed on the substrate. Thus, there is provided a booster antenna which has excellent electrical characteristics and flexibility and which can be inexpensively mass-produced. |
| US09537201B2 |
Reconfigurable antenna structure with reconfigurable antennas and applications thereof
A reconfigurable antenna structure includes first and second reconfigurable antennas, a configuration module, and an antenna processing circuit. The first reconfigurable antenna is configured, in response to a first configuration signal, to have a first radiation pattern and to have a first frequency bandwidth and the second reconfigurable antenna is configured, in response to a second configuration signal, to have a second radiation pattern and to have a second frequency bandwidth. The configuration module is configured to generate the first and second configuration signals. The antenna processing circuit is configured to send one or more transmit signals to one or more of the first and second reconfigurable antennas for transmission via one or more of the channels of interest and receive one or more receive signals from the one or more of the first and second reconfigurable antennas. |
| US09537187B2 |
Battery pack having novel cooling structure
Disclosed is a battery pack having a plurality of battery cells or unit modules (‘unit cells’), which can be charged and discharged, mounted in a pack case, wherein the unit cells are stacked in a direction (a Z direction) in which the unit cells are sequentially stacked in parallel to a ground in a state in which a spacing distance for coolant flow is provided between the respective unit cells to constitute a battery module, two or more battery modules are arranged in a horizontal direction (an X direction) on the plane with respect to a coolant introduction direction in which a coolant is introduced through a coolant inlet port in a state in which flow of the coolant between the battery modules is restrained to constitute a battery module group. |
| US09537182B2 |
Process and device for ensuring operational readiness of batteries
The invention claims a process and device for ensuring the operational readiness of a battery in which the battery is first electrically connected with a testing device, and is then tested with the testing device to determine whether the battery is passivated. If the battery is passivated, a procedure for de-passivation of the battery is performed. If the battery is not passivated, a point in time for the next testing of the battery is scheduled. |
| US09537181B2 |
Battery pack
A battery pack is disclosed. The battery pack includes a battery cell, a protection circuit module, and a temperature sensor, which are each held by a case. The case includes a dedicated space for the temperature sensor and a fixing element to fix the temperature sensor in the dedicated space. |
| US09537178B2 |
Electrode assembly and lithium secondary battery including the same
Provided is an electrode assembly, and more particularly, an electrode assembly having a structure wound in a state, in which a plurality of unit cells having a stacking structure is disposed on a long sheet type separation film, and including the unit cells having two or more types of configurations of electrode materials, wherein a separator stacked on the unit cell having a stacking structure has a coating material coated on both sides thereof and the long sheet type separation film has a coating material coated on one side thereof. According to the present invention, an electrode assembly improving processability of preparation of a battery while reducing initial resistance during the preparation of the battery as well as having battery lifetime equivalent to that of a conventional battery and a lithium secondary battery including the electrode assembly may be provided. |
| US09537175B2 |
Material for solid electrolyte
A material capable of producing a sintered body of cubic system garnet type Li7La3Zr2O12 as a solid electrolyte having specified ion conductivity by firing at relatively low temperature in short time. The material for the solid electrolyte is an oxide containing Li, La, Zr and Bi, and the oxide has a cubic system garnet crystal structure where La sites are partly or entirely substituted by Bi. |
| US09537171B2 |
Fuel cell module
A fuel cell module includes a fuel cell stack, a reformer, and an exhaust gas combustor. The fuel cell stack has an oxygen-containing exhaust gas channel and a fuel exhaust gas channel at one end in a stacking direction of fuel cells. An exhaust gas combustor connected to the oxygen-containing exhaust gas channel and the fuel exhaust gas channel are provided at the one end of the fuel cell stack in the stacking direction. A reformer is provided around the exhaust gas combustor. |
| US09537165B2 |
Fuel cell module
A fuel cell module (includes a first area where an exhaust gas combustor and a start-up combustor are provided, an annular second area around the first area and where a reformer and a heat exchanger are provided, and an annular third area around the second area and where an evaporator is provided. Second circumscribed non-uniform-flow suppression plates are provided along the minimum circumscribed circles which contact outer surfaces of heat exchange pipes of the heat exchanger. |
| US09537159B2 |
Fuel cell vehicle
In a fuel cell vehicle of the present invention, a floor panel is constructed to have a center tunnel formed to extend in a front-rear direction of the vehicle. A fluid distributor provided below the floor panel is at least partly located in the center tunnel and is operative to distribute a supply of a fluid in a vehicle width direction. At least one fuel cell stack is provided adjacent to the fluid distributor in the vehicle width direction below the floor panel and is operative to receive the distributive supply of the fluid from the fluid distributor. This fuel cell system has an efficient component layout from the total standpoint of the operability and the space efficiency. |
| US09537158B2 |
Oxidation resistant ferritic stainless steel including copper-containing spinel-structured oxide, method of manufacturing the steel, and fuel cell interconnect using the steel
An oxidation-resistant ferritic stainless steel including a ferritic stainless steel base material, and a Cu-containing spinel-structured oxide. |
| US09537152B2 |
Collector for bipolar lithium ion secondary batteries
A collector for bipolar lithium ion secondary batteries comprises a first conductive layer that is obtained by adding a conductive filler to a base that contains an imide group-containing resin, and a second conductive layer that has a function of blocking lithium ions. The second conductive layer comprises a blocking resin layer that is obtained by adding a conductive filler to a base that contains a resin which contains no imide group, and a metal layer. This collector for bipolar lithium ion secondary batteries is used in such a manner that the first conductive layer is on the positive electrode active material layer side with respect to the second conductive layer. |
| US09537150B2 |
Electrode for secondary battery and production process for the same and secondary battery
To provide an electrode for secondary battery, electrode which can materialize secondary batteries that are adapted into producing high output and additionally whose durability is high.It is characterized in possessing an electrode material that has an active-material powder 11, a conductive material 12 being formed of a carbonaceous material, and being adhered to a surface of said active-material powder 11, and fibrous conductive materials 13 being bonded to said conductive material 12. First of all, it becomes feasible to maintain the electric connection between the active-material powder and the conductive material stably by adhering the conductive material to a surface of the active-material powder. Further, the fibrous conductive materials are bonded to the conductive material that is adhered to a surface of the active-material powder. It is feasible to maintain the electric connection by getting the fibrous conductive materials entangled to each other. That is, it is feasible to keep the electric connection even when strains occur in the electrode material, because the fibrous conductive materials absorb the strains to keep the mutual contacts; even if large strains occur, it is possible to maintain the electric connection, because it is not disconnected compared with that in conventional conductive materials. |
| US09537148B2 |
Positive electrode active substance, positive electrode material, positive electrode, and non-aqueous electrolyte secondary battery
Disclosed is a positive electrode active substance for a non-aqueous electrolyte secondary battery including a composite oxide containing lithium and nickel, in which the positive electrode active substance has a structure of secondary particles formed by aggregation of primary particles. The average particle diameter of the primary particles (D1) is 0.9 μm or less. The average particle diameter of the primary particles (D1) and the standard deviation (σ) of the average particle diameter of the primary particles (D1) meet the relationship of D1/σ2≧24. |
| US09537144B2 |
Single lithium ion conductor as binder in lithium-sulfur or silicon-sulfur battery
A sulfur-containing electrode has a binder comprising a single-lithium ion conductor. The electrode may be used a cathode in a lithium-sulfur or silicon-sulfur battery. |
| US09537138B2 |
Method for preparing a mixture of an electrode active compound powder and an electronic conductor compound powder, resulting mixture, electrode, cell and battery
A method for preparing a mixture of a powder of an electrode active compound and of a powder of an electron conducting compound is disclosed. According to some aspects, the method includes preparing a liquid medium containing the powder of the electrode active compound and the powder of the electron conducting compound, subjecting the liquid medium containing the powder of the electrode active compound and the powder of the electron conducting compound to the action of high energy ultrasonic waves, removing the liquid medium, and collecting the mixture of the powder of the electrode active compound and of the powder of the electron conducting compound. According to some aspects, an electrode including the mixture as an electrochemically active material, a cell including the electrode, and an accumulator or battery including one or more of these cells are disclosed. |
| US09537137B2 |
Cathode active material, cathode active material layer, all solid state battery and producing method for cathode active material
The main object of the present invention is to provide a cathode active material capable of reducing the initial interface resistance against a solid electrolyte material. The present invention solves the above-mentioned problems by providing a cathode active material comprising a cathode active substance exhibiting strong basicity and a coat layer formed so as to cover the surface of the above-mentioned cathode active substance and provided with a polyanionic structural part exhibiting acidity. |
| US09537135B2 |
Terminal of rechargeable battery and method of manufacturing the same
A rechargeable battery including a case; a cap plate on the case; a terminal post protruding from the cap plate; a terminal plate coupled to the terminal post, wherein the terminal plate includes a body having an opening; and a conductor within the opening and coupled to the body, wherein the conductor substantially surrounds a circumference of the terminal post. |
| US09537132B2 |
Battery having a plurality of battery modules arranged in battery strings, and method for operating the battery
A battery includes a plurality of battery modules which are arranged in battery strings and are selectively activated or deactivated by driving. The battery module voltage of a respective battery module contributes to an output voltage of the corresponding battery string of the battery in the activated state. The battery further includes a switching converter topology which is coupled to the battery strings and is configured to selectively generate currents flowing into one or more of the battery strings. |
| US09537130B2 |
Battery module
A battery module including a plurality of battery cells aligned in a direction, each of the battery cells including a cap plate including a terminal portion, and a vent portion to exhaust a gas; a cover covering the vent portions; and a heat-resistance member between the battery cells and the cover, and having an opening formed in a region corresponding to each vent portion. |
| US09537116B2 |
Transparent OLED light extraction
The present disclosure provides novel light emitting devices including AMOLED displays, based on transparent OLED architecture, where a laminated nanostructured light extraction film can produce axial and integrated optical gains as well as improved angular luminance and color. Generally, the transparent AMOLED displays (100) with laminated sub-micron extractors (110a-c) include: (a) an extractor (110a) on a transparent substrate (112a) for light outcoupling on both sides of the transparent device (120); or (b) an extractor (110b) on a reflective film (112b) for providing light outcoupling off the bottom side of the bottom-emitting (BE) AMOLED (120); or (c) an extractor (110c) on a light absorbing film (112c) for providing outcoupling off the bottom side of the BE AMOLED (120) combined with improved ambient contrast. |
| US09537104B2 |
Condensed-cyclic compound and organic light-emitting diode including the condensed-cyclic compound
A condensed-cyclic compound and an organic light-emitting diode including the condensed-cyclic compound. |
| US09537103B1 |
Material for organic electroluminescence device and organic electroluminescence device using the same
The present invention discloses an organic material is represented by the following formula(A), the organic EL device employing the material as light emitting host or dopant of emitting layer, hole blocking layer(HBL), electron blocking layer(EBL), electron transport layer(ETL) and hole transport layer (HTL) can display good performance. wherein A represents a substituted or unsubstituted fused ring hydrocarbon units with two to three rings, m represents an integer of 0 to 10, G, Rs and R1 to R3 are the same definition as described in the present invention. |
| US09537102B2 |
Fused polycyclic heteroaromatic compound, organic thin film including compound and electronic device including organic thin film
A low-molecular-weight fused polycyclic heteroaromatic compound may have a compact planar structure in which seven or more rings are fused together, and thereby exhibits high charge mobility, and furthermore, enables the use of a deposition process or a room-temperature solution process when applied to devices, therefore realizing improved processibility. An organic thin film and electronic device may include the fused polycyclic heteroaromatic compound. |
| US09537098B2 |
Substrate for organic electronic device
The present invention relates to a substrate for an organic electrode device, a manufacturing method thereof, and an organic electronic device. An exemplary substrate of the invention, if an organic light emitting element is formed on an upper part of the substrate, can obtain luminance with high emission and uniformity by efficiently controlling the surface resistance of an electrode even when the device is configured into larger sizes. |
| US09537096B2 |
Method for producing organic electroluminescent element, and organic electroluminescent display device
The present invention provides a method for producing an organic EL element capable of shortening the film formation time while suppressing an increase in the blur width; and an organic EL display device. The method is for producing an organic EL element by scanning vapor deposition, in which one or more vapor deposition sources each are provided with ejection orifices that face the respective openings of a limiting plate, and the ejection orifices facing the same opening are spaced from each other to give a sum of distributions. |
| US09537095B2 |
Tellurium compounds useful for deposition of tellurium containing materials
Precursors for use in depositing tellurium-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM), by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). |
| US09537093B1 |
Memory structure
A memory structure is disclosed. The memory structure comprises a phase change material layer, a first electrode, a second electrode, and conductive spacers. The second electrode and the first electrode are electrically connected to an upper surface and a lower surface of the phase change material layer respectively. The conductive spacers are separated from each other and on side surfaces of the phase change material layer. |
| US09537087B2 |
Magnetoresistance sensor with perpendicular anisotropy
A nanoscale tunnel magneto-resistance (TMR) sensor comprising an in-plane-magnetized reference layer and a free layer comprising interfacial perpendicular anisotropy, wherein the free layer comprises a sensing layer for sensing resistance as a function of applied magnetic field and is tunable to vary the direction of the sensing layer magnetization to be in-plane, canted, or out-of-plane. |
| US09537084B2 |
Piezoelectric sheet, method for manufacturing piezoelectric sheet, and manufacturing apparatus
A specific region of a polylactic acid sheet is heated by a microwave. To allow the polylactic acid sheet to exhibit piezoelectricity in the thickness direction of the polylactic acid sheet, a high voltage is applied to the heated polylactic acid sheet in the thickness direction of the polylactic acid sheet, and thereby the screw axes of at least a part of the polylactic acid molecules are relatively aligned with the thickness direction. Then the polylactic acid sheet is rapidly cooled, and thereby the polylactic acid molecules are immobilized. The same step is executed for other regions of the polylactic acid sheet, and thereby piezoelectricity is imparted to a wide area of the polylactic acid sheet in the thickness direction. The resultant piezoelectric sheet is capable of exhibiting a high piezoelectricity in the thickness direction. |
| US09537083B2 |
Piezoelectric composition and piezoelectric device
Provided is a piezoelectric composition containing a major component that is a perovskite-type oxide which is represented by the general formula ABO3, which contains no Pb, and which has A-sites containing Bi, Na, and K and B-sites containing Ti. The Ti is partly substituted with a transition metal element Me that is at least one selected from the group consisting of Mn, Cr, Fe, and Co. The content of Bi and the transition metal element Me in the perovskite-type oxide, which is the major component, is 6 mole percent to 43 mole percent in terms of Biu1MeO3. |
| US09537078B2 |
Manufacturing process of the thermoelectric conversion element
A manufacturing process of the thermoelectric conversion element is provided, wherein the system using semiconductor process technology to the construction of the thermoelectric conversion element nanoscale thermoelectric effect to increase, and the use of different type and surface state of the sample to increase the thermoelectric conversion element thermoelectric figure of merit. Through the use of a specific thickness of deposition of nanostructures on a nanoscale roughening of the substrate cannot affect the conductivity of thermoelectric materials under, and also can improve the Seebeck coefficient and lower thermal conductivity in order to significantly enhance the thermoelectric figure of merit. |
| US09537075B2 |
Graphite structure, electronic component and method of manufacturing electronic component
The graphite structure includes a plurality of domains of graphite where a layer body of graphene sheets is curved in domelike, wherein the plurality of domains are arranged in plane, and the domains adjacent each other are in contact with each other. |
| US09537066B2 |
Method of manufacturing semiconductor light emitting device, and semiconductor light emitting device
When an uneven pattern is formed on a light extraction surface composed of a semiconductor crystal by wet-etching using an alkaline solution, a plurality of convex portions cannot be formed in a desired arrangement. A method of manufacturing a semiconductor light emitting device includes a light extraction surface composed of a semiconductor crystal, wherein when the uneven pattern is formed by a plurality of convex portions on the light extraction surface, first, a plurality of impressions are formed on the light extraction surface of a semiconductor layer composed of a semiconductor crystal using a processing substrate, and next, by applying wet-etching to the light extraction surface using an alkaline solution, to thereby form convex portions with a portion where each impression is formed as a top portion, and a plurality of facets of the semiconductor crystal as a side face thereof. |
| US09537062B2 |
Solid state light emitter package, a light emission device, a flexible LED strip and a luminaire
A solid state light emitter package (200), a light emitting device, a flexible LED strip and a luminaire are provided. The solid state light emitter package comprising: i) at least three solid state light emitter dies (132, 142, 152) which emit violet/blue light, red light and further light, respectively, ii) a luminescent converter (120) with luminescent material, iii) an optical element (102, 105) for mixing at least portion of the light of the different colors of light and iv) a light exit window (114). The luminescent material at least partially converts the further light towards greenish light having a peak wavelength in the green or cyan spectral range and has a color emission distribution that is wide enough such that the solid state light emitter package is capable of emitting light with a high enough Color Rendering Index. The Color Rendering Index relates to light that has a color point close to the black body line. |
| US09537059B2 |
Light source with quantum dots
The invention provides a luminescent nano particles based luminescent material comprising a matrix of interconnected coated luminescent nano particles, wherein for instance wherein the luminescent nano particles comprise CdSe, wherein the luminescent nano particles comprise a coating of CdS and wherein the matrix comprises a coating comprising ZnS. The luminescent material according may have a quantum efficiency of at least 80% at 25° C., and having a quench of quantum efficiency of at maximum 20% at 100° C. compared to the quantum efficiency at 25° C. |
| US09537054B2 |
Semiconductor heterostructure with stress management
A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure. |
| US09537052B2 |
Coated phosphors and light emitting devices including the same
Provided according to embodiments of the invention are method of coating a phosphor that include contacting the phosphor with a sol comprising at least one of silica, alumina, borate and a precursor thereof, to form a coating on the phosphor; and heating the phosphor. Also provided are phosphors that are coated with alumina, silica and/or borate, and light emitting devices that include such phosphors. |
| US09537050B2 |
Optoelectronic device and method for manufacturing same
The invention relates to an optoelectronic device and to the method for manufacturing same. The optoelectronic device (45), according to the invention includes, in particular: a semiconductor substrate (46) doped with a first type of conductivity; semiconductor contact pads (18) or a semiconductor layer on a surface (16) of the substrate which are/is respectively doped with a second type of conductivity that is the opposite of the first type; and semiconductor elements (24), each semiconductor element being in contact with a contact pad or with the layer. |
| US09537047B2 |
Phosphor in inorganic binder for LED applications
A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an O2 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties. |
| US09537043B2 |
Photoelectric conversion device and manufacturing method thereof
It is an object to reduce the region of a photoelectric conversion element which light does not reach, to suppress deterioration of power generation efficiency, and to suppress manufacturing cost of a voltage conversion element. The present invention relates to a transmissive photoelectric conversion device which includes a photoelectric conversion element including an n-type semiconductor layer, an intrinsic semiconductor layer, and a p-type semiconductor layer; a voltage conversion element which is overlapped with the photoelectric conversion element and which includes an oxide semiconductor film for a channel formation region; and a conductive element which electrically connects the photoelectric conversion element and the voltage conversion element. The photoelectric conversion element is a solar cell. The voltage conversion element includes a transistor having a channel formation region including an oxide semiconductor film. The voltage conversion element is a DC-DC converter. |
| US09537042B2 |
Non-ablative laser patterning
A method for processing a transparent substrate includes generating at least one laser pulse having laser parameters selected for non-ablatively changing a conductive layer disposed on the transparent substrate into a non-conductive feature, and directing the pulse to said conductive layer. A protective film may be affixed to a surface of the transparent substrate and need not be removed during the processing of the substrate. After processing, processed areas can be visually indistinguishable from unprocessed areas. |
| US09537038B2 |
Solar cell made using a barrier layer between P-type and intrinsic layers
A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer. |
| US09537036B2 |
Interconnect for an optoelectronic device
Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first and second ends. A stress relief feature is disposed in the interconnect body. The stress relief feature includes a slot disposed entirely within the interconnect body without extending through to the inner surface, without extending through to the outer surface, without extending through to the first end, and without extending through to the second end of the interconnect body. |
| US09537034B2 |
Process for the production of a solar module
The invention is to facilitate the attachment of an installation system in the production of a solar module. This is achieved via a process which comprises the following steps: a) mutual superposition of the layers that the structure of the solar module requires, where at least one heat-activatable double-sided adhesive tape is placed on the external side of the reverse-side layer and at least one retention plate is placed on said adhesive tape; b) mutual lamination of the layers mutually superposed in step a), at least with exposure to heat. |
| US09537033B2 |
Interface system and method for photovoltaic cladding to standard cladding
The present invention is premised upon a system and method for an improved photovoltaic cladding device array with an interface member (500) for use on a building structure with other non-solar cladding materials (600). The interface member is disposed under a portion of the photovoltaic cladding elements (P) and includes a photovoltaic cladding element nesting portion and a building sheatin nesting portion. |
| US09537030B2 |
Method of fabricating a solar cell with a tunnel dielectric layer
Methods of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described. |
| US09537029B2 |
Semiconductor device with an epitaxial layer and method of fabricating the same
A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction. |
| US09537022B2 |
Wavelength converting material
A wavelength converting material comprising a phosphate compound have a chemical formula of AB1-m-nPO4:Mm, Nn, wherein A comprises an alkali metal element, B comprises an alkaline earth metal element, M is a sensitizer comprising a rare-earth element, and N is an acceptor comprising a rare-earth element, wherein 0 |
| US09537018B2 |
Photovoltaic cell
A photo-voltaic cell has a first and second two-dimensional array of contact points on the first surface, each coupled to a respective one of base and emitter areas in or on the semi-conductor body. Electrically separate first and second conductor structures on the first surface emanate from each contact point, coupled to contact points of the first and second two-dimensional array respectively. The first conductor structure comprises sets of first conductor line branches, the first conductor line branches of each set branching out from a respective one of the contact points of the first two-dimensional array in at least three successive different directions at less than a hundred and eighty degrees to each other. The second conductor structure comprise second conductor line branches in at least three different directions in areas between respective pairs of adjacent non-parallel ones of the first conductor line branches, each second conductor line branch coupled at least to a respective one of the contact points of the second two-dimensional array. |
| US09537014B2 |
Semiconductor device, method for manufacturing semiconductor device, and electronic device
Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate. |
| US09537013B2 |
Display device including tapered substrate
A display device is provided including a first substrate comprising a resin material provided with a plurality region provided with a plurality of pixels including a display device, and a second substrate provided facing the first substrate and installed with the pixel region, wherein an outer periphery side surface of the first substrate having a taper shape and including a barrier layer covering an upper layer, lower layer and the outer periphery side surface of the first substrate. |
| US09537012B2 |
Semiconductor device with oxide semiconductor layer
It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor. |
| US09537008B2 |
Source/drain structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface. |
| US09537007B2 |
FinFET with cut gate stressor
A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region. |
| US09537006B2 |
Circuit element including a layer of a stress-creating material providing a variable stress
An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a first layer of a first stress-creating material, the first stress-creating material providing a stress that is variable in response to a signal acting on the first stress-creating material, wherein the first layer of the first stress-creating material is arranged to provide a first variable stress in the first channel region of the first transistor, the first variable stress being variable in response to a first signal acting on the first stress-creating material. The integrated circuit also includes a second transistor having a second source region, a second drain region, a second channel region, and a second gate electrode. |
| US09537004B2 |
Source/drain formation and structure
A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region. |
| US09537003B2 |
Semiconductor device with charge compensation
A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer. |
| US09537001B2 |
Reduction of degradation due to hot carrier injection
In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer. |
| US09536998B2 |
Semiconductor device and semiconductor device manufacturing method
[Problem] To provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for manufacturing the semiconductor device.[Solution] A semiconductor device (1) includes: an n-type SiC substrate (2) having a gate trench (9) formed therein; a gate insulating film (16), which integrally includes a side-surface insulating film (18) and a bottom-surface insulating film (19); and a gate electrode (15) which is embedded in the gate trench (9), and which selectively has an overlap portion (17) that overlaps, at the upper edge (26), the surface (21) of the SiC substrate (2). In the side-surface insulating film (18), an overhung portion (27) that is selectively thick compared with other portions of the side-surface insulating film (18) is formed such that the overhung portion protrudes, at the upper end edge (26), toward the inside of the gate trench (9). |
| US09536997B1 |
Semiconductor device
A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator. |
| US09536996B2 |
Apparatus and method of manufacturing a support layer
Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer. |
| US09536993B2 |
Thin film transistor and method for manufacturing thin film transistor
A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio. |
| US09536992B2 |
Semiconductor structure including a ferroelectric transistor and method for the formation thereof
A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region. |
| US09536990B2 |
Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask
One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin. |
| US09536989B1 |
Field-effect transistors with source/drain regions of reduced topography
Device structures and fabrication methods for a fin-type field-effect transistor. A first fin and a second fin are formed that are comprised of a semiconductor material that is single crystal. The first fin has a sidewall facing a sidewall of the second fin. A portion of a source/drain region of the first fin is damaged to form a damage region in the portion of the first fin. After the damage region is formed, a section of a semiconductor layer is epitaxially grown from the sidewall of the first fin in the source/drain region. The semiconductor material in the damage region has a level of crystalline disorder that is greater than a level of crystalline disorder of the semiconductor material in a portion of the first fin that is not damaged. |
| US09536986B2 |
Enriched, high mobility strained fin having bottom dielectric isolation
Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions. |
| US09536985B2 |
Epitaxial growth of material on source/drain regions of FinFET structure
A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer. |
| US09536979B2 |
FinFET with reduced capacitance
A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins. |
| US09536978B2 |
Semiconductor device
To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap. |
| US09536976B2 |
Trench schottky rectifier device and method for manufacturing the same
A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as poly-silicon structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode. |
| US09536974B2 |
FET device with tuned gate work function
A method of forming a semiconductor device is provided including forming a gate structure comprising a metal-containing layer over a semiconductor layer and doping the metal-containing layer by tilted ion implantation. |
| US09536972B2 |
Trench power MOSFET and manufacturing method thereof
A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P+/N− or N+/P− junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P+/N− or N+/P− junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced. |
| US09536970B2 |
Three-dimensional semiconductor memory devices and methods of fabricating the same
Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. |
| US09536962B1 |
Source/drain regions for high electron mobility transistors (HEMT) and methods of forming same
An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing. |
| US09536957B2 |
P-type oxide, composition for producing p-type oxide, method for producing p-type oxide, semiconductor element, display element, image display device, and system
To provide is a p-type oxide, including an oxide, wherein the oxide includes: Cu; and an element M, which is selected from p-block elements, and which can be in an equilibrium state, as being present as an ion, wherein the equilibrium state is a state in which there are both a state where all of electrons of p-orbital of an outermost shell are lost, and a state where all of electrons of an outermost shell are lost, and wherein the p-type oxide is amorphous. |
| US09536951B2 |
FinFET transistor comprising portions of SiGe with a crystal orientation [111]
FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate. |
| US09536942B2 |
Semiconductor device having a plurality of electric field relaxation layers and method for manufacturing same
A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region. |
| US09536940B2 |
Interfacial materials for use in semiconductor structures and related methods
A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the high-k dielectric material, and forming a conductive material over the continuous interfacial material. Additional methods and semiconductor structures are also disclosed. |
| US09536938B1 |
Semiconductor device including a resistor metallic layer and method of forming the same
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer. |
| US09536935B2 |
Organic thin film transistor merged with a light emitting diode using an accumulation layer as electrode
A novel light-emitting device includes an organic thin-film structure that is merged with an organic light-emitting diode structure by utilizing a part of the electron accumulation layer in the organic thin-film transistor as a common electrode for each structure. The organic thin-film structure and the organic light-emitting diode structure each include an organic semiconductor that comprises a material in which hole mobility is greater in a bulk region of the material than electron mobility in the bulk region. The advantages of such a light-emitting device include less complex processing and a simpler pixel circuit structure in comparison to separately fabricating OTFT and OLED structures and subsequently interconnecting them to form a pixel. Furthermore, relative to a light-emitting transistor, some embodiments offer the advantage of a broader light emission area more suitable for use in display devices. |
| US09536934B2 |
OLED array substrate
The present invention provides an OLED array substrate, a manufacturing method of the same, a display panel, and a display device, and relates to the field of active matrix organic light-emitting diode (AMOLED) display technology. The present invention can solve the problem that turn-on and turn-off of a switching thin film transistor and grayscale control cannot be performed effectively because the switching thin film transistor and a driving thin film transistor are manufactured as thin film transistors having same performance parameters in an existing OLED array substrate. The OLED array substrate according to the present invention includes a switching thin film transistor and a driving thin film transistor, wherein, an S factor of the switching thin film transistor is less than that of the driving thin film transistor. |
| US09536932B2 |
Method of making a semiconductor lighting emitting device that prevents defect of the mask without increasing steps
As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film. |
| US09536928B2 |
Organic light-emitting display device
An organic light-emitting display device comprising a substrate; an insulating layer disposed on the substrate; a plurality of bottom electrodes arranged on the insulating layer in a matrix pattern defining a plurality of intersecting rows and columns; an organic layer disposed on each of the bottom electrodes; a top electrode disposed on the organic layer; and a plurality of wiring lines adjacent to the first bottom electrode, the wiring lines being formed on the insulating layer placed between the rows of the bottom electrodes. |
| US09536919B2 |
Solid-state imaging device and method of manufacturing the same, and imaging apparatus
A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion. |
| US09536910B2 |
Transistor substrate and display device
In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region. |
| US09536908B2 |
Thin film transistor array panel
A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer. |
| US09536907B2 |
Thin film semiconductor device
According to one embodiment, provided is a thin film transistor with which it is possible to reduce the leakage current and thereby, for a liquid crystal display device, to ensure a good display quality. The thin film transistor includes a semiconductor layer, gate electrodes, first light-blocking electrodes, and second light-blocking electrodes. The first light-blocking electrodes are disposed opposite to the gate electrodes with respect to the semiconductor layer and opposed to channel regions to block light incident into the channel regions. The second light-blocking electrodes are disposed opposite to the semiconductor layer with respect to the gate electrodes, arranged to block light incident into the channel regions, and electrically connected with one of a signal line and a pixel electrode. |
| US09536905B2 |
Active matrix substrate and display device using same
An active matrix substrate (5) includes mounting terminals (DT) for supplying a signal from a driver, draw-out lines (22) connecting the mounting terminals (DT) and gate bus lines (G) or data bus lines (D), first common wires (24) connected in common to the plurality of gate bus lines (G) or the plurality of data bus lines (D), and second switching elements (23) connected between the draw-out lines (22) and the first common wires (24). The draw-out lines (22) include a fan-out portion (FA) that is arranged at an angle with respect to a direction of arrangement of the gate bus lines (G) or the data bus lines (D). At least a portion of the first common wires (24) and at least a portion of the second switching elements (23) are arranged between the fan-out portion (FA) and the mounting terminals (DT). |
| US09536904B2 |
Light-emitting device
A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits. The first circuit has a function of generating a signal including a value of current extracted from the pixel. The second circuit has a function of correcting an image signal by the signal. The pixel includes at least a light-emitting element and first and second transistors. The first transistor has a function of controlling supply of the current to the light-emitting element by the image signal. The second transistor has a function of controlling extraction of the current from the pixel. A semiconductor film of each of the first and second transistors includes a first semiconductor region overlapping with a gate, a second semiconductor region in contact with a source or a drain, and a third semiconductor region between the first and second semiconductor regions. |
| US09536897B2 |
Semiconductor device and method of fabricating the same
A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole. |
| US09536891B2 |
Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage. |
| US09536890B2 |
Semiconductor transistor and flash memory, and manufacturing method thereof
A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties. |
| US09536889B2 |
Split gate memory device, semiconductor device and forming method thereof
A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible. |
| US09536888B2 |
Method to prevent oxide damage and residue contamination for memory device
The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region. |
| US09536887B2 |
Airgap structure and method of manufacturing thereof
A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided. |
| US09536876B2 |
Temperature detector and controlling heat
A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET. |
| US09536875B2 |
Semiconductor device
An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n−-type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n−-type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n−-type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (α) is 50% to 100%. |
| US09536873B2 |
Semiconductor device and method of manufacturing the same
Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode. |
| US09536872B2 |
Shallow trench isolation area having buried capacitor
A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area. |
| US09536869B2 |
Electrostatic discharge protection apparatus and method therefor
An electrostatic discharge protection apparatus comprises a stack arrangement having a first electrostatic discharge protection element and a second electrostatic discharge protection element. The stack arrangement is arranged to provide a bias potential between the first and second electrostatic discharge protection elements. In one embodiment, the bias potential can be achieved by a clamp arrangement coupled across the stack arrangement. |
| US09536865B1 |
Interconnection joints having variable volumes in package structures and methods of formation thereof
An embodiment method includes analyzing warpage characteristics of a first package component and a second package component and forming a plurality of solder paste elements on the first package component. A volume of each of the plurality of solder paste elements is based on the warpage characteristics of the first package component and the second package component. The method further includes aligning a plurality of connectors disposed on the second package component to the plurality of solder paste elements on the first package component and bonding the second package component to the first package component by reflowing the plurality of connectors and the plurality of solder paste elements. |
| US09536863B2 |
Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces
Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package. |
| US09536861B2 |
Semiconductor package including a plurality of stacked chips
A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window. |
| US09536859B2 |
Semiconductor device packaging having plurality of wires bonding to a leadframe
A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and to which the first bonding portion is bonded. The lead includes a second bonding surface and a third bonding surface both facing to the first side in the first direction and forming an angle larger than 180° on the first side in the first direction. The semiconductor device further includes a ball bump extending onto both the second bonding surface and the third bonding surface. The second bonding portion is bonded to the lead via the ball bump. |
| US09536858B2 |
Semiconductor device and manufacturing method thereof
Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer. |
| US09536849B2 |
Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof. |
| US09536847B2 |
Bump pad structure
An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. |
| US09536846B2 |
Semiconductor devices having through electrodes, methods of fabricating the same, electronic systems including the same, and memory cards including same
A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body. |
| US09536843B2 |
Semiconductor package and semiconductor module
According to one embodiment, a semiconductor package includes: a first metal body on which a part of a waveguide structure is formed; a second metal body including a mounting area for a semiconductor device and disposed on the first metal body; a line substrate on which a signal transmission line configured to communicate a waveguide with the semiconductor device mounted on the mounting area is formed; and a lid body disposed at a position facing the first metal body, interposing the second metal body and the line substrate. The lid body is made of resin, on which a structure corresponding to another waveguide structure on an extension of the waveguide structure in the first metal body is formed. The structure includes a metal-coated inner wall surface. |
| US09536839B2 |
Semiconductor device and a method of manufacturing the same
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region. |
| US09536835B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width. |
| US09536832B1 |
Junctionless back end of the line via contact
A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via. |
| US09536828B2 |
Semiconductor device
On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6. |
| US09536827B1 |
Semiconductor structures
The present disclosure relates to a semiconductor structure which includes a first row of diffusion strap having two sections separated by a first distance, a second row of diffusion strap having two sections separated by the first distance, a third row of diffusion strap having two sections separated by the first distance, a fourth row of diffusion strap having two sections separated by the first distance, a first row of conductive strap over the first row of diffusion strap and the second row of diffusion strap, and a second row of conductive strap over the third row of diffusion strap and the fourth row of diffusion strap. The first row of conductive strap has two sections separated by a second distance. The second row of conductive strap has having two sections separated by the second distance, wherein the second distance is greater than the first distance. |
| US09536825B2 |
Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor. The first contact includes a first work function control layer having a first thickness and a first conductive layer formed on the first work function control layer, the second contact includes a second work function control layer having a second thickness different from the first thickness and a second conductive layer formed on the second work function control layer, and the first contact and the second contact have different work functions. |
| US09536824B2 |
Dual sided circuit for surface mounting
A method of forming an integrated circuit, including providing a first substrate layer having a center piece and two side pieces on opposite sides of the center piece, assembling one or more circuit elements on a top side and a bottom side of the center piece of the first substrate layer, preparing two support pieces from a substrate, matching the size of the side pieces, coupling the support pieces to the bottom of the first substrate layer under the side pieces to form a second substrate layer with a void in the center under the center piece of the first substrate layer; and wherein the side pieces and support pieces include via connectors electrically connecting between a bottom side of the second substrate layer and the circuit elements. |
| US09536815B2 |
Semiconductor socket with direct selective metalization
A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members. |
| US09536812B2 |
Cavity package with pre-molded cavity leadframe
A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow. |
| US09536810B1 |
Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes
A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided. |
| US09536809B2 |
Combination of TSV and back side wiring in 3D integration
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip. |
| US09536805B2 |
Power management integrated circuit (PMIC) integration into a processor package
A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package. |
| US09536799B2 |
Hot-melt type curable silicone composition for compression molding or laminating
The present invention relates to a hot-meltable curable silicone composition for compression molding or laminating and a laminate provided with at least one layer comprising the composition, as well as a semiconductor device using these and a method of manufacturing the same. In accordance with the present invention, it is possible to efficiently manufacture a semiconductor device provided with a hemi-spheroidal lens- or dome-shaped seal. In the present invention, it is easy to control the shape of the seal, and the seal does not contain any bubbles. In the present invention, it is also easy to control the thickness of the coating layer of the semiconductor device apart from the seal. |
| US09536798B2 |
Package structure and the method to fabricate thereof
The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the device carrier and a conductive element is disposed on the substrate, wherein the substrate is disposed on the device carrier and the conductive element is located in the recess of the device carrier. The conductive pattern in the substrate is electrically connected to the device carrier and I/O terminals of the first conductive element. The invention also discloses a method for manufacturing a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a portion of the conductive pattern in the substrate can be modified. |
| US09536788B1 |
Complementary SOI lateral bipolar transistors with backplate bias
A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate. |
| US09536787B2 |
Wafer processing method
Disclosed herein is a wafer processing method for dividing a wafer into a plurality of individual devices along a plurality of crossing division lines. The wafer is composed of a substrate and a functional layer formed on the front side of the substrate. The division lines are formed on the front side of the functional layer. A laser beam having a transmission wavelength to the substrate is applied to the wafer from the back side thereof to detect the height of an interface between the functional layer and the substrate in an area corresponding to each division line. The depth of cut by a cutting blade for cutting the substrate is next set according to the height detected above. The back side of the substrate is next cut by the cutting blade according to the depth of cut set above to thereby form a cut groove having a depth not reaching the functional layer with a remaining part of the substrate left between the bottom of the cut groove and the functional layer along each division line, the remaining part having a uniform thickness. Thereafter, the remaining part and the functional layer are cut along each division line to thereby divide the wafer. |
| US09536786B2 |
Wafer processing method using pulsed laser beam to form shield tunnels along division lines of a semiconductor wafer
A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a plurality of regions partitioned by the division lines. The wafer is processed by setting a numerical aperture (NA) of a focusing lens for focusing a pulsed laser beam so that a value obtained by dividing the numerical aperture (NA) by a refractive index (N) of the single crystal substrate falls within the range from 0.05 to 0.2. The pulsed laser beam is applied along the division lines, with a focal point of the pulsed laser beam positioned at a desired position from a back surface of the single crystal substrate, so as to form shield tunnels each composed of a pore and a pore-shielding amorphous portion along the division lines from the focal point positioned inside the single crystal substrate. |
| US09536784B1 |
Integrated circuit (IC) chips with through silicon vias (TSV) and method of forming the IC
A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip. |
| US09536782B2 |
Tungsten film forming method, semiconductor device manufacturing method, and storage medium
A tungsten film forming method includes: supplying a tungsten chloride gas as a source material of tungsten and a reducing gas towards a substrate to be processed under a depressurized atmosphere to cause reaction between the tungsten chloride gas and the reducing gas while heating the substrate to be processed, such that a main tungsten film is directly formed on a surface of the substrate to be processed without forming an initial tungsten film for nucleus generation. |
| US09536781B2 |
Method of making integrated circuit
Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud. |
| US09536775B2 |
Aspect ratio for semiconductor on insulator
A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer. |
| US09536772B2 |
Fin structure of semiconductor device
The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width. |
| US09536768B2 |
Electrostatic carrier for thin substrate handling
Embodiments provided herein generally relate to an electrostatic chuck (ESC). The ESC may comprise a reduced number of stress initiation points, such as holes through the ESC, which may improve the mechanical integrity of the ESC. Electrodes disposed within the ESC may be connected to electrical contacts and a power source via conductive leads, which may be coupled or formed along a peripheral edge of the ESC. Thus, the need for holes formed in the ESC may be reduced or eliminated. In addition, gas channels may be formed on a top surface, a bottom surface, or both. The gas channels may reduce or eliminate the need for a gas channel formed through the ESC and may facilitate heat transfer between a substrate support, the ESC, and a substrate coupled to the ESC. |
| US09536760B2 |
Semiconductor die encapsulation or carrier-mounting method, and corresponding semiconductor die encapsulation or carrier-mounting apparatus
A semiconductor die encapsulation or carrier-mounting method and apparatus for manufacturing a semiconductor product, wherein a first tool part for holding multiple semiconductor dies is provided and the semiconductor dies are placed on the first tool part, one of the first and a second tool part including displaceable insert members applying a pressure by each displaceable insert member on a surface area of the semiconductor die, and the first and second tool parts are brought together to define a space between the first and second tool parts with the semiconductor products being arranged within the space. The pressure applied by the displaceable insert members is monitored and regulated to a predetermined pressure, and subsequently, the first and second tool parts are separated and the processed semiconductor dies removed. |
| US09536759B2 |
Baking apparatus and method
A baking apparatus for baking a wafer is provided. The baking apparatus includes a wafer chuck configured to hold the wafer, and a heating device disposed over the wafer chuck and configured to heat the wafer. The baking apparatus also includes a carrying arm configured to transport the wafer over the wafer chuck. The wafer chuck is in physical contact with the center area of the bottom surface of the wafer when the wafer is held by the wafer chuck. |
| US09536758B1 |
Time-varying frequency powered semiconductor substrate heat source
A semiconductor substrate can include two or more electrodes, located directly or indirectly on the semiconductor substrate, separated from each other and capacitively coupled to the semiconductor substrate. At the two or more electrodes, non-zero frequency time-varying electrical energy can be received. The time-varying electrical energy can be capacitively coupled via the two or more electrodes to trigger a displacement current to activate free carriers confined within the semiconductor substrate to generate heat in the semiconductor substrate. A temperature associated with the semiconductor substrate can be sensed, using a temperature sensor located in association with the semiconductor substrate. A temperature of the semiconductor substrate can be established or adjusted. This can include controlling the electrical energy received at the two or more electrodes using information received from the temperature sensor. |
| US09536757B2 |
Device manufacturing cleaning process using vaporized solvent
A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants. |
| US09536755B2 |
Laminating system
It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used. |
| US09536754B2 |
Method of forming contact structure of gate structure
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench. |
| US09536750B1 |
Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath. |
| US09536748B2 |
Use of ion beam etching to generate gate-all-around structure
Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions. |
| US09536743B2 |
Process for manufacturing a power device with a trench-gate structure and corresponding device
An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate to make a first trench having first side walls and a first bottom; and further etching said semiconductor substrate to make a second trench inside the first trench, realized in a self-aligned way and below this first trench, the first trench and the second trench defining the trench-gate structure with a bird beak-like transition profile suitable for containing a gate region. |
| US09536740B2 |
Increasing the doping efficiency during proton irradiation
A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion. |
| US09536739B2 |
Self-cut sidewall image transfer process
A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask. |
| US09536738B2 |
Vertical gate all around (VGAA) devices and methods of manufacturing the same
Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer. |
| US09536737B2 |
Nanostructure and process of fabricating same
A process of fabricating a nanostructure is disclosed. The process is effected by growing the nanostructure in situ within a trench formed in a substrate and having therein a metal catalyst selected for catalyzing the nanostructure growth, under the conditions in which the growth is guided by the trench. Also disclosed are nanostructure systems comprising a nanostructure, devices containing such systems and uses thereof. |
| US09536734B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber; exhausting the precursor gas in the process chamber through an exhaust system; confining a reaction gas, which differs in chemical structure from the precursor gas, in the process chamber by supplying the reaction gas to the substrate in the process chamber while the exhaust system is closed; and exhausting the reaction gas in the process chamber through the exhaust system while the exhaust system is opened. |
| US09536733B2 |
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. |
| US09536728B2 |
Lamp for rapid thermal processing chamber
A lamp assembly for the lamp assembly adapted for use in a substrate thermal processing chamber to heat the substrate to temperatures up to at least about 1100° C. is disclosed. In one embodiment, the lamp assembly comprises a bulb enclosing at least one radiation generating filament attached to a pair of leads, the bulb having an inner surface and an outer surface, a lamp base configured to receive the pair of leads and at least a portion of the bulb having a surface treatment adapted to reflect light away from the lamp base. In another embodiment, a sleeve covers the lamp base, which has a cross-sectional area less than about 1.2 times the cross-sectional area of the bulb. |
| US09536725B2 |
Means of introducing an analyte into liquid sampling atmospheric pressure glow discharge
A liquid sampling, atmospheric pressure, glow discharge (LS-APGD) device as well as systems that incorporate the device and methods for using the device and systems are described. The LS-APGD includes a hollow capillary for delivering an electrolyte solution to a glow discharge space. The device also includes a counter electrode in the form of a second hollow capillary that can deliver the analyte into the glow discharge space. A voltage across the electrolyte solution and the counter electrode creates the microplasma within the glow discharge space that interacts with the analyte to move it to a higher energy state (vaporization, excitation, and/or ionization of the analyte). |
| US09536719B2 |
Methods for broad-stability mass analysis using a quadrupole mass filter
A method of mass analysis comprises: generating ions from the sample; delivering the ions to a quadrupole; applying a radio frequency voltage, V, to rods of the quadrupole such that the instantaneous electrical potential of each rod is out of phase with each adjacent rod and a non-oscillatory voltage, U, across each pair of adjacent rods such that a subset of the ions having a range of mass-to-charge (m/z) ratios are selectively transmitted through the quadrupole; varying at least one of voltage U and voltage V such that the range of selectively transmitted m/z ratios is caused to vary and varying at least one additional operational parameter; acquiring a data set comprising a series of temporally-resolved images of spatial distribution patterns of transmitted ions at each combination of U, V and the at least one additional operating parameter; and mathematically deconvolving the data set to generate mass spectra. |
| US09536717B2 |
Multiple ion injection in mass spectrometry
This invention relates to mass spectrometry that includes ion trapping in at least one of the stages of mass analysis. In particular, although not exclusively, this invention relates to tandem mass spectrometry where precursor ions and fragment ions are analyzed. A method of mass spectrometry is provided comprising the sequential steps of: accumulating in an ion store a sample of one type of ions to be analyzed; accumulating in the ion store a sample of another type of ions to be analyzed; and mass analyzing the combined samples of the ions; wherein the method comprises accumulating the sample of the one type of ions and/or the sample of another type of ions to achieve a target number of ions based on the results of a previous measurement of the respective type of ions. |
| US09536707B2 |
Etching method of multilayered film
An etching method of etching a multilayered film includes etching a multilayered film by generating plasma within a processing vessel of a plasma processing apparatus. In the etching of the multilayered film, a first processing gas containing a hydrogen gas, a hydrogen bromide gas, a fluorine-containing gas, a hydrocarbon gas, a hydrofluorocarbon gas and a fluorocarbon gas is supplied from a first supply unit configured to supply a gas toward a central region of the processing target object and a second supply unit configured to supply a gas toward outer region than the central region; a second processing gas containing a hydrocarbon gas and a fluorocarbon gas is supplied from either one of the first supply unit and the second supply unit; and the first processing gas and the second processing gas are excited. |
| US09536706B2 |
Self-aligned dynamic pattern generator device and method of fabrication
A dynamic pattern generator (DPG) device and method of making a DPG device are disclosed. The DPG device is used in semiconductor processing tools that require multiple electron-beams, such as direct-write lithography. The device is a self-aligned DPG device that enormously reduces the required tolerances for aligning the various electrode layers, as compared to other design configurations including the non-self-aligned approach and also greatly simplifies the process complexity and cost. A process sequence for both integrated and non-integrated versions of the self-aligned DPG device is described. Additionally, an advanced self-aligned DPG device that eliminates the need for a charge dissipating coating or layer to be used on the device is described. Finally, a fabrication process for the implementation of both integrated and non-integrated versions of the advanced self-aligned DPG device is described. |
| US09536703B2 |
Scanning electron microscope
This scanning electron microscope is provided with: a deceleration means that decelerates an electron beam (5) when the electron beam is passing through an objective lens; and a first detector (8) and a second detector (7) that are disposed between the electron beam and the objective lens and have a sensitive surface having an axially symmetric shape with respect to the optical axis of the electron beam. The first detector is provided at the sample side with respect to the second detector, and exclusively detects the signal electrons having a high energy that have passed through a retarding field energy filter (9A). When the distance between the tip (13) at the sample side of the objective lens and the sensitive surface of the first detector is L1 and the distance between the tip at the sample side of the objective lens and the sensitive surface of the second detector is L2, then L1/L2≦5/9. As a result, when performing low-acceleration observation using a deceleration method by means of a scanning electron microscope, it is possible to detect signal electrons without the effect of shading in a magnification range of a low magnification on the order of hundreds of times to a high magnification of at least 100,000×. Also, it is possible to highly efficiently detect backscattered electrons, of which the amount generated is less than that of secondary electrons. |
| US09536700B2 |
Sample observation device
Provided is a sample observation apparatus including a charged particle optical column that irradiates a sample including an observation target portion that is a concave portion with a charged particle beam at an acceleration voltage, an image generation section that acquires an image including the observation target portion from a signal acquired with irradiation of the charged particle beam, a storage section that stores information representing a relationship between a brightness ratio of a concave portion and its neighboring portion of a reference sample that is irradiated with the charged particle beam at the acceleration voltage and a value that represents a structure of the concave portions of the reference sample in advance, a calculation section that acquires a brightness ratio of the concave portion and its neighboring portion of the image, and a determination section that determines whether or not a defect occurs in the observation target portion based on the information that represents the relationship and the brightness ratio of the image. |
| US09536699B2 |
Charged particle beam system and method of operating a charged particle beam system
The present disclosure relates to a gas field ion source having a gun housing, an electrically conductive gun can base attached to the gun housing, an inner tube mounted to the gun can base, the inner tube being made of an electrically isolating ceramic, an electrically conductive tip attached to the inner tube, an outer tube mounted to the gun can base, the outer tube being made of an electrically isolating ceramic, and an extractor electrode attached to the outer tube. The extractor electrode can have an opening for the passage of ions generated in proximity to the electrically conductive tip. |
| US09536697B2 |
System and method for calibrating charge-regulating module
This invention provides a system and a method for calibrating charge-regulation module in vacuum environment. Means for mounting the charge-regulation module provides motions to the charge-regulation module such that a beam spot, illuminated by the charge-regulation module, on a sample surface can be moved to a pre-determined position which is irradiated by a charged particle beam. |
| US09536693B2 |
Electrical switching apparatus and trip assembly therefor
A trip assembly is for an electrical switching apparatus. The electrical switching apparatus includes a housing, separable contacts enclosed by the housing, and an operating mechanism for opening and closing the separable contacts. The operating mechanism includes a poleshaft and a trip D-shaft. The trip assembly comprises: a yoke assembly comprising a yoke member and a trip pin coupled to the yoke member, the yoke member being structured to be coupled to the poleshaft; and a link assembly comprising a linking member, the linking member being structured to cooperate with each of the trip pin and the trip D-shaft. When the yoke member moves in response to a trip condition, the linking member is structured to transmit movement of the yoke member into movement of the trip D-shaft. |
| US09536692B2 |
Capacitive microelectromechanical switches with dynamic soft-landing
A microelectromechanical system (MEMS)-based electrical switch. The electrical switch includes a moveable electrode, a dielectric layer positioned adjacent the moveable electrode on a first side of the dielectric layer and spaced apart from the moveable electrode when the moveable electrode is in an inactivated position and in contact with the moveable electrode when the moveable electrode is in an activated position, and a substrate attached to the dielectric layer on a second side opposite to the first side, the moveable electrode is configured to brake prior to coming in contact with the dielectric layer when the moveable electrode is switched between the inactivated state and the activated state. |
| US09536689B2 |
Multi-operating switch unit for vehicles
Provided is a multi-operating switch unit for vehicles including: a housing part; a substrate; a switch shaft part; a rotary switch part; a directional switch part; and a push switch part. The directional switch part has: a directional slide part in which the position thereof can vary in the housing part due to a tilting directional operation of the switch shaft part; a directional switch that is arranged on the substrate and is operated due to the positional variation of the directional slide part; and a directional return part that returns the directional slide part and the switch shaft part. The directional return part has a return plunger; a return elastic part; and a return groove. The return plunger can be movable in the axial length direction of the switch shaft part with respect to the housing part, and the return groove is formed in the directional slide part. |
| US09536688B2 |
Press button device and audio equipment having the press button device
A press button device includes a button unit having a main body with a surrounding wall, and an actuating member protruding from an inner side of the main body for actuating a control switch. A flexible connection unit includes a button-coupling portion connected to the surrounding wall in an airtight manner, a fixed portion radially spaced apart from and surrounding the button-coupling portion, and a deformable portion interconnecting the button-coupling and fixed portions. The deformable portion is elastically displaced relative to the fixed portion when the button unit is pressed, and restores the button unit to its original position when the pressing force thereon is removed. |
| US09536684B2 |
Multiple signaling hinged safety switch for mobile protection barriers
A multi-signaling hinged safety switch for mobile protection barriers includes a fixed member designed to be secured to a stationary part of the barrier and having a pair of axial end holes, a movable member designed to be secured to a pivotal part of the barrier and having a pair of substantially transverse arms located outside the fixed member and pivoted to the axial end holes, an electrical detection system within the fixed member switching one or more electric safety circuits of the barrier at a predetermined switching angle. A pair of cylindrical pins extend in cantilever fashion from the arms and are pivotally inserted in the holes, with mutually spaced opposed ends defining a gap with no axial connection member therein. The detection system includes a pair of detectors each interacting with one end of a pin and having a switching angle that are operatively independent of each other. |
| US09536683B2 |
Touch module
A touch module is provided, including a hollow frame, a positioning member, and a touch unit. The positioning member includes a main body, an extending portion, and a U-shape structure. The extending portion is connected to the main body and fixed to the frame. The U-shape structure includes a contact portion and a pair of flexible arms. The flexible arms are connected to the main body, wherein the U-shape structure and the main body form a gap therebetween. The contact portion and the extending portion are disposed on opposite sides of the main body, wherein the contact portion is disposed between the two flexible arms. The touch unit is connected to the main body and forms a protrusion, wherein when a force is applied to the touch unit, the protrusion contacts the contact portion. |
| US09536680B2 |
Electrical switching apparatus, and jumper and associated method therefor
A jumper is for an electrical switching apparatus having a plurality of poles. Each of the poles comprises a terminal. The terminal of a first one of the poles is proximate the terminal of a second one of the poles. The jumper includes a jumper member having an attachment portion and a heat sink portion. The attachment portion is structured to electrically connect the terminal of the first one of the poles to the terminal of the second one of the poles. The heat sink portion includes a plurality of spaced apart heat transfer members that are arranged in a plurality of rows and a plurality of columns. |
| US09536676B2 |
Dye-sensitized solar cell module
A dye-sensitized solar cell module includes a plurality of dye-sensitized solar cells electrically connected in series. The dye-sensitized solar cell includes a first electrode that comprises a transparent substrate, and a transparent conductive film provided on the transparent substrate, a second electrode that faces the first electrode, an oxide semiconductor layer that is provided on the first electrode or the second electrode, and an annular sealing section that joins the first electrode and the second electrode. The transparent substrate is composed of a transparent substrate that is common to the plurality of dye-sensitized solar cells. The second electrodes of two adjoining dye-sensitized solar cells are separated apart from each other. The sealing section includes an annular first sealing section that is provided between the first electrode and the second electrode, and the first sealing sections that are adjoining are integrated together. |
| US09536675B2 |
Polymerization liquid, conductive polymer film obtained from polymerization liquid, and solid electrolytic capacitor
Provided is a polymerization liquid for electropolymerization, which uses a solvent that is mainly composed of water, which is greatly increased in the amount of a monomer contained therein, and which is capable of quickly forming a conductive polymer layer having high conductivity and heat resistance, A polymerization liquid for electropolymerization of the present invention contains: a solvent that is composed of 100-80% by mass of water and 0-20% by mass of an organic solvent; at least one monomer having a pi-conjugated double bond; at least one supporting electrolyte; and at least two nonionic surfactants. The at least two nonionic surfactants are composed of at least one acetylenol surfactant and at least one water-soluble nonionic surfactant other than the acetylenol surfactant. Due to the combination of the two nonionic surfactants, the amount of the monomer emulsified with the solvent can be greatly increased. |
| US09536669B2 |
Laminated ceramic electronic component and manufacturing method therefor
In a method of forming a plating layer for an external terminal electrode by applying, for example, copper plating to an end surface of a component main body with respective ends of internal electrodes exposed, and then applying a heat treatment at a temperature of about 1000° C. or more in order to improve the adhesion strength and moisture resistance of the external terminal electrode, the plating layer may be partially melted to decrease the bonding strength of the plating layer. In the step of applying a heat treatment at a temperature of about 1000° C. or more to a component main body with plating layers formed thereon, the average rate of temperature increase from room temperature to the temperature of about 1000° C. or more is set to about 100° C./minute or more. This average rate of temperature increase maintains a moderate eutectic state in the plating layer and ensures a sufficient bonding strength of the plating layer. |
| US09536666B2 |
Multi-layer ceramic capacitor
A multi-layer ceramic capacitor has a laminate of dielectric layers and internal electrode layers laminated alternately with one another, as well as cover layers formed as the outermost layers at the top and bottom of the laminate in the laminating direction, wherein the dielectric layers are constituted by a sintered compact containing a barium titanate and a silicon compound, and a fresnoite phase having an average grain size of 1 μm or less is present in the dielectric layers. |
| US09536665B2 |
High capacitance single layer capacitor
A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces. |
| US09536662B2 |
Multilayer ceramic capacitor and mounting board for mounting thereof
A multilayer ceramic capacitor includes: a ceramic body including a plurality of dielectric layers and a plurality of first and second internal electrodes stacked in a width direction; a pair of first external electrodes disposed on a mounting surface of the ceramic body to be spaced apart from one another and connected to the plurality of first internal electrodes; a second external electrode disposed between the pair of first external electrodes on the mounting surface of the ceramic body and connected to the plurality of second internal electrodes; and a dummy electrode disposed on a surface of the ceramic body opposing the mounting surface of the ceramic body. |
| US09536659B2 |
Solenoidal magnets composed of multiple axially aligned coils
A magnet assembly has a number of axially-aligned coils, the radial mid-point of each coil being axially-aligned with a portion of a radial extent of an adjacent coil in the assembly. Compression blocks are provided between adjacent coils at circumferential intervals, to retain the coils in fixed relative positions. |
| US09536655B2 |
Wireless power feeding apparatus, vehicle, and method of controlling wireless power feeding system
A power supply device generates power having a prescribed frequency. A primary self-resonant coil transmits the power in a contactless manner to a secondary self-resonant coil by resonating with the secondary self-resonant coil through an electromagnetic field. A power sensor detects reflected power to the power supply device. A communication device receives a power receiving state of a vehicle. An ECU estimates a positional mismatch amount of the secondary self-resonant coil relative to the primary self-resonant coil based on the power receiving state of the vehicle and the reflected power, by using relation obtained in advance between the power receiving state and the reflected power, and the positional mismatch amount. |
| US09536653B2 |
Coil component, powder-compacted inductor and winding method for coil component
A coil component includes an air-core winding wire portion wound by a wire with a plurality of wound layers by alignment winding, a spiral shaped wound portion in which the wire wound in a spiral shape from an inner edge of an end surface toward an outer edge thereof along the end surface while in contact with the end surface on one side in the axis direction of the winding wire portion, a first lead portion extended and extracted outward from a winding first end point of the spiral shaped wound portion, and a second lead portion extended and extracted outward from a winding second end point at the outer circumference of the winding wire portion. |
| US09536650B2 |
Magnetic structure
Magnetic structure production may relate, by way of example but not limitation, to methods, systems, etc. for producing magnetic structures by printing magnetic pixels (aka maxels) into a magnetizable material. Disclosed herein is production of magnetic structures having, for example: maxels of varying shapes, maxels with different positioning, individual maxels with different properties, maxel patterns having different magnetic field characteristics, combinations thereof, and so forth. In certain example implementations disclosed herein, a second maxel may be printed such that it partially overwrites a first maxel to produce a magnetic structure having overlapping maxels. In certain example implementations disclosed herein, a magnetic printer may include a print head comprising multiple parts and having various properties. In certain example implementations disclosed herein, various techniques for using a magnetic printer may be employed to produce different magnetic structures. Furthermore, description of additional magnet-related technology and example implementations thereof is included herein. |
| US09536649B2 |
MRI apparatus, operation method thereof, and quenching prevention device
In order to prevent quenching caused accidentally in a superconducting magnet, an MRI apparatus vibrates the superconducting magnet in order to prevent quenching of the superconducting magnet in a time period for which a predetermined imaging sequence is not executed (step 210). As a specific method, a gradient magnetic field may be generated by a gradient magnetic field coil for an imaging sequence of the MRI apparatus, or a gradient magnetic field may be generated using a gradient magnetic field coil for vibration provided apart from the gradient magnetic field coil for an imaging sequence. In addition, in a period for which the predetermined imaging sequence is not executed, a phantom may be imaged to prevent the quenching of the superconducting magnet. |
| US09536639B2 |
Wire harness
A wire harness is provided in which, by merely overlap wrapping a binding tape member around a group of lead wires, intruding water can be guided to the outside. The wire harness includes a group of lead wires and a binding tape-type protection portion that covers the group of lead wires. The binding tape-type protection portion is formed by overlap wrapping a binding tape member around the group of lead wires, the binding tape member having a tape member body made of a synthetic resin and an adhesive layer formed on one surface of the tape member body. The tape member body has a plurality of water drain holes that are provided so as to penetrate the wall of the tape member body in the width direction, and that are provided in the lengthwise direction. |
| US09536634B2 |
Insulating wire having partial discharge resistance and high partial discharge inception voltage
The present invention relates to an insulating wire and, more particularly, to an insulating wire having partial discharge resistance that exhibits excellent partial discharge resistance and high partial discharge inception voltage and also excellences in the adhesion between the conductor and the insulation layer and the flexibility of the insulation layer, which insulating wire can be prepared by a simple process at a low production cost. |
| US09536633B2 |
Metallic composite and composition thereof
A metallic composite in which a conjugated compound having a molecular weight of 200 or more is adsorbed to a metallic nanostructure having an aspect ratio of 1.5 or more, for example, a metallic composite in which a compound having a group represented by the formula (I) or a repeating unit represented by the formula (II) or both of them is adsorbed to a metallic nanostructure having an aspect ratio of 1.5 or more, is useful for electronic devices such as a light-emitting device, a solar cell and an organic transistor. |
| US09536632B2 |
Mechanically deformed metal particles
A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including deformed conductive particles. |
| US09536623B2 |
Gate drive circuit and shift register
The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide. |
| US09536622B2 |
Programming of antifuse cells
For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated. |
| US09536621B2 |
Nonvolatile memory
A nonvolatile memory includes a memory area including plural first magnetoresistive elements each serving as a memory element, each first magnetoresistive element including a first storage layer and a first reference layer, with a first insulating film therebetween. A fuse circuit storing correction information of the memory area when a defect exists in the memory area, includes plural second magnetoresistive elements and plural fuse elements, the second magnetoresistive elements each serving as an anti-fuse element. Each second magnetoresistive element includes a second storage layer and a second reference layer, with a second insulating film therebetween. The fuse elements each store at least part of the correction information. A redundancy area includes plural third magnetoresistive elements each serving as a redundancy element, each third magnetoresistive element including a third storage layer and a third reference layer, with a third insulating film therebetween. When an external address signal matches the correction information, one third magnetoresistive element is selected. |
| US09536620B2 |
Method and system for improving the radiation tolerance of floating gate memories
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention. |
| US09536617B2 |
Ad hoc digital multi-die polling for peak ICC management
Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation. |
| US09536616B1 |
Non-volatile memory device and method for reading out data
A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent to the second electrode layer, a fourth electrode layer adjacent to the third electrode layer, and a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in a first direction. The device further includes a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body. The circuit providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, the fourth electrode layer with a third potential between the first potential and the second potential and the channel body with a potential rising in the first direction. |
| US09536615B2 |
Nonvolatile semiconductor memory device and control method thereof
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on. |
| US09536611B2 |
3D NAND memory using two separate SSL structures in an interlaced configuration for one bit line
A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition. |
| US09536607B2 |
Preservation circuit and methods to maintain values representing data in one or more layers of memory
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. |
| US09536606B2 |
Seasoning phase change memories
A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory. |
| US09536601B2 |
Threshold voltage grouping of memory cells in same threshold voltage range
A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell. |
| US09536600B2 |
Simultaneous multi-page commands for non-volatile memories
Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the non-volatile memory device. The non-volatile memory device receives a single combined memory command for accessing the non-volatile memory. The non-volatile memory device decodes the row address and the column address for the word-line to be accessed by the single combined memory command. The non-volatile memory device accesses the word-line such that at least a most significant bit (MSB) page and a least significant bit (LSB) page are accessed simultaneously. |
| US09536599B1 |
Optoelectronic device, in particular memory device
A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes. |
| US09536597B2 |
Low-power SRAM cells
The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (VSS, VDD 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30). |
| US09536588B2 |
Reduction of power consumption in memory devices during refresh modes
Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source. |
| US09536586B2 |
Memory device and memory system having the same
A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss. |
| US09536584B2 |
Nonvolatile logic gate device
A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network. |
| US09536582B2 |
Enable/disable of memory chunks during memory access
Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described. |
| US09536577B2 |
Data movement in memory devices
Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed. |
| US09536575B2 |
Power source for memory circuitry
An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source. |
| US09536574B2 |
Memory device and signal processing circuit
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit. |
| US09536570B2 |
Method and system for systematization of production-process video data
There are disclosed a method and a system for systematization of production-process video data. The method is executable at an electronic device. The method comprises: receiving data regarding a correspondence between at least one service zone of a video-data source and at least one workplace for a performance of a production operation; generating a list of identifier types for marking video data to be received form the video-data source; receiving data regarding the production operation from at least one input device for production-operation data, the data regarding production operation being indicative of at least one identifier of at least one workplace for the production operation; based on the data regarding the production operation and the data regarding the correspondence between at least one service zone and the at least one workplace for the production operation, determining a given at least one video-data source of a given service zone in which the production operation is currently being performed; composing a reference that is indicative of a correspondence between video data generated by the given at least one video-data source at least some of the identifiers in the list of identifier types for marking video data to be received form the video-data source, the at least some of the identifiers being specifically selected for a type of the production operation being performed. |
| US09536569B2 |
Content-triggered highlight recording
Systems and methods for selectively recording and bookmarking a portion of broadcast media content include receiving a video stream containing the broadcast media content, determining a video segment of the video stream to be output to a display device, and performing OCR on characters present within the video segment. The systems and methods may further include detecting a trigger event in the OCR of the video segment and creating a digital bookmark corresponding to the detected trigger event. The systems and methods may include generating a recording of a portion of the broadcast media content, whereby the recording begins prior to the trigger event and concludes after the trigger event, and storing the digital bookmark associated with the generated recording. |
| US09536568B2 |
Display system with media processing mechanism and method of operation thereof
A method of operation of a display system includes: receiving a recap request for a source media; generating source content descriptors for the source media with a control unit; extracting a source recap segment from the source media based on correlation of the source content descriptors with a recap theme associated with the recap request; and generating a custom recap with the source recap segment for displaying on a device. |
| US09536566B2 |
Video processing device, video processing method, and recording medium
An imaging device includes a video acquisition unit, a tilt information acquisition unit, and an extraction period determination unit. The video acquisition unit obtains videos. The tilt information acquisition unit obtains information about shifts in posture, which are changes in angles of view or the like, during obtaining of the videos by the video acquisition unit. The extraction period determination unit determines periods to extract in the respective videos in accordance with the information obtained by the tilt information acquisition unit. |
| US09536564B2 |
Role-facilitated editing operations
Some embodiments of the invention provides a media editing application that includes tools to perform a variety of different editing operations based on roles assigned to media content. In some embodiments, the media editing application includes focus-editing tools to emphasize or de-emphasize different sets of clips based on the assigned roles. In some embodiments, the media editing application allows one or more sets of clips to be disabled or enabled during playback based on the assigned roles. |
| US09536559B1 |
Determining a HAMR laser power that reduces adjacent track interference
A laser power applied to a recording head is changed for a plurality of iterations. Each iteration involves, via the recording head at each laser power, writing multiple adjacent tracks to a heat-assisted recording medium and determining a bit error rate for at least one of the adjacent tracks at each laser power. A first laser power is found that achieves a minimum bit error rate of the iterations. An operational value of laser power that is smaller than the first laser power is used during operational recording to reduce adjacent track interference. |
| US09536558B2 |
Erasing recorded data by utilizing read head and write head
Techniques for reducing the time required for erasing specific data recorded on a tape medium. A specific group of records is erased without preliminarily locating the erasure end position. This is carried out by simultaneously utilizing three heads, that is, two read heads and one write head, to detect the erasure end position during data erasure. Various embodiments are applicable to tape media as well as other storage media. Various embodiments are not only applicable as a file system cooperating as a combination of hardware (H/W) and software (S/W), but also applicable in systems, such as databases, that directly use storage without an intermediary file system. |
| US09536552B1 |
Retaining slide-in ramp for hard disk drive
Examples of slide-in ramps for hard-disk drives are disclosed. In one example according to aspects of the present disclosure, a slide-in ramp includes: a ramp body, a head load/unload section connected to the ramp body, and a slot defined in the ramp body. The slot includes a first portion and a second portion. A first upper surface of the ramp body surrounds the first portion of the slot at a top side of the ramp body, and a second upper surface of the ramp body surrounds the second portion of the slot at the top side of the ramp body. The second upper surface is non-coplanar with the first upper surface according to various examples. |
| US09536541B2 |
Content aware audio ducking
A novel audio ducking method that is aware of the loudness levels of the audio content is provided. The method specifies a minimum loudness separation between audio tracks that are designated as masters and audio tracks that are designated as slaves. The method attenuates the volume of the slave tracks in order to provide at least the minimum loudness separation between the slave tracks and the master tracks. The amount of attenuation for a slave is determined based on the loudness levels of the slave and of a master. |
| US09536539B2 |
Nonlinear acoustic echo signal suppression system and method using volterra filter
A nonlinear acoustic echo signal suppression system and method using a Volterra filter is disclosed. The nonlinear acoustic echo signal suppression system includes an acoustic echo signal estimator configured to estimate a nonlinear acoustic echo signal by using a Volterra filter in a frequency filter, and a near-end talker speech signal generator configured to generate a near-end talker speech signal, in which the nonlinear acoustic echo signal is suppressed, by using a gain function based on a statistical model. |
| US09536538B2 |
Method and device for reconstructing a target signal from a noisy input signal
A method for reconstructing at least one target signal comprises determining a first set of feature vectors from the input signal, the first set of feature vectors forming a non-negative input matrix; determining a second set of feature vectors, the second set of feature vectors forming a non-negative noise matrix; decomposing the input matrix into a sum of a first matrix and a second matrix, the first matrix representing a product of a non-negative bases matrix and a non-negative weight matrix, and the second matrix representing a combination of the noise matrix and a noise weight vector; and reconstructing the at least one target signal based on the non-negative bases matrix and the non-negative weight matrix. |
| US09536536B2 |
Adaptive equalization system
An adaptive equalization system that adjusts the spectral shape of a speech signal based on an intelligibility measurement of the speech signal may improve the intelligibility of the output speech signal. Such an adaptive equalization system may include a speech intelligibility measurement module, a spectral shape adjustment module, and an adaptive equalization module. The speech intelligibility measurement module is configured to calculate a speech intelligibility measurement of a speech signal. The spectral shape adjustment module is configured to generate a weighted long-term speech curve based on a first predetermined long-term average speech curve, a second predetermined long-term average speech curve, and the speech intelligibility measurement. The adaptive equalization module is configured to adapt equalization coefficients for the speech signal based on the weighted long-term speech curve. |
| US09536535B2 |
Decoding wireless in-band on-channel signals
Described herein are systems, methods and apparatus for decoding in-band on-channel signals and extracting audio and data signals. Memory requirements are reduced by selectively filtering a bit stream of data in the signal so that services of interest which are encoded therein are processed. A single pool of memory may be shared between physical layer and data link layer processing. Memory in this pool may be allocated dynamically between processing of data at the physical and data link layers. When the available memory is not sufficient to support the required services, the dynamic allocation allows for graceful degradation. |
| US09536530B2 |
Information signal representation using lapped transform
An information signal reconstructor is configured to reconstruct, using aliasing cancellation, an information signal from a lapped transform representation of the information signal including, for each of consecutive, overlapping regions of the information signal, a transform of a windowed version of the respective region, wherein the information signal reconstructor is configured to reconstruct the information signal at a sample rate which changes at a border between a preceding region and a succeeding region of the information signal. |
| US09536526B2 |
Electronic device with speaker identification, method and storage medium
According to one embodiment, an electronic device includes a display controller and circuitry. The display controller displays a first object indicative of a first speaker, a first object indicative of a second speaker different from the first speaker, a second object indicative of a first speech period identified as a speech of the first speaker, and a second object indicative of a second speech period identified as a speech of the second speaker. The circuitry integrates the first speech period and the second speech period into a speech period of a same speaker when a first operation of associating the first object indicative of the first speaker with the first object indicative of the second speaker is operated. |
| US09536523B2 |
Method and system for identification of speech segments
A system for distinguishing and identifying speech segments originating from speech of one or more relevant speakers in a predefined detection area. The system includes an optical system which outputs optical patterns, each representing audio signals as detected by the optical system in the area within a specific time frame; and a computer processor which receives each of the outputted optical patterns and analyses each respective optical pattern to provide information that enables identification of speech segments thereby, by identifying blank spaces in the optical pattern, which define beginning or ending of each respective speech segment. |
| US09536522B1 |
Training a natural language processing model with information retrieval model annotations
Systems and techniques are provided for training a natural language processing model with information retrieval model annotations. A natural language processing model may be trained, through machine learning, using training examples that include part-of-speech tagging and annotations added by an information retrieval model. The natural language processing model may generate part-of-speech, parse-tree, beginning, inside, and outside label, mention chunking, and named-entity recognition predictions with confidence scores for text in the training examples. The information retrieval model annotations and part-of-speech tagging in the training example may be used to determine the accuracy of the predictions, and the natural language processing model may be adjusted. After training, the natural language processing model may be used to make predictions for novel input, such as search queries and potential search results. The search queries and potential search results may have information retrieval model annotations. |
| US09536519B2 |
Method and apparatus to generate a speech recognition library
Methods and apparatus to generate a speech recognition library for use by a speech recognition system are disclosed. An example method comprises identifying a plurality of video segments having closed caption data corresponding to a phrase, the plurality of video segments associated with respective ones of a plurality of audio data segments, computing a plurality of difference metrics between a baseline audio data segment associated with the phrase and respective ones of the plurality of audio data segments, selecting a set of the plurality of audio data segments based on the plurality of difference metrics, identifying a first one of the audio data segments in the set as a representative audio data segment, determining a first phonetic transcription of the representative audio data segment, and adding the first phonetic transcription to a speech recognition library when the first phonetic transcription differs from a second phonetic transcription associated with the phrase in the speech recognition library. |
| US09536513B2 |
Polymer dispersions and sound deadener compositions with emulsion polymer from two-stage preparation
A description is given of an aqueous polymer dispersion comprising a polymer which is obtainable by emulsion polymerization from a monomer mixture comprising as hydrophilic monomers ethoxylated (meth)acrylate monomer, acid monomer, and C1 to C20 hydroxyalkyl(meth)acrylate; and also at least one hydrophobic principal monomer, selected from C1 to C20 alkyl(meth)acrylates and vinylaromatics; and also, optionally, further monomers. This polymer is preparable by at least two-stage emulsion polymerization, where in a first polymerization stage the predominant fraction or the entire amount of the hydrophilic monomers is used, and in a later polymerization stage the predominant fraction or the entire amount of the hydrophobic monomers is used. The polymer dispersion is a suitable binder for aqueous particle dispersions, more particularly of sound deadener compositions, which comprise inorganic and optionally also organic particulate solids. Also described is a method for damping oscillations or vibrations of vehicle components. |
| US09536511B2 |
Ultrasound transducer stack
Certain embodiments provide an ultrasound transducer stack. The ultrasound transducer stack includes a backing layer, an active layer overlying the backing layer, and a matching layer overlying the active layer. The active layer has a surface comprising a plurality of textures. The matching layer has a first thickness region and a second thickness region, wherein the first thickness region has a larger thickness than a thickness of the second thickness region, wherein the first thickness region extends into the plurality of textures and the second thickness region does not extend into the plurality of textures. |
| US09536508B2 |
Accompaniment data generating apparatus
An accompaniment data generating apparatus has a storing portion 15 for storing sets of phrase waveform data each related to a chord identified on the basis of a combination of chord type and chord root, and a CPU 9. The CPU 9 carries out a chord information obtaining process for obtaining chord information by which a chord type and a chord root are identified, and a chord note waveform data generating process for generating phrase waveform data indicative of chord notes of the chord root and the chord type identified by the obtained chord information in accordance with the obtained chord information by use of the sets of phrase waveform data stored in the storing portion 15, and outputting the generated data as accompaniment data. |
| US09536505B1 |
Automatic tuning floating bridge for electric stringed instruments
A method, computer program product, and system for automatically tuning a stringed instrument. An initial height of a first string of an instrument having a plurality of strings and a floating bridge is determined. The height of the plurality of strings is determined using a bridge sensor. The floating bridge is locked. A frequency of the first string is analyzed. In response to determining the frequency of the first string does not match a predetermined frequency, a tuning peg servo motor to adjust a tuning peg, thereby adjusting a string tension of the first string. The one or more bridge servo motors adjusts a spring tension until the spring tension of the one or more springs equals the string tension of the first string. In response to determining the first string is tuned, the floating bridge is unlocked. |
| US09536504B1 |
Automatic tuning floating bridge for electric stringed instruments
A method, computer program product, and system for automatically tuning a stringed instrument. An initial height of a first string of an instrument having a plurality of strings and a floating bridge is determined. The height of the plurality of strings is determined using a bridge sensor. The floating bridge is locked. A frequency of the first string is analyzed. In response to determining the frequency of the first string does not match a predetermined frequency, a tuning peg servo motor to adjust a tuning peg, thereby adjusting a string tension of the first string. The one or more bridge servo motors adjusts a spring tension until the spring tension of the one or more springs equals the string tension of the first string. In response to determining the first string is tuned, the floating bridge is unlocked. |
| US09536503B2 |
Simplified banjo and drum body
The present invention is directed to a Simplified Banjo and Drum Body where the body section of the instruments will consist of an upper compression ring with grooves on the lower surface, a shell having mating compression grooves on the upper edge surface and the banjo head material. An optional tone ring can be added on the inner surface of the shell. The unique feature of this application is that when the compression ring is tightened down on the shell of the instrument the head material is automatically tightened over the instrument. |
| US09536501B2 |
Radiographic-image processing device
A radiographic-image processing device executes image processing on radiographic image data obtained by radiographic imaging of a diagnostic target part as an imaging subject. The device includes a display unit and an enlargement display unit. The display unit displays a radiographic image based on the radiographic image data. The enlargement display unit enlarges a predetermined area including an interest area in the radiographic image and which displays the enlarged predetermined area on the display unit as an initial image which is the first to be displayed after radiographic imaging. |
| US09536494B2 |
Method and apparatus for controlling an output device of a portable electronic device
According to embodiments described in the specification, a method and apparatus are provided for controlling an output device of a portable electronic device comprising a processor, a first motion sensor, a second motion sensor and an output device. The method comprises: receiving at the processor, from the first motion sensor, first motion data representing movement of an external object relative to the portable electronic device; receiving at the processor, from the second motion sensor, second motion data representing movement of the portable electronic device; generating, at the processor, third motion data based on the first and second motion data, the third motion data representing movement of the external object; and, controlling the output device based on the third motion data. |
| US09536492B2 |
Pixel structure, driving method thereof and display device
A pixel structure includes a plurality of data lines, a plurality of scan lines, a plurality of pixels located in an area defined by the data lines crossing the scan lines, a common voltage line connected with the plurality of pixels, a voltage detection unit connected with the data lines and configured to detect voltages on the data lines, and a voltage compensation unit connected with the data lines and configured to compensate voltages on the data lines so that brightness differences between different pixels corresponding to the plurality of scan lines is the lowest, so as to improve or eliminate effectively linear cloudy strips with uniform bright and dark strips and improve the image quality of a displayed image on a liquid crystal display panel. |
| US09536486B2 |
Display driving method with multi-type common voltages and display driving circuit using the same
A display driving method including the following steps is provided. A common voltage is provided to define a reference voltage of a display. The reference voltage is sequentially switched between a plurality of AC voltage swings, between a plurality of DC voltage levels, or between one or more AC voltage swings and one or more DC voltage levels. Each of the plurality of AC voltage swings is provided for a time length of one or more frames. The step of providing the common voltage is repeated one or more times. A display driving circuit using the same is also provided. |
| US09536476B2 |
Gate driver circuit, gate driving method, gate-on-array circuit, display device, and electronic product
The gate driver circuit is connected to a row of pixel unit, each includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module is connected to a first row scanning signal, and the driving module is connected to a second row scanning signal and a driving voltage. The gate driver circuit further includes a row pixel controlling unit configured to provide the first row scanning signal to the compensating module and provide the second row scanning signal and the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor and control the driving module to drive the light-emitting device. |
| US09536469B2 |
Pulse signal combination circuit, display panel and display device
Disclosed is a pulse signal combination circuit for combining N input pulse signals sequentially effective within each display period into an output pulse signal, N being an integer greater than 1, including N output control units and a pulse signal output end. A first control end of an nth output control unit is configured to receive an nth input pulse signal, a second control end thereof is configured to receive an (n+1)th input pulse signal, and an output end thereof is connected to the pulse signal output end. The nth output control unit is configured to, within a time duration of each display period after the nth input pulse signal is effective for the first time and before the (n+1)th input pulse signal is effective for the first time, output the nth input pulse signal to the pulse signal output end, where n is a positive integer less than N. |
| US09536467B2 |
Display device
A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period. |
| US09536459B2 |
Testing device and testing method for display panels
The present invention provides a testing device and a testing method. The testing method comprises: providing a testing device; bonding at least one connecting terminal of the testing device to signal lines of the display panel; and inputting test signals to the signal lines of the display panel through at least one test contact of the testing device. In the present invention, it is not required to arrange shorting bars on the display panel. |
| US09536456B2 |
Image display device
An image display device includes a flexible display unit bendable by an external force between a first state and a second state having different radii of curvature from each other, a pressing member disposed to face the flexible display unit and configured to apply the external force to the flexible display unit in a bending manner, and a drive part configured to pull both ends of the pressing member such that the pressing member is bent. |
| US09536455B2 |
Universal signage frame kit for a point of purchase interface such as a speaker post
A signage frame kit for a point of purchase interface, such as a speaker post, is provided. The signage frame kit includes frame elements that can be retrofitted to an existing point of purchase interface. The frame elements provide not only a means for attaching the frame to the point of purchase interface but also provide a means for receiving signage which can be prominently displayed at the point of purchase interface. |
| US09536452B2 |
System and method to assist users having reduced visual capability utilizing lighting device provided information
A lighting device obtains data related to objects and boundaries in an area in the vicinity of the lighting device, and a user wearable device provides a display (e.g. an augmented reality display based on the data related to the objects and the area boundaries) for a user/wearer. The lighting device includes a mapping sensor that collects data related to the objects and boundaries in the area. The user wearable device includes a camera or other optical sensor and wireless communication capability. The user wearable device is provided with mapping data that is presented on a display of the user wearable device. The communications and display capabilities allow the user wearable device to obtain room mapping information related to area in the vicinity of the lighting device in order to provide navigational assistance to a visually impaired person in the area. |
| US09536451B2 |
Bone conduction tags
Concepts and technologies are disclosed herein for bone conduction tags. According to one aspect of the concepts and technologies disclosed herein, a device can receive, via a transducer, a vibration signal from a body of a user. The vibration signal can be generated in response to the user interacting with a bone conduction tag. For example, the vibration signal can be generated in response to the user moving one or more fingers across the bone conduction tag. The device can analyze the vibration signal to determine an action that is to be performed. The device can perform the action or can instruct a further device to perform the action. |
| US09536448B1 |
Device and method for displaying pediatric medical instructions
A device, method and system for displaying medical information/instructions is presented. The device is comprised generally of an elongated base displaying a plurality of color-coded zones having a plurality of removable instruction portions attached which correspond to each color zone. The instruction portion is generally comprised of fastener and a medical information/instruction display. The medical information/instruction display can be at least one sheet on which the medical information/instructions are printed or an electronic display such as an LCD screen. If printed information/instructions are used, each sheet may be contained within a transparent sleeve to protect the sheet from damage. In use, a child's weight is correlated to a specific color zone on the elongated base and the corresponding instruction portion is removed and fastened to an object near the child to easily enable the user to administer medical treatment to the child. |
| US09536445B2 |
System and method for visually tracking a learned process
The disclosed embodiments include systems and methods for creating trails indicative of a learned process. In one embodiment, a user provides a title and user input for generating the learned processed is received. Nodes are created to represent steps of the learned process in response to the user input. Information for each of the steps is associated with each of the nodes. The nodes are connected in an order for performing the learned process. The connected nodes are visually displayed as a trail for one or more users to perform the learned process. |
| US09536444B2 |
Evaluating expert opinions in a question and answer system
An approach is provided for evaluating subject matter experts (SMEs) in a question and answering (QA) system. In the approach, a number of responses are received at the QA system with each of the responses being a response to a common question and each of the responses being received from a SME. One of the responses is selected with the selected response being from one of the SMEs that is being evaluated. The approach evaluates the selected response by comparing the selected response to the responses received from the other SMEs. Based on the evaluation, the approach updates a SME confidence score that corresponds to the selected SME. |
| US09536442B2 |
Proctor action initiated within an online test taker icon
An aspect of the present invention relates to an online test platform adapted to facilitate the development, delivery, and management of educational tests with interactive participation by students, teachers, proctors, and administrators even when some or all of them are remotely located. The platform may include administrator interfaces, test proctor interfaces, and test taker (e.g. student) interfaces to allow each participant to view, navigate, and interact with aspects of the online test platform that are intended to meet their needs. |
| US09536435B1 |
System and method for optimizing an aircraft trajectory
Systems and methods of the present invention are provided to generate a plurality of flight trajectories that do not conflict with other aircraft in a local area. Interventions by an air traffic control system help prevent collisions between aircraft, but these interventions can also cause an aircraft to substantially deviate from the pilot's intended flight trajectory, which burns fuels, wastes time, etc. Systems and methods of the present invention can assign a standard avoidance interval to other aircraft in the area such that a pilot's aircraft does not receive an intervention by an air traffic control system. Systems and methods of the present invention also generate a plurality of conflict-free flight trajectories such that a pilot or an automated system may select the most desirable flight trajectory for fuel efficiency, speed, and other operational considerations, etc. |
| US09536434B2 |
Aircraft turns for interval management
A method and apparatus of turning an aircraft for interval management. Interval management information identifying a desired spacing between the aircraft and a target aircraft is received. Turn information is determined using a performance gain factor. The turn information identifies a turn point for the aircraft. The performance gain factor identifies a desired portion of achieving the desired spacing due to turning the aircraft at the turn point and a desired portion of achieving the desired spacing due to changing speed of the aircraft. The turn information is used to turn the aircraft at the turn point. |
| US09536430B2 |
Method and device for detecting presence of vehicle in parking space
A method for notifying a user of the status of a parking space. The method comprises transmitting a pulse from a transceiver assigned to a parking space and for each pulse receiving by transceiver a corresponding echo created by said pulse being reflecting back from a object occupying said parking space. The method further comprises measuring corresponding echo time by a processing unit. The method further comprises comparing said corresponding echo time to a predefined range of echo times by a processing unit to determine occupancy of said parking space. The method further comprises using said occupancy of parking space to determine the parking space status by a processing unit, together with information on time of day and parking space permission. The method further comprises notifying a user of said parking space status by visual indication from at least one light emitting diode array. |
| US09536427B2 |
Methods and software for managing vehicle priority in a self-organizing traffic control system
Methods and software for managing vehicle priority proximate to a potential travel-priority conflict zone, such as a roadway intersection, where travel conflicts, such as crossing traffic, can arise. Coordination involves forming an ad-hoc network in a region containing the conflict zone using, for example, vehicle-to-vehicle communications and developing a dynamic traffic control plan based on information about vehicles approaching the conflict zone. Instructions based on the dynamic traffic control plan are communicated to devices aboard vehicles in the ad-hoc network, which display one or more virtual traffic signals to the operators of the vehicles and/or control the vehicles (for example, in autonomous vehicles) in accordance with the dynamic traffic control plan, which may account for a priority level associated with one or more of the vehicles. |
| US09536419B2 |
Security alarm systems and methods
A method for providing notification of an alarm event to a plurality of individuals and communication therebetween having steps that include: receiving an alarm event signal from an alarm system indicating an alarm event; determining a customer associated with the alarm event; determine a plurality of individuals that are to be contacted based upon the customer that has been determined as being associated with the alarm event; selecting a transmission vector having a corresponding transmission identifier; correspondingly associating the selected transmission identifier with the alarm event; sending an alarm event notification to each of the plurality of individuals utilizing the selected transmission vector; and receiving a response to the notification and automatically associating the same; directing each of the plurality of individuals into a virtual chat room corresponding to the alarm event; and facilitating communication between the individuals within the virtual chat room. |
| US09536418B2 |
Industrial field real-time working condition radio alarm system
An industrial field real-time working condition radio alarm system, comprises a transmitting end (11) and a receiving end (12) carried a worker; the transmitting end (11) comprises a detector (101) to detect the current working condition, a transmitting end processor (102) to process an on-off signal sent by the detector (101), and a radio transmitter (103) to transmit an alarm signal to the receiving end (12) under the control of the transmitting end processor (102); the receiving end (12) comprises a radio receiver (105) to receive the alarm signal, a receiving end processor (106) to process the alarm signal sent by the radio receiver (105), and an alarm (107) to send an alarm under the control of the receiving end processor (106); the transmitting end processor (102) is connected to the detector (101) and the radio transmitter (103) respectively; and the receiving end processor (106) is connected to the radio receiver (105) and the alarm (107) respectively. The radio alarm system can send a dangerous working condition alarm to all workers in real time. |
| US09536411B2 |
Biometric monitoring and alerting for a vehicle
A computer storage medium has embodied thereon computer-readable instructions that, when executed, perform a method for identifying biometric markers within a vehicle. The method includes detecting a biometric marker of a driver within the vehicle and displaying data associated with the biometric marker to the driver. |
| US09536408B2 |
Programmable proximity alert system for child in vehicle
A programmable proximity alert system for providing a sensory reminder to a parent when the exit the vicinity of a vehicle possibly containing their child. The programmable proximity alert system comprises a remote receiver adapted to sense the presence of a seat transmitter that it has been paired with and provide plural sensor alerts upon exiting from within a predetermined proximity of the seat transmitter, as well as a coding remote for initiating a bonding request that pairs a remote receiver and a seat transmitter. |
| US09536405B2 |
Unreported event status change determination and alerting
In a method for determining an unreported event status change for an asset, an asset management system receives a position of an asset from a reporting source coupled with the asset. The position is associated with a particular time by the reporting source. The position is compared to a previous position of the asset, the previous position being associated with a previous time that is earlier than the particular time. Based upon the comparing of the position to the previous position, it is determined if an unreported event status change has occurred for the asset. |
| US09536402B2 |
Electronic device that outputs easily recognizable notification sound and recording medium
An electronic device includes a sound output circuit, a notification sound control circuit, and a stop instruction accepting circuit. The sound output circuit outputs a sound. The notification sound control circuit controls a notification sound output by the sound output circuit. The stop instruction accepting circuit accepts a stop instruction of the notification sound. The notification sound control circuit increases frequency of the notification sound in phases as time elapses when the notification sound is output by the sound output circuit, and stops the notification sound output by the sound output circuit when the instruction is accepted by the stop instruction accepting circuit. |
| US09536400B2 |
Alarm sound detection device
By detecting the specific frequency component included in an alarm sound by a frequency analysis and a period analysis, even under a noisy and echo environment, a reliable, almost-no-false-detecting and small-sized abnormality detection device, which can detect the alarm sound, can be realized and then an integrated security system can be realized. |
| US09536397B2 |
Peep device for poker card game machine
A peep device for a poker card game machine includes a box. The box is provided with first and second video cameras, circuit boards having light emitting diodes for fill-in light, and a reflector on top of the box. The reflector has first and second sight holes corresponding in position to the first and second video cameras. When a poker card slowly passes through the first and second sight holes and the first and second video cameras, the suit and the number of the poker card will be displayed slowly for the player to peep at the poker card with excitement. The light emitting diodes illuminate to shoot the poker card clearly. |
| US09536396B2 |
Method and apparatus for providing advice regarding gaming strategies
Methods for providing gaming advice are provided. For example, regarding a blackjack game, one or more first player cards are identified for a first player and one or more second player cards are identified for a second player. The first and second player cards are displayed to the first player. A probability associated with a first one of the plurality of playing options is determined based at least on a set of predetermined statistical blackjack data, the one or more first player cards, and the one or more second player cards. It is then determined, based at least on the determined probability associated with the first playing option, whether to display a first indication corresponding with first advice regarding the first playing option, a second indication corresponding with second advice regarding the first playing option, or a third indication corresponding with third advice regarding the first playing option. |
| US09536394B2 |
Gaming system and method for providing awards
A gaming system including a central server linked to a plurality of gaming machines is provided. The gaming system includes a plurality of progressive awards arranged in a hierarchy. Upon the occurrence of a triggering event or qualifying condition, a bonus game is started. A player can win a next higher progressive award by accumulating award values. If the player's total award value is greater than or equal to a trigger value for a progressive award, the player wins the progressive award. Unless a termination condition occurs, the bonus game continues. The total award value is set to the progressive award value. Alternatively, the progressive award value is added to the player's total award value. The trigger value for a progressive award can be the startup value for that progressive award. |
| US09536390B2 |
Serving patrons in a wagering game environment
Systems and methods for serving patrons in a wagering game environment are described herein. In some embodiments, a method includes receiving patron service information, wherein the patron service information indicates activities of a patron in a casino. The method can also include selecting, based on the patron service information, a service for the patron, wherein the patron has not requested the service. Additionally, the method can include presenting a service order instructing a service attendant to deliver the service. |
| US09536389B2 |
Wager recognition system having ambient light sensor and related method
A gaming table apparatus has a gaming table with a gaming table support surface. A token sensor assembly includes a container having a height and side walls that define an inside and outside perimeter of the container, and a top surface and bottom surface, a translucent cover disposed on the top surface of the side walls, a circuit board secured to the inside perimeter of the container, a plurality of lights disposed on a top side of the circuit board, and a passive ambient light sensor disposed on the top side of the circuit board. The passive ambient light sensor and the translucent cover may operate within predetermined wavelength ranges for receiving and passing light, respectively. A condition of the passive ambient light sensor may not be polled if the plurality of lights is emitting light. |
| US09536388B2 |
Gaming chip having capacitive coupling and related methods
A system is disclosed for identifying and reading gaming tokens. The system includes: a plurality of gaming tokens; a playing surface including a network of conductors disposed to make electrical contact with the conductive rims of the gaming tokens; one or more transceivers disposed under the playing surface and associated with areas where the gaming tokens are placed on the playing surface; and an identification processor in communication with the transceiver to determine the denomination of the token from the data. Each transceiver is configured to transmit an electromagnetic interrogation signal to the conductive layer of a gaming token resting on the playing surface. The grounded circuit, in response to the interrogation signal, responds with data to identify the chip denomination through capacitive coupling between the conductive layer and a transceiver. |
| US09536378B2 |
Systems and methods for recommending games to registered players using distributed storage
While a player is playing one game on a gaming machine, the systems and methods described herein recommend other games to the player based on the player's past gaming history, accessed via player registration, and the player's real time game play. Upon the player selecting a different game, the system may automatically transfers the player's credits between games or gaming machines. Each gaming machine may carry out one or more game. |
| US09536376B2 |
Gaming system and method providing a slot game including a symbol generator modification event
Various embodiments of the present disclosure are directed to a gaming system and method providing a slot game including a symbol generator modification event. In various embodiments, the gaming system is configured to provide a slot game, each play of which employs a subset of a plurality of symbol generators. If a symbol generator modification event occurs in association with a first play that employs a first subset of the symbol generators, the gaming system removes one of the symbol generators from the first subset and adds another one of the plurality of symbol generators to the first subset to form a second subset, and employs the second subset for a second play. The gaming system removes and adds the symbol generators to form the second subset such that the average expected payback percentage of the second play is greater than the average expected payback percentage of the first play. |
| US09536369B2 |
Pharmacy medication verification system
A pharmacy medication verification system is particularly useful for verifying medications to be dispensed to hospital patients while minimizing or eliminating verification by a pharmacist. Typically, a technician or robot picks the medications from storage bins in accordance with a medical prescription or stocking order and uses various sensors to ensure that the correct medication was picked and enters a medication container. The system typically provides correct and incorrect medication indicators as well as correct and incorrect entry indicators. Error reports may be generated when appropriate to communicate any relevant errors to the pharmacist, who can then verify that the correct medications are in the container. In one aspect, the containers are in the form of patient drawers which fit within a cart for delivery to hospital rooms. A containment device may be used to secure the drawer or other container during the verification process. |
| US09536368B2 |
Authentication device
There is disclosed an authentication device (10) for authenticating a luminescent security mark, the device comprising: an illumination source (30) configured to irradiate the security mark with a pulse of excitation radiation so as to cause the security mark to emit luminescent radiation that decays with time; a radiation detector configured to detect the luminescent radiation emitted by the security mark; and an optical waveguide (22) positioned relative to the illumination source (30) and the radiation detector and configured so as to guide by internal reflection both excitation radiation emitted from the illumination source towards the security mark, and luminescent radiation emitted by the security mark towards the radiation detector. |
| US09536367B2 |
Chip handling devices and related methods
Chip sorting devices and methods of ejecting chips from chip wells are disclosed. In some embodiments, chip sorting devices may include at least one chip ejection unit including at least one finger member selectively movable between a first position outside of at least one channel of a chip conveying unit and a second position within the at least one channel. In additional embodiments, a chip sorting device may include a separating wheel comprising a plurality of chip wells, each chip well configured to hold a plurality of chips. In yet additional embodiments, methods of ejecting a chip from a chip well may include urging a selected chip out of the chip well with the at least one finger member and at least one wall segment of a trailing segmented wall of the chip well. |
| US09536366B2 |
Systems and methods for voting
Various embodiments are directed to systems and methods for facilitating voting. A first computer system may select a voter data pack for a first voter. The first computer system may also store an indication of the voter data pack and encrypt the voter data pack. A second computer system may receive the encrypted voter data pack and consolidate the encrypted voter data pack with checkable data. The second computer system may also store an association between the encrypted voter data pack and the checkable data, and encrypt the consolidated encrypted voter data pack and checkable data to generate a consolidated voter authorization for the first voter. |
| US09536363B2 |
Operation communication system
An operation communication system is provided including a server, a mobile device, and a reader device. The server and the reader device communicate data with one another via the mobile device. The mobile device may communicates with the reader device via Bluetooth, for example. The mobile device may communicate with the server via the Internet, for example. Associated methods, devices and apparatuses are also provided. |
| US09536353B2 |
System and method for dynamic in-vehicle virtual reality
A method for in-vehicle dynamic virtual reality, including receiving vehicle data from a portable device, the portable device operably connected for computer communication to an output device, the vehicle data including vehicle dynamics data, and receiving user data from at least one of the portable device or the output device. The method including generating a virtual view based on the vehicle data, the user data and a virtual world model, the virtual world model including one or more components that define the virtual view, wherein generating the virtual view includes augmenting one or more components of the virtual world model according to at least one of the vehicle data or the user data. The method including rendering the virtual view to the output device by controlling the output device to update display of the virtual view according to at least one of the vehicle data or the user data. |
| US09536352B2 |
Imitating physical subjects in photos and videos with augmented reality virtual objects
Technologies for rendering augmented reality virtual objects include an augmented reality device to capture an image and recognize subjects within the image. Subjects may include persons or objects, such as accessories. The augmented reality device determines a context associated with the subjects of the image and selects one or more virtual objects based on the context. The identified context may include an activity or theme associated with the subject or accessories included in the image. Virtual objects may include accessories and clothing for virtual characters. The augmented reality device may select virtual objects that are similar to identified subjects and accessories, or that are associated with an identified activity or theme of the subject. The augmented reality device applies the virtual objects to a virtual character and renders an augmented reality scene based on the captured image that includes the virtual character. Other embodiments are described and claimed. |
| US09536350B2 |
Touch and social cues as inputs into a computer
A system for automatically displaying virtual objects within a mixed reality environment is described. In some embodiments, a see-through head-mounted display device (HMD) identifies a real object (e.g., a person or book) within a field of view of the HMD, detects one or more interactions associated with real object, and automatically displays virtual objects associated with the real object if the one or more interactions involve touching or satisfy one or more social rules stored in a social rules database. The one or more social rules may be used to infer a particular social relationship by considering the distance to another person, the type of environment (e.g., at home or work), and particular physical interactions (e.g., handshakes or hugs). The virtual objects displayed on the HMD may depend on the particular social relationship inferred (e.g., a friend or acquaintance). |
| US09536349B2 |
Compression of a three-dimensional modeled object
It is proposed a computer-implemented method for compressing a three-dimensional modeled object. The method comprises: providing a mesh of the three-dimensional modeled object; parameterizing (u,v) the mesh in a two-dimensional plane, the parameterization of the mesh resulting in a set of vertices having two-dimensional coordinates; providing a grid on the two-dimensional plane; and modifying the two-dimensional coordinates of each vertex by assigning one vertex to one intersection of the grid. Such compression method is lossless, completely reversible, suitable to efficiently reduce the storage size of a CAD file. |
| US09536346B2 |
Medical image display apparatus, medical image display method, and medical image display program
A medical image display apparatus includes: a medical image obtaining section for obtaining a three dimensional medical image of a subject; a display control section for displaying the three dimensional medical image obtained by the medical image obtaining section and an additional information image that represents information added to the three dimensional medical image; and an additional information display command receiving section for receiving a command to display the additional information image along with the three dimensional medical image. The display control section displays the additional information image along with the three dimensional medical image and changing the color of the displayed three dimensional medical image to a color which can be discriminated from the color of the additional information image, when the command to display the additional information image is received. |
| US09536339B1 |
Processing unordered point cloud
Described are methods and systems of processing three-dimensional (“3D”) data by generating an edge map, a depth map, or both. Data points are placed into a bin array based their respective image coordinates. The data points in each bin are processed to determine edge data. An edge map may be generated from this edge data. A bin value may be generated based on the data points in each bin, and a depth map generated using these bin values. The edge data and the edge map may be processed using one or more filter functions. Measurements based on the edge map may be provided at a resolution greater than that available with the depth map. |
| US09536335B2 |
Using frequency decomposition for better color consistency in a synthesized region
A method and apparatus for synthesis of homogeneous regions when infilling a missing region, such as for inpainting removed (or moved) objects from the image is presented. A color interpolation process is performed across opposing boundaries of the missing region for directing the color selection in the patch matching process. Patch matching is performed based on using a detail layer modified by information from color interpolation for each target patch which fills from the extremity of the missing region in towards its center. |
| US09536332B2 |
Display of graphical representations of legends in virtualized data formats
A computer-implemented method for displaying graphical representation of legends in a data visualization engine is provided. The computer-implemented method includes receiving input to configure a plurality of swatches of the legends of graphical charts, the input comprises at least one of a threshold number of swatches, an identification of graphical area for displaying the swatches, and a size or a data of the swatches for display in the graphical charts of the data visualization engine. The computer-implemented method further includes modifying the legend swatches, based on the received input. The computer-implemented method further includes generating a plurality of graphical charts of the data visualization engine for displaying the swatches, based on the modification, wherein the display is generated randomly, based on at least one user preference for displaying the swatches. |
| US09536330B2 |
Program information generation system, method for program information generation, program for program information generation, and program information display system for displaying the execution status of a program
A system according to an embodiment may include: a generation unit that acquires axis information in a coordinate system drawing execution status of a program, and generates an axis object representing the coordinate system based on the axis information; a display event information generation unit that acquires event information related to each of the two or more events and program structure information related to a section of the program generating the two or more events, and generates display event information related to one or more display events representing the two or more events; and an object generation unit that acquires the display event information and display event unit information indicating a display unit of the display event, and generates one or more event objects based on the display event information and the display event unit information. |
| US09536325B2 |
Night mode
A device that provides a map and/or navigation application that displays items on the map and/or navigation instructions differently in different modes. The applications of some embodiments provide a day mode and a night mode. In some embodiments the application uses the day mode as a default and activates the night mode when the time is after sunset at the location of the device. Some embodiments activate night mode when multiple conditions are satisfied (for example, when (1) the time is after sunset at the location of the device and (2) the ambient light level is below a threshold brightness). |
| US09536322B1 |
Implementation of multi-camera tracking applications using rich color transition curve target sequences
A method and apparatus for tracking a location of an object or target in a 3D space. At least one target including unique sub-targets is attached to a vision object in the 3D space. A camera disposed in a 3D space, and coupled to a computing device captures a 2D image of a target. The camera computing device identifies the sub-targets of the target and transfers the sub-target data to a computing device associated with the camera which accesses a data base of target data to identify target an, using sub-target separation distances in the database to determine 3D location and orientation of the target. Another computing device transforms the 3D locations of the detected target in the camera coordinate system into a single 3D coordinate system for the 3D space. The 3D location of targets detected by multiple cameras of different computing devices maybe daisy chained together to convert the target location in the 3D coordinate systems of each computing device into a single 3D coordinate system. |
| US09536321B2 |
Apparatus and method for foreground object segmentation
Embodiments of apparatus and methods for foreground object segmentation are described. In embodiments, an apparatus may include a color modeler to build a color model based at least in part on a boundary of a foreground object in an image frame. The apparatus may further include a segmentation processor to segment the foreground object from a background of the image frame, based at least in part on the color model. Other embodiments may be described and/or claimed. |
| US09536320B1 |
Multiple coordinated detectors for examination and ranging
This invention focuses specifically on the use of epipolar lines and the use of matrix transformations to coordinate cameras. This invention organizes cameras in a manner which is intuitive and effective in perceiving perspectives which are not normally possible; to calculate range precisely; to allow redundancy; to corroborate feature recognition; and to allow perspectives from angles from which no cameras exist. By enabling remote scene reconstruction with a limited set of images, transmission bandwidth is greatly conserved. |
| US09536318B2 |
Image processing device and method for detecting line structures in an image data set
The present invention relates to an image processing device for detecting line structures in an image data set. The device comprises a model definition unit (12) for defining a line model of a line structure to be detected, said line model comprising a number of voxels, a calculation unit (14) for calculating, per voxel of interest of said image data set, several correlation values of a correlation between said line model and an image area around said voxel of interest, said image area comprising a corresponding number of voxels as said line model, wherein for each of a number of different relative orientations of said line model with respect to said image area a respective correlation value is calculated, and a determining unit (16) for determining, per voxel of interest, the maximum correlation value from said calculated correlation values and the corresponding optimal orientation at which said maximum correlation value is obtained. |
| US09536317B2 |
Region segmentation apparatus, recording medium and method
A candidate-region for an object-region is set in an image. In a graph including point-S corresponding the object-region, point-T corresponding to a background-region, a point corresponding to each pixel in the image, S-link connecting each pixel and point-S, T-link connecting each pixel and point-T, and N-link connecting each pair of adjacent pixels, a cost is set for each link, graph-cut is performed. Whether a pixel connected to point-S by a link is present in the graph is judged. If no pixel is present, graph-cut is performed at each stage while costs set for all the S-links connecting each pixel in the candidate-region and point-S are increased stepwise in an increment of a predetermined threshold or less until a pixel connected to point-S by a link appears. Whether each pixel in the image belongs to the object-region or the background-region is determined based on a result of graph-cut performed last. |
| US09536316B2 |
Apparatus and method for lesion segmentation and detection in medical images
An apparatus and method are provided including a first segmenter and a second segmenter. The first segmenter is configured to generate a first segmentation result from a medical image using a first segmentation parameter for a candidate lesion. The second segmenter is configured to determine a target lesion to segment from among the candidate lesion based on the first segmentation result, and generate a second segmentation result using a second segmentation parameter to segment the target lesion. |
| US09536314B2 |
Image reconstruction
A method for reconstructing a three-dimension image includes receiving a plurality of two-dimensional images and projection information of the two-dimensional images, projecting a plurality of rays onto the plurality of two-dimensional images, determining correspondence information between pixels of different ones of the plurality of two-dimensional images, determining a value of each of the pixels, and reconstructing a three-dimension image by integrating the plurality of rays, wherein a position on each ray can be associated to one pixel of the plurality of two-dimensional images. |
| US09536312B2 |
Depth reconstruction using plural depth capture units
A depth construction module is described that receives depth images provided by two or more depth capture units. Each depth capture unit generates its depth image using a structured light technique, that is, by projecting a pattern onto an object and receiving a captured image in response thereto. The depth construction module then identifies at least one deficient portion in at least one depth image that has been received, which may be attributed to overlapping projected patterns that impinge the object. The depth construction module then uses a multi-view reconstruction technique, such as a plane sweeping technique, to supply depth information for the deficient portion. In another mode, a multi-view reconstruction technique can be used to produce an entire depth scene based on captured images received from the depth capture units, that is, without first identifying deficient portions in the depth images. |
| US09536309B2 |
Method, system and apparatus for displaying surgical engagement paths
A method and computing device for displaying surgical path data are provided. The computing device includes an input device, a display, a memory and a processor. The memory stores (i) an image of a volume of patient tissue having an outer surface, and (ii) anatomical data defining anatomical features of the volume. The processor receives an identifier of a target location within the volume; generates a plurality of paths from the outer surface to the target location, each path having a start point located on the outer surface, and an end point at the target location; for each of the plurality of paths, determines a score based on a comparison between the path and the anatomical data; and controls the display to present the outer surface and, at the locations of the start points, indications of the respective scores of the paths corresponding to the start points. |
| US09536308B2 |
Irregular event detection in push notifications
Systems and methods of detecting irregular events include the extraction of values for measure in each of a plurality of notifications. The extracted values are stored in a measures database and a distribution is calculated for the values of each of the measures. The extracted values are compared to the calculated distributions to determine if an irregular event has occurred. An irregularity alert is produced if an irregular event has occurred. |
| US09536307B2 |
Registration of medical images
The invention relates to a method and an image processing device (50) for the registration of two images (I1, I2) that may for example be provided by a CT scanner (10) and/or an MRI scanner (20). According to one embodiment of the invention, the images are first globally registered (GR) with a given registration algorithm using a first parameter vector (p). A user may then select a region of interest ROI, and a plurality of local registrations (LR1, . . . LRs, . . . LRn) are calculated for this ROI using the same registration algorithm but different parameter vectors (p, p, . . . p). The results of the local registrations (LR1, . . . LRs, . . . LRn) are displayed and the user can select the best local registration(s). In a final step, the selected local registration(s) (LRs) and the global registration (GR) may be merged. Additionally or alternatively, a parameter vector for a local registration in the ROI may be determined by an automatic analysis of the ROI. |
| US09536303B2 |
MRI method for assigning individual pixels or voxels tissue-specific PET attenuation values
A magnetic resonance (MR) system (10) generates an attenuation or density map. The system (10) includes a MR scanner (48) defining an examination volume (16) and at least one processor (54). The at least one processor (54) is programmed to control the MR scanner (48) to apply imaging sequences to the examination volume (16). In response to the imaging sequences, MR data sets of the examination volume (16) are received and analyzed to identify different tissue and/or material types found in pixels or voxels of the attenuation or density map. One or more tissue-specific and/or material-specific attenuation or density values are assigned to each pixel or voxel of the attenuation or density map based on the tissue and/or material type(s) identified as being in each pixel or voxel during the analysis of the MR data sets. In one embodiment, the tissue and/or material types are identified on the basis of a time series of MR phase images. |
| US09536301B1 |
System and method for automatically measuring the dimensions of and identifying the type of exterior siding
Methods, systems, and computer readable media are disclosed for determining a pixel-to-length ratio between a number of pixels disposed over a predetermined length of a reference object within an image of a siding sample and the predetermined length of the reference object. A first and second distance between respective first and second pairs of points within the image corresponding to respective first and second length measurements of the siding sample are determined, as well as a first and second number of pixels disposed between the first and second pair of points, respectively. Furthermore, the method, system, and computer readable medium disclose determining the first length measurement based on the pixel-to-length ratio and the first number of pixels, determining the second length measurement based on the pixel-to-length ratio and the second number of pixels, and identifying a siding product associated with the first and second length measurements. |
| US09536298B2 |
Electronic device and method for detecting surface flaw of object
Method for detecting a surface flaw of an object using an electronic device includes requesting a detection device to control a camera unit to capture a current image of a test object placed on the detection device. The current image includes a sidewall image and a reflected image. The method obtains the current image, and detects whether the sidewall image has a surface flaw. When the sidewall image has a surface flaw, a rotation angle of the test object is determined based on the reflected image. The method obtains a standard sidewall image of a standard object stored in a storage device of the electronic device, based on the rotation angle, compares the sidewall image with the standard sidewall image, and determines and displays a position of the surface flaw on a sidewall of the test object based on the comparison. |
| US09536294B2 |
Package essence analysis kit
Systems and methods are disclosed herein to a package essence analysis method comprising receiving, by a computer, first and second video files; indexing, by a computer, the first and second video files; decoding, by a computer, a selected frame of the first video file by referencing a first frame image using the index of the first video file; decoding, by a computer, a selected frame of the second video file by referencing a second frame image using the index of the second video file; and performing, by a computer, video quality analysis by comparing the decoded selected frame of the first video file to the decoded selected frame of the second video file. |
| US09536293B2 |
Image assessment using deep convolutional neural networks
Deep convolutional neural networks receive local and global representations of images as inputs and learn the best representation for a particular feature through multiple convolutional and fully connected layers. A double-column neural network structure receives each of the local and global representations as two heterogeneous parallel inputs to the two columns. After some layers of transformations, the two columns are merged to form the final classifier. Additionally, features may be learned in one of the fully connected layers. The features of the images may be leveraged to boost classification accuracy of other features by learning a regularized double-column neural network. |
| US09536291B2 |
Image processing device, image processing method, and program
To suppress influence of a rounding error and acquire a more highly precise filter processing result, by performing convolution processing in order from a divided filter having a smaller sum of filter coefficient among divided filters, shifting a position of the decimal point of a filter processing result in a fixed-point format to generate an intermediate image, integrating the filter processing result having a larger bit width of a decimal part, and substantially reflecting a processing result of the decimal part. |
| US09536289B2 |
Restoration filter generation device and method, image processing device, imaging device, and non-transitory computer-readable medium
A restoration filter generation device that generates a restoration filter for a restoration process on the basis of a point spread in an optical system, the restoration process being performed on luminance system image data as image data concerning a luminance which is generated on the basis of image data for each color of plural colors acquired by an image pickup device having the optical system, the restoration filter generation device includes a first transfer function acquisition device, a correction information acquisition device, a second transfer function acquisition device, a third transfer function calculation device, and a restoration filter generation device that generates the restoration filter for the restoration process on the basis of the third transfer function calculated by the third transfer function calculation device. |
| US09536287B1 |
Accelerated lens distortion correction with near-continuous warping optimization
A digital image processing technique, such as an image warping operation, is stored in a pre-computed lookup table (LUT) prior to image processing. The LUT represents a pixel-to-pixel mapping of pixel coordinates in a source image to pixel coordinates in a destination image. For vectors containing only inlier pixels, a fast remap table is generated based on the original LUT. Each SIMD vector listed in the fast remap is indexed to the coordinates of one of the source pixels that maps to one of the destination pixels in the vector. Other SIMD vectors that contain at least one outlier pixel are listed in an outlier index. For each vector indexed in the fast remap, linear vector I/O operations are used to load the corresponding source pixels instead of using scatter/gather vector I/O load operations via the LUT. The remaining outlier pixels are processed using scatter/gather I/O operations via the LUT. |
| US09536286B2 |
Magnetic resonance method and tomography system for acquiring image data sets
In a method and a magnetic resonance tomography system, at least two temporally separate original data sets are acquired with one phase measurement value being acquired for each pixel in each original image data set. An optimization technique for the shared calculation of corrected phase values for the pixels in the data sets is implemented in a computer, wherein the corrected phase values of the pixels in a first of the data sets is in each case dependent at least on the phase measured value of the pixel at the same location in a second of the data sets which is recorded beforehand or afterwards, and the corrected phase values of the pixels in the second data set are in each case dependent at least on the phase measured value of the pixel at the same place in the first data set. Corrected image data sets are generated from the corrected phase values. |
| US09536285B2 |
Image processing method, client, and image processing system
An image processing method, a client device, and an image processing system are provided. The method includes: detecting by a client device an image to be processed to obtain image information, and uploading the image information to a server; receiving by the client device at least one case related to the image, the at least one case being obtained by the server according to the image information and sent by the server; and processing the image by the client device according to the at least one case related to the image. The client device includes: a detection module, a receiving module, and a processing module. The system includes the foregoing client device and a server, where the server includes: a receiving module, a selection module, and a sending module. The method not only achieves simple and fast image processing but also improves adjustability during the processing process. |
| US09536282B2 |
Method and apparatus for controlling spatial resolution in a computer system
A computer implemented method of producing output pixels for display in a graphics system, in which the steps include performing rendering operations on one or more pixels, wherein the rendering operations includes the steps of using a POI analyzer to determine one or more of: (a) whether a pixel is a POI or a pixel not of interest (PNOI); (b) selecting different resolutions for a POI and for a PNOI. |
| US09536279B2 |
Method and apparatus for creating a graphics data representation and scaling a graphic represented thereby
A processor is operable to generate a graphics data representation (GDR) for a graphic created at a first resolution and including two or more separated objects. The processor decomposes the objects into contours and determines features and control points along the contours. Additionally, the processor determines constraints for imposition upon the features and control points during scaling, where the constraints include spatial relationships between the control points. The processor stores the constraints, identifications of the features and control points, contour descriptions, and information identifying the first resolution to produce the GDR. Upon acquiring the GDR, a displaying device's processor determines a scaling value based on the first resolution and a second resolution at which the graphic will be displayed, adjusts features and control points of the contours based on the scaling value and the GDR constraints to produce a scaled graphic, and displays the scaled graphic at the second resolution. |
| US09536278B2 |
Graphics processing of a vertex buffer using a relative index buffer
Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index. |
| US09536276B2 |
Method of submitting graphics workloads and handling dropped workloads
Described herein are technologies related to performing of a preemption operation in graphics hardware. Particularly, the preemption operation includes tracking of unreported or dropped workload independent of workloads submitted to the graphics hardware. |
| US09536274B2 |
Drawing processor, drawing processing system, and drawing processing method
Disclosed herein is a drawing processing apparatus including: a drawing library section adapted to transmit a drawing command via a network; and a data transmission management section adapted to transmit reusable data, used to execute the drawing command, via the network at a time different from when the drawing command is transmitted. Also disclosed herein is a drawing processing apparatus including: a data reception management section adapted to receive reusable data, used to execute a drawing command, via a network at a time different from when the drawing command is received; and a drawing library section adapted to set the reusable data, received by the data reception management section, in a graphics processor as a resource and adapted to receive the drawing command via the network and supply the drawing command to the graphics processor. |
| US09536273B2 |
Simulation method for improving picture quality of image display device and a simulation device therefor
The present invention relates to a method for simulating image quality improvement of an image display device, in which the image display device to be tested is made to display an optimized picture quality with a simplified process by applying simplified simulation program and device; and a device therefor. The method for simulating picture quality improvement of an image display device includes the steps of selecting at least one input image data from a list of plurality of test image data by using a file input/output interface unit of a simulation tool, selecting at least one image processing algorithm from a list of a plurality of image processing algorithms by using an image control interface unit, applying the at least one image processing algorithm selected thus to the at least one input image data to convert the at least one input image data by using an algorithm application control unit, comparing and determining at least one output image data converted and forwarded thus to the input image data, and analyzing characteristics of the output image data by using a resultant image analysis and control unit. |
| US09536272B2 |
Information processing apparatus, method and computer-readable medium
In one example embodiment, an information processing apparatus causes a display device to display a first image in a display range. In this embodiment, the first image is from images associated with an observation target object. The images include a first image, a second image, and a third image. In response to a request to change the display range, the information processing apparatus changes the display range at a first speed, and causes the display range to display the second image. In response to a request to terminate the change of the display range, the information processing apparatus changes the display range at a deceleration speed, and causes the display range to display the third image. |
| US09536270B2 |
Reranking of groups when content is uploaded
Systems and methods for the forming of user device groups are presented. In one example, logical relationship information describing logical relationships among a plurality of users is accessed. Potential membership of a first user in a first group of users is determined based on scores generated for each of a plurality of possible groups of users, the scores based on the logical relationship information. Then the first user is added to the first group of users. Content from an electronic device of the first user is received for broadcast to the first group of users. In response to the receiving of content, the scores for each of the plurality of possible groups of users are regenerated based on the content. Then the first user is added to or removed from a second group of users selected from the plurality of possible groups of users based on the regenerated scores. |
| US09536265B2 |
Dynamically activating and deactivating one or more elements of a trading tool
Various embodiments relate to intelligently activating and deactivating a trading tool element of a trading tool to improve a user's confidence in the trading tool. By dynamically activating and deactivating elements on the trading screen, the trading tool effectively increases a user's confidence in placing a trading order, canceling a trade order, or both, for example, by eliminating or reducing undesirable options. Undesirable options might include those that are risky, contrary to a particular trading strategy, would result in a loss of money, and so on. Such an embodiment can improve the overall speed at which a user places or cancels a trade order by, among other things, effectively increasing the user's overall confidence in the trading tool. |
| US09536263B1 |
Debt services candidate locator
Methods and systems are disclosed that identify and locate debt settlement candidates based on credit data associated with the consumer. For example, candidacy may be based on a debt score, generated by an assessment of the consumer's credit data. Credit data may include the consumer's credit score rank, credit score, revolving credit to debit ratio, credit available, delinquent accounts, negative accounts, instances of negative information on their credit report, public record data, average account age, debit, or a combination thereof. |
| US09536262B2 |
Method for verifying authenticity, corresponding server, system and computer program
A method and apparatus are provided for verifying authenticity of a data acquisition peripheral to be used, which has at least one identifier. The method includes: receiving the identifier by means of an authentication server, verifying, by the authentication server, an association of the identifier with a referenced authentic peripheral, delivering a decision of identification; and transmission, by the server, of the decision of identification. |
| US09536261B2 |
Resolving conflicts within saved state data
Disclosed are various embodiments for synchronizing application state information across devices. More specifically, embodiments of the disclosure are related to resolving conflicts between application state information. A synchronization rule, an event name and/or event value are embedded within application state information obtained from devices associated with a user, from which conflicts can be resolved by an application synchronization service. |
| US09536260B2 |
Business communication service
Methods, systems, and computer program products for providing business communication services are disclosed. A computer-implemented method may include detecting a communication initiated by a user, analyzing the detected communication to determine an intended recipient of the communication, determining whether the recipient is responsive to the communication, determining whether to provide visual information associated with the recipient to the user in response to the communication, analyzing one or more prior transactions involving the user and the recipient, identifying a reason that the user initiated the communication with the recipient, determining one or more preferences of the user to generate a personalized user interface comprising the visual information, generating the personalized user interface for the user comprising the visual information, and displaying the personalized user interface to the user in response to the communication, for example, when the recipient is unable to respond to the communication. |
| US09536259B2 |
Entity-based searching with content selection
Systems and methods for entity-based searching with content selection include receiving a search query and determining that the search query corresponds to a search entity. The search entity may be associated with an online action, thereby forming an entity-action pair. Auction parameters that specify the entity-action pair may be used to select third-party content. A visual layout for the third-party content may be generated based on the relationship between a search query and the entity-action pair and used as part of the presentation of the third-party content on a search result screen. |
| US09536251B2 |
Providing advertisements in an augmented reality environment
A computer-implemented method for providing advertisements in an augmented reality environment to a user includes receiving data related to a marker, the marker placed amongst one or more physical objects captured by the video camera. The computer-implemented method also includes retrieving dynamic digital content associated with the marker. Further, the computer-implemented method includes displaying the dynamic digital content amongst the one or more physical objects. Furthermore, the computer-implemented method includes receiving a user interaction with the dynamic digital content. Moreover, the computer-implemented method includes performing an action based on the user interaction. |
| US09536249B2 |
Measuring inline ad performance for third-party ad serving
A method, apparatus, and computer program product for measuring inline internet ad performance for third-party ad serving. The method comprises receiving an original third-party internet ad and recoding the original third-party internet ad for producing a recoded third-party internet ad where the recoded third-party internet ad comprises ad instrumentation code. In real-time, as the internet ad is composited and rendered, the instrumentation code measures the response latency of the server or servers in the third-party network using the ad instrumentation code. In some cases, the original third-party internet ad comprises ad code using a markup language such as HTML language, and/or JavaScript language (e.g. in ad code segments). The recoding comprises recoding an ad code segment of the ad by transforming the ad code segment into a JavaScript literal, which in exemplary embodiments includes emitting a specialized document.write( ) call. Response latency measurements are collected and included in a latency table. |
| US09536248B2 |
Apparatus and method for predicting customer behavior
A predictive model generator that enhances customer experience, reduces the cost of servicing a customer, and prevents customer attrition by predicting the appropriate interaction channel through analysis of different types of data and filtering of irrelevant data. The model includes a customer interaction data engine for transforming data into a proper format for storage, data warehouse for receiving data from a variety of sources, and a predictive engine for analyzing the data and building models. |
| US09536247B2 |
System and method for transmitting/receiving data by using a mobile communication terminal in a Zigbee PAN
A mobile communication terminal, a method for transmitting/receiving data by a mobile communication terminal in a communication system, and a communication system comprising at least one mobile communication terminal are provided. The terminal includes a communication module for performing short-distance communication, a context engine for extracting a tag from contents data, and a controller for generating the contents data, generating profile information using the tag, and controlling the communication module to broadcast the profile data and the contents data. |
| US09536246B2 |
Content recommendation system, content recommendation device, and content recommendation method
A content recommendation system includes: a client terminal operated by a user; and a content recommendation server that recommends content to the terminal through a network and includes a preference discrimination information storage section accumulating and storing preference discrimination information in which information related to evaluation of content input to the terminal by a user and identification information of the user are associated with each other, a content feature information storage section storing content feature information in which data indicating features of content are associated with identification information of content, a preference information creation section creating preference information of each user by integrating evaluation for content with the feature of the content for each user based on the preference discrimination information and the content feature information, and a recommended content list providing section transmitting a list of recommended content, extracted by evaluating the degree of similarity of features with the preference information based on the content feature information, to the terminal. |
| US09536244B1 |
Managed content delivery via web services
Providing access to manage content via a web service is disclosed. A business object that includes a method configured to access a content item comprising a body of managed content is received. The business object is processed to project as a web service a content management functionality associated with the object, including by exposing a method of the business object as a web service operation. |
| US09536232B2 |
Transferring money using email
Method, systems, and apparatus for receiving the email message from a sender device; identifying, using data processing apparatus of a payment service system, a sender email address, a service email address, and one or more recipient email addresses from the email message; identifying, for the sender email address, a sender financial account associated with the payment service system and, for each of the one or more recipient email addresses, a respective recipient financial account associated with the payment service system; identifying a payment amount from a subject or body of the email message; submitting a request to transfer, using the payment service system, the payment amount from the respective sender financial account to the respective recipient financial account. |
| US09536230B2 |
Managing calendaring events
An indication of a meeting being scheduled between a plurality of attendees is received. A first one of the attendees is designated an owner of the meeting. Ownership privileges for the meeting are associated with at least a second one of the meeting attendees. The ownership privileges associated with at least a second one of the meeting attendees are associated based upon, at least in part, a social network defined for the owner of the meeting. |
| US09536229B2 |
Out-of-office notification mechanism for email clients
A method for an out-of-office message notification system to notify at least one sender who has sent an email in a pre-defined time span prior to a start time associated with an out-of-office notification being set by a user is provided. The method may include identifying an unresponded email within a plurality of unresponded emails in an inbox received within the pre-defined time span prior to the start time associated with the out-of-office notification being set by a user. The method may also include sending an out-of-office message notification to the sender associated with the unresponded email. |
| US09536226B2 |
Method and system for leveraging the power of one's social network in an online marketplace
Methods and systems for leveraging one's social network in the context of an opportunities marketplace are described. One aspect of the invention involves integrating social networking features into an online marketplace, or exchange. Accordingly, one aspect of the invention involves facilitating an opportunity search in a manner that provides social networking information with the results of the search. |
| US09536222B2 |
Progress information in a service-oriented architecture
A system may include reception of an instruction to execute a business process from a client application, execution of the business process in a first software work process, and storage, during execution of the business process, of progress information associated with the business process within a memory. A system may further include reception, at a second software work process, of a request from the client application for progress information, retrieval, in the second software work process, of the progress information from the shared memory, reception, at the second software work process, of the progress information from the memory, and provision of the progress information to the client application from the second software work process. |
| US09536216B1 |
Delivery of packages by unmanned aerial vehicles
A package delivery apparatus uses an unmanned aerial vehicle (UAV) to deliver a package containing a product to a delivery destination area. The UAV uses GPS signals to guide it to the delivery destination area and an altimeter to determine its height above the delivery destination area. The UAV then adjusts its height to a preferred drop or release height for that package and product and releases the package. An optional camera allows a human operator to view the delivery destination area. An expandable foam package surrounds the product to protect the product from impact and moisture. The package may be streamlined to reduce air resistance and increase the range of the UAV. The package characteristics, such as its thickness, are determined based one or more of the weight and fragile nature of the product, and the drop height. |
| US09536214B2 |
Weather-driven multi-category infrastructure impact forecasting
A method, system, and computer program product for resource management are described. The method includes selecting trouble regions within the service area, generating clustered regions, and training a trouble forecast model for the trouble regions for each type of damage, the training for each trouble region using training data from every trouble region within the clustered region associated with the trouble region. The method also includes applying the trouble forecast model for each trouble region within the service area for each type of damage, determining a trouble forecast for the service area for each type of damage based on the trouble forecast for each of the trouble regions within the service area, and determining a job forecast for the service area based on the trouble forecast for the service area, wherein the managing resources is based on the job forecast for the service area. |
| US09536213B2 |
System for business suite and network integration
A system includes a suite of business applications and an add-on module coupled to the suite of business applications. The add-on module is configured with Commerce eXtensible Markup Language (cXML) and is operable to enable the suite of business applications to communicate with a network using cXML and a direct web service call to the network. The network is configured to operate using cXML. The direct web service call uses no middleware between the suite of business applications and the network. |
| US09536211B2 |
Service system and service method
A service system includes at least one administration computer having a display device and a user interface for administering machines having components. A respective configuration of components of delivered machines is stored in the administration computer. When a component in one of the machines in the administration computer is exchanged, a spare part that has been installed is stored in the administration computer instead of an original component. A current configuration of the components can be displayed on the display device by operating the user interface, for each of the machines stored in the administration computer. A servicing method is also provided. |
| US09536203B2 |
Method for solving linear programs
The invention provides for a computer-implemented method for solving a linear program (LP), the method comprising the steps of: receiving (100) the linear program; determining (101) a kernel K and determining a kernel matrix G of the kernel K, wherein the kernel matrix is a non-singular submatrix of the original matrix; determining (102) a set of non-basic variable indices and a set of extra constraint indices; computing (103) a primal kernel vector (xK) from the determined kernel; computing (104) a dual kernel vector (yK) from the determined kernel; and evaluating (105) the feasibility of the primal kernel vector and of the dual kernel vector. |
| US09536201B2 |
Identifying associations in data and performing data analysis using a normalized highest mutual information score
A method to identify a relationship between at least pairs of variables in a dataset generates a novel measure of dependence, referred to as a Maximal Information Coefficient (MIC), that captures a wide range of interesting associations (not limited to specific function types such as linear, exponential or periodic, or to all functional relationships), and that gives similar scores to equally noisy relationships of different types. MIC is based on the idea that if a relationship exists between two variables, then a grid can be drawn on a scatterplot of the two variables that partitions the data to encapsulate that relationship. |
| US09536198B2 |
Non-technical loss detection and localization
Embodiments of the present invention provide a system, method, and computer program product to detect and localize non-technical losses in an energy distribution system. A computing device determines the energy consumption of a link and/or node that is associated with an energy grid. The computing device determines the mismatch between the determined energy consumption of the link and/or node and the predicted energy consumption of the link and/or node. The computing device also determines the location of unauthorized energy consumption within the energy that is associated with the mismatch. |
| US09536197B1 |
Methods and systems for processing data streams from data producing objects of vehicle and home entities and generating recommendations and settings
Methods and systems are provided for cloud processing data streamed from a vehicle and a home associated with a user account. One method includes receiving metadata from the vehicle regarding one or more data producing objects of the vehicle and receiving metadata from the home regarding one or more data producing objects of the home. The method further includes accessing action rules for the user account. The action rules require at least one condition that relates to the vehicle and at least one condition that relates to the home. The conditions are determined based on content of the received metadata. The method further includes sending control information to one of the vehicle or the home to recommend or make a setting to one of the data producing objects when one of the action rules are satisfied. In one embodiment, explicit preferences and learned preferences are used to filter or adjust when to send control information or to avoid sending control information. |
| US09536195B2 |
Goal-oriented process generation
A method comprises the steps of receiving a set of process metrics, evaluating the set of received process metrics to determine a set of process classifications, determining a set of process parameters, and generating one or more processes based at least in part on the set of process parameters and the set of process classifications, each of the one or more processes having respective sets of process metrics similar to the set of received process metrics. The receiving, evaluating, determining and generating steps are performed by at least one processing device. |
| US09536192B2 |
Solving vehicle routing problems using evolutionary computing techniques
According to one exemplary embodiment, a method for solving combinatorial optimization problems is provided. The method may include receiving a plurality of problem instance parameters associated with a graph. The method may also include determining a dynamic path change indicator exists. The method may then include initializing the graph based on the determining the dynamic path change indicator does not exist. The method may further include inserting a placeholder node and at least one placeholder node edge based on the determining the dynamic path change indicator exists. The method may also include reinitializing the graphiniti with the inserted place holder node and the at least one placeholder node edge. The method may then include initializing the reinitialized graph. The method may further include executing a hybrid algorithm on the initialized graph or on the reinitialized graph, wherein the hybrid algorithm comprises an ant colony optimization algorithm and a genetic algorithm. |
| US09536191B1 |
Reinforcement learning using confidence scores
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for reinforcement learning using confidence scores. One of the methods includes receiving a current observation; for each of multiple actions: determining a respective value function estimate that is an estimate of a return resulting from the agent performing the action in response to the current observation, determining a respective confidence score that is a measure of confidence that the respective value function estimate for the action is an accurate estimate of the return that will result from the agent performing the action in response to the current observation, adjusting the respective value function estimate for the action using the respective confidence score for the action to determine a respective adjusted value function estimate; and selecting an action to be performed by the agent in response to the current observation using the respective adjusted value function estimates. |
| US09536189B2 |
Phase-coding for coordinate transformation
A method for coordinate transformation in a spiking neural network includes encoding a first positional representation as phase information in the spiking neural network. The method also includes shifting the phase information to modify the first positional representation into a second positional representation. |
| US09536188B2 |
Dual-interface IC card components and method for manufacturing the dual-interface IC card components
Dual-interface Integrated Circuit (IC) card components and methods for manufacturing the dual-interface IC card components are described. In an embodiment, a dual-interface IC card component includes a single-sided contact base structure, which includes a substrate with an electrical contact layer. On the single-sided contact base structure, one or more antenna contact leads are attached to the single-sided contact base structure to form a dual-interface contact structure by applying an adhesive material to partially cover an overlapping area of the at least one antenna contact and the substrate, which is a component of a dual-interface IC card. Other embodiments are also described. |
| US09536185B2 |
Image forming apparatus, method of controlling the same, and storage medium
An image forming apparatus, and a method of controlling it. The apparatus performs, in a case where at least one function out of a plurality of functions of the apparatus ceases to be usable, degeneracy control for operating to provide functions other than the at least one function, and stores information indicating a degeneracy control state is entered. The apparatus controls so as to activate without initialization operation of an image forming mechanism in a case where it is determined that the activation is due to the return from a power saving mode and the information is stored and so as to activate with the initialization operation when the activation is due to a power of the apparatus being turned on. |
| US09536180B2 |
Text recognition based on recognition units
Methods and systems for grapheme splitting of text input for recognition are provided. A method may include receiving a text input in a script and segmenting the text input into one or more graphemes. Each of the one or more graphemes may be split into one or more recognition units based on one or more recognition unit identification criteria associated with the script. Next, a text recognition system may be trained using the recognition units. Text input may be handwritten text input received from a user or a scanned image of text. |
| US09536178B2 |
System and method for structuring a large scale object recognition engine to maximize recognition accuracy and emulate human visual cortex
An object recognition system and method is provided which uses automated algorithmically determined negative training. Negative training with respect to a particular object classifier allows for more streamlined and efficient targeted negative training, enabling time and cost savings while simultaneously improving the accuracy of recognition based on the targeted negative training. According to certain additional aspects, embodiments of the invention relate to a system and method for structuring an object recognition engine to maximize recognition accuracy and emulate human visual cortex. |
| US09536168B2 |
Image capture and identification system and process
A digital image of the object is captured and the object is recognized from plurality of objects in a database. An information address corresponding to the object is then used to access information and initiate communication pertinent to the object. |
| US09536167B2 |
Realogram scene analysis of images: multiples for scene analysis
The techniques include an image recognition system to receive a realogram image including a plurality of organized objects and to detect and identify objects in the realogram image of one or more items on a retail shelf, identify shelf fronts and labels on the shelf fronts, identify empty space under shelves, identify areas where unidentified products may be, and identify areas where products are “out of stock”. |
| US09536161B1 |
Visual and audio recognition for scene change events
Various embodiments describe systems and methods for utilizing a reduced amount of processing capacity for incoming data over time, and, in response to detecting a scene-change-event, notify one or more data processors that a scene-change-event has occurred, and cause incoming data to be processed as new data. In some embodiments, an incoming frame can be compared with a reference frame to determine a difference between the reference frame and the incoming frame. The reference frame may be correlated to a latest scene-change-event. In response to a determination that the difference does not meet one or more difference criteria, a user interface or at least one processor of the computing device can be notified to reduce processing of incoming data over time. In response to a determination that the difference meets the one or more difference criteria, the user interface or the at least one processor can be notified that a scene-change-event has occurred. Incoming data to the computing device is then treated as new and processed as those under an active condition. The current incoming frame can be selected as a new reference frame for detecting next scene-change-event. |
| US09536156B2 |
Arrangement and method for recognizing road signs
Various embodiment include a system and a method for recognizing road signs. An image of a road sign may be captured by least one image sensor. A vehicle computer may receive the image data representing one or more road signs along a route and display one or more images of the road sign based on the image data. The display may be capable of presenting one or more status of the road sign based on one or more travel states for the vehicle. These travel states may include at least one of an amount of elapsed travel time, distance travelled, or speed. |
| US09536150B2 |
Video camera with capture modes
Embodiments provide a video camera that can be configured to allow tagging of recorded video and/or capture of video segments or sequences of images in response to user actuation of a camera control identifying an event of interest. For example, a user may press a button on the camera when an event of interest occurs, and in response the camera may tag a captured video file at a timestamp corresponding to the event. In another example, the user may initiate capture of video segments or sequences of images at an occurrence of an event of interest by pressing a button. The camera may include an image data buffer that may enable capture of video segments and/or sequences of images occurring before the user initiates capture of the event. User interfaces may enable the user to quickly review the captured video or sequences of images of the events of interest. |
| US09536146B2 |
Determine spatiotemporal causal interactions in data
Techniques for detecting outliers in data and determining spatiotemporal causal interactions in the data are discussed. A process collects global positioning system (GPS) points in logs and identifies geographical locations to represent the area where the service vehicles travelled with a passenger. The process models traffic patterns by: partitioning the area into regions, segmenting the GPS points from the logs into time bins, and identifying the GPS points associated with transporting the passenger. The process projects the identified GPS points onto the regions to construct links connecting GPS points located in two or more regions. Furthermore, the process builds a three-dimensional unit cube to represent features of each link. The points farthest away from a center of data cluster are detected as outliers, which represent abnormal traffic patterns. The process constructs outlier trees to evaluate relationships of the outliers and determines the spatiotemporal causal interactions in the data. |
| US09536145B2 |
System and method for selecting features for identifying human activities in a human-computer interacting environment
A System and method for identifying one or more human activities in a human-computer interacting environment. Skeleton points associated with a human are received. A data variation factor for the skeleton points is calculated, and a set of skeleton points is selected based on the data variation factor. One or more features are defined from the set of skeleton points by identifying a variance in coordinates of the set of skeleton points by using one or more statistical parameters. The one or more features are used to identify the one or more human activities. |
| US09536144B2 |
Automatic image classification
A method, system and product for image classification. The method comprising obtaining a set of encoding functions and signature values which corresponds to a set of class images, wherein each pair of an encoding function and a signature value corresponds to a class image of the set of class images, wherein the signature value is a value produced by applying the encoding function on the class image; obtaining an image to be classified to a class associated with a class image of the set of class images; with respect to each class image of the set of class images: determining a transformation from the image to the class image; and applying the encoding function using the transformation on the image to produce a value; and automatically determining a class to which the image is classified based on the values and the signature values. |
| US09536142B2 |
Automated user information provision using images
A method for automated user information provision using an image includes requesting at least one user information image in response to receiving a user information form from a requesting entity over a network. The at least one user information image is received from a camera. The at least one user information image is analyzed using a processor to determine that the at least one user information image includes requested user information in at least one request section of the user information form. The requested user information is automatically provided into the at least one request section of the user information form. The user information form including the requested user information in the at least one request section is displayed on a display. The user information form may then be sent over the network to provide the requested user information to the requesting entity. |
| US09536140B2 |
Information processing apparatus and computer readable medium
An information processing apparatus includes: an image pickup unit, a recognition unit and an execution unit. The image pickup unit photographs a recording medium to generate a picked-up image. The recognition unit recognizes a handwritten mark in the picked-up image generated by the image pickup unit. The execution unit performs a predetermined process according to the handwritten mark recognized by the recognized unit. |
| US09536139B2 |
Systems and methods for assessing standards for mobile image quality
Methods are provided for defining and determining a formal and verifiable mobile document image quality and usability (MDIQU) standard, or Standard for short. The Standard ensures that a mobile image can be used in an appropriate mobile document processing application, for example an application for mobile check deposit. In order to quantify the usability, the Standard establishes 5 quality and usability grades. A mobile image is first tested to determine if the quality is sufficient to obtain content from the image by performing multiple different image quality assessment tests. If the image quality is sufficient, one or more document usability computations are made to determine if the document or content in the image is usable by a particular application. A ranking is then assigned to the image based on the results of the tests which is indicative of the quality and usability of the image. |
| US09536137B2 |
Object detection apparatus
In an object detection apparatus 1, a window definer 11 defines a window relative to the location of a pixel in an input image 20. A classification value calculator 13 calculates a classification value indicative of the likelihood that a detection target is present in the window image contained in the window based on the feature data of the detection target. A classification image generator 14 arranges the classification value calculated from the window image according to the pixel location to generate a classification image. An integrator 15 integrates the classification image and a past classification image 42 generated from a past input image input prior to the input image 20 to generate an integrated image 45. A determiner 16 determines whether the detection target is present in the input image 20 based on the integrated image 45. |
| US09536135B2 |
Dynamic hand gesture recognition using depth data
The subject disclosure is directed towards a technology by which dynamic hand gestures are recognized by processing depth data, including in real-time. In an offline stage, a classifier is trained from feature values extracted from frames of depth data that are associated with intended hand gestures. In an online stage, a feature extractor extracts feature values from sensed depth data that corresponds to an unknown hand gesture. These feature values are input to the classifier as a feature vector to receive a recognition result of the unknown hand gesture. The technology may be used in real time, and may be robust to variations in lighting, hand orientation, and the user's gesturing speed and style. |
| US09536133B2 |
Display apparatus and control method for adjusting the eyes of a photographed user
A display apparatus is provided. The display apparatus includes a photographing unit configured to photograph the shape of a face; a detector is configured to detect a direction and angle of the face shape; a transformer is configured to mix the photographed face shape and a 3D face model and to transform the mixed face shape by using the detected direction and angle of the face shape; and an output interface is configured to output the transformed face shape. |
| US09536131B1 |
Fingerprint recognition methods and electronic device
An electronic device and method are provided. The fingerprint recognition method includes: obtaining a verification fingerprint image; transmitting the verification fingerprint image to the second processing unit; generating verification fingerprint data according to the verification fingerprint image by the second processing unit; transmitting the verification fingerprint data to the first processing unit by the second processing unit; comparing the verification fingerprint data with a plurality of registered fingerprint datasets to generate matching information by the first processing unit; transmitting the matching information from the first processing unit to the second processing unit; and verifying the verification fingerprint data according to the matching information by the second processing unit. |
| US09536130B2 |
Electronic device with a fingerprint reader and method for operating the same
A method for operating an electronic device is provided, in which the device detects contact with a user's finger, scans its fingerprint and sets the orientation of the electronic device based on the fingerprint (e.g., whether is from the user's left hand or right hand) and on an angle of the fingerprint with respect to the device. This allows the electronic device to determine its orientation with respect to the user rather than with respect to the environment. |
| US09536123B2 |
Data application method and system of RFID tags
A data application method and system of radio-frequency identification (RFID) tags are provided. The method includes: when a first-type RFID tag is within a readable range of a first-type RFID reader, acquiring, by the first-type RFID reader, data of the first-type RFID tag; obtaining, by an RFID emulator, the data of the first-type RFID tag, converting the data of the first-type RFID tag to data of a second-type RFID tag according to a predetermined data conversion protocol, and providing the data of the second-type RFID tag for a second-type RFID reader; and forming, by the second-type RFID reader, a second-type RFID signal according to the data of the second-type RFID tag and sending the second-type RFID signal. The data application method and system expand applications of RFID tags. |
| US09536122B2 |
Disposable multivariable sensing devices having radio frequency based sensors
A multivariable sensing device for sensing one or more parameters of a process fluid disposed in a container is provided. The multivariable sensing device includes a radio frequency based sensor configured to sense a physical parameter, a chemical parameter, a biological parameter, or combinations thereof, representative of the process fluid. The radio frequency based sensor includes a sensor substrate, a radio frequency coil disposed on at least a portion of the sensor substrate, and a support structure configured to be physically coupled to the container. Further, the support structure is configured to position the radio frequency based sensor in operative proximity to an inside of the container. |
| US09536117B2 |
Pluggable small form-factor UHF RFID reader
Systems and methods for reading Radio Frequency Identified (RFID) tags. In an embodiment, an enclosure having, within it, an antenna and processor is provided. The processor may be configured to record tag observations for tag identifiers received by the antenna from RFID tags. For one or more time intervals, tag observations may be identified which satisfy a tag filter, and a confidence that RFID tags satisfying the tag filter were in the field of view of the antenna during the time interval may be computed based on the identified tag observations. According to an embodiment, reports for tag filters may be then generated using the computed confidences, and these reports may be transmitted to an external system over a network. |
| US09536115B2 |
Electronic device and method for unlocking the electronic device
In a method for unlocking an electronic device with a touch screen and a distance sensor, a triggering signal to unlock the electronic device is received. Objects within a predetermined distance of the distance sensor is determined. The touch screen is activated to display an unlocking area if no object is detected within the predetermined distance of the distance sensor. Touch signals are received from the unlocking area to determine whether an unlocking operation is performed. A time duration that the touch screen has been activated is calculated to determine whether the unlocking operation is performed within a preset time period from activation of the touch screen. The electronic device is unlocked if the unlocking operation is performed within a preset time period from activation of the touch screen, and a predetermined application is executed when the electronic device is unlocked. |
| US09536114B1 |
Secure mobile proactive multiparty computation protocol
Described is system for secure mobile proactive multi-party computation. The system securely evaluates a circuit in the presence of an adversary. The circuit receives secret inputs comprising secret values from a set of servers. Sharings of random values for the random and input gates are generated. For each input gate, a sharing of a random value associated with the input gate is opened toward a server Pi. A sum of the server Pi's secret values and the random value is broadcast to the set of servers. Each server uses the sum to adjust its sharing of the random value, generating a sharing of server Pi's secret values. The secret values are re-randomized to preserve privacy of the secret values. A sharing of the secret values is determined for each output gate, and each sharing of secret values is revealed to an intended recipient. |
| US09536112B2 |
Delaying or deterring counterfeiting and/or cloning of a component
In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value. |
| US09536108B2 |
Method and apparatus for generating privacy profiles
A privacy processing system may use privacy rules to filter sensitive personal information from web session data. The privacy processing system may generate privacy profiles or privacy metadata that identifies how often the privacy rules are called, how often the privacy rules successfully complete actions, and the processing time required to execute the privacy rules. The privacy profiles may be used to detect irregularities in the privacy filtering process that may be associated with a variety of privacy filtering and web session problems. |
| US09536105B2 |
Method and apparatus for providing data access via multi-user views
An approach is provided for providing data access via multi-user views. An access management platform determines at least one view of data, wherein the at least one view is created based on one or more queries with one or more projections in one or more monadic elements to the data. The access management platform further determines one or more policies for accessing the data, wherein the one or more policies specify at least one or more access capabilities. The access management platform also causes storage of the one or more policies, the one or more access capabilities, or a combination thereof in the one or more monadic elements. The access management platform further causes granting of access to the at least one view by one or more requesting devices, wherein the granting of the access is determined by processing of the one or more monadic elements. |
| US09536104B2 |
Managing global cache coherency in a distributed shared caching for clustered file systems
Various embodiments are provided for managing a global cache coherency in a distributed shared caching for a clustered file system (CFS). The CFS manages access permissions to an entire space of data segments by using the DSM module. In response to receiving a request to access one of the data segments, a calculation operation is performed for obtaining most recent contents of one of the data segments. Most recent contents are determined if ownership of the one of the data segments is possessed by a remote DSM module and the request to access one of the data segments is for shared permission and exists in the local external cache. The most recent contents are transported within the response if the response is in a remote external cache and has a valid permission for the one of the data segments otherwise reading from the one of the data segments. |
| US09536103B2 |
Secure cloud storage distribution and aggregation
Methods and systems for vendor independent and secure cloud storage distribution and aggregation are provided. According to one embodiment, an application programming interface (API) is provided by a cloud storage gateway device logically interposed between third-party cloud storage platforms and users of an enterprise. The API facilitates storing of files, issuing of search requests against the files and retrieval of content of the files. A file storage policy is assigned to each user, which defines access rights, storage diversity requirements and a type of encryption to be applied to files. Responsive to receiving a request to store a file, (i) searchable encrypted data is created relating to content and/or metadata of the file based on the assigned file storage policy; and (ii) the searchable encrypted data is distributed among the third-party cloud storage platforms based on the storage diversity requirements defined by the assigned file storage policy. |
| US09536099B2 |
Information processing apparatus and method of setting security thereof
An information processing apparatus includes an accepting unit that accepts from a user a command relating to security; a setting unit that makes a setting relating to security of the information processing apparatus based upon the command from the user accepted by the accepting unit; a recording unit that performs the following operation in a case where the accepting unit has accepted a command for changing a security-related setting that has already been made by the setting unit: before the setting unit changes the security-related setting, the recording unit records an event, among events that occur in the information processing apparatus, the content of which will be different between a case where the security-related setting is changed and a case where the security-related setting is not changed; and a notification unit that notifies the user based upon the event that has been recorded by the recording unit. |
| US09536098B2 |
Methods and systems for concealing information
A retrieving system for retrieving information concealed within a sequence of symbols. The system includes a decoder configurable using rule information and operable when so configured to retrieve the information concealed within the sequence of symbols by applying to the sequence of symbols at least one decoder rule determined by the configuration of the encoder. |
| US09536096B2 |
Presenting visualizations of business intelligence data
A system and method for managing business intelligence data is described. In some example embodiments, the system extracts data and metadata from a business intelligence file, generates a data bundle of the data and metadata, generates an application bundle based on the date bundle, and generates an interactive document using the data bundle and application bundle. |
| US09536095B1 |
System for booting and dumping a confidential image on a trusted computer system
A computer system for booting a confidential image on a trusted computer system. A trusted computer system loads an encrypted client image key onto a protected area on the trusted computer system. The trusted computer system loads an encrypted boot image onto a secure logical partition on the trusted computer system. The trusted computer system decrypts the encrypted client image key to obtain a client image key in the protected area. The trusted computer system decrypts, with the client image key, the encrypted boot image to obtain a boot image and a client data key. The trusted computer system starts the boot image, and the boot image mounts the encrypted client data onto the secure logical partition. The client data key is used by the boot image to decrypt data read from the encrypted client data and to encrypt data written to the encrypted client data. |
| US09536094B2 |
Mediated secure boot for single or multicore processors
A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes. This results in an end-to-end secure boot process for a variety of architectures, such as single processor systems, synchronous and asynchronous multiprocessing systems, single core systems and multi-core processing systems. |
| US09536093B2 |
Automated verification of a software system
Software code of a software system (e.g., a software stack) may be verified as conforming to a specification. A high-level language implementation of the software system may be compiled using a compiler to create an assembly language implementation. A high-level specification corresponding to the software system may be translated to a low-level specification. A verifier may verify that the assembly language implementation functionally conforms to properties described in the low-level specification. In this way, the software system (e.g., a complete software system that includes an operating system, device driver(s), a software library, and one or more applications) may be verified at a low level (e.g., assembly language level). |