| Document | Document Title |
|---|---|
| US09509492B2 |
Authentication device, output device, verification device and input device
According to an authentication device is for authenticating the validity of a subject ciphertext generated by encrypting a plaintext using homomorphic encryption. The authentication device includes a commitment generator and a response generator. The commitment generator is configured to generate a commitment from a randomly selected verification value, and transmit the commitment to a verification device for verifying the validity of the subject ciphertext. The response generator is configured to generate a response value generated by computing from an acquired challenge value, the plaintext, and the verification value, and transmit the response value to the verification device. The response generator is configured to generate the response value by a third operation where a result of a first operation using the response value is equal to a result of processing the challenge value, the subject ciphertext, and the commitment by a second operation. |
| US09509490B1 |
Reference clock sharing
A system for sharing a reference clock signal between multiple devices is disclosed. The system includes a source device, and a plurality of destination devices. The source device may be configured to generate a reference clock signal and transmit data via a communication link. The reference clock signal may include first and second phases, and the second phase may be an inverse of the first phase. A filter unit configured to filter the reference clock signal may be coupled between the first and second phases of the reference clock signal. Each destination device may be configured to receive the reference clock signal and receive the data dependent upon the reference clock signal. |
| US09509489B1 |
Correction of quadrature modulation errors
In one aspect a computer-implemented method is performed. The method may include capturing intermediate data samples for transmission by a wireless communications transmitter. The method may further include applying signal processing to the intermediate data samples, capturing output data samples after applying the signal processing, and/or determining quadrature correction coefficients from the intermediate data samples and the output data samples, wherein the quadrature correction coefficients remove quadrature errors caused by the signal processing. The method may further include applying the quadrature correction coefficients to a series of input data samples, wherein the intermediate data samples comprise the input data samples with the quadrature correction coefficients applied to the input data samples. The capturing the intermediate data samples, the applying the signal processing, the capturing the output data samples, the determining the quadrature correction coefficients, and the applying the quadrature correction coefficients may be performed by at least one processor. |
| US09509487B2 |
Synchronous transfer of streaming data in a distributed antenna system
Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal. |
| US09509483B2 |
Uplink control and data transmission in multiflow-enabled networks
Signaling and procedural considerations are disclosed for uplink multiflow operations in user equipment configured for carrier aggregation. Advanced wireless networks may take advantage of unused capacity of neighboring cells by configuring network nodes and UEs to both receive on the downlink and transmit on the uplink to multiple cells or network nodes. Implementing multiflow on UE for the uplink transmission process may cause issues in various channels, signaling, and procedural operations that may be addressed through data and control signaling the techniques disclosed herein. |
| US09509478B2 |
Method and apparatus for data and control multiplexing
System(s) and method(s) are provided for transmitting data code symbols and control code symbols spanning disparate transmission time intervals in the uplink. Data and control symbols that overlap in time-domain within a transmission time interval are multiplexed and transmitted employing resources scheduled for data transmission, whereas data and control code symbols that are not multiplexed are transmitted in respective allocated resources. Multiplexing in conjunction with localized and distributed resource scheduling preserves the single-carrier characteristics of a single-carrier frequency division multiple access system. |
| US09509475B2 |
Method and apparatus for transmitting and receiving data
Disclosed are a method and an apparatus for transmitting and receiving data. A method for transmitting an uplink comprises the steps of: a terminal receiving periodic channel state information (CSI) configuration information; the terminal determining an uplink subframe according to the periodic CSI configuration information; and the terminal transmitting a periodic CSI through the uplink subframe, wherein the periodic CSI configuration information may include information regarding a period, subframe offset, and a reference cell to which a wireless frame number is applied. |
| US09509469B2 |
Device, network, and method for utilizing a downlink discovery reference signal
User equipments can achieve quick channel synchronization when establishing a connection to base stations transitioning from a sleep mode to an active mode by using discovery resource signal (DRS) processing results and cell reference signal (CRS) processing results to establish channel synchronization with a CRS antenna port. More specifically, the user equipment may be notified that the CRS antenna port and DRS antenna port are quasi-co-located (QCL), and then use DRS processing results in conjunction with CRS processing results to obtain faster channel synchronization with a CRS antenna port. This may be particularly beneficial when the target BS is transitioned from a sleep mode to an active mode in order to accept a handover of the user equipment. |
| US09509465B2 |
Multi-channel communication station for communicating a multi-channel PPDU and methods of reducing collisions on secondary channels in multi-channel wireless networks
Embodiments of a very-high throughput communication station and method for communicating on a primary channel and up to three or more secondary channels are generally described herein. Short-preamble detection may be performed during a contention window to detect packet transmissions on any one of the secondary channels starting within the contention window. Guard-interval detection is also performed during the contention window to detect a guard interval of a packet transmission on any one of the secondary channels. The short-preamble detection and the guard-interval detection may be performed concurrently during the contention window to determine if any of the secondary channels are busy. |
| US09509460B2 |
Apparatus for receiving downlink signal in a wireless communication system and method thereof
A method of receiving downlink signal at a user equipment in a wireless communication system is disclosed. The present invention includes receiving an information related to a reference signal of a neighbor cell from a serving cell and performing an interference handling in resources in accordance with the information related to the reference signal of the neighbor cell, wherein the information related to the reference signal of the neighbor cell comprises at least one selected from the group consisting of a cell ID (identity) of the neighbor cell, the number of ports for transmitting the reference signal of the neighbor cell, an frequency information for transmitting the reference signal of the neighbor cell and an time information for transmitting the reference signal of the neighbor cell. |
| US09509457B2 |
Allocating resources and transmitting data in mobile telecommunication systems comprising machine type communication applications
A method of communicating data in a wireless telecommunications system between plural base stations and plural terminal devices using plural Orthogonal Frequency Division Multiplex, OFDM, sub-carriers spanning a first frequency bandwidth. The method includes: communicating data between a first base station and a first terminal device using a first OFDM sub-carrier group distributed across the first frequency bandwidth, communicating data between a second base station, geographically separated from the first base station, and a second terminal device using a second OFDM sub-carrier group distributed across a second frequency bandwidth, the second frequency bandwidth being smaller than and within the first frequency bandwidth; and communicating control-plane data between the first base station and the first terminal device using a combination of the first and second groups of the OFDM sub-carriers. Guard regions may be provided in the frequency domain between frequencies of transmissions associated with the first and second base stations. |
| US09509455B2 |
Autonomous channel quality information prediction
Data characterizing a first signal transmitted in an orthogonal frequency-division multiplexing (OFDM) system by a transmitter with one or more transmit antennas through an in-band channel and received by a receiver with a plurality of receive antennas can be received. The first signal can include one or more in-band pilot pulses. A channel quality for an out-of-band channel can be predicted based on the received data and a cross-correlation between an in-band channel and one or more out-of-band channels. Data characterizing the predicted channel quality for the out-of-band channel can be provided. Related apparatus, systems, techniques, and articles are also described. |
| US09509454B2 |
Signal transmission system, transmission apparatus, receiver apparatus, signal transmission method, transmission apparatus control program, and receiver apparatus control program
A signal transmission system includes a transmission apparatus provided with a transmitting device which outputs a transmitting data signal as a transmission signal using a driving ability designated by a drive control signal, and a drive control device which outputs a drive control signal based on a transmission timing signal and a determination notice signal for notifying reception quality; and a receiver apparatus provided with a receiving device which receives the transmission signal and outputs a received signal, a timing generating device which generates a received timing signal from the received signal, and a determining device which determines reception quality of the received signal using the received timing signal, and outputs the determination result as the determination notice signal. |
| US09509452B2 |
Increasing capacity in wireless communications
Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding is performed on slots as they are received over the air, and techniques are described for signaling acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes in the system. |
| US09509451B2 |
Methods and apparatus for multi-carrier communication systems with automatic repeat request (ARQ)
Hybrid ARQ is employed in a multi-carrier communication system for retransmission of erroneous packets by taking advantage of time/frequency/space diversity and by combining ARQ functions at physical layer and MAC layers, making the multi-carrier system more robust in a high packet-error environment. |
| US09509448B2 |
Methods and apparatus for enhanced status retransmission
Methods and apparatus of enhanced status retransmission in wireless communication include receiving at least a first portion of a reconfiguration message from a network entity. The methods and apparatus further include detecting an absent second portion of the reconfiguration message. Moreover, the methods and apparatus include sending a retransmission request to the network entity based at least in part on the detecting of the absent second portion of the reconfiguration message and irrespective of a state of a status prohibit timer. Additionally, The methods and apparatus include triggering a status prohibit timer disregard state for at least a portion of a status prohibit time period of the status prohibit timer, wherein the status prohibit timer disregard state permits the sending of the retransmission request during the status prohibit timer period. |
| US09509447B2 |
Method and apparatus for improved network coding in wireless communication system
A method of performing a Network Coding (NC) by a transmitting node in a wireless communication system, the method comprising receiving uplink packets from a plurality of nodes through respective links, grouping the links into at least one group based on channel quality information, each group satisfying a listed range of channel quality information, performing the NC on downlink data for each group and transmitting each scheduling information shared by each group to the at least one respective group. A method of receiving network-coded data in a wireless communication system comprises transmitting an uplink packet to a transmitting node, receiving scheduling information shared by a group of links from the transmitting node, the group of links satisfying a listed range of channel quality information, receiving downlink data on which NC is performed and decoding the downlink data based on the scheduling information. |
| US09509440B2 |
Method and radio node for enabling use of high order modulation in a radio communication with a user equipment
A method and radio node (500) for enabling higher-order modulation in a radio communication with a first UE (502). A first table configuration comprises at least one of a first Modulation and Coding Scheme, MCS, table and a first Channel Quality Indicator, CQI, table which tables support a certain maximum modulation order. When the radio node (500) detects that a modulation order higher than the maximum modulation order of the first table configuration is potentially possible to use in the radio communication, the radio node (500) instructs the first UE (502) to apply a second table configuration which comprises at least one of a second MCS table and a second CQI table which second tables support the higher modulation order. At least one entry for at least one modulation order in the tables of the first table configuration is maintained in the tables of the second table configuration as a fall-back in case it is desirable to use the at least one modulation order of the first table configuration when the second table configuration is applied. Thereby, a higher data rate can be achieved in the radio communication. |
| US09509436B2 |
Protection of near-field communication exchanges
Techniques are disclosed for protecting communication of an NFC-enabled device by generating one or more blocking signals during an NFC data exchange. The blocking signal(s) can include a similar carrier frequency, modulation type, and/or modulation rate an NFC signal, thereby effectively masking the NFC signal. Furthermore, the blocking signal(s) can have a varying amplitude and/or length, which can further mask when an NFC signal is transmitted. |
| US09509432B2 |
Optical spectral-temporal connector
An optical spectral-temporal connector, having multiple connector modules, interconnects a large number of nodes in a full-mesh structure. A wavelength-division-multiplexed link from each node is de-multiplexed into wavelength channels individually directed to different connector modules. Each connector module has a set of star couplers, each star coupler connecting to wavelength channels from a respective set of nodes through spectral translators. Each spectral translator cyclically shifts a spectral band of a wavelength channel so that, at any instant of time, spectral bands of signals at inlets of any star coupler are disjoint. A spectral router connects outlets of the set of star couplers to a respective set of nodes. A spectral-translation controller prompts each spectral translator to shift to a new spectral band. Several arrangements for time-aligning all the nodes to the connector modules are disclosed. |
| US09509428B2 |
Photonic routing systems and methods computing loop-free topologies
Systems and methods for routing wavelengths in an optical network include responsive to a path request for a wavelength or group of wavelengths, determining a path through the optical network; determining a location on the path where wavelength blocking should occur to form a loop-free path in the optical network; and setting the wavelength blocking at the location. The optical network can utilize a broadcast and select architecture and the wavelength blocking is configured to prevent the wavelength or group of wavelengths from looping back on a port where the wavelength or group of wavelengths has already been received on. The optical network can utilize an all-broadcast architecture and the wavelength blocking is configured to prevent multiple paths for the wavelength or group of wavelengths by constraining the wavelength or group of wavelengths to a single path through the optical network. |
| US09509426B2 |
Interference estimation resource definition and usage for enhanced receivers
At a wireless node in a wireless network, multiple interference estimation resources are received in a time-frequency resource space. The multiple interference estimation resources are resource elements in an assigned physical shared channel of the time-frequency resource space that do not contain physical shared channel data for the wireless node. An interference covariance matrix is determined from received signals on the multiple interference estimation resources. Symbol estimates are determined for a desired signal based in part by using the interference covariance matrix. Methods, computer programs and products and apparatus are disclosed. The techniques may be used for uplink, downlink, or D2D communications. |
| US09509425B2 |
Signal detection method and apparatus
A method and an apparatus for detecting signals in a cellular system are provided. The method includes estimating power of a dominant interference cell and detecting a signal by reducing a detection performance degradation caused by an interference signal of the dominant interference cell. The dominant interference cell includes a cell, other than a serving cell, causing an interference. |
| US09509422B2 |
Configurable, highly-integrated satellite receiver
A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters. |
| US09509421B2 |
Differential signal transmission circuit, disk array controller, and differential signal transmission cable
The invention provides a differential signal transmission circuit, a disk array controller, and a differential signal transmission cable, which are capable of allowing a worker to easily confirm a failure in a differential signal transmission path. The differential signal transmission circuit includes an inductance provided between positive and negative transmission paths, a DC voltage part that applies a DC voltage to the transmission paths, a monitoring part that monitors a magnitude of the DC voltage applied to the transmission paths, and a controller that detects a failure in each of the transmission paths on the basis of the magnitude of the DC voltage monitored by the monitoring part, and, when the failure is detected, outputs a notification of the occurrence of the failure. |
| US09509419B2 |
Communication circuit and associated calibration method
A communication circuit includes a receiver path, a frequency translating loop filter and a signal source circuit. The frequency translating loop filter includes an auxiliary mixer, and a frequency translating filter backend circuit such as a filter. The signal source circuit can be shared with a transmitter path. When the receiver path receives an external signal, the auxiliary mixer and the frequency translating filter backend circuit perform high-frequency filtering. When the receiver path need not receive the external signal, the auxiliary mixer up-converts a low-frequency auxiliary signal provided by the signal source circuit to a high-frequency domain, and the up-converted signal is received by the receiver path. Thus, an operation parameter of the receiver path can be adjusted and calibrated according to a response of the receiver path. |
| US09509417B2 |
Method in which a terminal transceives a signal in a wireless communication system and apparatus for same
The present application relates to a method in which a terminal receives a signal in a wireless communication system. More particularly, the method comprises: a step of receiving, from a serving cell, interference mitigation information for mitigating interference from a neighboring cell; and a step of applying an interference mitigation technique based on the interference mitigation information so as to receive a signal from the serving cell. It is assumed that the serving cell does not apply said interference mitigation technique from after the reception of the interference mitigation information to the application of the interference mitigation technique. |
| US09509416B2 |
Interference cancellation within OFDM communications
Many communication systems operate based on orthogonal frequency division multiplexing (OFDM) signaling and/or orthogonal frequency division multiple access (OFDMA) signaling. Within such systems, narrowband interference, which may alternatively be referred to as narrowband ingress, narrowband ingress interference, narrowband noise, etc., may adversely affect one or more subcarriers or tones causing a reduction in performance or even link failure. Such narrowband interference may affect only one or a relatively few tones employed within such communications. When the narrowband interference is identified, a transmission may then be made including one or more information-free tones. A device that receives such a transmission then uses those information-free tones to reduce or cancel the narrowband interference. Such processing may be performed in the frequency-domain, the time domain, or both. |
| US09509414B2 |
Encryption and decryption method and device
The present invention provides an encryption and decryption method and device. In the method, a first optical transport network (OTN) transport device encrypts, according to an initial vector (IV), a key, and an encryption algorithm that are preset, data received by the first OTN transport device, and sends the IV and the encrypted data to a second OTN transport device; and the second OTN transport device receives a value of a high-order counter in the IV and the encrypted data that are sent by the first OTN transport device, where the encrypted data is data encrypted by using the IV, the preset key, and the encryption algorithm, and decrypts the encrypted data according to the preset key, the IV, and a decryption algorithm corresponding to the encryption algorithm. |
| US09509413B2 |
Optical receiver, optical receiving device, and method for correcting received optical intensity
The common mode rejection ratio (CMRR) decreases due to the difference in receiving intensity of the optical signal or in photoelectric conversion efficiency of the photodiode in the related coherent optical receiver, therefore, an optical receiver according to an exemplary aspect of the present invention includes a first photodiode receiving a first optical signal and outputting a positive signal; a second photodiode receiving a second optical signal and outputting a complementary signal; a differential transimpedance amplifier receiving the positive signal and outputting an amplified positive signal voltage, and receiving the complementary signal and outputting an amplified complementary signal voltage; and a gain adjustment means for adjusting a first gain of a gain of the differential transimpedance amplifier for the positive signal and a second gain of a gain of the differential transimpedance amplifier for the complementary signal. |
| US09509411B2 |
Phase shift keying optical modulation apparatus and method of encoding a symbol onto an optical carrier signal
Phase shift keying optical modulation apparatus comprising optical phase shifting apparatus and an optical modulator. The optical phase shifting apparatus is arranged to receive an optical carrier signal and is arranged to selectively apply a preselected optical phase shift to the optical carrier signal in dependence on a symbol of a 2N-level phase shift keying modulation format to be encoded onto the optical signal. The optical modulator is arranged to receive the optical carrier signal from the optical phase shifting apparatus and is arranged to apply a phase modulation to the optical carrier signal in dependence on the symbol, to thereby encode the symbol onto the optical carrier signal. The phase modulation is a phase-modulation of an N-level phase shift keying modulation format. |
| US09509405B2 |
Multi-mode fiber node
In a first configuration, circuitry of a fiber node may be configured to modulate an optical carrier by an analog upstream electrical signal received via the electrical network. In a second configuration, the circuitry may be configured to digitize the analog upstream electrical signal to generate a digitized upstream signal, and modulate the optical carrier with the digitized upstream signal. An optical receiver of the fiber node may be configured to convert a downstream optical signal to a downstream electrical signal. In the first configuration, the downstream electrical signal may be a first analog signal and the circuitry may be configured to output the first analog signal into the electrical network. In a third configuration, the downstream electrical signal is a digitized waveform and the circuitry is configured to convert the digitized waveform to a second analog signal and output the second analog signal into the electrical network. |
| US09509402B2 |
System and method for communication with a mobile device via a positioning system including RF communication devices and modulated beacon light sources
A light source emits a modulated light, and a radio-frequency transceiver disposed therewith emits a radio-frequency signal. A mobile device may receive either or both signals and determine its position based thereon. The light and radio-frequency sources may be disposed in node in a network of said sources, and the nodes may communicate via the radio-frequency transceivers. |
| US09509401B2 |
Visible light communication method in an information display device having an LED backlight unit, and information display device for the method
Proposed is a method for providing additional information to a mobile communication terminal by means of visible light communication in an information display device having an LED backlight unit. For this purpose, the method of the present invention comprises the steps of: receiving, from a mobile communication terminal, a request for additional information on an object in a content image when a content image is being displayed on a screen of an information display device; determining whether or not there exists additional information corresponding to the request; and controlling, if said additional information does exist, the light emission of the LED backlight unit so as to transmit said additional information in the form of visible light to the mobile communication terminal. Further, according to the present invention, it is possible to provide various additional information corresponding to the request from the mobile communication terminal. |
| US09509398B2 |
Relay method, relay system, recording medium, and method
A relay method includes transmitting, by a first apparatus in a ring network, a first control frame in which information of the first apparatus is stored, through a first port different from a second port where a communication failure is detected; receiving, by a second apparatus in the ring network, the first control frame through a third port, when the communication failure does not occur at a side of a fourth port different from the third port: storing information of the second apparatus in the first control frame; and transmitting the first control frame through the fourth port; and when the communication failure occurs at the side of the fourth port, determining whether a data frame flowing into the ring network is affected by the communication failure for every VLAN (virtual local area network) based on the first control frame; and switching a communication path set in an affected VLAN. |
| US09509396B2 |
Systems and methods for shared analog-to-digital conversion in a communication system
A low noise block circuit includes a first input signal trace configured to receive a first satellite signal centered at a first frequency; a second signal trace configured to receive a second satellite signal centered at a second frequency; a combiner having a first input connected to the first input signal trace and a second input connected to the second signal trace, and configured to combine the first and second satellite signals to generate and output a combined satellite signal; and an analog-to-digital converter element having a first input coupled to receive the combined satellite signal, and configured to convert the combined satellite signal from an analog signal to a digital signal. |
| US09509395B2 |
Wireless software dialer and messaging head
Provided is a system and device, and for use with a satellite for communicating between a vehicle and a base station. The system comprises a peripheral device, an access point to link the peripheral device to an onboard satellite communication device, and the onboard satellite communication device. The device is programmable, has a software dialer, and a messaging controller for the onboard satellite communication device. Also provided is a method for communicating between a vehicle and a base station. |
| US09509390B2 |
Method and apparatus for providing Channel State Information-Reference Signal (CSI-RS) configuration information in a wireless communication system supporting multiple antennas
A method for receiving channel state information (CSI) feedback by a base station supporting multiple transmit antennas from a mobile station; the base station therefore; a method for transmitting CSI feedback by a mobile station to a base station supporting multiple transmit antennas; and the mobile station therefore are discussed. The method for receiving CSI feedback by a base station includes according to one embodiment configuring, by the base station via radio resource control (RRC) signaling, one or more channel state information-reference signal (CSI-RS) configurations and one or more null resource element (RE) configurations; transmitting CSI-RSs; and receiving the CSI feedback measured based on the CSI-RSs and the one or more null RE configurations. The one or more CSI-RS configurations are used for a channel quality measurement of the CSI feedback. The one or more null RE configurations are used for an interference measurement of the CSI feedback. |
| US09509389B2 |
Method and apparatus for transmitting channel state information in wireless communication system
Disclosed are a method and an apparatus for transmitting channel state information (CSI) of a user equipment, which is allocated a plurality of serving cells, in a wireless communication system. The method comprises: receiving setting information for setting groups comprising at least one serving cell from the plurality of serving cells, and transmitting periodic CSI with respect to a group that is selected according to priority between the groups, when the periodic CSI with respect to each of the groups is set to be transmitted from the same subframe, wherein the periodic CSI with respect to each of at least two serving cells are transmitted together when the at least two serving cells are included in the group that is selected. |
| US09509385B2 |
Apparatus and method for digital beam-forming with low-resolution quantization
An antenna arrangement configured for digital beam-forming of a transmit signal comprising; a number N>1 of digital to analog converters, DACs, each of the N DACs being arranged to receive one respective digital transmit signal component, and to convert and output an analog transmit signal component, each of the N DACs having a respective resolution below a resolution required to fulfill a regulatory radio requirement in an interchangeable antenna arrangement arranged for transmission by a single antenna element connected to a single DAC; and N antenna elements, each of the N antenna elements being configured to receive one respective analog transmit signal component and to transmit the analog transmit signal component as part of the digitally beam-formed transmit signal. |
| US09509384B2 |
System and method for mapping symbols for MIMO transmission
Methods and devices are provided for MIMO OFDM transmitter and receivers having odd and/even numbers of transmit antennas. Various methods for pre-coding information bits before space time coding (STC) are described for enabling transmission of information bits over all antennas. Methods of decoding received signals that have been pre-coded and STC coded are also provided by embodiments of the invention. Pilot patterns for downlink and uplink transmission between a base station and one or more wireless terminals for three transmit antenna transmitters are also provided. Variable rate codes are provided that combine various fixed rate codes in a manner that results in codes whose rates are dependent on all the various fixed rate codes that are combined. |
| US09509382B1 |
Beamforming to a subset of receive antennas in a wireless MIMO communication system
In a method for determining a transmit steering matrix for use in transmission of an information signal from a first communication device to at least one second communication device, a subset of antennas of the at least one second communication device is selected from a plurality of different subsets of the antennas of the at least one second communication device, wherein selecting the subset of antennas is for developing the steering matrix for transmit beamforming from the first communication device to the least one second communication device. The steering matrix is developed i) based on training signals received via the selected subset of the antennas of the at least one second communication device, and ii) assuming that only the selected subset of the antennas of the at least one second communication device will be utilized by the at least one second communication device when receiving the information signal. |
| US09509381B1 |
Apparatus and method of blind detection of interference rank information in wireless communication system
A method is provided. The method includes receiving a signal, wherein the signal includes a serving signal and an interference signal; removing the serving signal from the received signal to provide a residual signal; equalizing the residual signal based on linear estimation; determining a sample sum of the equalized signal; determining a plurality of eigenvalues from the sample sum; and estimating a transmission rank of the interference signal using hypothesis testing based on the plurality of eigenvalues. |
| US09509380B2 |
Methods for opportunistic multi-user beamforming in collaborative MIMO-SDMA
A system and method for opportunistically designing collaborative beamforming vectors is disclosed for a wireless multiple input, multiple output (MIMO) space division multiple access (SDMA) communication system by sequentially designing beamforming vectors for ranked channels in order to exploit the instantaneous channel conditions to improve per user average SNR performance. Each subscriber station independently transmits information to a base station that allows the base station to determine beamforming vectors for each subscriber station by ranking the subscriber stations by channel strength. Using sequential nullspace methods, the ranked channel matrices are then used to select the channel matrix Hi for the best subscriber station, to design the wi, vi for the best subscriber station as the left and right singular vectors of the MIMO channel matrix Hi, to transform the remaining channels and to continue the process until beamforming vectors are designed for all channels. |
| US09509376B2 |
Information handling system with multi-purpose NFC antenna
A server information handling system baseboard management controller (BMC) includes an NFC transceiver that communicates NFC signals through an NFC antenna structure. The BMC selectively configures the NFC antenna structure to isolate portions of conductive material for use as an antenna in non-NFC communications, such as wireless local area network communications (WLAN) at 2.4 or 5 GHz or wireless personal area network (WPAN) communications at 2.4 or 60 GHz. In one embodiment, WLAN and WPAN communications are encrypted with a key provided through NFC or other types of wireless communication, such as visible, infrared or ultraviolet light signals. |
| US09509369B2 |
Systems and methods for adjusting signaling properties based on cable attributes
This is generally directed to adjusting signaling properties based on cable attributes. In some embodiments, the cable attributes can include information such as the length of a cable, the diameter of a cable, the type of plug on a cable, the type of or presence of shielding on a cable, or any combination of the above. This information can then be used to determine the appropriate signaling properties for that cable (e.g., with respect to an EMC standard). The appropriate signaling properties may, for example, optimize the signal that is used to drive the cable while still allowing the cable to generate emissions that are within acceptable EMC standards. In some embodiments, the appropriate signaling properties can include factors such as the drive strength of the signal, the slew rate of the signal, the maximum voltage of the signal, the frequency of the signal, or any combination of the above. |
| US09509364B2 |
Integrated antenna unit with field replaceable frequency specific devices
An integrated antenna unit, including an extra-wideband antenna, a docking station, and an integrated, field replaceable remote radio unit that electrically couples to the docking station. The docking station may be configured to receive a removable transmission circuit that that electrically couples the remote radio unit and the antenna. |
| US09509361B1 |
Camera-based accessory classification
A method for using an accessory with a mobile device is disclosed. The method includes: causing at least one camera of the mobile device to capture one or more images of a pattern disposed on a surface of an accessory that is being used with the mobile device; identifying a code associated with the accessory from the one or more images of the pattern; determining a type associated with the accessory based on the identified code; and entering an accessory-specific operating mode in which behavior of the mobile device is controlled to accommodate features that are specific to the accessory. |
| US09509359B2 |
Mobile terminal device
A mobile terminal device (1) according to the present invention includes a housing (11) and a display panel (14). The housing (11) includes a housing body (111) and side walls (112a) provided around the housing body (111). The display panel (14) is provided on the side walls (112a, 112b). The side walls (112a, 112b) are made of sheet metal. An end portion of the sheet metal that faces the display panel (14) is bonded to the display panel(14). Thereby, a mobile terminal device that allows a reduction in frame width while maintaining the strength can be provided. |
| US09509357B2 |
Removable vehicular rooftop communication system
A vehicular rooftop communication system (200) provides communication electronics (216) within a housing (210) formed of a removable rooftop enclosure (212) and a base (214). The housing (210) is removable and transferable to another vehicle. The vehicular rooftop communication system (200) does not require any access to the vehicle's trunk. |
| US09509354B2 |
Homodyne receiver with improved linearity
A homodyne receiver (100, 200, 300), comprising a first mixer (115, 215, 315) with an RF input port (105, 213, 313) and an LO input port (110, 214, 314) for an LO signal and an output port (120, 217, 317) for the output signal of the first mixer which is also arranged to be the output port of the homodyne receiver. The homodyne receiver (100, 200, 300) also comprises a control unit (125) for controlling signal leakage from the LO input port (110, 214) to the RF input port (105, 213) of the first mixer (115, 215). The control unit (125) is arranged to control the leakage in amplitude and phase so that second-order distortion products and third order distortion products which are created when the RF and LO signals are mixed in the first mixer (115, 215) exhibit similar amplitudes but a phase difference of 180 degrees. |
| US09509353B2 |
Data processing device
One example discloses a data processing device, comprising: a local oscillator (LO) having an LO frequency output, an LO performance parameter output, and an LO frequency select input; and a degradation detection module, coupled to the LO performance parameter output and to the LO frequency select input, and including an LO frequency select module triggered by the LO performance parameter output. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for controlling a data processing device which comprise: monitoring a set of local oscillator (LO) performance parameters; setting an LO degraded state when at least one of the LO performance parameters is not within a predetermined range; and adjusting an LO frequency in response to the LO degraded state. |
| US09509352B2 |
Phase-noise cancellation apparatus and method
A noise cancellation method comprises receiving, by an adaptive phase-noise cancellation apparatus, a noise-corrupted symbol from a receiver, performing a hard decision process on the noise-corrupted symbol to generate a substantially clean symbol based upon the noise-corrupted symbol, calculating a phase deviation of the noise-corrupted symbol based upon the substantially clean symbol and the noise-corrupted symbol, generating a phase error based upon the phase deviation and transmitting, at an output of the adaptive phase-noise cancellation apparatus, a phase corrected symbol determined in accordance with a subtraction of the generated phase error from the received noise-corrupted symbol. |
| US09509348B1 |
Transmitter efficiency optimization
Radio transceiver efficiency is improved by operations involving a calibration mode and an operating mode. The calibration mode includes a first calibration to determine a first optimized tuning control data for a first antenna matching network of a first transmitter when a second transmitter of the portable transceiver system inactive. A second calibration of the first antenna matching network while the second transmitter is active to determine second optimized tuning control data. In operational mode the first optimized tuning control data is used when the second transmitter is not active. The second optimized tuning control data is used when the second transmitter is active. |
| US09509347B2 |
Antenna driver with scalable output impedance
A system includes an antenna, a modulator, and a controller. The modulator may be operatively connected to the antenna. The modulator may be configured to send, a signal to a wireless device via the antenna. The modulator may have an output impedance. The controller may be connected to the output of the antenna. The controller may include a detector and a driver. The detector may be configured to determine the amplitude of a response from the wireless device. The driver may be configured to scale the output impedance responsive to the amplitude. |
| US09509340B2 |
Low-power low density parity check decoding
In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node. |
| US09509338B2 |
Apparatus and method for processing data
A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad. |
| US09509337B1 |
Hardware data compressor using dynamic hash algorithm based on input block type
A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block. |
| US09509335B1 |
Hardware data compressor that constructs and uses dynamic-prime huffman code tables
A hardware data compressor for compressing an input block of characters. A first hardware engine that, for an initial fraction of the input block of characters produces character string replacement back pointers and indicates characters not replaced by the back pointers, and generates occurrence frequencies of symbols associated with the produced back pointers and the non-replaced characters. A second hardware engine constructs a Huffman code table using the frequencies generated for the initial fraction of the input block. The first hardware engine, for the remainder of the input block beyond the initial fraction, produces character string replacement back pointers and indicates characters not replaced by the back pointers. A third hardware engine, for the entire input block of characters, Huffman encodes the symbols associated with the back pointers and the non-replaced characters using the Huffman code table constructed using the frequencies generated for the initial fraction of the input block. |
| US09509333B2 |
Compression device, compression method, decompression device, decompression method, information processing system, and recording medium
A compression device includes a processor configured to execute a process. The process includes: storing, in a storage, a first compressed code in association with a first element, the first compressed code corresponding to a combination of a first element and a first delimiter, the first element being one of a plurality of elements constituting input data, the first delimiter being one of delimiters delimiting the plurality of elements and succeeding the first element in the input data; acquiring, from the storage, the first compressed code in response to reading a sequence of the first element and the first delimiter from the input data; and writing the first compressed code into a storage area that stores therein compressed data of the input data. |
| US09509330B2 |
Analog-to-digital converter probe for medical diagnosis and medical diagnosis system
Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal. |
| US09509327B2 |
A/D converter and A/D converter calibrating method
An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit. |
| US09509321B2 |
Main clock high precision oscillator
A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator. |
| US09509320B2 |
Feedback loop frequency synthesizer device
This frequency synthesis device comprises a servo circuit for the control of a frequency provided as output by a reference frequency received as input, with this circuit comprising a first phase accumulator clocked at a frequency linked to the reference frequency, a first digital-to-analog converter, a phase comparator, a loop filter and a controlled frequency oscillator providing an electrical signal oscillating at the output frequency. It further comprises a feedback loop connecting the output to the phase comparator, comprising a second phase accumulator clocked at a frequency linked to the output frequency and a second digital-to-analog converter. A reduction in dynamics by quantization is provided between each phase accumulator and each respective digital-to-analog converter, with this quantization being carried out by truncation of digital values of accumulated phases at the output of each phase accumulator. |
| US09509319B1 |
Clock and data recovery circuit
A clock and data recovery (CDR) circuit that receives an input signal and generates clock and sampled output signals includes a phase-frequency detector (PFD) circuit, a control circuit, a digital-to-analog converter (DAC), a current-controlled oscillator (CCO) and a data sampler. The PFD generates intermediate and fine digital control signals. The DAC receives the intermediate digital control signal as a coarse digital control signal and the fine digital control signal and generates an output current. The CCO receives the output current and generates the clock signal. The coarse digital control signal is used to coarse calibrate a frequency of the clock signal and the fine digital control signal is used to fine calibrate the frequency of the clock signal. The data sampler receives the clock signal and samples the input signal at the frequency of the clock signal to generate the sampled output signal. |
| US09509318B2 |
Apparatuses, methods, and systems for glitch-free clock switching
Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit. |
| US09509316B2 |
Gray counter and analogue-digital converter using such a counter
An N-bit Gray counter, with N an integer greater than 1, comprises a string of N logic cells connected in cascade, wherein each logic cell comprises an input port for a succession of clock pulses, a circuit for generating a Gray count bit having an output port for the Gray count bit and a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell. An analog-digital converter of ramp type using such a Gray counter is also provided. |
| US09509315B2 |
Superconducting three-terminal device and logic gates
A three-terminal device that exhibits transistor-like functionality at cryogenic temperatures may be formed from a single layer of superconducting material. A main current-carrying channel of the device may be toggled between superconducting and normal conduction states by applying a control signal to a control terminal of the device. Critical-current suppression and device geometry are used to propagate a normal-conduction hotspot from a gate constriction across and along a portion of the main current-carrying channel. The three-terminal device may be used in various superconducting signal-processing circuitry. |
| US09509313B2 |
3D semiconductor device
A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors. |
| US09509310B1 |
LVDS and subLVDS driver circuit
A driver circuit configured to produce a pair of output signals from a pair of input signals.The proposed solution brings improvements over conventional LVDS and subLVDS driver circuits because it enables the use of a single driver circuit (also known as “buffer”) which is compliant with both LVDS and subLVDS transmission standards. This allows flexibility with MCUs for instance the automotive industry. Further, proposed solution has the advantage of saving die size in comparison to a solution where two buffers would have been used for different transmission standards. Further, high speed transmission rate is maintained since transmission is performed for one standard at the time.An integrated circuit, a printed circuit and a data processing circuit are also claimed. |
| US09509306B2 |
Tamper resistant IC
According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth. |
| US09509303B2 |
Pressure-sensitive switch, manufacturing method for same, touch panel including pressure-sensitive switch, and manufacturing method for touch panel
A pressure-sensitive switch includes a first substrate, a conductive structure provided on the first substrate, and an electrode unit disposed to face the first substrate with the conductive structure located therebetween. The conductive structure includes an electrode layer on the first substrate, and an elastic component having conductivity and extending to protrude from the electrode layer toward the electrode unit. |
| US09509299B2 |
Apparatus and method for control of semiconductor switching devices
Disclosed is a control circuit for control of a semiconductor switching device, such as an IGBT. The control circuit comprising a first feedback path between a first electrode and a control electrode of said semiconductor switching device which has a capacitance. The circuit is operable such that the capacitance in the first feedback path is dependent on the voltage level at said first electrode. In another embodiment the control circuit is operable such that a feedback signal begins to flow in the first feedback path immediately as the semiconductor switching device begins switching off, thereby causing a control action on the semiconductor switching device. |
| US09509297B2 |
Switching circuit for controlling current responsive to supply voltage values
A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value. |
| US09509292B2 |
Method and apparatus for improving a load independent buffer
Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal. |
| US09509290B2 |
Frequency converter
A frequency converter, comprising a multi-phase local oscillator and a multi-phase mixer. The mixer comprises a plurality of mixer switches, each connected to a respective amplifier. The local oscillator is configured to provide a switching signal to each mixer switch, and comprises a plurality of inverters configured as a ring oscillator. |
| US09509288B2 |
Variable pulse width generator and method
In one embodiment a dozer blade controller, which may comprise two-way, four-way, or six-way dozer blade position control such as, for example, a two-way control only for blade tilt. In one embodiment, a pulse width control is provided for use in a blade tilt electronic controller, which controls blade tilt independently of movement of the body of the bull dozer. And in another embodiment, a pulse width controller is operable to multiply and/or divide the width of a variable pulse by a preset multiplier factor or divider factor, e.g. by 100 or dividing by 100. |
| US09509281B1 |
Peaking inductor array for peaking control unit of transceiver
Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor. |
| US09509280B1 |
Cavity filtered qubit
A technique relates to a microwave device. A qubit is connected to a first end of a first coupling capacitor and a first end of a second coupling capacitor. A resonator is connected to a second end of the first coupling capacitor and a second end of the second coupling capacitor. The resonator includes a fundamental resonance mode. A filter is connected to both the qubit and the first end of the first or second coupling capacitor. |
| US09509260B2 |
High-speed transimpedance amplifier
A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node. |
| US09509259B2 |
Amplifier
An amplifier 12 including a first transistor 23 which is a common base transistor and whose emitter current fluctuates in accordance with fluctuations in an input current that is input to the emitter, a second transistor 24 which is a common base transistor, whose emitter is connected to the collector of the first transistor 23, and whose collector voltage fluctuates in accordance with fluctuations in the emitter current of the first transistor 23, a third transistor 31 which is a common collector transistor and whose base is connected to the collector of the second transistor 24, and an amplification unit 40 to which an emitter voltage of the third transistor 3 is input and which outputs an amplified voltage obtained by amplifying the emitter voltage of the third transistor, wherein the base resistance of the second transistor 24 is higher than the base resistance of the first transistor 23. |
| US09509258B2 |
Signal amplifier having inverted topology in stacked common gate structure
A signal amplifier may include a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal, a second common gate-type amplifying unit connected to a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal, a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit, and an impedance matching unit impedance-matching a signal summed by the signal summing unit. |
| US09509252B2 |
Doherty amplifier
The invention relates to a Doherty amplifier for amplifying an input signal at an operating frequency, comprising: a main amplifier; a first peak amplifier; a second peak amplifier, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal, a plurality of peak amplifiers, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal; a first input phase shifter; a second input phase shifter; a first capacitor coupled between the source and drain of the first peak amplifier; a first output phase shifter and a second output phase shifter. |
| US09509246B2 |
Control system for an electric motor
A control system for an electric motor, the control system comprising a first control device arranged to control current in a first coil set of the electric motor and a second control device arranged to control current in a second coil set of the electric motor; wherein the first control device includes a first interface arrangement for receiving data from a first controller for allowing the first control device to determine a required current flow in the first coil set, wherein the first interface arrangement is arranged to communicate data to the second control device for allowing the second control device to determine a required current flow in the second coil set. |
| US09509243B2 |
Automatic actuator calibration using back EMF
A self-calibrating linear actuator is configured to control a spring return valve with variable stroke. The actuator includes a motor, a spindle coupled to an output of the motor, a motor controller coupled to the motor, a microcontroller coupled to the motor controller, and a back electromotive force (BEMF) circuit, coupled to the motor, configured to provide to the microcontroller a BEMF value for each motor step. The microcontroller is configured to determine a difference of a number of motor steps during operation of the actuator and to store the difference as a calibrated touch point for the actuator. |
| US09509242B2 |
Systems and method for speed and torque control of a DC motor
A method for operating a direct current (DC) motor is shown and described. The method includes generating a first pulse width modulated (PWM) signal having a first duty cycle, providing the first PWM signal as a PWM DC output for the DC motor, and adjusting the first duty cycle to control a speed of the DC motor. The method further includes sensing an electric current output to the motor using a current sensor and, when the sensed current exceeds a threshold, holding the PWM DC output off. |
| US09509240B2 |
Electric motor using multiple reference frames for flux angle
A drive unit includes: an electric motor; a flux estimator circuit configured to estimate at least a flux angle; a synchronous frame generator coupled to a rotor of the AC induction motor and configured to detect a rotor mechanical angle; and a switch configured to selectively provide either the flux angle or the rotor mechanical angle for controlling the motor. |
| US09509239B2 |
Rotating electric machine control system
A rotating electric machine control system has a power control unit (PCU) and a control section separately disposed therein. The apparatus receives a trigger signal from a communicator of the PCU via a trigger communication line from an MG ECU when the MG ECU obtains electric angles from a rotation sensor. The communicator, upon receiving an input of the trigger signal, generates a communication frame that includes plural detection values from a current sensor and a voltage sensor. Then, the communicator outputs the communication frame to the MG ECU via a multiplex communication line. The MG ECU performs a preset process for a control of an inverter and a booster converter based on the detected electric angles and the communication frame matching with those electric angles. |
| US09509237B2 |
AC motor with stator winding tap and methods for starting an AC motor with a variable speed drive
Methods for starting an AC motor with a variable speed drive and switching the motor to a higher voltage power source are described. Provided are AC motors with a stator having a plurality of coils, the plurality comprising a complete set of coils for each phase, the complete set comprising a first set of coils comprising first groups of coils connected in series, or parallel, or a combination, and a second set of coils comprising second groups of coils connected in series, or parallel, or a combination, wherein the output of a variable speed drive is connected to a tap on the complete set of coils such that the AC motor may be started with a variable speed drive, and an output of the power line is connected to the series of the first and second sets of coils. |
| US09509235B2 |
Piezoelectric element, oscillatory wave motor, and optical apparatus
A piezoelectric element that can decrease the output voltage for detection relative to the input voltage for driving without requiring a step-down circuit between a detection phase electrode and a phase comparator and an oscillatory wave motor including the piezoelectric element are provided. A piezoelectric element includes a piezoelectric material having a first surface and a second surface, a common electrode disposed on the first surface, and a drive phase electrode and a detection phase electrode disposed on the second surface. An absolute value d(1) of a piezoelectric constant of the piezoelectric material in a portion (1) sandwiched between the drive phase electrode and the common electrode and an absolute value d(2) of a piezoelectric constant of the piezoelectric material in a portion (2) sandwiched between the detection phase electrode and the common electrode satisfy d(2) |
| US09509224B2 |
Method for controlling synchronous rectifier of power converter and control circuit using the same
The invention discloses a method for controlling a synchronous rectifier of a power converter and a control circuit using the same. The method includes the following steps. A control signal is generated to control a synchronous rectification transistor in response to an on-time of a switching signal, a level of a transformer voltage and an output voltage of the power converter. The switching signal is used for switching a transformer. The control signal is generated once the switching signal is turned off. A transformer signal is related to an input voltage of the power converter. The control signal is generated when the on-time of the switching signal is longer than a first time threshold. |
| US09509223B2 |
LLC bidirectional resonant converter and methods of controlling
A LLC bidirectional resonant converter comprising: a resonant tank, a first switching circuit connected to the resonant tank via first power conduits, a second switching circuit connected to the resonant tank via second power conduits, a switching element, and at least one switchable inductive element which is arranged by the switching element to be in parallel across the second power conduits when operating in a first mode of operation and arranged by the switching element to be in parallel across the first power conduits when operating in a second mode of operation. |
| US09509221B2 |
Forward boost power converters with tapped transformers and related methods
In a switching mode power converter coupled between first and second terminal pairs, a first circuit path includes a first inductance and a first switch. A tapped transformer has a first winding coupled across the first inductance and a tapped second winding with a tapped winding portion. A second circuit path includes a capacitance coupled to a second inductance, and the second circuit path is coupled to the first inductance through the tapped winding portion in a third circuit path and through the second winding in a fourth circuit path. During their respective conduction periods, the first switch couples the first inductance across the first terminal pair, a second switch completes a circuit between the second terminal pair and the second circuit path or the third circuit path, and a third switch completes a circuit that includes another of the second circuit path and the fourth circuit path. |
| US09509220B2 |
Bi-modal voltage converter
A bi-modal voltage converter and associated method for reducing stress on secondary rectifiers and decreasing switching losses. An embodiment of the voltage converter comprises three switches and control circuitry that is operative, upon a determination with respect to the input voltage, to select between a two-switch operation and a three-switch operation. When the input voltage is greater than a threshold value, one of the three switches is permanently turned on, while the other two switches are controlled using a pulse-width modulated (PWM) signal. When the input voltage is equal to or less than the threshold value (e.g., requiring a duty cycle greater than 50%), all three switches are controlled by the PWM signal. |
| US09509216B2 |
Switching power supply circuit
A switching power supply circuit includes: a voltage generation circuit that generates an output voltage by smoothing, with a capacitor, a voltage produced in an inductor; an integration circuit that integrates a switching voltage to generate a first ripple voltage including a first ripple component; a feedback voltage generation circuit that divides the output voltage to generate a feedback voltage; a comparison circuit that compares the feedback voltage with a reference voltage to output the result of the comparison as a comparison result signal; an integration circuit that integrates the comparison result signal to generate a second ripple voltage including a second ripple component; and a drive circuit that controls the turning on and off of a switch element based on the comparison result signal, where the first ripple component and the second ripple component are added to the feedback voltage. |
| US09509213B1 |
Charge pump circuit suitable for low voltage operation
A charge pump device with NMOS transistor circuit is provided for low voltage operation. The charge pump stage, comprising four NMOS transistors and three capacitors, is configured to alleviate the substrate body effect and the charge transfer loss. The charge pump circuit can be constructed on a p-type semiconductor substrate directly without deep N well isolation. The circuit is driven by two non-overlapping complementary clock signals, which can be generated easily with an integrated fabrication. The charge pump device can be implemented with a multiple stage to provide a stable high voltage output. |
| US09509210B2 |
Start-up circuit and method for AC-DC converters
For starting-up a power converter, an AC rectified voltage is generated upon power-up of the power converter. A depletion mode transistor generates a first voltage from the rectified voltage. The first voltage is inputted to a controller of the power converter to provide power for operation of the controller before an output stage of the power converter starts outputting power. A gate biasing voltage is generated from the first voltage and supplied to a gate terminal of the depletion mode transistor to bias the gate terminal of the depletion mode transistor. |
| US09509209B2 |
Drive unit for switching element
An inverter for driving a motor generator has series connection units, each of which has two switching elements, connected in series, in high and low voltage sides, respectively. A drive unit is arranged for each switching element. A gate of the switching element is connected to an emitter thereof through a first cutoff resistance and a first cutoff switching element in the drive unit. The gate of the switching element is also connected to the emitter thereof through a second cutoff resistance and a second cutoff switching element in the drive unit. A resistance value of the first cutoff resistance is higher than a resistance value of the second cutoff resistance. A software cutoff process is performed when the switching element is in a completely turned-on state so that the first cutoff switching element is turned on and the second cutoff switching element is turned off. |
| US09509207B2 |
Apparatus for compensating for ripple and offset of inverter and method therefor
An apparatus and method for compensating for a ripple and offset of an inverter and an apparatus and method for compensating for a ripple and offset of an inverter which removes a ripple component by compensating for an offset component included in a signal input to the inverter from an inverter controller. A method that senses a direct current (DC) input to an inverter from an inverter controller and an alternating current (AC) output from the inverter and removes a ripple component included in the DC based on the sensed currents, a method that removes a ripple component included in a reference voltage that is output from an inverter controller and is input to an inverter, and a method that compensates for an offset component of an AC voltage/AC used for inverter control and reduces a ripple component corresponding to an output frequency of an inverter. |
| US09509206B2 |
Power factor corrector correcting a power factor of an alternating current (AC) voltage
A power factor corrector correcting the power factor of an alternating current (AC) voltage is disclosed. A power factor correcting unit corrects the power factor of the AC voltage. A smoothing unit smoothes a power factor corrected voltage and includes a film condenser and a plurality of electrolytic condensers. A rectified voltage is applied to one end of an inductor. One end of a switch is connected to the other end of the inductor, and the other end of the switch is earthed. One end of a diode is connected to one end of the switch. One end of a film condenser is connected to the other end of the diode, and the other end of the film condenser is earthed. An electrolytic condenser is parallel-connected to the film condenser. |
| US09509203B1 |
Stepping motor
Provided is a stepping motor which includes a bracket, a stator and a rotor disposed at the bracket, a lead screw of which both ends are fixed to the bracket, and rotating while coupled to the rotor, and a moving part coupled to the lead screw and guided along a side surface of the bracket to move, wherein guide protrusions are formed at both side surfaces of the moving part, the bracket includes guide slots formed at side surfaces and into which the guide protrusions are inserted, and the guide slots are formed to have heights higher than those of the guide protrusions, thereby providing an advantageous effect of minimizing friction contact. |
| US09509200B2 |
HF generator with improved solid-state switch connections
An HF generator has first and second solid-state switches. Each of the solid-state switches has first and second output connectors and is designed to switch a high-frequency electrical current between the first and second output connectors. Furthermore, the HF generator has a coaxial cable with first and second conductors. The first conductor successively has a first section and a second section in the longitudinal direction of the coaxial cable which are separated from one another by a first break point. The first output connector of the first solid-state switch is conductively connected to the second conductor, and the second output connector of the first solid-state switch is conductively connected to the first section. In addition, the first output connector of the second solid-state switch is conductively connected to the first section, and the second output connector of the second solid-state switch is conductively connected to the second section. |
| US09509199B2 |
Energy harvesting devices
An energy harvesting device includes at least one first magnet configured to rotate along a first circular path in a first plane. The energy harvesting device includes at least one piezo-electric cantilever spaced apart from the first plane, the at least one piezo-electric cantilever being configured to bend in a direction substantially perpendicular to the first plane. The energy harvesting device also includes at least one second magnet coupled to the at least one cantilever and configured to overlap the at least one first magnet. |
| US09509195B1 |
Embedded encoder for an outrunner brushless motor
An example embedded encoder for an outrunner brushless motor is provided. An example motor includes a motor shaft, a stationary stator, a rotor coupled to the motor shaft and provided external to the stationary stator for rotating around the stationary stator to cause rotation of the motor shaft, and a faceplate coupled to the stationary stator that includes a cavity. The motor also includes an encoder embedded into the cavity of the faceplate that comprises a code wheel coupled to the motor shaft and a read head for providing an output indicative of an angular position of the code wheel. The faceplate provides alignment between the code wheel and the read head. |
| US09509194B2 |
Generator assembly
An electric machine, such as a generator, providing for the generation of electricity and includes a rotor generating a magnetic field and a stator having stator windings. The interaction of the magnetic field with the stator windings generates current in the windings. The generator may provide the generated current to a power output of the generator, where it may be further transmitted to an electrical load to power the load. |
| US09509193B2 |
Motor actuator
A motor actuator of the present invention includes: a motor including an outer shell portion internally provided with a rotor that rotates as a unit with a rotation shaft, and supported portions respectively provided at both axial direction end portions of the outer shell portion; a power supply terminal connected to the motor; a case internally housing the motor, and including support portions; a resilient member fitted interposed between each of the support portions and the supported portions; and an insulating member disposed between the outer shell portion and the power supply terminal, nipped between an outer peripheral portion of the outer shell portion and the resilient member, and formed with a cut-out hole at a location to the radial direction outer side of a location in contact with the resilient member, and at the radial direction inner side of an outer peripheral portion of the outer shell portion. |
| US09509188B2 |
Stator of rotary electric machine
A stator of a rotary electric machine includes a stator core that includes a plurality of slots; and a plurality of conductor segment coils that each have a U-shape. A sectional area of the U-shaped portion of the conductor segment coil that protrudes out from one side in the axial direction of the stator core is larger than a sectional area of a tip end portion of the conductor segment coil that protrudes out from the other side in the axial direction of the stator core; and the sectional area of the tip end portion of the conductor segment coil that protrudes out from the other side in the axial direction of the stator core is larger than a sectional area of an in-slot portion of the conductor segment coil. |
| US09509185B2 |
Rotor with permanent excitation including permanent magnets and soft-magnetic flux conducting elements therebetween, electric machine having such a rotor and manufacturing method for the rotor
A rotor includes a shaft, a plurality of permanent magnets arranged around the shaft in a circumferential direction for permanent excitation and attached to the shaft by an adhesive bond, and a flux conducting device provided for conducting a magnetic flux of the permanent magnets. The flux conducting device has a plurality of soft-magnetic flux conducting elements. Each flux conducting element is placed between two of the permanent magnets and adhesively bonded thereto. |
| US09509180B2 |
Brushless motor for electric power tool
A brushless motor for the electric power tool is configured such that a rotor having a magnet is radially disposed on the inner side of a stator having winding wires, and a bonded magnet is used as the magnet of the rotor. |
| US09509178B2 |
System and a method for communicating user interaction data to one or more communication devices
A system attached to an object for communicating the object information to communication devices. The system includes an electronic circuitry to communicate an identification-information, and a hub section coupled to the communication device to power the electronic circuitry and further receives the identification-information transmitted from the electronic circuitry. The electronic circuitry may be embedded in a single chip/printed decal/flexible polymer foil. The hub section includes a generator, a first converter, a first switching unit, a first electrode, a first detection unit, and a hub controller. The electronic circuitry includes a second electrode, a floating electrode, a second converter, a buffer, a second detection unit, a modulation unit, and an analog processing unit. The hub controller authenticates the electronic circuitry on receiving the modulated identification-information; further the hub controller communicates the object information to the electronic circuitry and the communication devices based on the modulated identification-information. |
| US09509173B2 |
Wireless power transmission and charging system, and impedance control method thereof
A wireless power transmission and charging system and method are provided. The wireless power may refer to energy that may be transferred from a wireless power transmitter to a wireless power receiver. The wireless power transmission and charging system may include a source device to wirelessly transmit power, and a target device to wirelessly receive power. |
| US09509169B2 |
Wireless charging device and control method thereof
There are provided a wireless charging device and a control method thereof, the wireless charging device including: a first receiving module receiving power from the outside in a magnetic induction scheme to thereby charge a battery; a second receiving module receiving power from the outside in a magnetic resonance scheme to thereby charge the battery; a switching unit performing a switching operation at a preset interval such that one of the first receiving module and the second receiving module is selected; and a switching controlling unit receiving a stop signal or an operating signal from one of the first receiving module and the second receiving module to thereby control the switching operation of the switching unit. |
| US09509168B2 |
Wireless power transmitters with wide input voltage range and methods of their operation
The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging DC input voltage. The inverter is configured to generate the square wave with a duty cycle that results in a desired equivalent voltage output, effectively independent of the DC input voltage that is provided. Thus, by generating a square wave with a selectable duty cycle the inverter provides the ability to facilitate wireless power transfer with a wide range of DC input voltages. Furthermore, in some embodiments the power transmitter may provide improved power transfer efficiency using a quasi-resonant phase shift control strategy with adjustable dead time and a matching network that is dynamically selectable to more effectively couple with the transmitter coil combination being used to transmit power to the electronic device. |
| US09509166B2 |
Apparatus and method for wireless power transmission
An apparatus and method for efficiently, wirelessly transmitting a power to a plurality of target devices are provided. A wireless power transmitter may include: a source resonator configured to wirelessly transmit energy to a target device with at least one target resonator, the energy being stored in a capacitor; and a feeding unit configured to generate an induced current flowing in the source resonator in the same direction as a direction of an input current flowing in a transmission line, the feeding unit being electrically connected to the capacitor and forming a closed loop with the source resonator. |
| US09509159B2 |
Systems and methods for decreasing peak energy consumption of a power consumer using vehicle battery capacity
Systems and methods of reducing peak energy consumption of a power consumer comprise preprogramming an actual consumption line based on expected power usage, and determining the battery's connection time, required departure time, required departure energy and connection energy. A charge rate and a discharge rate are preselected, and a first charge energy level is calculated from the peak energy level less the discharge rate and the charge rate. A connection time of the battery when the battery is connected to the power consumer, a connection energy of the battery at the connection time, a required departure time of the battery, a required departure energy are determined. A power exchange curve is determined during a connection period between the connection time and the required departure time configured to minimize an expected peak energy level. |
| US09509157B2 |
Power bank device and current-output method thereof
A power bank device includes a load node, a power-supply circuit, an output circuit, a detecting unit, and a control circuit. The power-supply circuit provides an output current via the load node. The output circuit generates an output voltage at the load node according to the output current. The detecting unit generates a detecting signal according to the output current. The output circuit includes an impedance circuit. The control circuit, according to the detecting signal, controls the output circuit to switch an impedance of the impedance circuit, thereby down-regulating the output voltage and the output current. |
| US09509156B2 |
Power supply apparatus
A battery charger in a power supply apparatus is mechanically and electrically connectable to and disconnectable from a battery that is for supplying electric power to a power-assisted bicycle, and includes an AC outlet and a USB connecting terminal that are electrically connected with the other apparatus and supply the electric power from the battery to the other apparatus. |
| US09509152B2 |
Method and apparatus for self-heating of a battery from below an operating temperature
A method and apparatus for a self-heating battery pack uses a battery cells of a first battery cell circuit to power a device. However these battery cells become substantially inoperative below a very cold temperature, so a second battery cell circuit, having a second type of battery cells which can operate at the cold temperature, is used to power a heating element to warm up the first battery cells to a temperature at which they can operate. |
| US09509149B2 |
Power management system and management method
A power management system comprises a power generation equipment that generates power and a storage battery that stores power, and is connected to a power grid. The power management system comprises: a control unit that controls an operation mode of the storage battery so as to start charging the storage battery when a voltage value of the power grid exceeds a predetermined system voltage threshold value. |
| US09509145B2 |
Distributed power supply system
The disclosed distributed power supply system does not become disconnected from a grid simultaneously with others when the grid voltage falls instantaneously. In a distributed power supply device which controls an inverter circuit 10 based on a control signal obtained by comparing a predetermined carrier signal and voltage command signals of three phases and which converts DC power to AC power and supplies the AC power to a power grid of a three-phase AC power supply, fundamental wave signals of three phases are generated from a grid voltage of the three-phase AC power supply. A reference cosine wave signal is generated from the fundamental wave signals of three phases. A third harmonic signal is generated from the reference cosine wave signal and the fundamental wave signals of three phases. The three-phase fundamental wave signals and the third harmonic signal are added to generate voltage command signals of three phases. |
| US09509143B1 |
Wide dynamic range charger
A wide dynamic range charger module is configured to couple a variable power source such as a photovoltaic cell to a load. The module determines a maximum power point (MPPT) of the power source and based at least in part upon that MPPT selects one of a plurality of power converters to provide power to the load. The selection is such that the selected power converter is operating within its operating regime. The selected power converter may further be configured to a pre-determined input admittance which corresponds to the power source. |
| US09509137B2 |
Electrostatic discharge protection device
An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased. |
| US09509134B2 |
Centralized DC curtailment for overvoltage protection
A disconnect unit and an associated method in a photovoltaic system includes a plurality of input power lines configured to receive power from a photovoltaic (PV) generator, and deliver the received power to an inverter. The disconnect unit further includes a sensor configured to determine a voltage at the plurality of input power lines, and a controller configured to selectively disconnect and reconnect one or more of the plurality of input power lines based on the determined voltage. |
| US09509132B2 |
Switching device for controlling energy supply of a downstream electric motor
A switching device includes an energy store and a measuring device connected to a control apparatus. The energy store is connected in series between the supply connection and the power supply. The control apparatus can monitor the energy supply of the switching device in the area between the supply connection and the power supply taking place via the supply connection via the measuring device. If the energy supply monitored by the measuring device falls into a critical range, and using the energy from the energy store: the control apparatus connects the semiconductor switch in an electrically conductive manner and then opens the second switch; and subsequently switches the semiconductor switch to an electrically non-conductive state and then opens the first switch. |
| US09509122B1 |
Optical cladding layer design
Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a III-V semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the III-V semiconductor layer. A cladding region between the silicon semiconductor layer and the III-V semiconductor layer has a spatial property to substantially confine the optical mode to the III-V semiconductor layer and enable heat dissipation through the silicon semiconductor layer. |
| US09509121B2 |
Semiconductor laser element, integrated semiconductor laser element, and method for producing semiconductor laser element
A semiconductor laser element includes: a semiconductor-layered structure including a waveguide core layer and having a distributed feedback laser portion and a distributed Bragg reflection portion, the waveguide core layer having a length continuous in an optical cavity length direction and a diffraction grating layer being disposed in vicinity of the waveguide core layer and along the waveguide core layer in the distributed feedback laser portion, and the waveguide core layer being disposed discretely and periodically to form a diffraction grating in the distributed Bragg reflection portion; and an electrode for injecting a current to the distributed feedback laser portion. The distributed feedback laser portion oscillates a laser light at a wavelength corresponding to a period of the diffraction grating layer. The diffraction grating formed by the waveguide core layer in the distributed Bragg reflection portion is set to have a stop band including the wavelength of the laser light. |
| US09509117B2 |
Optoelectronic component, optoelectronic device and method of producing an optoelectronic device
An optoelectronic component includes a housing including a base having an upper side and a lower side, and a cap, and a laser chip arranged between the upper side of the base and the cap, wherein a first solder contact pad and a second solder contact pad are formed on the lower side of the base, the laser chip includes a second electrical contact pad, and the second electrical contact pad electrically conductively connects to a section of the base electrically conductively connected to the second solder contact pad by a second bonding wire. |
| US09509113B2 |
Transient gain cancellation for optical amplifiers
Methods and systems for transient gain cancellation at an optical amplifier may involve generating saturating light that is introduced in a reverse direction to a transmission direction at a doped fiber amplification element. The doped fiber amplification element may amplify an input optical signal having a plurality of wavelengths as well as the saturating light. The saturating light may be regulated by a control circuit to counteract transient gain effects of add/drop events in the input optical signal. The saturated light may be filtered to achieve a desired spectral profile. |
| US09509112B2 |
CW DUV laser with improved stability
A deep ultra-violet (DUV) continuous wave (CW) laser includes a fundamental CW laser configured to generate a fundamental frequency with a corresponding wavelength between about 1 μm and 1.1 μm, a third harmonic generator module including one or more periodically poled non-linear optical (NLO) crystals that generate a third harmonic and an optional second harmonic, and one of a fourth harmonic generator module and a fifth harmonic generator. The fourth harmonic generator module includes a cavity resonant at the fundamental frequency configured to combine the fundamental frequency with the third harmonic to generate a fourth harmonic. The fourth harmonic generator module includes either a cavity resonant at the fundamental frequency for combining the fundamental frequency with the third harmonic to generate a fifth harmonic, or a cavity resonant at the second harmonic frequency for combining the second harmonic and the third harmonic to generate the fifth harmonic. |
| US09509110B1 |
Adapter for LED strip light
A waterproof adapter that connects strip light to a standard power cord, such that the power cord can then be routed to a power source. The adapter has an internal vertical barrier to separate power and ground leads, and gripping structures that help to retain the strip light within the adapter. A gasket or gaskets within the adapter seal the adapter from the elements. |
| US09509109B2 |
Combination RJ connector and flash card connector
A combination connector includes a number of walls defining a housing and a female RJ connector and a female flash card connector inside the housing. Contact pins extend from contacts of the female RJ connector and contacts of the female flash card connector through at least one wall of the housing for connection to a PCB. The walls include electromagnetic interference (EMI) shielding. |
| US09509106B2 |
Coaxial connector plug
A coaxial connector plug includes a first outer conductor with a cylinder shape extending in a first direction, a first center conductor that has a cylinder shape extending in the first direction and is provided inside the first outer conductor, and an insulation member that fixes the first center conductor to the first outer conductor. In the coaxial connector plug, a communication section to cause the inside and the outside of the first center conductor to communicate with each other is provided in an end portion of the first center conductor on one side in the first direction. A width of the communication section in a second direction orthogonal to the first direction becomes larger as it progresses from the one side toward the other side of the first direction, and the insulation member penetrates from the outside to the inside of the first center conductor through the communication section. |
| US09509103B2 |
Electrostatic discharge protection
An apparatus comprising: a connector for providing an electrical interface, the connector comprising an opening configured to receive a suitable member; at least one conductive contact located at least partially within the connector and configured to operate as a switch such that when the connector is in an unplugged to partially plugged state the at least one conductive contact is grounded and when the connector is in a partially plugged to a fully plugged state the at least one conductive contact is coupled to an electrical terminal channel interfacing an electrical signal between the connector and the member. |
| US09509099B2 |
Electrical connector having improved anti-EMI performance
An electrical connector (100) with an end connected with a cable (200) includes: an insulative housing (10) including a front face (102), a rear face (103), and a number of side faces (101); a number of contacts (20) mounted to the insulative housing; and a metal shell (30) enclosing the insulative housing. The metal shell includes a first metal shell (31), a second metal shell (32), and a third metal shell (3) cooperated to seal gaps between the insulative housing and the cable. |
| US09509093B2 |
Connector
When a female connector body is inserted into a hood portion in a temporary lock state of a moving plate, plate lifting locks are deflected in a falling-over direction which is different from an outside direction of a male connector housing by lock portions and the plate lifting locks and the lock portions are engaged with each other after the plate lifting locks are deflected in the falling-over direction. |
| US09509090B2 |
Plug comprising an internal pullout mechanism
A plug comprising: a housing (210); an ejector (220); an inner core (230) comprising at least two pins (232); wherein: the inner core (230) is slidably mounted within the ejector (220) while the ejector (220) is slidably mounted in the housing (210); the housing (210) comprises a fixedly mounted first bracket (211) configured to guide a first end of a lever (240); the ejector (220) comprises a fixedly mounted second bracket (221) configured to guide a second end of the lever (240); the lever (240) has a middle mounting element (242B), shifted from the center of the lever (240) towards one of its ends, configured to guide a rod (243) attached to the inner core (230); wherein the lever (240) is configured within the housing (210) such that when the ejector (220) slides out of the housing (210) to a first extent, due to the movement of the lever (240), the inner core (230) slides within the ejector (220) to a second extent, which is lower than the first extent. |
| US09509087B2 |
Docking apparatus for portable device
A docking apparatus for a portable device includes: a mounting unit on which the portable device is to be mounted; a mounting unit support which supports the mounting unit; a connection terminal disposed in the mounting unit and configured to connect with a connector of the portable device; a terminal support part which supports the connection terminal and comprises an opening, and wherein a portion of the terminal support part is exposed through the opening so that the connection terminal can be tilted; and a hinge part which rotatably connects the terminal support part to the mounting unit. The mounting unit includes: a base support which supports a bottom portion of the portable device; and a side support which extends upwardly from a side of the base support to support a rear side portion of the portable device. |
| US09509086B2 |
Cable retention system for power distribution unit
A cable retention system for a power distribution unit includes a tether and a tether mount. The tether has an elongate portion and an attachment portion, and the attachment portion includes a channel therein. The tether mount has a base at a proximal end and a head at a distal end. The base is adapted to attach the proximal end of the tether mount to the power distribution unit. The tether is adapted to be secured to the tether mount by snap-fitting the head of the tether mount into the channel of the attachment portion. |
| US09509075B2 |
Connector connection structure
Provided is a structure in which: after a harness-side connector including a harness-side female terminal and a unit-side connector including a unit-side female terminal are caused to face each other at a position of a through hole in a floor panel, the harness-side connector and the unit-side connector are connected by a male terminal of a male connection member. In more detail, provided is a structure in which the male terminal of the male connection member is inserted through a connection-use penetrating part of the unit-side female terminal to electrically connect two female terminals, that is, the harness-side female terminal and the unit-side female terminal, to each other. Thus, a connector connection structure that does not cause the terminals to deform can be provided, and a connector connection structure that can also enhance ease of assembly and enhance ease of maintenance as a consequence can be provided. |
| US09509071B2 |
Sealed circuit board plug connector
A sealed circuit board connector for electrically connecting a connector to a circuit board. The connector includes an interface housing which has at least one signal contact in the connection region and which has at least two press-in elements with press-in zones. The interface housing is designed with a contact area for a seal. The seal is arranged in the sealing region of the circuit board plug. The seal has a passage opening for the at least one signal contact or contacts and has in each case one opening for the at least two press-in elements. |
| US09509069B2 |
Electrical connector and female terminal
An electrical connector is disclosed having a housing and a female terminal. The housing has an assembly receiving space. The female terminal is positioned in the assembly receiving space and has a first female terminal, a second female terminal, and an elastic connecting spring. The first female terminal has a first contact receiving space. The second female terminal has a second contact receiving space and is independently displaceable relative to the first female terminal along a longitudinal axis. The elastic connecting spring connects the first female terminal to the second female terminal. |
| US09509066B2 |
Connector
A connector that can adjust a force for inserting a terminal includes a base and a spring. The spring has a bend portion bent from the edge of the base and an abutment portion continued from the bend portion. The spring extends along the base and is sandwiched between the base and the abutment portion. A terminal is inserted toward the bend portion from an opening located on an opposite side of the bend portion and formed between the base and the abutment portion. |
| US09509062B2 |
Alford loop antennas with parasitic elements
According to one embodiment of the invention, a network device comprises a plurality of antennas comprising a first antenna, wherein the first antenna comprises: a first set of one or more elements that form an Alford loop and that is configured for electrical excitation via a current transmitted over a conductive medium from a signal source and a second set of one or more elements that is configured for electromagnetic induction without contact with the conductive medium from the signal source. |
| US09509061B2 |
Antenna array with asymmetric antenna elements
An RFID reader is provided that includes an antenna array comprising multiple antenna elements circumferentially distributed around a longitudinal axis of the antenna array. Each antenna element includes multiple patch elements disposed above one or more underlying substrates, wherein the patch elements of each antenna element are disposed on an outer side of the antenna element. Further, one or more of the antenna elements is an asymmetric antenna element, wherein a first end of the asymmetric antenna element is wider than a second, opposite end of the asymmetric antenna element, wherein a first patch element disposed proximate to the first end of the asymmetric antenna element is larger than a second patch element disposed proximate to the second end of the asymmetric antenna element, and wherein a resonant frequency associated with the first patch element is approximately the same as a resonant frequency associated with the second patch element. |
| US09509059B2 |
Reflector antenna including dual band splashplate support
A reflector antenna includes a dual-band waveguide feed and a splashplate support arranged to define a space between the waveguide feed aperture and the splashplate. The dual-band waveguide feed is configured to receive an input signal in a first transmission mode, to convert a transmission mode of an upper frequency band from a first transmission mode to a mixed transmission mode including the first transmission mode and a second transmission mode. The supporting portion can be spaced apart from the aperture of the waveguide feed, and may have a thickness corresponding to half a wavelength of a beam emitted from the aperture. |
| US09509057B2 |
Antenna
An antenna includes a dielectric substrate, an antenna conductor, a ground conductor, a waveguide tube, a shield, and short-circuit portions. The shield is provided with a cut having a reverse-taper shape whose width becomes greater from an open end of the cut to an inward end of the cut. The short-circuit portions are provided along a whole periphery of the shield except for a portion provided with the cut. |
| US09509048B2 |
Antenna apparatus and electronic device including the antenna apparatus
According to one embodiment, an antenna includes a second element that has an end connected to a first point of a first element, and first and second ends kept open, and includes a first portion extending from a feed terminal to the first end, and a second portion extending from the feed terminal and bifurcated at a second point between the first point and the first end. The lengths of the first and second portions are set to substantially ¼ of a resonance frequency, and substantially ¾ of a resonance frequency, severally. The second portion includes a portion extending from the feed terminal to the second point, and a portion extending from the second point to the second end and interposed between the portion and a ground. |
| US09509047B2 |
Self-configurable resonance antenna
A self-configurable resonance antenna includes a main antenna for transmitting and receiving radio waves of a plurality of mutually different frequency bands, a coupling element having at least two radiating patches with different effective electrical lengths for configuring the impedance of the self-configurable resonance antenna, and a matching circuit disposed between the main antenna and the coupling element. The matching circuit has a filter, a RF detector, a switching logic and a RF switch, the RF switch switching between at least the two radiating patches with different effective electrical lengths for adjusting the main antenna operating in different frequency bands. |
| US09509042B1 |
Single feed passive antenna for a metal back cover
Antenna structures and methods of operating the same are described. One apparatus includes a metal cover having a first corner ground element, a second corner ground element, a first strip element, a second strip element, a radio frequency (RF) feed, and a RF circuit. The first strip element is physically separated from the first corner ground element by a first cutout in the metal cover. The first strip element is physically separated from the second strip element by a second cutout in the metal cover. The second strip element is physically separated from the second corner ground element by a third cutout in the metal cover. The RF circuitry is coupled to the RF feed, where the RF circuitry is operable to cause the first corner ground element and the first strip element as well as the second corner ground element and the second strip element to radiate electromagnetic energy. |
| US09509033B2 |
Balun device for UHF signals
A balun device for UHF signals includes two conductive connection pads, a printed conductive track and a conductive ground pattern that are formed on a dielectric base plate. The conductive connection pads are connectable respectively with a pair of first signal lines for a pair of differential signals. One of the conductive connection pads is further connectable with a second signal line for a single-ended signal. The printed conductive track interconnects electrically the conductive connection pads. The conductive ground pattern is surrounded by and spaced apart from the printed conductive track and the conductive connection pads. |
| US09509028B2 |
Microbial batteries with re-oxidizable solid-state electrodes for conversion of chemical potential energy into electrical energy
A microbial battery is provided. At the anode, microbial activity provides electrons to an external circuit. The cathode is a solid state composition capable of receiving the electrons from the external circuit and changing from an oxidized cathode composition to a reduced cathode composition. Thus, no external source of oxygen is needed at the cathode, unlike conventional microbial fuel cells. The cathode can be removed from the microbial battery, re-oxidized in a separate oxidation process, and then replaced in the microbial battery. This regeneration of the cathode amounts to recharging the microbial battery. |
| US09509026B2 |
Power station arrangement with high-temperature storage unit
A power station arrangement is provided having an energy generation unit for generating useful thermal energy on the basis of physical and/or chemical processes, a high-temperature storage unit to be at least partially supplied with heat for regular operation, particularly a metal oxide/air storage unit, and a piping system for thermally coupling the energy generation unit to the high temperature storage unit. |
| US09509023B2 |
Structure for securing battery
When a battery is supported on a cooling plate, since a heat transfer sheet, which is deformable by pressure, is held between the cooling plate and a cooling surface of the battery, it is possible to efficiently transfer the heat of the battery from the cooling surface to the cooling plate via the heat transfer sheet, thereby enhancing the effect in cooling the battery. Since the heat transfer sheet includes a plurality of through holes, compared with a case in which a heat transfer sheet does not include the through hole, the reaction force generated by restoration of the compressively deformed heat transfer sheet to its original shape is decreased, thus reducing the load acting on a mounting flange securing the battery to the cooling plate and thereby preventing the mounting flange from being broken. |
| US09509022B2 |
Electric storage device and electric storage apparatus
An electric storage device includes a case having a cuboid shape and including a terminal surface having an electrode terminal, a bottom surface opposite to the terminal surface, a long side surface, and a short side surface. The device also includes an electric storage element formed by winding positive and negative plates being laminated via a separator, the electric storage element being housed in the case and being away from an inner surface of the long side surface, the electric storage element being in electrical connection with the electrode terminal, and a heat transfer member in contact with an outer surface of the long side surface. |
| US09509021B2 |
Estimation of lithium-ion battery capacity as function of state-of-lithiation swing
A method includes controlling operation of a vehicle in response to an estimation of a capacity loss and capacity of a lithium-ion battery module of the vehicle. The estimation is a function that includes a state-of-lithiation swing and fracture of a solid-electrolyte interphase of an electrode of the lithium-ion battery module. The methodology can be implemented in a vehicle that includes a lithium-ion battery module and a controller that controls operation of the vehicle in response to such an estimation. |
| US09509014B2 |
Galvanic cell having a lithium metal or an alloy comprising a lithium metal as anode material and an electrolyte having lithium . . . complex salt
A galvanic cell having a lithium metal or an alloy comprising a lithium metal as anode material, having an electrolyte comprising lithium bis(oxalate)borate and at least one other lithium complex salt in an aprotic solvent or solvent mixture, in the ratio of lithium complex salt in the conducting salt equals 0.01 to 20 mol %. |
| US09509012B2 |
Lithium ion secondary battery and method of manufacturing lithium ion secondary battery
In a lithium ion secondary battery, a negative electrode sheet is made of a metal foil and an active material layer containing active material particles. The negative active material layer includes a facing portion that faces a positive active material layer and a non-facing portion that does not face the same. The negative active material particles can be oriented in a magnetic field direction. When an angle between an extending direction of a major axis of the cross section of each particle and the metal foil is θ, the number of particles with the angle θ of 60°-90° is MA, the number of negative active material particles with the angle θ of 0°-30° is MB, and a value MA/MB is assumed to be an orientation degree (AL) of particles, the negative active material layer is made such that an orientation degree (AL1) in the non-facing portion is 1.2 or more. |
| US09509010B2 |
Biological fuel cell and methods
A fuel cell has an anode and a cathode with anode enzyme disposed on the anode and cathode enzyme is disposed on the cathode. The anode is configured and arranged to electrooxidize an anode reductant in the presence of the anode enzyme. Likewise, the cathode is configured and arranged to electroreduce a cathode oxidant in the presence of the cathode enzyme. In addition, anode redox hydrogel may be disposed on the anode to transduce a current between the anode and the anode enzyme and cathode redox hydrogel may be disposed on the cathode to transduce a current between the cathode and the cathode enzyme. |
| US09509009B2 |
Enzyme catalyzed oxidation of hydrocarbons
The present disclosure provides a method of generating electricity from a long chain hydrocarbon, said method comprising contacting the liquid non-polar substrate with a plurality of enzymes, wherein at least one enzyme is non-electric current/potential enzyme that functions as a catalyst for chemical reaction transforming a first substrate or byproduct to a second substance that can be used with an additional electric current/potential generating enzyme. |
| US09509008B2 |
Dibenzylated polybenzimidazole based polymer and method for preparing the same
A polybenzimidazole based polymer in which substituted or non-substituted benzyl groups are introduced to the two nitrogen atoms of benzimidazole ring. The benzimidazole ring is not decomposed by the attack of hydroxide ions but shows excellent alkali resistance, and thus maintains high ion conductivity. The polybenzimidazole based polymers are particularly useful for not only solid alkali exchange membrane fuel cells (SAEMFC) but also various industrial fields in which polybenzimidazole based polymers are used. |
| US09509005B2 |
Fuel cell system
A fuel cell system suppresses the deterioration of an electrolyte membrane of a fuel cell. The fuel cell system comprises: a temperature rise speed calculation unit for calculating a target temperature rise speed of the fuel cell using a temperature of the fuel cell and a water content of the fuel cell; and a drive control unit for controlling a drive of the cooling water pump using the temperature rise speed of the fuel cell and the target temperature rise speed calculated by the temperature rise speed calculation unit. The drive control unit controls the drive of the cooling water pump such that a circulation amount of the cooling water is decreased when the temperature rise speed of the fuel cell is below the target temperature rise speed and controls the drive of the cooling water pump such that the circulation amount of the cooling water is increased when the temperature rise speed of the fuel cell is equal to or greater than the target temperature rise speed. |
| US09509003B2 |
Battery comprising a plurality of elecrochemical cells and, for each cell, a device for controlling the voltage across the terminals of said cell
A battery is provided. The battery includes a plurality of electrochemical cells connected in series with each other and adapted for each generating an electric current from an oxidation-reduction reaction between an oxidizing fluid and a reducing fluid. The battery also includes, for each electrochemical cell, a control device for controlling the voltage across the terminals of the cell. The battery also includes a voltage regulator device electrically connected to the cell so that the control device measures the voltage across the terminals of the cell, increased by an offset voltage across the terminals of the regulator device. |
| US09508999B2 |
Wicking layer for managing moisture distribution in a fuel cell
An exemplary device for managing moisture content within a fuel cell includes a reactant distribution plate having a plurality of members that establish reactant flow channels that are open on at least one side of the plate. A wicking layer is against the one side of the plate. The wicking layer includes a first portion that is uninterrupted and covers over at least some of the channels. A second portion of the wicking layer extends along ends of at least some of the members such that sections of the channels coextensive with the second portion are open toward the one side. |
| US09508997B2 |
Media supply plate for a fuel cell stack
The invention relates to a media supply plate (10) for a fuel cell stack (12) comprising at least one anode gas terminal (14) and at least one cathode gas terminal (16). According to the invention the media supply plate (10) further comprises at least one anode waste gas terminal (18) and at least one cathode waste gas terminal (20). The invention further relates to a fuel cell system (52) using such a media supply plate (10) as well as a method for producing such a fuel cell system. |
| US09508995B2 |
Laminar structure and a production method for same
The present invention relates to a laminar structure which is used in a microporous layer, an electrode layer or the like of a membrane electrode assembly for a fuel cell, and also relates to a production method for same. The laminar structure is a laminar structure which is comprised in the membrane electrode assembly (MEA) of a polymer electrolyte membrane fuel cell (PEMFC), and comprises an electrosprayed layer which is formed by the lamination of electrospraying ink, that has been charged by means of an electric field, through an electrospraying process in which the electrospraying ink is dispersed and sprayed as electrospraying liquid droplets, and, in the electrospraying process, the electrospraying substance transmission mode is set in accordance with the adjustment of electrospraying process variables. When the present invention is employed, an optimal substance transmission route is formed and three dimensional structure control is allowed through the electrospraying process and/or an inkjet printing process, and thus it is possible to simultaneously ensure economic advantages and durability when producing a laminated structure which is used in a microporous layer, an electrode layer, or the like of a membrane electrode assembly for a fuel cell. |
| US09508990B2 |
Si-based-alloy anode material
Disclosed is a Si-based alloy anode material for lithium ion secondary batteries, including an alloy phase with a Si principal phase including Si and a compound phase including two or more elements, which includes a first additional element A selected from Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb and Mg and a low-melting second additional element B selected from S, Se, Te, Sn, In, Ga, Pb, Bi, Zn, Al. This compound phase includes (i) a first compound phase including Si and the first additional element A; a second compound phase including the first additional element A and the second additional element B; and one or both of a third compound phase including two or more of the second additional elements B and a single phase of the second additional element B. |
| US09508986B2 |
Electrode mixture paste, electrode, and non-aqueous electrolyte rechargeable battery
The present invention provides an electrode mixture paste containing an electrode active material, a conductive material, a binder, and an organic solvent. The electrode active material has a sodium-containing transition metal compound, the binder has a polymer soluble to the organic solvent, and the polymer does not have a structural unit derived from vinylidene halide. |
| US09508978B2 |
Rechargeable battery module
A rechargeable battery module includes a plurality of unit cells each including a rechargeable battery, a first electrode terminal, and a second electrode terminal; a bus bar coupling adjacent ones of the plurality of unit cells; a first module terminal coupled to the first electrode terminal of one of the plurality of unit cells at one side of the unit cells; a second module terminal coupled to the second electrode terminal of an other one of the plurality of unit cells at an opposite side of the unit cells; and a module short-circuit member coupled to the first module terminal or the second module terminal, separated from the other module terminal, and configured to contact the other module terminal according to temperature. |
| US09508976B2 |
Battery separator with dielectric coating
Implementations of the present disclosure generally relate to separators, high performance electrochemical devices, such as, batteries and capacitors, including the aforementioned separators, and methods for fabricating the same. In one implementation, a separator for a battery is provided. The separator comprises a substrate capable of conducting ions and at least one dielectric layer capable of conducting ions. The at least one dielectric layer at least partially covers the substrate and has a thickness of 1 nanometer to 2,000 nanometers. |
| US09508975B1 |
Nonaqueous electrolyte secondary battery separator, nonaqueous electrolyte secondary battery laminated separator, nonaqueous electrolyte secondary battery member, and nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery separator is a porous film containing a polyolefin as a main component. The nonaqueous electrolyte secondary battery separator (i) has a phase difference of 80 nm or less with respect to light having a wavelength of 590 nm in a state where the nonaqueous electrolyte secondary battery separator is impregnated with ethanol and (ii) has a porosity of 30% to 60%. |
| US09508970B2 |
Enclosure for rechargeable batteries
An apparatus comprises a rechargeable battery susceptible to thermal runaway, and a metal enclosure for the battery. The enclosure is configured to mitigate battery failure consequences resulting from thermal runaway. |
| US09508969B2 |
Secondary battery, component for the same and method for manufacturing the same
A secondary battery includes an electrode assembly having an electrode tab; an electrode lead attached to the electrode tab and having at least one lead hole; a pouch case for accommodating the electrode assembly so that the electrode lead is drawn out; and a sealing tape interposed between the electrode lead and the inner surface of the pouch case and having a venting pattern portion formed at a region corresponding to the lead hole. Therefore, when gas is generated inside a pouch case of a secondary battery due to an abnormal circumstance, for example when an overcurrent flows at the secondary battery since a protective circuit does not operate normally, a sealed state of the pouch case is rapidly released, thereby ensuring the safety of the secondary battery in use. |
| US09508967B2 |
Battery-embedded board
A battery-embedded plate includes a base and a battery is present. The base has an accommodation space on a bottom face, and comprises a corner-locating element and two edge-locating elements, each of the two edge-locating elements adjoins to one side of the corner-locating element respectively and two through slots communicated with the accommodation space is defined respectively between each edge-locating element and each side of the corner-locating element. The battery is set in the accommodation space and fixed by the corner-locating element and the two edge-locating elements. The battery is electrically connected with a positive cable and a negative cable respectively, and the two cables are extended out of the accommodation space through the two through slots respectively. |
| US09508964B2 |
Structure for holding voltage detecting terminal
A voltage detecting terminal includes a flat plate-shaped electric contact portion having an insertion hole into which an electrode column of a battery is inserted, and a bent portion formed such that a tip is bent upward with respect to the electric contact portion. The bent portion is provided with a holding portion, and both ends of the holding portion in a plate width direction are expanded in the plate width direction, respectively. The voltage detecting terminal has a lower end surface of the holding portion in a thickness direction abutting against supporting surfaces of the plate and is held by a first housing portion. |
| US09508962B2 |
Battery cell of novel embedded type structure
Disclosed herein is a battery cell including an electrode assembly of a cathode/separator/anode structure, the electrode assembly being impregnated with electrolyte, the electrode assembly being chargeable and dischargeable, a battery case in which the electrode assembly is mounted, the battery case being made of aluminum or an aluminum alloy, and a protective coating layer applied to at least a portion of an outer surface of the battery case, the protective coating layer containing an electrically insulative polymer material. |
| US09508961B2 |
Method for manufacturing light-emitting device
To provide a method for manufacturing a lightweight light-emitting device having a light-emitting region on a curved surface. The light-emitting region is provided on a curved surface in such a manner that a light-emitting element is formed on a flexible substrate supported in a plate-like shape and the flexible substrate deforms or returns. |
| US09508955B2 |
Organic light emitting display device
The present invention relates to an organic light emitting display device. An aspect of the present invention provides an organic light emitting display device comprising a first electrode on a substrate, an organic light emitting layer on the substrate, and a second electrode including at least two layers of which a composition of compensation materials is different on the organic light emitting layer. Another aspect of the present invention provides an organic light emitting display device in which a first electrode includes two or more layers having different compositions of compensation material such that thin and double compensation layers are formed on both surfaces of an organic light emitting layer. |
| US09508953B2 |
Display device
A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided. According to the present invention, a display device and a method of manufacturing the same comprising: a display portion formed by aligning a light-emitting element using an organic light-emitting material between a pair of substrate, wherein the display portion is formed on an insulating layer formed on any one of the substrates, the pair of substrates is bonded to each other with a sealing material formed over the insulating layer while surrounding a periphery of the display portion, at least one layer of the insulating layer is made of an organic resin material, the periphery has a first region and a second region, the insulating layer in the first region has an opening covered with a protective film, the sealing material is formed in contact with the opening and the protective film, an outer edge portion of the insulating layer in the second region is covered with the protective film or the sealing material. |
| US09508950B2 |
Organic light emitting diode
The present specification discloses an organic electroluminescent device including an anode, a cathode, a light emitting layer provided between the cathode and the anode, a first p-type organic material layer provided between the cathode and the light emitting layer, and a first n-type organic material layer provided between the first p-type organic material layer and the light emitting layer. |
| US09508949B2 |
Organic light-emitting device
An organic light emitting device includes a first electrode, a second electrode, and two or more organic material layers provided between the first electrode and the second electrode. The organic material layer includes a light emitting layer, and a mixed layer including one or more hole transfer materials and one or more electron transfer materials. |
| US09508948B2 |
Organic light emitting display device and method of manufacturing the same
Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate in which at least three pixel areas are defined, a first electrode and a hole transporting layer formed on the substrate, an light-emitting material layer formed on the hole transporting layer in each of the pixel areas, and an electron transporting layer and a second electrode formed on the light-emitting material layer. An optical assistant transporting layer is formed on the light-emitting material layer at a position corresponding to one of the pixel areas, and formed of an electron transporting material. Accordingly, provided can be a high-resolution organic light emitting display device that solves an imbalance of electric charges and has an excellent light output efficiency and an enhanced service life. |
| US09508944B2 |
Composite organic-inorganic energy harvesting devices and methods
A hybrid organic-inorganic thin film is provided. The hybrid organic-inorganic thin film comprising: an organic-phase comprising a porous organic nanostructure comprised of an interpenetrating network having at least one dimension between 0.1 and 100 nm; and an inorganic phase at least partially distributed within the porosity of the organic phase. In a first aspect, the organic phase has a first band gap and the inorganic phase has a second band gap different from the first band gap. A method of producing an organic-inorganic energy harvesting device and a device therefrom comprising the hybrid organic-inorganic thin film is provided. |
| US09508943B2 |
Organic light emitting diode display device
An organic light emitting diode display device is disclosed. The organic light emitting diode display device includes an organic light emitting diode array formed on a flexible substrate, a cover film formed to cover the organic light emitting diode array, and a bottom film attached to a lower surface of the flexible substrate. Reliability of the organic light emitting diode display device may be improved by forming a cover film attached to the organic light emitting diode array and a bottom film attached to the lower surface of the flexible substrate on which the organic light emitting diode array is formed using the same material, and forming a moisture absorbent on the bottom film. |
| US09508942B2 |
Liquid crystal photoalignment materials
A charge transporting, liquid crystal photoalignment material comprising a charge transporting moiety connected through covalent chemical bonds to a surface derivatizing moiety, and a photoalignment moiety connected through covalent chemical bonds to a surface derivatizing moiety. |
| US09508938B2 |
Organic compound and photovoltaic device comprising the same
The present invention provides a organic compound of the general structural formula I and photovoltaic device and photovoltaic layer comprising thereof Said organic compound forms rod-dike supramolecules and absorbs electromagnetic radiation in at least one predetermined spectral subrange within a wavelength range from 400 to 3000 nm with excitation of electron-hole pairs. The polycyclic core Cor1, the bridging group B, and the polycyclic core Cor2 form a molecular system selected from the list comprising donor-bridge-acceptor-bridge-donor and acceptor-bridge-donor-bridge-acceptor in which a dissociation of excited electron-hole pairs is carried out. A solution of the organic compound or its salt forms a solid photo voltaic layer on a substrate. |
| US09508934B2 |
Organic film transistor, organic semiconductor film, and organic semiconductor material and use applications thereof
An organic film transistor containing a compound, which is composed of n repeating units represented by Formula (101-1), in a semiconductor active layer is an organic film transistor using a compound having high carrier mobility and high solubility in an organic solvent; where each of R111 to R114 independently represents a hydrogen atom or a substituent; each of Ar101 and Ar102 independently represents a heteroarylene group or an arylene group; V101 represents a divalent linking group; m represents an integer of 0 to 6; when m is equal to or greater than 2, two or more groups represented by V101 may be the same as or different from each other; and n is equal to or greater than 2. |
| US09508929B2 |
Method for making phase change memory cell
A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode. |
| US09508920B2 |
Voltage-controlled magnetic device operating over a wide temperature range
A voltage-controlled spintronic device includes a magnetic layer having an effective anisotropy Keff; a non-magnetic insulating layer; a contact layer; the magnetic layer having an anisotropy switching threshold such that application of a polarization voltage Vmax allows switching of the effective anisotropy Keff from a direction perpendicular to the reference plane to a direction in the reference plane or vice versa, the magnetic layer including a first layer, with thickness tB, having a volume anisotropy KVB; a second layer, with thickness tA, having a surface anisotropy KSA and a volume anisotropy KVA; the surface anisotropy KSA and the volume anisotropies KVA and KVB respecting, over a given operating temperature range: Min(KSA(V=0), KSA(V=Vmax))<−{KVBtB+KVAtA) |
| US09508919B2 |
Nonvolatile magnetic memory device
A nonvolatile magnetic memory device with a magnetoresistance-effect element includes a laminated structure, a first wiring line, and a second wiring line. The laminated structure includes a recording layer in which an axis of easy magnetization is oriented in a perpendicular direction. The first wiring line is electrically connected to a lower part of the laminated structure. The second wiring line electrically connected to an upper part of the laminated structure. A high Young's modulus region is provided on a side surface of the laminated structure. A Young's modulus value of a material of the high Young's modulus region is greater than a Young's modulus value of a material of the recording layer. |
| US09508914B2 |
Magnetic annealing apparatus
Disclosed is a magnetic annealing apparatus including a carrier conveyance region and a workpiece conveyance region. The carrier conveyance region includes: a first mounting table where a carrier is disposed; second mounting tables where carriers convey workpieces from the carrier conveyance region to the workpiece conveyance region; a storage unit; and a carrier conveyance mechanism that performs carrying-out/carrying-in of the carriers. The workpiece conveyance region includes: an aligner device; a workpiece boat; a workpiece conveyance mechanism that conveys the workpieces from the carriers disposed on the second mounting tables to the workpiece boat via the aligner device; a heating unit; a magnetic field generating unit; and a transfer mechanism that transfers the workpieces held by the workpiece boat into the magnetic field generating unit. |
| US09508912B2 |
Thermoelectric conversion device having perovskite crystal including grain domain
A thermoelectric conversion device includes a perovskite film over a substrate and formed with first and second electrodes on the perovskite film, wherein the perovskite film includes a domain having a crystal orientation different from a crystal orientation of a crystal that constitutes the perovskite film. |
| US09508907B2 |
Light emitting device on a mount with a reflective layer
Embodiments of the invention include a semiconductor light emitting diode (LED) attached to a top surface of a mount. A multi-layer reflector is disposed on the top surface of the mount adjacent to the LED. The multi-layer reflector includes layer pairs of alternating layers of low index of refraction material and high index of refraction material. A portion of the top surface in direct contact with the multi-layer reflector is non-reflective. |
| US09508906B2 |
Light emitting device package
A light emitting device package may be provided that includes: a lead frame which includes a first frame and a second frame disposed on both sides of the first frame respectively; a light emitting device which is disposed on the first frame and is electrically connected to the second frame; and a resin body which includes a first resin body which is disposed between the first frame and the second frame, and a second resin body which covers an outer surface of the lead frame. An end of the first frame and an end of the second frame are disposed on an outer surface of the second resin body. |
| US09508904B2 |
Structures and substrates for mounting optical elements and methods and devices for providing the same background
Methods are disclosed including generating a substrate surface topography that includes a mounting portion that is higher than a relief portion that defines a perimeter of the mounting portion. |
| US09508890B2 |
Photovoltaics on silicon
Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material. |
| US09508888B2 |
Solar cell with silicon nitride layer and method for manufacturing same
A solar cell is provided with: a semiconductor substrate; an insulating layer formed of a silicon compound or a metal compound, and having a predetermined pattern over the substrate; and a surface covering layer formed of an amorphous semiconductor, having a same pattern as the insulating layer, and that directly contacts the insulating layer. |
| US09508887B2 |
Methods of forming solar cells
Methods of fabricating conductive patterns over a solar cell structure are provided, in which a patterned resist layer is provided over an anti-reflective coating layer formed over a solar cell structure. The patterned resist layer is used to etch the exposed portion of the anti-reflective coating, and a metal seed layer is provided over the resist layer and the exposed portion of the solar cell structure's surface. The metal seed layer is selectively removed from over the patterned resist layer without removal from the exposed portion of the surface of the solar cell structure. Different thermal conductivities of the patterned resist layer and the solar cell structure's surface facilitate the selective removal of the seed layer from over the resist layer. Also provided are methods of facilitating simultaneous fabrication of conductive patterns over a plurality of solar cell structures using one or more frame structures. |
| US09508883B2 |
Rectangular conductor for solar battery, method for fabricating same and lead wire for solar battery
A rectangular conductor for a solar battery and a lead wire for a solar battery, in which warping or damaging of a silicon crystal wafer is hard to occur at the time of bonding a connection lead wire even when a silicon crystal wafer is configured to have a thin sheet structure, can be provided. A conductor 1 having a volume resistivity equal to or less than 50 μΩ·mm, and a 0.2% yield strength value equal to or less than 90 MPa in a tensile test is formed into a rectangular conductor 10 for a solar battery having a rectangular cross section, and a surface of the rectangular conductor 10 for a solar battery is coated with a solder plating film 13, to provide a lead wire 20 for a solar battery. |
| US09508882B2 |
Solar cell module
A solar cell module includes a solar cell panel including a plurality of solar cells and a bus bar connected to the solar cells, a protective substrate on the solar cell panel, and a spacer part between the solar cell panel and the protective substrate. The spacer part includes an air layer and a spacer surrounding the air layer. |
| US09508880B2 |
Method for processing a minute structure on a surface of the silicon substrate
It is an object to provide a method for processing a silicon substrate that can reduce surface reflectance as much as possible. The method includes a first step of forming a thin film including a metal having higher electronegativity than silicon and having a plurality of openings on a silicon substrate, a second step of soaking the silicon substrate subjected to the first step in a hydrofluoric acid solution containing oxidizer, and a third step of soaking the silicon substrate subjected to the second step in an ammonia aqueous solution containing oxidizer. By performing the steps in the above order, a minute uneven structure is formed on a surface of the silicon substrate to reduce the reflectance. |
| US09508874B2 |
Photovoltaic device and method of manufacture
A photovoltaic module including a dielectric tunneling layer and methods of forming a photovoltaic module with a dielectric tunneling layer. |
| US09508868B2 |
Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. |
| US09508866B1 |
Thin-film transistor element, method for manufacturing same, and display device
A thin-film transistor includes: a gate electrode; a channel layer not adjacent to the gate electrode; a channel protection layer exposing portion of the channel layer; a source electrode contacting the channel layer at portion of an exposed portion of the channel layer; and a drain electrode contacting the channel layer at portion of the exposed portion, in respective order. The channel layer includes oxide semiconductor. Surface of the channel protection layer includes upper surface and side surface extending from the upper surface to the exposed portion. The drain electrode has: a rising portion extending from above the exposed region to the channel layer along the side surface; and an upper surface covering portion continuous with the rising portion and extending onto portion of the upper surface. The upper surface covering portion has a facing portion facing a channel region and being 2.5 μm or less in channel length direction. |
| US09508861B2 |
Semiconductor device
A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode. |
| US09508856B2 |
Thin film transistor
Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm. |
| US09508852B2 |
Radiation-hardened-by-design (RHBD) multi-gate device
The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers. The interlayer has a doping type which is opposite to that of the substrate so that a shunt PN junction is formed between the interlayer and the substrate, and the shunt PN junction has an electrode not connected to the drain so that a part of the charges collected by the shunt PN junction are not output to the drain and are ultimately guided out of the multi-gate devices, thereby weakening the influence of the single-event effect. In comparison with a multi-gate device of prior art, the multi-gate device of the present invention may effectively suppress the sensitivity of the device to single event irradiation in the event that the layout areas of the two types of devices are almost same. |
| US09508850B2 |
Epitaxial block layer for a fin field effect transistor device
Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate. |
| US09508849B2 |
Device having source/drain regions regrown from un-relaxed silicon layer
A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer. |
| US09508844B2 |
Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. |
| US09508842B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with a gate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability. |
| US09508841B2 |
Method and system for a semiconductor device with integrated transient voltage suppression
A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value. |
| US09508839B2 |
Short-gate tunneling field effect transistor having non-uniformly doped vertical channel and fabrication method thereof
The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears as a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region. |
| US09508837B2 |
Semiconductor device and method of manufacturing same
To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy. |
| US09508836B2 |
3-dimensional non-volatile memory device and method of manufacturing the same
A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines. |
| US09508832B2 |
Method of fabricating a semiconductor device
A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer. |
| US09508831B2 |
Method for fabricating vertically stacked nanowires for semiconductor applications
Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes in a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer includes a coating layer coated on an outer surface of a main body formed in the material layer, selectively removing a first portion of the coating layer from the material layers to expose the underlying main body of the material layers while maintaining a second portion of the coating layer remaining on the material layers, laterally etching the main body of the material layers exposed by removal of the coating layer, and selectively growing film layers on the exposed main body of the material layer. |
| US09508827B2 |
Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure. |
| US09508826B2 |
Replacement gate structure for enhancing conductivity
After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed. |
| US09508824B2 |
Method for fabricating a bipolar transistor having self-aligned emitter contact
A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto. |
| US09508823B2 |
Chemical sensor with multiple sensor cells
In a method for manufacturing a chemical sensor with multiple sensor cells, a substrate is provided and an expansion inhibitor is applied to the substrate for preventing a sensitive material to be applied to an area on the substrate for building a sensitive film of a sensor cell to expand from said area. The sensitive material is provided and the sensitive film is built by contactless dispensing the sensitive material to said area. |
| US09508819B2 |
Semiconductor device for compensating internal delay, methods thereof, and data processing system having the same
A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process. |
| US09508818B1 |
Method and structure for forming gate contact above active area with trench silicide
A semiconductor device includes a substrate including an active area; a gate formed on the active area and surrounded by a spacer along a sidewall; a first source/drain contact and a second source/drain contact positioned on opposing sides of the gate and in contact with the active area; a first recess formed in the first source/drain contact and a second recess formed in the second source/drain contact; a gate contact including a conductive material on and in contact with the gate and the spacer; and an insulating liner disposed along a sidewall of the gate contact and in the first recess in the first source/drain contact and the second recess in the second source/drain contact. |
| US09508816B2 |
Low resistance replacement metal gate structure
A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure. Each sacrificial gate structure is then removed forming gate cavities. A high k dielectric material, a metal nitride hard mask and a physical vapor deposited (PVD) amorphous-silicon cap are provided. Vertical portions of the metal nitride hard mask and the high k dielectric material are removed from a portion of each gate cavity. Additional PVD amorphous silicon is then deposited and then all amorphous silicon and remaining metal nitride hard mask portions are removed. A work function portion having a stair-like surface, a diffusion barrier portion, a conductive metal structure and a dielectric cap are then formed into to each of the gate cavities. |
| US09508815B2 |
Semiconductor device and method for manufacturing thereof
A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein. |
| US09508812B2 |
Semiconductor device
A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area. |
| US09508807B2 |
Method of forming high electron mobility transistor
A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features. |
| US09508806B2 |
Electronic device, image display device and sensor, and method for manufacturing electronic device
An electronic device includes a control electrode 11 formed on a substrate 10, an insulating layer 12 covering the control electrode 11, an active layer 13 including an organic semiconductor material, which is formed on the insulating layer 12, and a first electrode 14A and a second electrode 14B formed on the active layer 13, and portions 15 of the first electrode and second electrode in contact with the active layer 13 are modified with an electrode modification material. |
| US09508798B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, an insulating section, and a semiconductor section. The second semiconductor region is provided on the first semiconductor region. A carrier concentration of the first conductivity type of the second semiconductor region is lower than a carrier concentration of the first conductivity type of the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating section is provided around the first semiconductor region and the second semiconductor region. The insulating section is in contact with the second semiconductor region. The semiconductor section is provided around the insulating section. The semiconductor section is not in contact with the first semiconductor region. |
| US09508795B2 |
Methods of fabricating nanowire structures
Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures. |
| US09508792B2 |
Semiconductor device including an electric field buffer layer and method for manufacturing same
An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate. |
| US09508785B1 |
Semiconductor device including a resistor metallic layer and method of forming the same
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer. |
| US09508783B2 |
Display panel and fabrication method thereof
A display panel and fabrication method is provided. The display panel may include a substrate, and the substrate includes a display region and a border region surrounding the display region. The display panel also include a heat transfer pattern formed in the border region of the substrate to transfer and dissipate heat generated during a laser cutting process when forming the display panel. The heat transfer pattern includes at least one metal layer. |
| US09508781B2 |
Method for manufacturing organic EL display and organic EL display
A method for manufacturing an organic electroluminescence display including multilayer structures that are each formed in a respective one of pixel areas in an effective area of a substrate and are each formed by a lower electrode, an organic layer, and an upper electrode, the organic electroluminescence display having a common electrode that electrically connects the pixel areas, the method including the steps of: forming a protective electrode and an outer-peripheral electrode that are electrically connected to the common electrode; forming the multilayer structures; and carrying out film deposition treatment involving electrification of the substrate. |
| US09508778B2 |
Organic light emitting diode display
An organic light emitting device includes: a first substrate; a plurality of electrodes on the first substrate; a pixel definition layer on the plurality of electrodes and including a plurality of openings and respectively exposing the plurality of electrodes; and a spacer on the pixel definition layer, wherein the pixel definition layer includes a first opening and a second opening adjacent to each other along a first direction by an interval for each pixel, and a third opening adjacent to the first opening and the second opening by an interval along a second direction crossing the first direction, and wherein the spacer is at a crossing point of a first imaginary line extending in the first direction and passing between the first opening and the third opening and a second imaginary line extending in the second direction and passing between the first opening and the second opening. |
| US09508776B2 |
Gating device cell for cross array of bipolar resistive memory cells
A gating device cell for a cross array of bipolar resistive memory cells comprises an n-p diode and a p-n diode, wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel, such that the gating device cell exhibits a bidirectional rectification feature. The gating device cell exhibits the bidirectional rectification feature, that is, it can provide a relatively high current density at any voltage polarity in its ON state, and also a relatively great rectification ratio (Rv/2/RV) under a read voltage. Therefore, it is possible to suppress read crosstalk in the cross array of bipolar resistive memory cells to avoid misreading, thereby solving the problem that a conventional rectifier diode is only applicable to a cross array of unipolar resistive memory cells. |
| US09508775B2 |
Solid-state imaging apparatus and manufacturing method of solid-state imaging apparatus
The first face of the pad is situated between the front-side face of the second semiconductor substrate and a hypothetical plane including and being parallel to the front-side face, and a second face of the pad that is a face on the opposite side of the first face is situated between the first face and the front-side face of the second semiconductor substrate, and wherein the second face is connected to the wiring structure so that the pad is electrically connected to the circuit arranged in the front-side face of the second semiconductor substrate via the wiring structure. |
| US09508773B2 |
Solid-state image pickup device
A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity. |
| US09508769B1 |
Semiconductor structure and method of manufacturing the same
Some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate, a radiation-sensing region in the substrate, and a trench in the substrate including a liner over an inner wall of the trench, a FSG layer over the line, an oxide layer over the FSG layer, and a reflective material over the oxide layer. The radiation-sensing region of the semiconductor structure comprises a plurality of radiation-sensing units. The trench of the semiconductor structure separates at least two of the radiation-sensing units. The FSG layer of the semiconductor structure comprises at least 2 atomic percent free fluorine and a thickness of from about 500 to about 1300 angstroms. |
| US09508765B2 |
Photodiode array detector with different charge accumulation time for each light receiving element within one unit
A photodiode array detector used for detecting light which has undergone wavelength separation by a spectroscopic element, the photodiode array detector including: a light receiving element array wherein, taking a plurality of light receiving elements which detect light of the same wavelength range as one unit, a plurality of such units are arrayed in the direction of dispersion of said wavelength; and a charge accumulation time setting unit which sets different charge accumulation times for the plurality of light receiving elements within the one unit. |
| US09508764B2 |
Monolithically integrated antenna and receiver circuit
The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET1, FET2), which has a first electrode, a second electrode, a control electrode, and a channel between the first electrode and the second electrode, and comprising an antenna structure. An electrode is connected to the antenna structure such that an electromagnetic signal which lies in the THz-frequency range and which is received by the antenna structure (1) can be fed into the channel between electrodes and the control electrode is connected to an electrode via a capacitor and/or the control electrode and the first electrode or the control electrode and the second electrode have an intrinsic capacitor such that no AC voltage drop occurs between the control electrode and the first electrode or the second electrode. |
| US09508759B2 |
Semiconductor device and driving method thereof
To reduce adverse effect of variations in threshold voltage. A semiconductor device includes a transistor including a gate connected to one electrode of a capacitor and one terminal of a SW1, a source and a drain one of which is connected to one terminal of a SW2 and one terminal of a SW3 and the other of which is connected to the other terminal of the SW1 and one terminal of a SW4; a first wiring electrically connected to the other terminal of the SW2; a second wiring electrically connected to the other terminal of the SW4; a load including electrodes one of which is connected to one electrode of the capacitor and the other terminal of the SW3; and a third wiring connected to the other electrode of the load. |
| US09508745B1 |
Array substrate and method of fabricating the same
An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape. The array substrate has a simple process, low producing cost, and high product yield. |
| US09508742B2 |
Semiconductor device having switching transistor that includes oxide semiconductor material
One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal. |
| US09508739B2 |
Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member. |
| US09508738B2 |
Semiconductor devices
A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other. |
| US09508737B2 |
Semiconductor device and method of fabricating the same
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer. |
| US09508736B2 |
Three-dimensional charge trapping NAND cell with discrete charge trapping film
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell. |
| US09508734B2 |
Sonos device
A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer. |
| US09508733B1 |
Methods of fabricating embedded electronic devices including charge trap memory cells
A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively. |
| US09508727B2 |
Integrated circuit device and method of manufacturing the same
A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line. |
| US09508726B2 |
Semiconductor device and method of fabricating the same
A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and second impurity regions in each of the active patterns and on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region to the bit line, and a second contact electrically connected to the second impurity region. The second contact includes a vertically-extended portion covering an upper side surface of the second impurity region. |
| US09508725B2 |
Trench to trench fin short mitigation
A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited. |
| US09508720B1 |
Low leakage FinFET
An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that first PMOS transistors are formed in first epitaxial regions on the first plurality of fins, NMOS transistors are formed in second epitaxial regions on the second plurality of fins and second PMOS transistors are formed in third epitaxial regions on the third plurality of fins. In three embodiments, the fins are formed in silicon; the first epitaxial region is silicon germanium; the second region is silicon; and the third region is 1) silicon, 2) silicon carbide, or 3) silicon or silicon carbide on a silicon carbide cladding. In another embodiment, the third epitaxial regions are wide band gap semiconductors formed on wide band gap semiconductor fins. In another embodiment, all the fins and epitaxial regions are wide band gap semiconductors. |
| US09508719B2 |
Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm. |
| US09508717B2 |
Integrated circuit device and repair method thereof
The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer. The IC device also includes a repair circuit configured to apply a negative bias voltage to the substrate of the PMOS transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric layer to neutralize holes caused by negative bias temperature instability (NBTI) effect. The repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor when the PMOS transistor is in an ON state. As such, the disclosed IC device repairs defect caused by NBTI effect in the PMOS transistor and prolongs the lifespan of the PMOS transistor. |
| US09508714B2 |
Multi-gate FETs and methods for forming the same
A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation. |
| US09508712B2 |
Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions. |
| US09508711B2 |
Semiconductor device with bipolar junction transistor cells
A semiconductor device includes a bipolar junction transistor cell including an emitter region which is at least partly formed between mesas of a semiconductor body. The emitter region extends between a first surface of the semiconductor body and an emitter bottom plane. The transistor cell further includes a collector region and a base region that separates the emitter region and the collector region. |
| US09508704B2 |
Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided. |
| US09508700B2 |
Semiconductor device module with solder layer
The present invention relates to a semiconductor device used in power equipment. The semiconductor device includes: a base plate; an insulating substrate mounted on the base plate; a power switching element bonded to the insulating substrate with a solder layer; and the base plate, the insulating substrate, and the power switching element forming a module, a control substrate located above the module. The control substrate includes a variable gate voltage circuit measuring a collector-emitter voltage of the power switching element and changing a gate voltage such that the power switching element is supplied with given target power determined by a product of the collector-emitter voltage and a collector current. |
| US09508699B2 |
Semiconductor package and method for manufacturing the same
A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer. |
| US09508697B2 |
Semiconductor light emitting device and semiconductor light emitting device package including the same
There is provided a semiconductor light-emitting device which includes a light-emitting diode (LED) chip having a first plane on which first and second electrodes are disposed and a second plane disposed opposite to the first plane, first and second solder bumps disposed in bonding areas of the first and second electrodes, respectively, and a protective device electrically connected to the first and second electrodes and mounted on the first plane of the LED chip. The protective device has the substantially same thickness as each of the first and second solder bumps. |
| US09508695B2 |
Method of manufacturing light emitting device
A method of manufacturing a light emitting device includes: disposing a group of electrically conductive members on a support substrate, the group of the electrically conductive members forming a plurality of mounting portions arranged in two or more columns and two or more rows with the mounting portions respectively corresponding to a plurality of light emitting elements; placing the light emitting elements on the group of the electrically conductive members with a bonding member being disposed between the light emitting elements and the electrically conductive members, each of the light emitting elements being shifted from a corresponding one of the mounting portions; and melting the bonding member to mount the light emitting elements respectively on the mounting portions by self-alignment effect generated by the melting of the bonding member. |
| US09508684B2 |
Resin-encapsulated semiconductor device and method of manufacturing the same
A first resin encapsulated body (25) and a second resin encapsulated body (26) are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body (25) includes: a first semiconductor element (2); an external terminal (5); inner wiring (4); and a first resin (6) for covering those components, at least a rear surface of the external terminal (5), a rear surface of the semiconductor element (2), and a surface of the inner wiring (4) are exposed from the first resin (6). The second resin encapsulated body (26) includes: a second semiconductor element (7) having an electrode pad formed on a surface thereof; a second resin (8) for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other. |
| US09508679B2 |
Mounting method
A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding. |
| US09508678B2 |
Method of manufacturing a semiconductor device including applying ultrasonic waves to a ball portion of the semiconductor device
A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion. |
| US09508673B2 |
Wire bonding method
A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad. |
| US09508670B2 |
Semiconductor device including semiconductor chips stacked via relay substrate
A semiconductor device includes a support body provided with a wiring layer that includes a first pad; a first semiconductor chip; a first relay substrate stacked on the first semiconductor chip through a first non-conductive adhesion layer and including a first conductive portion and a first protruding electrode electrically connected to the first conductive portion; a second semiconductor chip stacked on the first relay substrate through a second non-conductive adhesion layer, the first protruding electrode of the first relay substrate penetrating the second non-conductive adhesion layer to be connected to the second semiconductor chip; and a first metal wire formed at the first relay substrate to be connected to the first conductive portion for electrically connecting the first conductive portion with the first pad of the wiring layer of the support body. |
| US09508668B2 |
Conductive contacts having varying widths and method of manufacturing same
A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. |
| US09508666B2 |
Packaging structures and methods with a metal pillar
A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. |
| US09508665B2 |
Method for insertion bonding and device thus obtained
A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion. |
| US09508662B2 |
Optical semiconductor device
A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device.In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line. |
| US09508655B2 |
Method for forming identification marks on refractory material single crystal substrate, and refractory material single crystal substrate
An identification mark formation method for forming an identification mark on a refractory material single crystal substrate that is made of one selected from the group consisting of sapphire, gallium nitride, aluminum nitride, diamond, boron nitride, zinc oxide, gallium oxide, and titanium dioxide is disclosed. The method includes: (a) scanning a principal surface of the refractory material single crystal substrate with a laser beam at a first energy density such that a groove is formed in the principal surface of the refractory material single crystal substrate, thereby forming an identification mark in the principal surface of the refractory material single crystal substrate; and (b) scanning an inside of the groove of the refractory material single crystal substrate with a laser beam at a second energy density that is lower than the first energy density. |
| US09508652B1 |
Direct IC-to-package wafer level packaging with integrated thermal heat spreaders
A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height. |
| US09508645B1 |
Contact pad structure
A contact pad structure includes alternately stacked N insulating layers (N≧6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions. |
| US09508643B2 |
Electronic component
An electronic component includes: a plate-shaped semiconductor element connected to a metallic contacting by a sinter layer; a dielectric layer having a surface metal layer disposed thereon, the dielectric layer being provided in an edge region of the semiconductor element, the edge region being provided with raised areas and depressions by patterning of the dielectric layer and/or the surface metal layer; and the sinter layer covers the edge region with the raised areas and depressions and thereby connects the edge region to the metallic contacting. |
| US09508642B2 |
Self-aligned back end of line cut
Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density. |
| US09508639B2 |
Package-in-substrate, semiconductor device and module
A package-in-substrate includes an exposed pad having a surface that is capable of contacting the outside; a semiconductor chip arranged on a surface opposite to the surface of the exposed pad; a molding resin for molding the semiconductor chip; and a lead frame extending from a side surface of the molding resin and having a leading end portion with a machined shape. The leading end portion of the lead frame is cut to have a cutting angel that is an acute angle formed by an extended straight line of the lead frame with respect to a top surface of a package. |
| US09508638B2 |
Making electrical components in handle wafers of integrated circuit packages
A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond. |
| US09508636B2 |
Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed. |
| US09508635B2 |
Methods of forming conductive jumper traces
Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines. |
| US09508634B2 |
Package structure
A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias. |
| US09508633B2 |
High performance power transistor having ultra-thin package
A field-effect transistor package includes a leadframe with a first linear thickness (150a) and a leadframe pad (151) of a reduced thickness; a first terminal of a field-effect transistor chip (140) attached to the pad and a second and a third terminal remote from the pad; a metal sheet (110) of a second linear thickness (110a) connecting the second transistor terminal to a package terminal; a metal sheet (112) of a third linear thickness (112a) connecting the third transistor terminal to a package terminal; the sum of the first linear thickness (about 0.125 mm) and the second linear thickness (about 0.125 mm) plus attach material (about 0.05 mm) comprising the package thickness (about 0.3 mm). |
| US09508630B2 |
Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP. |
| US09508629B2 |
Memory module in a package
A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. |
| US09508621B2 |
Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer. |
| US09508616B2 |
Method for lower thermal budget multiple cures in semiconductor packaging
A method for forming a multilayer structure comprises the steps of: depositing a first polymerizable layer on a substrate; applying microwave energy to the polymerizable layer while monitoring at least one property of the layer; and, ending the application of microwave energy when the monitored property indicates that the polymerizable layer has reached a desired degree of cure. The property monitored may be optical, e.g., Raman spectrum, or electrical, e.g., dielectric loss. This process control strategy lowers the overall thermal budget, and is especially suitable for curing polymer films on silicon. The method may be used repetitively to cure multiple layers of polymeric material when a thicker film is needed. |
| US09508615B2 |
Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees. |
| US09508611B2 |
Semiconductor inspection method, semiconductor inspection device and manufacturing method of semiconductor element
In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. |
| US09508610B2 |
Inline measurement of molding material thickness using terahertz reflectance
A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector. |
| US09508609B2 |
Fin field effect transistor and method for forming the same
Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology. |
| US09508608B2 |
Monitoring laser processing of semiconductors by raman spectroscopy
A Raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The Raman probe may be coupled to a targeting system of a laser thermal processing system. The Raman probe includes a laser positioned to direct probe radiation through the targeting system to the substrate, a receiver attuned to Raman radiation emitted by the substrate, and a filter that blocks laser radiation reflected by the substrate. The Raman probe may include more than one laser, more than one receiver, and more than one filter. The Raman probe may provide more than one wavelength of incident radiation to probe the substrate at different depths. |
| US09508603B2 |
Formation of nickel silicon and nickel germanium structure at staggered times
A method includes providing a first source/drain contact, providing a second source/drain contact, and surrounding the first and second source/drain contacts with a dielectric material layer. The providing a first source/drain contact and the providing a second source/drain contact are performed one after the other. |
| US09508597B1 |
3D fin tunneling field effect transistor
A method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures and recessing the fin between the gate structures. A first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. A second gap between the gate structures having a larger pitch is filled with a second dielectric layer. The first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap. A source region is formed on the fin in the first gap. A dielectric fills the source region in the first gaps. The second gap is opened by etching the second dielectric layer and the first dielectric layer. A drain region is formed on the fin in the second gap. |
| US09508596B2 |
Processes used in fabricating a metal-insulator-semiconductor field effect transistor
During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET. |
| US09508592B2 |
Semiconductor device and manufacturing method thereof
To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed. |
| US09508587B2 |
Formation of isolation surrounding well implantation
Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials. |
| US09508583B2 |
Article transport carriage
An article transport carriage includes a carriage main body configured to travel along a travel path, a support portion configured to support a bottom surface of an article from below, a projecting and retracting actuator for projecting and retracting the support portion between a projected position and a retracted position, a pressure applying portion located directly above the article supported by the support portion in the retracted position, and a distance changing actuator for changing the distance in the vertical direction between the support portion and the pressure applying portion between a pressure applying distance and a spaced apart distance. |
| US09508582B2 |
Parallel single substrate marangoni module
A substrate drying apparatus for drying a width of a surface of a substrate in a liquid. The substrate drying apparatus has a liquid tank containing the liquid. An injection nozzle is coupled to the liquid tank, the injection nozzle having a continuous knife edge injection surface across the width of the surface of the substrate. A drain is coupled to the injection nozzle, the drain having a continuous drain surface substantially parallel to the continuous knife edge injection surface and across the width of the surface of the substrate. The liquid forms a meniscus between the continuous drain surface and the width of the surface of the substrate. The injection nozzle directs a vapor at the meniscus. |
| US09508580B2 |
Transport device
A transport device includes a large-article drive portion that moves each of a pair of large-article supporting portions between a large-article supporting position and a large-article retracted position, and a small-article drive portion that moves each of a pair of small-article supporting portions between a small-article supporting position and a small-article retracted position. The small-article retracted position is set at a height at which the pair of small-article supporting portions are located above a supported portion supported by the pair of large-article supporting portions, and the pair of small-article supporting portions are provided between the pair of large-article supporting portions in a lateral width direction. |
| US09508577B2 |
Semiconductor manufacturing apparatuses comprising bonding heads
A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled. |
| US09508574B2 |
Process liquid supply apparatus operating method, process liquid supply apparatus and non-transitory storage medium
According to an embodiment of the present disclosure, a process liquid supply apparatus operating method is provided. The method includes filling a filter unit with a process liquid from an upstream side of the filter unit to a downstream side of the filter unit after newly mounting or replacing the filter unit and repeating a depressurization filtering process and a pressurization filtering process for a predetermined number of times. The depressurization filtering process depressurizes the process liquid in the downstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit. The pressurization filtering process pressurizes the process liquid from the upstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit. |
| US09508572B2 |
Bonding device
A boding device includes a light guiding part that guides laser beam oscillated from a laser oscillator, a bonding head that heats a chip with the laser beam, and a bonding head moving part that moves the bonding head between a supply position and a bonding position. The laser oscillator is separated from the bonding head. The light guiding part includes an irradiation barrel that is provided in the vicinity of the bonding position and, a shutter part that is provided in the irradiation barrel, and a light receiving part that is provided in the bonding head and guides the laser beam to the chip. When the bonding head moving part moves the bonding head to the bonding position, the shutter part is opened so that the laser beam from the irradiation barrel is guided to the bonding head through the light receiving part. |
| US09508571B2 |
Method for cleaning base, heat process method for semiconductor wafer, and method for manufacturing solid-state image capturing apparatus
A method for cleaning a base for supporting an object to process in an apparatus configured to perform a heat process, the method comprising a first step of forming an oxide film on the base including silicon carbide, by subjecting the base to a heat process in a gas atmosphere including oxygen, and a second step of, after the first step, subjecting the base to a heat process in a gas atmosphere including steam, wherein the first step is performed for 10 hours at a temperature of 1000° C. or more. |
| US09508568B2 |
Substrate processing apparatus and substrate processing method for performing cleaning treatment on substrate
A special mode has a second rinsing process which supplies a rinsing liquid to a substrate while holding and rotating the substrate with a spin chuck under operating conditions different from those in a first rinsing process in a normal mode. In the second rinsing process, a processing cup is cleaned with the rinsing liquid flown off from the rotating substrate. In the second rinsing process in which the substrate is held by the spin chuck, the rinsing liquid flown off from the substrate is less prone to collide with chuck members. The provision of a mechanism designed specifically for the cleaning of the cup is not required in the special mode. The special mode is a mode executable when a substrate is present inside a chamber, and can be executed in the middle of lot processing. |
| US09508567B2 |
Cleaning jig and cleaning method for cleaning substrate processing apparatus, and substrate processing system
Disclosed is a method of cleaning components of a substrate processing apparatus The components of the substrate processing apparatus are cleaned by using a first cleaning jig including a disk-shaped lower member, and a disk-shaped upper member connected to the lower member and forming a gap between the upper member and the lower member. The lower member of the first cleaning jig is held by the substrate holding unit to rotate the first cleaning jig. The cleaning liquid is ejected toward the first cleaning jig from a bottom side of the first cleaning jig while the first cleaning jig is rotated. The cleaning liquid flows out toward outside of the first cleaning jig via the gap between the upper member and the lower member by a centrifugal force, and the components of the substrate processing apparatus are cleaned by the cleaning liquid that has flowed out. |
| US09508565B2 |
Semiconductor package and method of manufacturing the same
The semiconductor package according to an exemplary embodiment includes: a substrate having a plurality of circuit layers and connection pads which are provided between a plurality of insulating layers; a plated tail part of which one end is electrically connected to the connection pad; a dicing part provided in contact with the other end of the plated tail part; a molded part provided on the substrate; and molded part vias provided on the connection pads and penetrating through the molded part. |
| US09508563B2 |
Methods for flip chip stacking
A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip. |
| US09508562B2 |
Sidewall image templates for directed self-assembly materials
In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask. |
| US09508559B2 |
Semiconductor wafer and method for manufacturing semiconductor device
A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner. |
| US09508558B2 |
Wafer treatment solution for edge-bead removal, edge film hump reduction and resist surface smooth, its apparatus and edge-bead removal method by using the same
The present disclosure provides a wafer treatment solution for edge-bead removal, edge film hump reduction and resist surface smooth. The wafer treatment solution includes a solution and a fluorine-containing additive mixed in the solution. The fluorine-containing additive has a following formula (I): Rf—X—(CH2CH2O)m—R1 (I); or a following formula (II): An apparatus and a method by using the wafer treatment solution are also provided herein. |
| US09508556B1 |
Method for fabricating fin field effect transistor and semiconductor device
A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes steps as follows. A gate stack is formed over a substrate having a semiconductor fin. Recesses are formed in the semiconductor fin beside the gate stack. A pre-clean process is performed to remove native oxides on surfaces of the recesses. After the pre-clean process, a selectivity proximity push process is performed using a fluorine-containing gas and a first hydrogen gas to the recesses. Strained layers are formed in the recesses. |
| US09508552B1 |
Method for forming metallic sub-collector for HBT and BJT transistors
A heterojunction bipolar transistor having an emitter, a base, and a collector, the heterojunction bipolar transistor including a metallic sub-collector electrically and thermally coupled to the collector wherein the metallic sub-collector comprises a metallic thin film, and a collector contact electrically connected to the metallic sub-collector. |
| US09508547B1 |
Composition-matched curtain gas mixtures for edge uniformity modulation in large-volume ALD reactors
Disclosed are methods of performing film deposition. The methods may include volumetrically isolating a first process station from a second process station by flowing a curtain gas between them, and igniting first and second plasmas supported by first and second plasma feed gases, while flowing the curtain gas, to cause film deposition at the first and second process stations. The curtain gas and the first and second plasma feed gases may each include a high-breakdown voltage species that may be molecular oxygen. The high-breakdown voltage species may have a breakdown voltage of at least about 250 V for a pressure-distance (pd) value of 3.4 Torr-cm. The curtain gas may have a higher concentration of the high-breakdown voltage species than the first and second plasma feed gases. The high-breakdown voltage species may make up about 5-50% of the curtain gas by mole fraction. The high-breakdown voltage species may be molecular oxygen. |
| US09508545B2 |
Selectively lateral growth of silicon oxide thin film
Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the substrate having terminal hydroxyl groups. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma and H2O soak in order to perform an additional silylation. Further methods include catalyzing the exposed surfaces using a Lewis acid, directionally inactivating the exposed first and second surfaces and deposition of a silicon containing layer on the sidewall surfaces. Multiple plasma treatments may be performed to deposit a layer having a desired thickness. |
| US09508544B2 |
Semiconductor device and method for manufacturing same
This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a). |
| US09508542B2 |
Arrangement for the production of structured substrates
An arrangement for producing structured substrates is provided, which includes a device for applying layer systems including a device for applying liquid materials to rotating substrates, a housing, a rotating holder for the substrate to be coated, a feeder for liquid materials to be applied, and a collection device having multiple removal contraptions for liquid materials that do not remain on the substrate. The housing of the device is filled with an inert gas, in particular dried, molecular nitrogen, noble gas, or a mixture thereof. The additional receptacles and conduits of the arrangement for producing structured substrates are gas-tight and are designed such that an inert molecular nitrogen or noble gas atmosphere is created above the liquid contents thereof. The collection device has various collection zones in which different liquid materials can be selectively collected and selectively removed via the associated removal contraption. |
| US09508541B2 |
Apparatus and method for treating substrate
Provided is a substrate treatment apparatus. The substrate treatment apparatus includes a load port on which a carrier accommodating a plurality of substrates to which a back-ground wafer is attached to a mounting tape fixed to a frame ring is placed, a plasma treatment unit supplying plasma to treat a top surface of the wafer, and a substrate transfer unit transferring the substrate between the carrier and the plasma treatment unit. |
| US09508537B2 |
Photo-dissociation of proteins and peptides in a mass spectrometer
A method of mass spectrometry is disclosed comprising directing first photons from a laser onto ions located within a 2D or linear ion guide or ion trap. The frequency of the first photons is scanned and first photons and/or second photons emitted by the ions are detected. The ions are then mass analyzed using a Time of Flight mass analyzer. |
| US09508536B2 |
Chemical sampling and detection methods and apparatus
This invention describes a sample collection and desorption device and method that collects residues of explosives and other chemicals from a surface and then introduces them into a detector. The desorption method and device include introducing additional chemicals while heating up the sample collector, thus, the collected sample may be converted via a chemical reaction or a catalytic process. The detector can be an ion mobility spectrometer or mass spectrometer. |
| US09508535B2 |
Ion-mobility spectrometer including a decelerating ion gate
An ion mobility spectrometer having an ion source for generating ions; an ion detector for recording ions, and a number of substantially flat diaphragm electrodes arranged substantially perpendicular to a straight system axis that passes through the apertures in said diaphragms, with the diaphragms being arranged in a series of cells with each cell including an entrances and an exit diaphragm and a short region in between. The exit diaphragm of one cell is identical to the entrance diaphragm of the next cell, and the cells of said ion mobility spectrometer are grouped into three parts: an ion-beam forming region, an ion analyzing region, and a decelerating ion gate. |
| US09508532B2 |
Magnetron plasma apparatus
A magnetron plasma apparatus boosted by hollow cathode plasma includes at least one electrically connected pair of a first hollow cathode plate and a second hollow cathode plate placed opposite to each other at a separation distance of at least 0.1 mm and having an opening following an outer edge of a sputter erosion zone on a magnetron target so that a magnetron magnetic field forms a perpendicular magnetic component inside a hollow cathode slit between plates and, wherein the plates and are connected to a first electric power generator together with the magnetron target to generate a magnetically enhanced hollow cathode plasma in at least one of a first working gas distributed in the hollow cathode slit and a second working gas admitted outside the slit in contact with a magnetron plasma generated in at least one of the first working gas and the second working gas. |
| US09508526B2 |
Top opening-closing mechanism and inspection apparatus
A top opening-closing mechanism for opening and closing a top of a container including a container body and the top includes a rolling element rotatably provided at the top and positioned on the outside of the container body in a planar view, a rail, a jack for lifting the rail, and a top resting table disposed adjacent to the container and mounting the top thereon. When the top is opened, the jack lifts the rail, the rail lifts the rolling element from below, and thereby the top is lifted up from the container body. Then, the rolling element rolls on the rail and the top resting table to move the top from above the container body to the top resting table. |
| US09508524B2 |
Radiation generating apparatus and radiation imaging apparatus
A radiation generating apparatus of the present invention includes an envelope 1 including a first window 2 allowing radiation to pass; a radiation tube 10 that is accommodated in the envelope 1, and includes a second window 15 allowing radiation to pass, at a position opposite to the first window 2; a radiation passing hole 21 that is thermally connected to the second window 15 and communicates with the second window 15; and a radiation shielding member 16 protruding from the second window 15 toward the first window 2. In this apparatus, a thermally conductive member 17 having a higher thermal conductivity than the radiation shielding member 16 is connected to an outer periphery of the protruding portion of the radiation shielding member 16. The simple configuration can shield unnecessary radiation, and cool the target, while facilitating reduction in weight. |
| US09508518B2 |
Fuse unit
A first battery connecting end, an alternator connecting end and a second battery connecting end of a circuit body are located at an upper surface portion of a unit body. |
| US09508516B2 |
Thermal trip device having a current redirecting linking element, switching device, thermal magnetic circuit breaker and method for protecting an electric circuit
A thermal trip device, of a thermal magnet circuit breaker is disclosed for protecting an electrical circuit from damage by overload, a switching device and a thermal magnetic circuit breaker including at least the thermal trip device are disclosed. In at least one embodiment, the thermal trip device includes at least a bimetal element arranged with a first end at a current conductive element to conduct electrical current and arranged with a second end at a tripping slide adapted to interrupting a current flow. The at least a bimetal element is connectable with a linking element extending between the bimetal element and the current conductive element to redirect the electrical current at least partially. Furthermore, a method is disclosed for protecting an electric circuit from damage by overload by use of the thermal trip device of a thermal magnet circuit breaker. |
| US09508510B2 |
Mobile conducting unit for a breaker, including a spring for accelerating the separation of arc contacts
A disconnector (1) including a movable conductive unit (6) comprising a main electrically conductive body (9) has a main contact (4b) as well as an arcing contact (5b). According to the invention, the unit (6) further comprises a secondary body (14) mounted to move in sliding relatively to the main body (9) along a movement direction (11) of the unit (6), the secondary body (14) being designed to be connected to a connection point (22) of a drive device of the unit (6), the unit further comprising resilient return means (16) interposed between the bodies (9, 14), the switchgear being designed so that during an opening operation the resilient return means (16) can firstly store energy as a result of the secondary body (14) moving relative to the main body (9), and can then release the stored energy in order to cause the main body (9) to accelerate. |
| US09508509B2 |
Contact device having arc root movement promotion portion, and electromagnetic switch in which the contact device is used
A contact device includes a pair of fixed contacts fixedly disposed inside an arc extinguishing chamber and maintaining a predetermined interval from each other; a movable contact disposed to contact to and separate from the pair of fixed contacts; and an arc root movement promotion portion formed on the movable contact to promote a movement of root of arc in a direction away from the fixed contacts. The root of arc is generated when the movable contacts are opened and separated from the pair of fixed contacts. |
| US09508507B2 |
Gas insulated electrical equipment
Gas insulated electrical equipment includes: a metal enclosure having an insulating gas introduced therein; a conductor that is accommodated inside the metal enclosure and to which voltage is applied; and an insulating and supporting member insulating and supporting the conductor relative to the metal enclosure. The conductor is circumferentially covered with a dielectric film, and furthermore, a nonlinear resistance film provided on the dielectric film and having a nonlinear volume resistivity decreasing when the nonlinear resistance film is acted on by an electric field higher than a critical value. |
| US09508499B2 |
Recreational vehicle beam switch assembly
A switch assembly (108) includes a housing (202), a switch (204), a lock mechanism (206), and an input element (208). The switch (204) is disposed within the housing (202) and configured to translate, along a first axis (212), between a first switch position and a second switch position. The lock mechanism (206) is disposed within the housing (202) and configured to translate, along a second axis (216) that is parallel to the first axis (212), between an unlock position and a lock position. The input element (208) is coupled to the switch (204) and the lock mechanism (206) and is movable relative to the housing (202). The input element (208) is adapted to receive an input force and is configured, upon receipt thereof to selectively and simultaneously move the switch (204) and the lock mechanism (206) between the first and second switch positions and the unlock and lock positions, respectively. |
| US09508498B2 |
Electronic switching module for a power tool
An electronic power apparatus includes a housing, a pair of input power pins, a pair of output power pins, power components arranged to modulate a supply of power from the input power pins to the output power pins, and a user-actuated input unit providing an analog signal indicative of a desired power output level of the output power pins. A control unit of the electronic power apparatus receives the analog signal from the user-actuated input unit. The control unit includes a controller to control a switching operation of the power components based on the analog signal, and an input detection unit to generate an ON/OFF signal to turn on the controller based detection of a prescribed change in the analog signal indicative of an initial actuation of the user-actuation unit. |
| US09508490B2 |
Electronic component fabrication method using removable spacers
An electronic component and method for manufacture thereof is disclosed. A plurality of electrodes are positioned in stacked relation to form an electrode stack. The stack may include as few as two electrodes, but more may be used depending on the number of subcomponents desired. Spacing between adjacent electrodes is determined by removable spacers during fabrication. The resulting space between adjacent electrodes is substantially filled with gaseous matter, which may be an actual gaseous fill, air, or a reduced pressure gas formed through evacuation of the space. Further, adjacent electrodes are bonded together to maintain the spacing. A casing is formed to encapsulate the stack, with first and second conducting surfaces remaining exposed outside the casing. The first conducting surface is electrically coupled to a first of the electrodes, and the second conducting surface is electrically coupled to a second of the electrodes. |
| US09508488B2 |
Resonant apparatus for wireless power transfer
Provided is a bulk acoustic resonator (BAR)-based resonant structure in relation to electric and radio technologies, and more particularly, to a wireless power transmission system. A resonant apparatus for wireless power transmission may include a conducting loop, and a high quality capacitor. The high quality capacitor may include a metacapacitor including a thin piezoelectric layer disposed between two metal electrodes. The metacapacitor may be disposed between two dielectric layers of which central portions are etched, and the conducting loop may be disposed on an upper layer of the two dielectric layers. |
| US09508487B2 |
Systems and methods for limiting voltage in wireless power receivers
This disclosure provides systems, methods, and apparatus for the limiting of voltage in wireless power receivers. In one aspect, an apparatus includes a power transfer component configured to receive power wirelessly from a transmitter. The apparatus further includes a circuit coupled to the power transfer component and configured to reduce a received voltage when activated. The apparatus further includes a controller configured to activate the circuit when the received voltage reaches a first threshold value and configured to deactivate the circuit when the received voltage reaches a second threshold value. The apparatus further includes an antenna configured to generate a signal to the transmitter that signals to the transmitter that the received voltage reached the first threshold value. |
| US09508484B2 |
Planar transmitter with a layered structure
A planar transmitter, particularly an intrinsically safe transmitter, having a layer structure having a first circuit and at least a second circuit, wherein the first circuit and the second circuit are galvanically separated from one another by means of at least one insulation layer. The transmitter has a first magnetic layer and a second magnetic layer, wherein the first magnetic layer delimits a first side of the layer structure, and the second magnetic layer delimits a second side of the layer structure, wherein the first magnetic layer 4a and the second magnetic layer are separated from one another and can be assigned to different potential groups. |
| US09508481B1 |
Transformer access apparatus
A method and apparatus for providing temporary secure electric cable access to a terminal of a transformer mounted on a pad; the apparatus includes: 1) at least one riser for supporting an end of the transformer a distance above the pad thereby creating a gap between the pad and the transformer, the distance being sufficient to allow axial passage of the cable through the gap; 2) a barrier shaped for abutting engagement with the transformer and sized to cover the gap; 3) a cable access portal disposed through the barrier; the cable access portal being sized to permit axial passage of the cable; and 4) a barrier lock removably mounted to the barrier for removably securing the barrier to the transformer. |
| US09508480B2 |
Vertical slow-wave symmetric inductor structure for semiconductor devices
A vertical inductor structure in a semiconductor device includes a plurality of vertically oriented spirals that produce magnetic field in a dielectric material above the surface of a semiconductor substrate thereby preventing any eddy currents from propagating in the substrate. An inductor shield structure is also provided. The inductor shield structure is formed over the substrate surface and between an inductor such as the vertical inductor structure or other inductor types and also prevents eddy currents from being induced in the substrate. The inductor shield may surround the inductor to various degrees. |
| US09508479B1 |
Method for in-situ magnetization or degaussing of generator rotor
A method for in-situ magnetization of a generator rotor is provided. The generator has a stator and the rotor is located inside the stator. An air gap is formed between an outer radial portion of the rotor and an inner radial portion of the stator. The rotor has a plurality of excitation windings and a plurality of permanent magnets. The method includes the step of applying a current to the excitation windings, and the current is greater than a normal excitation current. A maintaining step maintains the current for a time period sufficient to magnetize the permanent magnets. The magnetization of the permanent magnets occurs on the rotor in-situ and while the rotor is inside the stator. |
| US09508478B1 |
Diamagnetic levitation system for sport field use in a stadium
A diamagnetic levitation system for levitating users to a levitation surface upon which they may engage in sports and other activities under relatively weightless conditions in a dome-shaped structure. Superconducting magnet segments are connected in series to form a superconducting magnet segment assembly. A plurality of these superconducting magnet segment assemblies form the diamagnetic levitation system. The diamagnetic levitation system not only generates the levitation surface to which players or other users are levitated but also confines them within the boundaries of the levitation surface. The magnetic field strength of the diamagnetic levitation system is self-terminating so that spectators viewing the players are not affected by the levitating magnetic field. |
| US09508476B2 |
Electromagnetic coil, method of manufacturing electromagnetic coil, and electromagnetic actuator
An electromagnetic coil includes a conductor winding 12a formed by winding a conductor 12b a plurality of times about a predetermined axis, and a ceramic layer 12c formed through thermal spraying on an axial end surface of the conductor winding 12a, and having a flattened surface. A maximal value t12 of thickness of the ceramic layer 12c is set to three times or less a maximal value t11 of depth of the recesses formed at the surface of turns of the conductor 12b at the axial end surface. |
| US09508475B2 |
Magnetic multilayer pigment flake and coating composition
The present invention provides a magnetic multilayer pigment flake and a magnetic coating composition that are relatively safe for human health and the environment. The pigment flake includes one or more magnetic layers of a magnetic alloy and one or more dielectric layers of a dielectric material. The magnetic alloy is an iron-chromium alloy or an iron-chromium-aluminum alloy, having a substantially nickel-free composition. The coating composition includes a plurality of the pigment flakes disposed in a binder medium. |
| US09508471B2 |
Material with improved conductivity properties for the production of composite parts in combination with a resin
The invention relates to a material (I) adapted for the production of composite parts by a process in which a thermoplastic or thermosetting matrix is diffused within said material, comprising at least one sheet (1) of unidirectional carbon fibers (2) associated on at least one of its faces with at least one conductive component (5) associated or integrated with a permeable layer (3a, 3b, 10) in a thermoplastic material or in a mixture of thermoplastic or thermosetting materials, said permeable layer being in the form of a fabric, a powder, a porous film, a knit, or, preferably, a non-woven (3a, 3b, 10),a process for fabricating composite parts using such a material and the composite parts that can be obtained by such a process. |
| US09508470B2 |
Vibration damage repair in dynamoelectric machines
Embodiments of the disclosure can include a method for reducing or repairing vibration-caused damage in a stator bar, and a dynamoelectric machine resulting therefrom. The method for reducing vibration-caused damage in a stator can include applying, from within a ventilation slot of a stator core, a liquid based vibration-absorbing material onto a side ripple spring, the side ripple spring being in contact with a stator bar and the stator core; and allowing the liquid based vibration-absorbing material to cure, wherein the cured vibration-absorbing material remains in contact with the side ripple spring for absorbing stator vibrations. |
| US09508467B2 |
Cable for integrated data transmission and power supply
A cable for integrated data transmission and power supply includes an insulative tube having a hollow chamber; an outer knitted shield disposed on an inner wall surface of the insulative tube; a first signal wire arranged inside the hollow chamber and including a plurality of first signal core lines and an inner knitted shield covering an outer thereof; a second signal wire penetrating through the hollow chamber and using the first signal wire as a center to be arranged at one side of the first signal wire; and a power wire penetrating through the hollow chamber and using the first signal wire as a center to be arranged at another side of the first signal wire and opposite from the second signal wire. |
| US09508466B2 |
High-frequency electric wire, manufacturing method thereof, and wire harness
A high-frequency electric wire is provided with a conductor which formed by compressing multiple wire strands, each of which is obtained by coating an outside of a wire rod made of insulating resin with a metal layer, and a sheath provided on the conductor. Each of the wire strands of the conductor is compressed in such a way that a deformation ratio of the wire strand exceeds 0% and is 20% or less. The compression is performed, for example, during bundling and sheathing of the multiple wire strands. |
| US09508465B2 |
Reinforced wiring unit and sealing structure
Sealing performance between a sealing member and a reinforcing plate adhered to a wiring unit is prevent from being deteriorated. An FPC 1 is integrated with a sealing member 2, and a cover 3 is attached to a front end portion. On upper and lower surfaces of the FPC 1, reinforcing plates 12 each having a shape of a rectangular flat plate are arranged and adhered in an opposing manner interposing the FPC 1. The sealing member 2 is formed of elastic material such as rubber, and is fixedly attached to the FPC 1 such that the sealing member 2 covers the reinforcing plates 12 adhered to the upper and lower surfaces of the FPC 1 together with the FPC 1 located along front edges and rear edges of the reinforcing plates 12. |
| US09508458B2 |
Semiconductor memory device and operating method thereof
A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a DRAM memory cell; a plurality of fuses suitable for storing repair information for replacing failed first memory cells with corresponding second memory cells; a normal operation unit suitable for accessing and refreshing one or more of the first and second memory cells according to the repair information during a normal mode; and a repair operation unit suitable for providing the repair information from the fuses to the third memory cells during a boot-up mode, and for providing the repair information from the third memory cells to the normal operation unit and for refreshing the third memory cells during a normal mode. |
| US09508456B1 |
Self repair device and method thereof
A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array. |
| US09508449B2 |
Liquid crystal display and bidirectional shift register device thereof
A liquid crystal display and its bidirectional shift register device including N stages of shift registers are provided. An ith stage shift register of the shift registers includes a pre-charge unit, a pull-up unit and a pull-down unit. The pre-charge unit outputs a pre-charge signal according to outputs of (i−2)th and (i+2)th stage shift registers. The pull-up unit outputs a scan signal. A first discharge unit of the pull-down unit determines whether to pull the scan signal down to a reference voltage potential according to the pre-charge signal and a first voltage-dividing signal associated with a first level signal. A second discharge unit of the pull-down unit determines whether to pull the scan signal down to the reference voltage potential according to the pre-charge signal and a second voltage-dividing signal associated with a second level signal. |
| US09508447B2 |
Non-volatile memory
A non-volatile memory including a substrate, a floating gate transistor, a select transistor and a stress-releasing transistor. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. |
| US09508444B2 |
3D non-volatile memory device and method for operating and fabricating the same
A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line. |
| US09508442B2 |
Non-volatile semiconductor storage device
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. |
| US09508438B2 |
Semiconductor memory device, memory system having the same and operating method thereof
An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage. |
| US09508433B2 |
Non-volatile memory cell
The invention concerns a memory cell comprising: first and second resistive elements (202, 204), at least one of which can be programmed to adopt at least two resistive states (Rmin Rmax); the first resistive element (202) being coupled between a first storage node (206) and a first intermediate node (208), the second resistive element (204) being coupled between a second storage node (210) and a second intermediate node (212); a transistor (220) coupled between the first and second intermediate nodes; and a control circuit arranged to activate the transistor while a second supply voltage (VDD, GND) is being applied to the first or second storage node to generate a programming current in a selected direction through the first and second resistive elements in order to program the resistive state of at least one of the elements. |
| US09508428B2 |
Vertical type semiconductor device, fabrication method thereof and operation method thereof
A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure. |
| US09508424B2 |
Nonvolatile memory and programming method using third latch for verification read results
In a program operation a plurality of memory cells are programmed depending on data stored in first and second data latches. Verification read operations are performed for the plurality of memory cells using different verification voltages respectively corresponding to different program states and collecting verification read results of the verification read operations. The first data latches and the second data latches are updated depending on the collected verification read results. |
| US09508420B1 |
Voltage-aware adaptive static random access memory (SRAM) write assist circuit
Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level. |
| US09508412B2 |
Semiconductor memory apparatus
A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage. |
| US09508409B2 |
Apparatuses and methods for implementing masked write commands
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein. |
| US09508408B2 |
Adjustment of write timing in a memory device
A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. |
| US09508402B2 |
Readout device, dual-function readout device, and detecting circuit thereof
A readout device includes a plurality of detecting circuits arranged in rows and columns to form a detecting array, and an output module. Each of the detecting circuits includes two transistors for generating a detection signal associated with impedance at a target site. Through selection of the rows and the columns of the detecting circuits, the output module outputs an output voltage signal having a magnitude positively correlated with magnitude of a selected one of the detection signals received from the detecting circuits. |
| US09508400B1 |
Storage device and operating method thereof
A storage device includes a memory controller suitable for outputting a program command or a read command; and a memory device suitable for performing a program operation in response to the program command, and immediately performing a read operation when the read command is received during the program operation. |
| US09508399B1 |
Residual capacitance performance booster
In some examples, a method includes determining, by a processor of a controller of a data storage device, that a voltage level of a capacitor in the data storage device is above a threshold voltage value, wherein the data storage device includes a capacitor circuit, and wherein the capacitor circuit includes the capacitor. The method further includes controlling, by the processor, the capacitor circuit to cause the capacitor to provide power to circuitry associated with memory devices of the data storage device along with power provided by a host device operably connected to the data storage device. |
| US09508398B1 |
Voltage generation circuit, semiconductor memory device including the same, and method for driving the same
A semiconductor memory device includes a voltage generation unit suitable for selecting one of the voltages which are supplied to a first and a second source voltage terminals, as a source voltage based on a driving mode signal, and generating a bit line precharge voltage by dividing the source voltage according to a resistance ratio determined based on the driving mode signal; a sense amplifier driving unit suitable for receiving the bit line precharge voltage based on a bit line precharge signal and a sense amplifier control signal, and providing a driving voltage through a pull-up power line and a pull-down power line; and a bit line sense amplifier suitable for sensing and amplifying data of a bit line pair by using the driving voltage supplied through the pull-up power line and the pull-down power line. |
| US09508393B1 |
Hard disk drive enclosure base with a helium sealed gasket
A sealing gasket sheet and a storage drive are provided. The sealing gasket sheet includes a first adhesive layer, a metal layer disposed adjacent to the first adhesive layer, and a second adhesive layer disposed adjacent to the metal layer. The storage drive includes an enclosure formed by a storage drive base and a cover with the sealing gasket sheet between the storage drive base and the cover. |
| US09508390B2 |
Trick play in digital video streaming
System and methods for improved playback of a video stream are presented. Video snippets are identified that include a number of consecutive frames for playback. Snippets may be evenly temporally spaced in the video stream or may be content adaptive. Then the first frame of a snippet may be selected as the first frame of a scene or other appropriate stopping point. Scene detection, object detection, motion detection, video metadata, or other information generated during encoding or decoding of the video stream may aid in appropriate snippet selection. |
| US09508389B2 |
System, method, and apparatus for embedding personal video recording functions at picture level
Described herein are system(s), method(s), and apparatus for embedding personal video recorder functions at the picture level. In one embodiment, there is presented a computer readable medium for storing a data structure. The data structure comprises a picture header and at least one command following the picture header. |
| US09508388B2 |
Method and apparatus for processing motion video
The present invention relates to a method for preparing presentation of recorded motion video. The method preparing and sending a request for recorded video that originates from a specific video source, receiving a video information message including data relating to characteristics of a plurality of motion video recordings captured by the video source, wherein the received characteristics of each motion video recording includes a recording identity, a video quality value, a media address, an indication of start time and end time for the recording, and generating a motion video play scheme based at least on said video quality value, said indication of start time, and said indication of end time for each motion video recording. |
| US09508387B2 |
Flick intel annotation methods and systems
Video content is a time varying presentation of scenes or video frames. Each frame can contain a number of scene elements such as actors, foreground items, background items, or other items. A person enjoying video content can select a scene element by specifying a screen coordinate while the video content plays. Frame specification data identifies the specific frame or scene being displayed when the coordinate is selected. The coordinate in combination with the frame specification data is sufficient to identify the scene element that the person has chosen, information about the scene element can then be presented to the person. An annotation database can relate the scene elements to the frame specification data and coordinates. |
| US09508386B2 |
Method and apparatus for synchronizing audio and video signals
A method, apparatus and computer program product are provided to synchronize audio signals with video images that are replayed with a modified motion. In a method, a trajectory is determined for each audio object of an audio signal. The method also determines each of the audio objects to be a transient or non-transient object. The method also causes a respective audio object to be differently extended depending upon whether the audio object is determined to be a transient object or a non-transient object, thereby synchronizing video signals that are to be played back with a predefined motion. The method causes the respective audio object to be differently extended by splitting the transient object into transient segments, inserting silent segments therebetween and maintaining the trajectories of the transient object and/or by repeating the non-transient object with a trajectory that varies based on the predefined motion of the video signals. |
| US09508384B2 |
Automatic generation of video from structured content
Apparatus for generation of playable media from structured data, comprises a structured data reading unit for reading in of content of a first structure, a transformation unit for transforming said content into a second structure, said transformation comprising incorporating media play instructions, and a rendering unit for rendering content from the second structure using said media play instructions to generate playable media from the content. |
| US09508382B2 |
Method of performing read/write process on recording medium, parameter adjustment method, storage device, computer system, and storage medium employing the methods
A method and apparatus for performing a read/write process on a recording medium having a defect, the method including determining an area of a recording medium, in which a defect, greater than a first set threshold, occurring in units of tracks, to be a massive defective area; adjusting a first parameter representing a logical track length, based on a size of a defect occurring in each track included in the massive defective area; and performing the read/write process on the recording medium by using the adjusted first parameter. |
| US09508380B2 |
Enclosure for reading an optical medium at an input port
Various devices and systems may benefit from enhanced reading of optical media. For example, certain computer systems may benefit from array reading of optical media. An apparatus may include, for example, an array of optical sensors. The array of optical sensors may be configured to read a plurality of parallel linear strips of data from an optical medium. |
| US09508378B2 |
Optical disk and optical disk reproduction device for reproducing same
An optical disk and an optical disk reproduction device for reproducing the same are provided. The optical disk including at least one layer comprises an information storage area for storing information on the optical disk and a data area for storing data, wherein the information storage area stores information on the amount of reflection and thickness of each of a plurality of layers, and transmission speed information on a plurality of areas which constitute the data area. |
| US09508377B2 |
Hologram recording and reproducing device, and angular multiplexing recording and reproducing method
A hologram recording and reproducing device and an angular multiplexing recording and reproducing method capable of detecting an angular error signal for which, in a two-beam angle multiplexing method, high-speed reproducing can be achieved with a superior recovered signal. A branch element branches a light beam, emitted from a light source, into a signal light and a reference light. Angle-variable elements modify the incident angle of the reference light that is incident to the optical information recording medium. A spatial light modulator adds information to the signal light; and an objective lens radiates the signal light to the optical information recording medium. An imaging element detects diffracted light generated from a recording region when the reference light is radiated upon the optical information recording medium; a detection system detects at least two angular error signals for controlling the angle-variable elements; and switching is performed between the two angular error signals. |
| US09508374B2 |
Enlarged substrate for magnetic recording medium
A hard disc drive (HDD) with an enlarged magnetic recording disc. In some embodiments, a base deck and top cover are arranged to provide an HDD housing with a 2½ inch form factor or a 3½ inch form factor. A magnetic recording disc is supported for rotation within the housing. A data transducer is controllably advanced across a recording surface of the magnetic recording disc to write data to the recording surface, and a printed circuit board assembly (PCBA) affixed to an external surface of the base deck incorporates control electronics to provide write signals to the data transducer during the writing of data to the recording surface. The disc has an outer diameter of at least 67 millimeters, mm for the 2½ inch form factor housing and has an outer diameter of at least 97 mm for the 3½ inch form factor housing. |
| US09508372B1 |
Shingle magnetic writer having a low sidewall angle pole
A method and system provide a shingle magnetic write transducer. The transducer has an air-bearing surface (ABS) and includes a main pole and at least one coil. The coil(s) are configured to energize the main pole. The main pole includes a leading surface, a trailing surface, and a plurality of sides between the leading surface and the trailing surface. At least one of the plurality of sides form a sidewall angle with a down track direction. The sidewall angle is less than thirteen degrees and is at least zero degrees. In some aspects, the sidewall angle is less than a maximum skew angle for the data storage system. |
| US09508369B2 |
Defining a maximum sequential write duration for a data storage device utilizing heat-assisted recording
A maximum write duration is determined for first and second heat-assisted write transducers of a data storage device. Exceeding the duration results in thermal degradation of the first and second write transducers. A request to write data to a heat-assisted recording medium is received. In response to a time to fulfill the request exceeding the maximum write duration, the data is divided into portions such that a respective writing of each of the portions does not exceed the maximum write duration. Writing successive ones of the portions to the heat-assisted recording medium involves alternating between the first and second write transducers. |
| US09508364B1 |
Perpendicular magnetic recording (PMR) writer with hybrid shield layers
A PMR writer is disclosed with an all wrap around (AWA) shield design in which one or more of the leading shield, trailing shield, and side shields are comprised of a composite wherein a magnetic “hot seed” layer made of a >19 kG to 24 kG material adjoins a gap layer, and a side of the hot seed layer opposite the gap layer adjoins a high damping magnetic layer made of a 10-16 kG material (or a 16-19 kG material in the trailing shield) having a Gilbert damping parameter α>0.04. In a preferred embodiment, the high damping magnetic layer is FeNiRe with a Re content of 3 to 15 atomic %. One or both of the main pole leading and trailing sides may be tapered. Side shields may have a single taper or dual taper structure. Higher writer speed with greater areal density capability is achieved. |
| US09508362B2 |
Write management for interlaced magnetic recording devices
A storage device includes a controller that implements an interlaced magnetic recording scheme with prioritized random access. According to one implementation, a controller is configured to write data at a first linear density to alternating data tracks and write data at a second linear density to one or more data tracks interlaced with the alternating data tracks. |
| US09508358B2 |
Noise reduction system with remote noise detector
Noise reduction system with remote noise detector The present invention relates to a noise reduction system with at least one remote noise detector placed close to at least one noise source, which transmits relevant information to a primary device where it is used for noise reduction. Thereby, acoustic signal enhancement can be achieved via the at least one remote noise detector in that a noise estimate is transmitted to controller for noise reduction in the signal obtained from a primary source. |
| US09508354B2 |
Media synchronisation system
A communications system distributes code word pairs within the audio of a television or radio program or the like. Each pair of code words includes an ID code word that is the same for a given program and a synchronization code word that is unique within the program. A portable user device is able to synchronize itself to the program using the embedded synchronization code words. |
| US09508349B2 |
Method, system, and terminal device for transmitting information
Methods, systems, and terminal devices for transmitting information are provided. An exemplary system includes a sending end and at least one receiving end. The sending end is configured to obtain audio data to be transmitted, encode the obtained audio data according to an M-bit unit length, and use a pre-set cross-platform audio interface to control an audio outputting device of the sending end to send the encoded audio data to the at least one receiving end. The M-bit unit length is an encoding length corresponding to each frequency of a number N of frequencies, N is greater than or equal to 2, and M is greater than 0. The at least one receiving end is configured to use the pre-set cross-platform audio interface to control an audio inputting device of the at least one receiving end to receive the encoded audio data. |
| US09508347B2 |
Method and device for parallel processing in model training
A method and a device for training a DNN model includes: at a device including one or more processors and memory: establishing an initial DNN model; dividing a training data corpus into a plurality of disjoint data subsets; for each of the plurality of disjoint data subsets, providing the data subset to a respective training processing unit of a plurality of training processing units operating in parallel, wherein the respective training processing unit applies a Stochastic Gradient Descent (SGD) process to update the initial DNN model to generate a respective DNN sub-model based on the data subset; and merging the respective DNN sub-models generated by the plurality of training processing units to obtain an intermediate DNN model, wherein the intermediate DNN model is established as either the initial DNN model for a next training iteration or a final DNN model in accordance with a preset convergence condition. |
| US09508346B2 |
System and method of automated language model adaptation
Systems and methods of automated adaptation of a language model for transcription of audio data include obtaining audio data. The audio data is transcribed with a language model to produce a plurality of audio file transcriptions. A quality of the plurality of audio file transcriptions is evaluated. At least one best transcription from a plurality of audio file transcriptions is selected based upon the evaluated quality. Statistics are calculated from the selected at least one best transcription from the plurality of audio file transcriptions. The language model is modified from the calculated statistics. |
| US09508344B2 |
Automatic volume control based on speech recognition
An entertainment system suitable for use in a vehicle and configured to control an output volume of the system includes a microphone and a processor. The microphone is configured to detect sound in a cabin of the vehicle, and output a microphone signal indicative of the sound. The processor is configured to determine a difference signal based on a difference between the microphone signal and an output signal corresponding to sound being output by the system, determine if the difference signal corresponds to human speech, and decrease the output volume of the system when the difference signal corresponds to human speech. |
| US09508342B2 |
Initiating actions based on partial hotwords
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, receiving audio data; determining that an initial portion of the audio data corresponds to an initial portion of a hotword; in response to determining that the initial portion of the audio data corresponds to the initial portion of the hotword, selecting, from among a set of one or more actions that are performed when the entire hotword is detected, a subset of the one or more actions; and causing one or more actions of the subset to be performed. |
| US09508338B1 |
Inserting breath sounds into text-to-speech output
A text-to-speech (TTS) system may be configured to incorporate breath sounds in the output speech. By incorporating breath sounds into speech output from text a TTS system may be able to mimic more naturally sounding human speech, particularly for long-form narration of text longer than short phrases. The breath sounds may be stored as units for unit selection or may be generated during parametric synthesis. The acoustic features of the breath sounds and duration between breaths may depend upon the punctuation of text, the linguistic distance between breaths, the breaks between intonational phrases, the linguistic context of the breaths, and other factors. |
| US09508335B2 |
Active noise control and customized audio system
An audio customization system responsive to one or more inputs that enhance aspects of an audio output and one or more inputs that diminish aspects of an audio output. The system is set up to be able to lessen the influence of ambient audio or in some situations enhance ambient audio over source audio. The system may specify aspects of audio to be modified by specification of filtering algorithm, characterization of audio samples, monitored distortion, user selection, location specification or environmental specification. |
| US09508332B2 |
Guitar amplifier
A system and method for a guitar amplifier that overcomes the disadvantages of known amplified speaker enclosures and circuits while providing more effective volume control. A venue switch selects different output ranges for the guitar amplifier. Volume control still adjusts output regardless of venue switch position. In the low-output setting for the venue switch a house or other quiet venue is accommodated with the guitar amplifier that can work in larger venues in the high-output setting. |
| US09508323B2 |
Appliance control system and method for controlling an appliance based on processing done by another appliance
An image display method including: obtaining (S2301) combined data including (i) image data of an image having an item as a subject and (ii) first setting information indicating processing which a first electric appliance performs on the item; determining whether or not the first setting information is convertible into second setting information, the first setting information being included in the obtained combined data, and the second setting information being information in a format previously designated by a user and executable by a second electric appliance; determining (S2305) a first mark to be added to the image of the image data, if it is determined that the first setting information is convertible into the second setting information; and displaying (S2307) the image of the image data to which the determined first mark is added, the image data being included in the combined data. |
| US09508322B2 |
Text box resizing
A system, method, and computer readable medium are disclosed for re-sizing input fields and text of a user interface displayed within a touch-sensitive screen. The user interface comprises an initial view with at least one input field. The user interface is provided for display on the screen. A touch interaction is detected on the screen, and it is determined whether the interaction is within a predefined area of an input field. Responsive to determining that the interaction is within the predefined area, a magnified view of the input field is generated. The magnified view increases the proportion of the screen filled by the input field and text relative to the initial view. The magnified view is then presented for display on the screen. |
| US09508319B2 |
Display and method for displaying video frames thereof
A display and a method for displaying video frames thereof are provided. In the method, a connection state between a first port, a second port and a source device is detected. When only one port is connected to the source device, an original resolution data is provided to the source device through the port and a video streaming transmitted from the source device is received. The video streaming is divided and respectively outputted to the display by a first display controller and a second display controller. When the first port and the second port are both connected to the source device, two adjusted resolution data are provided to the source device through the first port and the second port respectively, and two video streamings transmitted from the source device are received and outputted to the display by the first display controller and the second display controller respectively. |
| US09508318B2 |
Dynamic color profile management for electronic devices
Dynamic white point management techniques include determining a white point of ambient light proximate to a display. A color profile adjustment is determined based upon the determined white point and intensity of the ambient light. The image color space is transformed to a display color space for rendering on the display based on the determined adjusted to the color profile. |
| US09508311B2 |
Display apparatus, connectable external peripheral device and method of displaying an image
A display apparatus, a connectable external peripheral device and a method of displaying an image are disclosed. The display apparatus includes a display unit; an image processor which first processes an image signal according to a preset first image processing operation, and secondly processes the first processed image signal processed according to the first image processing operation, and outputs the processed image signal to the display unit. The display apparatus further includes a peripheral device connector, to which an external peripheral device is connected that processes the image signal processed by the first image processing operation. The second image processing operation is performed in the external peripheral device. The image processor transmitting to the external peripheral device the first processed image signal in response to the external peripheral device being connected to the peripheral device connector. |
| US09508309B2 |
Computer-based method for cropping using a transparency overlay/image overlay system
The present disclosure provides a method for cropping one or more files in freeform using transparent or non-transparent layers. Specifically, the embodiments allow a user to crop a file with irregular/freeform boundaries while using a plurality of transparent or non-transparent layers that overlay the original file. The transparent layers overlap the image data for cropping, so that the finalized cropped image may be copied, pasted, or imported into another document while leaving the original file unaltered. The cropped portion of the image may also be sent or emailed by the user. |
| US09508300B2 |
Driving circuit having extra transistor or capacitor, and flat panel display device including the driving circuit
A driving circuit includes: an input terminal; an output terminal; a first transistor having a source electrode coupled to the input terminal, a drain electrode coupled to the output terminal, and a gate electrode; a second transistor having a source electrode, a drain electrode, and a gate electrode respectively coupled to the source electrode, the drain electrode, and the gate electrode of the first transistor; a first capacitor having a first electrode coupled to the input terminal and a second electrode coupled to the output terminal; and a second capacitor coupled in parallel with the first capacitor and having a first electrode coupled to the first electrode of the first capacitor and a second electrode that is floated. |
| US09508298B2 |
Adaptive inversion control of liquid crystal display device
A display device is disclosed. The display device includes a liquid crystal display panel; a data driver for driving the liquid crystal display panel in a first inversion manner; a timing controller for controlling the data driver; and a power converter for changing a first power voltage supplied from a power supply unit into a second power voltage and outputting the second power voltage, wherein, when the power of one of the power supply unit and the power converter is turned on after being abnormally turned off, the liquid crystal display panel is driven in a second inversion manner different from the first inversion manner. |
| US09508296B2 |
Driving method of pixel array, driving module of pixel array and display device
The present invention provides a driving method of a pixel array, wherein the driving method includes: step 1, obtaining a theoretical brightness value of each sub-pixel for an image to be displayed; step 2, calculating an actual brightness value of each sub-pixel, the actual brightness value of a sub-pixel to be calculated is a sum of a part of the theoretical brightness value of the sub-pixel to be calculated and a part of the theoretical brightness values of a plurality of auxiliary sub-pixels corresponding to the sub-pixel to be calculated; and step 3, outputting a signal to each sub-pixel so that the brightness value of each sub-pixel reaches the actual brightness value thereof which is obtained in the step 2. The present invention further provides a driving module of a pixel array and a display device. |
| US09508295B2 |
Display device
According to one embodiment, a display device includes a first substrate including a first pixel electrode disposed on a first color pixel of red, a second pixel electrode disposed on a second color pixel of green, a third pixel electrode disposed on a third color pixel of blue, and a fourth pixel electrode disposed on a fourth color pixel of white, a second substrate including a common electrode, and a liquid crystal layer held between the first substrate and the second substrate, wherein a top voltage applied to the fourth color pixel to correspond to a maximum gradation value is set to be less than a top voltage applied to each of the first color pixel and the second color pixel to correspond to respective maximum gradation values. |
| US09508292B2 |
Pixel driving circuit and driving method thereof, and display device
The present invention provides a pixel driving circuit and a driving method thereof, and a display device. The pixel driving circuit is used for driving a pixel array, wherein each pixel in the pixel array comprises four sub-pixels with different colors, and wherein the pixel driving circuit comprises: at least one first sub-pixel driving chip and at least one second sub-pixel driving chip, wherein the at least one first sub-pixel driving chip each is connected to a part of sub-pixels corresponding thereto in corresponding pixels to drive them, and the at least one second sub-pixel driving chip each is connected to the other part of sub-pixels corresponding thereto in the corresponding pixels to drive them. In the invention, noise interference can be avoided, and the display quality is improved; the cost is reduced; signal transmitting efficiency is increased and the EMI characteristic of products is improved. |
| US09508286B2 |
Pixel circuit, display substrate and display device
The present invention provides a pixel circuit, a display substrate and a display device. The pixel circuit comprises a control section, a light emitting diode, a high-level input terminal, a low-level input terminal and a reference terminal, in which the control section comprises a driving thin film transistor, at least one capacitors and a plurality of switching thin film transistors. The reference terminal is connected with the low-level input terminal so as to discharge a capacitor which is connected with a gate of the driving thin film transistor in a pixel resetting stage of the pixel circuit. |
| US09508284B2 |
Method of driving organic electroluminescent display device
A method for controlling a display device includes adjusting the luminance value of input data by a first method when the luminance value is greater than or equal to a predetermined number of nits, and adjusting the luminance value by a second method when the luminance value is less than the predetermined number of nits. The first method reduces the luminance value by a first predetermined percentage. The second method adjusts the luminance value to a first value corresponding to a predetermined luminance value set for the predetermined number of nits, and then reduces the first value by a second predetermined percentage different from the first predetermined percentage. The predetermined number of nits may be 2 nits or another number of nits. |
| US09508280B2 |
Method of compensating color of transparent display device
A method of compensating color of a transparent display device includes generating a first pixel data by adding an input image pixel data and an external optical data which represents an effect of an external light on the transparent display device, generating a second pixel data having the same color as the input image pixel data by scaling the first pixel data, and generating an output image pixel data by subtracting the external optical data from the second pixel data. |
| US09508279B2 |
Color conversion apparatus and non-transitory computer readable medium
A conversion apparatus, includes: a target value setting unit that sets a target value for color reproduction at the time when output image data is displayed on a display device, the target value is set by using a first target value set based on a display characteristic of the display device and a second target value set by designating targets of hue and saturation with respect to a gray image; a conversion relation creation unit that creates a conversion relation based on the set target value; and an output image creation unit that performs color conversion processing on an input image data using the conversion relation to creates the output image data, in which the second target value is set to suppress variation of color representation. |
| US09508278B2 |
Present contents on persistent display
Various systems and methods for presenting contents on a persistent display are described herein. A system for controlling an electronic display comprises a persistent display; a trigger module to detect a triggering event; a configuration module to access a dead screen configuration in response to the triggering event, the dead screen configuration specifying content to display on the persistent display of the system after the system is powered down; and an output module to write the specified content to the persistent display as an image. |
| US09508272B2 |
Fluid activatable adhesives for glue-free, liner-free labels for glass and plastic substrates and methods of use thereof
Methods for applying a liner-free, or liner-less label, to a substrate, particularly glass or plastic (e.g., PET) substrates are described herein. The method includes applying an adhesive composition, such as a polymeric coating, to a label face sheet, activating the adhesive composition with an activating fluid, and contacting the label to the substrate. The activating fluid is preferably a mixture of water and one or more organic solvents, such as low molecular weight alcohols. In some embodiments, the labels exhibit a percent fiber tear greater than about 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95% after one, two, three, four, or five minutes. In particular embodiments, the labels exhibits a percent fiber tear greater than 60, 65, 70, 75, 80, 85, 90, or 95% after two minutes. |
| US09508265B2 |
Methods and systems for wind mitigation in autonomous parafoil guidance
According to one aspect, a flight controller constructed to control a parafoil in flight from a starting location to a target location is provided. The flight controller includes an interface constructed to connect to one or more actuators and one or more wind sensors, a memory, a processor coupled to the memory, the interface, and a flight manager component executable by the processor. The flight manager component is configured to identify the target location and the starting location, receive wind data, determine a relationship between a ground reference frame (GRF) and a wind fixed frame (WFF) based on the wind data, generate a trajectory between the starting location and the target location in the WFF, determine a desired heading based on the trajectory and the relationship between the GRF and the WFF, and generate an actuator control signal based on the desired heading to adjust a heading of the parafoil. |
| US09508262B2 |
Systems and methods for voice enabled traffic prioritization
A system and method capable of responding to an audible traffic alert by visually depicting the identified neighboring aircraft traffic on the onboard display is presented. The system and method employ speech recognition in order to minimize the visual and manual cognitive workload associated with responding to a traffic alert. The system and method maximize the pilot's hands-on control of the host aircraft. |
| US09508261B2 |
Method and device for operating a vehicle
A method for operating a vehicle, including the tasks of detecting a dynamic parameter of a preceding other vehicle, computing an assessment criterion based on the detected dynamic parameter, computing a setpoint vehicle trajectory as a function of the assessment criterion, and adjusting an actual vehicle trajectory to the setpoint vehicle trajectory. Also described is a corresponding device and a computer program. |
| US09508260B2 |
Method to improve parking space identification in autonomous driving
A method for parking an autonomous vehicle in a parking lot. The method comprises receiving primary data from a first source and receiving secondary data from a second source. The primary data may include information sufficient to identify a location for one or more of a plurality of parking spaces within the parking lot. The secondary data may include status identifier information for at least one of the plurality of parking spaces. The method includes using the primary data and the secondary data to identify at least one vacant parking space in the plurality of parking spaces, and occupying the at least one vacant parking space. |
| US09508259B2 |
Wearable device and method of controlling the same
Provided is a wearable device including: a biological-signal sensing unit that senses a biological signal of a user; a vehicle-state sensing unit that senses a state where a vehicle that the user gets in is moved; and a controller that determines a parking mode and a parking direction using a result of the sensing by the vehicle-state sensing unit, when the vehicle is parked, and that measures a level of user tension for the parking mode and the parking direction that are determined using the biological signal that is sensed while the vehicle is being parked, in which the controller selects the parking mode and the parking direction that the user prefers, based on the measured level of user tension, and provides the user with information relating to a parking lot where the vehicle is able to be parked in the parking mode and the parking direction that are selected. |
| US09508258B2 |
Intersection guide system, method, and program
Intersection guide systems, methods, and programs acquire a degree of approach of a vehicle to an intersection ahead of a vehicle and display a guide image at a position of the intersection superimposed on a forward scene ahead of the vehicle. The systems, methods, and programs set, as a position of superimposition of the guide image, an intersection position within the forward scene when the degree of approach is less than a threshold. The intersection position corresponds to a registered position registered in map information as the position of the intersection. The systems, methods, and programs set, as the position of superimposition, a straight-line position within the forward scene when the degree of approach is equal to or more than the threshold. The straight-line position corresponds to a position on a straight-ahead line that is a straight line extending in a travel direction of the vehicle from the vehicle. |
| US09508257B2 |
Road detection logic
An analyzer of the invention adequately analyzes a change in road network by using probe information generated with driving of a vehicle. This analyzer determines a traffic amount of vehicles passing through a specified section included in the road network from a plurality of the probe information accumulated over a predetermined period. The analyzer also determines a discontinuity rate, which is a rate of incidents that vehicle locations are discontinuous in the specified section, from the plurality of probe information accumulated over the predetermined period. The analyzer detects a change in the road network, based on a degree of change between traffic amounts in two different periods with respect to the specified section included in the road network and a degree of change between discontinuity rates in the two different periods. The detected change in the road network can be used for survey of the road network. |
| US09508256B2 |
Magnetic resonance imaging (MRI) with dual agent characterization
Example apparatus and methods concern determining whether a target material appears in a region experiencing nuclear magnetic resonance. One method acquires a baseline value for a magnetic resonance parameter (MRP) while the region is not exposed to a molecular imaging agent that affects the MRP, acquiring a non-specific uptake value for the MRP while the sample is influenced by a non-specific molecular imaging agent and acquiring a specific uptake value for the MRP while the sample is influenced by a specific molecular imaging agent. The non-specific masking problem is solved by characterizing the region as a function of the baseline value, the non-specific uptake value, and the specific uptake value. The function relies on the similarities and differences between non-specific uptake of the non-specific molecular imaging agent, non-specific uptake of the specific molecular imaging agent, and specific uptake of the specific molecular imaging agent. |
| US09508255B2 |
Integrated system of infrared remote controls
An integrated system of infrared remote controls includes a touch remote control and at least one infrared emitter. The touch remote control is wirelessly connected with the infrared emitter to transmit a remote signal. Each infrared emitter is mounted on a home appliance. When the infrared emitter receives the remote signal, the infrared emitter produces an infrared signal according to the remote signal and emits the infrared signal to the home appliance to control the home appliance. The infrared emitter can be adhered to or attracted on the home appliance by an adhesive layer or a magnet. Therefore, the infrared emitter can be easily mounted on the home appliance. It is very convenient for a user to set up and use the integrated system. |
| US09508254B1 |
Proximity location system and method thereof for locating a communications device
A proximity location system and method thereof for locating a communications device. A radio-frequency identification (RFID) proximity location tag is arranged in a proximity of the communications device and detected thereby. A proximity location key included in the RFID proximity location tag is acquired by the communications device and forwarded to a location information server. The location information is queried for location information associated with the proximity location key. Based on the location information, data transmitted by the communications device is routed to the appropriate receiver of the data. The location information is also provided to the receiver. |
| US09508253B1 |
Systems and methods for programming a remote control device
A method for programming a first remote control device associated with a first electronic device that includes receiving, by the first electronic device, a first electronic command signal issued from a second remote control device. The first electronic command signal includes a key code indicative of a first key entry on the second remote control device. The first electronic device accesses a key code database, which stores a plurality of key code sets, and each of the plurality of key code sets has a plurality of key codes for controlling at least one electronic device. The first electronic device compares the received first key code to the key code database to identify matching key code sets including the first key code. The first electronic device analyzes the matching key code sets to identify a preferred next key entry, and prompts a user of the second remote control device to press a key on the second remote control device corresponding to the identified preferred next key entry. |
| US09508250B2 |
Automatic security system mode selection
Systems and techniques are provided for automatic security system mode selection. A set of signals may be received from sensors distributed in an environment with a security system. The security system may be in a first mode. An occupancy model may be received. An occupancy estimate may be generated for the environment based on the set of signals from the sensors and the occupancy model. Mode rules may be received. The mode rules associate occupancy estimates with modes of the security system. A second mode for the security system may be determined based on the occupancy estimate and mode rules. The second mode may be different from the first mode. The mode of the security system may be automatically changed from the first mode to the second mode. |
| US09508247B2 |
Systems and methods of automated arming and disarming of a security system
Systems and methods of security are provided, including at least one of a plurality of sensors to detect a location of at least one user, and generate detection data according to the detected location of the at least one user. A processor may be communicatively coupled to the at least one of the plurality of sensors to receive the detection data and to determine whether the at least one user is occupying a building according to the detection data. An alarm device, communicatively coupled to the processor, can be armed or disarmed by the processor according to the determination as to whether the at least one user is occupying the building. |
| US09508243B1 |
Hydrogen sulfide alarm methods
H2S (hydrogen sulfide) alarm methods include automated systems for creating reports, initiating different safety drills and/or recording certain calibration and bump tests. The methods being automated reduces the chance of human error and falsified records. The H2S alarm methods are particularly useful for ensuring the safety of workers at remote worksites. |
| US09508235B2 |
Projection unit for a self-directing mobile platform, transport robot and method for operating a self-directing mobile platform
A projection unit for a self-directing mobile platform, in particular for a freely moving transport robot and/or for one or more freely moving transport devices of a transport robot, is characterized in that the projection unit is adapted for signal transmission for projecting the movement path of the mobile platform, wherein the projection takes place within the spatial vicinity of the mobile platform. |
| US09508234B2 |
Cargo compartment indication for tie down restraint locations
A system and method for identifying tie down restraint locations in a cargo compartment or other storage area is disclosed. The system includes labeling or otherwise highlighting the tie down locations on a floor where the cargo is to be secured. The labeling is based on a reference coordinate system that is associated with a tie down plan. Additionally or alternatively, a tie down locator device is mounted above the floor that highlights or otherwise illuminates a tie down location. As a cargo handler completes a connection, the device highlights the next tie down location. |
| US09508232B2 |
Short depth cash drawer with downstream checkout placement
Embodiments described herein pertain to checkout stands and related components. Checkout stands illustratively include scanners and cash drawers. In some embodiments, cash drawers are located downstream from scanners. In some embodiments, checkout stands include item entering and exiting sides. Scanners are illustratively positioned between an entering side and a cash drawer, and cash drawers are illustratively positioned between a scanner and an exiting side. |
| US09508230B2 |
Gaming machine and methods of allowing a player to play a gaming machine having multiple games with the same reel
A gaming machine for providing multiple games to a player with the same reel is described herein. The gaming machine displays a first game that includes a first portion of a reel in a first display area and concurrently displays a second game that includes a second portion of the reel being displayed in a second display area. The gaming machine randomly generates an outcome of the first game and spins and stops the at least one reel to display the first game outcome in the first display area and awards the player an award as a function of the first game outcome. |
| US09508228B2 |
Multiplayer gaming system
The present invention generally relates to gaming systems for playing ball games where a ball is launched into a gaming area. More particularly, the present invention relates to a multiplayer gaming system comprising a ball game device having a launching mechanism for launching a ball into a gaming area to start a game, the gaming system further comprising a start control means for controlling start of the launching mechanism and a plurality of gaming terminals for a plurality of players, said gaming terminals including an input device for inputting a prediction and/or a bet for the outcome of a game. In accordance with the present invention, the input device of each gaming terminal includes start signal input means for inputting a start signal for starting the launching mechanism, wherein the start control means of the gaming system includes a random signal generator for randomly selecting one of the plurality of gaming terminals for each game to generate the start signal and a display signal generator for generating a display signal indicative of the gaming terminal selected for the generation of the start signal. |
| US09508227B1 |
Multi-draw video poker
A method of generating and displaying a game of chance on an electronic device to one or more players, wherein each player places a wager on a primary hand of cards dealt from a deck of cards containing at least one Multi-Draw Bonus Card. The player may place an additional wager on one or more Multi-Draw Bonus cards (bonus card) provided on the deal and/or the draw. The bonus card provides for a multiplier and/or n additional cards to be dealt in place of the bonus card. The cards for each band are dealt from a deck of cards using a random number generator. |
| US09508226B2 |
Method and apparatus for bonus round play
Methods and apparatus are provided for enabling a player to take a tour of a secondary game at a game machine. In one embodiment, a method is provided that includes offering to enable entry of a player into a bonus round of a game machine in exchange for a fee, receiving the fee from the player, and enabling entry of the player into the bonus round. The method further includes receiving an indication of at least one player selection during the bonus round, and determining an outcome based on the at least one player selection. In other embodiments, the method includes providing a prize to the player based on the outcome. |
| US09508225B2 |
Methods and apparatus for enhanced interactive game play in lottery and gaming environments
Methods and systems for electronic interaction comprising a display for presenting a grid of identifying objects, an input for receiving a player selection of an identifying object, a random generator for randomly selecting a winning identifying object, and a point tally system for awarding points to the player according to the rules comprising a first point value if the player selected identifying object exactly matches the winning identifying object, a second point value if the player selected identifying object is in a geometric relationship with the winning identifying object, and a third, negative, point value if the player is not awarded the first point value or the second point value. |
| US09508224B2 |
Player specific network
Embodiments of the invention allow a player to have a unique gaming experience, different than other players, even when playing on the same network. A game may span several gaming sessions. States of a game, for example a bonus game, may be stored when the player decides to stop playing the game. When the player initiates a next gaming session, at the same or another location, the previous state of the game is re-loaded onto the gaming machine and the player returns to the previous state. Further, additional bonuses can be implemented because the network knows the identity and other information about the player. The additional bonuses may be unique to that player. Messages particular to a player are exchanged between a gaming device and a gaming network. |
| US09508223B2 |
Method and apparatus for competitive bonus games based upon strategy or skill
The present invention relates to gaming systems and methods where enablement for play of a bonus game is linked to play of a primary game. A player may qualify for the bonus game by preselected criteria associated with play of the primary game. The qualified players may participate in the bonus game and compete against one another in one or more rounds to achieve a final winning outcome based on the individual player's skill, strategy, or knowledge. The player who achieves the final winning outcome at the end of a plurality of rounds of the bonus game is awarded a bonus pool funded by a portion of wagers accumulated during play of the primary game. |
| US09508222B1 |
Customized chance-based items
A system configured to facilitate user customization of the distribution of virtual items usable in a virtual space. Virtual items may be distributed via probability item bundles. Probability item bundles may be associated with a set of potential awards. The potential awards included in the set of potential awards may be individually associated with a probability of being distributed once the probability item bundle is activated by a user. Customization of probability item bundles may comprise facilitating user selection of the potential awards included in the sets of potential awards of the probability item bundles. |
| US09508221B2 |
Gaming system adapted to receive bill data and ticket data based on a minimum acceptable denomination
A controller for a gaming machine, the controller adapted to receive data from a bill acceptor that may represent bill data or ticket data, the controller arranged to process the data and to output bill data to a game controller, and output ticket data to a ticket processing mechanism. |
| US09508220B2 |
Method and apparatus for influencing cash outs from a gaming device
A gaming device is described that provides a number of different methods for cashing out credit balances from a gaming device. These methods include providing incentives, such as benefits, to a player for selecting particular monetary forms in which to receive the cash out. Non-preferred cash out forms may be associated with disincentives, such as penalties, to dissuade players from selecting these types of monetary transfers. In certain embodiments, incentives and disincentives may be associated with a variety of available monetary forms for cash out. |
| US09508215B2 |
Method and apparatus for gaming with alternate value payouts
Systems and methods are provided for permitting a player to play a game at a gaming device. The gaming device provides a payout for the game. The payout is redeemable for one of a plurality of values, and at least two of the plurality of values are different from each other. The values typically have different corresponding forms of payout, such as cash or merchandise credits. |
| US09508214B2 |
Three-dimensional reels for an electronic gaming device
Examples disclosed herein relate to systems and methods for delivering game play, which may include providing wagering game options that may include a two-dimensional option, a three-dimensional option, and/or a combination of both. |
| US09508213B2 |
Systems and methods of reading gaming chips and other stacked items
Systems, methods and computer program products associated with wirelessly (e.g., RF) readable gaming chips are disclosed. |
| US09508212B2 |
Apparatus for controlling access to and use of portable electronic devices
Various prison services are rendered more efficient by providing inmates access to portable electronic devices in a controlled and regulated manner. A dispenser is employed to control and monitor the checking out and return of portable electronic devices and to communicate with such devices during use by inmates to monitor inmate use and ensure the portable electronic devices are only used by inmates as authorized. |
| US09508207B2 |
Method and apparatus for network controlled access to physical spaces
The system provides a method and apparatus for providing controlled access to premises. The system in one embodiment uses a reader/scanner associated with a controlled entrance that can receive credentials manually or via scanning or some other form of electronic communication. In one embodiment, the system uses NFC (Near Field Communication) from a mobile device to determine if access should be granted. The system contemplates a number of different tiers of users whose right of access to a location depends on the tier in which the user resides. For one time visitors, the system contemplates transmitting an access credential that can be used by a specific user for a limited time period. In some cases, the access credential is tied to a particular device. |
| US09508201B2 |
Identifying the origins of a vehicular impact and the selective exchange of data pertaining to the impact
Approaches are provided for identifying the origin of a vehicular impact and selectively exchanging data pertaining to the impact. An approach includes determining whether an impact to a vehicle exceeds a predetermined threshold. The approach further includes when the impact exceeds the predetermined threshold, sending a signal that includes impact information and identifier information stored in a persistent storage device. The approach further includes receiving signals from one or more other vehicles within a predetermined proximity of the vehicle. The approach further includes comparing impact information from the signals to the impact information stored in the persistent storage device. The approach further includes when the impact information from the signals matches the impact information stored in the persistent storage device within a tolerance threshold, storing the impact information and identifier information from the signals in the persistent storage device. |
| US09508200B1 |
System and method for using a specialty vehicle data identifier to facilitate treatment of a vehicle damaged in a crash
A system, method, and computer-readable medium to facilitate treatment of a damaged vehicle by gathering crash information, estimating an extent of vehicle damage, and transmitting information associated with treating the damaged vehicle. |
| US09508194B1 |
Utilizing content output devices in an augmented reality environment
Techniques for enabling an augmented reality system to utilize existing output devices in an environment are described herein. An augmented reality system may include one or more augmented reality functional nodes (ARFNs) that are configured to project content onto different non-powered and/or powered display mediums. In addition to projecting content in this manner, the ARFN may also utilize existing content output devices within the environment to further enhance a user's experience while consuming the content. For instance, the ARFN may identify that a television exists within the environment and, in response, the ARFN may instruct the television to display certain content. For instance, if the ARFN is projecting a particular movie, the ARFN may stream or otherwise provide an instruction to the television to begin displaying the movie if the television would provide a better viewing experience than the projector. |
| US09508190B2 |
Method and system for color correction using three-dimensional information
A system and method for the color correction of an image using three-dimensional, geometrical information of the capture environment of the image includes determining geometrical properties of at least a portion of the image and modifying a look of at least the portion of the image by altering a value of at least one of the determined geometrical properties and using image formation theory. In one embodiment of the present invention, the geometrical properties of the image include at least one of light properties, surface color, reflectance properties, and scene geometry of the at least one portion of the image. In accordance with the present invention, the geometrical properties of the image are alternatively determined by using sensing devices, by inferring the geometrical properties from the image itself, or by user input. |
| US09508189B2 |
Method and apparatus for creating 3D image of vehicle surroundings
The present invention relates to a method and apparatus for creating a 3D image of vehicle surroundings. The method according to the present invention includes the steps of: mapping images captured by a plurality of cameras installed in a vehicle to a virtual plane defined by a 3-dimensional space model having a container shape with a flat bottom surface and a top surface which has an increasing radius; and creating a view image having a viewpoint of a virtual camera by using the image mapped to the virtual plane. According to the present invention, it is advantageous that an image of vehicle surroundings including surrounding obstacles can be expressed naturally and three-dimensionally. It is also advantageous that an optimal image of vehicle surroundings can be provided by changing the virtual viewpoint according to a traveling state of the vehicle. There is also the advantage that a user can conveniently adjust the viewpoint of the virtual camera. |
| US09508185B2 |
Texturing in graphics hardware
Methods, systems, and devices for rendering computer graphics using texture maps are disclosed. Multiple texture maps with disparate data types, such as a mix of integer data types for RGB colors and floating point data types for XYZ normal vector components, are passed as one texture map set to a graphics processing unit (GPU). Filter parameters and other interpolation parameters are re-used between the disparate texture maps. A user can specify a number of integer and floating point-based channels for processing at one time by the GPU, thereby customizing a texture set structure. |
| US09508182B2 |
Method of displaying 3D image and display apparatus for performing the method
A display apparatus includes a display panel and an active parallax barrier panel. The display panel displays n numbers of viewpoint images on a display panel (‘n’ is natural numbers greater than 2). The active parallax barrier panel includes a plurality of barrier units. Each of the barrier units includes an opening portion and a blocking area divided into m numbers of sub-areas. The active parallax barrier panel selectively opens the m numbers of sub-areas to exit the m numbers of viewpoint images on (n×m) numbers of viewpoint positions (‘m’ is natural numbers greater than 2). Thus, an active parallax barrier panel is time-division driven to display multi-viewpoint images. Moreover, a pixel structure and a barrier structure are alerted, so that deterioration of a resolution of a 3D image may be minimized. |
| US09508180B2 |
Avatar eye control in a multi-user animation environment
In a multi-participant modeled virtual reality environment, avatars are modeled beings that include moveable eyes creating the impression of an apparent gaze direction. Control of eye movement may be performed autonomously using software to select and prioritize targets in a visual field. Sequence and duration of apparent gaze may then be controlled using automatically determined priorities. Optionally, user preferences for object characteristics may be factored into determining priority of apparent gaze. Resulting modeled avatars are rendered on client displays to provide more lifelike and interesting avatar depictions with shifting gaze directions. |
| US09508179B2 |
Flexible 3-D character rigging development architecture
A method of generating an animation rig for a three-dimensional (3-D) computing environment may include providing a rig generation environment that includes a library storing a plurality of blocks. Each of the plurality of blocks may represent particular rig elements and include information for generating the rig elements in the 3-D computing environment along with a first icon that is visually representative of the particular rig elements. The method may also include receiving and displaying two or more blocks in the rig generation environment, and receiving one or more graphical connections between the blocks. The method may additionally include generating the animation rig using the information of each of the two or more blocks and sending the animation rig from the rig generation environment to the 3-D computing environment. |
| US09508176B2 |
Path and speed based character control
A 3D animation environment that includes an animation object is generated. A movement speed is assigned to object the 3D animation environment. An animation path containing at least first and second waypoints is generated. An animation sequence is generated by identifying a first section of the animation path connected to the first waypoint. A first animation of the animation object is generated in which the animation object moves along the first section of the path at the movement speed. A spatial gap in the animation path is identified between the first and second waypoints. A second animation of the animation object is generated in which the animation object moves, by keyframe animation, from the first waypoint to the second waypoint. A third animation of the animation object is generated in which the animation object moves along at least a second portion of the path at the movement speed. |
| US09508173B2 |
Image processing device having depth map generating unit, image processing method and non-transitory computer redable recording medium
An object of the present invention is to provide an image processing device and the like that can generate a composite image in a desired focusing condition. In a smartphone 1, an edge detecting section 107 detects an edge as a feature from a plurality of input images taken with different focusing distances, and detects the intensity of the edge as a feature value. A depth estimating section 111 then estimates the depth of a target pixel, which is information representing which of the plurality of input images is in focus at the target pixel, by using the edge intensity detected by the edge detecting section 107. A depth map generating section 113 then generates a depth map based on the estimation results by the depth estimating section 111. |
| US09508168B2 |
Method and system for utilizing transformation matrices to process rasterized image data
A method and system render rasterized data by receiving non-rasterized page description language data and a corresponding transformation matrix representing transformation operations to be performed. The non-rasterized page description language data is rasterizing to create rasterized data. The corresponding transformation matrix is decomposed into a plurality of individual transformation operation matrices and a discrete transformation operation value, from each corresponding individual transformation operation matrix, is generated for each transformation operation to be performed upon the rasterized data. The transformation operations are performed upon the rasterized data based upon the generated discrete transformation operation values. |
| US09508160B2 |
User interface panel
The present disclosure provides a method of modifying a user interface on a display relative to a user, comprising: detecting a position of a user's eyes relative to a user interface (UI) viewing surface, wherein the detecting includes sensors selected from the group consisting of proximity sensors, web cams, and face recognition scanners; wherein the detecting further includes detecting the position of the user's eyes relative to the user interface; adjusting the UI's viewing surface for altered viewing based on the position of the user's eyes; and, wherein the adjusting comprises a software algorithm for switching on and off semi-transparent pixels in the UI viewing surface for viewing the UI by the user at a viewing angle from about 20 degrees to about 90 degrees. |
| US09508155B2 |
Method and apparatus for feature computation and object detection utilizing temporal redundancy between video frames
A method, apparatus and computer program product are provided for determining spatial location for one or more facial features. A method computes features for an initial frame. The computed features of the initial frame generate a feature image. A method also determines whether a translation is verified between the initial frame and an intermediate frame, wherein a translation is verified in an instance in which a distance used to verify the translation between the initial frame and the intermediate frame is within a predetermined threshold level. A method also includes a face search, using a portion of the feature image, for one or more facial features, wherein the portion of the feature image searched is a fraction of the total number of frames analyzed in a feature computation cycle. A method also determines a spatial location for the one or more facial features detected in the intermediate frame. |
| US09508154B2 |
Medical imaging apparatus and method of operating the same
A medical imaging apparatus and a method of operating the same are provided. The method includes acquiring three-dimensional (3D) volume data about an object, generating a 3D image based on the 3D volume data, extracting a muscle tissue figure corresponding to a muscle tissue shape of the object by grouping voxels included in the 3D image, analyzing a motion of the object based on the extracted muscle tissue figure, and displaying the extracted muscle tissue figure and a result of the analysis. |
| US09508148B2 |
Vision-guided alignment system and method
A vision-guided alignment system to align a plurality of components includes a robotic gripper configured to move one component relative to another component and a camera coupled to a processor that generates an image of the components. A simulated robotic work cell generated by the processor calculates initial calibration positions that define the movement of the robotic gripper such that position errors between the actual position of the robotic gripper and the calibration positions are compensated by a camera space manipulation based control algorithm executed by the processor to control the robotic gripper to move one component into alignment with another component based on the image of the components. |
| US09508147B2 |
Information processing apparatus and method
An index detecting section detects an index in a physical space, from a captured image obtained by an imaging apparatus. An erroneous-detection prevention processing section performs erroneous-detection prevention processing, based on information relating to image coordinates of a detected index. An image output section outputs, to a display device, an image having been subjected to the erroneous-detection prevention processing. This prevents an image displayed on the display device from being mistaken for a real index when the display device is in the field of view of the imaging apparatus. |
| US09508146B2 |
Automated frame of reference calibration for augmented reality
One or more systems, methods, routines and/or techniques for automated frame of reference calibration for augmented reality are described. One or more systems, methods, routines and/or techniques may allow for calibration of an Augmented Reality (AR) system, for example, by automatically calibrating the frames of reference of virtual objects and/or a camera. One example calibration routine and/or technique may determine and/or calculate a mapping or transform from a frame of reference of a virtual object (e.g., a CAD model) to a coordinate frame associated with the tracking system. Another example calibration routine and/or technique may determine and/or calculate a mapping or transform from a camera lens frame of reference to a frame of reference of the whole camera as determined by a tracking system. These routines and/or techniques may calibrate an AR system to provide rapid, precise alignment between virtual content and a live camera view of a real scene. |
| US09508142B2 |
X-ray CT apparatus and X-ray CT image-generating method
An X-ray detector (320), configured to have X-ray detecting elements (322) arranged in array, detects the intensity of X-rays that are radiated from the X-ray tube (311) and have passed through a subject (500). A data processing device (420) executes steps of: arranging scan data, which is based on the intensity of X-rays, in an array sequence of the X-ray detecting elements (322) or in a time sequence, to detect an anomalous scan data; associating a weight greater than “1” with scan data adjacent to the anomalous scan data, and associating a weight of “1” with other imaging data; calculating an update amount of a pixel vector that reflects these weights; and performing an iterative operation using the update amount to generate an X-ray CT image of the subject (500). |
| US09508141B2 |
Non-touch optical detection of vital signs
A non-touch thermometer senses temperature from a digital infrared sensor is described. A microprocessor is operably coupled to a camera from which patient vital signs are determined. A digital signal representing a temperature without conversion from analog is transmitted from the digital infrared sensor. A temporal variation of images is generated from which a heart rate and the respiratory rate can be determined and displayed or stored. |
| US09508140B2 |
Quantifying curvature of biological structures from imaging data
A method and system are proposed to obtain quantitative data about the shape of a biological structure, and especially a heart ventricle. A set of three-dimensional input meshes are generated from MRI data. They represent the shape of a ventricle at successive times. The input meshes are used to generate a set of three-dimensional morphed meshes which have the same number of vertices as each other, and have respective shapes which are the shapes of corresponding ones of the input meshes. Then, for each of the times, shape analysis is performed to obtain a curvedness value at each of a plurality of corresponding locations in the morphed meshes. The curvedness value may be used to obtain a curvedness rate at each of the locations, indicative of the rate of change of curvedness with time at each of the locations. |
| US09508138B2 |
Method of detecting photolithographic hotspots
A method for detecting photolithographic hotspots is disclosed. After receiving layout data, an aerial image simulation is conducted to extract aerial image intensity indices. Based on the combination of one or more aerial image intensity indices, various aerial image detectors are generated. The value of aerial image detectors is verified to determine the position and type of the photolithographic hotspots. |
| US09508136B2 |
Image fusing method
Provided is an image fusing apparatus for fusing a thermal image and a visible image of a subject. The image fusing apparatus includes: a determination processor configured to determine importance of each pixel, based on a luminance value thereof, of the thermal image and the visible image; a pixel coefficient setting processor configured to set a pixel coefficient for each pixel of the thermal image based on the importance of each pixel of the thermal image and the visible image; a thermal image processor configured to generate another thermal image by applying the pixel coefficient to the luminance value of each pixel of the thermal image; and an image fusing processor configured to fuse the other thermal image and the visible image to generate a fused image. |
| US09508135B1 |
System and method for image enhancement
An improved image processing system for enhancing a blurred image is described herein. According to an embodiment, a method for enhancing a blurred image provided by an image capturing device includes generating a standard gray low-resolution image by convoluting the blurred image with a Gaussian low-pass filter, extracting one or more high-frequency components from the standard gray low-resolution image, obtaining one or more higher-frequency nonlinear components by approximating the one or more high-frequency components, and adding the higher-frequency components to the blurred image. |
| US09508134B2 |
Apparatus, system, and method for enhancing image data
Described herein is a method for enhancing image data that includes transforming image data from an intensity domain to a wavelet domain to produce wavelet coefficients. A first set of wavelet coefficients of the wavelet coefficients includes low-frequency wavelet coefficients. The method also includes modifying the first set of wavelet coefficients using a coefficient distribution based filter to produce a modified first set of wavelet coefficients. The method includes transforming the modified first set of wavelet coefficients from the wavelet domain to the intensity domain to produce enhanced image data. |
| US09508132B2 |
Method and device for determining values which are suitable for distortion correction of an image, and for distortion correction of an image
A method for determining values which are suitable for distortion correction of an image, including the following steps: a step of splitting a vector field, which is suitable for distortion correction of the image, into a sum of vector products, and a step of determining terms of the vector products as suitable values for distortion correction of the image. |
| US09508127B1 |
Processing for creating a transmission image without artificial noises
A method for reducing a linear artifact in a medical image. The method includes identifying, in the medical image, a region occupied by the linear artifact and isolating, in the region, a signal intensity component attributed to the linear artifact from an overall signal intensity of the region. The method further includes obtaining a corrected signal intensity by subtracting, in the region, the signal intensity component attributed to the linear artifact from the overall signal intensity of the region, and, after obtaining the corrected signal intensity, correcting a contrast in the region to match the contrast in surrounding regions. |
| US09508126B2 |
Image haze removal using fast constrained transmission estimation
Techniques are disclosed for removing haze from an image or video by constraining the medium transmission used in a haze image formation model. In particular, a de-hazed scene, which is a function of a medium transmission, is constrained to be greater than or equal to a fractionally scaled variant of the input image. The degree to which the input image is scaled can be selected manually or by using machine learning techniques on a pixel-by-pixel basis to achieve visually pleasing results. Next, the constrained medium transmission is filtered to be locally smooth with sharp discontinuities along image edge boundaries to preserve scene depth. This filtering results in a prior probability distribution that can be used for haze removal in an image or video frame. The input image is converted to gamma decoded sRGB linear space prior to haze removal, and gamma encoded into sRGB space after haze removal. |
| US09508125B2 |
Restoration of photographic film having a color matrix using digital photographic film processing techniques
Embodiments of the present invention are directed to using digital photographic film processing techniques for restoration of photographic film having a color grid over an underlying silver film. More specifically, embodiments of the present invention improve the resolution and reduce the noise of images with color matrix dots for use with modern digital display technologies. In doing so, embodiments of the present invention advantageously overcome the adverse situation of color matrix dots in images being distracting when viewed directly, particularly in the case of the modern world of digital displays because displaying such a color matrix as is has previously not been practical on a digital display, however means of suppressing the dots in preparation for a digital display have produced low resolution and noisy images. |
| US09508124B2 |
Method of shutterless non-uniformity correction for infrared imagers
A method of correcting an infrared image including a plurality of pixels arranged in an input image array, a first pixel in the plurality of pixels having a first pixel value and one or more neighbor pixel with one or more neighbor pixel values. The first pixel and the one or more neighbor pixels are associated with an object in the image. The method includes providing a correction array having a plurality of correction pixel values, generating a corrected image array by adding the first pixel value to a correction pixel value in the correction array, and detecting edges in the corrected image array. The method also includes masking the detected edges in the corrected image array, updating the correction array, for each correction pixel value in the correction array and providing an output image array based on the correction array and the input image array. |
| US09508123B2 |
Image direction determination
In one example embodiment, a device includes an object detector configured to: rotate an image multiple times in increments of a predetermined number of degrees, detect upright occurrences of at least one object from the image at each incremental rotation of the image, and divide the detected occurrences of the at least one detected object, at each incremental rotation of the image, into a corresponding classification; and a direction manager configured to: determine a normal direction of the image, based on a number of detected occurrences of the at least one detected object, at each incremental rotation of the image, for each corresponding classification. |
| US09508121B2 |
Method and apparatus for controlling spatial resolution in a computer system by rendering virtual pixel into physical pixel
A computer implemented method of producing output pixels for a graphics system includes the steps of receiving one or more input pixels from the graphics system; performing rendering operations on the one or more pixels, wherein the rendering including the steps of: selecting one or more pixels of interest the resolution of which are to be increased; defining a sampling grid or a sampling orientation; multi sampling the one or more pixels of interest having a first resolution and multiple sampling points; collecting information from each sampled point; storing information from each sampled point as a virtual pixel; defining one or more pixels the resolution of which are one of to remain the same as received from the graphics system or the resolution of which are to be reduced; and rendering pixels of interest in a higher resolution than the their first resolution by rendering each virtual pixel into a physical pixel in a displayable frame or offscreen buffer. |
| US09508120B2 |
System and method for computer vision item recognition and target tracking
A system for recognizing objects under different environmental conditions by manipulating an original image with light and animation effects in real time and comparing the result with an input frame. This improves the ability of the system to detect and recognize a matching real world object in a variety of conditions. 3D rendering techniques are used to create a new and more accurate reference model as compared to current static object descriptions. The system is implemented on a computer with GPU capabilities. The real world object to be recognized is configured in the system as a 3D object, and is manipulated to create custom environmental conditions that can be adjusted by the user to optimize detection and recognition in an environment appropriate for each user. |
| US09508119B2 |
Application of filters requiring face detection in picture editor
An electronic device and method of operation, the electronic device including at least one processor communicatively coupled to a display and memory, the processor configured for filtering a facial image rendered on the display. In an illustrative embodiment, the at least one processor is configured to generate a boundary around the facial image, the boundary having 2-dimensional x and y coordinates relative to boundaries of the display; store the coordinates in memory; in response to at least one of a cropping and moving of the image, recalculate the coordinates to match a new transform setting; and apply an effect to the facial image based on the updated coordinates. |
| US09508113B2 |
Pipeline system including feedback routes and method of operating the same
A pipeline system includes input buffers, a relay for controlling withdrawal of data stored in the input buffers, and functional blocks for performing one or more processing operations. A method of operating a pipeline system includes withdrawing data from one of input buffers and performing different one or more processing operations. |
| US09508111B1 |
Method and system for detecting a display mode suitable for a reduced refresh rate
A method and system for detecting a display mode suitable for a reduced display refresh rate are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a memory and a processing unit. The memory stores multiple image surface data. The processing unit is configured to compose a first display frame from a first base surface and optionally a first overlay surface, calculate a first numerical code representative of a first frame content of the first display frame, compose a second display frame from a second base surface and optionally a second overlay surface, calculate a second numerical code representative of a second frame content of the second display frame, and track the results of comparing the first numerical code with the second numerical code to determine whether a change between the first frame content and the second frame content has occurred. |
| US09508107B2 |
Intelligent barcode systems
Systems and methods using intelligent barcodes for processing mail, packages, or other items in transport are provided. Systems and methods allowing end-to-end visibility of a mail stream by uniquely identifying and tracking mail pieces are also provided. Systems and methods include the use of standardized intelligent barcodes on mail pieces, a seamless process for mail acceptance, continuous mail piece tracking, and feedback on mail quality in real time. In one embodiment, systems and methods using intelligent barcodes allow a mailing service to provide enhanced acceptance, sorting, tracking, address correction, forwarding, and delivery services. In another embodiment, systems and methods using intelligent barcodes allow a mailing service to identify a mail piece as undeliverable-as-addressed (UAA) and determine a final disposition for the mail piece. In yet another embodiment, systems and methods using intelligent barcodes allow mailers more visibility into the mail stream and information on the quality of their mailings. |
| US09508106B1 |
Method and system for provisioning of dental implants and related services
The present invention relates to a system and method for dental implant and restorative services. By locating the key functions at one physical location, dental implant services are efficiently provided to patients. These functions include a treatment coordinator, a direct marketer, a restorative doctor/prosthodontist, a surgeon, an imaging area, and a dental laboratory, Further, services for dentate patients are improved by utilizing advanced dental implant methods and systems. These methods and systems include both model-based services and CT (computed tomography) guided surgery services. Using these services, improved surgical guides for dental implants are constructed. |
| US09508104B2 |
Question routing for user communities
A computer-implemented method routes a current question to one or more of a plurality of online communities. A computer system can determine, for the current question presented by an asking user a plurality of question-to-question similarity values, a plurality of question-to-user similarity values and a plurality of question-to-community similarity values. The system can select one or more of the plurality of online communities based on the similarity values. The system can route the current question presented by the asking user to the selected one or more of the plurality of online communities. |
| US09508103B2 |
Deferred social network check-in
A system and method is disclosed for sharing previously visited locations in a social network. A mobile computing device (for example, a smartphone) may be configured to receive and transmit a token to a server, the token including event information related to an event at a previously visited location. One or more candidate places of interest are then determined based on the event information, and provided for display to a user of the mobile computing device. The user selects one or more selected places of interest from the candidate places of interest, and the server provides, for display to one or more other users in a social network, a representation of the user and the selected places of interest. |
| US09508097B2 |
Method and system to conduct electronic commerce through motion pictures of life performance events
Systems and methods for enabling a viewer of a motion art form to select an object of interest from within the motion art form are disclosed. The system includes a computing device configured to: receive at least one selection signal from at least one viewer; synchronize the at least one selection signal with an elapse time of the motion art form; and transmit the at least one selection signal to a destination. |
| US09508096B2 |
Method and system for creating and processing personalized gift cards
A method for processing a personalized gift card transaction includes: receiving a gift card request from a consumer associated with a payment account, the request including a usage amount, a plurality of merchant identifiers, an account identifier associated with the payment account, and a message; identifying a personalized gift card number; storing a gift card data entry including the personalized gift card number, usage amount, plurality of merchant identifiers, account identifier, and message; transmitting the personalized gift card number; receiving an authorization request for a financial transaction not involving the consumer, the request including the personalized gift card number, a transaction amount, and at least one merchant identifier of the plurality of merchant identifiers; processing the financial transaction including updating, in the database, the usage amount of the gift card data entry based on the transaction amount; and transmitting the message to a recipient of the personalized gift card. |
| US09508095B2 |
System and method for optimizing the selection of cloud services based on price and performance
A system and method is provided for generating and using purchase strategies based on the price, performance, and/or other information related to cloud services to optimize the selection of such services. The purchase strategies may comprehensively describe various cloud services in real-time so that customers may purchase cloud services using up-to-date, real-time information. The purchase strategies may, for example, describe pricing, performance, availability, and/or other attributes of various cloud services. A purchase agent may use the purchase strategies, one or more purchase rules, and/or other information to generate a purchase specification that specifies one or more cloud service instances that should be purchased. The purchase agent may leverage unique properties of spot instances to make favorable purchase decisions. For example, the system may determine bid prices that should be made to obtain certain spot instances. |
| US09508093B2 |
Apparatus, method and system for electronic gifting
Electronic gifting is performed using various devices, servers, and other system nodes on a network. A gifting server and a transaction facility server associated with a transaction facility have access to the network. A donor's personal electronic device and a recipient's personal electronic device also have access to the network. Both the donor personal electronic device and the recipient personal electronic device may be enabled with the light-simulated barcode technology and/or NFC technology. Financial systems such as, for example, credit card systems, banking systems, and loyalty card systems may also have access to the network, or may be directly accessible to the transactions facility systems. |
| US09508088B2 |
Advertisement delivery management apparatus and advertisement delivery management method
An advertisement delivery management apparatus according to an embodiment includes an acquisition unit, a determination unit, and an accepting unit. The acquisition unit acquires information on two or more types of delivery target user groups, each including a plurality of delivery target users predicted as future advertisement delivery destinations. The determination unit determines whether each of the delivery target user groups satisfies delivery conditions designated by an advertisement delivery order request. The accepting unit accepts the advertisement delivery order request based on the determination result of the determination unit. |
| US09508086B2 |
Methods and apparatus to monitor, verify, and rate the performance of airings of commercials
Methods and apparatus to monitor, verify, and rate the performance of airings of commercials are disclosed. An example method includes analyzing received advertisement detection information associated with the advertisement, the advertisement detection information detected from a presentation of the advertisement; identifying a buy order corresponding to the presentation of the advertisement based on the advertisement detection information; determining a purchased ratings value from the buy order; comparing the purchased ratings value of the buy order to received ratings information corresponding to the presentation of the advertisement to determine whether the advertisement was presented as indicated in the buy order; and generating a performance monitoring report using the buy order and the advertisement detection information to indicate whether the ratings information is less than the purchased ratings value. |
| US09508085B2 |
Pipeline arrangement for utilizing a gas comprising biomethane
Embodiments of the invention provide a process in which a gas comprising biomethane having a heating value of less than about 925 BTU/cubic foot is introduced to a pipeline system that is connected to at least one source of natural gas having a heating value of at least about 950 BTU/cubic foot. The gas comprising biomethane combines with natural gas in the pipeline system to produce a mixed gas having a heating value below about 925 BTU/cubic foot. An amount of natural gas at least equal to the amount of gas comprising biomethane is withdrawn from the pipeline system for use as a transportation fuel, a fuel intermediate or as a feedstock for producing a fuel. The process can enable fuel credit generation and/or reductions in life cycle greenhouse gas emissions. |
| US09508083B2 |
Extensibility for sales predictor (SPE)
Disclosed are methods and systems for implementing extensibility in sales prediction engines. An extensibility framework may be used to modify the metadata schema of the data used by the sales prediction engine to account for extended attributes and entities. The sales prediction engine is also modified to recognize the extended attributes and entities so that a user will be able to create new rules and train new models based on the extended attributes and entities. |
| US09508077B2 |
Podcasting having inserted content distinct from the podcast content
Disclosed herein are systems, devices, and methods for providing a podcast file that has inserted content that is distinct from the content of the podcast. A remote server provides a web page to a subscriber computing device via a network, and a subscriber computing device transmits a podcast file to the remote server via the network. The remote server inserts content into the podcast file and provides the podcast file along with the inserted content for access from the web page. The remote server transmits the podcast file along with the inserted content responsive to requests from the subscriber computing devices. The subscriber computing devices can process and play the podcast content along with the inserted content from the remote server. |
| US09508074B2 |
Method for secure use of identification cards
A method for approving or refusing a transaction is based on the use of an identification card having card data thereon, the card data identifying account information pertaining to the authorized user of the identification card. The method includes storing issuer secondary security data in association with the account information. A transaction approval request is received from a vendor, the transaction approval request including the card data and transaction secondary identifier (secondary ID) data. The transaction is refused if the transaction secondary ID data does not correlate properly to the stored issuer secondary security data. Optionally, a post-transaction confirmation request is issued if the transaction is not refused. |
| US09508073B2 |
Shareable widget interface to mobile wallet functions
Configuring a shareable widget interface to mobile wallet functions includes disposing a wallet module in a memory of a client device, and disposing a wallet companion applet in a secure element accessible by the client device, wherein the wallet companion applet facilitates access by at least one other applet and at least one wallet module to content that is stored in the secure element via a mobile wallet function sharable interface. |
| US09508071B2 |
User authentication method and device for credentials back-up service to mobile devices
Back-up credentials data is stored for a user. A communication channel is established with a mobile device. A cryptogram is received from the mobile device, such that the cryptogram is relayed by the mobile device from an authentication device that interacted with the mobile device. The authentication device is associated with the user. The cryptogram is verified. In response to the verification of the cryptogram, the stored back-up credentials data is made accessible to the mobile device. |
| US09508067B2 |
System, program product and methods for retail activation and reload associated with partial authorization transactions
Systems, program product, apparatus and method for transmitting and processing the sale of a transaction card product over an existing payment network using partial authorization messaging, are provided. An example of such a system can include a merchant POS apparatus equipped to support partial authorization messaging, a transaction card issuer server in communication therewith, and a transaction card product. The transaction card product can include a conventional transaction card securely wrapped within a tamper evident container that can carry its own magnetic strip. The container magnetic strip can store an assigned unique card identifier linked to, but different from, the card identifier normally associated with the card. The container card identifier stored in the container magnetic strip is compatible with the merchant POS card reader and is usable to activate the card without the merchant or consumer having access to the card, the card identifier, or the card magnetic strip. |
| US09508064B2 |
Kiosk gift card system and method
A kiosk gift card system and method for purchasing and redeeming gift cards is disclosed. The system/method includes a gift card distribution kiosk that provides a user with access to a multitude of different forms of gift cards that may be purchased and printed onto customizable gift card stock. The kiosk includes a kiosk processor interface, a gift card dispenser, a card reader, and gift card management server connected to a network. The gift card management server, through the kiosk processor interface, provides vendor options to users to select and pay via the card reader. The kiosk may be used to redeem unused user gift cards for a reduced value user selected gift card, reduced cash value, full value store card, rewards points, bank debit, and/or an electronic code (eCode) towards online user purchases. |
| US09508056B2 |
Electronic note taking features including blank note triggers
Embodiments provide electronic note-taking and application features and functionality, but the embodiments are not so limited. In an embodiment, a computer-based method can be configured to provide note-taking features, including using blank notes as focus placeholders and resurfacing triggers. Other embodiments are included. |
| US09508054B2 |
Extracting purchase-related information from electronic messages
Product order and shipping information received via email messages is automatically aggregated for ready user review. Once the user is authenticated, authorization to access their email mailbox is obtained and the email message headers of their emails are analyzed to identify those messages of interest. The bodies of the email messages of interest are parsed to extract the product order and shipping information which is stored and presented for display to the user typically grouped by individual product thus greatly simplifying user review of orders. The aggregated product order and shipping information can be augmented with additional information such as shipping status, delivery status, a product image, and/or a last date that the product can be returned. |
| US09508050B2 |
Executing a business process in a framework
Various embodiments of systems and methods for executing a customized business process in a business process framework are described herein. A user selection of a solution type corresponding to a business process is received from a user interface. In response to the user selection, a query is executed to retrieve application types and corresponding sub-application types from a business logic stored in a database. Configurable attributes are generated based upon the application types and the corresponding sub-application types. Based upon the application types, the sub-application types and the configurable attributes, the business process is customized to create a customized business process. Based upon a configuration information, a user input to the customized business process is captured from the user interface. The user input is validated by comparing the user input with the business logic. The customized business process that is validated is further executed in the business process framework. |
| US09508045B2 |
Continuous-time baum-welch training
The apparatus, systems, and methods described herein may operate to receive information identifying and describing at least one of a set of events, an initial distribution of a plurality of states, an initial transition matrix, or an initial event matrix; generate, based at least in part on the information, at least one intermediate transition matrix and at least one intermediate event matrix describing a sparse Baum-Welch training that allows no event to occur at one or more time steps; and transform the at least one intermediate transition matrix and the at least one intermediate event matrix into a transition matrix and an event matrix describing a continuous-time Baum-Welch training, the continuous-time Baum-Welch training allowing events to occur simultaneously or at sporadic time intervals in a Markov model including a hidden Markov Model (HMM) having more than two hidden states. |
| US09508044B1 |
Method and apparatus for managing configurations
A method and apparatus for managing configurations of computer resources in a datacenter is described. In one embodiment, a method comprises analyzing multiple configurations using rule information to produce an analysis result where each configuration in the multiple configurations defines a configuration of a resource that is managed by the data center, training a Bayesian classifier using the analysis result, and classifiying a second configuration using the trained Bayesian classifier. |
| US09508039B2 |
Deployment pattern realization with models of computing environments
Deployment pattern matching is implemented by accessing a target computing environment model that captures environment modeling parameters relating to resources and resource-resource relationships of a corresponding computing environment and expressing the target computing environment model as a model graph defined by target resource elements and resource-to-resource relationship links. Deployment pattern matching is further implemented by accessing a realization pattern that captures deployment parameters relating to resources and resource-resource relationships of a deployment of interest and expressing the realization pattern as a pattern graph defined by conceptual resource elements and constraints arranged by resource-to-resource relationship links and constraint links. The realization pattern is then evaluated against the target computing environment model by executing at least one pattern matching algorithm that attempts to match the pattern graph to the model graph and information corresponding to results of the evaluation are conveyed. |
| US09508034B2 |
Multi-frequency bulk RFID tag commissioning
A system and method for the rapid bulk commissioning of RFID tags includes exploiting simultaneous writing of plural tags via isolated communications bands, avoiding write acknowledgement, collision/retransmission, and other delays. |