| Document | Document Title |
|---|---|
| US09485229B2 |
Object level encryption system including encryption key management system
A symmetric PGP encrypted communications path is provided in which the recipient may be identified with only publicly available information. Data to be encrypted is encrypted at the object level. Encryption keys for both the transmitter and receiver are sent to a security server. Data received from the transmitter includes intended receiver ID. The receiver includes its actual ID. The received ID and the actual ID are sent to the security server for authentication. If authentication succeeds, the security server sends a session key to the receiver, and the receiver can use its own key to decrypt data. The system reacts to authentication failure by disabling decryption in the receiver and may also take countermeasures. |
| US09485221B2 |
Selective content cloud storage with device synchronization
Programmable devices selectively allocate file content portions between cloud and secured hardware device storage mediums. A confidential portion of a first file is stored as a second file on a first device, and a remainder portion of content of the first file that is different from the confidential portion and is not designated as confidential is stored on a cloud storage system. A uniform resource indicator is generated that includes a routing identifier to the first device, and a section routing identifier to the second file stored on the first device. A revised version of the first file is stored to the cloud storage system wherein the confidential portion of the first file is replaced with the generated uniform resource indicator within the revised version of the first file at a location of the confidential portion within the content of the first file. |
| US09485217B2 |
Method for configuring network nodes of a telecommunications network, telecommunications network, program and computer program product
A method for configuring network nodes of a telecommunications network includes configuring a remote network node of a plurality of remote network nodes based on a first set of configuration parameters; authenticating the remote network node based on an encryption information obtained from an encryption information infrastructure; configuring a firewall entity of a plurality of firewall entities based on a second set of configuration parameters, wherein the configuration of the firewall entity is initiated by the remote network node based on an initial configuration message being sent directly or indirectly from the remote network node to the firewall entity; and authenticating the configuration of the firewall entity based on the encryption information of the remote network node, the encryption information being obtained by the firewall entity directly or indirectly from the remote network node with the initial configuration message. |
| US09485209B2 |
Marking of unfamiliar or ambiguous expressions in electronic messages
A method comprising using at least one hardware processor for constructing an index of corpora of multiple users, wherein each corpus of said corpora is associated with a single user of said multiple users, analyzing an electronic message addressed at least to one of said multiple users, to identify an expression which, based on the index, is likely to be unfamiliar or ambiguous to said one of the multiple users, and marking the expression in the electronic message. |
| US09485202B2 |
Alerting recipients to errors occurring when accessing external services
A hosting provider operates a server system that provides a service to one or more tenants. The server system receives configuration data from the tenants. As part of providing the service to a given tenant, the server system attempts to access an external service due to the configuration data received from the given tenant identifying the external service. Service access errors can occur when attempting to access the external service. In response to determining that an error has occurred when attempting to access the external service, the server system sends a service access alert to a recipient associated with the given tenant. The service access alert notifies the recipient that the error has occurred. |
| US09485199B2 |
System and method for data flow identification and alignment in a 40/100 gigabit ethernet gearbox
A system and method for data flow identification and alignment in a 40/100 gigabit Ethernet gearbox. Virtual lane (VL) identifiers can be identified to create an effective wiring diagram for data flows. This wiring diagram enables a multiplexer or de-multiplexer to align the VL identifiers to match physical lane identifiers. |
| US09485198B1 |
Methods and apparatus for multicast traffic failover in a network
An apparatus includes an access switch having a set of ports and configured to be operatively coupled to a multicast router via a first port from the set of ports. The access switch is configured to be associated with a network associated with the multicast router, and designate the first port as a multicast-router interface during a time period. The access switch is configured to send a message to the multicast router via each port from the set of ports in response to an indication of a change in a topology of the network after the time period. The access switch is configured to designate a second port from the set of ports as the multicast-router interface and dedesignate the first port as the multicast-router interface in response to receiving, via the second port and in response to the message, a signal from the multicast router. |
| US09485189B2 |
Transfer device, and transfer method
A transfer device allocates, within the range of the maximum communication band of a network that a plurality of groups of applications use in common, a communication band equal to or larger than the minimum band for each of the groups. Furthermore, the transfer device converts, within a communication band allocated to each group, TCP data received from a transmission source of data to UDP data, transfers the UDP data to a transmission destination, and retransmits retransmission data in response to a retransmission request of the UDP data. |
| US09485181B2 |
Dynamic bandwidth adjustment in packet transport network
A method for adjusting bandwidth in a communications network having a plurality of nodes connected over multiple links with a plurality of services running on the links includes detecting an impairment of a link wherein the impairment invokes a reduction in bandwidth available to the services running on the link, communicating information about the impairment to other nodes in the network and redistributing services between the links to limit a bandwidth required by services running on the impaired link to a value not exceeding the bandwidth available on the impaired link. |
| US09485174B2 |
Routing using cached source routes from message headers
In one embodiment, an intermediate node of a computer network can receive a message intended for a destination. The message can include a header indicating a source route. The intermediate node can determine a routing entry for a routing entry for the destination associated with a next hop based on the source route and cache the routing entry. The intermediate node can further receive a second message intended for the destination that does not indicate the next hop, and transmit the second message according to the cached routing entry. |
| US09485172B2 |
Data transmitting device, data transmitting method and non-transitory computer-readable storage medium
A data transmitting device coupling to a plurality of nodes in a network includes a plurality of communication paths, the data transmitting device includes a memory and a processor coupled to the memory configured to set a routing table based on a command that designates a first communication path included in the plurality of communication paths, to detect a link failure occurred in the network, and when the link failure has occurred at a first location between the data transmitting device and a first node adjacent to the data transmitting device on the first communication path, to modify the routing table so that data are to be transmitted to a second node on a second communication path different from the first communication path, and when the link failure has occurred at a second location that differs from the first location in the network, to maintain the routing table. |
| US09485170B2 |
Systems and methods for fractional routing redundancy
Systems and methods for fractional routing are described. An exemplary method may include receiving, by a first router, data information regarding routing by a first portion of a third router, receiving, by a second router, data information regarding routing by a second portion of a third router, wherein the data information regarding routing by the first portion and data information regarding routing by the second portion is not the same, routing, by the first router, data associated with the routing by the first portion of the third router, and routing by the second router, data associated with the routing by the second portion of the third router. |
| US09485168B2 |
Temperature sensitive routing of data in a computer system
An apparatus and method routes data over network links based on a temperature of the network links. When the temperature of a link meets a first threshold a routing mechanism re-routes a portion of the network traffic over a lower temperature link to reduce the likelihood that the link will exceed a second threshold that necessitates that the link be throttled back or disabled. Re-routing data to cooler links allows the system to maintain the lowest possible temperature of the network links to gain optimal performance of the system. In the disclosed example, the network links include interconnect cable connections and backplane connections. A temperature of the network links is determined by monitoring a region of an integrated circuit near a line driver driving the network link. |
| US09485167B2 |
Communication device and address learning method
A processor determines, when a frame is received, whether a total of current learning numbers stored in a second storage unit has reached a total of maximum learning numbers. The processor identifies in the second storage unit, if it is determined that the total of current learning numbers has reached the total of maximum learning numbers, a first group identifier associated with a lower priority than a priority associated with a reception group identifier contained in the frame. The first group identifier is associated with a first current learning number not less than a first minimum learning number associated with the first group identifier. The processor replaces a first correspondence relationship including the first group identifier with a reception correspondence relationship among a port number of a port at which the frame has been received, a source address contained in the frame, and the reception group identifier. |
| US09485166B2 |
Network abnormality detection system, measurement apparatus, and analysis apparatus
In a communication system in which a plurality of communication apparatuses perform communication via a communication network, a network abnormality detection system dynamically creates a monitoring rule during operation without defining information (monitoring rule) regarding communication to be monitored in advance and perform a collection process and an abnormality determination process quickly even when an amount of information to be monitored is vast. The network abnormality detection system copies packets transmitted at predetermined measurement positions in the communication network, calculates communication statistics information at each measurement position from the copied packets, analyzes one or more pieces of communication statistics information, and detects occurrence of communication abnormality. |
| US09485159B1 |
Rules-based network service management with on-demand dependency insertion
Techniques are described for managing network services deployed in a network using a rules engine with on-demand dependency insertion. A network service manager may use a rules engine to monitor a network service at network devices in order to detect a device-level event, and determine a service-level impact of the detected event based on network service rules and dependencies. The dependencies define links between the device-level event and actions triggered by the device-level event. According to the techniques, a rules engine is configured to detect a device-level event and, in response, insert only those dependencies associated with the detected device-level event into a working memory. Once the device-level event has been cleared, the dependencies related to the device-level event are removed from the working memory. The working memory, therefore, will include only the dependencies needed to determine service-level impacts of currently detected device-level events. |
| US09485158B1 |
Methods for aggregating per-session statistics on a clustered system and devices thereof
A method, non-transitory computer readable medium and an multi-blade network traffic manager device that assists with aggregating per-session statistics on a clustered system includes receiving a request for a HTTP transaction. Presence of a cookie within the received request is determined. One or more actions is performed based on the determination of the presence of the cookie to prepare for aggregating session statistics within a clustered system. Session statistics information is aggregated upon performing the one or more actions and completing the request for the HTTP transaction. |
| US09485155B2 |
Traffic analysis of data flows
A device includes a memory, flow table logic, sampling logic, and a processing unit. The memory is configured to store a flow table that stores, as a number of entries, statistics regarding a number of data flows. The flow table logic is configured to generate records corresponding to data flows for which entries are created in the flow table or removed from the flow table. The sampling logic is configured to select one of the data flows for sampling and sample initial data units for the one of the data flows. The processing unit is configured to receive the records generated by the flow table logic, receive the initial data units sampled by the sampling logic, analyze the initial data units to generate analysis results, correlate the records and the analysis results associated with a same one of the data flows, and store the correlated records and analysis results. |
| US09485154B2 |
Multiple-pipe techniques and multiple optical streams for managing over-the-top traffic
Methods and apparatus for managing an over-the-top data traffic flood using multiple-pipe techniques are provided. For example, provided is a method for routing Internet data including receiving the Internet data at a carrier portal, as well as classifying the Internet data based on criteria specified by the carrier, such as a quantity of payment from at least one of a user of the Internet data to a provider of the Internet data. The classified data is transmitted via one of a plurality of ports, where port selection is based on the classification. Each of the ports in the plurality of ports is coupled to a respective one of a plurality of independent data transport networks and/or separate optical paths. The data transport networks and/or separate optical paths can differ in capacity and/or latency. |
| US09485152B2 |
Web server and method for hosting a web page for presenting location based user quality data related to a communication network
A web-server communicates wireless networking performance data that reflects the true user experience of a mobile device operating in a particular location and operating on a particular wireless network. |
| US09485149B1 |
Routing device having multiple logical routers
Techniques are described for implementing one or more logical routers within a single physical routing device. These logical routers, as referred to herein, are logically isolated in the sense that they achieve operational and organizational isolation within the routing device without requiring the use of additional or redundant hardware, e.g., additional hardware-based routing controllers. The routing device may, for example, include a computing platform, and a plurality of software process executing within the computing platform, wherein the software processes operate as logical routers. The routing device may include a forwarding component shared by the logical routers to forward network packets received from a network in accordance with the forwarding tables. |
| US09485146B1 |
Providing services using a device capabilities service
Systems and methods for providing a service to a device based on a capability of the device are described herein. A device type of the device may be identified based on information associated with the device. A determination may be made whether the device supports the service, based at least on the device type. The service may be provided to the device when the device supports the service. |
| US09485145B1 |
System, method, apparatus, and computer program product for determining a configuration of a converged infrastructure
A system, method, apparatus, and computer program product for determining a configuration of a converged infrastructure are disclosed. A method may include performing a scan of network addresses for components of the converged infrastructure. The method may further include capturing fingerprints of components discovered by the scan. The method may additionally include identifying the components discovered by the scan based at least in part on a comparison between each captured fingerprint and one or more known component fingerprints in a fingerprint library, which may include a set of known component fingerprints and associated component identities. The method may further include accessing at least one identified component. The method may also include determining a component configuration of each of at least one accessed component. |
| US09485142B2 |
Method and apparatus for dynamic DL-UL reconfiguration in TDD system
Embodiments of the disclosure provide a method and apparatus for reconfiguring DL-UL resource allocation in a TDD system. The method includes steps of: a) obtaining traffic condition about DL and UL data to be transmitted; b) estimating system-wise transmission capability and/or UE-wise transmission capability, wherein the system-wise transmission capability accounts for DL transmission capability and UL transmission capability of the TDD system, and the UE-wise transmission capability accounts for transmission capabilities of different UEs; and c) reconfiguring the DL-UL resource allocation according to the obtained traffic condition and the estimated system-wise transmission capability and/or UE-wise transmission capability. |
| US09485140B2 |
Automatic proxy setting modification
The proxy settings for a browser are modified to route public Internet traffic through a local client assistant, while keeping previous proxy policies intact. The process compares the previous proxy results for a known, public Internet address to the previous proxy results for the desired Internet address. If the two proxy results are equivalent, then the request is directed to the local client assistant, otherwise the request is directed according to the previous proxy results. If the testing of the public Internet address had resulted in the use of a proxy, then the local client assistant will route its requests to the proxy so indicated. |
| US09485138B1 |
Methods and apparatus for scalable resilient networks
In some embodiments, an apparatus includes a first controller configured to be operatively coupled within a network having a set of network nodes, a forwarding gateway and a configuration entity. The first controller is configured to manage session state and node state associated with the set of network nodes independent of the forwarding gateway. The first controller is configured to fail over to a second controller when the first controller fails, without the forwarding gateway failing over and without the configuration entity failing over. |
| US09485137B2 |
Online reconfiguration transition synchronization
An online reconfiguration method comprising communicating data transfer units (DTUs) using a subscriber line, monitoring the subscriber line for a line condition event, detecting the line condition event, wherein detecting the line condition event comprises determining whether the line condition triggers a threshold, sending an online reconfiguration request message that indicates a robust management channel (RMC) frame type in response to detecting the line condition event, wherein the RMC frame type is a normal RMC frame that comprises time marker information when the line condition event does not trigger the threshold, and wherein the RMC frame type is a special RMC frame that comprises time marker information when the line condition event triggers the threshold, receive an online reconfiguration response message that comprises the time marker information, and synchronizing a transition of one or more transmission parameters using the time marker information. |
| US09485136B2 |
Repair of failed network routing arcs using data plane protocol
A network includes multiple routing arcs for routing network traffic to a destination. Each arc comprising nodes connected in sequence by reversible links oriented away from a node initially holding a cursor toward one of first and second edge nodes through which the network traffic exits the arc. Each node includes a network device. The nodes in the arc detect a first failure in the arc. Responsive to the detecting the first failure, the nodes exchange first management frames over a data plane within the arc in order to transfer the cursor from the node initially holding the cursor to a first node proximate the first failure and reverse links in the arc as appropriate so that the network traffic in the arc is directed away from the first failure toward the first edge node of the arc through which the network traffic is able to exit the arc. |
| US09485134B2 |
Managing configurations of system management agents in a distributed environment
A method, system and computer program product for managing system management agent configurations which include agent system management programs and program parameters in a distributed environment. A configuration management server sends upon request from the agents installed on the distributed system a description of their configuration. To this effect, the configuration management server maintains a database storing the agent configuration information, this database being usually updated by a system management administrator. The agents get from the server the list of peer distributed systems having the same agent configuration and their configuration from one distributed system of the list or obtain an agent configuration directly from the configuration management server if the peer distributed systems have modified their configuration. The agents advise the system management server when a new configuration has been installed. |
| US09485131B2 |
Multilayer network connection communication system, smart terminal device, and communication method thereto
A multilayer network connection communication system includes a mobile device, a smart terminal device, a service server, a first layer network, and a second layer network. The mobile device sends at least one inquiry message through the first layer network to inquire the smart terminal device whether the smart terminal device supports at least one first application. Among the at least one first application, the smart terminal device supports at least one second application including a third application. The smart terminal device requests the mobile device through the first layer network to start up the at least one second application, where the third application is started up to respond to the at least one startup message. The smart terminal device receives a user data from the mobile device through the first layer network and transmits the user data to the service server through the second layer network. |
| US09485127B2 |
OFDM communications
Disclosed is a wireless transmitter comprising: a module configured to modulate input data bits into data symbols according to a predetermined modulation scheme, and group the data symbols into one or more precoding blocks; at least one symbol insertion module, each configured to insert one or more cancellation symbols into a corresponding precoding block; at least one precoding module, each configured to precode a corresponding precoding block; a subcarrier insertion module configured to concatenate the one or more precoded blocks and to insert at least one cancellation subcarrier into the concatenated precoded blocks to form a precoded OFDM symbol; a module configured to process the precoded OFDM symbol so as to reduce the out-of-band power emitted by the transmitter in transmitting the precoded OFDM symbol, wherein the processing uses the inserted cancellation symbols and cancellation subcarriers; and a module configured to transmit the processed precoded OFDM symbol over a wireless communication channel. |
| US09485125B2 |
Dynamically reconfigurable channelizer
Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object. |
| US09485124B2 |
Method and apparatus for multiple bit encoding
Methods and apparatus for encoding data for wireless transmission are disclosed in which a data message may be encoded into a transmission code as a first coding format and a second coding format. The first coding format characterized by a first bit representation and the second coding format characterized by a second bit representation different from the first bit representation. The transmission code may be transmitted having the first and second coding formats. |
| US09485120B1 |
Method and apparatus for signal detection and baseline wander cancellation
Apparatus, methods, and other embodiments associated with reliably determining signal loss over a data communication channel have been described. According to one embodiment, a method includes receiving input signals at an input of a serializer/deserializer device and equalizing the input signals to form equalized signals which compensate for frequency response distortion. The method also includes analyzing the equalized signals to determine whether peak amplitudes of the equalized signals are within a range of amplitudes defined by two threshold values. Furthermore, the method includes analyzing the equalized signals to determine whether logic levels of the equalized signals correspond to a sequence of a same logic level. The method further includes generating a signal absent indicator when the peak amplitudes of the equalized signals are within the range, or when the logic levels of the equalized signals correspond to the sequence of the same logic level. |
| US09485118B1 |
Penalty-box policers for network device control plane protection
In general, techniques are described for dynamically controlling host-bound traffic by dynamically adding and updating, within the forwarding plane of a network device, network packet policers that each constrains, for one or more packet flows, an amount of host-bound traffic of the packet flows permitted to reach the control plane in accordance with available resources. In one example, a control plane of the network device detects internal congestion in the communication path from the forwarding plane to control plane (the “host-bound path”), identifies packet flows utilizing an excessive amount of host-bound path resources, computes limits for the identified packet flows, and adds “penalty-box policers” configured with the computed limits for the identified packet flows to the forwarding plane. The forwarding plane subsequently applies the policers to the identified packet flows to constrain the amount of traffic of the packet flows allowed to reach the control plane to the computed limits. |
| US09485117B2 |
Providing user-controlled resources for cloud computing environments
A cloud management system can be configured to offer a marketplace for user-controlled resources provided by third party users by performing a valuation for user controlled resources offered to the cloud. The cloud management system can be configured to determine the usage of cloud resources, demands on the clouds resources, and revenue generated by the cloud resources and determine a value for user-controlled resources based on the usage, demands, and revenue. Once the value is determined, the cloud management system can be configured to provide an indication of the value to a set of the third party users. If offered and accepted, the cloud management system can be granted access to the user-controlled resources and allocate the user-controlled resources to the cloud. |
| US09485115B2 |
System and method for enabling conversational learning in a network environment
A system and a method for providing conversational learning is implemented in a network environment. An exemplary method includes receiving a subnet route advertisement that includes an attribute that triggers glean behavior for routing decisions; and installing a subnet entry in a Forwarding Information Base/Adjacency (FIB/ADJ) table. The subnet entry includes a subnet associated with the subnet route advertisement and a corresponding glean adjacency. The corresponding glean adjacency is configured to trigger installation of a host entry associated with a host in an active conversation in a network. |
| US09485113B2 |
Data communications network for an aircraft
A method of providing current operation data for a plurality of data generating components connected to a data communications network. The network may include input units that generate data and subscribing units that require the generated data to function. The generated data may be formatted or processed in a manner so that it can be used by the subscribing units. The formatted and processed data may then be supplied to the subscribing units. |
| US09485112B2 |
Home control gateway and gateway control method thereof
A home control gateway and a gateway control method are provided. The home control gateway includes a gateway management module, a storage module, and first and second communication circuits. The gateway management module includes a plurality of switches and a user interface for controlling the switches. The first communication circuit receives an incoming called-signal via a mobile phone network. The gateway management module opens a first switch when an incoming called-number corresponding to the incoming called-signal is identical to a pre-stored phone number in the storage module. The second communication circuit receives a connection request for accessing the user interface and instructing to open a second switch via a local area network, where the gateway management module opens the second switch in response to the connection request. The gateway management module activates a home control function corresponding to the second switch when the first and second switches are both opened. |
| US09485109B2 |
Carrier aggregation methods of broadcast channels with broadcast channels or broadcast channels with unicast channels
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be a UE. The UE monitors a first component carrier and at least one second component carrier of a plurality of aggregated component carriers for a service and configuration information associated with the service. The UE receives the service concurrently via the first component carrier and the at least one second component carrier. At least one of the first component carrier or the at least one second component carrier carries the service via broadcast. |
| US09485107B2 |
System and method for distributed internet group management protocol processing
A method may include receiving, at a network interface of a first network element, an Internet Group Management Protocol (IGMP) message from a second network element. The method may also include updating first multicast group data associated with the network interface based on the received IGMP message, the first multicast group data including one or more entries setting forth a multicast group and one or more other network elements which are members of the multicast group. The method may additionally include determining whether the second network element is the sole member of its multicast group based on the IGMP message and the first multicast group data. The method may further include forwarding the IGMP message to a switching element of the first network element in response to determining that the second network element is the sole member of its multicast group, the switching element communicatively coupled to the network interface. |
| US09485097B2 |
Device, system, and method for registering and authenticating handwritten signatures and archiving handwritten information
There is provided an electronic pen device configured to be used with a remote secure server for registering handwritten signatures, the secure server comprising an authentication database storing authentication information in connection with pre-registered users and a signature registration database for registering handwritten signatures, the electronic pen device comprising: an input/output (I/O) interface; a memory; a tip and capturing means connected thereto for capturing handwritten signatures; a network interface adapted to be connected to a data network, and a processing unit connected to the I/O interface, to the capturing means, to the memory and to the network interface. As another aspect of the invention, there is further provided a system for registering handwritten signatures. As another another aspect of the invention, there is further provided a method of authenticating handwritten signatures. As a further aspect of the invention, there is provided a method of signing a document by a plurality of contracting user. As a further further aspect of the invention, there is provided an electronic pen device configured to be used with a remote server for archiving handwritten information. |
| US09485096B2 |
Encryption / decryption of data with non-persistent, non-shared passkey
The method herein teaches encrypting a Private Key using a Passkey from an RSA generated private key/public key pair; the encrypted Private Key is split and then the portions are stored in two different databases. To encrypt data a new AES key is created that encrypts the data that is stored in another database. All users have their AES key encrypted using their associated public encryption keys such that the encrypted AES keys are stored in another database. To decrypt data the user enters his PassKey that is used to decrypt a rejoined split private key from portions that were retrieved from their respective databases. Next the encrypted AES key is retrieved and decrypted using the decrypted Private Key. Finally the AES encrypted data is retrieved from a database and decrypted using the decrypted AES key. |
| US09485095B2 |
Client control through content key format
Client control may be provided. First, content may be encrypted using an actual key. Then an identifier corresponding to a client device may be received and a transformation may be performed on the actual key and the identifier to produce a transmitted key. The transmitted key and the encrypted content may then be sent to the client device where it may be received. The client device may then receive the identifier corresponding to the client device and perform a reverse transformation on the transmitted key using the identifier to produce the actual key. The content may then be decrypted with the actual key. |
| US09485090B2 |
Managed authentication on a distributed network
An authoritative computer network (10) comprising: at least one manager user (12); a plurality of subordinate users (14); and access control means adapted to allow the manager user to control access of one or more subordinate users to the authoritative computer network, wherein the authoritative computer network is provided as an overlay network on or within a distributed network (100). |
| US09485086B2 |
Phase interpolator
Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. |
| US09485085B2 |
Phase locked loop (PLL) architecture
In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking. |
| US09485078B2 |
Point-to-multipoint microwave communication
A microwave communication system may include subscriber stations in communication with a base station. The stations may include time duplex circuitry normally found in wireless local area networks (WLANs). Signals normally routed through antennas associated with such circuitry instead are routed through circuitry to perform frequency conversion to and from microwave communications frequencies, for communications over microwave links between the subscriber stations and the base station. In some embodiments the wireless circuitry is configured for multiple input multiple output (MIMO) operation with one antenna port dedicated for transmission of data and one antenna port dedicated to reception of data. |
| US09485077B2 |
System and method for energy efficient ethernet with asymmetric traffic profiles
System and method for energy efficient Ethernet with asymmetric traffic profiles. A low power mode such as a low power idle mode is typically leveraged when both direction of a link do not have data traffic to transmit. Where only one direction of a link has data traffic to transmit, a physical layer device can transition from a full duplex mode to a simplex mode to produce energy savings (e.g., disabling cancellation circuitry). |
| US09485075B2 |
Method and system for transmission and reception of signals and related method of signaling
A base station (e.g., an evolved Node B) determines whether the physical broadcast channel (PBCH), reference signals (SCH) and common reference signals (CRS) are transmitted (or awaiting transmission) on a secondary component carrier (Scell) with the cell. The determination information is transmitted to a user equipment (UE) to inform the UE that the Scell transmissions do not include PBCH/SCH/CRS. As a result, the resource elements (REs) normally used to carry system information in the PBCH/SCH/CRS can be dynamically assigned (or reassigned) to the data channel. In this manner, the physical downlink shared channel (PBSCH) bandwidth can be increased by utilizing those resource elements that are normally reserved/assigned to the PBCH/SCH/CRS. |
| US09485073B2 |
Apparatus and method for transmitting channel quality indicator and acknowledgement signals in SC-FDMA communication systems
A method and apparatus are provided for transmitting symbols in wireless communication system. A method includes determining a channel quality indicator (CQI) and one or more acknowledgements; generating a first symbol based on the CQI; generating a second symbol based on the one or more acknowledgements; and transmitting the first symbol and the second symbol in a slot. One of a first code and a second code is applied for generating the second symbol, if the one or more acknowledgements is one bit. One of the first code, the second code, a third code, and a fourth code is applied for generating the second symbol, if the one or more acknowledgements are two bits. |
| US09485072B2 |
Method of transmitting and receiving ACK/NACK signal and apparatus thereof
Disclosed is a method for transmitting an ACK/NACK signal for an HARQ (Hybrid Automatic Repeat reQuest) in a CA (Carrier Aggregation) system, the method including obtaining at least one transmission resource among first and second transmission resources; configuring a first table showing a relationship in which a combination of at least one of the first and second transmission resources and modulation symbols is mapped to an ACK/NACK signal, and transmitting modulation symbols corresponding to a transmission target ACK/NACK signal in the first table by using transmission resource corresponding to the transmission target ACK/NACK signal in the first table. |
| US09485068B2 |
Method and apparatus for mitigating pilot pollution in a wireless network
Techniques for mitigating pilot pollution in a wireless network are described. In an aspect, pilot pollution may be mitigated by reducing density and/or transmit power of common pilots whenever possible. A cell may send a common pilot at a first density and a first transmit power level during a first time period and may send the common pilot at a second density and a second transmit power level during a second time period. The second density may be lower than the first density and/or the second transmit power level may be lower than the first transmit power level. Lower density may be achieved by sending the common pilot less frequently, on fewer subcarriers, and/or from fewer antennas. The cell may determine whether to reduce the density and/or transmit power of the common pilot based on network loading, SINRs of terminals, etc. In another aspect, pilot pollution may be mitigated by performing pilot cancellation at a terminal. |
| US09485066B2 |
Method of interference cancellation and method of detection of erroneous neighbour cell measurements
Methods of interference cancellation are provided. Channel estimation is performed with or without interference cancellation. Methods of detection of erroneous neighbor cell measurements are provided. The channel estimates for neighbor cells are processed to identify unreliable measurements. |
| US09485064B2 |
Communication method and radio transmitter
Radio transmission is performed even to a communication party whose bandwidth that can be used for transmission and reception is limited without having an influence of an offset of a DC component. A radio transmitter applied to an OFDMA communication system in which a plurality of different terminals performs communication using OFDM signals at the same time that includes a mapping part that allocates transmission power to each subcarrier, and also selects a subcarrier to which minimum power of the transmission power to be allocated is allocated and modulates transmission data in units of communication slots to output the modulated data; and a transmission part for transmitting radio signals including the modulated data using each of the subcarriers. |
| US09485061B2 |
Communication system with flexible repeat-response mechanism and method of operation thereof
A communication system includes: a message communication module configured to communicate a preceding data before a repeat request; a metric module, coupled to the message communication module, configured to determine a repeat metric associated with the repeat request for re-communicating the preceding data or a portion therein; and wherein the message communication module is further configured to communicate a repeat data including a repeat portion based on the repeat metric for re-communicating the preceding data or a portion therein for communicating with a device. |
| US09485060B2 |
Uplink control data transmission
Methods and systems for transmitting uplink control information and feedback are disclosed for carrier aggregation systems. A user equipment device may be configured to transmit uplink control information and other feedback for several downlink component carriers using one or more uplink component carriers. The user equipment device may be configured to transmit such data using a physical uplink control channel rather than a physical uplink shared channel. The user equipment device may be configured to determine the uplink control information and feedback data that is to be transmitted, the physical uplink control channel resources to be used to transmit the uplink control information and feedback data, and how the uplink control information and feedback data may be transmitted over the physical uplink control channel. |
| US09485057B2 |
Vector signaling with reduced receiver complexity
Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power. |
| US09485055B2 |
Packet retransmission and memory sharing
Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. |
| US09485052B2 |
Method for detecting control information in wireless communication system
A method for detecting control information in a wireless communication system is provided. The method includes checking a cyclic redundancy check (CRC) error by monitoring control channels, determining whether a value of an error check field is equal to a specific value, and, if the value of the error check field is equal to a specific value, detecting the control information on the control channel. |
| US09485050B2 |
Subchannel photonic routing, switching and protection with simplified upgrades of WDM optical networks
The present invention includes novel techniques, apparatus, and systems for optical WDM communications. Tunable lasers are employed to generate respective subcarrier frequencies which represent subchannels of an ITU channel to which client signals can be mapped. In one embodiment, subchannels are polarization interleaved to reduce crosstalk. In another embodiment, polarization multiplexing is used to increase the spectral density. Client circuits can be divided and combined with one another before being mapped, independent of one another, to individual subchannels within and across ITU channels. A crosspoint switch can be used to control the client to subchannel mapping, thereby enabling subchannel protection switching and hitless wavelength switching. Network architectures and subchannel transponders, muxponders and crossponders are disclosed, and techniques are employed (at the subchannel level/layer), to facilitate the desired optical routing, switching, concatenation and protection of the client circuits mapped to these subchannels across the nodes of a WDM network. |
| US09485045B2 |
Communication control equipment
Communication control equipment is connected to a plurality of communication control equipment via a network and is configured to be time-synchronized with the plurality of communication control equipment by using a time synchronization procedure using a communication including at least request packets and acknowledgement packets. The communication control equipment includes a receiving-interval measurement section configured to measure a receiving interval of request packets from the plurality of communication control equipment; and a queuing-occurrence determination section configured to detect conflict of the request packets from any of the plurality of communication control equipment on a basis of the receiving interval of the request packets measured by the receiving-interval measurement section. The communication control equipment is configured to determine whether to transmit an acknowledgement packet to the communication control equipment that has transmitted the request packets based on a detection result of the queuing-occurrence determination section. |
| US09485044B2 |
Method and apparatus of announcing sessions transmitted through a network
An electronic service guide (ESG) is provided by transmitting announcements describing multimedia sessions, such as video streams. Sessions are organized into a session directory (28) which is split into two parts: a full session directory (291) and an updated session directory (292). A first kind of announcement describes all sessions in the full session directory. A second kind of announcement describes sessions in the updated session directory. Once a client has received a description of the full session directory, it need only listen to announcements of the second type so as to learn of any updates to sessions. |
| US09485041B1 |
Antenna device capable of measuring signal strength of a radio frequency signal received thereby
An antenna device includes an antenna for receiving an RF signal and generating an antenna signal associated with the RF signal, and a measuring device. The measuring device includes a measurement unit, a processing unit and a display unit. The measurement unit receives the antenna signal, and outputs a voltage signal associated with the antenna signal. The processing unit obtains a strength signal according to the voltage signal. The display unit has a plurality of lighting elements configured to light with different colors, and displays an indication of signal strength of the RF signal according to the strength signal by a number of the lighting elements that emit light and by color of the light. |
| US09485035B2 |
Self-tuning transfer function for adaptive filtering
The technology described in this document can be embodied in a computer-implemented method that includes receiving, at one or more processing devices, a plurality of values representing a set of coefficients of an adaptive filter over a period of time, and identifying, by the one or more processing devices based on the plurality of values, a phase error associated with a transfer function of the adaptive filter. The method also includes adjusting, based on the identified phase error, a phase associated with the transfer function of the adaptive filter such that coefficients calculated using the adjusted transfer o function reduce the phase error. The method further includes determining a set of coefficients for the adaptive filter based on the adjusted transfer function, and programming the adaptive filter with the determined set of coefficients to enable operation of the adaptive filter. |
| US09485034B2 |
Device with external metal frame as coupling element for body-coupled-communication signals
A device is equipped with at least one communication module. The communication module supports communication on the basis of body-coupled-communication signals. Further, the device is equipped with a metal frame. The metal frame forms a part of an outer surface of the device. The metal frame is operable to provide conductive coupling of the of body-coupled-communication signals to a body of a user of the device. |
| US09485029B2 |
Multinary signaling based coded modulation for ultra-high-speed optical transport
Systems and methods for communication using an optical transmission system having optical transmitters and receivers includes performing a low-density parity-check (LDPC) encoding; performing nonbinary pm-ary signaling, where p is a prime larger than 2; taking m p-ary symbols at a time and selecting a point from pm-ary signal constellation; after up-sampling and driving amplification, using coordinates of the pm-ary constellation as input of I/Q modulator x (y); combining two independent pm-ary streams corresponding to x and y-polarization states by a polarization beam combiner (PBS) and transmitting data over the optical transmission system. |
| US09485025B2 |
Data transmission coordination over digital subscriber lines
An optical management node comprising a memory comprising instructions, a processor coupled to the memory and configured execute the instructions, wherein executing the instructions causes the processor to schedule data transmissions across an electrical network between a plurality of user terminals and an optoelectrical interface by using time division multiplexing or time division multiple access based on optimization of crosstalk performance of electrical lines of the electrical network, and a transmitter coupled to the processor and configured to transmit schedule information to the optoelectrical interface via an optical network. Also disclosed is a method implemented in a management node comprising scheduling data transmissions with a plurality of user terminals across a Digital Subscriber Line (DSL) network using time division scheduling based on optimization of crosstalk performance of DSL lines of the DSL network, and transmitting schedule information to the user terminals via an optical network. |
| US09485024B2 |
Auto commissioning for optic distributed antenna system
An optic distributed system includes a head end unit (HE) comprising a head end radio frequency unit (HRFU), at least one remote unit (RU), a corresponding optic cable connected between the HRFU and the at least one RU, and a controller configured to detect a forward radio frequency (RF) signal received from a base transceiver station (BTS), to perform a system wide commissioning function on the HRFU corresponding to the detection, to perform the system wide commissioning function on the at least one RU in accordance with a signal intensity of the forward RF signal from the HRFU, and to perform the system wide commissioning function on the optic cable to compensate for losses in the optic cable during signal transmissions between the HRFU and the at least one RU. |
| US09485022B2 |
Radio-over-fiber (ROF) system for protocol-independent wired and/or wireless communication
A switched wireless system is used to increase the range of peer-to-peer communications. The optically-switched fiber optic communication system includes a head-end unit (HEU) having a switch bank. Cables couple the HEU to one or more remote access points in different coverage areas. The switch bank in the HEU provides a link between the remote access points in the different coverage areas such that devices in the different cellular coverage areas communicate with each other, such as through videoconferencing. By using the switched communication system, the range and coverage of communication between devices may be extended such that devices in different coverage areas and devices using different communication protocols can communicate. |
| US09485021B2 |
Hybrid laser anti-clipping for fiber-coaxial networks
Systems, devices, and methods for hybrid anti-clipping in optical links in hybrid fiber-coaxial (HFC) networks are disclosed. A hybrid anti-clipping circuit can be included in both the uplink and downlink paths of the HFC network to avoid driving the laser in the optical link above a clipping threshold. The anti-clipping circuit can compare the average, or RMS, input power level and the power envelope of a RF input signal to a clipping threshold associated with the particular laser module being used. If the average power is above the clipping threshold, then the input signal can be attenuated proportionally to avoid clipping. If peaks in the power envelope are above the clipping threshold, then the bias current of the laser module can be adjusted to avoid clipping. Accordingly, the modes of anti-clipping circuit operation include applying attenuation to the input signal and/or adjusting the laser module bias current. |
| US09485020B2 |
Remote sensing device and monitoring apparatus
A remote sensor device comprises at least one sensor that produces an output signal indicative of the value of a measure, and a reflective display that is positioned such that it is visible along a line of sight from a remote location, the reflective display comprising at least two retro-reflective assemblies, each of which is arranged to reflect a variable fraction of radiation incident upon the reflective assembly back towards a source in response to respective control signals applied to the reflector assemblies. Each of the reflector assemblies preferentially reflects one wavelength of the incident radiation or preferentially removes at least one wavelength of the incident radiation that is not preferentially reflected or removed by the other reflector assembly. The device further comprises modulating means for modulating the control signals applied to the reflector assemblies as a function of the value of the output signal from the sensor so as to modulate the fractions of incident light reflected by the display. |
| US09485017B2 |
Monitoring of optical performance in an optical data transmission network
A method for monitoring optical performance in an optical data transmission network, the optical data transmission network including a first router node, a second router node, and an optical data transmission line connecting the first router node with the second router node providing optical data transmission from the first router node to the second router node using at least two channels, includes: in a measurement step, determining, at the spare IP router interface, optical performance parameters of the at least two channels; in a transmission step subsequent to the measurement step, transmitting the determined optical performance parameters to a remote control unit; and in an analysis step subsequent to the transmission step, analyzing the transmitted optical performance parameters and determining whether to take a corrective action to improve optical performance of the at least two channels. |
| US09485016B2 |
Hands-free optical fiber testing using optical loss test instrument
A method for testing the operation of an optical fiber cable in a communication network using an optical loss test set (OLTS) instrument includes receiving a range of identifiers of fibers to be tested. Identifiers of a first fiber set to be tested are displayed. The first fiber set comprises one or more fibers. The first fiber pair is included in the range. The first fiber pair is a next fiber pair to be tested. A determination is made whether the first fiber set is connected to the OLTS instrument. In response to determining that the first fiber set is connected to the OLTS instrument, a test of the first fiber set operation is performed using the OLTS instrument. Identifiers of a second fiber set are displayed. The second fiber set is included in the range and constitutes a next fiber set to be tested. |
| US09485013B2 |
Systems and methods for optical dark section conditioning
A method for optical dark section conditioning includes determining a section in an optical network is a dark section that includes connected fiber spans that are functional with no traffic carrying channels present thereon; and causing generation of at least one of broadband noise and a signal at a head end of the dark section. An apparatus configured to perform optical dark section conditioning includes logic configured to determine a section in an optical network is a dark section that includes connected fiber spans that are functional with no traffic carrying channels present thereon; and logic configured to cause generation of at least one of broadband noise and a signal at a head end of the dark section. |
| US09485012B2 |
Optical link protection using common modulation of multiple combined wavelengths
An optical transmitter may include one or more lasers configured to provide a primary optical signal having a primary wavelength and a secondary optical signal having a secondary wavelength to a modulator via corresponding first and second modulator inputs. The modulator may combine the primary and secondary optical signals into a combined optical signal and modulate, with an electrical signal, the combined optical signal to provide a modulated optical signal to an optical filter. The optical filter may be configured to separate, from the modulated optical signal, a modulated primary optical signal having the primary wavelength and a modulated secondary optical signal having the secondary wavelength and provide the modulated primary optical signal to a primary optical link and the modulated secondary optical signal to a secondary optical link. |
| US09485011B2 |
System comprising a container and visual means able to express a plurality of visual structures
A system in the technical field of rigid or semi-rigid packaging for cosmetic or pharmaceutical products, is intended to generate visual expressions on a plurality of packagings on the basis of information provided by an outside creator (5). This system includes a master station (4) able to emit control data (2COM) on the basis of the information provided by the outside creator (5) via a command interface (4a) and to transmit an electronic instruction signal (2|NS), dependent on these control data (2COM), to a remote server (2); and includes intermediate communication devices (6) able to receive, by long-distance communication, the instruction signal (2|NS) received by the remote server (2) and to transmit, by short-distance radiofrequency communication, the instruction signal (2|NS) to a telecommunication unit (16) of a container (12). |
| US09485009B1 |
Antenna system with high dynamic range amplifier for receive antenna elements
An antenna system is provided. The antenna system includes a planar array of antenna elements configured to operate as an array having a plurality of receive (Rx) antenna elements for receiving a signal in a first frequency band and a plurality of transmit (Tx) antenna elements for transmitting a signal in a second frequency band. The Rx antenna elements and the Tx antenna elements are interleaved in a pattern such that total Tx power leakage is distributed among the plurality of Rx antenna elements. Furthermore, each Rx antenna element is provided with a high dynamic range amplifier (HDRA) for amplifying a receive signal and filtering any Tx power leakage at each Rx antenna element. |
| US09485007B2 |
Repeater, broadcast transmitting system and method for relaying broadcast signal
A repeater, broadcast transmitting system, and method for relaying a broadcast signal between a gateway apparatus and a client apparatus are provided. The repeater includes a first interface which is configured to be connected to a gateway apparatus via a Wi-Fi communication protocol and is configured to receive a broadcast signal from the gateway apparatus; and a second interface which is configured to be connected to a client apparatus via the Wi-Fi communication protocol and is configured to transmit the broadcast signal to the client apparatus, wherein the first interface and the second interface use different frequency bands. |
| US09485004B2 |
Systems and methods of antenna orientation in a point-to-point wireless network
An exemplary method comprises positioning a first antenna to receive a first signal from a second antenna, the second antenna comprising energy absorbing material that functions to expand beamwidth, receiving the first signal from the second antenna, detecting a plurality of gains based on the first signal, repositioning the first antenna relative to the second antenna to a position associated with an acceptable gain based on the first signal, removing at least some of the energy absorbing material from the second antenna to narrow the beamwidth of the second antenna, receiving, by the first antenna, a second signal from the second antenna, detecting a plurality of gains based on the second signal, and repositioning the first antenna relative to the second antenna to a position associated with an increased gain of the plurality of gains based on the second signal, the increased gain being greater than the acceptable gain. |
| US09485003B2 |
User apparatus and user assignment information estimation method
A user apparatus that is used in a radio communication system including a plurality of base stations, and that includes a function for performing interference reduction based on user assignment in an interference cell, including: interference pattern generation means that generates a plurality of interference patterns each of which is a combination of presence or absence of an interference signal in a given number of interference cells for the user apparatus; reception quality calculation means that calculates a reception quality after interference reduction for each of the plurality of interference patterns generated by the interference pattern generation means; and user assignment information estimation means that determines presence or absence of an interference signal in each interference cell corresponding to an interference pattern based on which the best reception quality is obtained in reception qualities calculated by the reception quality calculation means to be presence or absence of user assignment. |
| US09485001B2 |
Diversity receiver front end system with switching network
Diversity receiver front end system with switching network. A receiving system can include a plurality of amplifiers, each one of the plurality of amplifiers disposed along a corresponding one of a plurality of paths between an input of the receiving system and an output of the receiving system and configured to amplify a signal received at the amplifier. The receiving system can further include a switching network including one or more single-pole/single-throw switches, each one of the switches coupling two of the plurality of paths. The receiving system can further include a controller configured to receive a band select signal and, based on the band select signal, enable one of the plurality of amplifiers and control the switching network. |
| US09485000B2 |
Wireless communication system, wireless communication device, and wireless communication method
A wireless communication system includes a transmitting device and a receiving device each including a plurality of antennas. A plurality of streams are subjected to spatial multiplexing and are transmitted in a downlink in which packets are transmitted from the transmitting device to the receiving device. In the transmitting device, each of the plurality of transmission streams is divided into a plurality of bit-series groups having decoding characteristics to which priority levels are assigned, the bit-series groups are subjected to encoding processes and modulating processes in accordance with the priority levels and further subjected to weighting and synthesizing, and each of the plurality of transmission streams in which a plurality of bit series items are synthesized with one another is spatially multiplexed and transmitted. |
| US09484999B2 |
Method and device for transmitting signal
Embodiments of the present invention provide a method and device for transmitting signal. The method includes: obtaining a downlink beamforming matrix; and using a conjugate transposed matrix of the downlink beamforming matrix as an uplink beamforming matrix for processing uplink signal. In the embodiments of the present invention, the conjugate transposed matrix of the downlink beamforming matrix may be used as the uplink beamforming matrix for processing uplink signal, which can simplify design of the uplink beamforming matrix and thereby reduce complexity of the system. |
| US09484993B2 |
Broadcast signal transmitter/receiver and broadcast signal transmitting/receiving method
A broadcast signal transmitter according to one embodiment of the present invention comprises: an input signal generating unit which generates a first input signal and a second input signal; a MIMO encoder which performs MIMO processing of the first input signal and the second input signal to output a first transmission signal and a second transmission signal; and a first OFDM generator and a second OFDM generator which performs OFDM modulation of the first transmission signal and OFDM modulation of the second transmission signal. The MIMO processing applies a MIMO matrix to the first input signal and the second input signal. The MIMO matrix changes phases using a phase rotation matrix, and adjusts power of the first input signal and second input signal using parameter a, wherein the parameter is set to different values in accordance with the modulation types of the first input signal and second input signal. |
| US09484991B2 |
Device, system and method of wireless communication via a plurality of antennas
Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of second transmissions from another device via one or more of the quasi-omnidirectional antenna assemblies, and, based on the second transmissions, to select at least one selected transmit antenna assembly for transmitting to the other device and a selected receive antenna assembly for receiving transmissions from the other device. Other embodiments are described and claimed. |
| US09484990B2 |
Spatial mode adaptation at the cell edge using interferer spatial correlation
A system and method is proposed for adapting the spatial transmission strategy in a cellular MIMO (multiple input multiple output) communication system for the downlink. Spatial mode adaptation, the choice of multiplexing, transmit diversity, number of streams, space-time code family, and the like are performed slowly based on side information from other base stations. Base stations exchange their transmission plans with neighboring base stations and broadcast this information to active users. Each user measures its susceptibility to spatial interference and returns this information to the base station. The base station then schedules active users according to the decisions made in interfering base stations and the preferred transmission strategies of its own users. |
| US09484985B2 |
Apparatus and method for communication using wireless power
An apparatus and method are described that may enable a target device to communicate with a source device using a wireless power. The communication apparatus receives a wireless power from a source resonator through a magnetic coupling between the source resonator and a target resonator. The communication apparatus transmits a message, and modulates the message based on the received wireless power and impedance mismatch between the source device and the target device. The communication apparatus controls the impedance mismatch by changing an impedance of the target device. |
| US09484984B2 |
Cable-level crosstalk reduction
A device for managing signal transport, on a cable level, in a communication system, and a method for using same, are provided herein. The device is connectable between one or more access multiplexers (e.g., Very-high-speed Digital Subscriber Loop Access Multiplexer (VDSLAM) or a switch) and a cable in said communication system. The device includes: a plurality of access multiplexer-side transceivers connectable to access multiplexer-related physical medium, associated with said one or more access multiplexers; a plurality of customer-side transceivers connectable to respective customer-related wire pairs of said cable; and a processor connected to said access multiplexer-side transceivers and said customer-side transceivers, said processor comprising means for reducing crosstalk among said customer-related wire pairs. In some embodiments, vectoring is used for the crosstalk reduction, thus implementing a so-called cable level vectoring (CLV). |
| US09484983B2 |
Impedance adjustment method, delay capacitance adjustment method and associated apparatus for communication device
An impedance adjustment method for a communication device, wherein the communication device has a plurality of impedance paths for selection, includes: selecting an initial impedance path; and utilizing a predetermined algorithm to examine a portion of the plurality of impedance paths by starting from the initial impedance path for selecting an optimized impedance path for the communication device. A delay capacitance adjustment method for a communication device, wherein the communication device has a plurality of delay capacitance paths for selection, includes: selecting an initial delay capacitance path; and utilizing a predetermined algorithm to examine a portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting an optimized delay capacitance path of the communication device. |
| US09484982B2 |
Base station apparatus and radio communication method
A wireless communication apparatus and method minimizes degradation in a separation characteristic of a code-multiplexed response signal using two-dimensional processing. One of plural cyclic shift values defines a reference signal sequence that is spread with an orthogonal sequence associated with one of the plural cyclic shift values. This two-dimensional processing compensates for interference affecting the reference signal. |
| US09484981B2 |
CDMA-based crosstalk cancellation for on-chip global high-speed links
Synchronous CDMA/spread spectrum methods, devices, and systems are used to suppress crosstalk in clock-forwarded on-chip interconnects. Transmitting a spread spectrum signal across on-chip interconnects for recovery at the terminus permit integrated chip designers to overcome the effects of capacitive cross-talk between adjacent data bus lines. The methods, devices, and systems provided herein improve cross-talk immunity between adjacent high speed signal lines by applying synchronous CDMA spread spectrum techniques to some or all of the high speed signal lines. Other methods, devices, and systems provided herein apply synchronous CDMA spread spectrum techniques to the concept of sending phantom signals to reduce the number of signal lines used to carry data. |
| US09484980B1 |
Precision timing source back-up for loss of GPS satellites
Methods are provided for implementing a timing synchronization or a backup timing synchronization in a telecommunication network. Timing pulses are received from a celestial body such as a star, pulsar, or quasar. The timing pulses are periodic and repetitive and act as a primary reference source in place of GPS timing or an atomic clock. The telecommunication network is synchronized from the timing pulses. |
| US09484979B2 |
Switching between transmit and receive modes in a wireless transceiver
A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then initiates a power-ON of the transmit radio portions of the transceiver prior to initiating a power-OFF of the receive radio portions. The technique enables the transceiver to meet timing requirements when operating in environments that require an acknowledgement to be sent in response to receipt of data. |
| US09484977B2 |
RF transformer based TX/RX integrated RF switch
The present invention is a novel and useful RF transformer based transmit/receive (TX/RX) integrated RF switch. In one embodiment of the invention, the TX/RX RF switch circuit is based on the use of an RF transformer which functions as (1) the PA output transformer during TX mode and (2) as a series inductance in an LNA matching network during receive mode. Thus, the RF transformer plays a dual function or role. Antenna diversity is achieved by having multiple antennas each having an associated antenna switch connected to the output transformer. The TX/RX switch of the invention reduces the number of switches required for antenna diversity to a minimum and minimizes RF losses in the system. The TX/RX switch is suitable for use with modern wireless communication standards such as DECT, 802.11 WLAN, Bluetooth, ZigBee, etc. The configuration of the TX/RX circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. |
| US09484975B2 |
Modular microwave backhaul outdoor unit
A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals. |
| US09484964B2 |
Interactive entertainment system
Disclosed here is an interactive audio system and a method of operating the same. In one embodiment, the interactive audio system comprises a processor and a receiving module for receiving a radio frequency (RF) carrier signal associated with a broadcast station. The audio system further comprises a memory storing computer-executable instructions, where the processing module is configured to access and execute the computer-executable instructions to perform a set of acts. The acts include shifting a frequency associated with the received RF carrier signal to an intermediate frequency (IF). The acts include demodulating the frequency shifted portion of the RF carrier signal associated with the broadcast station, the demodulation resulting in an output signal. The acts further include extracting an embedded data from the demodulated output signal, where the embedded data can be utilized to interact with a party associated the embedded data. The acts further include serving the embedded data in conjunction with the demodulated audio signal. |
| US09484961B2 |
Wireless electronic device with antenna switching circuitry
A wireless electronic device may include antennas formed at different locations on the device. The wireless electronic device may include transceivers that are used to wirelessly communicate in different frequency bands by transmitting and receiving radio-frequency signals in the frequency bands. The transceivers may include Wi-Fi® transceivers and cellular transceivers such as Long Term Evolution transceivers. The wireless electronic device may include antenna switching circuitry interposed between the transceivers and the antennas. The wireless electronic device may include control circuitry that controls the antenna switching circuitry to ensure that radio-frequency transmissions in adjacent frequency bands are routed to different antennas. By routing radio-frequency transmissions in adjacent frequency bands to different antennas, self-interference between communications in the adjacent frequency bands may be reduced. Self-interference may also be reduced by performing time division multiplexing to isolate radio-frequency signals that are transmitted in adjacent frequency bands. |
| US09484960B1 |
Reconfigurable FEC
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well. |
| US09484958B2 |
Method and system for controlling an interleaver
Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals. |
| US09484957B2 |
Transmitter apparatus and signal processing method thereof
A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol. |
| US09484956B2 |
Method for correcting messages containing bit stuffing
The invention relates to a method for correcting a message the generation of which involves transforming an initial message and inserting bit stuffing into the transformed message, which method comprises providing an observation sequence containing the message to be corrected. A number of path hypotheses are generated via a trellis diagram associated with the transformation. The nodes of the trellis diagram each represent a state of a finite-state machine capable of transforming the initial message and the branches represent the possible transitions between nodes. Among the branches of the trellis diagram, certain represent conditional transitions that may be made only when bit stuffing is present. During the generation of a path hypothesis, bit stuffing is detected and the branches taken are those associated with the detected bit stuffing. The most likely path hypothesis relative to the observation sequence is finally retained. |
| US09484952B2 |
Context state and probability initialization for context adaptive entropy coding
In one example, an apparatus for context adaptive entropy coding may include a coder configured to determine one or more initialization parameters for a context adaptive entropy coding process based on one or more initialization parameter index values. The coder may be further configured to determine one or more initial context states for initializing one or more contexts of the context adaptive entropy coding process based on the initialization parameters. The coder may be still further configured to initialize the contexts based on the initial context states. In some examples, the initialization parameters may be included in one or more tables, wherein, to determine the initialization parameters, the coder may be configured to map the initialization parameter index values to the initialization parameters in the tables. Alternatively, the coder may be configured to calculate the initialization parameters using the initialization parameter index values and one or more formulas. |
| US09484947B1 |
Variable length dynamic element matching in digital-to-analog converters
Embodiments of the disclosure provide improved mechanisms for applying DEM techniques to a DAC comprising a plurality of cells. Disclosed mechanisms include keeping track of the amplitude of input digital signal over a certain time period to determine a range of amplitudes of a portion of the input signal, and, when converting the digital values of that portion to analog values and applying a particular DEM technique, limiting the number of DAC cells on which a DEM technique is applied only to a number that is necessary for generating the analog output corresponding to the tracked portion, which number is determined based on the tracked amplitudes and could be smaller than the total number of DAC cells. In this manner, mismatch error may be reduced for smaller input signal amplitudes. Whenever possible, unused DAC cells may be put into a power saving mode, providing the advantage of reduced power consumption. |
| US09484946B2 |
Digital-to-analog converter (DAC), method for operating a DAC and transceiver circuit
Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described. |
| US09484945B1 |
Asynchronous successive-approximation-register analog-to-digital converter (SAR ADC) in synchronized system
A correcting asynchronous Successive-Approximation Register (SAR) analog-to-digital converter (ADC) detects and corrects metastability errors. An analog signal is synchronously sampled by a system clock, but data bits are converted asynchronously. A valid detector compares true and complement outputs of a comparator that compares the sampled voltage to a DAC voltage generated from digital test value from the SAR. Once the true and complement outputs diverge past logic thresholds, the valid detector activates a VALID signal indicating that comparison is completed. The compare result is then latched in as a data bit and the SAR advances to the next test value. Once all bits have been converted, an End-of-Conversion (EOC) is signaled. If the EOC does not occur by the end of the system clock, a metastability error is detected. The current bit that never finished comparison is forced high and all other unconverted bits are forced low. |
| US09484943B2 |
Digital-to-analog converter with integrated fir filter
A Digital-to-Analog Converter contains a digital shift register and a digital multiplexer. During each input signal clock period, the Digital-to-Analog Converter is multiplexed in time to perform multiple conversions on samples stored in the shift register. In this way, a weighted average of several signal samples is calculated, which corresponds to a FIR filter operation. Errors due! to Quantization Noise, INL or DNL undergo the same FIR filter characteristic. |
| US09484940B2 |
Using high frequency crystal from external module to trim real time clock
Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a remote signal transmitted by an external device. The received signal is provided to a clocking circuit having a clocking circuit for computation of a calibration factor based on a difference between phases of the clock signal generated by the local clock and transitions in the received remote signal. The calibration factor may be derived as a function of an edge of the clock signal lagging or leading relative to a corresponding edge of the remote signal. |
| US09484939B2 |
Techniques for fractional-N phase locked loops
Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL. |
| US09484936B2 |
Phase locked loop having fractional VCO modulation
An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal. |
| US09484935B2 |
Apparatus and methods for frequency lock enhancement of phase-locked loops
Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels. |
| US09484929B2 |
Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators
In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and—that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived. |
| US09484927B2 |
Semiconductor device and automobile
A semiconductor device includes a semiconductor element having a gate and controlled with a gate voltage, a gate drive circuit which controls the gate voltage, an electrode connected to the semiconductor element, a principal current in the semiconductor element flowing through the electrode, a temperature sensing part which senses the temperature of the electrode, a generation section which generates, on the basis of the temperature sensed by the temperature sensing part, a first control signal for giving a maximum amount of energization to the semiconductor element in such a range that the temperature of the electrode does not exceed a predetermined temperature, and a comparison section which compares the first control signal and a second control signal transmitted from the outside for the purpose of controlling the gate voltage, and selects a selective control signal which is one of the control signals with which the temperature of the electrode can be limited. The gate drive circuit controls the gate voltage according to the selective control signal. |
| US09484926B2 |
Semiconductor circuit device, oscillator, electronic apparatus, and moving object
A semiconductor circuit device includes an oscillation circuit, an output circuit that outputs a signal output from the oscillation circuit, a temperature sensing element, a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element, a first wiring via which power is supplied to the output circuit, and a second wiring via which a reference voltage is supplied to the output circuit in which at least one of the first wiring and the second wiring overlaps the temperature sensing element in a plan view. |
| US09484925B2 |
Programmable divider
A technique includes controlling a modulus of a programmable divider, including selectively activating and deactivating cells of the divider. The activation for at least one of the cells includes configuring an output signal of the cell to exhibit a predetermined signal state when the cell transitions from a deactivated state to an activated state. |
| US09484920B2 |
Switching circuit and electronic device
The present invention provides a switching circuit and an electronic device, which relate to the field of electronic technologies, so as to improve reliability of image processing. The switching circuit includes a comparator circuit, a first switch circuit, a second switch circuit, a first drive voltage source, and a second drive voltage source. Two input ends of the comparator circuit respectively receive an input voltage and a reference voltage, an output end is separately connected to an input end of the first switch circuit and an input end of the second switch circuit; The comparator circuit determines whether the input voltage is greater than the reference voltage, outputs a high level when determining that the input voltage is greater than the reference voltage, and outputs a low level when determining that the input voltage is not greater than the reference voltage. |
| US09484919B1 |
Selection of logic paths for redundancy
Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory. |
| US09484911B2 |
Output driver with back-powering prevention
A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage. |
| US09484907B2 |
Device for controlling at least one transistor
A device for controlling at least one transistor is disclosed. The device includes the transistor, which includes a control electrode and two other electrodes, a main control circuit connected to the control electrode of the transistor and configured to control the state of the transistor in a main operating mode, and an auxiliary control circuit configured to inject, in an auxiliary operating mode. An auxiliary current opposed to the current flows between the main control circuit and the control electrode of the transistor. |
| US09484902B2 |
Delay circuit
A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit. |
| US09484891B2 |
Multi-modal communication interface
An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage. |
| US09484883B2 |
Acoustic wave device and fabrication method of the same
An acoustic wave device includes: a substrate; an input terminal that is located on a first surface of the substrate, and to which a high-frequency signal is input; a resonator that is connected to the input terminal, and to which a high-frequency signal input to the input terminal is input; and an insulating layer that is located between the input terminal and the substrate, and has a permittivity smaller than that of the substrate. |
| US09484882B2 |
Acoustic resonator having temperature compensation
An acoustic resonator structure comprises a substrate having an air cavity, an acoustic stack disposed over the substrate and comprising a piezoelectric material disposed between a first electrode and a second electrode, and an acoustic reflector disposed over the substrate and comprising a single pair of acoustic impedance layers configured to reflect acoustic waves produced by vibration of the acoustic stack, wherein at least one of the acoustic impedance layers comprises a temperature compensating material. |
| US09484881B2 |
Impedance matching device and control method
In an impedance matching device between a power transmission circuit and a power transmission antenna, a storage unit stores tables associated with a load value, each storing control values of a coupling coefficient between the power transmission and reception antennae. A selection unit selects a table corresponding to the load value estimated by the load value estimation unit. An adjustment direction determination unit determines the direction of a position for reading out one of the control values from the selected table. A readout position determination unit determines the position for reading out the control value from the selected table based on the direction and a predetermined step width for shifting the position for reading out the control value. A circuit selection unit electrically connects a matching circuit or the through circuit. A control value output unit outputs the control value at the determined position to the selected circuit. |
| US09484880B2 |
Variable capacitor, impedance matching device, mobile terminal thereof and method for matching impedance
Disclosed is an impedance matching device. Variable devices of the impedance matching device installed in a mobile terminal, such as a portable terminal, are configured to have a MEMS structure. The MEMS structure and other components are integrated as one package, so the manufacturing cost is reduced and the manufacturing efficiency is improved. |
| US09484879B2 |
Nonlinear capacitance linearization
An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance. |
| US09484875B2 |
Active attenuator keeping saturated output power for reduced input power
An active attenuator is disclosed. The attenuator includes a divider to divide an input signal into two signals, a phase shifter to shift a phase of one of output signals of the divider, and a combiner to combine an output of the phase shifter with another of output signals of the divider. The phase shifter includes a coupler and two reflectors, or two amplifiers to cause a phase difference between two signals. |
| US09484874B2 |
Input amplitude modulated outphasing with an unmatched combiner
An amplifier system is disclosed, configured to apply a signal component separator algorithm such that the first phase modulated signal and the second phase modulated signal are allowed to take on several continuous amplitude levels in order to achieve a maximum efficiency at each desired output signal power level, without restricting the input signal power fed to the power amplifiers to a constant level, wherein for each desired output signal power level, the digital signal component separator assigns an amplitude and phases of input signals that result in a maximum instantaneous power efficiency at the amplified output signal combined with an unmatched/non-isolating combiner (e.g. Chireix combiner). |
| US09484870B2 |
Semiconductor integrated circuit device
A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output. |
| US09484865B2 |
Reconfigurable load modulation amplifier
A reconfigurable load modulation amplifier having a carrier amplifier and a peak amplifier that are coupled in parallel is disclosed. The peak amplifier provides additional power amplification when the carrier amplifier is driven into saturation. A quadrature coupler coupled between the carrier amplifier and the peak amplifier is configured to combine power from both the carrier amplifier and the peak amplifier for output through an output load terminal. The reconfigurable load modulation amplifier further includes control circuitry coupled to an isolation port of the quadrature coupler and configured to provide adjustable impedance at the isolation port of the quadrature coupler. As such, impedance at the isolation port of the quadrature coupler is tunable such that at least a carrier or peak amplifier is presented with a quadrature coupler load impedance that ranges from around about half an output load termination impedance to around about twice the output load termination impedance. |
| US09484860B2 |
Tracking power supply with increased boost capability
A tracking power supply for one or more amplifiers includes one or more cascaded sets of power boost circuits to temporarily boost the positive and/or negative power supply rail, respectively. Each power boost circuit may include a gain element and an energy source such as a capacitor or battery, and the power boost circuits are linked to provide a greater degree of voltage boost when needed. An optional control circuit monitors amplifier output signal levels, or separately amplified input signal levels, and provides power boost control signals to the power boost circuits, which temporarily raise or lower the positive and/or negative supply voltages above or below the nominal voltage rails in tandem with the highest and lowest output signals, respectively, from the amplifier(s). |
| US09484858B1 |
Inductive coupled pass transistor quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO) for providing an oscillating output signal. The QVCO includes a first oscillating circuit for producing a first output signal and a second output signal, those signals being a first set of antiphase signals. The QVCO also includes a second oscillating circuit for producing a first output signal and a second output signal, those signals being a second set of antiphase signals. The first oscillating circuit also has injection circuitry for injecting the second set of antiphase signals without a DC bias into the first output signal and the second output signal, and the second oscillating circuit also has injection circuitry for injecting the first set of antiphase signals without a DC bias into the third output signal and the fourth output signal. |
| US09484853B2 |
Panel mounting bracket assembly including an adjustable height extension device and related methods
A system for mounting at least one solar panel on a building may include at least one panel mounting bracket including a base to be positioned on the building, and a vertical extension having a proximal end coupled to the base and a distal end vertically spaced apart from the base. The vertical extension may have a cavity extending vertically therein. The system may also include an adjustable height extension device for the at least one panel mounting bracket including a lower portion carried within the cavity of the vertical extension and vertically slidable within the cavity, an upper portion carried by the lower portion to be connected with the at least one solar panel, and a vertical height adjustment member carried by the upper portion to cause the lower portion to slide vertically within the cavity to adjust a vertical height of the upper portion. |
| US09484851B2 |
Technique for correcting resolver offset
Disclosed is a technique of correcting a resolver offset by measuring and correcting an offset of a resolver assembled to a motor of an eco-friendly vehicle in an accurate and simple way. The offset measurement process includes, after completing the assembly of a resolver a resolver to a motor, rotating the motor by using a rotation device able to transfer a rotation force to the motor, setting a voltage instruction and current-controlling the motor according to the voltage instruction, and obtaining a d-axis current and a q-axis current, which are feedback currents, during the current-control of the motor. Then when the system is in a steady state, a resolver offset ({tilde over (θ)}) is calculated from the d-axis current and the q-axis current by using {tilde over (θ)}=tan−1(d-axis current/q-axis current). |
| US09484850B2 |
Voltage regulator and methods for simulating reactive power in parallel power generation systems
Systems, methods, and a voltage regulator are provided for tuning reactive droop compensation of a generator in a parallel power generation system. The voltage regulator is configured to compute a simulated droop compensation voltage for the generator and control an excitation signal to the generator based at least in part on the simulated droop compensation voltage. |
| US09484846B2 |
Drive system with combined actuation of brake and encoder
A drive system includes a line assembly configured to connect a power converter to an electric motor which has a brake and an encoder. The line assembly has at least two power lines and only two brake lines exclusively to provide a data transfer between the power converter and the electric motor and to transfer energy to the encoder. The power converter applies a first supply voltage of a first polarity and a second supply voltage of a second polarity opposite to the first polarity to the brake lines for supplying the brake and the encoder. The electric motor supplies the encoder with the respective supply voltage independently of its polarity and the brake with the respective supply voltage depending on its polarity. |
| US09484841B2 |
Inverter device
A switching power supply device equipped with an inverter device includes a transformer including a primary winding and a secondary winding, which are magnetically coupled with each other. On the primary side, a capacitor and a switching element are connected in series with the primary winding and a switching element is connected in series the switching element and is connected in parallel with the primary winding and the capacitor. On the secondary side, a bidirectional switching element, which includes FETs, is connected in series with the secondary winding. A control circuit alternately turns the first switching element and the second switching element on, and turns the bidirectional switching element on in an off period of the first switching element or the second switching element. Thus, the inverter device outputs an alternating current output voltage by using a single secondary winding of a transformer. |
| US09484837B2 |
Switching branch for three-level inverter and method for controlling switching branch of three-level inverter
A switching branch for a three-level inverter, comprising a first and second switch (S1, S2) in series between a positive DC pole (P) and an AC pole (AC), a first and second diode (D1, D2) parallel to the first and second switches, a third and fourth switch (S3, S4) in series between a negative DC pole (N) and the AC pole, a third and fourth diode (D3, D4) parallel to the third and fourth switches, a fifth diode (D5) between a neutral DC pole (M) and a point between the first and second switches, a sixth diode (D6) between the neutral DC pole and a point between the third and fourth switches, a fifth switch (S5) and a seventh diode (D7) in series between the neutral DC and AC poles, and a sixth switch (S6) and an eighth diode (D8) in series between the neutral DC and AC poles. |
| US09484834B2 |
Circuit arrangement with a rectifier circuit
A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices. |
| US09484832B2 |
Isolation of secondary transformer winding current during auxiliary power supply generation
An electronic system and method include a controller to actively control power transfer from a primary winding of a switching power converter to an auxiliary-winding of an auxiliary power supply. The switching power converter is controlled and configured such that during transfer of power to the auxiliary-winding, the switching power converter does not transfer charge to one or more secondary-windings of the switching power converter. Thus, the switching power converter isolates one or more secondary transformer winding currents from an auxiliary-winding current. By isolating the charge delivered to the one or more secondary-windings from charge delivered to the auxiliary-winding, the controller can accurately determine an amount of charge delivered to the secondary-windings and, thus, to a load. |
| US09484830B2 |
Five-level rectifier
A five-level rectifier includes at least one phase bridge arm that includes an upper-half and a lower-half bridge arm circuit modules. The upper-half bridge arm circuit module includes a first power semiconductor switch unit, a second power semiconductor switch unit, a first diode unit, a second diode unit, a first connecting busbar, a first insulated wire and a first transfer busbar; the lower-half bridge arm circuit module includes a third power semiconductor switch unit, a fourth power semiconductor switch unit, a third diode unit, a fourth diode unit, a second connecting busbar, a second insulated wire and a second transfer busbar. The two modules are disposed side by side and facing each other. |
| US09484828B2 |
Power frequency converter and associated method
A power frequency converter and an associated method are provided to convert an AC input signal at a first frequency, such as a first frequency that is permitted to vary within a range, to an AC output signal at a second frequency that is different than the first frequency and that may be fixed. The power frequency converter includes a plurality of power rectification modules. Each power rectification module includes a plurality of power rectification components for receiving different phases of an input signal at a first frequency. Each power rectification module is configured to provide an output signal to a load, such as an induction motor, at a second frequency. The power frequency converter also includes a controller configured to provide control signals to selectively enable the power rectification modules. The controller is configured to provide the control signals without synchronization to the first frequency. |
| US09484819B2 |
Regulator device
A regulator device includes: a plurality of regulators that are equipped in parallel between a power input terminal and a power output terminal and converts a power inputted from the power input terminal to output to the power output terminal; a dummy load circuit that is coupled to a power output system different from a power output system to the respective power output terminal of the plurality of regulators; a selector that selects a regulator to carry out an output to the power output terminal and a regulator to carry out an output to the dummy load circuit among the plurality of regulators; and a controller that obtains conversion efficiency characteristic information representing a characteristic of power conversion efficiency relative to a current flowing in the dummy load circuit for the regulator to carry out an output to the dummy load circuit. |
| US09484812B2 |
Direct-current power supply device
The present invention includes: a converter configured to convert the direct-current voltage of the rectifier to another direct-current voltage and supply to a load; a peak hold unit configured to hold a peak value of a current detected by a current detecting unit configured to detect a current flowing in the switching element; an averaging unit configured to convert, to a current, an output of an n/2 output unit, and then integrate and output the converted current, the n/2 output unit configured to output n/2 (n is an integer of 1 or more) of the held peak value only in a regeneration current period of the reactor; a control unit configured to turn the switching element on and off based on an output signal of the averaging unit in such a way that an average current value of a current flowing in the reactor is equal to a predetermined value. |
| US09484809B2 |
Apparatus and methods for low voltage high PSRR systems
Provided herein are apparatus and methods for low voltage high power supply rejection ratio (PSRR) systems. A charge pump converts a supply voltage to a larger charge pump voltage and provides the charge pump voltage to a circuit subsystem. The charge pump voltage is regulated to a state dependent reference. In the steady state the charge pump voltage is regulated with respect to an output voltage of the circuit subsystem; in this way PSRR of the circuit subsystem is enhanced. |
| US09484801B2 |
Start-up regulator for high-input-voltage power converters
A power converter system includes first and second input terminals; a converter connected to the first and second input terminals and including an output terminal; a start-up circuit connected to a first capacitor and configured to charge the first capacitor during start-up and hiccup conditions; a voltage source connected to the first and second input terminals and configured to provide, during the start-up and hiccup conditions, a voltage proportional to a voltage applied to the first and second input terminals; and a voltage buffer including a MOSFET with a gate connected to the voltage source, a source connected to the start-up circuit, and a drain connected to one of the first and second input terminals. |
| US09484800B2 |
Soft-start circuit for switching regulator
A soft-start circuit for a switching regulator (e.g., a buck converter) in which the soft-start circuit supplies a DC ramp voltage to the switch regulator's pre-driver such that the pulsed gate voltage supplied to power switch during the initial soft-start operating phase includes a series of pulses having amplitudes that respectively gradually change (e.g., sequentially increase from 0V to the system operating voltage), whereby the regulated output voltage passed from the power switch to the load is gradually increased at a rate that prevents voltage overshoot and inrush current. The DC ramp voltage is generated, for example, by a current source that begins charging a capacitor at the beginning of the initial soft-start operating phase. This arrangement allows a constant-frequency ramp signal generated by a single oscillator to be shared by multiple switch regulators that are fabricated on an IC chip. |
| US09484799B2 |
Switched capacitor DC-DC converter with reduced in-rush current and fault protection
To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor. |
| US09484798B2 |
Power control device and image forming apparatus including the same
A power control device and an image forming apparatus including the same are disclosed. A power control device meets the need for low power consumption by minimizing standby power consumption in a plug-on state of an electronic apparatus, and meets the safety requirements by increasing a discharging rate of an X-cap or an E-cap in a plug-off state. The power control device includes a first capacitor charged by AC power during input of the AC power, a rectifier converting the AC power to DC power, a second capacitor disposed at an output of the rectifier, and a discharge circuit including at least one discharge resistor, and a first switch and a second switch configured to be alternately turned on/off in response to supply and interruption of the AC power, and discharging at least one of the first and second capacitors via the at least one discharge resistor, in response to turn-off of the first switch and turn-on of the second switch. |
| US09484796B2 |
Induction generator and method for producing an induction generator
An induction generator (100) for a remote switch which comprises a U-shaped magnetic diverter (102) with first and second limbs as well as a coil core (104) with an induction coil (106) arranged between the limbs. A movable magnetic element (110) is provided for switching the induction generator (100). When the magnetic element (110) is in its first position, the magnetic element (110) is connected with the first limb and the coil core (104) and, when the magnetic element (110) is in its second position, the magnetic element (110) is connected with the coil core (104) and the second limb. |
| US09484793B2 |
Electrical rotating machine system or wind turbine system
An electrical rotating machine system that can be easily maintained and can provide improved power generation efficiency. The electrical rotating machine system includes: a first electrical rotating machine having a first stator that has first stator windings, and a first rotor that has first rotor windings and is disposed on the internal diameter side of the first stator so as to have a gap between the internal diameter side of the first stator and the first rotor itself; a second electrical rotating machine having a second stator that has second stator windings, and a second rotor that has second rotor windings and is disposed on the internal diameter side of the second stator so as to have a gap between the internal diameter side of the second stator and the second rotor itself; and at least one power converter that is electrically connected to the first rotor windings and the second rotor windings, and configured to rotate when the first rotor rotates. |
| US09484786B2 |
Induction generator
An induction generator for a radio switch having a magnet element as well as an induction coil with a coil core, characterized in that the coil core is U-shaped, wherein a first contact position and a second contact position for the magnet element are defined on the limbs of the coil core, with a flux direction reversal taking place in each case in the coil core when a change takes place between said positions, wherein the magnet element is arranged such that it can move in a defined manner linearly between the contact positions on the induction generator in a direction in which the limbs are adjacent to one another. |
| US09484782B2 |
Concentrated power-distribution member for concentrated winding motor
A concentrated power-distribution member for a concentrated winding motor including a ring-shaped busbar and a coil connection terminal formed in one-piece with the busbar to hold a coil winding end positioned in an inner side of the busbar. The coil connection terminal has an erected portion extending from the busbar in parallel with the center axis of the busbar and a pair of arms extending from the leading end of the erected portion toward a center axis. A pair of arms is constructed by a pair of wing portions that extend to both sides of the erected portion and are bent toward the center axis along a bending line parallel to the center axis. A coil end holding portion is provided in leading ends of the pair of arms. According to this construction, a dimension of the concentrated power-distribution member is reduced. |
| US09484779B2 |
Mechanical assembly for maintaining an air gap between a stator and rotor in an electro-mechanical energy converter
An apparatus and corresponding method for maintaining an air gap between a stator and rotor in an electro-mechanical energy converter is provided. The apparatus includes a structural sleeve and a plurality of stator sections attached to an inner surface of the structural sleeve. A hub is enclosed by the structural sleeve and is concentric with the structural sleeve. A plurality of rotor sections is flexibly coupled to the hub and is enclosed by the structural sleeve. A rail system is positioned within the structural sleeve and is concentric with the structural sleeve. The rail system guides the rotor sections in a substantially circular path and defines an air gap between the plurality of stator sections and plurality of rotor sections. |
| US09484774B2 |
Single phase brushless motor
A single-phase brushless motor has both superior start-up stability and low cogging torque. In the outer-rotor-type single-phase brushless motor, when a gap width between the rotor and one edge of the salient pole surface is defined as d1, a gap width between the rotor and the other edge of the salient pole surface is defined as d2, and a minimum gap width between the rotor and the salient pole surface is defined as d3, the formula d3 |
| US09484770B2 |
System and method of charging a chemical storage device
A system is provided to allow for charging of a chemical storage device without a rectifier. A gate is used in conjunction with a gate controller. The gate controller monitors input voltage and opens the gate when voltage crosses a zero crossing in a first direction. The gate monitor then closes the gate when the voltage crosses a zero crossing in a second direction. This increases the chances that the output power will have voltage in a single direction. This output power is then fed to a chemical storage device, where it can be stored and used by one or more electronic devices. |
| US09484767B2 |
Board assembly and electronic device including the same
There is provided a wireless power transmitter, including: a board having circuit wiring thereon; a connector mounted on a surface of the board; a terminal pin formed on one side of the connector and penetrating through the board; and a battery provided on the other surface of the board to be coupled to the terminal pin. |
| US09484765B2 |
Charging device and operating method thereof
An electronic device having a charging function is provided. The electronic device includes a conversion unit for converting an Alternating Current (AC) voltage to a Direct Current (DC), a first charging unit for generating a first charging voltage or current using the DC voltage, and an output unit for providing the DC voltage and the first charging voltage or current to an external device. Various other implementations are possible. |
| US09484764B2 |
Charge control device and drive load module
A charge control device that controls a state of charging to a storage section that stores electric power supplied from a power source and supplies the stored electric power to a load. The charge control device includes a voltage monitoring section which, if the storage section has its inter-terminal voltage being higher than or equal to a predetermined upper limit voltage, determines that the storage section is on a full charge, and which, if the storage section has its inter-terminal voltage being lower than or equal to a predetermined lower limit voltage which is lower than the predetermined upper limit voltage, determines that the storage section needs to be charged. |
| US09484761B2 |
Dark current cutoff device and dark current cutoff method
A dark current cutoff device (1) includes: a battery (10) configure to perform electrical power supply to a load (20); a cutoff switch (32), which is provided between the battery (10) and the load (20), cuts off the electrical power supply to the load (20) at a time of being opened, and supplies electrical power to the load (20) at a time of being closed; a failure recording unit (21) that determines and records a case where the load (20) does not operate as a failure of the load (20); and an open/close determining unit (41) that determines that the cutoff switch (32) is opened; and a recording prohibiting unit (22) configure to prohibit, in a case where the cutoff switch (32) is determined to be opened by the open/close determining unit (41), the failure recording unit (21) from determining and recording the failure. |
| US09484759B2 |
Method for detecting a type of charger coupled to an input-output circuit and input-output circuit therefor
A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit. |
| US09484756B2 |
Battery having multi-orientation conductions, battery holder having multi-orientation conductions, and battery assembling method
A battery includes a casing, a battery pack, and at least two electrical connecting assemblies. The casing includes an inner space and plural contact planes. Vertical directions of the contact planes are different. The battery pack includes a battery cell disposed in the inner space, and the battery cell includes a positive and a negative electrodes. The electrical connecting assemblies are electrically connected to the positive electrode and the negative electrode respectively, so as to transmit power between the battery pack and an electronic device. The electrical connecting assembly electrically connected to the positive electrode is arranged on at least two of the contact planes, and the electrical connecting assembly electrically connected to the negative electrode is arranged on at least two of the contact planes. If power supply in one certain direction is interrupted, the battery transmits power in the other directions, thereby avoiding power supply from being interrupted. |
| US09484752B2 |
Multi-charging device for connecting and charging portable terminal
A multi-charging device for a portable terminal is provided. The device includes a cabinet, a plurality of charging bodies accommodated in the cabinet, a plurality of slots formed in each of the plurality of charging bodies, a plurality of charging terminals each provided in a corresponding one of the slots, and a power supply unit supplying power to each of the charging terminals. When the portable terminal is inserted into one of the slots, a charging terminal provided in the slot is connected to the inserted portable terminal. |
| US09484749B2 |
Electric power supply system for an aircraft, aircraft and airport power supply system
The present invention relates to an electric power supply system for an aircraft having a transformer-less HVDC architecture, the system including: at least one multiphase engine generator in a star configuration which provides a multiphase alternating (AC) voltage; a converting circuit for converting the multiphase AC voltage into a corresponding direct (DC) voltage for supplying at least one aircraft load; an electric power supply interface for connection with a standardized GPU plug of an external GPU, the electric power supply interface comprising a supply voltage output terminal coupled to a self-contained power source for providing a low voltage control signal for driving a GPU internal switching circuit wherein the power source is decoupled from the AC voltage and DC voltage. The present invention further relates to an aircraft and an airport power supply system. |
| US09484746B2 |
Power converter circuit with AC output
A power converter circuit includes output terminals configured to receive an external AC voltage. At least one series circuit has at least two converter units. Each converter unit includes input terminals configured to be coupled to a DC power source. Output terminals provide an AC output current. The at least one series circuit is connected between the output terminals of the power converter circuit. A voltage measurement circuit is connected between the output terminals of the power converter circuit and configured to provide at least one measurement signal that includes information related to phase and frequency of the external AC voltage. At least one of the converter units is configured to receive the at least one measurement signal and is configured to regulate the generation of the AC output current dependent on the at least one measurement signal. |
| US09484745B2 |
Virtual oscillator control of power electronics inverters
A system includes power electronics inverters connected in a network. The power electronics inverters can utilize measurements at local terminals, without a need to exchange information between other power electronics inverters. |
| US09484743B2 |
Power distribution network event analysis using data from different data sources
A method for power distribution network analysis includes receiving power distribution network event data from a plurality of data sources, filtering the power distribution network event data, normalizing the power distribution network event data, storing the power distribution network event data in an event database and retrieving, in a querying engine, the power distribution network event data. |
| US09484741B2 |
Multiple voltage power box
A device and method of use directed to providing various voltages based on the voltage selection by the user for various applications. In one embodiment, the device is comprised of two or more 12 volt batteries coupled in a manner that allows the voltage output of the device to be modified by allowing each battery to change from in parallel to in series with a switching device. In another embodiment, the switching device may control all batteries, there may be more than one switching device whereby a switching device may control one or more batteries, or each battery may have its own switching device to determine which state the battery is in. |
| US09484740B2 |
Electrostatic discharge clamp
An electrostatic discharge clamp may include a reference generator and a comparator. The electrostatic discharge clamp may be characterized by a time constant. A voltage difference caused by an electrostatic discharge event may activate the electrostatic discharge clamp. The comparator may hold the electrostatic discharge clamp in an active state responsive to a reference voltage provided by the reference generator. A duration of the active state of the electrostatic discharge clamp may facilitate dissipation of the electrostatic discharge event. |
| US09484735B2 |
Protective device having a thin construction
The present invention is directed to an electrical wiring device that includes a circuit interrupter assembly coupled to a solenoid actuator and configured to move along an assembly axis in a direction normal to a major surface of the electrical isolation member to provide electrical continuity between the plurality of line terminals, the plurality of load terminals and the plurality of receptacle contact structures in a reset state and to interrupt the electrical continuity to effect a tripped state. The circuit interrupter assembly including at least one portion configured to pivot relative to the assembly axis to effect the reset state or the tripped state. |
| US09484734B2 |
Protection of photovoltaic modules of a photovoltaic generator against surge voltages relative to ground
For protecting a photovoltaic generator comprising photovoltaic modules, having an open circuit voltage higher than an insulation design voltage of its photovoltaic modules and being connected to an AC power grid via an inverter against a surge voltage relative to ground resulting from a ground fault and exceeding the insulation design voltage, the photovoltaic generator is surveyed for the occurrence of the ground fault or the surge voltage. Upon the actual occurrence of the ground fault or the surge voltage, at first, the photovoltaic generator is separated from an input-side intermediate link capacitance of the inverter, and the inverter is separated from the AC power grid. Then, the intermediate link capacitance is discharged via a resistor, prior to permanently closing semiconductor switches of an inverter bridge of the inverter and to reconnecting the photovoltaic generator to the input-side intermediate link capacitance of the inverter to short circuit the photovoltaic generator. |
| US09484733B1 |
Power control module for data storage device
A power control module including first port for receiving supply voltage from host power supply, second port for providing output voltage to power one or more data storage device components, isolation circuit coupled to first and second ports, driver including output coupled to control terminal of isolation circuit, voltage booster including input for receiving supply voltage and output for providing boost voltage to supply terminal of driver, voltage limiter operable to limit boost voltage to a limited boost voltage, and control circuitry coupled to drive input and operable to cause the isolation circuit to be in closed state during normal operating mode by causing the driver to apply limited boost voltage to the control terminal of the isolation circuit, thereby enabling the isolation circuit to provide over-voltage protection to one or more data storage device components by limiting output voltage at second port to less than the limited boost voltage. |
| US09484732B2 |
Method and apparatus for sealing motor terminals
A wire insulator apparatus includes an insulator/separator member, a cap portion, a tube and potting material. The insulator/separator member has apertures formed therein for receiving a plurality of wires. By threading the wires through the insulator/separator member, the wires are spaced apart so that a potting material can be molded to provide a complete seal from the environment, particularly conductive liquids such as ammonia, which may cause short-circuiting between the wires. Individual wires are terminated in the cap portion, and the cap portion, the insulator/separator member and the wire ends are positioned within a tube or a mold portion depending on the application, and a potting epoxy is fluidly inserted within the tube. The epoxy surrounds or encases the wire ends within the tube or mold to insulate the wire ends in an airtight seal. |
| US09484725B2 |
Access plate adapter for electrical fixture
An electrical assembly, such as a lighting assembly, includes a housing adapted for mounting to a wall or ceiling. The housing has an outer wall for attaching to the wall or ceiling and an opening for wire connections between the housing and the power source. An access plate adapter is removably coupled to the opening in the housing to define a channel between the housing and the wall or ceiling. The adapter has a bottom wall and a side wall forming a well and an outwardly extending top wall at a top end of the side wall. The bottom wall has as plurality of tabs forming hooks for coupling with the opening in the housing wall. The top wall of the adapter has a dimension to contact the surface of the wall or ceiling and form a seal to define a closed channel between the housing and the wall or ceiling. |
| US09484720B2 |
Medium voltage switchgear
A medium voltage switchgear (1) which is characterized in that it comprises a casing (2) defining an internal volume for housing at least a circuit breaker assembly (4) movable between at least two operative positions, said casing comprising a front panel (21) provided with an opening (5) for the insertion of an operating handle (8) for actuating the movement of said circuit breaker assembly between said operative positions, a closing and retaining device (6) being positioned in correspondence of said opening (5) and movable between a closed position when said operating handle is not inserted and an open position for allowing insertion of said operating handle, said closing and retaining device (6) comprising locking means for retaining said operating handle in position when inserted in said opening. |
| US09484719B2 |
Active-control resonant ignition system
A method is disclosed for producing a corona discharge for igniting an air/fuel mixture in an internal combustion engine. An igniter is provided having a discharge tip that protrudes into a combustion zone. During a first stage of a combustion process, a first primary winding of a RF transformer is driven at a first predetermined voltage level and at a first resonant frequency that is based on a first impedance in the combustion zone prior to onset of combustion, for generating a corona discharge at the tip of the igniter. During a second stage subsequent to the first stage, a second primary winding of the RF transformer is driven at a second predetermined voltage level and at a second resonant frequency that is based on a second impedance in the combustion zone at a time that is subsequent to onset of the combustion process. |
| US09484716B2 |
Surface emitting laser, atomic oscillator, and manufacturing method of surface emitting laser
A surface emitting laser includes: a substrate; and a laminated body disposed over the substrate, wherein the laminated body includes a first mirror layer disposed over the substrate, an active layer disposed over the first mirror layer, and a second mirror layer disposed over the active layer, and surface roughness Ra of an uppermost layer of the first mirror layer is greater than or equal to 0.45 nm and less than or equal to 1.0 nm. |
| US09484715B2 |
Quantum-cascade laser
A quantum cascade laser is configured with a semiconductor substrate and first and second active layers provided in series on the substrate. A unit laminate structure of the first active layer has a subband level structure having an emission upper level and an emission lower level, and is configured so as to be able to generate light of a first frequency ω1, a unit laminate structure of the second active layer has a subband level structure having a first emission upper level, a second emission upper level, and a plurality of emission lower levels, and is configured so as to be able to generate light of a second frequency ω2, and light of a difference frequency ω is generated by difference frequency generation from the light of the first frequency ω1 and the light of the second frequency ω2. |
| US09484714B2 |
Method for manufacturing optical semiconductor device having modulator with hollowed regions between waveguides
A second insulating film, which includes a hollowed portion inside in a region where the high mesa ridge type optical element is formed, is formed. By using the second insulating film as a mask and etching, a concave portion is formed in the transparent waveguide layer and the upper cladding layer below the hollowed portion. The modulator layer having the Al-based material is formed. By etching with the modulator layer formed in the concave portion being covered with the third insulating film, the modulator layer formed outside the concave portion is removed. By etching with the modulator layer formed in the concave portion being covered with the fourth insulating film, the ridge of the semiconductor laser is formed without exposing the modulator layer formed in the concave portion. |
| US09484713B2 |
Light-emitting element and method for manufacturing the same
A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure. |
| US09484704B2 |
Gas circulation type laser oscillator
A laser oscillator comprising an electric discharge excitation part having a discharge tube, and generates laser by excitation discharge of a laser gas flow through the inside of the discharge tube, an optical resonance part which has optical components attached to outsides of end walls of the discharge tube, and resonates laser generated in the discharge tube, and blower piping which connects an intake port and exhaust port of the discharge tube to form a circulation path of laser gas. The end walls of the discharge tube are provided with through holes which connect the inside of the discharge tube and the optical components, and blocking members are arranged in the through holes so as to block the flow of laser gas through the through holes toward the optical components. |
| US09484703B2 |
Gas circulation loop for a laser discharge tube
The gas circulation loop for a laser discharge tube includes a gas supply duct (a) and a gas exhaust duct (c), wherein the gas supply duct (a) and/or the gas exhaust duct (c) is elongated in the longitudinal direction of the laser discharge tube (b) and connected to the laser discharge tube (b) by an inlet flow distributor and, respectively an outlet flow distributor, adapted for controlled transversal gas inlet and, respectively outlet, over at least part of the laser discharge tube (b), and wherein the inlet flow distributor and/or the outlet flow distributor include a plurality of respective inlet channels or outlet channels, characterized in that the ratio between the diameter of the gas supply duct (a) and the diameter of the inlet channels, and/or the ratio between the diameter of the gas exhaust duct (c) and the diameter of the outlet channels is at least 2. A laser apparatus including such gas circulation loop is also described. |
| US09484702B2 |
System and method for agile remote generation of a broadband tunable short-pulse emission
A method comprising using a pulse shaper in the spectral domain to generate multiple-color pulses directly at the output of the laser amplifier. The delay can thus be controlled directly in the spectral domain and there is no need for an optical delay line. The method allows reducing the number of optical components and insures insensitivity to alignment, vibrations and turbulence on long distance propagation and filamentation, particularly in air. The method allows programmable and tunable interaction, since the pulse shaper is able to control the laser spectral amplitude and phase. |
| US09484701B2 |
Quick release push feed guide and tool support for terminal applicator
An electrical terminal applicator system including a feed guide and tool support assembly defining a one-piece member includes a stock guide portion joined to a tool receiving portion. A motor is positioned adjacent to the feed guide and tool support assembly. A drive shaft received in a bore of the stock guide portion is rotated about a longitudinal axis of the drive shaft within the bore by operation of the motor. A tool assembly is mounted on the tool receiving portion and located downstream of the stock guide portion and the drive shaft. The drive shaft when rotated about the longitudinal axis of the drive shaft is positioned to engage a terminal holder strip having multiple electrical terminals to push the terminal strip holder toward the tool assembly. |
| US09484699B2 |
Elastomeric connectors
In a first embodiment, an elastomeric connector may include conductive and nonconductive portions and a guide that at least partially surrounds the connector and transfers compression in at least two directions. In a second embodiment, an elastomeric connector includes conductive portions at least partially surrounded by a nonconductive portion that is at least partially surrounded by conductive material connectible to ground to shield. In a third embodiment, an elastomeric connector may include multiple conductive portions and a nonconductive portion. One of the conductive portions may be separated from a first other in a cross section of a first connection surface and a second one of the others outside the cross section. At least one of the conductive portions may be connected to at least one of the others within the connector. In a fourth embodiment, a sealing component may include conductive and nonconductive elastomeric material. |
| US09484698B2 |
Electrical outlet drying boot
An apparatus for attaching duct work to an electrical outlet or electrical switch, said apparatus comprising: a generally cylindrical tube having a first end having a first diameter and a second end having a second diameter where said second diameter larger than said first diameter; a tapered wall that connects said first and second ends; at least two slots disposed through said tapered cylindrical wall; a gasket disposed about the perimeter of the said second end; at least one bracket, said bracket comprising at least two tabs, said tabs sized and oriented to be inserted into said slots, where said bracket is disposed across the diameter of said second end; means for selectively and releasably attaching said bracket to an electrical outlet. |
| US09484697B2 |
Alternator brush holder
A brush holder assembly for an alternator having a rotational axis includes a pair of brushes each having a contacting surface defining a width and a height, and each having a shunt wire extending laterally from the brush in the widthwise direction. The brush holder assembly includes a housing having first and second brush chambers, corresponding first and second wire cavities each defining a cavity height, and first and second slots respectively interposed between the corresponding chamber and cavity. The respective shunt wires extend through the first and second slots then through the first and second wire cavities. The cavity heights are each at least approximately 0.9 times the height of one of the brushes. The height of the first wire cavity is less than approximately 0.97 times ((A/2) plus B), wherein A is the brush height and B is the distance between the brushes. |
| US09484691B2 |
RJ45 socket connector having a terminal module prventing dislodgment of a terminal due to mistaken insertion
An RJ45 socket connector includes an insulative housing and a terminal module received in the insulative housing. The insulative housing includes a receiving space, a number of partitions, and a number of receiving passageways each formed between every two adjacent partitions. The terminal module comprises an insulative body and a row of conductive terminals insert molded in the insulative body, the conductive terminal having a fixed portion fixed in the insulative housing and an elastic contact portion extending from the fixed portion and received in a corresponding receiving passageway. The insulative body defines a trough and a number of tubers disposed in the trough, every two adjacent tubers defining a groove for accommodating a downwardly moved conductive terminal. |
| US09484688B2 |
Printed circuit board coaxial connector
The invention relates to a coaxial connector (1) having a first and a second connector part (2, 3) and an adapter (4) arranged between said connector parts. When installed, the adapter (4) is arranged in an opening (6) in an external conductor (8) of the first connector part (2, 3) such that it can fold out laterally. A limiting element (9) made from an insulating material is arranged in the region of the entrance to the opening (6) so that it limits the lateral movement of the adapter. |
| US09484685B2 |
Cable connector assembly with optical element transmitting LED light
A cable connector assembly includes an electrical connector and a cable electrically connected with the electrical connector. The electrical connector defines a plug portion, a printed circuit board electrically connected to the plug portion, a pair of LED lamps mounted on the printed circuit board, an optical element transmitting the light emitted by the LED lamps and an insulative housing covering the printed circuit board. The optical element defines a pair of transition portions transmitting the light emitted by the LED lamps and a photic zone, the photic zone of the optical element is exposed to the insulative shell and has a closed circumference so that the light emitted by the LED lamps passes through the photic zone to form a continuous aperture. |
| US09484684B2 |
Connector with peripheral wall having an opening and a detector slidably engaging the peripheral wall adjacent the opening for preventing widening of the opening
A connector includes a first housing (10) with a terminal accommodating portion (11) surrounded by a peripheral wall (17), a second housing (60) connectable to the first housing (10), and a detector (40) to detect a connected state of the housings (10, 60) based on whether the detector (40) moves from an initial position to a detection position in a space between the terminal accommodating portion (11) and the peripheral wall (17). An opening (22) extends circumferentially in a part of the peripheral wall (17) and exposes the detector (40). Deformation regulating portions (23, 53) are formed on the peripheral wall (17) and the detector member (40) and permit movements of the detector (40) between the initial position and the detection position and regulate deformation of the peripheral wall (17) to enlarge an opening width of the opening (22) by being fit to each other. |
| US09484676B2 |
Electrical connector having latches and method of making the same
An electrical connector (100) includes a metal plate (1) having a pair of affixed portions (12) at opposite sides thereof, a first housing (21) insert molded with the metal plate and defining two rows of passageways (211), two rows of terminals (3) accommodated in the two rows of passageways, a pair of latches (4) respectively connected to the affixed portions of the metal plate and soldered on the circuit board, and a second housing (22) over molded with the first housing and the pair of latches to form a subassembly. |
| US09484672B2 |
Adapter for USB and HSD interfaces
An adapter having a first electrical interface and a second electrical interface which each have contact elements for transmitting data (data contact elements) and for transmitting electric supply energy (supply contact elements), the contact elements of the first interface being connected to the corresponding contact elements of the second interface via conductors. A first supply contact element of the first interface is connected to two first supply contact elements of the second interface and a second supply contact element of the first interface is connected to a second supply contact element of the second interface, the second supply contact element of the second interface being in the form of an external conductor surrounding the other contact elements. |
| US09484670B2 |
Connector assembly with enabling contact and housing structure
A connector is mateable with a mating connector which has a mating lock portion. The connector comprises a first housing, a second housing and a contact. The first housing accommodates, at least in part, the contact. The contact is provided with a cable holding portion which holds an end of a cable so that the cable extends in a predetermined direction. The second housing is attached to the first housing to hold the contact in cooperation with the first housing. The second housing is provided with a hooked portion, a spring portion, an operation portion and a lock portion. The spring portion is resiliently deformable. The operation portion and the lock portion are supported by the spring portion. The lock portion locks the mating lock portion when the connector and the mating connector are mated with each other. The hooked portion is a portion which is hooked by a finger upon operation of the operation portion. The hooked portion is positioned apart from the operation portion in the predetermined direction. The operation portion releases a lock of the lock portion against the mating lock portion when operated to be moved toward the hooked portion. |
| US09484668B2 |
Connector device
A connector device comprises a connector and a mating connector connectable with each other. The mating connector comprises a mating primary terminal and a mating secondary terminal. The connector comprises a primary terminal, a secondary terminal, an operation member and a push-back mechanism. The operation member changes its state from an initial state to a second state via a second state. When the state of the operation member is changed to the first state, the primary terminal is connected to the mating primary terminal. When the state of the operation member is changed to the second state, the secondary terminal is connected to the mating secondary terminal. When the state of the operation member is changed to the first state, the push-back mechanism applies a push-back force to the operation member to change the state of the operation member back toward the initial state. |
| US09484667B2 |
Vehicle-side connector
A vehicle-side connector (10) to be connected to a battery mounted in a vehicle includes an outer housing (31) to be fixed to a body of the vehicle, an inner housing (50) to be fitted into the outer housing (31) from a vehicle interior side, terminal fittings (11) respectively connected to a plurality of wires (20P, 20S) drawn out from the interior of the vehicle including the battery, a plurality of terminal accommodating chambers (53, 40) provided from the inner housing (50) to the outer housing (31) and configured such that the respective terminal fittings (11) are inserted and accommodated thereinto from behind, a retainer (60) assemblable with the inner housing (50) to lock and retain each terminal fitting (11), and a lock mechanism portion (47, 70) configured to lock the retainer (60) and the outer housing (31) in a joined state. |
| US09484665B2 |
Cable connector assembly with improved strain relief and method of making the same
A cable connector assembly includes a connector, a printed circuit board having a rear portion, a cable connected to the rear portion, a strain relief having a main portion, a shell having a front wall and a rear wall, an outer case enclosing the shell and having a front end face and a rear end face, wherein the main portion is disposed between the rear wall and the rear end face, and the main portion comprises at least one through hole. A method of assembling a cable connector assembly, the cable connector assembly including a connector, a printed circuit board, and a cable, the method comprising the steps of: over-molding a strain relief with the cable to have a main portion defining at least one through hole; disposing the printed circuit board in a shell; and mounting an outer case forwardly over the shell to press the strain relief. |
| US09484663B2 |
Device for dividing a bundle of insulated electrical conductors
A device for dividing at least one bundle of insulated electrical conductors is provided, where in the housing, is arranged a contact part, consisting of metal, which protrudes outwardly beyond the profile of the housing and has at its end projecting out of the housing at least one throughhole and at its end located in the housing a connecting element for electrically conductively connecting a conductor. In the assembly position at least one electrical individual line extends through one of the openings into the housing. The line has at least two conductors, wherein one of the conductors is electrically conductively connected to the contact part, while the other conductor of the individual line projects through one of the openings out of the housing. |
| US09484652B2 |
Crimp terminal, crimp-connection structural body, and method for manufacturing crimp-connection structural body
A crimp terminal includes; a crimping portion and a cover, the crimping portion is formed in a hollow cylindrical shape in cross section and has a first and a second end portion opposite to the first end portion. The conductor portion is inserted into the first end portion in a longitudinal direction, and the second end is sealed. The second end portion at the opposite side is sealed by welding. The crimping portion has a guide section inside the crimping portion into which the exposed conductor portion is inserted. An inner diameter of the guide section is smaller than an outer diameter of the cover of the insulated wire and larger than an outer diameter of the conductor portion. A length between the first end portion into which the conductor portion is inserted and the guide section is smaller than a length of the exposed conductor portion of the insulated wire. |
| US09484649B2 |
Electromechanical assembly with socket and card edge connector
An electromechanical assembly includes a socket housing having a cavity for seating an integrated circuit and a first plurality of electrical contacts in the cavity to electrically connect an integrated circuit seated in the socket housing with a circuit board upon which the electromechanical assembly is mounted. The socket housing has a supporting body on a different plane than a bottom surface of the cavity. The socket housing has a second plurality of electrical contacts that form a first row across the supporting body and a third plurality of electrical contacts that form a second row across the supporting body. The socket housing has alignment elements. The electromechanical assembly also includes a card edge connector having slots that accept the alignment elements of the socket housing, a fourth plurality of electrical contacts that form a third row, and a fifth plurality of electrical contacts that form a fourth row. |
| US09484646B2 |
Cable connector structured for reassembly and method thereof
A connector includes, in one embodiment, a body assembly configured to be secured to a prepared end of a coaxial cable. The connector has a coupler assembly connected to the body assembly for connecting the body assembly to an interface port. The connector also has a flexible interlock to facilitate repeated assembly and disassembly of the connector. |
| US09484645B2 |
Quick mount connector for a coaxial cable
A post-less coaxial cable connector includes a body, a shell, a compression ring, and a coupling portion. The shell has a collapsible groove that, when the post-less coaxial cable connector is axially compressed, collapses and engages the coaxial cable. This provides pull strength and electrical communication in the post-less coaxial cable connector. The compression ring has projections, that when the post-less coaxial cable connector is axially compressed, engage the coaxial cable jacket, providing sealing at the back end and rotation torque. |
| US09484643B2 |
Contact element for connecting to a circuit board, contact system and method
The invention relates to a contact element for connecting to a circuit board. The circuit board has at least one substrate layer, particularly an electrically insulating substrate layer. The circuit board also has at least one electrically conductive layer. The contact element is designed for connecting to the electrically conductive layer. According to the invention, the contact element is designed to be pushed onto a circuit board edge of the circuit board. The contact element is designed to reach over the circuit board edge and has at least one cutting blade with a cutting edge, the cutting edge having a harder metal in the area of a severing section than in an adjoining contact section alongside the cutting edge. The cutting edge is designed to cut through the substrate layer with the severing section when pushed onto the circuit board edge and to contact the electrically conductive layer electrically with the contact section. |
| US09484638B2 |
Transmission and reception parameter control
A system and method for implementing transmission parameter control at a transmitting station is described. The exemplary system and method comprises querying a transmission parameter control module for a transmission schedule. The transmission schedule comprises at least one schedule entry defining a set of transmission parameter controls as they pertain to a destination address. At least one packet of data is then transmitted to the destination address according to the transmission parameters controls of at least one schedule entry from the transmission schedule. A system and method for selecting an antenna configuration corresponding to a next transmission of packet data is also disclosed. |
| US09484636B2 |
Mesh reflector with truss structure
A reflector assembly includes a frame centered about a longitudinal axis, a first curved body extending from the frame, and a second curved body extending from the frame and connected to the first curved body for supporting the first curved body. A reflective mesh has an electromagnetically reflective surface and a support structure secures the reflective mesh to the first curved body and spaces the reflective mesh away from the first body towards the second body. |
| US09484634B1 |
Three dimensional bow tie antenna array with radiation pattern control for high-altitude platforms
This disclosure relates to an antenna system. The antenna system includes a first and a second set of radiating elements each configured to emit electromagnetic radiation corresponding to an input signal. The electromagnetic energy may be emitted by the first set may have a first polarization. The first set of radiating elements includes a first radiating element having a first height. The first set also includes a second radiating element having a second height. The second radiating element may be coupled to a first phase adjustment component. The electromagnetic energy may be emitted by the first set may have a second polarization that is perpendicular to the first polarization. The second set of radiating elements includes a third radiating element having a third height. The second set also includes a fourth radiating element having a fourth height. The fourth radiating element may be coupled to a second phase adjustment component. |
| US09484631B1 |
Split band antenna design
Antenna structures and methods of operating the same of an electronic device are described. One apparatus includes a single radio frequency (RF) feed and a folded monopole element coupled to the single RF feed. The folded monopole element is an integrated WAN/GNSS antenna that receives electromagnetic energy in a first frequency band and receives electromagnetic energy in a second frequency band. The first frequency band is a wireless area network (WAN) frequency band and the second frequency band is a global navigation satellite system (GNSS) frequency band. The apparatus further includes an impedance matching circuit coupled to the single RF feed. The impedance matching circuit includes a diplexer to extract out GNSS frequency signals received by the folded monopole element from WAN signals received by the folded monopole element. |
| US09484627B2 |
Wireless communication device
The invention includes a first circuit board on which a plurality of first terminal sections is arranged, a high-frequency circuit arranged on the first circuit board and connected to at least one of the plurality of first terminal sections, a second circuit board on which is arranged a plurality of second terminal sections facing the plurality of first terminal sections, a first internal circuit arranged on the second circuit board and connected to at least one of the plurality of second terminal sections, and electrical continuity unit providing electrical continuity among the plurality of first terminal sections and the plurality of second terminal sections. At least two contiguous terminals of the plurality of first terminal sections and/or the plurality of second terminal sections including a terminal connected to the high-frequency circuit are connected via a capacitor and function as an antenna for wireless communication. |
| US09484626B2 |
Vehicle door handle assembly with antenna circuit
A door handle assembly for a door of a vehicle, with the door handle assembly configured to mount at a handle region of a vehicle door, includes an antenna circuit for an antenna of a passive entry system of the vehicle. The antenna circuit includes at least an inductor in series electrical connection with a capacitor. The antenna circuit includes a resistor in electrical connection with the inductor and the capacitor. The resistor is selected to provide a selected reduction of a quality factor or Q factor of the antenna circuit to a reduced level. |
| US09484625B2 |
Dynamically adjusting width of beam based on altitude
An antenna includes a radiator and a reflector and has a radiation pattern that is based at least in part on a separation distance between the radiator and the reflector. The antenna includes a linkage configured to adjust the separation distance based at least in part on the altitude of the antenna. The resulting radiation pattern can be dynamically adjusted based on altitude of the antenna such that, while the antenna is aloft and the antenna is ground-facing, variations in geographic boundaries and intensity of the radiation received at ground level are at least partially compensated for by the dynamic adjustments to the radiation pattern. |
| US09484624B2 |
Reflection controller
A reflection controller for modifying electromagnetic reflections from a surface includes a conducting patch being positioned proximate to an electromagnetically reflecting surface. The floating conducting patch includes an electrical conductor at a floating potential positioned on a dielectric substrate where at least one of a dielectric thickness, dielectric constant, or the dimensions of the electrical conductor are chosen to reduces retro-reflection of incident radiation. |
| US09484623B2 |
Antenna device of mobile terminal
Various mobile communication terminals, apparatuses, and methods having antenna improvements are discussed. An apparatus is described which includes an outer front side having a display disposed therein; an outer rear side a conductive part and a non-conductive part; a battery disposed between the outer front side and the outer rear side; and an antenna including a radiation unit capable of receiving a signal, at least a portion of the radiation unit being disposed between the outer front side and the non-conductive part of the outer rear side, a feeding unit which electrically connects the radiation unit to a circuit board, and a ground part which electrically connects the radiation unit to the conductive part of the outer rear side. |
| US09484616B2 |
Support truss for an antenna or similar device
Methods and devices for securing an antenna or similar device to a structure to inhibit undesirable movement when stowed or folded for travel. A truss having a mount and a plug can be used to secure an antenna to a structure, in particular a rod holder of a boat. A truss can be used to secure the antenna and prevent undesirable contact with other structures. Particular embodiments can be configured to accommodate antennas that, when stowed, are not located near a structure. |
| US09484614B2 |
Dielectric waveguide signal divider
A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant value that is lower than the first dielectric constant value. A first port of a signal divider is connected to receive a signal from the DWG. A second port and a third port are each configured to output a portion of the signal received on the first port, wherein the first and second port are approximately in line and the third port is at an angle to a line formed by the first port and the second port. The first port and second port have a core member with the first dielectric constant value, and the third port has a core member with a second dielectric constant value that is higher than the first dielectric constant value. |
| US09484611B2 |
Coupled line system with controllable transmission behaviour
The invention relates two lines each with two terminals. A first line provides a first terminal and a second terminal. A second line provides a first terminal and a second terminal. The lines extend in spatial proximity and are coupled. The two lines transport an electromagnetic signal fed into the line system. Distanced from the first terminal of the second line and distanced from the second terminal of the second line, at least one controllable element is arranged along the second line. The invention further relates to a switch, a controllable diplexer, a controllable frequency filter, a controllable attenuator and a controllable phase shifter. |
| US09484609B2 |
Microwave coupling structure for suppressing common mode signals while passing differential mode signals between a pair of coplanar waveguide (CPW) transmission lines
A transmission line structure having a pair of separated coplanar waveguide transmissions line section. A coupling circuit is coupled between the pair of coplanar waveguide transmissions line sections, the coupling circuit suppresses common mode signals therein and passes, substantially unsuppressed, differential mode signal transmission between the pair of coplanar waveguide transmissions line sections. |
| US09484606B1 |
Recycling and reconditioning of battery electrode materials
Embodiments are disclosed herein that relate to recycling and refurbishing battery electrode materials. For example, one disclosed embodiment provides a method comprising obtaining a quantity of spent electrode material, reacting the spent electrode material with an aqueous lithium solution in an autoclave while heating the spent electrode material and the aqueous lithium solution to form a hydrothermally reacted spent electrode material, removing the hydrothermally reacted spent electrode material from the aqueous lithium solution, and sintering the hydrothermally reacted spent material to form a recycled electrode material. |
| US09484603B2 |
Sealed lithium secondary battery and method of manufacturing same
The invention provides a method capable of more simply and easily mass-producing sealed lithium secondary batteries having a stable battery performance. This method of manufacturing a sealed lithium secondary battery having an electrode assembly, an electrolyte solution and a sealable metallic or nonmetallic hard case of a given shape includes the steps of housing the electrode assembly, which includes a positive electrode and a negative electrode, and the electrolyte solution within the hard case; negatively pressurizing the interior of the hard case and sealing the hard case in the negatively pressurized state; carrying out, after the sealing step, initial charging so as to adjust the battery to a voltage at which the electrode assembly generates gases; and carrying out, after the initial charging step, main charging so as to charge the battery to a predetermined voltage. During the interval following the sealing step and up until the main charging step, the hard case is maintained in a sealed state so that the interior of the hard case is not open to the atmosphere. |
| US09484601B2 |
Load-managed electrochemical energy generation system
Described embodiments include a system and a method. A system includes a controllable electrochemical cell configured to output electric power. The controllable cell includes an electrolyte and a first working electrode configured to transfer electrons to or from the electrolyte. The controllable cell includes a second working electrode configured to transfer electrons to or from the electrolyte. The controllable cell includes a gating electrode spaced-apart from the second working electrode. The gating electrode is configured, if biased relative to the second working electrode, to modify an electric charge, field, or potential in the space between the electrolyte and the second working electrode. The controllable cell includes a control circuit coupled to the gating electrode of the controllable cell and configured to apply a biasing signal responsive to an electrical property of an external electrical load coupled to the controllable cell. |
| US09484599B2 |
Non-aqueous electrolyte secondary battery
Provided is a non-aqueous electrolyte secondary battery having a high capacity and an improved cycle life. The battery includes an electrode group and a non-aqueous electrolyte, and has a volume energy density of 650 Wh/L or more. The electrode group includes wound positive and negative electrodes with a separator interposed therebetween. The positive and negative electrodes each include a current collector and a material mixture layer adhering thereto. The positive and negative electrode material mixture layers each have a porosity Pp of 22% or less and porosity Pn of 25% or less. The ratio VE/VT of a volume VE of the electrolyte to a total VT of the pore volumes of the positive and negative electrode material mixture layers, and the separator is 1 to 1.5. The difference between contact angles CAp and CAn of the positive and negative electrodes with respect to the non-aqueous electrolyte is 23° or less. |
| US09484596B2 |
Battery system, method for producing battery system, and battery control apparatus
The object of the present invention is to provide a battery system in which reductive decomposition of a Ge-containing solid electrolyte material is restricted. The present invention attains the object by providing a battery system including a battery and a control apparatus, wherein the battery has a cathode active material layer containing a cathode active material, an anode active material layer containing a Si-containing anode active material, and an electrolyte layer formed between the cathode active material layer and the anode active material layer, at least one of the anode active material layer and the electrolyte layer contains a Ge-containing solid electrolyte material, and the control apparatus is an apparatus to control an electric potential of the Si-containing anode active material so as to be reduction potential or less of the Ge-containing solid electrolyte material. |
| US09484595B2 |
Li/metal battery with composite solid electrolyte
In accordance with one embodiment, an electrochemical cell includes a first anode including a form of lithium a first cathode including an electrolyte, and a first composite electrolyte structure positioned between the first anode and the first cathode, the first composite electrolyte structure including (i) a first support layer adjacent the first anode and configured to mechanically suppress roughening of the form of lithium in the first anode, and (ii) a first protective layer positioned between the first support layer and the first cathode and configured to prevent oxidation of the first support layer by substances in the first cathode. |
| US09484591B2 |
Voltage sensing member and battery module employed with the same
Disclosed herein is a voltage sensing member for sensing the voltage of battery cells constituting a battery module, the voltage sensing member comprising: (a) a pair of supporting parts mounted to the bottom of the battery module at regions (the front and rear parts of the battery module) corresponding to electrode terminal connections of the battery cells; (b) connection parts for electrically connecting the supporting parts to a connector; (c) a plurality of conductive sensing parts protruding upward while one end of each is connected to the corresponding support part and the other end of each is elastically connected to electrode terminals of the battery cells; and (d) the connector mounted on the front part or the rear part of the battery module for transmitting the sensed voltage of the battery cells to a battery management system (BMS). |
| US09484587B2 |
Method of operating electrochemical cells comprising electrodeposited fuel
An electrochemical cell system and a process for operating the same, the system having at least two fuel electrodes for receiving electrodeposited metal fuel; at least one oxidant electrode spaced apart from the fuel electrode; at least one charging electrode; an ionically conductive medium communicating the electrodes of the electrochemical cell system for conducting ions to support electrochemical reactions at the fuel, oxidant, and charging electrodes; and, one or more controllers configured to operate the cell system in discharging and charging modes and monitor a state of charge for each fuel electrode. The controllers may assign each fuel electrode in a discharging unit having a state-of-charge meeting a predetermined depletion criteria from the discharging unit to the charging unit, and each fuel electrode in the charging unit having a state-of-charge meeting a predetermined loading criteria from the charging unit to the discharging unit. |
| US09484583B2 |
Fuel cell electrode catalyst having graduated layers
Embodiments of electrode assemblies and fuel cells having increased catalyst durability are provided. One embodiment of an electrode assembly for a fuel cell comprises a first catalyst layer adjacent an electrolyte membrane comprising first active catalyst particles supported on first support particles having a first support size and a second catalyst layer adjacent the first catalyst layer opposite the electrolyte membrane comprising second active catalyst particles supported on second support particles having a second support size. The first support particles are a non-carbon support. |
| US09484582B2 |
Fuel cell catalyst treatment
According to an embodiment, a method of preparing a catalyst for a fuel cell component includes soaking catalyst particles in citric acid. The catalyst particles are then rinsed after having been soaked in the citric acid. Catalyst particles are dried after they have been rinsed. When desired, the pre-treated catalyst particles may be incorporated into a catalyst ink used for making a fuel cell component. |
| US09484581B2 |
Integrally molded gasket for a fuel cell assembly
A fuel cell membrane electrode assembly (MEA) comprising first and second gas diffusion layers and an ion exchange membrane disposed between the diffusion layers. Each diffusion layer includes an inner surface facing the membrane, an outer surface opposite the inner surface, and a side surface defining a perimeter of the diffusion layers. An outboard region extends about the diffusion layers at the perimeter. The outboard region surrounds an inboard region. The outboard region has a low density region proximate to the side surface and a high density region between the low density region and the inboard portion. A seal is mounted at the low density region. The high density region prevents portions of the seal from entering the inboard region thereby damaging the MEA. The seal includes a first rim having a smaller radius than a second rim. |
| US09484579B2 |
Binder composition for rechargeable battery and rechargeable lithium battery having the same
A binder composition for a rechargeable battery, including a binder polymer having a glass transition temperature (Tg) of 20° C. or less, and having a storage modulus (60° C.) of 50-150 MPa. The binder composition according to an embodiment can improve life characteristics of the rechargeable battery by efficiently controlling expansion of a negative electrode plate. |
| US09484575B2 |
Cathode material for an alkali-sulfur cell
In a method for preparing a cathode material for an alkali-sulfur cell, e.g., a lithium-sulfur cell, at least one polyacrilonitrile-sulfur composite material and elemental sulfur are mixed, in order to increase the voltage, the capacitance and the energy density. |
| US09484571B2 |
Cathode for a cell of a lithium-ion battery, its manufacturing process and the battery incorporating it
The invention relates to a cathode that is usable in a cell of a lithium-ion battery comprising an electrolyte based on a lithium salt and on a non-aqueous solvent, to a process for manufacturing this cathode and to a lithium-ion battery having one or more cells incorporating this cathode. This cathode is based on a polymer composition, obtained by melt processing and without solvent evaporation, that is the product of a hot compounding reaction between an active material and additives including a polymer binder and an electrically conductive filler. According to the invention, the binder is based on at least one crosslinked elastomer and the additives furthermore comprise at least one non-volatile organic compound usable in the electrolyte solvent, the composition advantageously includes the active material in a mass fraction greater than or equal to 90%. |
| US09484570B2 |
Method for producing electrode for electrochemical element
It is an object of the present invention to provide a method for producing an electrode for an electrochemical element, which can easily adjust a capacity and can produce the electrochemical element at low cost. The method for producing an electrode for an electrochemical element of the present invention includes a thickness adjustment step of compressing an aluminum porous body having continuous pores to adjust the thickness of the aluminum porous body to a predetermined thickness, and a filling step of filling the aluminum porous body, the thickness of which is adjusted, with an active material. |
| US09484567B2 |
Battery pack
A battery pack includes battery cells, at least one terminal having a shape that enables connection with another device, and electric connectors located between at least two of the battery cells and between one of the battery cells and the at least one terminal. At least one of the electric connectors breaks a current path when contacting water. |
| US09484565B2 |
Energy storage device
In an energy storage device including a positive electrode plate and a negative electrode plate that are insulated from each other with a separator interposed therebetween, and a non-aqueous electrolyte, the separator includes a base material layer and a coating layer that is disposed on at least one surface of the base material layer, and the separator has an air permeability of the base material layer of 25 (sec/100 cc) or greater and 250 (sec/100 cc) or less, a porosity of the base material layer of 45% or greater, an air permeability of an interface between the base material layer and the coating layer of 15 (sec/100 cc) or less, and an air permeability of the coating layer of 15 (sec/100 cc) or less. |
| US09484562B2 |
Traction battery assembly
A traction battery assembly includes a base plate and a plurality of prismatic cells stacked in an array on the base plate. A spacer assembly surrounds and is in contact with at least a portion of each of the cells. Each of the spacers assemblies include a pair of brackets having retaining tabs configured to extend over and retain a top portion of the cell opposite the base plate and anchoring tabs extending away from a base of the array. A clamp is disposed along the array and is configured to anchor the anchoring tabs to the base. |
| US09484561B2 |
Prismatic battery pack with novel structure
Disclosed herein is a prismatic battery pack including an electrode assembly of a cathode/separator/anode structure impregnated with an electrolyte, a prismatic container, in which the electrode assembly is mounted, the prismatic container having at least one depressed groove formed at a bottom thereof in a longitudinal direction of the prismatic battery pack, a cap plate coupled to an open upper end of the prismatic container, in which the electrode assembly is mounted, a protection circuit module (PCM) including a protection circuit to control operation of the prismatic battery pack, the PCM being loaded on the cap plate, and an insulative cap mounted to the prismatic container while surrounding the PCM. |
| US09484560B2 |
Electric device having a round corner and including a secondary battery
An electric device has a curved structure formed at at least one position of an outside thereof. At least one secondary battery having an external appearance corresponding to a shape of the curved structure is mounted at the position of the electric device at which the curved structure is formed. The secondary battery is a battery cell having an electrode assembly including a cathode, an anode, and a separator disposed between the cathode and the anode mounted in a battery case or a battery pack having the battery cell mounted in a pack case. |
| US09484551B2 |
Organic EL display provided with gel-state encapsulant incorporating a desiccant and a high molecular-weight medium
A sealing substrate is arranged to oppositely face an element substrate on which organic EL layers are formed in a matrix array with a sealing material sandwiched therebetween. A gel-state desiccant is filled in an inner space surrounded by the element substrate, the sealing substrate and the sealing material. Since the gel-state desiccant is in a gel state, the gel-state desiccant is flexibly filled in the inner space of the organic EL display device thus completely eliminating a gap. Since the inner space is filled with the gel-state desiccant, moisture hardly intrudes into the inner space from the outside and, at the same time, a mechanical strength of the organic EL display device is also enhanced. |
| US09484548B2 |
Organic light emitting diode display
An organic light emitting device includes a pixel electrode, a hole auxiliary layer formed on the pixel electrode, an organic emission layer formed on the hole auxiliary layer, an electron auxiliary layer formed on the organic emission layer, and a common electrode layer formed on the electron auxiliary layer. An electric field dependency of electron mobility is increased by increasing an energetic disorder or decreasing a positional disorder for the organic emission layer. |
| US09484546B2 |
OLED with compact contact design and self-aligned insulators
OLEDs and techniques for fabricating OLEDs are provided, in which the OLED has a shortest lateral current path through an active region that is longer than the shortest lateral electric field line within the active region. Such configurations prevent “hot spots” in the OLED panel, leading to a more uniform emission by the panel. |
| US09484545B2 |
Organic electroluminescent element and lighting device
Provided is an organic electroluminescent element that can obtain white light with excellent color rendering properties and is particularly suitable for a light source of a lighting device. The organic electroluminescent element includes a plurality of light emitting units that are provided between a cathode and an anode and include at least a light emitting layer made of an organic compound. White light emitted from the plurality of light emitting units has a continuous emission spectrum (S) in a wavelength range of at least 380 nm to 780 nm. The emission spectrum (S) includes one peak wavelength (p1) in a red wavelength range (R) of 600 nm to 640 nm, one peak wavelength (p2) in a green wavelength range G of 500 nm to 540 nm, and two peak wavelengths (p3) and (p4) in a blue wavelength range B of 440 nm to 490 nm. |
| US09484544B2 |
Organic electroluminescent device with multiple phosphorescent emitters
A multiple emitter organic light emitting diode (OLED) is provided. The OLED comprises a host having a triplet energy gap. At least one emitter having a triplet energy gap greater than the triplet energy gap of the host is doped into the host and at least one other emitter having a triplet energy gap less than the triplet energy gap of the host is also doped into the host. |
| US09484542B2 |
Thin film transistor panel and method of manufacturing the same, and electronic device including the thin film transistor panel
A thin film transistor panel includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, an organic semiconductor overlapping with the gate electrode, a source electrode and a drain electrode electrically connected to the organic semiconductor, a fluorine-containing organic insulation layer covering the organic semiconductor, and a photosensitive organic insulation layer covering the fluorine-containing organic insulation layer. |
| US09484535B1 |
High density resistive random access memory (RRAM)
A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line. |
| US09484534B2 |
Via formation for cross-point memory
Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device. |
| US09484532B2 |
Semiconductor device and method for producing semiconductor device
The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. |
| US09484523B2 |
Bistable piezoelectric cantilever vibration energy generator based on spherical composite structure and partial separation of different layers
Implementations herein relate to a bistable piezoelectric cantilever vibration energy generator based on spherical composite structure with partial separation of different layers that includes a beam bracket and a shell. The shell is spherical, the bottom of the shell has a circular opening. The beam bracket and the shell are fixed to the base respectively. Vibration of the beam bracket can cause deformation of the piezoelectric cantilever beam, the piezoelectric cantilever beam generates electrical energy using the piezoelectric effect during deformation. The bistable piezoelectric cantilever vibration energy generator further includes twenty-five piezoelectric oscillator structures, and the lengths of the cantilever beam in the same layer are different such as to form a wide resonance frequency domain and to substantially increase power generation. |
| US09484520B2 |
Method for producing flexible EAP generators
In a method for manufacturing electroactive polymer generators, a strip, including one layer of an electroactive polymer and electrodes applied to sections of this layer, is spirally wound in such a way that multiple electrodes are situated congruently on top of each other, in each case two electrodes situated on top of each other being separated from each other by a layer of electroactive polymer. |
| US09484518B2 |
Tubular thermoelectric module and method for producing the module
A method for producing a thermoelectric module and a tubular thermoelectric module include at least an inner tube, an outer tube and an interspace therebetween. At least a plurality of rings each formed by a plurality of n-doped and p-doped semiconductor elements disposed alternately in a circumferential direction are disposed in succession in an axial direction of the thermoelectric module in the interspace. On an inner side or an outer side of the semiconductor elements of one ring, electrically conductive first connections run only in the circumferential direction and, on an opposite outer side or inner side, at least one electrically conductive second connection electrically conductively connects an n-doped to a p-doped semiconductor element of an adjacent ring and runs at least in the axial direction of the thermoelectric module. |
| US09484516B2 |
Method for preparing electroconductive polymer and thermoelectric device comprising electroconductive polymer film prepared using the same
There are provided a method for producing an electroconductive polymer which can be operated at a low temperature such as the human body temperature, is safe to the human body, and is flexible and useful as a thermoelectric material, and a thermoelectric element including a thin film of an electroconductive polymer produced by the production method. |
| US09484513B2 |
Semiconductor light emitting device with thick metal layers
A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature. |
| US09484512B2 |
Light emitting device, and substrate for light emitting device
A light emitting device includes a substrate, conductive members, and first and second light emitting elements. The conductive members have first to fourth lands and a linking portion linking the second and third lands. An outer edge of the first land is positioned to the inside of a point at which an extension of a side facing the second land and an extension of a side facing the third land intersect. An outer edge of the fourth land is positioned to the inside of a point at which an extension of a side facing the second land and an extension of a side facing the third land intersect. The first light emitting element has electrodes connected to the first and second lands, and the second light emitting element has electrodes connected to the third and fourth lands. |
| US09484511B2 |
Light emitting device and method for manufacturing same
A light emitting device includes a light emitting element, a terminal substrate and a fixing member. The light emitting element is a semiconductor laminate having a first semiconductor layer, a light emitting layer, and a second semiconductor layer that are laminated in that order, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The terminal substrate includes a pair of terminals connected to the first electrode and the second electrode, and an insulator layer that fixes the terminals. At least a part of the outer edges of the terminal substrate is disposed more to a center of the light emitting device than the outer edges of the semiconductor laminate. The fixing member fixes the light emitting element and the terminal substrate. |
| US09484510B2 |
Lens and light emitting module for surface illumination
An exemplary embodiment of the present invention discloses a light-emitting module including a circuit board, a light-emitting device disposed on the circuit board, and a lens disposed on the circuit board and configured to distribute light emitted from the light emitting device. The lens includes a concave portion having an incidence surface configured to receive incident light emitted from the light-emitting device, and the light emitting device is disposed within the concave portion of the lens. |
| US09484508B2 |
Optoelectronic semiconductor component
The invention relates to an optoelectronic semiconductor component, which has a carrier element (1), on which an optoelectronic semiconductor chip (2) having at least one active layer is arranged, wherein the active layer is designed to emit or receive light during operation and wherein the semiconductor chip (2) is covered with a protective layer (3) that contains poly-para-xylenes. |
| US09484505B2 |
LED structure applied to backlight source
An LED structure is applied to a backlight source to set a white light of a backlight module at a standard D65 position of the CIE1931 chromaticity coordinates and used together with a display module. A red phosphor for emitting a red light, a yellow phosphor for emitting a yellow light, and a blue light LED chip are provided. The mixing ratio of the red phosphor to the yellow phosphor is controlled within a range of (2.33−1):1, so that the original LED white light falls within a region enclosed by ccy≦1.8*ccx−0.12, ccy≧1.8*ccx−0.336, ccy≦0.33 and ccy≧0.15 of the CIE1931 coordinates. Since the red phosphor does not absorb or convert yellow light, the brightness loss of the yellow light that excites the yellow phosphor is minimized. A color filter may be installed to achieve better NTSC effect and luminous efficacy. |
| US09484502B2 |
Light emitting device and method for manufacturing the same
By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same. |
| US09484500B2 |
Semiconductor light emitting device and method of manufacturing the same
A semiconductor light emitting device and method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The device may also includes a first electrode connected to the first conductivity type semiconductor layer, and a second electrode connected to the second conductivity type semiconductor layer and having a pad region and a finger region extended from the pad region in one direction. The second electrode may include a transparent electrode part positioned on the second conductivity type semiconductor layer and including at least one opening therein, at least one reflective part spaced apart from the transparent electrode part within the opening and disposed in the pad region and the finger region, and a bonding part positioned on at least one portion of the reflective part and including a plurality of bonding finger parts spaced apart from each other in the finger region and a bonding pad part disposed in the pad region. |
| US09484499B2 |
Transparent ohmic contacts on light emitting diodes with carrier substrates
A light emitting diode is disclosed that includes an active structure formed of at least p-type and n-type epitaxial layers of Group III nitride on a conductive carrier substrate. A conductive bonding system joins the active structure to the conductive carrier substrate. A first transparent ohmic contact is on the active structure adjacent the conductive carrier substrate, a second transparent ohmic contact is on the active structure opposite the conductive carrier substrate, and a third ohmic contact is on the conductive carrier substrate opposite from the active structure. |
| US09484497B2 |
Surface treatment of a semiconductor light emitting device
A semiconductor light-emitting device includes a semiconductor structure having a light-emitting region. A surface of the semiconductor structure has flattened peaks. |
| US09484496B2 |
Light emitting device, method of manufacturing the same, light emitting device package and lighting system
A light emitting device includes an active layer formed between first and second semiconductor layers. The first semiconductor layer includes a first surface facing the active layer, a second surface opposing the first surface, and a side surface that includes a stepped portion. The stepped portion causes the side surface to extend beyond one of the first surface or second surface of the first semiconductor layer. A light emitting device may also be formed with a buffer layer that includes a stepped portion, and a light emitting device package and system may be formed from the light emitting devices. |
| US09484495B2 |
Semiconductor light-emitting element and method for manufacturing the same
A semiconductor light-emitting element includes: a double-mesa structure of semiconductor formed to have a cylindrical cross section; an insulating member formed to fill a space surrounding the double-mesa structure, with the insulating member comprising a lower insulating member and an upper insulting member covering the lower insulating member; and a first electrode formed on the upper insulating member to come into contact with part of a top surface of the double-mesa structure. The lower insulating member has multiple lower air pillars that are formed in an area aligning with the first electrode, and the upper insulating member has multiple upper air pillars that are formed around the first electrode. It has low dielectric constant and reduced electrical parasitics especially parasitic capacitances, thereby improving high frequency performance and improving modulation speed of light-emitting device finally. |
| US09484492B2 |
LED structures for reduced non-radiative sidewall recombination
LED structures are disclosed to reduce non-radiative sidewall recombination along sidewalls of vertical LEDs including p-n diode sidewalls that span a top current spreading layer, bottom current spreading layer, and active layer between the top current spreading layer and bottom current spreading layer. |
| US09484489B2 |
Engineered band gaps
An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions. The first and second semiconducting atomically thin layers are located proximate to each other, and an angular difference between the first lattice direction and the second lattice direction is between about 0.000001° and 0.5°, or about 0.000001° and 0.5° deviant from of a Vicnal angle of the first and second semiconducting atomically thin layers. Alternatively, or in addition to the above, the first and second semiconducting atomically thin layers may form a Moiré superlattice of exciton funnels with a period between about 50 nm to 3 cm. The optoelectronic device may also include charge carrier conductors in electrical communication with the semiconducting atomically thin layers to either inject or extract charge carriers. |
| US09484488B1 |
CIGSSe thin film for solar cell, preparation method thereof and its application to thin film solar cell
Provided is a CIGSSe thin film for a solar cell, a method for preparing the same, and a solar cell using the same. More particularly, the CIGSSe thin film for a solar cell shows a decrease in peak intensity of sulfur from the surface of the thin film to the local minimum value point of sulfur content in the depth direction, after the analysis based on the Auger electron spectroscopy, and thus controls the band-gap in the thin film. Therefore, the solar cell including the CIGSSe thin film shows an excellent effect in improving photoelectric conversion efficiency. |
| US09484481B2 |
Radiograph detector and method for manufacturing the same
A radiograph detector includes: a fluorescent layer, a bonding layer, and a light detector disposed in this order, wherein the fluorescent layer includes fluorescent particles, first binder resin, and second binder resin, and the second binder resin contains a binder polymer identical to a bonding layer forming polymer contained in the bonding layer. |
| US09484479B2 |
Solar cell module and manufacturing method thereof
A solar cell module in the present invention includes: a wiring member electrically connecting solar cell elements to each other; and a structure in which a solder bonding portion is formed by bonding a collecting electrode, which is provided on a light receiving surface of the solar cell element, extends in a first direction parallel to the wiring member, and has a width smaller than that of the wiring member in a cross section vertical to the first direction, and the wiring member together by melting solder, a cross-sectional shape of the solder bonding portion vertical to the first direction has a shape that gradually narrows toward the collecting electrode from a lower surface of the wiring member, and a side surface of the solder bonding portion and a side surface of the wiring member are covered with a thermosetting resin. |
| US09484478B2 |
Solar cell module
A second protective member faces a first protective member. A bonding layer is disposed between the first and the second protective member. A solar cell includes a first main surface facing a side of the first protective member and a second main surface facing a side of the second protective member. A wiring member disposed on the second main surface. The bonding layer includes a first bonding layer disposed between the first protective member and the solar cell and made of a transparent resin a second bonding layer disposed between the second protective member and the solar cell and made of a colored resin, and a third bonding layer disposed between the second bonding layer and the solar cell and made of a transparent resin, and the second bonding layer is in contact with a main surface of the wiring member on a side of the second protective member. |
| US09484476B2 |
Photoelectric conversion device
It is an object of the present invention to improve photoelectric conversion efficiency in a photoelectric conversion device. The photoelectric conversion device according to the present invention uses a polycrystalline semiconductor layer including a plurality of semiconductor particles coupled together as a light-absorbing layer, each of the semiconductor particles including a group I-III-VI compound, each of the semiconductor particles having a higher composition ratio PI of a group I-B element to a group III-B element in a surface portion thereof than that in a central portion thereof. |
| US09484475B2 |
Semiconductor ferroelectric compositions and their use in photovoltaic devices
Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid solution of KNbO3 and BaNi1/2Nb1/2O3-delta, wherein delta is in the range of from 0 to about 1. The specification also discloses photovoltaic devices comprising one or more solar absorbing layers, wherein at least one of the solar absorbing layers comprises a semiconducting ferroelectric layer. Finally, this patent application provides solar cell, comprising: a heterojunction of n- and p-type semiconductors characterized as comprising an interface layer disposed between the n- and p-type semiconductors, the interface layer comprising a semiconducting ferroelectric absorber layer capable of enhancing light absorption and carrier separation. |
| US09484473B2 |
Anti-reflection glass substrate
A glass substrate of which at least one surface multiple concave and convex portions. Rp representing the size of the convex portion is 37 nm to 200 nm; a tilt angle θp indicating a maximum frequency in the frequency distribution of a tilt angle θ of the convex portion is 20° to 75°; and an absolute value of a difference between θp and θ50 (θp−θ50) is 30° or less, where θ50 indicates a value showing 50% of a cumulative frequency distribution of the tilt angle θ. The concave and convex portion is such that the surface roughness (Ra) is 2 nm to 100 nm, the maximum height difference (P−V) is 35 nm to 400 nm, and the area ratio (S-ratio) is 1.1 to 3.0. |
| US09484472B2 |
Semiconductor device, electrical device system, and method of producing semiconductor device
A semiconductor device includes a first semiconductor layer having a first conductive type; a circuit layer including a second semiconductor layer; and a plurality of layered members. Each of the layered members includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film. The second semiconductor layer includes a circuit element. The layered members form a multilayer wiring layer. The semiconductor device further includes a penetrating conductive member; a conductive portion; and a first conductive type region. The penetrating conductive member penetrates from the first semiconductor layer to the interlayer insulation film of the layered member at the highest position. The conductive portion includes an electrode formed in the wiring layer of the layered member at the highest position and connected to the penetrating conductive member. The first conductive type region has an impurity concentration greater than that of the first semiconductor layer. |
| US09484469B2 |
Thin film device with protective layer
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer. |
| US09484467B2 |
Semiconductor device
A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer. |
| US09484465B2 |
Array substrate, manufacturing method thereof and display device
A array substrate is disclosed. The array substrate includes: a substrate (10); and a first gate metal layer (111), a first gate insulating layer (121), a semiconductor layer (13) and a source-drain electrode layer (14) disposed in this order on the substrate from bottom to top. The array substrate (10) further includes a second gate insulating layer (122) disposed on the source-drain electrode layer (14); and a second gate metal layer (112) disposed on the second gate insulating layer (122). A method of manufacturing an array substrate is also disclosed. |
| US09484464B2 |
Structure and method for adjusting threshold voltage of the array of transistors
A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. |
| US09484462B2 |
Fin structure of fin field effect transistor
An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location. |
| US09484461B2 |
Integrated circuit structure with substrate isolation and un-doped channel
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over the fin structure; source/drain regions over the substrate and disposed on opposing sides of the gate stack; a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped; and a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide. |
| US09484459B2 |
Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material. |
| US09484454B2 |
Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V. |
| US09484453B2 |
Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of the gate oxide It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09484450B2 |
Integrated channel diode
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor. |
| US09484442B2 |
Method of fabricating thin-film transistor substrate
A method of fabricating a TFT substrate in which a thin-film transistor is formed on a substrate, includes: forming an oxide semiconductor layer above the substrate; forming a first oxide film on the oxide semiconductor layer; performing an oxidation treatment on the oxide semiconductor layer, after the first oxide film is formed; and forming a second oxide film above the first oxide film, after the oxidation treatment is performed. In the performing of the oxidation treatment, at least one parameter of the oxidation treatment is set, based on a predetermined relationship between the at least one parameter and the threshold value of the thin-film transistor, so that the threshold value becomes a predetermined value. |
| US09484440B2 |
Methods for forming FinFETs with non-merged epitaxial fin extensions
Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins. |
| US09484438B2 |
Method to improve reliability of replacement gate device
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. |
| US09484431B1 |
Pure boron for silicide contact
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2. |
| US09484426B2 |
Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor. |
| US09484424B2 |
Semiconductor device with a NAND circuit having four transistors
A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area. |
| US09484411B1 |
Integrated circuit and a method to optimize strain inducing composites
A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed. |
| US09484408B1 |
Bipolar junction transistor layout
A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector. |
| US09484407B2 |
Methods of forming a nanowire transistor device
A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress. |
| US09484406B1 |
Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer. |
| US09484401B2 |
Capacitance reduction for advanced technology nodes
After forming source/drain contact trenches to expose source/drain regions, contact liner material layer portions are formed on sidewalls and bottom surfaces of the source/drain contact trenches. Contact material layer portions are then formed over the contact liner material layer portions to fill in the source/drain contact trenches. At least portions of the contact material layer portions and the contact liner material layer portions present on sidewalls of the source/drain contact trenches are removed to provide source/drain contacts with reduced contact capacitance. |
| US09484389B2 |
Three-dimensional resistive memory array
A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed. |
| US09484386B2 |
Diffraction grating with multiple periodic widths
An integrated circuit includes a substrate, a plurality of photo detectors formed in the substrate, and a diffraction grating having multiple sections disposed over the plurality of photo detectors. Each section of the diffraction grating has a respective periodic width for a respective target wavelength. The diffraction grating has at least two different target wavelengths. The diffraction grating is interlaced with filters. The filters in each section of the diffraction grating are configured to pass a respective electromagnetic wave with the respective target wavelength. |
| US09484385B2 |
Method for fabricating an image sensor package
An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via hole for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced. |
| US09484383B2 |
Solid-state image pickup device, method of manufacturing thereof, and electronic apparatus
Provided is a solid-state image pickup device including: a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion. |
| US09484382B2 |
Image sensor and manufacturing method thereof
According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region. |
| US09484380B1 |
Backside illumination (BSI) image sensor and manufacturing method thereof
A back side illumination image sensor includes a substrate including a front side and a back side opposite to the front side, a plurality of sensing elements formed in the substrate, a plurality of isolation structures isolating each element, and a plurality of cambered surfaces formed on the back side of the substrate. The cambered surfaces are formed correspondingly to the sensing elements, respectively. |
| US09484378B2 |
Semiconductor devices including back-side integrated circuitry
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings. At least one laterally extending conductive element may be electrically connected to a first transistor or capacitor and may extend laterally underneath a second, different transistor or capacitor to which the laterally extending conductive element is not electrically connected. |
| US09484356B2 |
Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer. |
| US09484350B2 |
Semiconductor device having an inter-layer via (ILV), and method of making same
A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device. |
| US09484341B2 |
Mom capacitor circuit and semiconductor device thereof
A capacitor circuit formed by a plurality of capacitors using metal electrodes formed on a substrate is provided, such that the capacitance of the capacitor can be adjusted with higher precision as compared to the conventional art. The MOM capacitor includes a plurality of MOM (Metal-Oxide-Metal) capacitors respectfully formed by pairs of metal electrodes facing each other through an insulating film on a substrate. The MOM capacitor circuit is formed by at least one capacitor element in a manner that each of the pairs of the metal electrodes of the MOM capacitors is connected to a first terminal and a second terminal through a connecting conductor; and at least one switch element, connected to the plurality of metal electrodes and at least one of the first terminal and the second terminal, wherein a capacitance of the MOM capacitor circuit is adjusted by turning on/off the switch element. |
| US09484340B2 |
Semiconductor device and method of manufacturing the same
Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode. |
| US09484338B2 |
Diode string implementation for electrostatic discharge protection
A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string. |
| US09484336B2 |
Semiconductor device, semiconductor device mounting structure and power semiconductor device
A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. |
| US09484330B2 |
Light-emitting device
A light-emitting device includes light-emitting units and an electrical connection layer. Each light-emitting unit includes a light-emitting stacking layer, a first electrode layer, an insulation layer, and a second electrode layer. The light-emitting stacking layer includes first and second-type doped semiconductor layers, an active layer, and a first inner opening passing through the second-type doped semiconductor layer and the active layer. The second electrode layer is close to and is electrically connected to the second-type doped semiconductor layer. The insulation layer is disposed on a sidewall of the first inner opening and forms a second inner opening. The first electrode layer is disposed in the second inner opening and electrically connected to the first-type doped semiconductor layer. The electrical connection layer is electrically connected to the first electrode layer of one of two adjacent light-emitting units and the second electrode layer of the other adjacent light-emitting unit. |
| US09484329B2 |
Light emitter array layout for color mixing
Solid state lighting components are disclosed having multiple discrete light sources whose light combines to provide the desired emission characteristics. One embodiment of an LED component according to the present invention comprises a rectangular submount. A first group of blue shifted yellow (BSY) LED chips, a second group of BSY LED chips and a group of red LED chips are mounted on the submount. A plurality of contacts is arranged along one of the edges of the submount and accessible from one side of the component for applying electrical signals to the groups of LED chips. |
| US09484328B2 |
Backside through silicon vias and micro-channels in three dimensional integration
Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled. |
| US09484321B2 |
High frequency device
A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame. |
| US09484320B2 |
Vertically packaged integrated circuit
A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate. |
| US09484319B2 |
Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate. |
| US09484318B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer. |
| US09484313B2 |
Semiconductor packages with thermal-enhanced conformal shielding and related methods
The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding. |
| US09484311B2 |
Chip package and packaging method
A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate. |
| US09484310B2 |
Invisible dummy features and method for forming the same
A plurality of first miniature elements of an overlay mark is formed in a first layer. A plurality of second miniature elements of the overlay mark is formed in a second layer different from the first layer. A plurality of dummy features is formed around the overlay mark. The dummy features are formed such that they each have a dimension below a resolution of an alignment detection tool configured to optically scan the overlay mark in an alignment process. |
| US09484307B2 |
Fan-out wafer level packaging structure
Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer. |
| US09484306B1 |
MOSFET with asymmetric self-aligned contact
A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates. |
| US09484301B2 |
Controlled metal extrusion opening in semiconductor structure and method of forming
Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer. |
| US09484299B2 |
Signal line connection structure and apparatus using the same
The present disclosure relates to a signal line connection structure and apparatuses using the same. The signal line connection structure according to an embodiment of the present disclosure comprises a first signal line and a second signal line, one end of the first signal line and one end of the second signal line corresponding to each other and being connected through a conductive layer; and a first tip end arranged in the first signal line; and a second tip end arranged in the second signal line. The first tip end and the second tip end are arranged as opposed to but not connected with each other, and static charges in the first signal line and the second signal line are discharged through the first tip end and the second tip end. |
| US09484297B2 |
Semiconductor device having non-magnetic single core inductor and method of producing the same
Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench. |
| US09484296B2 |
Self-aligned integrated line and via structure for a three-dimensional semiconductor device
At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures. |
| US09484295B2 |
Image forming apparatus, chip, and chip package to reduce cross-talk between signals
An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals. |
| US09484291B1 |
Robust pillar structure for semicondcutor device contacts
Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper. |
| US09484286B2 |
Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. |
| US09484284B1 |
Microfluidic impingement jet cooled embedded diamond GaN HEMT
A MMIC power amplifier circuit assembly comprised of a SiC substrate having a plurality of microchannels formed therein, where a diamond layer is provided within each of the microchannels. A plurality of GaN HEMT devices are provided on the substrate where each HEMT device is positioned directly opposite to a microchannel. A silicon manifold is coupled to the substrate and includes a plurality of micro-machined channels formed therein that include a jet impingement channel positioned directly adjacent each microchannel, a return channel directly positioned adjacent to each microchannel, a supply channel supplying a cooling fluid to the impingement channels and a return channel collecting heated cooling fluid from the supply channels so that an impingement jet is directed on to the diamond layer for removing heat generated by the HEMT devices. |
| US09484279B2 |
Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die. |
| US09484275B2 |
Semiconductor module for high pressure applications
A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips installed on the base plate, a first power supply connected to the plates, a second power supply connected to the plates and an electrically insulating outer casing component. The semiconductor chips are individually in contact with the top plates. Each semiconductor chip comprises a first electrode electrically coupled with the base plate, and a second electrical pole electrically coupled with the corresponding top plate. The first power supply connecting plate is equipped with protruding parts that are individually in electrical contact with the top plates. The second power supply connecting plate is electrically connected to the base plate. The outer casing component is used to integrate the first power supply connecting plate and the second power supply connecting plate. The outer casing component comprises at least one opening. |
| US09484271B2 |
Semiconductor device and method of manufacturing the same
Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. |
| US09484270B2 |
Fully-depleted silicon-on-insulator transistors
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage. |
| US09484267B1 |
Stacked nanowire devices
A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material. |
| US09484266B1 |
Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET
A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins. |
| US09484261B2 |
Formation of self-aligned source for split-gate non-volatile memory cell
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type. |
| US09484260B2 |
Heated carrier substrate semiconductor die singulation method
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. Heat is applied to the first carrier substrate while the localized pressure is applied. |
| US09484259B2 |
Semiconductor device and method of forming protection and support structure for conductive interconnect structure
A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer. |
| US09484255B1 |
Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill. |
| US09484252B2 |
Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer. |
| US09484246B2 |
Buried signal transmission line
A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit. |
| US09484244B2 |
Structures and methods for forming fin structures
Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices. |
| US09484240B2 |
Film adhesive, dicing tape with film adhesive, method of manufacturing semiconductor device, and semiconductor device
The present invention provides a film adhesive that can prevent a thermal effect to a semiconductor wafer and that can suppress warping of the semiconductor wafer; a dicing tape with a film adhesive; and a method of manufacturing a semiconductor device.The present invention relates to a film adhesive comprising a thermoplastic resin and electrically conductive particles, the film adhesive having an adhesion strength measured at 25° C. after the film adhesive is pasted to a mirror silicon wafer at 40° C. of 0.5 N/10 mm or more. |
| US09484238B2 |
Attachment method
An attachment method including an overlapping step of overlapping a support plate over a substrate under a reduced pressure environment; a temporary fixing step of temporarily fixing the support plate to the substrate; and an attaching step of attaching the support plate to the substrate under a reduced pressure environment. The method further includes, prior to the overlapping step, at least one of a first heating step in which heating is performed under an atmospheric pressure environment and a second heating step in which heating is performed under a reduced pressure environment. |
| US09484231B2 |
Temperature controller for semiconductor manufacturing equipment, method for calculating PID constants in semiconductor manufacturing, and method for operating temperature controller for semiconductor manufacturing equipment
A temperature adjustment system configured to adjust the temperature of a fluid used in a semiconductor manufacturing apparatus includes: a heat exchanger including therein a temperature adjuster for heating and cooling the fluid, the heat exchanger being configured to perform heat exchange between the fluid therein and the temperature adjuster; a temperature sensor configured to measure the temperature of the fluid; a PID-constant calculator configured to calculate PID constants for PID control based on the physical properties of the fluid and a time constant of the temperature sensor; and a PID-control calculator configured to perform the PID control on the temperature adjuster with the PID constants calculated by the PID-constant calculator. |
| US09484229B2 |
Device and method for processing wafer-shaped articles
A device for processing wafer-shaped articles includes a spin chuck for holding and rotating a wafer-shaped article about a rotation axis and at least one dispenser for dispensing liquid onto at least one surface of a wafer-shaped article. A liquid collector surrounds the spin chuck for collecting liquid spun off the substrate during rotation, with at least two collector levels for separately collecting liquids in different collector levels. At least one lifting device moves the spin chuck relative to the liquid collector. At least two exhaust levels are provided for separately collecting gas from an interior of the liquid collector. Each of the exhaust levels includes at least one opening communicating with an ambient exterior of the liquid collector and a door that closes and opens the opening. Each door on one of the exhaust levels can be opened and closed separately from each door on another exhaust level. |
| US09484228B2 |
Simultaneous independently controlled dual side PCB molding technique
Molding assemblies and methods for dual side package molding are described. In an embodiment, a molding compound is injected into a front cavity with a first actuator, and a molding compound is injected into a back cavity with a second actuator, with the first and second actuator assemblies being independently controlled. In an embodiment, the molding compound flows through a through-hole in a molding substrate from a front side of the molding substrate to a back side of the molding substrate, and into the back cavity. |
| US09484225B2 |
Method for packaging circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly. |
| US09484220B2 |
Sputter etch processing for heavy metal patterning in integrated circuits
A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma. |
| US09484219B2 |
Methods of fabricating memory devices using wet etching and dry etching
A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration. |
| US09484212B1 |
Chemical mechanical polishing method
A chemical mechanical polishing method is provided comprising: providing a substrate, wherein the substrate comprises a silicon oxide and a silicon nitride; providing a polishing slurry; providing polishing pad, comprising: a polishing layer having a composition that is a reaction product of ingredients, comprising: a polyfunctional isocyanate and an amine initiated polyol curative; wherein the stoichiometric ratio of the amine initiated polyol curative to the polyfunctional isocyanate is selected to tune the removal rate selectivity of the polishing layer; creating dynamic contact between the polishing surface and the substrate; dispensing the polishing slurry on the polishing pad at or near the interface between the polishing surface and the substrate; and, removing at least some of the silicon oxide and the silicon nitride from the substrate. |
| US09484209B1 |
Flexible and stretchable sensors formed by patterned spalling
A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together. |
| US09484208B2 |
Preparation method of a germanium-based schottky junction
The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity. |
| US09484206B2 |
Semiconductor device including catalyst layer and graphene layer thereon and method for manufacturing the same
According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area. |
| US09484201B2 |
Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins. |
| US09484198B1 |
Physical vapor deposition of an aluminum nitride film
A method for physical vapor deposition of an aluminum nitride film, comprising: positioning a substrate and an aluminum target in a chamber; vacuuming the chamber so that a chamber pressure is at a base pressure between 7.1×10−7-5×10−6 torr; conducting a working gas composed of argon gas and nitrogen gas into the chamber so that the chamber pressure is at a working pressure between 3-7 mtorr; and depositing the aluminum nitride film on the substrate by applying a high power impulse power supply to the aluminum target and applying a direct current bias power supply to the substrate under the working pressure and a substrate temperature between room temperature (25° C.) to 200° C.; wherein a power of the high power impulse power supply is between 500-600 W and a frequency thereof is between 750-1250 Hz, and a bias of the direct current bias power supply is between −50-0 V. |
| US09484197B2 |
Lateral growth semiconductor method and devices
A method of growing high quality crystalline films on lattice-mismatched or amorphous layers is presented allowing semiconductor materials that would normally be subject to high stress and cracking to be employed allowing cost reductions and/or performance improvements in devices to be obtained. Catalysis of the growth of these films is based upon utilizing particular combinations of metals, materials, and structures to establish growth of the crystalline film from a predetermined location. The subsequent film growth occurring in one or two dimensions to cover a predetermined area of the amorphous or lattice-mismatched substrate. Accordingly the technique can be used to either cover a large area or provide tiles of crystalline material with or without crystalline film interconnections. |
| US09484196B2 |
Semiconductor structures including liners comprising alucone and related methods
A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed. |
| US09484194B2 |
Controlling hydrogen-deuterium exchange on a spectrum by spectrum basis
A mass spectrometer is disclosed comprising a liquid chromatography device for separating ions. A gas phase ion-neutral reaction device is arranged downstream to perform a gas phase ion-neutral reaction such as Hydrogen-Deuterium exchange. A control system is arranged to automatically and repeatedly switch the reaction device back and forth between a first mode of operation and a second mode of operation, wherein in the first mode of operation at least some parent or precursor ions are caused to react within the reaction device and wherein in the second mode of operation substantially fewer or no parent or precursor ions are caused to react. |
| US09484191B2 |
Pulsed remote plasma method and system
A system and method for providing pulsed excited species from a remote plasma unit to a reaction chamber are disclosed. The system includes a pressure control device to control a pressure at the remote plasma unit as reactive species from the remote plasma unit are pulsed to the reaction chamber. |
| US09484187B2 |
Arrangement for transporting radicals
The invention relates to an arrangement for transporting radicals. An electron beam system is presented comprising a beamlet generator; a beamlet manipulator (204) comprising an array of apertures; a plasma generator comprising a chamber for forming a plasma, an inlet receiving input gas and outlets removing plasma or radicals created therein, the plasma generator further comprising outlets in flow connection with the plasma chamber outlets; and a hollow guiding body (309b) guiding radicals formed in the plasma towards the array of apertures for removing contaminant deposition. The hollow guiding body (309b) is removably connectable to an extended portion (307b) of the plasma generator outlet. A cover (400) can be placed over a connection between the hollow guiding body (309b) and the extended portion (307b). The extended portion (307b) of the plasma generator outlet and the hollow guiding body (309b) can be similarly formed as a slit. |
| US09484182B2 |
Charged-particle-beam device and method for correcting aberration
The present invention provides a method and apparatus for correcting an aberration in a charged-particle-beam device. The apparatus includes a charged-particle-beam source, a charged-particle optical system that irradiates a specimen with charged particles emitted from the charged-particle-beam source, an aberration corrector that corrects an aberration of the charged-particle optical system, a control unit that controls the charged-particle optical system and the aberration corrector, a through-focus imaging unit that obtains plural Ronchigrams in which a focal position of the charged-particle optical system is changed, and an aberration calculation unit that divides the obtained Ronchigram into plural local areas, and calculates the amount of the aberration based on line focuses detected in the local areas. |
| US09484178B2 |
Target and X-ray generating tube including the same, X-ray generating apparatus, X-ray imaging system
The target includes a target layer configured to be irradiated with an electron to generate an X-ray and a support substrate configured to support the target layer. The support substrate includes a polycrystalline diamond and includes multiple structure planes having different area densities of plane orientations from one another. The target layer is supported by the support substrate at a structure plane with a smaller area density of the {101} plane than the area density of the {100} plane and the area density of the {111} plane. |
| US09484177B2 |
Longitudinal high dose output, through transmission target X-ray system and methods of use
An X-ray tube for accelerating electrons under a high voltage potential, said X-ray tube includes an evacuated elongated housing that is sealed, a through transmission target anode deposited on an inner surface of said elongated housing, said through transmission target anode configured having a cross-sectional center, a cathode structure disposed in said elongated housing, said cathode structure configured to emit the electrons toward said through transmission target anode, two or more filaments disposed linearly in said elongated housing, said two or more filaments linearly positioned end-to-end proximate said cross-sectional center, said evacuated housing configured to vacuum seal therein said two or more filaments, and, thus, such X-ray tube functions to provide a lengthened, elongated, symmetrical radiation field. |
| US09484174B2 |
Fuse unit
A fuse unit includes a bus bar and an insulating protection portion. The bus bar has a power supply connection portion, an output connection portion, and a terminal installation recess provided around the power supply connection portion. The insulating protection portion is disposed on an outer surface of the bus bar so that portions of a surface of the bus bar in the power supply connection portion, the output connection portion, and the terminal installation recess are exposed from the insulating protection portion. |
| US09484171B2 |
Thermal protector
A thermal protector has superiority in current responsiveness or thermal responsiveness with a simple configuration that does not need a separate manufacturing step of incorporating a resistor. At a stage of press processing for cutting from an original material, a movable plate body part of a movable plate is partitioned into a narrow-width part and a wide-width part by a slim hole. The movable plate is assembled to a fixed conductor with columns of an insulator, a bimetal is assembled to the movable plate, the entire configuration is pressed down by a resinous block, and the entire fixing part is fixed by melting tips of the columns. The wide-width part serves as a normal movable plate, whereas the narrow-width part serves as a conductor in a normal state and as a resistor against an overcurrent. |
| US09484166B1 |
Double-throw switch with positive stops for preventing movement of the stationary contacts
A double-throw switch comprises: a housing; a push button that is mounted for movement with respect to the housing; a first stationary terminal; a second stationary terminal; a moveable terminal that, when in contact with the first stationary terminal, closes a first circuit, and when in contact with the second stationary terminal, closes a second circuit; a first set of one or more positive stops that engage the first stationary terminal; and a second set of one or more positive stops that engage the second stationary terminal. The first set of one or more positive stops applies pressure to and maintains a predetermined position of the first stationary terminal. The second set of one or more positive stops applies pressure to and maintains a predetermined position of the second stationary terminal. |
| US09484165B2 |
Illumination display switching device
An illumination display switching device includes a board, a push button-type switch mounted on the board, a light source mounted on the board, and a switch knob that is supported to a frame member to be slidable in an operation direction of the push button-type switch. The switch knob includes a display design part that is molded with a light-transmitting resin, a non-display design part except for the display design part that is molded with an opaque resin and a light guide member that is integrally molded with the light-transmitting resin of the display design part. The light guide member includes a base part and an arm part, and the base part is integrally molded with the display design part and the arm part extends from the base part and is connected to a switch part of the push button-type switch. |
| US09484163B2 |
Disconnect operating handles suitable for circuit breakers and related bucket assemblies
Disconnect operating handles for circuit breakers are configured with a rotary handle attached to an inwardly oriented shaft that connects to a gear assembly that translates rotational input to linear input. The disconnect operating handles include pivoting lockout levers that automatically “pop” out to expose the lockout space for a padlock when a user touches the lever in an appropriate location. |
| US09484154B2 |
Capacitor device and method for manufacturing same
An object of the invention is to provide a capacitor device that can be made slimmer and lighter and that enables the strength and heat dissipation properties to be improved. A capacitor device (1) has a plurality of capacitor units (2) integrally housed within a housing case (3), the housing case (3) having cylindrical housing sections (5) for housing the capacitor bodies. The housing sections (5) are longitudinally aligned in the same direction and are joined together as an integrated whole. A capacitor unit (2) is inserted via an opening (9) at one end of each of the housing sections (5) so that the entire circumference of the capacitor unit (2) is covered by the corresponding housing section (5). The housing sections (5) have a uniform thickness at least on the outer side along the outer periphery of the capacitor units. |
| US09484149B2 |
Resonance-type non-contact power supply system
A resonance-type non-contact power supply system includes a power-transmission-side metal shield to cover an area around a primary coil and a primary resonance coil. A coaxial cable outer conductor of a power-transmission-side coaxial cable and the power-transmission-side metal shield are threadedly engaged using a coaxial male connector and a coaxial female connector. |
| US09484137B2 |
Magnet arrays
Method and device for self-regulated flux transfer from a source of magnetic energy into one or more ferromagnetic work pieces, wherein a plurality of magnets, each having at least one N-S pole pair defining a magnetization axis, are disposed in a medium having a first relative permeability, the magnets being arranged in an array in which gaps of predetermined distance are maintained between neighboring magnets in the array and in which the magnetization axes of the magnets are oriented such that immediately neighboring magnets face one another with opposite polarities, such arrangement representing a magnetic tank circuit in which internal flux paths through the medium exist between neighboring magnets and magnetic flux access portals are defined between oppositely polarized pole pieces of such neighboring magnets, and wherein at least one working circuit is created which has a reluctance that is lower than that of the magnetic tank circuit by bringing one or more of the magnetic flux access portals into close vicinity to or contact with a surface of a ferromagnetic body having a second relative permeability that is higher than the first relative permeability, whereby a limit of effective flux transfer from the magnetic tank circuit into the working circuit will be reached when the work piece approaches magnetic saturation and the reluctance of the work circuit substantially equals the reluctance of the tank circuit. |
| US09484133B2 |
Filler assembly for cable gland
A dispenser apparatus for a curable liquid material is disclosed. The apparatus comprises a flexible bag defining a first compartment for accommodating a first component of a curable liquid material, and a second compartment for accommodating a second component of the curable liquid material and adapted to communicate with the first chamber to enable mixing of the first and second components to initiate curing of the curable liquid material. A first clamp temporarily prevents mixing of the first and second components, and an elongate nozzle communicates with the second compartment to dispense the mixed curable liquid material therefrom. A second clamp temporarily prevents passage of the curable liquid material from the second compartment to the nozzle. |
| US09484131B2 |
Method and device for positioning electrical conductors, and conductor group
A method for positioning electrical conductors includes arranging a first flat conductor and a second flat conductor such that the second flat conductor is on top of the first conductor. The arranged conductors create a conductor group. The method also includes providing a wrapping tape. The wrapping tape is configured in such a manner that it is able to engage with itself, but not able to engage with the conductors. The method further includes wrapping the wrapping tape around the conductor group. |
| US09484129B2 |
Manufacturing method of superconducting wire and superconducting wire made thereby
Provided is a method of manufacturing a superconducting wire. A superconducting tape having an outer surface is provided, a copper layer is formed on the outer surface of the superconducting tape, and first metal tape and second metal tape are respectively attached on a first surface and a second surface of the superconducting tape on which the copper layer is formed. |
| US09484126B2 |
Covering material for electric wire, insulated electric wire, and wiring harness
A covering material for electric wire, and an insulated electric wire and a wiring harness including the same, wherein the wire including the covering material has a reduced diameter, is inserted into a connector. The covering material containing a polyvinyl chloride having, with respect to 100 parts by mass of the polyvinyl chloride, 10 to 20 parts by mass of a plasticizer, 1 to 6 parts by mass of a chlorinated polyethylene, and 1 to 6 parts by mass of an MBS resin, and a total amount of the chlorinated polyethylene and the MBS resin is 2 to 7 parts by mass. The wire has an external diameter of smaller than 1.1 mm, and has a conductor 1 and an insulator 2 that covers the conductor 1. The insulator 2 is made of the covering material, and has a thickness of 0.25 mm or smaller. |
| US09484125B2 |
Mica-based strip
The present invention relates to a multilayer strip (1) comprising at least: an essentially mica-based layer (3) and a polymeric layer (2) comprising 60 to 85% by weight of a mineral filler (4) and 15 to 40% by weight of a polymer. |
| US09484120B2 |
Method for annulus spacer detection and repositioning in nuclear reactors
The present invention provides an apparatus for detecting and/or repositioning annulus spacers used to maintain the position of a pressure tube within a calandria tube of a nuclear reactor. The method comprises the steps of: vibrationally isolating a section of the pressure tube; vibrating the wall of said pressure tube within said isolated section; detecting vibration of the wall at a minimum of two axial positions within said isolated sections; and detecting the reduction in vibration level of the wall at one or more of said axial positions in comparison to the remaining axial positions. The apparatus comprises a tool head to be inserted into the pressure tube, the tool head comprising a first end and a second and a clamping block m each of said ends. The clamping blocks are used to vibrationally isolate a section of the pressure tube located between said ends. The apparatus also comprises piezo-actuators operable to vibrate said pressure tube; and accelerometers used for measuring vibration of said pressure tube. |
| US09484117B2 |
Semiconductor memory device having compression test mode
A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable. |
| US09484115B1 |
Power savings via selection of SRAM power source
A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory. |
| US09484114B1 |
Decoding data using bit line defect information
A data storage device includes a memory including a plurality of storage elements configured to store data. The plurality of storage elements includes a first group of storage elements and a second group of storage elements. The data storage device further includes a selection module configured to retrieve first bit line defect information affecting the first group of storage elements and to retrieve second bit line defect information affecting the second group of storage elements. |
| US09484113B2 |
Error-correction coding for hot-swapping semiconductor devices
A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation. |
| US09484110B2 |
Mask-programmed read only memory with enhanced security
A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor. |
| US09484108B2 |
Integrated circuit, semiconductor memory device, and operating method thereof
An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit suitable for supplying a first operating voltage to the internal circuit in response to a first control signal during a general operation, and supplying a second operating voltage that is higher than the first operating voltage to the input/output unit in response to a second control signal during an output of the data. |
| US09484104B2 |
Nonvolatile memory system with block managing unit and method of operating the same
According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of planes and each plane includes a plurality of memory blocks. The memory controller is configured to classify the memory blocks of each of the planes into a plurality of groups. The memory controller is configured to select at least two memory blocks in a corresponding one of the groups, and to control the nonvolatile memory device so that the selected at least two memory blocks are multi-block erased. |
| US09484103B1 |
Electronic storage device
A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed. |
| US09484101B2 |
Methods of programming memories
Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation. |
| US09484100B2 |
Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. |
| US09484097B2 |
Multipage program scheme for flash memory
A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline. |
| US09484096B1 |
Ternary content-addressable memory
A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access memory cell. The first switch is connected between a first search line and a match line. The first switch has a first control electrode. The first static random-access memory cell has a first storage node connected to the first control electrode of the first switch. The second switch is connected between a second search line and the match line. The second switch has a second control node. The second static random-access memory cell has a second storage node connected to the second control electrode of the second switch. |
| US09484092B2 |
Intrinsic vertical bit line architecture
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion. |
| US09484088B2 |
Permutational memory cells
Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the at least one RCM cell. A first portion of the pairs are arranged laterally to one another in a first grouping and a second opposing portion of the pairs are arranged laterally to one another in a second grouping. A memory cell material is disposed between opposing sides of the pairs of the three or more electrical contacts. The memory cell material is configured to form a conductive pathway between one or more of the pairs, with each of the three or more pairs being configured to be accessed individually for at least one operation including program, erase, and read operations. Additional apparatuses and methods are described. |
| US09484086B2 |
Determination of word line to local source line shorts
A number of techniques determine defects in non-volatile memory arrays, which are particularly applicable to 3D NAND memory, such as BiCS type. Word line to word line shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used to determine word line to word line leaks between different blocks. Select gate leak line leakage, for both the word lines and other select lines, is considered, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques determine shorts between bit lines and low voltage circuitry, such as in sense amplifiers. |
| US09484085B1 |
Static memory apparatus and static memory cell thereof
A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period. |
| US09484084B2 |
Pulling devices for driving data lines
A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated. |
| US09484083B2 |
Semiconductor device and semiconductor storage device
A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line. |
| US09484079B2 |
Memory device and memory system including the same
A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information. |
| US09484078B2 |
Providing services from a remote computer system to a user station over a communications network
A method includes receiving the second information at the remote computer system during a second user initiated communication session from the user station automatically, wherein the user station triggers automatically sending the second information to the remote computer system, retrieving the previously stored third information at the remote computer system and matching at least a portion of the received second information with the stored third information. |
| US09484076B1 |
Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit. |
| US09484068B2 |
MTP-thyristor memory cell circuits and methods of operation
An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements. |
| US09484066B2 |
Image display device and control method thereof
The present disclosure relates to an image display device including a display unit for playing video and a control method thereof, and the method may include selecting at least one of characters contained in video, searching at least one region containing the selected character within the entire region of a frame using at least one frame provided in the video, extracting a major playback section containing the selected character based on at least one of the size and location of the retrieved at least one region, and playing the extracted major playback section. |
| US09484056B2 |
Dynamic adjustments of tape head wrap angles
Embodiments of the present invention provide tape drives and methods for operating a tape drive. In one embodiment, tape head wrap angles are dynamically adjusted to increase or decrease contact pressure of magnetic tape on modules of a tape head. Embodiments of the present invention can be used to extend the lifespan of tape drives and components, and enable usage of tape media having increased smoothness and areal density. |
| US09484049B2 |
TMR device with novel free layer
A TMR sensor with a free layer having a FL1/FL2/FL3 configuration is disclosed in which FL1 is FeCo or a FeCo alloy with a thickness between 2 and 15 Angstroms. The FL2 layer is made of CoFeB or a CoFeB alloy having a thickness from 2 to 10 Angstroms. The FL3 layer is from 10 to 100 Angstroms thick and has a negative λ to offset the positive λ from FL1 and FL2 layers and is comprised of CoB or a CoBQ alloy where Q is one of Ni, Mn, Tb, W, Hf, Zr, Nb, and Si. Alternatively, the FL3 layer may be a composite such as CoB/CoFe, (CoB/CoFe)n where n is ≧2 or (CoB/CoFe)m/CoB where m is ≧1. The free layer described herein affords a high TMR ratio above 60% while achieving low values for λ (<5×10−6), RA (1.5 ohm/μm2), and Hc (<6 Oe). |
| US09484046B2 |
Smartphone-based methods and systems
Arrangements involving portable devices (e.g., smartphones and tablet computers) are disclosed. One arrangement enables a content creator to select software with which that creator's content should be rendered—assuring continuity between artistic intention and delivery. Another utilizes a device camera to identify nearby subjects, and take actions based thereon. Others rely on near field chip (RFID) identification of objects, or on identification of audio streams (e.g., music, voice). Some technologies concern improvements to the user interfaces associated with such devices. For example, some arrangements enable discovery of both audio and visual content, without any user requirement to switch modes. Other technologies involve use of these devices in connection with shopping, text entry, and vision-based discovery. Still other improvements are architectural in nature, e.g., relating to evidence-based state machines, and blackboard systems. Yet other technologies concern computational photography. A great variety of other features and arrangements are also detailed. |
| US09484045B2 |
System and method for automatic prediction of speech suitability for statistical modeling
An embodiment according to the invention provides a capability of automatically predicting how favorable a given speech signal is for statistical modeling, which is advantageous in a variety of different contexts. In Multi-Form Segment (MFS) synthesis, for example, an embodiment according to the invention uses prediction capability to provide an automatic acoustic driven template versus model decision maker with an output quality that is high, stable and depends gradually on the system footprint. In speaker selection for a statistical Text-to-Speech synthesis (TTS) system build, as another example context, an embodiment according to the invention enables a fast selection of the most appropriate speaker among several available ones for the full voice dataset recording and preparation, based on a small amount of recorded speech material. |
| US09484044B1 |
Voice enhancement and/or speech features extraction on noisy audio signals using successively refined transforms
Voice enhancement and/or speech features extraction may be performed on noisy audio signals using successively refined transforms. Downsampled versions of an input signal may be obtained, which include a first downsampled signal with a lower sampling rate than a second downsampled signal. Successive transforms may be performed on the input signal to obtain a corresponding sound model of the input signal. The successive transforms performed may include: (1) performing a first transform on the first downsampled signal to yield a first pitch estimate; (2) performing a second transform on the second downsampled signal to yield a second pitch estimate and a first harmonics estimate based on the first pitch estimate; and (3) performing a third transform on the input signal to yield a third pitch estimate and a second harmonics estimate based on the second pitch estimate and the first harmonics estimate. |
| US09484043B1 |
Noise suppressor
Provided is a method, non-transitory computer program product and system for an improved noise suppression technique for speech enhancement. It operates on speech signals from a single source such as either the output from a single microphone or the reconstructed speech signal at the receiving end of a communication application. The system performs background noise monitoring of an in-coming speech signal and determines its level, and performs a time domain gain calculation. The noise suppressed output signal is the gain shaped original speech signal. |
| US09484042B2 |
Speech enhancing method, device for communication earphone and noise reducing communication earphone
The present invention provides a speech enhancing method for communication earphone including two parts: sending end noise reduction processing and receiving end noise reduction processing, wherein the sending end noise reduction processing part includes: determining a wearing condition of the earphone by comparing energy difference of sound signals picked up by microphones of the communication earphone; if the earphone is normally worn, subjecting the sound signal first to multi-microphone noise reduction and then to single channel noise reduction to further suppress residuary stationary noise; otherwise suppressing stationary noise in the sound signal by single channel noise reduction directly. |
| US09484040B2 |
Audio decoding method and associated apparatus
An audio decoding method is provided. In the audio decoding method, a synchronization word and a corresponding packet header are inserted at the beginning of each packet data. A position of the packet data is confirmed according to the synchronization word, and the packet data is then decoded according to information in the packet header. Accordingly, when an error occurs during the decoding process, the decoding process skips to a next packet data for decoding to avoid noise. In addition, a packet header can be directly accessed in the situation of a fast-forward operation to obtain decoding information of the packet data to perform audio decoding. |
| US09484033B2 |
Processing and cross reference of realtime natural language dialog for live annotations
An approach is provided to receive audible speech and convert the received speech to text while the audible speech is being delivered to a user. An annotation candidate is identified in the text and an annotation reference relating to the identified annotation candidate is retrieved and presented to the user. |
| US09484031B2 |
Correcting text with voice processing
The present invention relates to voice processing and provides a method and system for correcting a text. The method comprising: determining a target text unit to be corrected in a text; receiving a reference voice segment input by the user for the target text unit; determining a reference text unit whose pronunciation is similar to a word in the target text unit based on the reference voice segment; and correcting the word in the target text unit in the text by the reference text unit. The present invention enables the user to easily correct errors in the text vocally. |
| US09484028B2 |
Systems and methods for hands-free voice control and voice search
In one embodiment the present invention includes a method comprising receiving an acoustic input signal and processing the acoustic input signal with a plurality of acoustic recognition processes configured to recognize the same target sound. Different acoustic recognition processes start processing different segments of the acoustic input signal at different time points in the acoustic input signal. In one embodiment, initial states in the recognition processes may be configured on each time step. |
| US09484023B2 |
Conversion of non-back-off language models for efficient speech decoding
Techniques for conversion of non-back-off language models for use in speech decoders. For example, a method comprises the following step. A non-back-off language model is converted to a back-off language model. The converted back-off language model is pruned. The converted back-off language model is usable for decoding speech. |
| US09484022B2 |
Training multiple neural networks with different accuracy
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a deep neural network. One of the methods includes generating a plurality of feature vectors that each model a different portion of an audio waveform, generating a first posterior probability vector for a first feature vector using a first neural network, determining whether one of the scores in the first posterior probability vector satisfies a first threshold value, generating a second posterior probability vector for each subsequent feature vector using a second neural network, wherein the second neural network is trained to identify the same key words and key phrases and includes more inner layer nodes than the first neural network, and determining whether one of the scores in the second posterior probability vector satisfies a second threshold value. |
| US09484017B2 |
Speech translation apparatus, speech translation method, and non-transitory computer readable medium thereof
A first speech processing device includes a first speech input unit and a first speech output unit. A second speech processing device includes a second speech input unit and a second speech output unit. In a server therebetween, a speech of a first language sent from the first speech input unit is recognized. The speech recognition result is translated into a second language. The translation result is back translated into the first language. A first speech synthesis signal of the back translation result is sent to the first speech output unit. A second speech synthesis signal of the translation result is sent to the second speech output unit. Duration of the second speech synthesis signal or the first speech synthesis signal is measured. The first speech synthesis signal and the second speech synthesis signal are outputted by synchronizing a start time and an end time thereof, based on the duration. |
| US09484011B2 |
Echo modulation methods and system
Methods and systems for echo modulation are described. In one embodiment, intensities of a plurality of values in multiple windows of an audio signal may be obtained. The windows may be subject to a periodic boundary condition. A plurality of echo values may be calculated for each of the respective windows. The audio signal may be altered in one or more of the windows using a windowing function and echo values. Additional methods and systems are disclosed. |
| US09484009B2 |
Microphone stand base
According to some embodiments a microphone stand base is provided. The microphone stand base may comprise a backer to couple a post and a bottom plate extending from the backer. The backer is coupled to the bottom plate such that the backer is flush with a plurality of edges of the bottom plate. |
| US09484006B2 |
Manipulation of textual content data for layered presentation
A method for creating visual content to be output in a layered manner, wherein content items are received, and are categorized into at least two categories. At least one of the categories includes at least one image content item and at least one other category includes at least one textual content item. The content items in each of the categories are manipulated, wherein the textual content data is manipulated with at least one operation applicable for textual content and the manipulation produces at least one data file including textual content data for the text layer to be prepared for outputting in a client device. Finally, data files including manipulated image content data and the manipulated textual content data are stored. A system, a computer program product, a method in the client device and the client device are also described. |
| US09484003B2 |
Content bound graphic
A method can include accessing content stored in a data store where the content includes a bound and content adjacent to the bound; rendering a portion of the content to a display; receiving a scroll command that calls for rendering the content adjacent to the bound; and, responsive to receipt of the scroll command, rendering a bound graphic. Various other apparatuses, systems, methods, etc., are also disclosed. |
| US09483997B2 |
Proximity detection of candidate companion display device in same room as primary display using infrared signaling
A candidate companion screen device is located by a primary display device as being in the same room as the primary device using IRDA, and in response ancillary content related to content being shown on the primary display device is provided to the companion screen device. The ancillary content may be provided from the Internet based on information in the content being presented on the primary display device by, e.g., providing a link to a website to the companion device. |
| US09483995B2 |
Display device, method for driving the same, and electronic device
A display device including a display unit including first and second lines, light emitting elements and pixel circuits; a first drive unit sequentially applying a selection pulse to the first lines; and a second drive unit applying a signal pulse including first to third voltages to each of the second lines. Each of the pixel circuits includes a first transistor sampling the signal pulse, and a second transistor driving one of the light emitting elements. The first drive unit applies the selection pulse when the first voltage is being applied by the second drive unit, before a correction of a threshold voltage of the second transistor is initiated and within a period that the one of the light emitting elements is being turned out, and the first drive unit applies the selection pulse when the second voltage is being applied by the second drive unit. |
| US09483985B2 |
Field-sequential-color liquid crystal device and the driving method thereof
A driving method of the FSC-LCD is disclosed. The method includes: calculating grayscale values of four pixels of each images, the grayscale values of four pixels comprises grayscale values for a white pixel, for a first color pixel, for a second color pixel, and for a third color pixel; within a first color field of the n-th image, a white backlight source is provided to the pixel cells, the grayscale value for the white pixel of the n-th image is inputted to the transparent subpixel, the grayscale value for the first color pixel of the n-th image is inputted to the first color subpixel, and the grayscale value for the second color pixel of the n-th image is inputted to the second color subpixel; within a second color field of the n-th image, a third-color backlight source is provided to the pixel cells, the grayscale value for the third color pixel of the n-th image is inputted to the transparent subpixel, a grayscale value is inputted to the first color subpixel and the second color subpixel such that the first color subpixel and the second color subpixel remain in a turn-on state. In addition, FSC-LCD driven by the above driving method is also disclosed. |
| US09483983B2 |
Display device, in particular for cooktops
A display device in particular for cooktops is provide that has a glass ceramic with a front side and a back side and a lamp arranged in the area of the back side. The display device further includes an optical compensation filter arranged between the front side and the lamp so as to implement any color impressions easily and inexpensively and in a preselectable manner. |
| US09483981B2 |
Dynamic display adjustment
Devices such as electronic book readers, televisions, and so forth use displays to present information to users. Described herein are devices and methods for dynamically adjusting illumination, waveforms used to generate the image, presentation of the information, or a combination thereof based on one or more of ambient light level, display illumination level, and so forth. |
| US09483978B2 |
Display device and method of driving the same
A display device includes a display unit having display elements arrayed in rows and columns. The display elements each include a current-driven light emitting unit and a drive circuit for driving the light emitting unit. A power supply unit supplies a drive voltage for driving the display elements to power supply lines corresponding to the rows of display elements. A signal output unit supplies video signal voltages to data lines corresponding to the columns of the display elements. A control unit detects maximum grayscale values of input signals corresponding to the display elements arranged in the rows, and accordingly controls duty ratios of the drive voltage supplied to the power supply lines corresponding to the rows of the display elements. The control unit also controls values of video signals corresponding to the display elements in each row. |
| US09483970B2 |
Method, system, and device for selecting and displaying information on a mobile digital display device
A method, system, and device for selecting and displaying information on a mobile digital display device includes determining preference criteria for local viewers of the mobile digital information display device, selecting digital information to be displayed on the mobile digital information display device as a function of the preference criteria, and displaying the selected information on a display of the mobile digital information device. |
| US09483969B2 |
Liquid crystal panel, and testing circuit and testing method thereof
A liquid crystal panel, the testing circuit and the testing method thereof are disclosed. The testing circuit includes shorting bars, bonding pads, and switches. The switches are arranged between the shorting bars and the bonding pads. In the testing process, the switches are turn on upon receiving the testing signals so as to transmit the testing signals from the shorting bars to the bonding pads. When the testing process ends, the switches are turn off to prevent the liquid crystal panel from being affected by the signals of the bonding pads during the normal screen display of the liquid crystal panel. In this way, the manufacturing cost is reduced. |
| US09483964B2 |
Display apparatus
A display apparatus includes a display panel which receives a light to display an image, a backlight unit which provides the light to the display panel, and a first protection member accommodating the backlight unit therein. The first protection member includes a bottom part, an inclined part connected to an edge of the bottom part and bent upward at a predetermined angle with respect to the bottom part, a connection part connected to an edge of the inclined part, and a first sidewall part connected to an edge of the connection part and extending upward. The display panel, the backlight unit, the bottom part and the connection part have a curved surface shape in a first direction and have a flat shape in a second direction substantially perpendicular to the first direction. |
| US09483958B1 |
Magnetic writing board chore chart
An Improved chore chart assembly consisting of a writable, erasable and rewritable surface capable of removably securing labels to display lists of tasks and chores and a method for creating and displaying lists and tasks. The chore chart assembly further consisting of a drawer capable of holding the labels which are capable of being removably affixed. |
| US09483957B1 |
Methods, systems, and computer readable media for promoting behavioral intervention via evidence-based recommendations and game mechanics
The subject matter described herein includes methods, systems, and computer readable media for promoting behavioral intervention via evidence-based recommendations and game mechanics. According to one aspect, a method for promoting behavioral intervention via evidence-based recommendations is provided. The method occurs at a computing platform including a processor and memory. The method includes receiving information regarding characteristics and/or activities of a user, wherein the user is associated with a medical condition or an age group. The method further includes determining, using the received information and predetermined health information associated with the medical condition or the age group, an action for promoting behavioral intervention. The method also includes providing the action or information associated with the action to the user. |
| US09483947B2 |
Passing assistance system and method
A passing assistance system and method is provided for one's vehicle having an electronic control device for at least receiving messages from car-to-car communication systems of other vehicles. The messages include information about the presence or absence of a vehicle that trails the vehicle transmitting the message. The control device evaluates these messages as follows: the control device has a filter for identifying the first oncoming vehicle and its message and activates a warning system in the ego-vehicle to prevent a passing process if this message includes the information about the presence of a trailing vehicle. |
| US09483942B2 |
Transportation location and alert application for mobile device
An application program interface (API) for communicating with a transportation integration network is provided wherein an application can utilize the API to retrieve, store, and otherwise access or modify transportation location tracking data from disparate data stores and then display the data in a single API, website or computer software program. |
| US09483941B1 |
Communicating an alert notification to a particular vehicle
Communicating a notification to a particular vehicle is provided. A processor: identifies, one or more vehicles within a particular radius to a first vehicle based on one of: WiFi network visibility, a geo-fenced radius with known geo-tags of the one or more vehicles, or scanning for visible Bluetooth devices; receives a selection for a particular vehicle of the one or more vehicles identified based on descriptive wireless tags or line-of-sight selection from a first device in the first vehicle; establishes a connection between the first device in the first vehicle and a second device in the particular vehicle; receives a selection for a predetermined message; receives an image of a problem associated with the particular vehicle; and sends the predetermined message and the image from the first device to the second device. |
| US09483938B1 |
Diagnostic system, method, and recording medium for signalized transportation networks
A diagnosis system for an adaptive signal control system in a network, the diagnosis system including a traffic state identification device configured to estimate a traffic state describing a supply-demand mismatch by identifying a relationship between real time data feed from a sensor and a control strategy of said adaptive signal control system and a network transition model device configured to diagnose the supply-demand mismatch and an evolution of the supply-demand mismatch on a network level based on said relationship and infrastructure data of the network. |
| US09483935B2 |
Channel-switching remote controlled barrier opening system
An improved barrier door one way wireless communication system for operating a barrier, such as a garage door, includes the transmission and reception of multibit code hopping data packets in combination with automatic RF channel switching. Packet data is transmitted automatically on more than one RF channels in a switching style while sending two or more redundant multibit code hopping data packets on each of the RF channels. The system also provides for the learning of a transmitter to a receiver where two or more code hopping data packets must be received and decoded by the receiver on all RF channels before a transmitter can be learned to a receiver. Once the transmitter is learned, actuation of the transmitter during a learn mode can open a window for learning of a single channel transmitter. |
| US09483934B2 |
Presence based system and method for controlling devices
System and method for presence based control of connected devices including a smart device configured to operate at least one connected device, and a locator configured to supervise an entrance of a subarea of a monitored area, wherein the smart device and the locator are configured to exchange radio frequency (RF) signals and to determine the presence of the smart device within the subarea based on received RF signals, and wherein the smart device to issue control commands to operate the at least one connected device based on a predefined scheme and on the presence of the smart device within the subarea. |
| US09483932B2 |
Systems and methods for a safety status indicator system
The present invention provides systems and methods for tracking a safety status of a number of individuals, and providing pro-active security and response based on historical safety data collected by the system, as well as third-party information such as crime, traffic, weather, and news data. |
| US09483928B2 |
Input/output circuits and devices having physically corresponding status indicators
Systems and methods are provided for aligning status indicators on a terminal block of an I/O device by locating the status indicators directly adjacent to or integrated directly within their respective terminals on the terminal block. The status indicators are illuminated by LEDs or other light emitters disposed within a housing of the I/O device. Light from the LEDs are directed to the status indicators by light pipes disposed within the housing of the I/O device. LED activation circuitry disposed within the housing determines a manner in which to activate the LEDs to illuminate the status indicators based on inputs and outputs between the I/O device and a controlled process. In certain embodiments, the status indicators are disposed on a raised section of the I/O device, which may be part of a removable LED indication assembly including the LEDs, light pipes, and LED activation circuitry. |
| US09483926B2 |
Monitoring inmate movement with RFID
The disclosure relates to systems and methods for tracking offender movement with RFID. Such a system can include a transponder associated with an offender and a radar module configured to determine a direction of a moving object passing within range of the radar module. The system can include a radio frequency identification reader situated near the radar module and configured to transmit an interrogating signal to the transponder and receive an identifying signal in response to the transponder receiving the interrogating signal. The system can include a server configured to receive data from the radio frequency identification reader and the radar module through a network, transmit the received data to a web service through the network, and receive an alert from the web service that a monitoring rule of a plurality of monitoring rules associated with the offender was violated. |
| US09483924B2 |
Smoke detector with airflow barrier
A smoke detector system that includes an airflow barrier installed between a detector base unit and a mounting surface to ensure there is separation between the detector base unit and the mounting surface. The barrier isolates and seals the smoke detector to prevent the formation of condensation in or around the smoke detector. The barrier further includes a cavity that can collect condensation if condensation does occur. The condensation is then directed to a channel that extends around the periphery of the airflow barrier. Additionally, the channel includes weep holes so that condensation has a means to exit the detector. |
| US09483921B2 |
Integrated visual notification system in an accessory device
The described embodiments relate generally to an accessory device for a tablet device. The accessory device takes the form of a flexible screen protector that can be disposed over a display portion of the tablet device. Because the flexible screen protector covers the display of the tablet there is no visual way for the tablet to provide notifications to the user while the screen protector overlays it. By providing a data and power connection between the tablet and the accessory device, the processor of the tablet device can command illumination elements disposed in the accessory device to be illuminated in any of a number of illumination states. Each of the illumination states can be associated with an operating state of the tablet device thereby allowing the tablet device to visually communicate operating state information while the display is covered. |
| US09483918B2 |
Personal illumination device with variable lighting patterns
A personal illumination device is described and taught. The personal illumination device is intended for use by motorcyclists, however, it may be used by any number of individuals looking to increase their visibility in environments where high visibility and safety is paramount. The illumination device has two illuminated strips that sit across the front and back of a user. The strips have LEDs positioned across capable of creating various illuminate patterns. Additionally, a user can choose to have either the front, back, or both strips illuminated at the same time. The personal illumination device further has straps that provide for adjustments to create a custom fit, as well as enhancement strips placed on the straps to further increase one's visibility. |
| US09483916B2 |
Gaming system, gaming device and gaming method providing stacking symbols and convertible reels
The gaming system, gaming device and method provides a reel game that includes stacks of symbols configured on the reels to provide a large number of winning symbol combinations. The gaming device includes a plurality of reels wherein each reel includes a reel-strip and a plurality of symbols. Each of the plurality of reels is configured to include one or more stacks of symbols wherein a stack of symbols is formed by placing a plurality of identical symbols adjacent to each other on a single reel. If two non-adjacent reels each generated a stack of identical symbols and at least one reel positioned between the two non-adjacent reels generated symbols different from the symbols used to form the stack of identical symbols, at least one symbol on the at least one reel positioned between the two non-adjacent reels is modified into the symbol that forms the stacks of identical symbols. |
| US09483915B2 |
Methods and systems for electronic gaming
Methods and apparatuses for administering game play include displaying an electronic reel simulation including a multiple reel array for a wagering game on a display. A user input indicates a selected play option from a plurality of play options. All play options enable all displayed positions of the multiple reel array to be considered in winning outcomes. A game outcome is determined and presented as game symbols on the display. Winning combinations of the game symbols are determined, wherein each winning combination includes three or more matching game symbols appearing in the displayed positions on each of three or more adjacent reels and at least one of the three or more matching game symbols is not used in another winning combination. A payout is determined and multiplied by a multiple correlated to the selected play option when a substitute multiplier symbol appears as one of the game symbols. |
| US09483894B2 |
Bezel assembly for use with an automated transaction device
The bezel assembly for data reception, for use with a bill validator in a financial transactional device, includes a bezel housing and a data reception assembly. The bezel housing includes a customer-facing front portion and a back plate connectable to the bill validator that is mounted within the transactional device cabinet. The front portion includes an insertion/dispensing slot for receiving currency and a projecting protrusion forward of the casing. The forward-extending protrusion accommodates at least a portion of the data reception assembly. The bezel assembly can include a wireless communication function that is communicably connectable with a mobile device via a wireless communication method, a manual entry function, a biometric reader, one or more cameras for scanning and decrypting 2D barcodes and the like, thus enhancing the overall functionality of the financial transactional device. |
| US09483893B2 |
Securable banknote carrier, and a banknote handling apparatus and banknote cassette for use with the securable banknote carrier
A securable banknote carrier comprising an enclosure of flexible material attached to an articulated bi-fold frame delimiting a banknote aperture, wherein the frame comprises a pair of hingedly coupled opposing jaw members, and wherein the frame is configured such that when moving from a banknote aperture open position to a banknote aperture closed position the opposing jaw members rotate inwardly towards one another from a position in which the jaw members are substantially coplanar to a position m which the members are substantial adjacent and parallel to each other. |
| US09483891B1 |
Wireless lock
A network lock system and a method for operating the network lock system. The network lock system includes: a lock mechanism for locking a first lock part to a second lock part together and for releasing the first lock part locked to the second lock part on application of a power signal to the lock mechanism; a wireless signal receiver for receiving a wireless signal from a network device; and a power converter for converting the wireless signal into the power signal for application to the lock mechanism. |
| US09483889B2 |
Method for controlling an electronically secured device and transponder for it
A method for controlling an electronically secured device by means of a transponder has the following procedural steps: a) Access authorization information is sent from an electrical access management system to the transponder via a mobile communications link, b) The access authorization information is received by the transponder, c) The access authorization information is transmitted from the transponder to the device, and d) A function of the device is activated if the received access authorization information matches reference information belonging to the device. |
| US09483888B2 |
Reusable electronic seal
A container including a reusable electronic seal, as well as a system and method for using the electronic seal are described. The container includes a closure member configured to detachably affix to a portion of the container, thereby sealing the container. In response to the closure member sealing the container, a signal generating component generates an electronic signal and transmits the electronic signal to a processing circuit operably connected to the signal generating component. The processing circuit includes a processing device configured to generate a unique code when the closure member is manipulated to open or close the container and an output device operably connected to the processing device and configured to output the unique code. The unique code is updated each time the container is opened, thereby providing a recipient with a way to determine whether the container has been opened during delivery. |
| US09483885B2 |
Method for detecting a failure of at least one sensor onboard an aircraft implementing wind detection, and associated system
A method for detecting a failure of at least one sensor onboard an aircraft implementing wind detection is provided. The method includes measuring an airspeed of the aircraft; measuring a geographical speed of the aircraft; determining an instantaneous wind vector, based on the measured airspeed and geographical speed; establishing an instantaneous wind variation vector, based on the determined instantaneous wind vector; projecting the instantaneous wind variation vector on the direction of the vector of an air or geographical speed of the aircraft; and determining the presence of a failure based on the obtained projection. |
| US09483881B2 |
System and method for testing vehicle emissions and engine controls using a self-service on-board diagnostics kiosk
A system and method for testing vehicle emissions and engine control components using a standalone self-service kiosk. The self-service kiosk includes a computer capable of gathering Vehicle Information (VIN) and OBD information from a vehicle being tested using a barcode reader and an OBD reader, respectively. The self-service kiosk generates a readable display or printed report to the user indicating any detected diagnostic trouble codes found during the vehicle emissions testing. By networking a plurality of self-service kiosks together in a secure network and accessible through the Internet, the self-service kiosk network maintains a centrally located vehicle information database for storing and retrieving pertinent vehicle-related information during vehicle emissions testing. If the vehicle being tested passes the vehicle emissions testing, then the self-service kiosk prints out a registration renewal sticker, registration renewal document and/or receipt for the user. |
| US09483876B2 |
Augmentation of elements in a data content
A computing device can augment video content by receiving video content from an image capturing device and detecting and tracking a self-propelled device in the video content. The computing device can display a plurality of augmented reality elements selectable to augment the self-propelled device and receive a user selection of one of the plurality of augmented reality elements to augment the self-propelled device. The computing device may then augment the self-propelled device in the video content by superimposing the selected augmented reality element over the self-propelled device as the self-propelled device moves. |
| US09483874B2 |
Displaying panoramic images in relation to maps
An example non-limiting game apparatus as an information processing apparatus includes a CPU which causes the game apparatus to function as a guide apparatus. A map image of a place or area to be guided is displayed on a lower LCD. When a predetermined position on the map image is designated, a photograph image of a part of a panoramic image produced from a panoramic photograph taken at a real position in a real space that corresponds to the predetermined position is displayed on a stereoscopic LCD. Therefore, not only a planar map image but also an actual photograph at the predetermined position are presented. Furthermore, if the map image is turned, the photograph image of a part of the panoramic image is changed such that the photograph image corresponds to a turned direction. |
| US09483873B2 |
Easy selection threshold
A method, system, and computer readable storage medium/computer program product provide the ability to select an object in a three-dimensional (3D) scene. A 3D scene is displayed and consists of a first object that is displayed in the foreground and a second object that is occluded or partially occluded by the first object. An object selection option is activated. A transparency threshold value is defined for the first object. A location in the displayed 3D scene is selected. Such a location is located on a portion of the first object that occludes the second object. Based on the transparency threshold value and the location, either the first object or the second object is selected and displayed in a visually distinguishable manner. |
| US09483872B2 |
Graphical representation of roads and routes using hardware tessellation
A technical solution is provided for graphical representation of road segments by employing hardware tessellation, wherein cartographic data that describe at least one two-dimensional or three-dimensional road contour of the road segment are assigned to each road segment. One method aspect comprises the steps of piecewise partitioning the parametrization of the road segment into mutually independent curve segments, of providing at least one tessellation factor for each curve segment, the at least one tessellation factor specifying into how many subsegments each curve segment is to be subdivided in the direction of the road contour, of generating a tessellation pattern for each curve segment based on the at least one tessellation factor, and of generating primitives, capable of being represented on a screen, on the basis of the generated tessellation pattern and on the basis of the parametrized road contour. |
| US09483866B2 |
User interface for efficiently displaying relevant OCT imaging data
The present invention is an OCT imaging system user interface for efficiently providing relevant image displays to the user. These displays are used during image acquisition to align patients and verify acquisition image quality. During image analysis, these displays indicate positional relationships between displayed data images, automatically display suspicious analysis, automatically display diagnostic data, simultaneously display similar data from multiple visits, improve access to archived data, and provide other improvements for efficient data presentation of relevant information. |
| US09483864B2 |
System and method for photorealistic imaging using ambient occlusion
Scene model data, including a scene geometry model and a plurality of pixel data describing objects arranged in a scene, is received. A primary pixel color and a primary ray are generated based on a selected first pixel data. If the primary ray intersects an object in the scene, an intersection point is determined. A surface normal is determined based on the object intersected and the intersection point. The primary pixel color is modified based on a primary hit color, determined based on the intersection point. A plurality of ambient occlusion (AO) rays each having a direction, D, are generated based on the intersection point, P and the surface normal. Each AO ray direction is reversed and the AO ray origin is set to a point outside the scene. An AO ray that does not intersect an object before reaching the intersection point is included in ambient occlusion calculations. The primary pixel color is shaded based on the ambient occlusion and the primary hit color and an image is generated based on the primary pixel color for the pixel data. |
| US09483862B2 |
GPU-accelerated path rendering
A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer. |
| US09483851B2 |
Systems and methods for filtering for image generation
A method is provided including acquiring imaging data of an object to be imaged from a computed tomography (CT) detector. The method also includes reconstructing the acquired imaging data into an initial reconstruction image, and performing material characterization of an image volume of the initial reconstruction image to provide a re-mapped image volume. Further, the method includes performing forward projection on the re-mapped image volume to provide forward projection data, and providing an error projection based on the forward projection data. Also, the method includes filtering at least one of the initial reconstruction image, the re-mapped image volume, the forward projection data, or the error projection. The method also includes using the error projection to update the initial reconstruction image to provide an updated reconstruction image. |
| US09483850B2 |
Cylinder source software-positioning method for PET calibration and image quality assurance
A method and system for determining a position of a source including obtaining prompt data and related delayed data from a Positron Emission Tomography (PET) scanner, generating a sinogram from the prompt data, generating crystal efficiency correction factors by performing a normalization calibration based on the obtained delayed data, performing normalization correction on the generated sinogram based on the crystal efficiency correction factors to generate a corrected sinogram, rebinning the corrected sinogram to generate a plurality of two-dimensional sinogram slices, and determining a central axis for each of the plurality of two-dimensional sinogram slices using a center estimation process. |
| US09483849B2 |
Method and apparatus for controlling camera for color calibration of multi-displays
A method for controlling a camera for color calibration of multi-displays including: acquiring a first image of data displayed on the multi-displays by photographing the multi-displays with the camera; analyzing color of the data displayed on at least one individual display from among the multi-displays using the acquired first image; determining image capture settings suitable for the color calibration of the multi-displays, based on a result of the analyzing; adjusting the image capture settings of the camera in accordance with the determined image capture settings; acquiring a second image of the data displayed on the multi-displays by photographing the multi-displays with the camera using the adjusted image capture settings of the camera; and performing color calibration of the multi-displays based on the second image. |
| US09483848B2 |
Image processing apparatus having a plurality of image processing blocks that are capable of real-time processing of an image signal
An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. |
| US09483845B2 |
Extending prediction modes and performance of video codecs
A video frame compression system includes a rendering engine that provides a current video frame and current additional rendering information. Additionally, the video frame compression system includes a warping engine that generates a warped video frame, wherein the warped video frame is a transformation of a previous video frame that is based on the current additional rendering information. Further, the video frame compression system includes a video encoder that compresses the current video frame by using the warped video frame as a reference frame and separately compresses the current additional rendering information. Still further, the video frame compression system includes a packetizer that provides main and auxiliary data streams corresponding to the compressed current video frame and the compressed current additional rendering information, respectively. A video frame decompression system and methods of video frame compression and decompression are also provided. |
| US09483843B2 |
Method and system for expediting bilinear filtering
The present document describes a method and system for expediting bilinear filtering of textures, by reducing the number of data load operations. The method expands the original data layout with additional borders containing replicated texels. The replicated texels correspond either to wrapped-around texels for two-dimensional textures or neighboring faces in cube textures. Therefore, a 2×2 filter kernel for bilinear filtering is built which requires only one texel address to be computed, with all texel data readable with two load operations which are a predetermined stride apart. Different addressing modes are implemented by adjusting the sampling locus. |
| US09483836B2 |
Method and apparatus for real-time conversion of 2-dimensional content to 3-dimensional content
Various aspects of a method and apparatus for video processing may include a computing device communicably coupled to an external device. The computing device may be operable to determine an average vertical velocity and an average horizontal velocity of a subset of pixels in an image frame and determine a depth value for each pixel of the subset of pixels based on calculated motion vectors of the pixel of the subset of pixels, the average vertical velocity of the subset of pixels and the average horizontal velocity of the subset of pixels. |
| US09483830B2 |
Depth map generation method, related system and computer program product
A depth map is generated from at least a first and a second image. A plurality of reference pixels are selected in the first image. A cost function is used to associate each reference pixel with a respective pixel in the second image. A masking operation is used to identify a subset of pixels in a block of pixels surrounding a reference pixel and the cost function is based on the identified subset of pixels. A disparity between each reference pixel and the respective pixel in said second image is determined, and a depth value is determined for each reference pixel as a function of the respective disparity. A depth map is generated based on the determined depth values. |
| US09483829B2 |
Efficient visual surface finding
A structure for determining a plane in a depth image includes dividing a portion of a depth image into a plurality of areas, fitting a two-dimensional line to depth points in each of the plurality of areas, and combining two or more of the plurality of two-dimensional lines to form a three-dimensional plane estimate. |
| US09483828B2 |
System for recognizing vehicle identification number
A system for recognizing a vehicle identification number includes a three dimensional scanner configured to scan, in a direction in which the vehicle identification number is engraved, a vehicle identification number engraved in a vehicle body to obtain an image. The system further includes an image processor configured to convert the image obtained by the three dimensional scanner into a gray image, divide the gray image according to a gray scale to extract a symbol in the image corresponding to a symbol engraved in the vehicle body, and compare the symbol with standard symbols to determine the vehicle identification number. |
| US09483822B2 |
Co-occurrence of local anisotropic gradient orientations
Methods, apparatus, and other embodiments associated with distinguishing disease phenotypes using co-occurrence of local anisotropic gradient orientations (CoLIAGe) are described. One example apparatus includes a set of logics that acquires a radiologic image (e.g., MRI image) of a region of tissue demonstrating disease pathology (e.g., cancer), computes a gradient orientation for a pixel in the MRI image, computes a significant orientation for the pixel based on the gradient orientation, constructs a feature vector that captures a discretized entropy distribution for the image based on the significant orientation, and classifies the phenotype of the disease pathology based on the feature vector. Embodiments of example apparatus may generate and display a heatmap of entropy values for the image. Example methods and apparatus may operate substantially in real-time. Example methods and apparatus may operate in two or three dimensions. |
| US09483821B2 |
Method and ultrasound apparatus for displaying ultrasound image corresponding to region of interest
Provided is an ultrasound image display method. The ultrasound image display method includes displaying an ultrasound image of an object, selecting at least one region of interest (ROI) in the ultrasound image based on a user input, converting image pixel information corresponding to the at least one ROI into height values, and three-dimensionally displaying a partial ultrasound image corresponding to the at least one ROI by using the height values. |
| US09483819B2 |
Contour-based array inspection of patterned defects
One embodiment relates to a method of inspecting an array of cells on a substrate. A reference image is generated using a cell image that was previously determined to be defect free. A reference contour image which includes contours of the reference image is also generated. The reference contour image is used to detect defects in the array of cells on the substrate. Another embodiment relates to a system for detecting defects in an array on a substrate. Other embodiments, aspects and features are also disclosed. |
| US09483816B2 |
Method and system for high accuracy and reliability registration of multi modal imagery
A method for mapping a target image to a reference image includes receiving a target image; receiving a reference image that overlaps the target image; preprocessing the target image, wherein the preprocessing includes: rejecting a target image with a shadow region above a shadow threshold while keeping a target image with a shadow region below a shadow threshold; providing an uncertainty in a location of the kept target image relative to the reference image; transforming the kept target image to an atlas projection to match the reference image; partitioning the transformed kept target image into a sub-region; and determining a matching statistic for each sub-region to determine a location for each sub-region relative to the reference image. |
| US09483815B2 |
Systems and methods for computational lighting
A device for creating a digital image is described. The device that may receive two or more input images. The input images may have a common viewpoint with unique lighting configurations. The device may utilize basis light functions and modifiers to create a final composite image. The device may include a computing device configured to provide user a graphical user interface enabling a user to create a final composite image. Devices described herein may be useful for computational light workflows in photography. |
| US09483814B1 |
Methods and apparatus for the filtering of spatial frequencies
A single still input image is converted into a decomposition video that, when played, appears to be a close facsimile of the input image. Each frame of the decomposition video has a subset of the pixels of the input image that is disjoint from the subset of pixels selected for any other frame. A union of the subsets, represented by each decomposition video frame, contains all the pixels of the input image. To preserve sufficient brightness, a decomposition video generally needs to contain a relatively small number of frames. To achieve effective and efficient blocking, of the content of the input image as it appears in each frame of a decomposition video, the present invention focuses upon a spatial filtering strategy and, preferably, a two-tiered strategy. A first tier focuses upon the obscuring of relatively high frequency spatial frequencies, while a second tier focuses upon the obscuring of relatively low frequency spatial frequencies. |
| US09483812B2 |
Enhancing motion pictures with accurate motion information
Methods and systems for digitally enhancing the characteristics of an image sequence including video and motion picture images are provided. Highly accurate motion information represented by trajectories are generated through analyzing available image frames in the image sequence. Some embodiments of the present invention relate to generating multiple layer trajectories from an image sequence. Certain aspects may be applicable to the enhancement of three-dimensional (3D) image sequences including 3D video and 3D motion pictures. |
| US09483811B2 |
Division of processing between systems based on external factors
A method includes acts for rendering, on a data processing system, a result derived from a set of data by performing data processing across a first data processing system and a second data processing system. The amount of processing performed by the second data processing system can be dynamically adjusted depending on factors affecting the second data processing system. The first data processing system receives information defining how the result will be rendered at the second data processing system. The first data processing system receives information indicating factors affecting the second data processing system. The first data processing system dynamically allocates the needed data processing between the first data processing system and the second data processing system, based on factors affecting the second data processing system. |
| US09483810B2 |
Reducing the number of IO requests to memory when executing a program that iteratively processes contiguous data
Methods and apparatuses to reduce the number of IO requests to memory when executing a program that iteratively processes contiguous data are provided. A first set of data elements may be loaded in a first register and a second set of data elements may be loaded in a second register. The first set of data elements and the second set of data elements can be used during the execution of a program to iteratively process the data elements. For each of a plurality of iterations, a corresponding set of data elements to be used during the execution of an operation for the iteration may be selected from the first set of data elements stored in the first register and the second set of data elements stored in the second register. In this way, the same data elements are not re-loaded from memory during each iteration. |
| US09483809B2 |
Method and system for identifying content
Disclosed is a method for identifying content, preferably media content for publishing including the steps of a) Providing a content element for a user, b) Marking the content element with a global mark, c) Marking the content element with a local mark, d) Presenting the marked content element, e) Detecting at least part of the presented content element, f) Extracting the global mark and the local mark from the detected part of the content element, g) Identifying the extracted local mark and the global mark, and h) Identifying the content element based on the global and local mark. The invention relates also to a corresponding system and a use of the method and the system. |
| US09483805B1 |
Limited tokens in online education
A method of limiting tokens for use by a student within an education application displays numerous membership options. For a price, a certain number of tokens are allowed per month. At the end of each month, tokens do not roll over; the account is reset with the monthly allotment of tokens. If the number of tokens in the account reaches zero, access is blocked. A method limits account sharing by using a limited time viewing window for videos and documents. A stated time limit displayed to the student is greater than the length of the video. An actual time limit not displayed to the student is greater than the stated time limit. Requests to restart the video within the actual time limit are granted. A request to restart the video after the actual time limit is denied unless the student again pays the number of tokens equal to the value of the video. |
| US09483803B2 |
Search intent for queries on online social networks
In one embodiment, a method includes receiving, from a client system of a first user, a structured query comprising references to one or more selected objects accessible by the computing device, generating one or more search results corresponding to the structured query, wherein each search result corresponds to a particular object accessible by the computing device, determining one or more search intents based at least on whether one or more of the selected objects referenced in the structured query match objects corresponding to a search intent indexed in a pattern-detection model, and scoring the search results based on one or more of the search intents. |
| US09483799B2 |
Methods and apparatus for the aggregation of data
Embodiments include a method of aggregating data from a plurality of QuickBooks (QB) files that may be in physically separate locations, and having at least one account name in common. In one embodiment, the method includes, assigning a different parent account identification (ID) number to each differently named parent account. The method includes creating an entry in a hash table for each parent account ID, the contents of the entry being a collection of rows including a row for each different sub account of the parent account, wherein data for multiple instances of like named parent accounts are aggregated, the key of the entry in the hash table being the parent account ID. |
| US09483797B1 |
Method and system for recording a transaction using a dynamic user interface within an application
A method for recording a transaction using a Dynamic User Interface (DUI) within an application, including receiving, from a user of the application, the transaction relating to a customer of the user; receiving a request to generate a form for the transaction; generating, based on the request to generate the form, the form containing a customer list and a form element; receiving a request to generate the DUI; generating, based on the request to generate the DUI, the DUI adjacent to the form displayed within the application; receiving an identification of the customer from the customer list; populating, based on the identification of the customer, the DUI with the transaction relating to the customer; receiving, from the user, a selection of the transaction from the DUI; populating, within the form adjacent to the DUI, the form element using the transaction; and recording, within the application, the transaction. |
| US09483796B1 |
Surveillance and positioning system
A position determining system includes a surveillance and monitoring special purpose computer, one or more sensors in electrical communication with the surveillance and monitoring special purpose computer, one or more surveillance cameras in electrical communication with the surveillance and monitoring special purpose computer, the surveillance and monitoring special purpose computer receiving from the one or more sensors positional data about an asset and assembling and forwarding instructions to the one or more surveillance cameras in electrical communication with the surveillance and monitoring special purpose computer, the instructions requesting specific surveillance to be undertaken by the one or more surveillance cameras; and a processor in electrical communication with the surveillance and monitoring special purpose computer that determines if additional data is required about the asset and when additional data is required, assembling and forwarding instructions regarding an action. |
| US09483794B2 |
Systems and methods for identification document processing and business workflow integration
A method includes: capturing or receiving at least one image of one or more identity documents (IDs) using a mobile device; determining identifying information from one or more of the IDs; building an ID profile based on the identifying information; storing the ID profile to a memory of the mobile device; invoking a workflow configured to facilitate a business transaction; detecting a predetermined stimulus in the workflow, the stimulus relating to the business transaction; providing at least a portion of the ID profile to the workflow in response to detecting the predetermined stimulus; and driving at least a portion of the workflow using the provided portion of the ID profile. Related systems and computer program products are also disclosed. |
| US09483792B2 |
Screen-based method and system for sizing an oral appliance
An oral appliance is sized by obtaining a scaled image of a patient's dental arch. Dimensions of the arch are marked on a screen image, and the processor chooses an oral appliance having a best fit for a particular patient. |
| US09483790B2 |
Systems and methods for providing goods
A robobox may automate all of the functions of a retail store, combining the best of online and traditional retail in a platform that costs significantly less to operate than a brick and mortar store while providing greater availability, a more predictable experience, and instant gratification to the shopper. Customers may use a touch screen interface to choose products from an inventory of the robobox. They may also place orders in advance through the web or with mobile devices. As soon as an order is completed and the payment has been collected electronically, the inner workings of the robobox pick the items in the order and may deliver it to the customer on-site. |
| US09483786B2 |
Gift card ordering system and method
A personalized gift card creation system and method includes providing an application to be executed on a computing device in which the application includes a peripheral application program interface (API) for interfacing with one or more peripheral devices of the computing device. A server in communication with the application generates a graphical user interface (GUI) on the computing device using the application, receives at least one of user-supplied textual, audio, or video content from the one or more peripheral devices using the application, and generates a gift card holder from the received user-supplied content. The server also receives information associated with a merchant of a gift card and a monetary amount to be associated with the gift card, and transmits the gift card holder and the gift card to a recipient. |
| US09483785B1 |
Utilizing excess resource capacity for transcoding media
A transcoding service is described that is capable of utilizing the excess capacity of the computing resources of a service provider. The customer of the transcoding service can submit a bid price for completing the transcodes. As long as the specified price exceeds the fluctuating price of the unused resource instances, the transcoding service will execute the job on the unused instance(s). If the price of the unused resource instances exceeds the customer's bid, the transcoding process stops. The transcoding service may pause the transcoding when the dynamically fluctuating price of the unused resource exceeds the customer's bid and then resume when the price falls back down. Users can specify constraints for transcoding, such as timeframes during which the transcode must be completed, a total price for completing transcoding or priorities of the media files. The system can automatically optimize the utilization of the resource instances according to the constraints. |
| US09483783B1 |
Purchase system using a computing device
The invention relates to a method for purchasing a product by a consumer using a computing device. The method includes transmitting product information from a payee to the computing device, obtaining a purchase request for the product from the computing device, wherein the purchase request comprises a security identifier input by the consumer, inferring a consumer identity based on the purchase request and consumer information, authorizing the consumer to access the consumer information based on the purchase request and the consumer identity, wherein the consumer information is used to purchase the product, and generating a purchase authorization for the product and sending the purchase authorization to the payee based on the purchase request and the consumer information. |
| US09483777B2 |
Content display on moving vehicles
Systems and methods are provided for displaying content on a vehicle with at least one display device coupled to a frame member and extending to the right or left of the license plate receiving area of the vehicle. Content is selected and altered as desired, including based on user preferences and/or vehicle location. |
| US09483774B2 |
Systems and methods for generating surveys
Embodiments introduced describe single-action surveys, wherein a survey requires a single action only, such as a click on a mouse, a touch, tap, or stroke on a touch screen. Each single action means selecting one specific survey answer and a survey session may end after a single action is taken. In addition, a survey may end automatically within a substantially short period of time in the absence of any action. |
| US09483773B2 |
Point of view shopper camera system with orientation sensor
A point of view shopper camera system is provided to generate and analyze shoppers' view data. The point of view shopper camera system may comprise a head device including an eye camera and a head orientation sensor, a position tracking sensor to identify a shopper's position, and an analysis computing device. The eye camera may be configured to be mounted to the head of the shopper, and to capture a still or moving image of the field of view of the shopper. The analysis computing device may be configured to receive the captured image data from the eye camera, head orientation data from the head orientation sensor, and the shopper's position data from the position tracking sensor, and determine an estimated field of view of the shopper during a trip in a shopping environment. |
| US09483768B2 |
Methods and apparatuses for modeling customer interaction experiences
A computer-implemented method and an apparatus for modeling customer interaction experiences receives interaction data corresponding to one or more interactions between a customer and a customer support representative. At least one language associated with the interaction data is detected. Textual content in a plurality of languages is generated corresponding to the interaction data based at least in part on translating the interaction data using two or more languages different than the at least one language. At least one emotion score is determined for text corresponding to each language from among the plurality of languages. An aggregate emotion score is determined using the at least one emotion score for the text corresponding to the each language. An interaction experience of the customer is modeled based at least in part on the aggregate emotion score. |
| US09483767B2 |
Retail location services
Methods of preparing retail establishments are disclosed. An area for a retail location may be chosen and an individual may be selected to manage the retail location. The selection of the area may include an evaluation of geographical factors. From the area, a retail location may be selected based on an aggregate score of a set of characteristics of the retail location. The individual may remotely select the layout and furnishing of the retail location and may remotely monitor the progress of the preparation of the retail location. In an embodiment, the individual may be prepared to manage the retail location at a centralized location that is distinct from the area where the retail location is located. |
| US09483764B1 |
Biometric financial transaction system and method
Tokenless biometric authorization of transaction between a consumer and a merchant uses an identicator and an access device. A consumer registers with the identicator a biometric sample taken from the consumer. The consumer and merchant establish communications via the access device. The merchant proposes a transaction to the consumer via the access device. The access device communicates to the merchant associated with the access device. After the consumer and merchant have agreed on the transaction, the consumer and the identicator use the access device to establish communications. The access device communicates to the identicator the code associated with the access device. The identicator compares biometric sample from the consumer with registered biometric sample. Upon successful identification, the identicator forwards information regarding the consumer to the merchant. These steps accomplish a biometrically authorized electronic financial transaction without the consumer having to present any personalized man-made memory tokens. |
| US09483762B1 |
Invariant biohash security system and method
Systems, methods, and program products for providing secure authentication for electronic messages are disclosed. A method may comprise generating an asymmetric private key based at least in part upon an invariant biometric feature vector derived from an input biometric reading. The private key may be further based at least in part upon a user password. The resulting private key may not be stored but rather may be generated when required to authenticate an electronic message, at which time it may be used to provide a digital signature for the electronic message. The private key may be deleted after use. The private key may be regenerated by inputting both a new instance of the biometric reading as well as a new instance of the password. |
| US09483754B2 |
Interactive building stacking plans
A method for generating an interactive stacking plan of a building is disclosed. A building data file with one or more external tenant records in a first format is received on a server computer system. Data values of one or more of the external tenant record fields are imported into master tenant records, each of which is defined by a plurality of master tenant record attributes. Stacking plan graphical elements are generated for each of the master tenant records with a size proportional to a leased space. A user-activatable link that generates an independent display of at least one of the master tenant record attributes is included in the stacking plan graphical element. The stacking plan graphical elements are arranged in the interactive stacking plan according to the floor identifier attributes of the corresponding master tenant records. The interactive stacking plan is then transmitted to the client computer system. |
| US09483752B1 |
Multi-user thin client
System and method enabling multiple users to simultaneously share a client computing device are disclosed. Method includes retrieving a plurality of I/O device groups, wherein a first I/O device group in the plurality of I/O device groups is associated with a first group of input or output (IO) devices locally connected to a client computing device, and wherein a second I/O device group in the plurality of I/O device groups is associated with a second group of I/O devices locally connected to the client computing device. Method includes launching first and second instances of an application. Method includes associating the first instance of the application with the first I/O device group on the client computing device. Method includes associating the second instance of the application associated with the second I/O device group on the client computing device. |
| US09483751B2 |
Label privileges
Methods, systems, and apparatus for managing labeling privileges. In one aspect, a method includes receiving label data defining a label to be associated with an image of a first user in a photograph, the first user identified by a first user identifier and the label data associated with a submitting user identifier; accessing data defining labeling privileges for the first user identifier, the labeling privileges being for second users identified by respective second user identifiers, and the labeling privileges defining, for each second user, a labeling privilege for the second user to label an image of the first user in a photograph; determining whether the submitting user identifier is included in the second user identifiers; in response to determining that the submitting user identifier is included in the second user identifiers: determining the labeling privileges for the user identified by the submitting user identifier, and processing the label accordingly. |
| US09483745B2 |
Business network GUI
A computer program product tangibly embodied in a computer-readable storage device includes instructions that, when executed, generate in a display device a graphical user interface comprising: a business view area with first objects representing business entities participating in a business network and second objects representing business connections between the business entities; and a connect view area with third objects representing applications participating in the business network and fourth objects representing logical interactions between the applications; wherein the graphical user interface dynamically updates the first, second, third and fourth objects with metadata that is at least in part automatically gathered in the business network. |
| US09483743B1 |
System and method for improving recovery of a telecommunications network from an unscheduled loss of service using repeatable requirements for applications by design criticality classification
A system provides repeatable requirements for projects designed for criticality. A user interface outputs a list of business requirements for a project to assist in functional requirement selection, outputs a set of general functional requirements associated with an application that is associated with the project for selection, and receives selection of the set of general functional requirements. A server determines a design class for an application based on the selection, wherein the design class is based at least in part on at least one of an upstream application and a downstream application, wherein the application depends on the upstream application, and wherein the downstream application depends on the application. The user interface also outputs specific functional requirements for the application based on the design class for the application, receives selection of the specific functional requirements, and outputs a list of selected specific functional requirements to assist in developing system requirements for the application. |
| US09483739B2 |
Transductive feature selection with maximum-relevancy and minimum-redundancy criteria
Various embodiments select features from a feature space. In one embodiment, a set of training samples and a set of test samples are received. The set of training samples includes a set of features and a class value. The set of test samples includes the set of features absent the class value. A relevancy with respect to the class value is determined for each of a plurality of unselected features based on the set of training samples. A redundancy with respect to one or more of the set of features is determined for each of the plurality of unselected features in the first set of features based on the set of training samples and the set of test samples. A set of features is selected from the plurality of unselected features based on the relevancy and the redundancy determined for each of the plurality of unselected features. |
| US09483733B2 |
Global regular expression backreferences
A system and a method are provided for querying a knowledge resource. The querying system is configured for executing queries in a query language that accepts global backreferences that are not limited to a being located in the condition including a regular expression (regex) to which the global backreference refers. In the method, an input query is received, a query based thereon containing one or more global backreferences is executed, and results are retrieved. One condition of the query includes a regex that identifies strings that match the regex. The regex includes one or more capturing groups for capturing substrings of an identified matching string. The global backreference retrieves the captured substring(s). Each global backreference in the query can be a remote backreference, which is outside the regex condition to which it refers, or a local backreference, which is in the same condition as the regex. |
| US09483726B2 |
Three dimensional electronic patch
A three-dimensional electronic patch includes a flat flexible circuit substrate that includes an elastic layer including a first portion and a second portion. The second portion includes at least side connected to the elastic layer and one or more sides defined by one or more cuts in the elastic layer. The three-dimensional electronic patch further includes a first sensor on the first portion of the elastic layer, a first conductive sensing pad under the first portion of the elastic layer and in electrical connection with the first sensor, and a conductive layer under the second portion of the elastic layer and in electrical connection with the first sensor. The second portion is folded to position the conductive layer away from the first portion. |