| Document | Document Title |
|---|---|
| US09485590B2 |
Hearing device with a means for receiver current estimation and a method of estimating a receiver current for a hearing device
A hearing device with a unit for estimating the current consumed by the receiver of the hearing device. The hearing device includes a signal input unit for converting an input signal picked up by the signal input unit into a digital audio signal, a signal processing unit for processing the digital audio signal, a digital-to-analog converter for converting a processed audio signal from the signal processing unit, a power amplifier for amplifying a converted audio signal from the digital-to-analog converter, a receiver for generating sound according to an amplified audio signal from the power amplifier, and a battery for powering the hearing device. A receiver current estimation unit has a filter for filtering a receiver current indicative signal derived from the processed audio signal, the filter having a frequency response dependent on an impedance of the receiver. A method is provided for estimating a receiver current for a hearing device. |
| US09485588B2 |
Mapping system and method
A mapping system comprises a sensor unit which is mobile and receives magnetic audio frequency transmission from a site and positioning data with respect to the site to be mapped. A processing unit is operationally coupled with the sensor unit and determines at least one parameter of the magnetic transmission, forms positions of the sensor unit on the basis of positioning data, associates positions and the at least one parameter together, forms a quality map graphically showing a distribution associated with the at least one parameter with respect to positions on the site and outputs said quality map. |
| US09485586B2 |
Speaker driver
A speaker driver with a high degree of symmetry for use in a loudspeaker is disclosed. The disclosed motor assembly may be symmetrical about its long and radial axes. A voice coil disclosed may be supported by opposing upper and lower suspensions on the voice coil upper and lower ends. The upper and lower voice coil suspensions may be adhered to a frame above and below the motor assembly, respectively. |
| US09485584B1 |
Dual ring magnet apparatus
An apparatus related to a magnetic circuit design is disclosed. The apparatus includes a magnetic assembly and an electrically-conductive mobile member. The magnetic assembly includes an inner magnet, an outer magnet, an inner cap, an outer cap and a washer. The magnetic assembly is configured to produce a magnetic field having a zone of operation between the inner cap and the outer cap. The zone of operation has substantially uniform magnetic field strength. The zone of operation has magnetic field directions substantially perpendicular to an ideal motion direction. The electrically-conductive mobile member is disposed in the zone of operation of the magnetic field and electrically coupled to a diaphragm of a driver. The electrically-conductive mobile member is configured to move within the zone of operation of the magnetic field in response to the magnetic field when an alternating current is passed through the electrically-conductive mobile member. |
| US09485580B1 |
Headset with microphone and wired remote control
In an example embodiment a headset includes a phone jack, a speaker connected to the phone jack, a microphone coupled to the phone jack and a resistive switch string coupled to the phone jack to the same ring of the phone jack as the microphone. In another example an integrated circuit device includes a charge pump, a multi-voltage LDO having an input which is capable of being coupled to an output of the charge pump, an ADC; and a pull-up resistor coupled between an output of the LDO and an input of the ADC. In another example embodiment, a method for headset signal multiplexing includes providing a headset with a plurality of signal sources and voltage division multiplexing the plurality of signal sources on a common wire. |
| US09485579B2 |
System and method for information handling system wireless audio driven antenna
Audio information coexists with best efforts data on a wireless network, such as a wireless local area network, by defining a backoff dedicated to communicate of audio information and using undedicated resources to communicate best efforts data. The backoff has a periodic interval that corresponds to the sample rate of the audio information so that a set of audio frame slots communicated at the start of a backoff interval has a length of time to complete communication. The set of audio frame slots has, for instance, an audio frame slot for each audio endpoint interfaced with the network. Periodic backoffs ensures synchronized audio playback by dedicating an antenna to communication of audio frames at the sample rate of the audio information, while supporting best efforts network communication when audio information is not being communicated. |
| US09485578B2 |
Audio format
Mechanisms for obtaining an audio signal and information relating to the recording conditions of the audio signal are provided, the method comprising: obtaining an audio signal, wherein the audio signal is a voltage signal representation of sound, the voltage signal having been converted from a pressure signal; obtaining first information indicative of at least one objective feature and/or at least one perceptual feature associated with the conversion of the pressure signal into the audio signal in the form of a voltage signal representation; storing the audio signal, the first information, and second information identifying a relationship between the audio signal and the first information; determining an error adjustment for adjusting the audio signal based on the obtained information; applying the error adjustment to the audio signal to create an error-adjusted audio signal; and obtaining an audio signal and information relating to the recording conditions of the audio signal. |
| US09485575B2 |
Pre-filtering for loudspeakers protection
The present invention relates to a method of protecting an inductive loudspeaker. The method comprises filtering the audio stream by applying a compensation filter to the audio stream, sending the filtered audio stream to the inductive loudspeaker, computing an estimation of a frequency response of the inductive loudspeaker and updating the compensation filter so as to attenuate a frequency corresponding to a resonant frequency in the estimated frequency response of the inductive loudspeaker. |
| US09485573B2 |
Wireless communication system for use by teams
A helmet mounted communication system for use by teams includes a headset including any one of a speaker for projecting audio or a microphone for receiving audio, a mounting structure for mounting the headset in a helmet cavity of a helmet, and a biasing material between the headset and a cavity wall of the helmet cavity for floatably attaching the headset to the helmet in the helmet cavity. |
| US09485569B2 |
Sound signal processing apparatus, microphone apparatus, sound signal processing method, and program
A sound signal processing apparatus includes a sliding operation detecting section to which a sound signal collected by a microphone is inputted, and which determines start and end of a sliding operation by a determination process using a sliding sound signal component in the inputted sound signal, the sliding sound signal component being produced by the sliding operation on the microphone itself or its vicinity, and a control section that performs a predetermined control process that is set with respect to the sliding operation, during a period from the start to the end of the sliding operation determined by the sliding operation detecting section. |
| US09485568B2 |
Power management controller for drivers
A driver controller comprising a state machine for controlling transitions between a plurality of states. An output switch for providing a low impedance path to ground during transition periods. An output stage for decoupling output signal from driver amplifier during the transition periods. |
| US09485566B2 |
Miniature speaker module, method for enhancing frequency response thereof and electronic device
The present invention discloses a method for enhancing frequency response of a miniature speaker module, a miniature speaker module, and an electronic device. The method for enhancing frequency response of a miniature speaker module comprises the steps of: additionally providing an inverted tube in a rear cavity of the miniature speaker module to form a second driver in the inverted tube when an active driver works, the second driver and the active driver radiating jointly; and matching enhancement processing the input signals of the active driver according to the vibrating amplitude characteristics of the diaphragm of the active driver of the miniature speaker module additionally provided with the inverted tube. In the technical solutions provided by the present invention, as the frequency response of the whole miniature speaker module additionally provided with an inverted tube is enhanced on frequency bands below F0, and the signals are further matching enhancement processed according to the vibrating amplitude characteristics of the active driver, the frequency resource of the miniature speaker module on the whole frequency bands is enhanced greatly. |
| US09485563B2 |
Two way communication assembly
A two way communication assembly for discrete wireless communication includes a remote unit that may be coupled to an external electronic device. A remote processor is coupled to the remote unit. A remote transceiver is coupled to the remote unit and the remote processor. A remote actuator is coupled to the housing and the remote transceiver. A base unit may be positioned within a user's ear. A base processor is coupled to the base unit. A base transceiver is coupled to the base unit and the base processor. The base transceiver is in communication with the remote transceiver. A first base actuator is coupled to the base unit and the base processor. A second base actuator is coupled to the base unit and the base transceiver. A microphone is coupled to the base unit and the base processor. A speaker is coupled to the base unit and the base processor. |
| US09485562B2 |
Contactless rechargeable audio headset
This headset comprises two earphones (10), each comprising a generally ring-shaped, flexible circumaural or supra-aural pad (16), mounted on a shell (14) receiving a transducer (30). The headset comprises an electronic circuitry powered by a battery, and a battery recharging circuit connected to at least one inductive-coupling recharging coil (20). The coil is housed in a pad (16), and it is housed in a region of the pad (16) that is close to an outer limit plane, on the wearer side, of the envelope (16a, 16b) of the pad, for example near a seam (C) between two portions (16a, 16b) of an envelope of the pad. |
| US09485561B2 |
Thermal powered wearable device
Embodiments disclosed herein generally relate to electronics powered by thermal energy. More particularly, embodiments of the present disclosure relate to wireless headphones that are powered by thermoelectric generators. One embodiment provides a wireless headphone having a wireless audio device capable of generating an acoustic output from signals received through a wireless communication link, and a thermoelectric generator assembly configured to provide electrical power to the wireless audio device. |
| US09485559B2 |
Hearing system and finger ring for the hearing system
The hearing system comprises a finger ring and a hearing device body. The finger ring includes: a first short-distance wireless communication portion; a vibration output portion disposed at a position that contacts a finger to convert a voice signal, which is received by the first short-distance wireless communication portion, into a cartilage conduction vibration and outputs it; and a first power source portion that supplies power to the first short-distance wireless communication portion and the vibration output portion. The talk device body includes: a second short-distance wireless communication portion that communicates with the first short-distance wireless communication portion; a microphone; a voice signal output portion that makes the second short-distance wireless communication portion output the voice signal according to a voice captured by the microphone; and a second power source portion that supplies power to the second short-distance wireless communication portion, the microphone, and the voice signal output portion. |
| US09485558B2 |
Flying disc with speaker
A flying disc is disclosed that can be used in recreational activities. The flying disc includes a body having an aerodynamic design. A sound reproduction device housing is attached to the body. A sound reproduction device is positioned in the sound reproduction device housing that is configured to generate audible music via an audio transducer when the sound reproduction device is activated. |
| US09485557B2 |
Device accessory with speakers
A device accessory to produce high quality high volume sound, comprising a clip case for holding the mobile device and a speaker unit that provides high quality high volume sound produced from the mobile device. The clip case further comprises a base portion attached to a plurality of side walls and a first pivotal attachment means. An outer side of the base portion includes at least one magnet and a configured to hold a support means. At least one of the pluralities of side walls recess includes a pair of side magnets. The speaker unit comprises a pair of lower magnets, a support means magnet, a second pivotal attachment means, a pair of speaker side magnets, a charging port, an ON/OFF button, an indicator, at least one flat panel speaker having at least one carbon fiber board excited by a mini exciter positioned inside the speaker unit and a microphone. |
| US09485556B1 |
Speaker array for sound imaging
In an augmented reality environment, a speaker array is centrally located within an area to generate sound for the environment. The speaker array has a spherical or hemispherical body and speakers mounted about the body to emit sound in multiple directions. A controller is provided to select sets of speakers to form beams of sound in determined directions. The shaped beams are output to deliver a full audio experience in the environment from the fixed location speaker array. |
| US09485551B2 |
Enhanced routing and wavelength assignment techniques for reducing wavelength continuity blocking
Embodiments of the disclosure are directed to optimizing routing and wavelength assignment in a network. An embodiment determines a routing assignment for a network, wherein the routing assignment is determined using a decongestion cost-based function; and determines a wavelength assignment for the network based on vector difference. The determination of the wavelength assignment comprises spanning the network for a path; calculating a weighted correlation function for at least one length in the network; storing the weighted correlation; and determining if a next path exists. If a next path is found, spanning for a next path in the network, and if a next path is not found, returning the stored correlation. |
| US09485548B2 |
Origination and destination based routing
One or more aspects of the disclosure relate to various functions and processes related to routing of calls based on origination and/or destination information. In one aspect, a method may comprise receiving a request for a call session, and the request may include an indicator that may indicate whether to route a call based on origination and/or destination information of the call session. Based on the indicator, a routing element may determine whether the call session should be routed based on origination information and/or destination information. |
| US09485542B2 |
Method and apparatus for adding and displaying an inline reply within a video message
Methods of adding an inline reply to a video email/message and presenting a chain of video emails/messages are provided. A video email/message is received and an inline reply to the video email/message is generated and associated with a point during playback of the video email/message. The inline reply is sent by return email such that, during subsequent playback of the video email/message, playback of the video email/message is paused at the point and the inline reply is displayed. |
| US09485539B2 |
Method and client module for use in a multimedia system
A multimedia server receives a plurality of programs of a multimedia source. The multimedia server includes a tuning module to receive the plurality of programs and to select a set of programs from the plurality of programs based on a set of program select commands that is derived from select requests. A program mixer mixes the set of programs into a stream of program data. One or more transceiving modules transmit the stream of program data on to corresponding communication paths and receive the select requests. A client module produces the select requests for one or more clients. The client module includes a selection module to produce at least one of the select requests. A network interface controller transmits at least one of select requests to the multimedia server and receives the stream of program data via the communication path or paths in response. |
| US09485536B1 |
Method and system for updating programming listing data for a broadcasting system
A method and system for processing listing data includes a listing system having a listing database associated therewith, an external data source communicating station data, external schedule data and external program data to a listing system and an internal source communicating internal program data to the listing system. The listing system stores the station data, external schedule data and external program data and the internal program data in the database. The listing system communicates the listing data to other systems using the listing data such as a program guide system. |
| US09485529B2 |
Method and apparatus for ordering entertainment programs from different programming transmission sources
The present invention provides an improved method and apparatus for purchasing media features for programming transmissions. A selection is sent to a server system to buy an upgraded media feature for a programming transmission. The server system automatically coordinates purchasing the media feature from a programming transmission source and providing the media feature from the programming transmission source. In one embodiment, an entertainment system includes a user interface from which a viewer selects an upgraded media feature for a programming transmission, wherein the programming transmission with the upgraded media feature is provided to the entertainment system. |
| US09485521B2 |
Encoding and decoding image using sample adaptive offset with start band indicator
A method for image decoding includes receiving image information including filter coefficients, generating a restored block for a current block on the basis of the image information; and applying an adaptive loop filter to the restored block on the basis of the filter coefficients. Image encoding efficiency may be improved, and complexity may be reduced. |
| US09485520B2 |
Parallel motion estimation in video coding
Methods for improved parallel motion estimation are provided that decouple the merging candidate list derivation and motion estimation for merge mode and skip mode and the advanced motion vector predictor (AMVP) candidate list construction from regular motion estimation to increase the coding quality in parallel motion estimation while meeting throughput requirements. This decoupling may be accomplished by modifying the availability rules for spatial motion data (SMD) positions for construction of the candidate lists. As part of the decoupling, largest coding units (LCUs) of a picture may be divided into non-overlapping parallel motion estimation regions (PMER) of equal size. Within a PMER, motion estimation for merge mode, skip mode, and normal inter-prediction mode may be performed in parallel for all the prediction units (PUs) in the PMER. |
| US09485518B2 |
Decoding method and apparatus with candidate motion vectors
A moving picture coding apparatus includes: a motion vector predictor candidate calculation unit which calculates one or more motion vector predictor candidates and the number of available predictor candidates; an inter prediction control unit which selects an optimum motion vector predictor candidate; and a variable length coding unit which sets the motion vector predictor candidate list size to the number of available predictor candidates, and variable-length codes a motion vector predictor index used for coding a motion vector, by assigning a bit string according to the motion vector predictor candidate list size to the index. |
| US09485517B2 |
Motion vector prediction with motion vectors from multiple views in multi-view video coding
Aspects of this disclosure relate to, in an example, a method that includes identifying a first block of video data in a first temporal location from a first view, wherein the first block is associated with a first disparity motion vector. The method also includes determining a motion vector predictor for a second motion vector associated with a second block of video data, wherein the motion vector predictor is based on the first disparity motion vector. When the second motion vector comprises a disparity motion vector, the method includes determining the motion vector predictor comprises scaling the first disparity motion vector to generate a scaled motion vector predictor, wherein scaling the first disparity motion vector comprises applying a scaling factor comprising a view distance of the second disparity motion vector divided by a view distance of the first motion vector to the first disparity motion vector. |
| US09485514B2 |
System and method for compressing video and reformatting the compressed video to simulate uncompressed video with a lower bandwidth
Presented is a video distribution system that includes a transmitter that receives an uncompressed source video signal and includes a compressor for compressing the uncompressed source video signal into a compressed video signal having a bandwidth lower than the bandwidth of the uncompressed source video signal, a reformatter configured for reformatting the compressed video signal to simulate an uncompressed video signal having a bandwidth lower than the bandwidth of the uncompressed video signal. The video distribution system also includes a receiver that receives the compressed video signal that simulates an uncompressed video signal and includes a decompressor configured for decompressing the compressed video signal that simulates an uncompressed video signal into a decompressed video signal, and output port configured for transmitting the decompressed video signal to a display. |
| US09485511B2 |
Video-encoding method and video-encoding apparatus based on encoding units determined in accordance with a tree structure, and video-decoding method and video-decoding apparatus based on encoding units determined in accordance with a tree structure
Provided are a method and apparatus for encoding a video and a method and apparatus for decoding a video. The encoding method includes: splitting a picture of the video into one or more maximum coding units that are coding units having a maximum size; encoding the picture based on coding units according to depths which are obtained by hierarchically splitting each of the one or more maximum coding units according to depths in each of the one or more maximum coding units, determining coding units according to coded depths with respect to each of the coding units according to depths, and thus determining coding units having a tree structure; and outputting data that is encoded based on the coding units having the tree structure, information about the coded depths and an encoding mode, and coding unit structure information indicating a size and a variable depth of a coding unit. |
| US09485510B2 |
Method and apparatus for coding video and method and apparatus for decoding video, using intra prediction
A video decoding method involving intra prediction includes: parsing a most probable mode (MPM) flag of a block while parsing symbols of the block of an encoded video from a received bitstream; determining whether a predetermined number of a plurality of candidate intra prediction modes are used to predict an intra prediction mode of the block based on the MPM flag; when it is determined that the plurality of candidate intra prediction modes are used based on the MPM flag, determining the plurality of candidate intra prediction modes based on intra prediction modes of a left block and an upper block that are adjacent to the block while restoring the intra prediction mode of the block by using the parsed symbols. |
| US09485509B2 |
Image compression device, image compression method, image decompression device, and image decompression method
An image compression device includes: a first encoder that encodes a target block included in a segment in a first encoding mode; a second encoder that encodes the target block in a second encoding mode using a fixed-length coding to obtain a second encoded data; a calculator that calculates an accumulated amount of the first encoded data of the blocks; a selector that selects an encoding mode to be used to encode the target block from among the first encoding mode and the second encoding mode; and a determiner that determines whether to encode encoding mode information according to a predetermined condition. The selector selects the second encoding mode if a sum of an accumulated amount and an amount of the second encoded data of all remaining blocks in a segment exceeds a target value. |
| US09485506B2 |
Method and system for constraining slice header processing overhead in video coding
A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing a maximum slice rate for the video sequence, computing a maximum number of slices for the picture based on the maximum slice rate, and encoding the picture wherein a number of slices used to encode the picture is enforced to be no more than the maximum number of slices. |
| US09485505B2 |
Method and apparatus of reference picture management for video coding
A method and apparatus that determine one or more reference pictures for the current image unit and indicate the reference pictures using information associated with COIs (coding order indexes) of the reference pictures are disclosed. The image unit corresponds to a picture, a slice of the picture, or a region of the picture. Inter-picture encoding or decoding is applied to the input data using the reference pictures. The information associated with the COIs can be incorporated in a slice header or a picture header of a bitstream associated with the video sequence. Furthermore, the COI can be represented by a coded COI using a fixed number of bits, wherein the coded COI is constrained to a range from 0 to MAC_COI-1 and MAX_COI is a positive integer. |
| US09485503B2 |
Inside view motion prediction among texture and depth view components
The techniques of this disclosure may be generally related to using motion information for a corresponding block from a texture view component that corresponds with a block in a depth view component in coding the block in the depth view component. In some examples, for coding purposes, the techniques may use motion information when the spatial resolution of the texture view component is different than the spatial resolution of the depth view component. |
| US09485498B2 |
Display apparatus, projection apparatus, display assist apparatus, and system
A display apparatus includes a master/slave setting unit configured to execute at least one of setting of a master apparatus which displays a switching-display synchronization signal superposed on an image as a target to be displayed and setting of a slave apparatus which does not display the switching-display synchronization signal, a synchronization-signal superposition unit configured to superpose the switching-display synchronization signal on the image as the target to be displayed, when setting of the master apparatus is executed by the master/slave setting unit, and a display unit configured to display the image on which the switching-display synchronization signal is superposed by the synchronization signal superposition unit. |
| US09485492B2 |
Compression methods and apparatus for occlusion data
Methods and apparatus for coding occlusion layers, such as occlusion video data and occlusion depth data in 3D video, are disclosed. A decoding method comprising the steps of: extracting an indicator representative of an original format for received occlusion data, the original format selected from one of a sparse occlusion data format and a filled occlusion data format; arranging 2D data, which is associated with the occlusion data, at location 0 in a reference picture list; decoding the occlusion data to produce decoded occlusion data; when the indicator indicates the sparse occlusion data format for the occlusion data, filling a non-occlusion area of the occlusion data with data indicative of a defined characteristic to produce decoded occlusion data; when the indicator indicates the filled occlusion data format for the occlusion data, replacing the occlusion data in a non-occlusion area of the occlusion data with sample values from a corresponding area of associated 2D data to produce decoded occlusion data; and outputting the decoded occlusion. |
| US09485490B2 |
Broadcast receiver and 3D video data processing method thereof
A broadcast receiver and a 3D video data processing method are disclosed. The method includes receiving a broadcast signal including system information and video data, parsing system information of a program, and determining whether the program provides a 3D broadcast service from the system information, extracting, if the program provides a 3D broadcast service, broadcast data of the program, and processing video data of broadcast data according to the system information. The broadcast receiver includes a receiving unit receiving a broadcast signal including system information and video data, an SI processor parsing system information of a program, and determining whether the program provides a 3D broadcast service from the system information, a demultiplexer extracting, if the program provides a 3D broadcast service, broadcast data of the program, and a video processor processing video data of the broadcast data according to system information. |
| US09485489B2 |
Broadcasting receiver and method for displaying 3D images
Disclosed are a method for displaying 3D images and a broadcast receiver. The method for displaying 3D images according to one embodiment of the present invention comprises the steps of: receiving broadcasting signals including video data and 3D object data; decoding the 3D object data, the 3D object data including texts or image information for a 3D object, output position information of the 3D object, and disparity information of the 3D object; obtaining parallax values from the disparity information and producing distortion compensation coefficients using the parallax values; adjusting a display size of the 3D object using the distortion compensation coefficients; and outputting and displaying the 3D object. |
| US09485482B2 |
Imaging device, method for controlling imaging device, and storage medium storing a control program for color mixing correction
An imaging apparatus (10) includes: an image pickup device (14) including plural photoelectric conversion elements arrayed in a predetermined first direction and second direction; a color filter that has a repeatedly disposed basic array pattern that includes a first filter corresponding to a first color that contributes most to obtaining a brightness signal, and second filters corresponding second colors, placed in a predetermined pattern; a drive section (22) that drives the image pickup device (14) such that, for an array of pixels to read from the image pickup device (14), pixel data of pixels placed at a set cycle in at least one direction of the first direction or the second direction is read to give a second array that is different from a first array expressing an array of all the pixels read from the image pickup device (14); and an image processing section (20) that corrects pixel data of a subject pixel for color mixing correction based on pixel data of a pixel that is the same color as an adjacent pixel in adjacent contact with the subject pixel in the first array, and that is a pixel that has the shortest distance from the adjacent pixel in the first array. |
| US09485480B2 |
Laser based projection display system
A laser projection system including one or more pluralities of laser sources, each plurality of laser sources emitting light having substantially a different predetermined wavelength in the visible range, a fiber optic laser beam combiner combining outputs of at least one of the pluralities of laser sources into one optical fiber, a fiber-optic delivery component coupled to the one optical fiber and one or more spatial light modulators, and one or more homogenizing optical elements, and one or more optical lens system for projecting the associated images on a screen. |
| US09485477B2 |
Security system including modular ring housing
A modular building system arrangement includes a plurality of electrical building systems. Each electrical building system has a housing with a mechanical connector that is connectable with a like connector of each other building system housing. Members of any subset of the building system housings are connectable with each other to form a building system assembly. The building systems of the building system assembly conjointly define an electrically conductive pathway interconnecting each of the building systems of the building system assembly. The pathway carries power and/or data. |
| US09485475B2 |
Surgical imaging system and method for processing surgical images
An imaging system having at least two surgical systems, each surgical system having a camera control unit with a network port; a camera head coupled to the camera control unit; and a monitor coupled to the camera control unit; a network is coupled to the network port of each camera control unit; and a server is coupled to the network, the server having a storage device with a user database and a case database; and wherein the server is configured as a web server to provide data, video and images from the camera control units to users connected to the network. |
| US09485471B2 |
Write-protected recording
A surveillance apparatus continuously records imaged data from a camera into a circular buffer in a local memory. When a record signal is received, the system records the video stream that was recorded before the record signal was received, and the video stream that is recorded after the record signal was received. The recorded segment is then write-protected, so that the surveillance apparatus does not overwrite the recorded segment. The recorded segment could then be sent to a remote memory via a wireless connection to free up local memory for future recording sessions. |
| US09485470B2 |
Evaluation unit, evaluation method, measurement system for a crash test vehicle measurement and a method for performing a crash test vehicle measurement
An evaluation unit is provided for processing images and/or image sequences of measurement areas (8, 10, 12, 14, 16, 18) that are detectable on a crash test vehicle (4). Transmitted images and/or image sequences from at least one measurement sensor are utilizable. Additionally, image fusion apparatus is provided to produce digital image fusion of images and/or image sequences as image data (38, 40) of the same measurement area (8, 10, 12, 14, 16, 18). An evaluation method, a measurement system for a crash test vehicle measurement and a method for performing a crash test vehicle measurement also are provided. |
| US09485468B2 |
System, method and device for providing communications
Provided are a system, method and device for providing communications to a multiple dwellings. |
| US09485466B2 |
Video processing in a multi-participant video conference
Some embodiments provide an architecture for establishing multi-participant video conferences. This architecture has a central distributor that receives video images from two or more participants. From the received images, the central distributor generates composite images that the central distributor transmits back to the participants. Each composite image includes a set of sub images, where each sub image belongs to one participant. In some embodiments, the central distributor saves network bandwidth by removing each particular participant's image from the composite image that the central distributor sends to the particular participant. In some embodiments, images received from each participant are arranged in the composite in a non-interleaved manner. For instance, in some embodiments, the composite image includes at most one sub-image for each participant, and no two sub-images are interleaved. |
| US09485464B2 |
Processing method for video conference and server using the method
In a processing method for a video conference, start speaking events and end speaking events of endpoints joined in the video conference are detected. Video streaming of a speaking endpoint is displayed in a speaking area of a foreground window of a display device. A current time “t”, a duration time “T” of the video conference, a start speaking time “si” and an end speaking time “ei” of the endpoints are recorded. Real-time activity scores of each of the endpoints are calculated and updated according to video recording contents. Video streaming of non-speaking endpoints are displayed in corresponding areas of the display device according to the calculated activity scores. |
| US09485461B2 |
Video conferencing using wireless peripheral video conferencing device
A method includes receiving, establishing, by a video session controlling device, a video conference session. The video session controlling device includes at least one video conference service providing component. The method includes identifying a specification of the at least one video conference service providing component. The method also includes identifying a position of the at least one video conference service providing component. A specification of at least one wireless peripheral video conferencing device is identified. A position of the at least one wireless peripheral video conferencing device is also identified. The method also includes determining a combination of devices to provide the video conference services based on relative specifications and positions of the at least one video conference service providing component and the at least one wireless peripheral video conferencing device. The video conference services are implemented using the determined combination of devices. |
| US09485459B2 |
Virtual window
Novel tools and techniques are provided for displaying video. In some embodiments, novel tools and techniques might be provided for sensing the presence and/or position of a user in a room, and/or for customizing displayed content (including video call content, media content, and/or the like) based on the sensed presence and/or position of the user. In particular, in some aspects, a user device (which might include, without limitation, a video calling device, an image capture device, a gaming console, etc.) might determine a position of a user relative to a display device in communication with the user device. The user device and/or a control server (in communication with the user device over a network) might adjust an apparent view of video or image(s) displayed on the display device, based at least in part on the determined position of the user relative to the display device. |
| US09485453B2 |
Moving image player device
A moving image player device of the present invention includes an interpolated image generating unit that generates an interpolated frame corresponding to a time between two adjacent input frames using two input frames among the plurality of input frames, and a video playing unit that detects a scene change in the video, outputs the plurality of input frames or the interpolated frames in time series based on the detection result, and plays the video at an arbitrary playing speed. When the scene change is detected, the video playing unit skips a display of the interpolated frames corresponding to time between an input frame at the end of a first scene and an input frame at the head of a second scene, and displays an input frame of the second scene or the interpolated frame after the input frame at the end of the first scene or the interpolated frame. |
| US09485452B2 |
Imaging device, video content generating method and storage medium
A CPU of an imaging device of the present invention causes an interval moving image to be captured for each interval photographing, selects frames to be stored as still images from among a plurality of frames constituting the interval moving image based on a face image, blurring, and the presence or absence of a change, and causes these selected still images to be stored in association with the interval moving image. When an amount of data exceeding that for a preset storage time length is recorded, the CPU first deletes low-grade interval moving images. Then, if this is not enough, the CPU deletes low-grade still images, and thereby retains an image file (a mixture of moving images and still images) within the desired time length. |
| US09485451B2 |
Image pickup apparatus with air cooling unit
An image pickup apparatus is reduced in width and length dimensions. The image pickup apparatus has a heat sink-cum-duct disposed on a rear face side of an air cooling fan. Air sucked from an opening defined by an opening portion of the heat sink-cum-duct is guided to an air inlet port of the cooling fan through a ventilation path defined by plural fins of the heat sink-cum-duct and is discharged from an air outlet port of the cooling fan. A circuit board disposed on a rear face side of the heat sink-cum-duct is cooled and heat generated in the circuit board is radiated from a heat radiation plate. The image pickup unit, cooling fan, heat sink-cum-duct, circuit board, and heat radiation plate are each formed into a flat shape having a short dimension in optical axis direction and are substantially parallel to one another. |
| US09485448B2 |
Method for receiving a broadcast signal and broadcast receiver
A method of receiving a broadcast signal including a Non-Real-Time (NRT) service and a broadcast receiver are disclosed herein. A method of receiving a broadcast signal including an NRT service, the method comprises receiving a broadcast signal including first signaling information and second signaling information, identifying the NRT service based on the first signaling information, parsing the second signaling information to identify an Internet Protocol (IP) address of an NRT service signaling channel, receiving the NRT service signaling channel by accessing the IP address, and downloading a desired NRT service based on the NRT service signaling channel. |
| US09485439B2 |
Shortwave infrared camera with bandwidth restriction
A camera comprises an image plane for capturing shortwave infrared wavelengths. The image plane captures only a portion of a shortwave infrared wavelength band, and excludes other wavelengths. A method of designing a camera is also disclosed. |
| US09485438B2 |
Image processing system with image conversion unit that composites overhead view images and image processing method
An image detection unit extracts image feature values from images of each camera. An image conversion unit computes a blend rate according to the image feature values and composites an image of a superposition area wherein a plurality of camera images overlap. An assessment is made of a correspondence of the image feature values of each image in the superposition area, and a determination is made that a solid object is present if the correlation is weak. Furthermore, a determination is made that the solid object is present in the superposition area if the image feature values in each image have locationally overlapping portions. In such a circumstance, the image is composited with the blend rate of the image with a greater image feature value set large. |
| US09485435B2 |
Device for synthesizing high dynamic range image based on per-pixel exposure mapping and method thereof
A device for synthesizing a high dynamic range image based on per-pixel exposure mapping includes an image-capturing module, an image-processing module, and a recursive control module. The image-capturing module serves to obtain a plurality of source images each having a unique exposure value. The image-processing module uses an exposure-value modulating means to perform exposure synthesis to pixels on an identical location of two of the source images that have similar exposure values according to exposure values of the pixels, so as to form synthesis images. The recursive control module sends the synthesis images back to the image-processing module for reprocessing until the image-processing module generates a single synthesis image. |
| US09485432B1 |
Methods, systems and apparatuses for dual-camera based zooming
A method and apparatus for zooming an image by a zoom factor wherein a first image without zoom and a second image with fixed optical zoom are processed to find a mapping between low resolution patches and high resolution patches that are then used for zooming the first image if the zoom factor is less than the fixed optical zoom else the mapping between low resolution patches and high resolution patches are used for zooming the second image with fixed optical zoom. |
| US09485431B2 |
Image capturing apparatus and method for controlling the same
An image capturing apparatus includes an image capturing unit configured to capture an image of a subject to generate image data; a detachable display unit configured to display the image data generated by the image capturing unit; a wireless communication unit configured to connect with a second device including the display unit via wireless communication; a detection unit configured to detect attachment/detachment of the display unit; and a control unit configured to control the wireless communication unit in order that connection to one of the display unit and the second device is given priority depending on the attachment/detachment of the display unit detected by the detection unit. |
| US09485429B2 |
Capturing device, capturing system and capturing method
A capturing device includes an image sensor that generates an image signal by performing photoelectric conversion for light from a subject, a control unit that generates a setting value for setting a range where an image resulting from the image signal is cut, based on a first instruction input from a user, a setting value storage unit that stores the setting value generated by the control unit, an image conversion unit that reads the setting value from the setting value storage unit, and cuts a specific region specified by the setting value from the image and enlarges the cut region, when there is a second instruction input from the user, and an output unit that converts a signal of the image cut and enlarged by the image conversion unit into an image signal of a predetermined format and outputs the converted image signal. |
| US09485427B2 |
Apparatus and methods for stabilization and vibration reduction
The present invention provides an apparatus for stabilizing an imaging device and methods of using the same for a wide variety of applications including photography, video, and filming. Also provided are unmanned vehicles including aerial vehicles that contain the apparatus disclosed herein. |
| US09485426B2 |
Moving picture processing device for controlling moving picture processing
A moving picture processing device detects a predetermined feature point existing in a frame of a moving picture, identifies a position of the frame, in which a changing state of the detected feature point in the moving picture shows a predetermined changing state, and causes the predetermined changing state, as a condition to identify the position of the frame, to be common to other moving pictures. |
| US09485423B2 |
Associating cameras with users and objects in a social networking system
Images uploaded by users of a social networking system are analyzed to determine signatures of cameras used to capture the images. A camera signature comprises features extracted from images that characterize the camera used for capturing the image, for example, faulty pixel positions in the camera and metadata available in files storing the images. Associations between users and cameras are inferred based on actions relating users with the cameras, for example, users uploading images, users being tagged in images captured with a camera, and the like. Associations between users of the social networking system related via cameras are inferred. These associations are used beneficially for the social networking system, for example, for recommending potential connections to a user, recommending events and groups to users, identifying multiple user accounts created by the same user, detecting fraudulent accounts, and determining affinity between users. |
| US09485419B2 |
Camera system encoder/decoder architecture
An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode. |
| US09485412B2 |
Device and method for using pressure-sensing touch screen to take picture
A device uses a pressure-sensing touch screen to detect the pressure from a touch input on the touch screen. Based on whether the pressure is greater than a predetermined pressure value or not, and the type of the touch input, various picture-taking operations are performed. |
| US09485409B2 |
Image capturing apparatus and control method therefor
An image capturing apparatus comprising: an image sensor configured to perform photoelectric conversion on light that enters via an imaging optical system and output an image signal; a focus detection unit configured to detect an in-focus position based on the image signal output from the image sensor; an edge detection unit configured to detect an edge angle and a number of edge of a subject included in an image based on the image signal output from the image sensor; and a correction unit configured to obtain a correction amount for the in-focus position based on the detected edge angle and the number of edge and correct the in-focus position detected by the focus detection unit based on the obtained correction amount. |
| US09485408B2 |
Imaging apparatus and exposure determining method
It is intended to provide an imaging apparatus that enables proper exposure of phase difference detection pixels and thereby makes it possible to perform phase difference autofocusing with high accuracy. A system control unit 11 selects phase difference detection pixels from phase difference detection pixels 51R and 51L existing in a selected phase difference detection area 52 according to a position of the selected phase difference detection area 52 in a row direction X, and determines exposure conditions based on output signals of the selected phase difference detection pixels. A defocus amount calculation unit 19 calculates a defocus amount using output signals of the phase difference detection pixels 51R and 51L existing in the selected phase difference detection area 52 that are part of a shot image signal produced by shooting that is performed by an imaging device 5 under the exposure conditions determined by the exposure determining unit 11. |
| US09485407B2 |
Method of capturing images and obtaining information of the images
A method of capturing images includes the following steps of: providing a camera module including an image capture unit, a liquid lens unit, and an image process unit; capturing a clear image through the camera module; enlarging the camera's relative aperture to create a shallow depth-of-field; adjusting the focal plane of the liquid lens unit to analyze object depth information in the clear image; and adding or storing the depth information of the object to the clear image. |
| US09485406B2 |
Focus detection apparatus, focus detection method and program, and imaging apparatus
A focus detection apparatus is arranged to obtain image data of an object obtained by an imaging unit having a pupil division unit of a photographing optical system for forming an optical image of the object, obtain setting information of a focus detection mode of the photographing optical system, set a focus detection area set into a pixel array area of the imaging unit, by dividing a predetermined area into a plurality of division areas in accordance with the focus detection mode and arranging the plurality of division areas in accordance with a different positional relation, form focus detection information by using the image data of the set focus detection area, and generate a drive signal of the photographing optical system on the basis of the focus detection information. |
| US09485404B2 |
Timing system and method with integrated event participant tracking management services
An automated system and method for managing a tracking and an automated real-time remote reporting thereof of a participant's participation in an event having a participant event management system (PEMS) that receives a request for tracking of the participant, a participant proximity detector detects the proximity of the participant to a detection point, a location detection system receiving and transmitting participant location data, the timing system receives the preorder request from the PEMS, determines a time of passing of the detection point of the participant, receives the location data and associates the participant event number with the participant identifier number, and transmits the location data forming at least a part of the participant tracking data to an output interface. |
| US09485402B2 |
Imaging apparatus, operation control terminal device, operation control system and computer readable medium for operation control
An imaging apparatus, comprising: a communication unit configured to communicate with an external device; an operation control unit configured to control execution of predetermined operation concerning photographing in accordance with a control signal received from the external device; and a detection unit configured to detect disconnection of communication with the external device, wherein the operation control unit is configured to control execution of the predetermined operation in accordance with a predetermined operation control setting when disconnection of the communication with the external device is detected during execution of the predetermined operation. |
| US09485400B2 |
Camera module and method for the production thereof
A camera module including an objective lens housing with an optical system, an image sensor chip with wire bonding connections, and a printed circuit board for contacting the image sensor chip. The printed circuit board is designed with wire bonding areas to which the wire bonding connections of the image sensor chip are connected, and the assembly made up of the image sensor chip and the printed circuit board is designed in such a manner that the image sensor chip is focus-adjusted to the optical system by changing its position relative to the printed circuit board taking advantage of the flexibility of the wire bonding connections of the image sensor chip. The invention further relates to a method of manufacturing the camera module. |
| US09485394B1 |
Machine vision inspection devices and machine vision methods of inspection
Machine vision inspection devices and machine vision methods for inspecting objects, such as objects with shiny surfaces. Device embodiments include an illumination housing with a central aperture and a specialized aperture cover. Use of the claimed device embodiments to inspect objects eliminates the void (dark spot) common to known machine vision inspection methods. |
| US09485393B2 |
Imaging device including detection unit having a light receiving plane
An imaging device includes an illumination unit that irradiates a moving object with light A, an optical system that focuses into an image of the object, a detection unit having a light receiving plane on which the image of the object by this optical system is formed, and an analysis unit. The detection unit includes a plurality of light receiving cells d1 to dN which are arrayed in an x direction on the light receiving plane, and is disposed such that the image moves in a y direction on the light receiving plane, the detection unit receives light or does not receive light according to pseudo noise code sequences along the y direction respectively on the plurality of light receiving cells. |
| US09485390B2 |
Method for creating color profile
The method includes creating: a first table defining conversion relationship from a signal of a first standard color to which limitation of a total amount of ink is not applied into a signal of a second standard color to which the limitation is applied; a second table defining conversion relationship from the signal of the second standard color into a first expansion color signal to which the limitation is applied; a third table defining conversion relationship from a color signal in a device-independent color space corresponding to the signal of the second standard color into a color signal in a device-dependent color space; and a fourth table (color profile) defining conversion relationship from a color signal in the device-independent color space corresponding to the signal of the second standard color into a second expansion color signal in the device-dependent color space by the third and second tables. |
| US09485389B2 |
Page image correction device, and recording medium
A page image correction device includes: an acquisition unit that acquires a page image of each page of a plurality of pages from a book, the book being successively imaged in a thickness direction thereof; and a processor configured to: derive, in accordance with a page image of a first prescribed page and a page image of a second prescribed page differing from the first prescribed page, an amount of change in a thickness of the book when the book is opened to the first prescribed page as compared to when the book is opened to the second prescribed page; and correct, in accordance with the amount of change in the thickness of the book, page images of pages between the first prescribed page and the second prescribed page. |
| US09485388B2 |
Image processing apparatus, method, and computer storage medium configured for line correction based on a number of linked dots
An apparatus that corrects multivalued data after halftone processing and which includes a line input unit configured to input multivalued data of a correction line to be corrected among the multivalued data, a detection unit configured to convert multivalued data of a precedent line that precedes the correction line by N lines into dot data and to detect a dot in the precedent line, and a line correction unit configured to correct the multivalued data of the correction line based on a number of linked dots from the bottom-end edge, and the number of linked detected dots is the number of dots that are linked in a sub scanning direction from the correction line down to the bottom-end edge, and the bottom-end edge is an edge at which the density becomes lower in the sub scanning direction and the lower of density values represents the background color. |
| US09485386B2 |
Method for creating scanner profile, method for creating device profile, method for acquiring color value, image reading system, and image forming apparatus
A method for creating a scanner profile according to the present invention includes the steps of: by reading, by a scanner, a printed material of chart image data comprising a plurality of patches which are composed of C, M, Y, K values and differentiated in color and density from each other, acquiring a first color value for the patches; acquiring a K value for the patches of the chart image data; acquiring a second color value for the patches by color-measuring the printed material by the colorimeter; and creating a scanner profile describing a relationship of the second color value to the first color value and the K value, based on the acquired first color value, K value, and second color value for each of the plurality of patches. |
| US09485385B2 |
Image processing apparatus and computer program for generating a file in which plural area images of a document image are disposed in different pages
An image processing apparatus includes a processor, and memory storing computer readable instructions, when executed by the processor, causing the apparatus to function as a document image acquiring unit configured to acquire document image data which is generated by optically reading a document and represents a document image, an area image generating unit configured to use the document image data to generate plural area image data representing plural area images that are included in the document image, and a file generating unit configured to generate a file including the plural area image data such that the plural area images are disposed in different pages. |
| US09485383B2 |
Image based correction of distortion from a scanner
System, method, and non-transitory computer readable medium encoded with instructions for imaging an object. Dividing raw data into forward scan data and backward scan data. Reversing the order of the backward scan data to produce inverted backward scan data. Determining an offset value that is associated with a maximum value of a first function based on the forward scan data and the inverted backward scan data. The forward scan data is shifted by the offset value relative to the inverted backward scan data. Producing a first image of the object that comprises the forward scan data interlaced with the inverted backward scan data. The forward scan data is shifted by the offset value relative to the inverted backward scan data. |
| US09485380B2 |
Image reading apparatus, image forming apparatus and computer readable medium storing program
An image reading apparatus includes: an illumination unit that is disposed so as to be moved relative to a recording medium and illuminates the recording medium with light beams of plural colors that are circulated in predetermined order; a reading unit that reads an image recorded on the recording medium by receiving reflection light that is produced as a result of the illumination unit's illuminating the recording medium during the moving relative to the recording medium; and a control unit that controls the illumination unit so that a difference between a first illumination interval and a second illumination interval is determined based on a reading resolution of the reading unit. |
| US09485377B2 |
Controlling power state based on presence detection
An image forming apparatus having a first power state and a second power state, which is lower in power consumption than the first power state, includes a detection unit in which a plurality of elements for detecting an object are arranged, and a control unit configured to acquire a detection result from part of the plurality of elements and to determine whether a person is present in a detection range of the detection unit, and in a case where it is determined that a person is present in the detection range, to acquire a detection result from part of the plurality of elements of the detection unit and to determine whether to shift the image forming apparatus from the second power state to the first power state. |
| US09485374B2 |
Image forming apparatus that detects the number of connection stage of a paper feed cassette unit
An image forming apparatus reducing number of control signals in detecting nth connection stage of a paper feed cassette unit piled up, and increases noise resistance. It includes a main body part and a paper feed cassette unit that can be piled up in plural stages under main body part. Main body part has a start control line transmitting a start signal; a ready control line transmitting a ready signal; and a main body side control part generating start signal and detects nth connection stage of paper feed cassette unit on number of times of ready signal. Paper feed cassette unit has a cassette side control part delaying start signal inputted from an upper stage through start control line to output it to a lower stage, and while delaying start signal, generating a ready signal to output it toward ready control line to upper stage. |
| US09485370B2 |
Device for display control over settings object, method for displaying settings object, and computer-readable storage medium for computer program
A device is provided which displays objects provided on an item by item basis of conditions of processing. The device includes a storage portion configured to store data therein, the data indicating specific objects belonging to a custom group, and indicating child specific objects belonging to a subordinate group lower than the custom group; an update portion configured to update the data in such a manner that the specific object designated belongs to the subordinate group and configured to update the data in such a manner that the child specific object designated is withdrawn from the subordinate group; and a display control portion configured to display a first screen in which a specific object not belonging to the subordinate group, and a call object are provided, and configured to display when operation is made on the call object, a second screen in which the child specific objects are provided. |
| US09485368B2 |
Electronic document generation apparatus, recording medium, and electronic document generation system
An electronic document generation apparatus generates a recognition object image by performing an image processing on a scan image so that each of a plurality of line areas extracted from a character area of the scan image should be determined as a unit recognition area and transmits the recognition object image to the cloud server. The apparatus further receives text data which is a processing result of an optical character recognition processing on the recognition object image, in which a delimiter code is added at the end of a character recognition result for each of a plurality of unit recognition areas, from the cloud server, separates the text data into a plurality of character string data on the basis of the delimiter code, and generates an electronic document by arranging each of the plurality of character string data in the line area corresponding to each character string data. |
| US09485362B2 |
Methods and systems for providing a mobile office phone
Methods and systems for providing a mobile office phone are provided herein. In one embodiment a system includes a private branch exchange (PBX), a server configured to integrate user equipment (UE) onto the PBX by attaching a mobile telephone number of the UE as an extension on the PBX, and a session initiation protocol (SIP) server coupled with the server and PBX that allows the UE to place and receive calls and messages over data channels of a network. |
| US09485358B2 |
Information acquisition method, device, and system
An information acquisition method includes establishing a data channel with a telephone agent system when a voice call is conducted with the telephone agent system, displaying an information acquisition page provided by the telephone agent system through the data channel, receiving feedback information via the information acquisition page, and sending the feedback information to the telephone agent system through the data channel. |
| US09485357B2 |
Splitting a call for an emergent event into multiple devices using data channels
Public safety access points (PSAP), such as 911 and e911 service providers, are often overwhelmed with information coming from a number of callers. As part of an initial assessment, a determination is often made as to whether two or more callers are calling about the same emergent event. If two or more callers are calling about the same emergent event, the callers and PSAP may interact at the same time but differently, such as different content or different media types. As a benefit, on-site activities may be coordinated in a manner that helps reduce the demands on PSAP resources and helps to facilitate a more accurate and appropriate response to the emergent event. |
| US09485355B2 |
Communication device for providing an automatically initiated outgoing communication as an incoming communication
A communication device and method for providing an automatically initiated outgoing communication as an incoming communication are provided. Outgoing communication is automatically initiated via a communication interface of the communication device. After the outgoing communication is initiated, an indication of the outgoing communication is provided at the communication device, such that the outgoing communication is provided as an incoming communication at the communication device. |
| US09485348B2 |
Mobile terminal and communication method thereof
A mobile terminal includes a wireless communication unit establishing a first communication session with a first entity and a second communication session with a second entity, a display displaying a plurality of windows including a first window and a second window, a memory storing a merging menu, and a controller controlling the display to display the first window related to the first communication session and the second window related to the second communication session, the controller generating a third window including the first communication session and the second communication session in response to a an input and controlling the display to display the third window further including the first entity and the second entity. |
| US09485347B2 |
Voice-operated interface for DTMF-controlled systems
An arrangement for allowing “hands-free” access to DTMF-controlled systems, such as one's voice mail messaging systems, utilizes a speech-to-DTMF tone application that monitors the communication between the user and the DTMF-controlled system. A speech recognition unit is utilized to retrieve certain voice commands (e.g., “next”, “skip”, “repeat”, “forward”, etc.) when uttered by the user. The application then translates the received commands into the proper DTMF tone sequence used by the DTMF-controlled system and transmits the DTMF tones to the system. The application is particularly useful in the cell phone environment and avoids the necessity of the user to constantly switch between using the keypad and listening to messages/commands from the system. |
| US09485345B2 |
911 services and vital sign measurement utilizing mobile phone sensors and applications
Improved methods for utilizing 911 services, for implementing 911 dispatch protocols, and for measuring vital signs of a human, all by accessing mobile phone sensors and applications, are disclosed. Vital signs such as heart rate, breathing rate, breathing distress, and blood pressure can be measured using mobile phone sensors and applications. A method for differential estimation of blood pressure involves the synchronization of time between two mobile phones, locating an appropriate position for one cell phone and recording heart sounds, and recording video data from the finger tip of the subject using the other mobile phone. |
| US09485338B2 |
Features and manufacturing methods for a case for a portable electronic device
An accessory unit for use with an electronic device is described. Accessory unit includes a front flap and a rear cover. The rear cover includes a recessed portion that defines a chamber and a lip portion. The chamber is configured to receive a consumer electronic device, and the lip portion is configured to hold the consumer electronic device therein by an interference fit that exposes substantially all of a display portion of the consumer electronic product. The front flap can include segments formed from panels with folding regions therebetween, which allow the front flap to fold. Further, an end region of the front flap pivotally couples the front flap to the rear cover, such that the front flap may be moved between open and closed configurations. The front may include magnetic elements. |
| US09485336B2 |
Waterproof structure and electronic apparatus
A waterproof structure includes a body member, a lid member that includes a waterproof member that inhibits water from entering through the opening, a guide member and in which a shaft hole including a circular hole portion and a long hole portion communicating with the circular hole portion is formed, a shaft section that is provided in the lid member, is supported in the shaft hole, is rotated inside the circular hole portion, is regulated in the rotation thereof inside the long hole portion, and is guided to the body member side, a first biasing section that biases the shaft section in a removing direction away from the body member, a second biasing section that biases the shaft section in a rotation direction, and a locking member that locks the lid member to the body member in a state where the waterproof member inhibits water from entering through the opening. |
| US09485335B1 |
Sub-rate codes within the 10GBASE-T frame structure
A method of operation in a high-speed Ethernet transceiver is disclosed. The method includes engaging in an autonegotiation process with a link partner transceiver to indicate whether one or more sub-rate modes of operation are supported. Each sub-rate mode of operation corresponds to a sub-data rate that is less than a maximum data rate. The autonegotiation process is terminated. The transceiver then participates in a training process. The training process includes receiving a first training sequence corresponding to a first sub-data rate that is less than the maximum data rate. A signal quality parameter for the received first training sequence is measured. The training sequence is terminated based on the measured signal quality parameter failing a predetermined criteria. A second training sequence is then initiated that corresponds to a second sub-data rate that is less than the first sub-data rate without starting a second autonegotiation process. |
| US09485334B2 |
Response time relaxation for high efficiency WLAN
Aspects of the present disclosure relate to techniques for generating responses to extended length frames having increased symbol lengths without changing the short interframe space duration. According to certain aspects, a method for transmitting an extended length frame generally includes generating a packet having a preamble decodable by a first type of device having a first set of capabilities and a second type of device having a second set of capabilities, wherein at least a first portion of the packet is generated using an increased symbol duration or increased cyclic prefix relative to a second portion of the packet generated using a standard symbol duration or standard cyclic prefix and the packet includes padding symbols after the first portion, and outputting the generated packet for transmission. |
| US09485332B2 |
Offloading execution of a portion of a client-side web application to a server
Offloading execution of a portion of a client-side Web application to a server. In one embodiment, for example, a computer-implemented includes identifying a function to-be-offloaded in a client-side scripting language file; generating an offloaded function based on the function to-be-offloaded; replacing, in the scripting language file, the body of the function to-be-offloaded with client RPC stub which, when executed by an end-user computing device as a result of a call to the function to-be-offloaded, causes one or more arguments passed into the function to-be-offloaded to be marshalled and sent to a server in one or more network messages. |
| US09485330B2 |
Web browser operation method and system
A browser operation and control method is provided for a server and a client having a browser. The server receives a query request message from the client, and the query request message contains a character string converted by the client from voice information inputted by a user of the client. The server obtains control information for operating the browser based on the character string in the query request message, and the control information indicating one of a plurality results provided by the server including a direct URL based on the character string, a direct operation command based on the character string, and a search result page based on the character string. The server sends a query response message containing the control information to the client such that the client operates the browser based on the control information in response to the voice information inputted by the user. |
| US09485329B1 |
Action-defined conditions for selecting curated content
The subject matter of this specification can be implemented in, among other things, a method that includes providing instructions to an administrative device for presenting an administrative interface. The administrative interface includes user input controls for selecting conditions for inclusion of content in a section of a user interface. The method includes receiving one or more selections of the user input controls. The selections include the conditions for inclusion of content in the section of the user interface. The conditions include types of actions requested by an account associated with the user interface. The method includes receiving a request for the user interface from a client device. The method includes selecting a subset of the content for inclusion in the section of the user interface based on the conditions and the type of action. The method includes providing instructions to the client device for presenting the user interface. |
| US09485328B2 |
Game control device, game program, game control method and game system
The game control device may include a storage unit, a first match-up executing unit, a character ability updating unit, and a second match-up executing unit. The storage unit stores an ability value of each player character. The first match-up executing unit executes a first match-up between two player characters in response to input of a communication terminal, and to determine a result of the first match-up based on the stored ability value of each player character. The character ability updating unit updates, based on the result of the first match-up, the ability values of the two player characters, and causes the storage unit to store the updated ability values. The second match-up executing unit executes a second match-up between player characters independently from the first match-up without input of the communication terminal, and determines a result of the second match-up based on the stored ability value of each player character. |
| US09485325B2 |
Prioritized reporting of metering data
A utility company may schedule when and how endpoints report resource consumption data based on relative priorities of endpoints or the customers associated therewith. By associating endpoints with one of multiple different quality of service (QoS) levels, and sending each endpoint a reporting schedule based on its respective QoS level, the utility company may configure prioritized reporting of resource consumption data by endpoints of an advanced metering infrastructure (AMI) with automatic meter reading (AMR). |
| US09485324B2 |
Fast sequential message store
A broker may be used as an intermediary to exchange messages between producers and consumers. The broker may store and dispatch messages from a physical queue stored in a persistent memory. More specifically, the broker may enqueue messages to the physical queue that are received from producers and may dispatch messages from the physical queue to interested consumers. The broker may further utilize one or more logical queues stored in transient memory to track the status of the messages stored in persistent memory. As messages are dispatched to and acknowledged by interested consumers, the broker deletes acknowledged messages from the physical queue. The messages deleted are those preceding a physical ACKlevel pointer that specifies the first non-acknowledged message in the physical queue. The physical ACKlevel pointer is advanced in the physical queue based on the relative position of corresponding logical ACKlevel pointers maintained by the logical queues. |
| US09485323B1 |
Managing pooled client-premise resources via provider-defined interfaces
Methods and apparatus for managing pooled client-premise resources via provider-defined interfaces are described. A pool management request is received from a client via a programmatic interface implemented at a provider network, indicating at least one resource located at a data center external to the provider network. An activation status of the resource within a pool is to be managed by a service of the provider network. A network connection between an administrative resource of the service, located within the provider network, and a control module instantiated on behalf of the service at the external data center is established. A command is transmitted from the administrative resource to the control module to activate the particular resource. |
| US09485322B2 |
Method and system for providing targeted information using profile attributes with variable confidence levels in a mobile environment
Various systems and methods for of generating a user profile for use in providing targeted-content-messages to a wireless access terminal (W-AT) are disclosed. For example, a user profile with at least one profile element may be provided to the W-AT, and a profile confidence level for the profile element may be also provided. |
| US09485312B2 |
Data network notification bar processing system
A method and apparatus are disclosed of providing a user application with a notification message. One example method may include receiving a script to setup a message queue, the script may include a database schema and the script may be executed by a processor to apply the database schema to a database that includes the message queue. The method may also include receiving one or more notifications messages having specific notification content that is applied to notification messages. The notifications may be received from a remote device. The message queue may include notification content used to generate notification messages destined for end user devices. |
| US09485310B1 |
Multi-core storage processor assigning other cores to process requests of core-affined streams
A multi-core processor of a network attached storage system processes requests from host computers for services of a file system service. Each core maintains endpoints of respective connection-layer connections to the hosts to affine respective streams of network traffic with the core, and dynamically and preferentially assigns execution threads of the core to process file system service requests of the streams affined with the core. Each core also co-operates with the other cores to dynamically and non-preferentially (a) assign execution threads of the core to process file system service requests of the streams affined with the other cores, and (b) assign execution threads of the other cores to process file system service requests of the streams affined with the core, promoting efficient use of the cores for the processing workload of the file system service. |
| US09485309B2 |
Optimal fair distribution among buckets of different capacities
A processing device can implement an optimal fair distribution. In one embodiment, the processing device divides a distribution pattern associated with a distributed system into segments based on a quality of distribution for the distributed system. For each partition of the plurality of partitions, the processing device calculates a weight for the partition based on a number of segments in the plurality of segments and a capacity of a bucket associated with the partition. The processing device generates a map of partitions based on the weight for each of the plurality of partitions. The processing device distributes a plurality of objects in the distributed system to the plurality of buckets based on the map of partitions. |
| US09485308B2 |
Zero copy volume reconstruction
Examples described herein include a data migration system for migrating data between different data storage environments. The data migration system creates a first volume on a first storage system, and creates a logical unit within the first volume. The data migration system then creates a virtual volume on a virtual storage system associated with a second storage system, wherein data stored in the virtual volume is backed by the logical unit on the first storage system. The data migration system then replicates, on the virtual volume, a set of data stored on the second storage system. Upon replicating the set of data onto the virtual volume the virtual storage system may automatically create a copy of the corresponding data in the logical unit of the first volume. |
| US09485303B2 |
Cluster system based on parallel computing framework, and host node, computing node and method for executing application therein
A cluster system based on a parallel computing framework is provided, and the cluster system includes a host node configured to execute a host program for a parallel computing framework and a computing node configured to be connected to the host node and execute a kernel program for the parallel computing frame work. |
| US09485302B2 |
Data management system and method for displaying data
A user information management method for a hub server connected to a terminal and service provider server, the method including registering user information for the terminal or the service provider server, receiving history information including data created by a user from the registered terminal or the registered service provider server, storing integrated history information obtained by sorting the received history information based on the user information, and transmitting the integrated history information in response to an integrated history information request message received from the registered terminal. Thus, the user can check the functions executed by the terminals owned by the user in an integrated manner and the data generated by multiple diverse terminals and service provider servers are managed in an efficient and integrated manner. |
| US09485301B2 |
Prioritized link establishment for data transfer using task scheduling
A system and method for scheduling data transfers between systems. One or more data requesting systems may request access to particular data. The request for access to the particular data may correspond to a request that a task to be performed. The task may be to exchange the particular data between a data accessing system having access to the particular data and a data requesting system requesting access to the particular data. The communication exchange may be scheduled for processing. In some embodiments, the communication exchange may be initiated based on a parameter included in the request that the task be performed. |
| US09485292B2 |
Display protocol interception in the network for services and network-based multimedia support for VDI
An apparatus and related method are provided for improving the performance of virtual desktop services. A network device is deployed in a network to intercept packets of a control session initiated by a client with a connection broker to obtain data from a host. The network device initiates a new control session to the connection broker on behalf of the client. The network device receives host information from the connection broker, replaces address information of the network device for the host information in a control session message and sends the control session message to the client. The network device establishes a data session with the client, initiates a data session with the host on behalf of the client and relays data between the data session with the host and the data session with the client such that the network device is transparent to the client and the host. |
| US09485288B2 |
Peer-to-peer communication method in content centric network environment
There is provided a peer-to-peer communication method in a content centric network environment. In embodiments, the peer-to-peer communication method in a content centric network (hereinafter referred to as a “CCN”) environment includes, receiving, by a CCN router, a join message including a desired service name of a user node from the user node, transmitting, by the CCN router, the join message to a rendezvous point mapped to the service name and forming a share tree, receiving, by the CCN router, a content request message including a name of content that is provided through the service from the user node, and transmitting, by the CCN router, the content request message through an interface connected to the share tree. |
| US09485287B2 |
Indicating bit stream subsets
A method of indicating bit stream subsets in a video bit stream (210) is provided. The method comprises receiving the bit stream, dividing the bit stream into video packets (211-216), wherein each packet comprises either one of video data or supplemental information, and marking each packet with a single subset identifier (stream_id). Each subset identifier is associated with a corresponding bit stream subset (221-223). Further, a method of extracting video packets from a video bit stream is provided. The method comprises providing relevant subset identifiers, receiving video packets from the bit stream, and, for each received packet, inspecting the subset identifier of the packet. The packet is extracted if the subset identifier matches one of the relevant subset identifiers. This allows condensing properties of a bit stream subset into a single identifier, thereby simplifying the processing of video packets in the network and on the client side. Further, devices corresponding to the aforementioned methods are provided. |
| US09485285B1 |
Assisting the authoring of posts to an asymmetric social network
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for assisting the authoring of posts to an asymmetric social network. In one aspect, a method performed by a system of one or more data processing devices includes receiving, at the system, an identification of an electronic document that is available on the Internet, the system identifying image content in the electronic document, the system filtering the identified image content, the system triggering presentation of the filtered image content to an author of a post to an asymmetric social network, the system receiving a selection of a first image from amongst the presented image content, and the system adding the first image to a post to the asymmetric social network. |
| US09485282B2 |
Method and apparatus for negotiating color information in image communication system
A method and apparatus for a video call service in a communication system is provided. The method includes transmitting, in a process of configuring a session together with a second terminal by a first terminal, resolution information and color information of an image, which are transmittable and receivable, to the second terminal by the first terminal, receiving the resolution information and the color information of the image, which are transmittable and receivable by the second terminal, from the second terminal by the first terminal, and compressing the image according to the received resolution information and the received color information, and transmitting the image to the second terminal, by the first terminal. |
| US09485281B2 |
Communication system and server
A SOAP-SIP adapter 2 establishes a session with the terminals 5b and 5c in accordance with a SIP. At this time, the SOAP-SIP adapter 2 sends an INVITE message including its own IP address and port number to the terminals 5b and 5c. Each terminal 5b, 5c sends a 200 OK including its own IP address and port number to the SOAP-SIP adapter 2. The SOAP-SIP adapter 2 stores correspondingly the IP address and port number of each terminal 5b, 5c in a memory. The SOAP-SIP adapter 2 transfers a media stream received from each terminal 5b, 5c to the destination of the corresponding IP address and port number by referring to the memory. Also, a pseudo RBT is sent to the terminal A5b from establishing the session with the terminal A5b till establishing the session with the terminal B5c to prevent a silent state. |
| US09485279B2 |
Automated generation of access control rules for use in a distributed network management system that uses a label-based policy model
An access control rule authorizing communication between a plurality of managed servers within an administrative domain is determined. Communication information describing past communication between the plurality of managed servers is obtained. A subset of managed servers from the plurality of managed servers is identified by grouping the plurality of managed servers based on the obtained communication information. A group-level label set is determined to associate with the subset of managed servers. Role labels are determined for managed servers in the subset of managed servers. A managed server is associated with one role label. Based on the group-level label set and the role labels, an access control rule is generated authorizing communication between a first managed server of the subset of managed servers and a second managed server. The access control rule is stored as part of an administrative domain-wide management policy. |
| US09485276B2 |
Dynamic service handling using a honeypot
A network device comprises one or more processors coupled to a memory, and a dynamic services module configured for execution by the one or more processors to receive, from a client device, a service request specifying a service. The dynamic service module is further configured for execution by the one or more processors to, in response to obtaining a negative indication for the service, send a representation of the service request to a honeypot to cause the honeypot to offer the service to the client device. |
| US09485269B2 |
Systems and methods for reporter-based filtering of electronic communications and messages
Methods and apparatuses for filtering electronic communications in a communication system. The method includes receiving a message report from a user in response to an electronic message received by the user, and identifying a confidence value associated with the user from whom the message report is received. The method also includes adding, if the confidence value exceeds a predetermined confidence value threshold, the confidence value to a signature value associated with the electronic message, and determining if the signature value exceeds a signature value threshold. The method further includes filtering the electronic message if the signature value exceeds the signature value threshold. |
| US09485263B2 |
Volatility-based classifier for security solutions
Various embodiments provide an approach to classifying security events based on the concept of behavior change detection or “volatility.” Behavior change detection is utilized, in place of a pre-defined patterns approach, to look at a system's behavior and detect any variances from what would otherwise be normal operating behavior. In operation, machine learning techniques are utilized as an event classification mechanism which facilitates implementation scalability. The machine learning techniques are iterative and continue to learn over time. Operational scalability issues are addressed by using the computed volatility of the events in a time series as input for a classifier. During a learning process (i.e., the machine learning process), the system identifies relevant features that are affected by security incidents. When in operation, the system evaluates those features in real-time and provides a probability that an incident is about to occur. |
| US09485260B2 |
Method and apparatus for information verification
The present disclosure provides a method and an apparatus for user verification. A terminal device recognizes a sequence of click operations made by the user according to a maneuver prompted on a terminal device. The sequence of click operations carries operation information from which a click pattern characteristic, such as a characteristic code, can be determined. Upon receiving the determined click pattern characteristic, a server verifies the user input by matching the click pattern characteristic with a verification code set or stored by the server. The click pattern characteristic may be based on recognizing clicking or tapping operations performed by the user at a specified time and/or in a designated area. The method enables user verification on devices that lowers the rate of errors in the user input of verification codes. |
| US09485254B2 |
Method and system for authenticating a security device
Methods for authenticating a security device at a local network location for providing a secure access from the local network location to a remote network location are provided. A security device is registered by installing private security software on the security device that generates an asymmetrical encryption key pair including an encryption key and a decryption key. The encryption key is stored only on the security device and the decryption key is stored only on a remote server. Embodiments of the present invention provide increased security by not storing the encryption key on the remote server so that attackers stealing data from the server cannot pretend to a user having the registered security device. A corresponding system for authenticating a security device is also provided. |
| US09485250B2 |
Authority trusted secure system component
One embodiment is in the form of a Self-Service Terminal (SST), such as an automated teller machine (ATM). The SST includes a peripheral device, such as a cash dispenser, and a security controller device including a memory device and a coupling to the peripheral device. The security controller device is operable to perform data processing activities including receiving peripheral device identifying data from the peripheral device and transmitting a public key (SCpk) of the security controller device to the peripheral device. The security controller may then decrypt a received peripheral device encryption key (Ki) according to SCpk, generate a first security controller encryption key (Ke1), and generate a first message authentication code key and encrypt the first message authentication code key according to Ke1 to obtain (Km1)Ke1. (Km1)Ke1 may then be stored in the memory device and transmitted to the peripheral device. |
| US09485248B2 |
Elevating trust in user identity during RESTful authentication and authorization
Credentials sent over a back channel during the authentication of a user to a RESTful service can elevate the trust the recipient system can place in the user's identity. The addition of an identity credential of higher strength can increase confidence in user identities electronically presented with a lower strength credential. Attributes from either credential can be used to determine authorization to a protected resource. |
| US09485244B2 |
Executing an operation over file repositories located in different authentication domains using a representational state transfer (REST)-compliant client
An initial server, located in an initial authentication domain, receives a requested operation from a RESTful client system, and generates a redirections list having entries indicating servers located in authentication domains other than the initial domain. The initial server transmits the redirections list back to the client system. The redirections list instructs the client system to perform a command on each of the servers indicated in the redirections list, and may optionally be transmitted with a partial result from the initial server. The client system verifies that partial results in responses from servers in the other authentication domains and from the initial server are of an appropriate result type and number, and then aggregates all the partial results received from all authentication domains into a single final result, which may be displayed to a user of the client system. |
| US09485241B2 |
Secure communication paths in data networks with tethered devices
A communication network processes intermediate security data from intermediate access nodes on a communication path between a network access node and an end-point device to determine if the intermediate access nodes are authorized. If the intermediate access nodes are authorized, then the network processes end-point security data from the end-point device to determine if the end-point device is authorized. If the end-point device is authorized, then the network processes end-point tethering data from the end-point device to determine if any tethered communication devices are coupled to the end-point device. If the end-point device is not coupled to any tethered communication devices, then the network authorizes a data transfer session for the end-point device over the communication path. If the end-point device is coupled to a tethered communication device, then the network denies authorization for the data transfer session over the communication path for the end-point device. |
| US09485240B2 |
Multi-account login method and apparatus
The present invention discloses a multi-account login method and apparatus. Herein, the multi-account login method comprises: opening a temporary webpage window in a browser according to a multi-account login instruction; creating a Cookie for the temporary webpage window, wherein the Cookie is independent of a global Cookie of the browser; and performing multi-account login by using the temporary webpage window. By means of this application, it is convenient for a multi-account user to use a browser, thereby improving the use experience of the multi-account user in using the browser. |
| US09485234B1 |
Virtualized endpoints in a multi-tenant environment
Customers accessing resources or services in a multi-tenant environment can obtain assurance that a provider of that environment will honor only requests associated with the customer and will reject any requests that might have been tampered with or otherwise falsely generated. Various endpoints or interfaces can be used, which can be located in the multi-tenant environment, in a customer environment, or in a separate location. These endpoints or interfaces can sign unsigned requests, or otherwise increase the credentials of a signed request, on behalf of a customer. In some embodiments, additional metadata can be added that can increase the authentication level of the requests. Such an approach can enable a customer to provide or delegate access to the resources without exposing the credentials outside a secure environment. |
| US09485233B1 |
Virtual desktop accelerator support for network gateway
The subject disclosure relates to a method for initiating an accelerated desktop session between a client device and a remote server. In some aspects, the method includes steps for receiving a request, from a client device, to initiate a second connection with a server using a second communication protocol, in response to the request, facilitating a validation of the client device by forwarding a token received from the client device to the server and receiving, from the server, an indication that the client device has been properly validated. In certain aspects, the method further comprises steps for initiating the second connection between the client device and the server using the second communication protocol, based on the indication that the client device has been properly validated. A client device and computer-readable medium are also provided. |
| US09485226B2 |
Method for including an implicit integrity or authenticity check into a white-box implementation
A method of performing a cryptographic operation using a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an identifying string value; receiving, by the cryptographic system, an input message; performing, by the cryptographic system, a keyed cryptographic operation mapping the input message into an output message wherein the output message is the correct result when the identifying string value equals a binding string value. |
| US09485225B2 |
Method for manufacturing a filtering module
A method is provided for defining a filtering module between a first module processing information with a first sensitivity level, and a second module processing information with a second sensitivity level connected, in parallel with the filtering module, by a cryptographic module. The method includes defining a set of filtering rules in a language that can be compiled, defining the properties of messages whereof transmission is allowed between the first and second modules; validation processing the predefined set of rules, validating that a transmission authorization or refusal has in fact been provided by applying the set of rules to any information that may be provided at the input of the filtering module; compiling the predefined set of rules; and integrating the compiled set of rules into a rules database of the filtering module. |
| US09485218B2 |
Device for preventing, detecting and responding to security threats
A device to prevent, detect and respond to one or more security threats between one or more controlled hosts and one or more services accessible from the controlled host. The device determines the authenticity of a user of a controlled host and activates user specific configurations under which the device monitors and controls all communications between the user, the controlled host and the services. As such, the device ensures the flow of only legitimate and authorized communications. Suspicious communications, such as those with malicious intent, malformed packets, among others, are stopped, reported for analysis and action. Additionally, upon detecting suspicious communication, the device modifies the activated user specific configurations under which the device monitors and controls the communications between the user, the controlled host and the services. |
| US09485214B2 |
Use of reversed DNS records for distributed mapping of asymmetric cryptographic keys to custom data
A server sends a lookup request for a first domain name to a Domain Name System (DNS) in response to receiving data associated with a user. The first domain name includes the data associated with the user. The server receives, an Internet Protocol (IP) address corresponding to the first domain name from the DNS. In response to receiving a request for data, the server determines an Internet Protocol (IP) address, wherein the request comprises an identifier, and wherein the IP address is determined based on the identifier. The server sends a reversed domain name lookup request for the IP address to the DNS. The server receives a domain name in response to the reversed domain name lookup request from the DNS. The data is determined based on the received domain name. |
| US09485211B2 |
Social networking website system with automatic participation based on current location information
A social networking website system with automatic registration based on a current location information. Individuals are automatically enrolled into social network services based on a current location determined from their mobile devices. In particular, farmers in rural places can be enrolled into social networks in their local districts, and they can interact with others using audio and video messages employing their local languages. Such interaction can be adhoc in nature, employing audio messages, or audio and video messages. In general, automatic memberships to social networks, social groups and to discussion lists are provided to users, based on user's current location. |
| US09485210B2 |
Systems and methods for social parenting platform and network
A parent social network based on relationship of children, including of activities, needs, interests or combinations thereof, is described. The parent social network can identify at least two minors with a common activity, need, interest or combination thereof, identify an adult responsible for the identified minors; and propose to link the identified adults. The parent social network can also provide post and other data to a parent based on interests and activities of a child. The parent social network can also identify and subscribe the parent to relevant children related calendars. The parent social network can allow effective communication between relevant parents using messaging and other means. |
| US09485207B2 |
Processing of messages using theme and modality criteria
Embodiments related to a message processing system are disclosed herein. In some embodiments, a computing system may include receiver logic to receive a message addressed to a user; analysis logic to determine whether a message collection, including the received message, has a common theme (e.g., a common sender or common content); modality logic to identify a messaging modality associated with each of the messages in the message collection; criteria logic to determine whether the message collection satisfies modality criteria (e.g., the messages represent at least two different messaging modalities); and notification logic to provide a notification of the message collection in response to determining that the message collection has a common theme and satisfies the modality criteria. Other embodiments may be disclosed and/or claimed. |
| US09485204B2 |
Reducing photo-tagging spam
A photo spam detector detects illegitimate non-natively captured images through extracting image features and feeding the extracted features into a probabilistic model. The probabilistic model categorizes the photo as legitimate or illegitimate. Requests to tag one or more users in a photo are analyzed by a tag analyzer that assesses relationships between the tag requests themselves, social relationships between the tagged users, and the presence or absence of faces within the regions specified by the tag requests. Based on the classification of images or tags as illegitimate, a social networking system applies one or more social media distribution policies to the image or tags to suppress or prohibit distribution. |
| US09485200B2 |
Network switch with external buffering via looparound path
Described embodiments process data packets received by a network switch coupled to an external buffering device. The network switch determines a queue of an internal buffer of the network switch associated with a flow of the received packet and determines whether the received packet should be forwarded to the external buffering device. If the received packet should be forwarded to the external buffering device, the network switch sets an external buffering active indicator indicating that the network switch is in an external buffering mode for the flow, tags the received packet with metadata, and forwards the packet to the external buffering device. The external buffering device stores the forwarded packet in a queue of a memory of the external buffering device corresponding to the tagged metadata of the forwarded packet. The network switch processes packets stored in the internal buffer of the network switch. |
| US09485197B2 |
Task scheduling using virtual clusters
In one embodiment, a device receives information regarding a data set to be processed by a map-reduce process. The device generates a set of virtual clusters for the map-reduce process based on network bandwidths between nodes of the virtual clusters, each node of the virtual cluster corresponding to a resource device, and associates the data set with a map-reduce process task. The device then schedules the execution of the task by a node of the virtual clusters based on the network bandwidth between the node and a source node on which the data set resides. |
| US09485195B2 |
Instantaneous random early detection packet dropping with drop precedence
A circuit that receives queue number that indicates a queue stored within a memory unit and a packet descriptor that includes a drop precedence value, and in response determines an instantaneous queue depth of the queue. The instantaneous queue depth and drop precedence value are used to determine a drop probability. The drop probability is used to randomly determine if the packet descriptor should be stored in the queue. When a packet descriptor is not stored in a queue the packet associated with the packet descriptor is dropped. The queue has a first queue depth range. A first drop probability is used when the queue depth is within the first queue depth range and the drop precedence is equal to the first value. A second drop probability is used when the queue depth is within the first queue depth range and the drop precedence equal to a second value. |
| US09485192B2 |
Selectable service node resources
In one example, a method includes receiving, by a service node, a request from an access node to establish a pseudowire to be used for sending subscriber traffic to the service node for application of services to the subscriber traffic at the service node, and, in response to receiving the request, sending a request message from the service node to a central server requesting both subscriber authentication and assignment of a forwarding component of the service node to which to anchor the pseudowire. The method also includes receiving, by the service node and from the central server, an authentication message in response to the request message, wherein the authentication message confirms subscriber authentication and indicates a forwarding component of the service node to which the service node should anchor the pseudowire. |
| US09485191B2 |
Flow-control within a high-performance, scalable and drop-free data center switch fabric
A high-performance, scalable and drop-free data center switch fabric and infrastructure is described. The data center switch fabric may leverage low cost, off-the-shelf packet-based switching components (e.g., IP over Ethernet (IPoE)) and overlay forwarding technologies rather than proprietary switch fabric. In one example, host network accelerators (HNAs) are positioned between servers (e.g., virtual machines or dedicated servers) of the data center and an IPoE core network that provides point-to-point connectivity between the servers. The HNAs are hardware devices that embed virtual routers on one or more integrated circuits, where the virtual router are configured to extend the one or more virtual networks to the virtual machines and to seamlessly transport packets over the switch fabric using an overlay network. In other words, the HNAs provide hardware-based, seamless access interfaces to overlay technologies used for communicating packet flows through the core switching network of the data center. |
| US09485190B2 |
Allocating shaping resources for a cloud computing environment based on transfer speeds associated with the shaping resources
A device stores shaping resource information in a data structure, where the shaping resource information includes identifiers associated with shaping resources of the device, information indicating whether the shaping resources are available, and information indicating transfer speeds associated with the shaping resources. The device defines a group of available shaping resources based on the shaping resource information stored in the data structure, and receives a packet requesting a particular transfer speed associated with transmitting the packet. The device performs a search of the group of available shaping resources based on the particular transfer speed requested by the packet, and identifies, based on the search, a list of one or more available shaping resources with transfer speeds that match the particular transfer speed requested by the packet. The device transmits the packet toward a destination via one of the one or more available shaping resources provided in the list. |
| US09485186B2 |
Network congestion control with awareness of random packet losses
Messages are sent from a first network device to a second network device across a network. The network includes a network portion with an expected random packet loss rate. The actual packet loss rate for packets sent across the network is compared to the expected random packet loss rate. A determination is made that the actual packet loss rate is greater than the expected random packet loss rate. Compensation for network congestion is performed in response to the determination that the actual packet loss rate exceeds the expected random packet loss rate. |
| US09485185B2 |
Adjusting connection validating control signals in response to changes in network traffic
Some embodiments provide a method for reducing the transmission of connection validating control signals when they are not needed. Network entities transmit connection validating control signals over network connections at regular intervals to validate that the network connections and the network entities remain functional. The method monitors data traffic fluctuations on the network connections to determine when connection validating control signals may not be needed. The method reduces unnecessary connection validating control signals in order to optimize the usage of network resources. |
| US09485184B2 |
Congestion control for delay sensitive applications
In various embodiments, methods and systems are disclosed for a hybrid rate plus window based congestion protocol that controls the rate of packet transmission into the network and provides low queuing delay, practically zero packet loss, fair allocation of network resources amongst multiple flows, and full link utilization. In one embodiment, a congestion window may be used to control the maximum number of outstanding bits, a transmission rate may be used to control the rate of packets entering the network (packet pacing), a queuing delay based rate update may be used to control queuing delay within tolerated bounds and minimize packet loss, and aggressive ramp-up/graceful back-off may be used to fully utilize the link capacity and additive-increase, multiplicative-decrease (AIMD) rate control may be used to provide fairness amongst multiple flows. |
| US09485180B2 |
Loop free alternate selection for multi-homed networks
In one example, a network device determines a set of candidate loop-free alternate (LFA) next hops for forwarding network traffic from the network device to a multi-homed network by taking into account a first cost associated with a second path from a first border router to the multi-homed network and a second cost associated with a second border router to the multi-homed network, wherein the multi-homed network is external to an interior routing domain in which the network device is located. The network device selects an LFA next hop from the set of candidate LFA next hops, to be stored as an alternate next hop for forwarding network traffic to the multi-homed network, and updates forwarding information stored by the network device to install the selected LFA next hop as the alternate next hop for forwarding network traffic from the network device to the multi-horned network. |
| US09485179B2 |
Apparatus and method for scalable and flexible table search in a network switch
A network switch comprises a packet processing pipeline including a plurality of packet processing clusters configured to process a received packet through multiple packet processing stages based on table search/lookup results. The network switch further includes a plurality of search logic units each corresponding one of the plurality of packet processing clusters, wherein each of the search logic units is configured to convert a unified search request of a table from its corresponding packet processing cluster to a plurality table search commands specific to one or more memory clusters that maintain the table, provide the plurality table search commands specific to the memory clusters in parallel and collect and provide the table search results from the memory clusters to the corresponding packet processing cluster. The network switch further includes said one or more memory clusters configured to maintain the table to be searched, search the table in parallel according to the plurality table search commands from the search logic unit, and process and provide the table search results to the search logic unit. |
| US09485177B2 |
Client applications communicating via a user tunnel
Methods, systems, and apparatuses are provided for managing communication of data to/from a device. For example, multiple client applications running on the device can communicate to a second device through a same primary socket connection. A mux module can receive data from two different client applications over respective client connections. The received data can include header information identifying the second device as the destination. When the first data from a first client application is received at the mux module, the primary socket connection can be created; and when the second data from a second client application is received, the existing primary socket connection can be identified and re-used. The primary socket connection can be managed by a controller of the mux module. |
| US09485175B2 |
Continuity check protocol optimization systems and methods
A Continuity Check (CC) protocol optimization method in a switch includes operating a plurality of CC sessions with a peer switch, wherein, for CC intervals, N sessions of the plurality CC sessions are set to a short interval and M sessions of the plurality of CC sessions are set to a long interval, wherein N and M are integers; switching a first session of the N sessions with a second session of the M sessions based on one of a fault and user provisioning; and exchanging the CC intervals between the first session and the second session subsequent to the switching. |
| US09485165B2 |
Method and apparatus for augmenting TWAMP
According to another embodiment of the invention, TWAMP path discovery is performed to determine a sequence of IP addresses of a forward direction TWAMP E2E path to be traversed by two different TWAMP test sessions between a Sender and a Reflector. Then, additional TWAMP test request packets are transmitted for the different TWAMP test sessions; and TWAMP test reply messages are received responsive to respective ones of the TWAMP test request packets. Responsive to the TWAMP test reply messages, a PM is determined that is specific to the different sequences of IP addresses of the forward direction TWAMP E2E paths traversed by the two different TWAMP test sessions. |
| US09485164B2 |
System and method for ensuring subscriber fairness using outlier detection
Various embodiments of the present invention relating to a subscriber fairness solution are disclosed. The subscriber fairness solution contemplates a variety of improved techniques for using a flow-based statistical collection mechanism to monitor subscriber usage across various attributes (e.g., subscriber byte count, flow count, etc.) and maintain subscriber usage information for different time frames. In embodiments, the subscriber fairness solution includes a detection phase and a mitigation phase. In the detection phase, “outliers,” or subscribers who are using more than their fair share of network resources, are identified. In the mitigation phase, appropriate action is taken to resolve the constraints on the network resources, caused by these outliers. The subscriber fairness solution may be embodied in hardware, software, or a composite approach of both hardware and software. |
| US09485163B1 |
Preventing split-brain scenario in a high-availability cluster
As disclosed herein a method, executed by a computer, includes determining, by a processor, that a first node of a HA cluster is unable to communicate with a second node of the HA cluster, and initiating, by a processor, by the first node, a handshake operation with a connected client, wherein the handshake operation comprises requesting that the client determine a status of the second node and receiving, from the client, a response indicating the status of the second node. The method further includes accepting, by a processor, new requests in response to determining that the second node is unavailable, and requesting, by a processor, restoration of communications between the first node and the second node in response to determining that the second node is available. A computer system and computer program product corresponding to the above method are also disclosed herein. |
| US09485162B2 |
Method and system for measuring frame loss ratio
The disclosure provides a method for measuring a frame loss ratio. A first end acquires a frame number of a received current measurement reply frame and a frame number of a received previous measurement reply frame, and judges whether the difference between the frame number of the current measurement reply frame and the frame number of the previous measurement reply frame is 1; if the difference is 1, the first end calculates the frame loss ratio according to count information carried in the current measurement reply frame and the previous measurement reply frame; and if the difference is greater than 1, the first end calculates the frame loss ratio according to the count information carried in the current measurement reply frame and the previous measurement reply frame and the difference. |
| US09485160B1 |
System for optimization of input/output from a storage array
A system and method for optimizing the performance of one or more disks in a storage array in response to access requests by other computer devices and processes across a network. For requests to access to the storage disk from the network, such as a read/write request, a response monitor notes the service time for each access requests by the storage disk, and if the performance in handling the access requests fails to meet, at least, a predetermined time threshold, actions can be taken to migrate data, modify accesses permitted to the disk, or otherwise indicate underperformance. |
| US09485157B2 |
Synchronized routing updates for TSCH networks
In one embodiment, a network node provides a time slotted channel hopping (TSCH) schedule to one or more child nodes of the network node. The TSCH schedule includes one or more mandatory routing protocol report time slots. The network node receives routing protocol reports from the one or more child nodes according to the TSCH schedule. The network node aggregates the received routing protocol reports into an aggregated routing protocol report. The network node provides the aggregated routing protocol report to a parent of the network node during a time slot that is subsequent to the one or more mandatory time slots for the one or more child nodes. |
| US09485156B2 |
Method and system for generic application liveliness monitoring for business resiliency
A system and method for monitoring liveliness includes a management device which has an application layer where applications are executed. A connection monitor is located other than on the application layer, and the connection monitor is configured to receive requests from clients and deliver the requests to components on the application layer. The components include a generic application monitor which responds to liveliness monitor requests from the clients for all applications monitored, and one or more applications which response to requests to that application. |
| US09485153B2 |
Dynamic network-driven application packet resizing
In one embodiment, information relating to network metrics in a computer network is collected. A packet delay for a packet to be transmitted along a particular communication path is predicted based on the network metrics. Then, an optimal packet size for optimizing a transmission experience of the packet to be transmitted along the particular communication path is calculated based on the predicted packet delay. Also, a size of the packet to be transmitted along the particular communication path is dynamically adjusted based on the calculated optimal packet size. |
| US09485151B2 |
Centralized system management on endpoints of a distributed data processing system
A method is described for performing system management operations on at least one target endpoint data processing apparatus of a distributed data processing system including a system management server adapted to the centralized system management of the endpoints of the distributed data processing system. The method comprises: at the system management server, receiving a system management activities plan including at least one system management activity to be performed on the at least one target endpoint; having the system management server executing the system management activities plan, wherein the executing the plan includes performing the at least one system management activity. Prior to executing the corresponding system management activity, having the system management server cause the execution, on the at least one target endpoint, of a simulated system management activity corresponding to and adapted to simulate the at least one system management activity in the plan so as to ascertain a capability of the at least one target endpoint of successfully executing the system management activity on the at least one target endpoint; and having the system management server execute the system management activity conditionally to a result of the execution of the simulated system management activity. Preferably, a selected corrective activity may be performed to remove the cause of the negative result of the simulated system management activity. |
| US09485150B2 |
Fast reroute for segment routing traffic
An apparatus and method are disclosed for fast reroute (FRR) for native segment routing (SR) traffic. In one embodiment, a node receives a packet that includes a segment routing (SR) segment identifier (ID) stack. The node determines what type of segment is designated as the active segment in the segment ID stack. Based, at least in part on the type of active segment, the node selects an update routine out of several possible update routines and performs the selected update routine. The update routine modifies the segment ID stack. |
| US09485148B2 |
Fabric formation for virtual cluster switching
One embodiment of the present invention provides a switch system. The switch includes a port to couple to a second switch and a control mechanism configured. During operation, the control mechanism receives from the second switch a set of configuration information. Based on the received configuration information, the control mechanism invites the second switch to join a virtual cluster switch. |
| US09485147B2 |
Method and device thereof for automatically finding and configuring virtual network
A virtual network auto-discovery and auto-configuration method and device thereof are provided. The method includes a tenant end system automatically discovering network virtualization edges (NVEs), the NVE initiating a VN identity authentication of the tenant end system, and the NVE automatically configuring a VN forwarding table of the VN after the tenant end system passes the VN identity authentication. The method and device solve the technical problem that virtual network configuration efficiency is low due to manually configuring the virtual network, and achieve the technical effect of improving the virtual network configuration efficiency. |
| US09485143B1 |
Redundancy of network services in restricted networks
Methods, systems, and devices are described for managing virtual network services provided to a network. Network services may be provided to a client network having a first network fabric at a self-contained network services system implementing a number of redundant instances of a network service application. The self-contained network services system may have a second network fabric. The second network fabric may be adapted to distribute network service tasks received from the client network which are associated with the network service application among the redundant instances of the network service application. |
| US09485139B2 |
Communication node, communication system, and method for performing a communication
A communication node includes a transmission and receipt setting part configured to perform a transmission setting or a receipt setting for each information based on a transmission request or a receipt request included in a transmission and receipt request information corresponding to a second communication node detected by a communication node detector among the transmission and receipt request information stored in a memory part, a communication part configured to transmit information representing the transmission setting or the receipt setting set by the transmission and receipt setting part and to receive information representing the transmission setting or the receipt setting from another first communication node, and a consistency determining part configured to determine consistency of the transmission setting or the receipt setting set by the transmission and receipt setting part and the transmission setting or the receipt setting received by the communication part from another first communication node. |
| US09485130B2 |
Universal OFDM synchronizer for power line communication
A universal OFDM synchronizer for power line communication is provided. The universal OFDM synchronizer can be used for all known OFDM standards and allows maximum flexibility with best performance. The OFDM synchronizer comprises of a preamble averaging, a correlator and a peak discriminator. The OFDM synchronizer can be used with signals having 256 sample size preamble or 512 sample size preamble. |
| US09485126B2 |
Signal combining system for constant envelope transmission of information
A method and apparatus for producing a transmission of constant envelope on a carrier signal. All possible combinations of all component codes for phases for producing the transmission are defined. Desired component code powers and desired intercode phases between all pairs of component codes are also defined. Still further, a portion of variables of a search process to reduce a number of variables searched by the search process is defined. Even further, deltas and weight variations for standard differences in a Jacobian matrix for use in the search process are defined. Penalty factors to evaluate an objective function of the search process are also defined. The search process is performed. |
| US09485119B1 |
Offset correction for sense amplifier
The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well. |
| US09485116B2 |
Cellular phone line replacement adapter
An apparatus and system automatically process and route data messages or packets, via a cellular network, from analog or digital data devices, wherein the routing is accomplished without a need for voice call origination on the cellular network. The apparatus includes a fixed cellular communication device and may also include a fixed wireless RF communication device and/or a mobile wireless RF transceiver. The fixed cellular communication device formats and transmits, on a cellular network, data packets received from data devices directly connected to the fixed cellular communication device and/or data packets received wirelessly from the fixed wireless RF communication device and/or from the mobile wireless RF transceiver. The fixed cellular communication device has a physical form of an AC wall adapter. |
| US09485114B2 |
MAC abstraction sub-layer and MAC table for a communication system and related communication device
A method of converging a plurality of communication standards is disclosed. The method comprises providing a medium access control (MAC) abstraction sub-layer, wherein the MAC abstraction sub-layer is arranged between an upper layer and a plurality of MAC layers of the plurality of communication standards; and providing a corresponding service management entity (SME) between the MAC abstraction sub-layer and the plurality of MAC layers and a plurality of physical (PHY) layers of the plurality of communication standards in a control plane; wherein the MAC abstraction sub-layer communicates with the plurality of MAC layers and the plurality of PHY layers in the control plane via the corresponding SME, and the corresponding SME communicates with the MAC abstraction sub-layer via an application programming interface (API). |
| US09485111B2 |
Monitoring system
In a monitoring system, a master device stores setting information indicating a predetermined state for detecting a target by using a sensor in a storage unit, and transmits the setting information to a camera (a baby monitoring camera or a monitoring camera) having a sensor built thereinto or correlated with a sensor so as to set a detection parameter therein. When the predetermined state set by the detection parameter is detected, the camera transmits a detection notification to the master device. When the detection notification is received from the camera, the master device transmits detection notification information to a smartphone, and the smartphone displays a detection information screen based on the detection notification information transmitted from the master device on a display/input unit. |
| US09485108B2 |
System and apparatus for using multichannel file delivery over unidirectional transport (“FLUTE”) protocol for delivering different classes of files in a broadcast network
Embodiments provide bandwidth efficient mechanisms for delivering data to a receiver device via a wireless broadcast network such that data may be assembled in the receiver device for use by a local application. In the various embodiments, data files may be broadcast as content elements via the broadcast network using the FLUTE protocol during a FLUTE session. In an embodiment, the content elements may be broadcast according to a broadcast schedule that may identify a time at which the content elements will be broadcast and the broadcast schedule may be communicated in a file delivery table (FDT) transmitted during a FLUTE session. |
| US09485106B2 |
Method for processing TDF session and PCRF
A method for processing Traffic Detection Function (TDF) session and a Policy and Charging Rules Function (PCRF) are provided. The method includes: the PCRF links a first TDF session related with a proxy mobile Internet Protocol version 4 (IPv4) address and a second TDF session related with a first proxy mobile Internet Protocol version 6 (IPv6) address to a same IP Connectivity Access Network (IP-CAN) session; when the IPv4 address of the IP-CAN session is released, the PCRF requests the TDF to terminate the first TDF session. |
| US09485105B2 |
Method and telecommunications network utilizing more than one online charging system for a given user
A method for enhanced policy and charging control when a telecommunications network is used by a User Equipment corresponding to a subscriber includes a Policy and Charging Enforcement Function and a first Online Charging System, configured to communicate via an online charging interface. The telecommunications network further includes a second Online Charging System being configured to communicate via an online charging interface. The method includes: communicating, by an interworking credit control function of the telecommunications network, relative to the subscriber of the telecommunications network and with regard to the same or overlapping traffic of the subscriber via a first online charging interface with the Policy and Charging Enforcement Function, via a second online charging interface with the first Online Charging System, and via a third online charging interface with the second Online Charging System. |
| US09485104B2 |
Information processing system
An information processing system according to the present invention includes a plurality of information processing apparatuses connected by a multihop network, and each of the information processing apparatuses includes a first communication unit configured to transmit and receive a first packet including information about a destination address and a second communication unit configured to communicate at a frequency higher than that of the first communication unit and transmit and receive a second packet including a payload, and in each of the information processing apparatuses, when the first communication unit receives the first packet, the second communication unit is woken up, so that efficient data transfer can be achieved while the power consumption is saved. |
| US09485101B2 |
Provisioning digital certificates in a network environment
A method for provisioning digital certificates in a compute service environment may include authorizing a customer entity for using and/or controlling a network resource in the compute service environment. Upon completing the authorization, a digital certificate may be issued to the customer entity. The digital certificate may be associated with the network resource and may be issued for a limited duration period. The use and/or control of the network resource by the customer entity may be monitored. Reissuance of the digital certificate may be conditioned on whether the customer entity is still using and/or controlling the network resource in the compute service environment. If the customer entity is still using and/or controlling the network resource in the multi-tenant environment, the digital certificate may be automatically reissued for another limited duration period. The automatically reissuing may take place without receiving a certificate reissue request from the customer entity. |
| US09485094B1 |
Systems and methods for stable physically unclonable functions
Various embodiments of the invention allow to take advantage of the natural statistical variation of physical properties in a semiconductor device in order to create truly random, repeatable, and hard to detect cryptographic bits. In certain embodiments, this is accomplished by pairing mismatch values of PUF elements so as to ensure that PUF key bits generated thereform remain insensitive to environmental errors, without affecting the utilization rate of available PUF elements. |
| US09485089B2 |
Stego key management
Systems, methods, devices and computer program products are provided that improve stego key management of watermarking systems and reduce the impact of leaked secrets related to watermark embedding and extraction operations. In the event that a watermark extractor is compromised and its extraction stego key is revealed, new extraction stego key sets are generated and assigned to a particular group of devices with similar security features. The new extraction stego key sets have significant overlap with one another, and can be retired once a device within the particular group of devices is compromised. The described techniques are complementary to other security enhancement practices, such as obfuscation and tamper resistant techniques, to strengthen the security of a watermarking system. |
| US09485088B2 |
Systems and methods for dynamic data masking
Systems and methods for dynamic data masking are disclosed. The disclosed methods and systems can be used to dynamically mask data in cryptographic operations, such as advanced encryption standard (AES) operations, data encryption standard (DES) operations or triple DES operations. Specifically, data in cryptographic operations can be covered with unlimited and continuously changing masks. As an example, the Substitution table, key schedule, and state register in AES, or key schedule and selection functions in a DES or triple DES can be covered with unlimited and constantly changing masks. In an aspect, dynamic masking operations can be combined with orbital RAM algorithm and no-operation clocks to make power signature analysis in cryptographic attacks even more difficult. |
| US09485083B2 |
Method and apparatus for time synchronization between nodes
A method and apparatus for time synchronization between a plurality of nodes in a network. The apparatus distinguishes between an optical synchronization signal for synchronization between nodes and an optical data signal for data transmission, and synchronizes nodes with each other using the optical synchronization signal. |
| US09485082B1 |
Multi-mode phase-frequency detector for clock and data recovery
A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set. |
| US09485081B2 |
Apparatus for compensating for skew between data signals and clock signal
An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal. |
| US09485079B2 |
Frequency division
A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal. |
| US09485071B2 |
Method and apparatus for allocating a control channel resource of a relay node in a backhaul subframe
A method and apparatus for configuring a control channel between a first transceiver and a second transceiver in a communication system are provided. The method includes generating, by the first transceiver, a signaling message including information for the control channel; transmitting, by the first transceiver, the signaling message including information for the control channel to the second transceiver; generating, by the first transceiver, the control channel based on the information for the control channel; and transmitting, by the first transceiver, the generated control channel to the second transceiver, wherein the information for the control channel includes resource assignment information, and information regarding that if interleaving is applied. |
| US09485070B2 |
Method and apparatus for transmitting and receiving different signal types in communication systems
A method and apparatus are provided for transmitting a Reference Signal (RS) by a User Equipment (UE) in a wireless communication system. The method includes transmitting a DeModulation Reference Signal (DM RS) and information data in a sub-frame; and transmitting a Sounding Reference Signal (SRS) in a last symbol in another sub-frame. The DM RS is transmitted in a middle symbol in each slot of the sub-frame, and the information data is transmitted in other symbols in each slot of the sub-frame. |
| US09485069B2 |
Transmission and reception of proximity detection signal for peer discovery
Techniques for performing peer discovery to enable peer-to-peer (P2P) communication are disclosed. In an aspect, a proximity detection signal used for peer discovery may be generated based on one or more physical channels and/or signals used in a wireless network. In one design, a user equipment (UE) may generate a proximity detection signal occupying at least one resource block based on a SC-FDMA modulation technique. In another design, the UE may generate a proximity detection signal occupying at least one resource block based on an OFDMA modulation technique. The UE may generate SC-FDMA symbols or OFDMA symbols in different manners for different physical channels. In yet another design, the UE may generate a proximity detection signal including a primary synchronization signal and a secondary synchronization signal. For all designs, the UE may transmit the proximity detection signal to indicate its presence and to enable other UEs to detect the UE. |
| US09485065B2 |
Method and base station for transmitting downstream link data, and method and user device for receiving downstream link data
The present invention relates to a method and apparatus which transmit/receive at least one demodulation reference signal by using a CDM group and/or a transmission rank of a user device that have been used to transmit the at least one demodulation reference signal for the user device, an OCC that has been used to spread the demodulation reference signal, etc. Also, the present invention relates to a method and apparatus which change an antenna port for transmitting the demodulation reference signal by using NDI for a disabled transmission block. |
| US09485059B2 |
Protocol synchronization for HARQ background
A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant. |
| US09485054B2 |
Transmission device, reception device and communication system
A video image data encoder comprises an input to receive stereoscopic image data. The stereoscopic image data includes first and second image data having chronological correspondence. An error correction encoding unit combines portions of the first image data and corresponding portions of the second image data from the input unit into a common encoding matrix. An error correcting code derived from the combined portions is added to the encoding matrix. |
| US09485048B2 |
Methods and devices for space-time multi-plane optical networks
Scalability and energy efficiency are key issues in data centers imposing tight constraints on the networking infrastructure connecting the servers. Optical interconnection mitigates electronic limitations but the additional flexibility offered by WDM and datarate across a data center interconnection network requires architectural design, photonic technologies, and operating strategies be selected and optimized to meet power consumption requirements. Multi-plane architectures based upon space-wavelength domain architectures have been proposed to overcome scalability limitations. It would be beneficial to extend space and time switching domains with the wavelength domain for additional capacity to increase throughput as well as providing same electro-optic interface. Accordingly, the inventors have established space-time domain interconnection network architectures with wavelength domain overlay overcoming power consumption issues, especially at low utilization, by exploiting all-optical implementations with active elements which act simultaneously as a switch and an amplifier, and the possibility to remain in an idle state when unused. |
| US09485039B1 |
Calibration and tracking of receiver
Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array. |
| US09485037B1 |
Compact dual-channel transceivers
In one embodiment, a dual-channel transceiver includes two harmonic repeaters each having a receive antenna, a transmit antenna, and a frequency multiplier connected to the antennas that is configured to increase the frequency of a signal received by the receive antenna to enable transmission by the transmit antenna of a reply signal having a higher frequency, wherein the harmonic repeaters operate at different frequencies from each other. |
| US09485036B2 |
RF receiver with testing capability
An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion. |
| US09485033B2 |
Signal processing apparatus and signal processing method
Signal processing means includes carrier compensation means for compensating for a phase difference and a frequency difference between signal light and local light in relation to two polarization signals, so as to generate two carrier compensated signals, symbol determination means for demodulating the two carrier compensated signals on the basis of a signal arrangement of multi-value modulation, symbol rough-determination means for demodulating the two carrier compensated signals on the basis of a signal arrangement in which the number of multi-values of the multi-value modulation is reduced, selection means for selecting either of an output of the symbol determination means and an output of the symbol rough-determination means, and coefficient setting means for updating filter coefficients of polarized wave separation means by using an output selected by the selection means. |
| US09485032B2 |
Optical multilevel transmitter and optical transponder
An optical multilevel transmitter includes a semiconductor quadrature optical modulator configured to separately modulate and output in-phase and quadrature electric field components and a semiconductor nonlinear characteristic compensation circuit configured to generate, from in-phase and quadrature drive signals to be inputted to the semiconductor quadrature optical modulator, two signals for correcting each other and to add the two correcting signals to the corresponding drive signals. |
| US09485031B2 |
Optical PAM modulation with dual drive mach zehnder modulators and low complexity electrical signaling
The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. In various embodiments, amplitude and phase of the optical wave are modulated. There are other embodiments as well. |
| US09485028B2 |
Modulator for optical transmitter
An optical transmitter has a modulator for modulating data onto an optical signal for transmission to the receiver, the modulated signal having components at one or more constellations of points of different amplitudes and phases. The modulator is tunable such that distortions of the points of the one or more constellation can be tuned, and a tuning controller is provided for receiving a feedback signal from the receiver indicating a distortion measured at the receiver, and for tuning automatically the modulator to adjust the modulation based on the received feedback signal to pre-compensate for the measured distortion. Such pre-compensation can reduce the amount of distortion in the transmission system and thus enable more transmission capacity, without the need for a complex transmitter. |
| US09485026B2 |
Scheme for remote control of the wavelength of a tunable transmitter in a smart transceiver
A scheme is described for remote control of the wavelength of a tunable transmitter in a smart small form-factor pluggable (SFP) transceiver, a smart SFP plus (SFP+) transceiver, a smart 10 gigabit small form-factor pluggable (XFP) transceiver, a smart duplex transceiver, a smart bidirectional (BiDi) transceiver, or a smart single wavelength single fiber (SWSF) BiDi-transceiver in a communication system using an operating system with Operation, Administration, and Maintenance (OAM) and Proprietary Protocol (PP) functions; an OAM, PP & Payload Processor; a transceiver; an optical spectrum analyzer; a bit error rate test (BERT); and an optical link in the field. |
| US09485023B2 |
Communication system, main unit, radio access unit and communication method
A plurality of radio access units form the single cell of a first communication system, while forming respective individual multi-cells of a second communication system within the single cell. The plurality of radio access units transmit a downstream signal of the first communication system input from a main unit to a terminal using the first communication system of the single cell, while each transmitting a downstream signal of the second communication input from the main unit to a terminal using the communication system of the corresponding respective one of the multi-cells. |
| US09485019B1 |
Methods and systems for optical channel monitoring with periodic optical filtering of dual polarization signals
Methods and systems for optical channel monitoring of dual polarization optical signals may use a periodic optical filter to scan a free spectral range of the periodic optical filter. The optical signals may further be tone modulated using frequency or amplitude modulation. From a filtered signal, normalized Stokes vector signals may be generated using a polarimeter. The normalized Stokes vector signals may be digitally processed to identify center frequencies and power levels of individual optical subcarriers. |
| US09485018B2 |
Optical source monitoring system
An example embodiment includes an optical transmission device. The optical transmission device includes an optical source, a collimator lens, and an optical monitor. The optical source is configured to transmit a channel of light. The collimator lens is configured to reflect a portion of the channel of light. The optical monitor is arranged to receive at least a first portion of the reflected channel of light directly from the collimator lens, and is configured to communicate a gross electrical signal representative of received light including the first portion of the reflected channel of light. |
| US09485010B1 |
Adaptive coding and modulation for spot beam satellite broadcast
A method and apparatus for adaptively controlling a transmission signal for transmission to at least one receiver in a terrestrial region is disclosed. The method selects a transmission signal mode having a modulation scheme, code scheme, and code rate from a plurality of transmission signal modes according to received information, generates a transmission signal according to the selected mode, and transmits the generated transmission signal to the receiver. |
| US09485005B2 |
Mobile station and radio base station
In order to prevent a mismatch between an HFN used by a PDCP layer on a transmitting side and an HFN used by a PDCP layer on a receiving side, and thereby to avoid a decrease in the throughput due to a failure in deciphering processing on PDCP-PDU in the PDCP layer on the receiving side. In a mobile station UE according to the present invention, a transmission unit 13 is configured to, if an HFN report trigger is detected, send a radio base station eNB the HFN or COUNT value most recently used in the deciphering processing on a PDCP-PDU. |
| US09484997B2 |
Determining a precoder of a codebook
A Network Node, a UE operable in a MIMO system and respective methods performed by the Network Node and UE are provided for determining a precoder of a Codebook to use for transmissions to the UE. The Network Node includes at least two transmitting antennas corresponding to two individual Ranks. The Network Node determines which precoders the UE shall evaluate, and transmits, to the UE, the determined precoders the UE shall evaluate. The Network Node receives, from the UE, a PMI, associated with one of the determined precoders, which the UE requests the Network Node to use for transmission to the UE; and the Network Node transmits, to the UE, data using the requested precoders. |
| US09484996B2 |
Receiver device, transmitter device, reception method, and transmission method
Provided is a receiver device that can switch between transmission methods, while minimizing increase in the number of blind decryption iterations and the amount of signaling needed for acknowledgement. In this device, a receiver part (201) receives a signal mapped to any of a plurality of mapping candidates; and according to application levels established for each of the plurality of mapping candidates, a control signal processor (205) performs blind decryption of the plurality of mapping candidates, employing either a first transmission method using a single antenna port to carry out precoding based on feedback information from the receiver device, or a second transmission method involving transmission diversity employing multiple antenna ports. |
| US09484992B2 |
Method and apparatus for performing antenna virtualization using polarimetric antenna in a wireless communication system
A method and apparatus for transmitting a signal using a polarimetric antenna to a reception apparatus in a wireless communication system are disclosed. The method includes generating a first matrix using a radiation pattern of the polarimetric antenna, calculating a second matrix that maximizes channel capacity, determining an antenna virtualization matrix by Singular Value Decomposition (SVD) based on the first and second matrices, and transmitting a signal to the reception apparatus using the antenna virtualization matrix. |
| US09484986B2 |
Method and system for broadband near-field communication
A first mobile consumer electronic device comprises a broadband near-field communications (BNC) transceiver and is configured to operate as a main processing unit for a second mobile consumer electronic device that is configured as a thin-client. The first mobile consumer electronic device may capture, via the BNC transceiver, a signal over a range of frequencies that spans multiple frequency bands which are licensed by a regulatory authority. The first mobile consumer electronic device may process the captured signal to determine which of the multiple frequency bands are not currently in use by other devices. The first mobile consumer electronic device may select a plurality of the frequency bands. The first mobile consumer electronic device may transmit, via the BNC transceiver, a signal over the selected plurality of frequency bands at a determined strength, where the signal carries video data destined for the second mobile consumer electronic device. |
| US09484978B2 |
System and method for communication with adjustable signal phase and power
A communication system includes a first antenna, a second antenna, a first transceiver, a second transceiver, and a phase and power distribution transform circuit. The phase and power distribution transform circuit is coupled between the first antenna, the second antenna, the first transceiver, and the second transceiver. The phase and power distribution transform circuit is configured to adjust the phase and power of each signal from the first antenna, the second antenna, the first transceiver, and/or the second transceiver, thereby improving the communication quality of the communication system. |
| US09484976B2 |
Assembly comprising two antennas controllable to output or not output signals
An assembly, a method of operating the assembly and antennas for use in the assembly, where two or more antennas (16, 18) each is adapted to output an output signal with one of two or more characteristics, only one antenna outputting a signal with a predetermined characteristic, such as a non-zero amplitude, whereby the output signals from the antennas may simply be added/summed while enabling selection of the signal with the predetermined characteristic using e.g. a simple filter. |
| US09484974B2 |
Methods and systems for multi-layer perceptron based non-linear interference management in multi-technology communication devices
The various embodiments include methods and apparatuses for canceling nonlinear interference during concurrent communication of multi-technology wireless communication devices. Nonlinear interference may be estimated using a multilayer perceptron neural network with Hammerstein structure by dividing an aggressor signal into real and imaginary components, augmenting the components by weight factors, executing a linear combination of the augmented components, and executing a nonlinear sigmoid function for the combined components at a hidden layer of multilayer perceptron neural network to produce a hidden layer output signal. At an output layer, hidden layer output signals may be augmented by weight factors, and the augmented hidden layer output signals may be linearly combined to produce real and imaginary components of an estimated jammer signal. A linear filter function may be executed for the components of the jammer signal, and to produce a nonlinear interference estimate used to cancel the nonlinear interference of a victim signal. |
| US09484972B2 |
Reception device and electronic apparatus
There is provided a reception device including first and second reception circuits configured to receive transmission signals, a first oscillation circuit configured to generate a differential signal having a predetermined frequency on the basis of an oscillation signal acquired from a connected crystal oscillator, and to supply the generated differential signal to the first reception circuit as a reference frequency signal, and a second oscillation circuit configured to be supplied with an oscillation signal having one of phases in the differential signal acquired by the first oscillation circuit, to generate a differential signal having a predetermined frequency on the basis of the supplied oscillation signal, and to supply the generated differential signal to the second reception circuit as a reference frequency signal. |
| US09484971B2 |
Wideband beamformer system
An adaptive phased-array processing solution, referred to as the Wideband Beamformer System (WBS), demonstrates an improvement in the range and quality of air link surveillance downlink wireless cell radio signals. The WBS applies wideband frequency-domain adaptive beamforming to preprocess the dense RF signal environment, minimizing co-channel interference (CCI) from each signal, and then reconstructing a “clean” version of the signal for input to the existing surveillance receiver(s). |
| US09484970B2 |
Analog-to-digital conversion with noise injection via wavefront multiplexing techniques
A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality. |
| US09484968B2 |
Post conversion mixing
An input signal having at least one modulated signal is captured. At least four analog sample streams are generated from the input signal. Each analog sample stream is generated by sampling the input signal at a frequency substantially equal to the frequency at which each other analog sample stream is generated and at a phase separate from that at which each other analog sample stream is generated. For each analog sample stream, multiple analog samples of the analog sample stream are combined to create a bandwidth adjusted signal. The bandwidth adjusted signals are jointly representative of the input signal. |
| US09484966B2 |
Method and apparatus for sensing inter-modulation to improve radio performance in single and dual tuner
A method of performing alternate frequency switching in a radio includes tuning the radio to a primary frequency. A candidate alternate frequency is identified. It is determined whether the candidate alternate frequency is a third order inter-modulation artifact. Tuning is switched from the primary frequency to the candidate alternate frequency only if it is determined in the determining step that the candidate alternate frequency is not a third order inter-modulation artifact. |
| US09484965B2 |
Terminal and method for making touchscreen of terminal
A terminal and a method for making a touchscreen of the terminal, relate to the field of communications technologies and are invented for improving flexibility for receiving an frequency modulation (FM) broadcast. A terminal includes: a touchscreen; where the touchscreen includes a basal layer, a first conductive layer, a second conductive layer, and a touch layer, an antenna layer, and a separation layer, where the antenna layer is configured to dispose a FM antenna; the antenna layer and the separation layer are disposed between the basal layer and the first conductive layer or disposed between the second conductive layer and the touch layer, and the antenna layer is separated from the first conductive layer or the second conductive layer by using the separation layer. The embodiments of the present invention are mainly used in a terminal. |
| US09484963B2 |
Multi-mode and multi-band front-end device
A multi-mode and multi-band front-end device comprises at least one amplifier unit, at least one switching unit, at least one control unit, a plurality of transmission paths, and a plurality of frequency matching networks. The switching unit comprises at least input end and a plurality of connecting ends. Wherein the input end is electrically connected to the amplifier unit, and each of connecting ends is connected to each of transmission paths, respectively. Each of frequency matching networks is configured on each of transmission paths, and achieves impedance matching at different frequency bands, respectively. The multi-mode and multi-band front-end device is able to select one of transmission paths to transmit RF signal according to the frequency band of RF signal to be transmitted so as to improve the output power of the multi-mode and multi-band front-end device. |
| US09484962B1 |
Device and method for adaptive digital pre-distortion
One embodiment relates to a system which includes a pre-distortion unit, a power amplifier circuit, a power amplifier model, and a parameter estimation unit. The pre-distortion unit is configured to pre-distort an input signal based on a model parameter by directly computing the model inverse in an iterative fashion, thereby providing a pre-distorted signal. The power amplifier circuit is configured to amplify the pre-distorted signal. The power amplifier model is configured to model amplification of the pre-distorted signal by the power amplifier circuit based on the pre-distorted signal and the model parameter. Based on the pre-distorted signal and an error signal, the parameter estimation unit is configured to update the model parameter provided to the pre-distortion unit and the power amplifier model. The error signal represents a difference between an output signal from the power amplifier circuit and a modeled output signal from the power amplifier model. |
| US09484959B2 |
Error correction encoding method and error correction encoding device
An error correction encoding device 1 includes a sparse matrix computing unit 2 that computes exclusive OR of a submatrix, in a parity-check matrix, corresponding to an information bit sequence, and the information bit sequence on the basis of the position of 1 in the submatrix to calculate a vector, a fundamental matrix operator 3 that calculates a predetermined matrix by performing a predetermined fundamental matrix operation on a submatrix, in the parity-check matrix, corresponding to a parity bit sequence, and a matrix multiplier 4 that calculates the parity bit sequence by multiplying the predetermined matrix which the fundamental matrix operator 3 calculates, and the vector which the sparse matrix computing unit 2 calculates. |
| US09484951B2 |
Encoder that optimizes bit allocation for information sub-parts
A digital information encoder including a divider configured to divide a block of information into a plurality of sub-parts, an initial bit allocator configured to perform an initial allocation of bits to a KTH sub-part of said plurality of sub-parts, a processor configured to compute an estimated number of bits for encoding said KTH sub-part, and a bit allocation adjuster configured to obtain an adjusted bit allocation for said KTH sub-part by adjusting said initial allocation of bits to said KTH sub-part based, at least in part, on said estimated number of bits, wherein the encoder encodes said KTH sub-part using said adjusted bit allocation for said KTH sub-part. |
| US09484942B1 |
Oscilloscope with logic analyzer frontend
An electronic test apparatus, such as an oscilloscope, comprising a logic analyzer frontend, wherein the logic analyzer frontend comprises a digital input port configured to receive a digital signal from a device under test. The logic analyzer frontend further comprises at least one analog-to-digital converter that is arranged downstream of the digital input port, and a digital comparator that is arranged downstream of the analog-to-digital converter. The digital comparator is configured to generate an adjusted digital signal and to provide the adjusted digital signal to further components of the electronic test apparatus. The logic analyzer frontend further comprises a digital correction unit configured to adjust a digital decision threshold value of the comparator. |
| US09484941B2 |
Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal. |
| US09484932B2 |
Signal generation circuit and electronic apparatus
A signal generation circuit includes a phase difference detector configured to detect a phase difference between a certain oscillation signal of a plurality of oscillation signals and a predetermined reference signal; an oscillator to which a plurality of delay elements are connected annularly, the oscillator being configured to generate the plurality of oscillation signals depending on the detected phase difference; a low-speed signal generation circuit configured to generate a low-speed signal having a lower frequency than the oscillation signal; a detection circuit configured to detect a difference between a predetermined reference timing and a timing at which the low-speed signal has changed; a selection unit configured to select the oscillation signal so that the phase difference with respect to the reference signal is close to the detected difference; and an output unit configured to output the generated low-speed signal in synchronization with the selected oscillation signal. |
| US09484928B2 |
Oscillator, electronic apparatus, and moving object
An oscillator includes: an integrated circuit including a circuit for oscillation; a resonator element; a circuit element; a heating element, and a container. The integrated circuit, the resonator element, and the heating element are arranged inside the container. The circuit element is arranged outside the container. |
| US09484923B2 |
Signal transmission circuit suitable for DDR
A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage. |
| US09484918B1 |
Dual edge pulse de-multiplexer with equalized path delay
A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer. |
| US09484915B2 |
Non-contact proximity switch for machine safety
A non-contact proximity switch having a first part and a second part which do not need to be in physical contact to detect proximity of the first and second parts. The first part is arranged to be connected to a reset circuit including an indicator light and a reset switch having a reset button. The first part includes a reset mechanism for machine safety, and the reset mechanism includes a signal generator and a signal detector. The reset mechanism is arranged to, upon indication that a reset is required, generate a signal so as to switch-on said indicator light, and the reset mechanism is further arranged to detect when the state of a connected reset switch corresponds to a state where the reset button is being pressed. |
| US09484914B2 |
Anti-trapping method and apparatus for an adjustable vehicle door
An anti-trapping method and a corresponding apparatus for a vehicle door that can be adjusted between an open position and a closed position along an adjustment path by an adjustment motor. First, a proximity sensor is used to monitor an adjustment path region ahead of the vehicle door for the presence of an obstacle during a closing movement of the vehicle door. The closing movement is stopped or reversed when an obstacle is identified in the adjustment path region. Second, when the obstacle is identified during the closing movement of the vehicle door, an additional emergency measure is taken at least when the vehicle door is already closed down to a remaining gap having size does not exceed a prespecified threshold value, and when the presence of the obstacle within this remaining gap is detected. |
| US09484913B2 |
Emulation of LED input characteristics in BICMOS process
An LED input emulator to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED forward and reverse bias voltages. VR reverse blocking circuitry includes MP1 and MP2 PMOS transistors coupled to an emulator anode port, and to emulate LED reverse bias voltage. VF control circuitry includes a variable resistance (MP3) coupled between anode and cathode ports, and a current control circuit coupled to an output node, and to control current through the variable resistance to maintain a desired forward voltage at the output node. In an example embodiment, the VF control circuitry is implemented with an amplifier and a bandgap voltage reference circuit coupled to the output node, generating both reference and feedback voltages input to the amplifier to control the variable resistance. |
| US09484912B2 |
Resistance element generator and output driver using the same
A resistance element generator includes a reference current generation unit suitable for receiving a source reference current to generate first and second reference currents, a first resistance generation unit suitable for generating a first resistance value by using a first reference voltage and the first reference current, and outputting a first voltage corresponding to the formed first resistance value, and a second resistance generation unit suitable for generating a second resistance value by using a third reference voltage and the second reference current, and outputting a second voltage corresponding to the formed second resistance value. |
| US09484910B2 |
Zero-current POR circuit
A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor through the RC circuit. When a voltage of the capacitor reaches a first threshold, the Schmitt trigger reverses, a first level is output. The POR circuit includes a discharge circuit used to detect a glitch of the power supply voltage, and output a first signal to an input end of the Schmitt trigger when the glitch is detected. The first signal allows the Schmitt trigger to reverse again to output a second level, so as to turn off the first PMOS tube through the inverting amplifier. When the power supply voltage rises along an oblique line again, the Schmitt trigger reverses, and the first level is output, so as to reset the system where the circuit is. |
| US09484908B1 |
Gate drive circuit
A driver circuit has a gate drive terminal that produces a gate drive signal to control paralleled power semiconductor switches, such as GaN high electron mobility transistor (HEMT) devices. One of the switches is closest to the gate drive terminal such that its gate drive loop inductance is smaller than the remaining switches that are farther away having a larger loop inductance. An additional resistor or gate-source capacitor is provided in the gate drive circuit of the closest switch which increases the total gate resistance of the closest switch compared to the remaining switches, which delays the turn off time of the closest switch. The delay permits zero voltage switching turn-off of the remaining switches to reduce noise. The closest switch is hard switched off but has the smallest loop inductance, which allows optimized turn off. |
| US09484906B2 |
Apparatus and methods of N-type load switch using bootstrap gate drive for wireless power receiver
Apparatus and methods are provided to power an N-type load switch using a bootstrap capacitor. In one embodiment, an integrated circuit for a wireless power receiver comprises a first rectifier input terminal (RX1), a second rectifier input terminal (RX2), a first bootstrap terminal (HSB1), a second bootstrap terminal (HSB2), and a load switch terminal (LSW). A first and a second bootstrap circuit are coupled with HSB1 and HSB2 to power the rectifier in a regular mode. A load switch driver circuit is coupled between LSW and either HSB1 or HSB2. In the regular mode the load switch driver circuit powers a load switch through a corresponding bootstrap circuit. In an output shutdown mode, an output shutdown circuit is turned on to turn off the load switch. In one embodiment, the load switch is external to the integrated circuit. In another embodiment, the load switch is internal to the integrated circuit. |
| US09484904B2 |
Gate boosting transmission gate
A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold. |
| US09484901B1 |
Interpolation circuitry and methods
Circuitry for interpolating a value based on a first plurality of samples from within a larger second plurality of samples includes storage for the second plurality of samples, including a plurality of sample memories corresponding in number to the first plurality of samples. Adjacent samples in the sample memories correspond to samples in the second plurality of samples that are separated by other samples numbering one less than that number. A first sample address into a first one of the sample memories is derived by dividing a floor of an index by the number. Respective circuitry for each respective other one of the sample memories derives a respective other sample address from the first sample address based on a remainder of dividing the floor of the index by the number. Shifting circuitry outputs selected samples in a second order under control of a value determined by the remainder. |
| US09484898B2 |
System for generating an analogue signal
The system has: a set of at least two electric current generators, at least one capacitor and activation/deactivation devices for the electric current generators; the electric current generator being connected in parallel with one another and the capacitor being connected in series with the electric current generators, the activation/deactivation devices controlling the generators by a digital stream allowing control of the intensity of the electric current entering the capacitor and generating a trapezoidal voltage signal at the terminals of the capacitor, the analog signal being reconstructed through interpolation of the trapezoidal signal. |
| US09484890B1 |
Systems and methods to reduce quadrature error in sensors
Various embodiments of the invention provide for improved performance by reducing a quadrature error signal. In certain embodiments, this is accomplished by using a mixed-signal architecture comprising analog and digital circuit components in a closed-loop configuration that generates from a detected quadrature error signal a calibration quadrature signal that is then compensated at a virtual ground of an analog front end circuit. Some embodiments allow for pre-calibration for quadrature error and/or adaptive compensation of unwanted drift effects of the quadrature error, including temperature drifts. |
| US09484889B2 |
Delay fabric apparatus and delay line
A fabric for delaying digital signals in continuous time has an array of node filters. Inputs of filters in the first column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form an output signal of the filter. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other rows of the array. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements. A delay line is constructed by combining a phase generator and a fabric, where the phase generator splits a digital input signal in multiple incrementally delayed versions for the fabric inputs. |
| US09484888B2 |
Linear resistor with high resolution and bandwidth
Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower. |
| US09484886B2 |
Surface acoustic wave device and composite module including same
A surface acoustic wave device includes a piezoelectric substrate including an interdigital transducer located on one principal surface thereof, an insulating layer arranged around the interdigital transducer, a cover layer arranged over the insulating layer and the interdigital transducer, and a columnar electrode penetrating through the insulating layer and the cover layer, and connected to the interdigital transducer through a connection wiring, wherein a buffer layer is arranged on the other principal surface of the piezoelectric substrate. |
| US09484877B2 |
Resonating device with single operational amplifier
A resonating device includes: an amplifying circuit having a first input terminal, and an output terminal for outputting an output signal; a first feedback circuit coupled between the first input terminal and the output terminal of the amplifying circuit; a second feedback circuit, coupled between the first input terminal and the output terminal of the amplifying circuit; and a gain adjusting circuit, having an input terminal for receiving an input signal, and a first output terminal coupled to the first input terminal of the amplifying circuit; wherein a first equivalent impedance on a first intermediate terminal in the first feedback circuit substantially equals a second equivalent impedance on a second intermediate terminal in the second feedback circuit, and the gain adjusting circuit is arranged to tune a transfer function from the input signal to the output signal. |
| US09484876B2 |
Control of a switched mode power supply and linear power supply for an audio device
An audio device and an output method thereof are provided. The audio device includes: an envelope detector configured to detect an envelope of an input audio signal; a power supply which includes a linear power supply (LPS) and a switching-mode power supply (SMPS); an amplifier configured to amplify the input audio signal; an output unit configured to output the audio signal amplified by the amplifier; and a controller configured to compare a voltage level of the detected envelope with a preset level, select one of the LPS and the SMPS based on a result of the comparison, and control the power supply to supply power from the selected one of the LPS and the SMPS to the amplifier. |
| US09484872B1 |
Amplifier circuit with static consumption control and corresponding control method
An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage. |
| US09484871B1 |
Complex bandpass filter having a transfer function with two poles
In some implementations, a filter circuit includes a first signal path that includes a first amplifier and a second signal path that includes a second amplifier. The first signal path is configured to receive a first component of a complex signal and provide a filtered version of the first component of the complex signal. The second signal path is configured to receive a second component of the complex signal and provide a filtered version of the second component of the complex signal. The first signal path before the first amplifier is coupled to the second signal path before the second amplifier. The first signal path after the first amplifier is coupled to the second signal path before the second amplifier. The second signal path after the second amplifier is coupled to the first signal path before the first amplifier. |
| US09484868B2 |
Distortion compensation apparatus and wireless communication apparatus
Distortion is effectively reduced in a wide frequency band of an output signal from an amplifier. A distortion compensation apparatus includes: a distortion compensation processing section that performs a distortion compensation process on an input signal to the amplifier, based on a first amplifier model of the amplifier, and output a compensated signal; a signal generation section that receives the compensated signal and a first digital monitor signal, and generates a second digital monitor signal; and an estimation section that estimates the first amplifier model, based on the compensated signal and the second digital monitor signal. The first digital monitor signal is a signal generated by subjecting an analog monitor signal obtained by monitoring an output signal from the amplifier, to analog-to-digital conversion. A monitor band of the first digital monitor signal is narrower than a frequency band of the compensated signal. A frequency band of the second digital monitor signal is wider than the monitor band of the first digital monitor signal, and includes signal components obtained by restoring signal components outside the monitor band, among signal components included in the analog monitor signal. The signal generation section restores the signal components outside the monitor band among the signal components included in the analog monitor signal, based on the compensated signal and the first digital monitor signal. |
| US09484863B2 |
Amplifier circuit and method
First and second amplifiers are respectively coupled to first and second lines, each having first and second portions. An auxiliary amplifier has an output coupled to an auxiliary line network which comprises: a first auxiliary line coupled between an auxiliary junction and a first intersection between the first and second portions of the first line; a second auxiliary line coupled between the auxiliary junction and a second intersection between the first and second portions of the second line; and a third auxiliary line for coupling the output of the auxiliary amplifier to the auxiliary junction. Each of the first and second lines have a higher-impedance portion and a lower-impedance portion whose lengths are substantially equal. Lengths of the respective first portions of the first and second lines sum to half a wavelength, and lengths of the respective second portions of the first and second lines sum to half a wavelength. |
| US09484862B2 |
Device and method for bias control of class A power RF amplifier
A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current. |
| US09484861B1 |
Method for system level oriented load-pull-based envelope tracking power amplifiers
The method for system level oriented load-pull-based envelope tracking power amplifiers includes steps of performing a multi-dimensional load-pull and selecting the reflection coefficients to be presented to the transistor while taking into account the system level architecture of the power amplifier. It is shown that adopting the proposed load reflection coefficient selection algorithm leads to an additional efficiency enhancement. This extra performance is achieved without additional circuitry or cost. |
| US09484856B2 |
Oscillator startup
A modulated signal based on a low-precision, fast startup oscillator is provided to a circuit with a high-precision, slow startup oscillator. The frequency of the modulated signal ranges around the characteristic or resonant frequency of the high precision oscillator without using feedback from the high precision oscillator circuit. An implementation can include one or more variable gain circuits that can be adjusted based on an amplitude threshold in relation to the output signal of the high precision oscillator circuit. |
| US09484855B2 |
System and methods for correcting clock synchronization errors
Clock synchronization error is corrected or minimized by fitting a parabolic f(T) function to the crystal's data, and compensating for sampling period drift in an Analog to Digital Converter (ADC) at various temperatures. |
| US09484849B2 |
Sensorless BEMF measurement in current-controlled brushless motors
A method for determining a reserve torque in an electronically-switched drive mechanism, specifically a pulse motor for a headlamp beam adjustment system, based upon a parameter in an essentially linear relationship to a back electromotive force of the drive mechanism. Whereby, for the determination of the back electromotive force-related parameter, the variation in the drive current is determined in relation to a change interval. |
| US09484843B2 |
Electric circuit with power amplifier for piezoelectric actuators
An electric circuit with one power amplifier (V1) for at least two piezoelectric actuators (C1, C2), said piezoelectric actuators (C1, C2) being in preferably antagonist arrangement connected mechanically in series and being connected electrically with each other and operated or clocked by a control circuit, such as a pulse modulator circuit, for time-variant energizing of the piezoelectric actuators (C1, C2) in push-pull fashion, said power amplifier (V1) being connected to a junction point between the two piezoelectric actuators (C1, C2), characterized in that said power amplifier (V1) is connected to a one directional diode (D1) and in that two buffer capacitors (C3, C4) and two static resistors (R3, R4) are provided downstream the one directional diode (D1) with regard to the power amplifier (V1). |
| US09484842B2 |
Segmentally structured disk triboelectric nanogenerator
A generator includes a disc shaped first unit, a disc shaped second unit and an axle. The first unit includes a substrate layer, a double complementary electrode layer and an electrification material layer. The electrode layer includes a first electrode member and a second electrode member. The first electrode member includes evenly spaced apart first electrode legs extending inwardly. The second electrode member is complementary in shape to the first electrode member. The legs of the first electrode member and the second electrode member are interleaved with each other and define a continuous gap therebetween. The electrification material includes a first material that is in a first position on the triboelectric series. The second unit defines elongated openings and corresponding elongated leg portions, and includes a second material that is at a second position on a triboelectric series, different than the first position. |
| US09484835B2 |
Modified voltage source converter structure
The invention concerns a voltage source converter (26) comprising a group of phase legs, at least three connection terminals (AC1, AC2, AC3, DC+, DC−) for connecting the phase legs to power transmission elements, a first group of cells (C1p1, C2p1, C1n1, C2n1, C1p2, C2p2, C1n2, C2n2, C1p3, C2p3, C1n3, C2n3) in each phase leg and a second group of cells (C3p1, C3n1, C3p2, C3n2 C3p3, C3n3). The cells (C1p1, C2p1, C1n1, C2n1, C1p2, C2p2, C1n2, C2n2, C1p3, C2p3, C1n3, C2n3) in the first group are only capable of providing unipolar voltage contributions to the converter and connected for only being capable of such unipolar voltage contributions, while the cells (C3p1, C3n1, C3p2, C3n2 C3p3, C3n3) in the second group are connected to the corresponding cells of the first group and arranged to have bipolar voltage contribution capability. |
| US09484831B2 |
Electric-power conversion system
The number of constituent components is reduced so as to provide a small-size and inexpensive electric-power conversion system. The electric-power conversion system is provided with an inverter circuit (14) connected with the rear stage of an AC power source, a smoothing capacitor (22) connected with the rear stage of the inverter circuit (14) by way of a rectifying device (20), a charging switch (2) that is connected with the front stage of the inverter circuit (14), that inputs an electric quantity based on an output of the AC power source (1) to the inverter circuit (14) when being turned on, and that cuts off an input of the electric quantity to the inverter circuit (14) when being turned off, and an inrush current prevention circuit (7) having an inrush current prevention switch (3) and an inrush current prevention resistor (4) that is connected in series with the rear stage of the inrush current prevention switch (3); the electric-power conversion system is characterized in that the inrush current prevention circuit (7) is connected in parallel with the charging switch (2). |
| US09484826B2 |
Multiport DC-DC autotransformer and methods for controlling and using the same
A multiport DC-DC autotransformer for interconnecting three or more DC systems. The autotransformer includes 2N−1 converters sequentially connected in series at a DC side, and connected to an AC transmission line via an AC link at an AC side, and a positive terminal of the ith converter of the 2N−1 sequentially connected converters and a negative terminal of the (2N−i)th converter are respectively connected to a positive terminal of the ith DC system and a negative terminal thereof, where N represents the number of DC systems, and i represents the serial number of converters. Also disclosed are a method for determining power rating of each converter of the multiport DC-DC autotransformer, and a method for controlling the autotransformer. Most power can be transferred between different DC systems via a direct electrical connection without DC-AC-DC conversion. |
| US09484822B2 |
Method and apparatus for implementing an unregulated dormant mode with an event counter in a power converter
A control circuit for use in a power converter includes a drive signal generator coupled to generate a drive signal to control switching of a switch to regulate an output of the power converter. An event detection circuit is coupled to the drive signal generator to indicate if a switching period of one switching cycle of the drive signal exceeds a threshold switching period. An event counter circuit is coupled to the event detection circuit to render dormant the drive signal generator if the event detection circuit indicates a period of a switching cycle of the drive signal exceeds the threshold switching period for a threshold consecutive number of switching cycles. |
| US09484821B2 |
Adjustable resonant apparatus for power converters
An apparatus comprises a first series resonant inductor coupled to a switching network and a transformer, a first series resonant capacitor coupled to the switching network and the transformer, a first parallel inductor coupled to the switching network through the first series resonant inductor and the first series resonant capacitor, a resonant frequency adjusting device coupled to the switching network and the transformer and a switch connected in series with the resonant frequency adjusting device. |
| US09484818B2 |
DC-DC converter
A DC-DC converter includes first and second switching devices electrically connected in series between an input terminal and a ground terminal, third and fourth switching devices electrically connected in series between an output terminal and the ground terminal, an inductor, a drive circuit that drives the first switching device to turn on and off, a bootstrap capacitor circuit connected electrically to the drive circuit, and a control circuit. The control circuit is operable to turn on and off the switching devices serially connected with each other after a simultaneous-off duration for which both of the switching devices are continuously turned off. The control circuit is operable to charge the bootstrap capacitor by continuously turning on keeping the second switching device for a charging duration while continuously turning off the first switching device for a sustaining duration determined by the simultaneous-off duration and the charging duration. This DC-DC converter can reduce a current ripple even when the bootstrap capacitor is charged. |
| US09484814B2 |
Power converter controller with analog controlled variable current circuit
A bleeder controller for controlling a magnitude of a variable current conducted by bleeder circuitry between input terminals of a device is disclosed. The magnitude of the variable current is controllable in response to a control signal. The bleeder controller includes a dimming detector to classify a half line cycle as leading-edge-dimmed or a trailing-edge-dimmed in response to at least one of an input current sense signal and an input voltage sense signal. |
| US09484813B2 |
Boost converter circuit and control method thereof
A boost converter includes an inductor configured to have one terminal connected with an input power source; a switching element configured to be connected between another terminal of the inductor and a reference potential terminal; a rectifier configured to be connected between the other terminal of the inductor and an output terminal; and a controller configured to boost a voltage of the input power source using the inductor by applying a duty drive to the switching element in a switching cycle so that a command value of a current to be flowing into the inductor is equivalent to an average value of a current flowing into the inductor during an off period during which the switching element is duty-off in the switching cycle, and to have the voltage output from the output terminal. |
| US09484810B2 |
Semiconductor device and method of manufacturing the same
A regulator includes a capacitor connected between a ground terminal and an output terminal at which a first voltage is supplied. The first voltage is higher than a power source voltage supplied to the regulator. A feedback circuit in the regulator is configured to output a boost signal corresponding to a comparison between the first voltage and a threshold voltage value. A clock generating circuit includes an oscillator circuit that outputs an oscillation signal and a buffer circuit that outputs a clock signal according to the oscillation signal. The clock signal has an electric current level that is controlled in accordance with the boost signal. A charge pump outputs the first voltage in accordance with the clock signal. |
| US09484808B2 |
Bidirectional unisolated DC-DC converter based on cascaded cells
A DC-DC converter (200) comprising a first (201) and a second (202) variable voltage source, a capacitor (203), an alternating current filter (204), and controlling means (205), is provided. A first DC voltage (UDC1) is provided over a series-connection of the first and the second voltage source, and a second DC voltage (UDC2), being lower in magnitude than (UDC1), is provided over the second voltage source. The conversion between (UDC1) and (UDC2) is effected by circulating an alternating current within a circuit comprising the two voltage sources and the capacitor, thereby exchanging power between the two voltage sources. The alternating current is driven by AC voltage components provided by the first and the second voltage source. The controlling means is arranged for controlling the first and the second voltage source so as to maintain a phase difference between the AC components to be close to π. |
| US09484806B2 |
Driving apparatus for driving power factor correction circuit
There is provided a driving apparatus for driving an interleaved power factor correction circuit including a first main switch and a second main switch performing a switching operation with a predetermined phase difference and a first auxiliary switch and a second auxiliary switch forming a transformation path for surplus power existing before an ON operation of the first main switch and a second main switch, respectively, including: an input unit obtaining an input signal; a current sensing unit obtaining information regarding a current of the interleaved power factor correction circuit; and an output unit outputting a first control signal with respect to the first main switch, a third control signal with respect to the second main switch, a second control signal with respect to the first auxiliary switch, and a fourth control signal with respect to the second auxiliary switch, based on the input signal and the current information. |
| US09484795B2 |
Vibration energy harvesting using cycloidal motion
Some embodiments relate to an energy conversion device, comprising: a casing; an electromagnetic (EM) transducer disposed at one side of the casing; a round magnet disposed in the casing and free to move relative to the casing and the EM transducer in at least two degrees of freedom; and a ferromagnetic object fixed relative to the casing at an opposite side of the casing to the EM transducer and arranged to attract the magnet toward a rest position within the casing. The EM transducer is positioned so that movement of the magnet relative to the EM transducer varies the magnetic field through the EM transducer, thereby generating electrical potential across at least a part of the EM transducer. |
| US09484789B2 |
Rotating electric machine
Provided is a rotating electric machine that is capable of sufficiently cooling, by using a liquid coolant, electronic devices which are attached to a rotor. The rotating electric machine is equipped with: a stator for generating a rotating magnetic field; a rotatable rotor that is installed so as to face the stator; diode devices that are connected to coils wound on the rotor and arranged so as to rotate with the rotor; and a cooling structure for cooling the diode devices by means of a cooling oil which is supplied from the inner side in the radial direction with respect to the diode devices. |
| US09484785B2 |
Electric motor
An electric motor has a rotor and a stator. The stator has an endcap with two brush assemblies, two brush brackets for holding the brush assemblies and two electrical terminals. Each brush assembly is detachably mounted to its brush bracket and has a brush holder, a brush slidably received in the brush holder, a spring for urging the brush out of the brush holder, and a conductive member electrically connecting the brush with a corresponding electrical terminal via a resilient releasable connection. |
| US09484780B2 |
Segmented armature motor having a segmented coil frame having coil windings on the outer surface
Provided is a segmented armature motor, which includes a plurality of armature coils which enclose a rotor having a rotary shaft, an armature which houses the armature coil and which is coupled in a segmented form, a motor frame which is coupled to the armature so as to enclose the armature, and motor covers coupled to the front and rear faces of the motor frame. The segmented armature motor is formed so that the armature coils completely enclose a pole portion of the rotor and are formed into a horseshoe shape or U shape, thereby minimizing magnetic losses of the armature and of the rotor. |
| US09484777B2 |
Rotor core of motor
Provided is a rotor core of a motor, the rotor core, the rotor core including: a thin disk-shaped rotor core member; a shaft hole penetratively formed at a center of the rotor core member; a shaft press-fitted into the shaft hole; a plurality of magnet insertion holes penetratively formed at a position near to a periphery of the rotor core member for inserted coupling by a magnet; and a magnet support rotor core member in which a magnet support member tightly contacting a magnet inserted into the magnet insertion hole to a radial direction of the rotor core member is protrusively formed at the magnet insertion hole, wherein the rotor core members are stacked each at a predetermined height, and the magnet support rotor core members are arranged at an upper surface and a bottom surface of the plurality of stacked rotor core members, and the shaft is press-fitted into the shaft hole. |
| US09484776B2 |
Motor
A rotor of a motor includes a first rotor that includes a first rotor core and a plurality of first magnets that are coupled to an outer circumferential surface of the first rotor core, a second rotor that includes a second rotor core and a plurality of second magnets that are coupled to an outer circumferential surface of the second rotor core, and a third rotor that is stacked between the first rotor and the second rotor and includes a third rotor core and a plurality of third magnets that are coupled to an outer circumferential surface of the third rotor core, wherein magnetic fluxes of the plurality of third magnets are less than magnetic fluxes of the plurality of first magnets or second magnets. |
| US09484773B2 |
Energy harvesting apparatus and energy harvesting system
An energy harvesting apparatus includes: a capacitor configured to store energy generated by an energy harvesting element; and a switch connected to the capacitor and configured to switch energy supply from the capacitor to a load based on a capacitor voltage with which the capacitor is charged. An energy harvesting system includes: energy harvesting elements; energy harvesting apparatuses which are provided to respectively correspond to the energy harvesting elements; and a load as an energy supply destination connected to the energy harvesting apparatuses. |
| US09484771B2 |
Uninterruptable power supply for device having power supply modules with internal automatic transfer switches
Techniques are described for determining whether power from a first power source is unavailable to a power supply module. In response to determining that power from the first power source is unavailable, the techniques de-couple the first power source from one or more components of an electronic device connected to an output of the power supply module with one or more de-coupling components of the power supply module that connect an automatic transfer switch (ATS) of the power supply module to an output of the power supply module. Subsequent to de-coupling the first power source from the one or more components of the electronic device, the techniques de-couple a power supply module from the first power source. The techniques couple the power supply module to a second power source for delivering power to the one or more components of the electronic device. |
| US09484769B2 |
Case having wireless charging receiver pad for electronic devices
A case for a portable electronic device includes a soft protective case, a hard protective frame, and a wireless charging receiver pad stored in a pad opening of the soft protective case. The pad opening has first, second, third and fourth walls such that the first and second walls face each other and the third and fourth walls face each other. Upper portions of the first and second walls are slanted to same directions and lower portions of the first and second walls are slanted to same directions whereas the upper and lower portions of the first wall are slanted in opposite directions. In addition, left and right portions of the third wall are slanted in opposite directions and left and right portions of the fourth wall are slanted in opposite directions as well. The right portions of the third and fourth walls are slanted in same directions. |
| US09484768B2 |
Complex device and electronic device having the same
Provided are a complex device including a piezoelectric device, a wire patch cell (WPC) antenna disposed on one surface of the piezoelectric device, the WPC antenna being connected to two antenna patterns that are vertically spaced apart from each other, and a near field communication (NFC) antenna disposed outside the WPC antenna and an electronic device having the same. |
| US09484763B2 |
Battery pack and method of controlling the same
A battery pack and a method of controlling the same. The battery pack includes: a first battery module that includes at least one battery cell; a second battery module that includes at least one battery cell electrically connected to the first battery module; a charge/discharge control unit that breaks or connects a charge/discharge path of each of the first battery module and the second battery module; a first battery management unit that controls the first battery module; and a second battery management unit that generates a signal for controlling switches included in the charge/discharge control unit by referring to a state of the second battery module, wherein the first battery management unit and the second battery management unit are connected in parallel to the charge/discharge control unit. |
| US09484760B2 |
Extendable jumper cables
Extendable jumper cables for transferring electrical energy from a charged battery to a discharged battery include a first short cable having two clamp ends that detachably connect to two terminals of the charged battery, and a plug end that detachably connects to a cooperating plug end of a second short cable. The second short cable includes two clamp ends that detachably connect to two terminals of the discharged battery. The plug end and the cooperating plug end include cable connection fittings that allow the first short cable and the second short cable to be connected together to form a typical set of jumper cables. The plug end and the cooperating plug end further include respective plugs that cooperate to receive corresponding plugs of an extension cord to increase a length of the extendable jumper cables to electrically connect the charged battery and the discharged battery together when a distance separating the charged battery and the discharged battery is greater than a combined length of the first short cable and the second short cable. |
| US09484758B2 |
Hybrid bootstrap capacitor refresh technique for charger/converter
The disclosed embodiments provide a synchronous switching converter that converts a DC input voltage into a DC output voltage. This synchronous switching converter includes a high-side switching MOSFET coupled between an input node and a first node. The converter also includes a low-side switching MOSFET coupled between the first node and a ground node and is in series with the high-side switching MOSFET. This converter additionally includes a bootstrap capacitor coupled to the high-side switching MOSFET to provide turn-on voltage for the high-side switching MOSFET. Furthermore, the converter includes a main refresh circuit coupled to the bootstrap capacitor and is configured to refresh the bootstrap capacitor during a first operating mode of the synchronous switching converter. Moreover, the converter includes an auxiliary refresh circuit coupled to the main refresh circuit and the bootstrap capacitor and is configured to refresh the bootstrap capacitor during a second operating mode of the converter. |
| US09484755B2 |
In-vehicle charging control device, vehicle charging system and vehicle
An in-vehicle charging control device may comprise a control module, a charging socket, and a switching circuit. The charging socket has a charging connection confirming terminal (CC) and a protective grounding terminal (PE). The switching circuit is connected with the charging connection confirming terminal (CC) and the protective grounding terminal (PE) of the charging socket. The control module is connected with an in-vehicle battery via the switching circuit. The charging socket matches with a charging plug. The switching circuit is in a conducting state when the charging plug is plugged in the charging socket and in a disconnection state when the charging plug is not plugged in the charging socket. |
| US09484748B2 |
Dual port pass-through midspan
A dual port pass through midspan constituted of: a first port arranged for connection to a first data terminal equipment over a first data communication cabling; a second port arranged for connection to a second data terminal equipment over a second data communication cabling; a first power sourcing equipment arranged to inject power on two of the 4 wire pairs of the first data communication cabling; a second power sourcing equipment arranged to inject power on two of the 4 wire pairs of the second data communication cabling; and a data pass through connection arranged to pass high speed data signals between the first port to the second port, the data pass through connection comprising a direct current blocking circuit arranged to: prevent power from the first power sourcing equipment from appearing at the second port; and prevent power from the second power sourcing equipment from appearing at the first port. |
| US09484747B1 |
Holistic optimization of distribution automation using survivability modeling
Transient survivability metrics are used to select improvements to distribution automation network designs. The approach combines survivability analysis and power flow analysis to assess the survivability of the distribution power grid network. Available investment decisions are then automatically optimized with respect to survivability and investment costs. |
| US09484744B2 |
Scheduling apparatus, scheduling method and computer-readable storage medium
A scheduling apparatus includes a first calculator, a storage, and a second calculator. The first calculator is configured to calculate an assignment of plural time slots to a consumer. Each of the plural time slots is classified into at least any of plural categories. The storage is configured to store a first demand, from the consumer, regarding an extent to which the categories associated with the assignment are biased. The second calculator is configured to calculate an extent to which the categories associated with the assignment calculated by the first calculator are biased and calculate a first evaluation value representing a deviation between the first demand and an extent to which the categories associated with the assignment calculated by the first calculator are biased. The first calculator calculates the assignment so as to optimize an evaluation function including the first evaluation value. |
| US09484737B2 |
Protector of rectifier and wireless power receiver including protector
A protector that protects a rectifier, and a wireless power receiver including the protector are provided. In one embodiment, a protector for an electronic device may include: a switch configured to control current flow to a rectifier of the electronic device; and a switch controller configured to: compare, with a predetermined threshold value, a voltage difference between an output voltage of the rectifier and a voltage of the electronic device; and transmit a control signal to the switch (i) to discontinue current flow to the rectifier when the voltage difference is greater than the predetermined threshold value, and (ii) to enable current flow to rectifier when the voltage difference is less than or equal to the predetermined threshold value. |
| US09484731B2 |
Bipolar lightning rod apparatus
A bipolar lightning rod apparatus includes a fixation plate, a rod member configured to have one end connected to the fixation plate in a length direction thereof and charged with the electric charges of a ground, at least two insulators installed in the length direction, an electrification plate installed between adjacent insulators, electrically insulated from the rod member, and charged with electric charges having an opposite polarity to the electric charges of the ground, an electrification tube installed between the electrification plate and the insulators, electrically connected to the electrification plate, and charged with electric charges having an opposite polarity to the electric charges of the ground, and a rod cap connected to the top of the rod member and configured to induce the falling of a thunderbolt. The rod cap has an outside diameter greater than that of the insulators. |
| US09484730B2 |
Anchoring clamp on bundle wires for high-voltage electric lines and dampening spacer provided with such clamp
The present invention relates to a clamp and a spacer for bundle-shaped wires of high-voltage electric lines, as well as a relative mounting kit. The clamp possesses an arm for fastening to wires, at the free end of which two fixed jaws are formed. The second jaw being movable through disengageable tightening means, both jaws being provided with opposite saddles for the housing of wire, wherein the second moving jaw has a first end mounted rotating on a pin, carried by said fastening arm in a position coinciding with a first end of the first jaw. The tightening includes a tie rod having an end mounted rotating on the jaw and a distal end constrained through a constraint pin to a cam lever. |
| US09484728B1 |
Joiner for channel raceway assembly
A joiner system for a channel raceway includes a joiner body with first and second posts, and a joiner wall panel separate from the joiner body. The joiner wall panel connects to the joiner body between the first and second posts to form a wall between the first and second posts. First and second connecting projections extend outward from adjacent the respective first and second posts. The first and second connecting projections are spaced apart from one another and in generally opposing relationship with respect to one another. The joiner body has a snap-fit component on the lower side of a base of the joiner body. The snap-fit component mates in a snap-fit connection with a splice plate to interconnect the joiner body and at least two pieces of channel framing. |
| US09484723B2 |
Wire harness
A wire harness (11) includes a one-sided self-adhesive sheet (28) which has a special adhesive layer (23) and is formed with a sheet hole (21), and which is folded at a folded part (25) so that two parts of the adhesive surface (23) are adhered and fixed, electric wires (15) which are sandwiched between the two parts of the special adhesive layer (23) along the folded part (25), and which have two end parts which are derived from the one-sided self-adhesive sheet (28), and a clip (17) which has a base plate (37), from which an elastic locking leg (43) which is inserted into the sheet hole (21) is raised, and which is formed with a regulating edge portion (45) which is sandwiched by the one-sided adhesive sheet (28) along the folded part (25). |
| US09484722B2 |
Pulling head assembly workstation
A workstation and method for the installation of a pulling head assembly onto one or more conductors of a cabling system are provided. The workstation incorporates one or more of: a conductor clamp that holds the conductors of the cabling system in place during the installation of the pulling head assembly; a cutting guide having indicia marks that indicate the lengths to which to cut the conductors in order to achieve a staggered pattern of pulling eyes attached to the conductors in the pulling head assembly; a stripping tool that is used to remove a portion of the insulation from the terminal end of each conductor so that the end of the conductor may be inserted into the pulling eye; and a crimping tool that is used to crimp the pulling eyes onto the terminal ends of each of the conductors. |
| US09484721B2 |
Truck and installation method for wires
A truck and method for installing catenary wire are disclosed in which the truck may have wire manipulating arms, a creep drive and a wire measuring device. The wire manipulating arms may be used to hold the messaging wire and/or contact wire while the wire measuring device may be used to measure the height and stagger of the contact wire. |
| US09484709B2 |
Optical amplifier arrangement
The invention relates to an optical amplifier arrangement for amplifying ultra-short pulsed laser radiation comprising a mode-locked laser (1) and two or more optical amplifiers (3) arranged downstream of the laser (1) in the propagation direction of the laser radiation. Optical amplifier arrangements of this type are known in the prior art. Here the intention is to present an alternative to the known amplifier arrangements. The invention proposes arranging between the laser (1) and the optical amplifiers (3) at least one splitting element (2) which splits the pulsed laser radiation between a plurality of amplifier channels (4), wherein each amplifier channel (4) has at least one optical amplifier (3), and wherein at least one common combination element (5) is disposed downstream of the amplifier channels (4) and coherently superimposes the pulsed laser radiation amplified in the amplifier channels (4). |
| US09484706B1 |
Tapered core fiber manufacturing methods
Tapered core fibers are produced using tapered core rods that can be etched or ground so that a fiber cladding has a constant diameter. The tapered core can be an actively doped core, or a passive core. One or more sleeving tubes can be collapsed onto a tapered core rod and exterior portions of the collapsed sleeving tubes can be ground to provide a constant cladding diameter in a fiber drawn from the preform. |
| US09484700B2 |
Hydraulic power tool
A biased closed crimping head for a hydraulic power tool. The crimping head comprises a first pivoting pin and a first jaw disposed for rotation about a first axis defined by the first pivoting pin. The crimping head further comprises a second pivoting pin and a second jaw disposed for rotation about a second axis defined by the second pivoting pin. An extension spring is operatively coupled to the first jaw and the second jaw so that the jaws reside in a biased closed position. During a crimping action, the first jaw rotates about a first axis defined by the first pivoting pin, and the second jaw rotates about a second axis defined by the second pivoting pin. |
| US09484696B2 |
Bulb socket and lighting system
A pair of terminal portions of a bus bar is composed of a first terminal portion and a second terminal portion extended along a sidewall of the base portion. Each of the first and second terminal portions has a spring portion for generating biasing force toward a direction of holding the base portion, and a contact portion provided on a tip of the spring portion. The contact portion of the first terminal portion abuts on a contact lead wire, and the contact portion of the second terminal portion abuts on the sidewall of the base portion, thereby the contact portions hold the base portion therebetween. In a natural condition that the bulb is not inserted and the spring portion is not elastically deformed, the pair of terminal portions is displaced from a center plane toward the one side corresponding to a projection size of the contact lead wire. |
| US09484695B2 |
Smart plug system and method
A smart plug system includes, in an embodiment, a smart plug that may be securable to an electrical outlet by way of an anti-theft device. The anti-theft device may include in an embodiment: a body securable to the electrical outlet; and a protrusion that extends from the body and which may extend into an aperture of the smart plug to secure the smart plug to the electrical outlet when the smart plug is plugged into an electrical outlet. In an embodiment, the smart plug may be configured to be customizable in appearance by including a plurality of different covers that may be secured to a face of the smart plug. |
| US09484694B2 |
Telecommunications cassette
A telecommunications cassette (14, 114) that includes a body (30) with a front (32) and an opposite rear (34), two rows (38) of RJ45 jacks (20) disposed on the front (32), and two MRJ21 connectors (36) disposed on the rear (34). The two rows (38) of RJ45 jacks (20) are oriented opposite to one another, and the two rows of RJ45 jacks are offset from one another. The MRJ21 connectors (36) are oriented in the same direction, and the MR21 connectors (36) are vertically offset from one another. Two circuit boards (52, 56) are provided within the body (30), wherein one row (38, 39, 40) of RJ45 jacks (20) is connected to a respective one of the MRJ21 connectors (36), and wherein one of the circuit boards (50, 52, 56) includes a notch (66) for receiving one of the MRJ21 connectors (36, 37, 41). |
| US09484689B2 |
Wire spacer for different types of cable wires
A method associated with the related structures to prepare cable wires of a cable connector, comprising the steps of: extending a first type and a second type of cable wires through a wire spacer having a notch; securing the first and second types of wires to the spacer; bending the extended cable wires of the first type in the spacer notch; operating the extended cable wires of the second type; returning the extended cable wires of the first type; and operating the extended cable wires of both the first type and the second type. The second type may be coaxial cables and the operating steps on these coaxial cables may include steps of removing outer jackets and braidings. |
| US09484687B1 |
Modular lighted tree
A lighted artificial tree includes a first tree portion including a first trunk portion, first branches joined to the first trunk portion, and a first light string. The first trunk portion has a trunk connector and a first trunk wiring assembly, the first trunk wiring assembly is electrically connectable to the first light string and the trunk connector, and at least a portion of the first wiring assembly is located inside the first portion. The second tree portion includes a second trunk portion, second branches, and a second light string. The second trunk portion has a trunk connector and a second trunk wiring assembly, the second trunk wiring assembly electrically connectable to the second lighting string and the trunk connector. The second tree portion may be mechanically coupled and electrically connected to the first tree portion by coaxially coupling the first trunk portion to the second trunk portion. |
| US09484683B1 |
Conductive terminal
The present invention discloses a conductive terminal including two conductive members or further comprising a hot melt fixing member. Each conductive member is provided with a groove which is concaved in from an edge of the host conductive member. The grooves on the two conductive members are opposite to each other and a gap is maintained between the two conductive members by an elastic force between the conductive members. The hot melt fixing member is put into the grooves of the two conductive members and is combined on the conductive members to overcome the elastic force, enabling the two conductive member to form contact limit, the hot melt fixing member to be damaged when overheat, and the two conductive members to be opened by the elastic force to form open circuit. The conductive member can be applied to overheat protection of a plug and a socket. |
| US09484682B2 |
USB socket
A USB socket includes a socket body, an upper cover, at least one USB interface disposed in the socket body, and a power supply conversion structure for converting an external power supply to a power supply suitable for output of the USB interface. A USB jack is disposed on the upper cover at a position corresponding to the USB interface, the upper cover is detachably mounted on the socket body, the USB interface is mounted at a lower side of the upper cover, and when the upper cover is mounted to the socket body, the USB interface inserts into the socket body. A moving contact is electrically connected to the USB interface, a fixed contact electrically connected to the power supply conversion structure is further disposed in the socket body and the moving contact is driven to be in contact conduction with the fixed contact. |
| US09484681B2 |
Flippable electrical connector
A plug connector for use with a complementary receptacle connector, includes an insulative housing defining a receiving cavity therein and a plurality of passageways on opposite of the mating cavity, a pair of terminal modules stacked on each other and a metallic shell. Each terminal module includes an insulator and a plurality of contacts loaded on insulator, the contacts includes contacting sections extending out of the insulator and tail extending out of the insulator. The insulators of the stacked terminal modules are located behind the insulative housing and the contacting sections of the contacts are disposed in the corresponding passageways. The terminal modules and the insulative housing are commonly enclosed in the metallic shell. |
| US09484679B2 |
Electrical connector with upper and lower terminals coupled with each other
An electrical connector for mounting to a printed circuit board for mating with a plug connector, includes an insulative housing and the upper and lower contacts on the housing, each contact including a contacting section, the contacts including grounding contacts each having a free end of the contacting section, and a mounting leg mounted to the corresponding grounding region of the printed circuit board wherein the free ends of the corresponding paired upper grounding contact and lower grounding contact either abut against each other or against a metallic shielding plate embedded within the mating tongue to form a parallel relation between the paired upper grounding contact and lower grounding contact. |
| US09484678B1 |
Electrical cage member having standoff features
An electrical connector assembly includes a cage member having a plurality of walls comprising side walls and an end wall defining a port configured to receive a pluggable module that is electrically connected to a communication connector housed within the cage member. The port has an airflow channel along the end wall allowing airflow through the port along the pluggable module. Standoff features extend from at least one of the end wall and the side walls. The standoff features extend into the airflow channel and are configured to engage the pluggable module and locate the pluggable module relative to the communication connector for mating thereto and locate the pluggable module relative to the airflow channel. |
| US09484675B2 |
Terminal structure of electrical connector
A connector includes a shielding case, an insulating main body and a terminal group. The shielding case has an opening for allowing a docking plug to insert therein. The insulating main body is covered by the shielding case. The terminal group is accommodated in the insulating main body. The terminal group has terminals. Each of the terminals has a contact portion and a connecting portion. The contact portion is arranged in two rows in the opening of the shielding case. The connecting portions are fixed to the insulating main body. The connecting portions of a portion of the terminals extend outwards from the insulating main body to form welding legs arranged in the same row. |
| US09484674B2 |
Differential electrical connector with improved skew control
An improved electrical connector is provided by compensating for skew in signal conductors of a differential pair while ensuring a uniform impedance along the differential pair. Skew is equalized by regions of lower dielectric constant preferentially positioned adjacent the longer conductor of each pair. Impedance along the length of the signal conductor is equalized by a compensation portion in the first conductor that offsets for a change in impedance associated with the change in dielectric constant adjacent the longer conductor. The compensation portion may be a widening in the first conductive element relative to a nominal width of the conductive element. The skew compensation portion may be along a longer edge of the longer conductor and the impedance compensation portion may be along the shorter edge of the longer conductor. |
| US09484666B2 |
Electrical connector and electrical connector assembly
An electrical connector assembly is disclosed having a first connector and a second connector. The first connector has a first engagement portion on a first mating end, and at least one first ridge positioned on and protruding outward from an outer surface of the first engagement portion. The second connector has a second engagement portion on a second mating end. The second engagement portion has a first connector receiving chamber having an inner surface, and at least one second ridge positioned on and protruding inward from the inner surface. The at least one second ridge is positioned on, and protrudes inward from, the inner surface, being in electrical contact with the first ridge when the first engagement portion is positioned in the first connector receiving chamber. |
| US09484664B1 |
Water and ingress resistant audio port
A water resistant port and a method for using it are provided. The port comprises a moveable seal assembly coupled to a spring structure. The moveable seal assembly may comprise a plastic material on an inner surface and a seal material on an outer surface. When the spring structure is in a relaxed position, the moveable seal assembly is caused to create a seal with a gasket material coupled to a side wall of a port casing. The spring structure comprises a spring coupled to the moveable seal assembly at one end and to a guide at an opposite end in an interior portion of the port casing. The port casing comprises, on an interior surface, one or more electrical connectors adapted to receive one or more electrical contacts of an accessory plug when the spring structure is compressed and the moveable seal assembly is in an engaged position. |
| US09484661B2 |
Electrical connector protection
An embodiment of an electrical connector assembly includes a shell, a plurality of fixed conductors, and a potting container. The shell includes a plurality of walls extending in a first direction from a base having at least one opening. The base and the plurality of walls define a shell outer surface and a shell inner surface. The shell inner surface bounds an inner volume of the shell and has an inner shell profile. The plurality of fixed conductors project through the opening into the inner volume of the shell. The potting container includes an outer surface complementing the shell inner profile, and a cavity receives the fixed conductors through a slot in the base. A potting compound fills the cavity such that the potting compound completely surrounds the conductors. |
| US09484660B2 |
Electrical connector
An electrical connector includes a housing including a front housing and a rear housing matable to define the housing. The front housing and the rear housing are molded as a single piece with a hinge member connecting the front housing and the rear housing. The rear housing is rotatable about the hinge member from an open position to a closed position. The front housing has front terminal channels configured to receive terminals and the rear housing has rear terminal channels aligned with the front terminal channels when the rear housing is rotated to the closed position but not aligned with the front terminal channels when the rear housing is in the open position. The rear terminal channels are configured to allow the terminals to at least partially pass therethrough into the front terminal channels during loading of the terminals into the housing. |
| US09484659B1 |
UL compliant and IEC compliant power connector products
The present invention relates to a power connector for receiving an electric plug. The power connector is provided with a three-piece safety shutter architecture to prevent unwanted or improper insertion of a single plug pole into the power receptacles. Preferably, the power connector is further provided with a Schuko grounding frame and a direct wiring architecture, allowing the invention to meet the strict international safety standards for household plugs, adapters and socket-outlets. |
| US09484658B2 |
Connector with a rectangular tab insertion hole and a detection probe insertion hole communicating with a corner region of the tab insertion hole
A connector (C) includes a housing (20) formed with terminal accommodation chambers (22). Terminal fittings (10) are inserted into the terminal accommodation chambers (22) from behind. Rectangular tab insertion holes (24) penetrates through a front wall (23) of the housing (20) and allow tabs (61) to be inserted into the terminal accommodation chambers (22). Guide slopes (29, 30) are formed by recessing and tapering an opening edge part of the tab insertion hole (22) on a front surface of the front wall (23). Detection holes (31) penetrate through the front wall (23) and communicate with corner parts of the tab insertion holes (24) so that a probe (50) for conduction test can be inserted into the terminal accommodation chambers (22) from the front. |
| US09484657B2 |
Harness connector having a power and signal cartridges
A harness connector includes a harness housing having a signal cavity and a power cavity defined by housing walls. At least one of the housing walls has a locking rail extending therefrom into the corresponding signal cavity or power cavity. Signal harness cartridges are received in the signal cavity, each holding a plurality of signal terminals. Each signal harness cartridge has a locking slot configured to receive a corresponding locking rail in a position directly behind the signal terminals to secure the signal terminals in the signal harness cartridge. A power harness cartridge is received in the power cavity that holds a plurality of power terminals. The power harness cartridge has a locking slot configured to receive a corresponding locking rail in a position directly behind the power terminals to secure the power terminals in the power harness cartridge. |
| US09484655B2 |
Connector
A connector that reduces damage of a contact portion of a contact, caused by a frame portion of a card holder when the frame portion is inserted into or extracted from a holder accommodating portion of a connector main body. A connector includes a card holder that includes a frame portion having a card accommodating portion for accommodating a card, and a connector main body that is mounted on a printed substrate and has a holder accommodating portion for accommodating the card holder. The frame portion is provided with inclined portions for suppressing deformation of contact portions of contacts protruding into the holder accommodating portion, caused by a front side of the frame portion when the card holder is inserted into or extracted from the holder accommodating portion. |
| US09484648B2 |
Connector
Disclosed is a connector mateable with a mating connector along a first direction. The connector comprises a housing and a plurality of terminals, wherein the housing includes a plurality of held portions, and the terminals correspond to the held portions, respectively. Each of the terminals includes a base portion, a first portion, a second portion and a third portion. The first portion extends directly from the base portion and is provided with a first contact portion which projects towards the second portion in a second direction perpendicular to the first direction. The second portion extends directly from the base portion and is provided with a second contact portion and a press-fitting projection. The second contact portion projects towards the first portion in the second direction and faces the first contact portion. The press-fitting projection projects towards the third portion in the second direction. The third portion extends directly from the base portion. Each of the held portions is held by the second portion and the third portion of the terminal corresponding thereto. |
| US09484647B2 |
Terminal block
A male connector (10) comprises: a male-side inner housing (30) which holds a plurality of male terminals (20) so as to expose circular portions (22) of the male terminals (20); and a partition member (40) which includes a rib (41) dividing the circular portions (22) of the plurality of the male terminals (30), and the male-side inner housing (30) and the partition member (40) are configured to be separate from each other. |
| US09484641B2 |
Female terminal
A female terminal includes a terminal body having a contact holder in a tubular shape at a front side of the terminal body, a contact member in a tubular shape which is contained inside the contact holder and into which a male terminal is inserted from a front side, and a rotary ring which is mounted to the contact holder. The contact member has a pair of holding rings provided at both ends thereof, and a diameter variable part held by a pair of the holding rings at both ends thereof, an inner diameter of the diameter variable part being set to be larger than an outer diameter of the male terminal in an initial state, and contracted to be smaller than the outer diameter of the male terminal, by twisting a pair of the holding rings. |
| US09484640B2 |
Wire with a crimp terminal with a bottom plate with an inclined portion and a raised portion
It is aimed to provide a wire with terminal in which small connection resistance and a large fixing force are easily combined and a core crimping portion is unlikely to be cracked in a crimping step of the core crimping portion. In a wire with terminal, a core crimping portion includes a bottom plate portion for supporting a core and a pair of core caulking portions sandwiching the core between the core caulking portions and the bottom plate portion. The bottom plate portion of the core crimping portion is shaped to include an inclined portion recessed gradually deeper toward the pair of core caulking portions from a first end side toward a second end side of a crimping terminal. |
| US09484637B2 |
Horn antenna with corrugated grating
A horn that radiates a radioelectric wave coming from an input waveguide, comprises a grating placed over the aperture of the horn. The waveguide comprises a horn-shaped segment, an entrance, an aperture, and a grating placed next to the aperture. It makes it possible for at least one linearly polarised electromagnetic wave to propagate between the entrance and the aperture along a first axis. The grating comprises a frame and a set of plates extending longitudinally and continuously from a first short side of the frame to a second short side of the frame, so as to form a linear polarising filter for any electromagnetic wave the electric field of which is not polarised along a second axis orthogonal to the first axis. The grating of the waveguide comprises corrugations to reinforce the filtering of the electromagnetic wave the electric field of which is not polarised along the second axis. |
| US09484635B2 |
Waveguide antenna assembly and system for electronic devices
A waveguide antenna assembly and process for transceiving signals of a predetermined radio frequency range comprising at least two collaterally aligned conductive layers configured in a conformable loop so as to form an electrically isolating channel dimensionally configured for support of the waveguide modes of the predetermined frequency range, an aperture for electromagnetically transceiving the signals, wherein the aperture extends along a surface of the electrically isolating channel such that the aperture extends between the outer edge of the inner surface of the first conductive layer and the second conductive layer, a back short spaced apart from the aperture a predetermined distance equal to a resonant length of the waveguide mode wavelength so as to provide a circuit impedance between the first conductive layer and the second conductive layer for tuning the waveguide to transceive the signals, and excitation points coupled to the aperture to propagate waveguide modes within the electrically isolating channel, which is conformable to the configuration of a supported electronic device. |
| US09484632B2 |
Diplexing and triplexing of loop antennas
An antenna system comprising a plurality of loop antenna sets with each of the plurality of loop antenna sets disposed in one of a plurality of different parallel planes with each of the planes being spaced apart from another adjacent plane and wherein loop antenna set in the plurality of loop antenna sets comprises a plurality of loop antennas and wherein the plurality of loop antennas are configured such that the near field inductive coupling between the plurality of loop antenna sets is zero. The absence of inductive coupling between the loop elements provides a frequency-independent means for multiplexing signals for transmission and reception by the multiple loop antenna system. |
| US09484630B2 |
Chip to dielectric waveguide interface for sub-millimeter wave communications link
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. |
| US09484622B2 |
Multi-band antenna
An multi-band antenna includes a base section including a first end and a second end opposite to each other, a first radiating arm and a second radiating arm extending opposite to each other from the first end and locating on two opposite sides of the base section in a longitudinal direction, and a loop conductive portion extending from the base section. The loop conductive portion includes a grounding portion locating adjacent to the second end of the base section and a connecting portion extending in the longitudinal direction. The connecting portion is located on the same side of the base section with the first radiating arm. |
| US09484621B2 |
Portable electronic device body having laser perforation apertures and associated fabrication method
A method of fabricating the body of the portable electronic device as well as the resulting portable electronic device and its body are provided to facilitate the transmission of radio frequency signals through the body of the portable electronic device. In the context of a method, at least one aperture and, in some instances, a plurality of apertures are defined by laser perforation through a conductive portion of the body of the portable electronic device. The method may also anodize the conductive portion including at least partially filling the at least one aperture with an anodization layer. As such, the conductive portion of the body of the portable electronic device has a relatively consistent, metallic appearance, even though laser perforation apertures are defined therein for supporting the transmission of radio frequency signals. |
| US09484620B2 |
Systems and methods for providing timing tracking loops in a communication system
Various embodiments are disclosed for providing timing tracking loops in a communication system. A communication system includes a delay locked loop (DLL) comprising a maximum region detector configured to identify a target channel profile comprising at least a portion of the multipath signals based on the timing information, the maximum region detector further configured to apply a weight vector to each channel tap in the target channel profile and determine a tap with a maximum power level relative to remaining channel taps in the channel profile. The system further comprises a window timing loop (WTL) adjuster configured to track a position of a channel estimation window (CEW) within an observation window corresponding to the maximum channel energy level, where the maximum channel energy level corresponds to the sum of the energy of all the taps for a given window. |
| US09484619B2 |
Switchable diversity antenna apparatus and methods
An active diversity antenna apparatus and methods of tuning and utilizing the same. In one embodiment, the active diversity antenna is used within a handheld mobile device (e.g., cellular telephone or smartphone), and enables device operation in several low frequency bands (LBs). The exemplary implementation of the active LB diversity antenna comprises a directly fed radiator portion and a grounded (coupled fed) radiator portion. The directly fed portion is fed via a feed element connected to an antenna feed. The coupled fed portion of the LB antenna is grounded, forming a resonating part of the low frequency band. A gap between the two antenna portions is used to adjust antenna Q-value. Resonant frequency tuning is achieved by changing the length of the grounded element. The LB feed element is disposed proximate the feed element of a high band diversity antenna, thus reducing transmission losses and improving diplexer operation. |
| US09484618B2 |
Antenna configuration for electronic devices
An antenna configuration is particularly suitable for use within a front panel assembly of an electronic device, such as a set-top box. According to an exemplary embodiment, the electronic device includes a chassis, a printed circuit board and an F-shaped antenna. The printed circuit board includes a ground portion and a dielectric portion. The ground portion is electrically coupled to the chassis. The F-shaped antenna includes a first portion, a second portion and a third portion. The first portion of the F-shaped antenna extends along the dielectric portion of the printed circuit board. The second portion of the F-shaped antenna is electrically coupled to the ground portion of the printed circuit board. The third portion of the F-shaped antenna extends between the ground portion and the dielectric portion of the printed circuit board and is electrically coupled to a signal processor via a reactive element (jX1, Jx2). |
| US09484617B2 |
Antenna device and method for attaching the same
An antenna device includes: a radio device for radio wave transmission; a primary radiator that has a function to radiates radio waves generated by the radio device; a parabolic reflector that reflects the radio waves radiated from the primary radiator; a shroud that shields against unnecessary radiation radio waves among the radio waves radiated from the primary radiator and reflected by the parabolic reflector; and an antenna mounting mechanism that fits the parabolic reflector to an antenna attachment pole. The shroud is arranged so as to cover at least a right and left of the parabolic reflector, the radio device and the primary radiator are arranged inside the shroud, and the antenna mounting mechanism fits the parabolic reflector to the antenna attachment pole so that the antenna attachment pole is located at a lateral center position of the parabolic reflector. |
| US09484615B2 |
Mast arrangement radio network node and related method
A mast arrangement comprises: a mast arranged for carrying a first module of a radio network node, a holding structure adapted to receive a lower portion of the mast, and a housing for a second module of the radio network node. An air inlet channel in the mast is connected to the housing via an inlet passage, and an air outlet channel in the mast is connected to the housing via an outlet passage. An interior of the housing is arranged to direct an airflow from the inlet passage along, and/or through, the second module to the outlet passage. Further, a radio network node and a method of cooling the second module in a radio network node are provided. |
| US09484613B1 |
Ka-band waveguide 2-way hybrid combiner for MMIC amplifiers with unequal and arbitrary power output ratio
One or more embodiments of the present invention describe an apparatus and method to combine unequal powers. The apparatus includes a first input port, a second input port, and a combiner. The first input port is operably connected to a first power amplifier and is configured to receive a first power from the first power amplifier. The second input port is operably connected to a second power amplifier and is configured to receive a second power from the second power amplifier. The combiner is configured to simultaneously receive the first power from the first input port and the second power from the second input port. The combiner is also configured to combine the first power and second power to produce a maximized power. The first power and second power are unequal. |
| US09484612B2 |
High-frequency signal line and electronic device including the same
A high-frequency signal line includes a dielectric body including flexible dielectric sheets laminated in a direction of lamination and also including a first line portion, a second line portion extending along the first line portion, and a third line portion connecting ends in a specified direction of the first and second line portions. In the dielectric body, a signal line extends through the first, second and third line portions, and a first ground conductor and a second ground conductor face the signal line from both sides in the direction of lamination. One or more interlayer connection conductors are pierced in the dielectric sheets to connect the first ground conductor and the second ground conductor. None of the interlayer connection conductors is provided in a portion of the third line portion that is farther in a direction opposite to the specified direction than the signal line when viewed from the direction of lamination. |
| US09484608B2 |
Switch module
A switch module includes a plurality of mounting electrodes for external connection provided on a peripheral portion of one main surface of a wiring substrate. The plurality of mounting electrodes includes a common electrode, a plurality of RF signal electrodes, a control electrode, and a power supply electrode. At least one of the power supply electrode and the control electrode is arranged between the RF signal electrodes. |
| US09484605B2 |
System and method for using exhaust gas to heat and charge a battery for a hybrid vehicle
A system and method for using exhaust gas to heat and/or charge a battery for a hybrid vehicle is provided. The system and method use an exhaust gas heat recovery (EGHR) device to heat a heat transfer fluid. The heat transfer fluid is thermally connected to a first heat exchanger to heat the battery and/or to a second heat exchanger to charge the battery if predetermined conditions are met. |
| US09484600B2 |
Electrolyte for sodium secondary battery and sodium secondary battery employing the same
Provided are an electrolyte for a sodium secondary battery, and a sodium secondary battery employing the same, and more particularly, a sodium secondary battery including an anode containing sodium, a cathode containing a transition metal, and a sodium ion conductive solid electrolyte provided between the anode and the cathode. The cathode is impregnated with a mixed salt electrolyte containing a molten sodium salt and an electrolyte additive, and the electrolyte additive contains a non-halogen sodium salt and a metal halide compound simultaneously. |
| US09484598B2 |
Electrolyte for secondary battery and lithium secondary battery including the same
Disclosed are an electrolyte for a lithium secondary battery which includes a non-aqueous solvent and a lithium salt, wherein the non-aqueous solvent includes a cyclic carbonate and a linear solvent, wherein an amount of the cyclic carbonate in the non-aqueous solvent is in the range of 1 wt % to 30 wt % based on a total weight of the non-aqueous solvent and a lithium secondary battery including the same. |
| US09484597B2 |
Sulfide solid electrolyte material, lithium solid-state battery, and method for producing sulfide solid electrolyte material
A sulfide solid electrolyte material contains glass ceramics that contains Li, A, X, and S, and has peaks at 2θ=20.2° and 23.6° in X-ray diffraction measurement with CuKα line. A is at least one kind of P, Si, Ge, Al, and B, and X is a halogen. A method for producing a sulfide solid electrolyte material includes amorphizing a raw material composition containing Li2S, a sulfide of A, and LiX to synthesize sulfide glass, and heating the sulfide glass at a heat treatment temperature equal to or more than a crystallization temperature thereof to synthesize glass ceramics having peaks at 2θ=20.2° and 23.6° in X-ray diffraction measurement with CuKα line, in which a ratio of the LiX contained in the raw material composition and the heat treatment temperature are controlled to obtain the glass ceramics. |
| US09484594B2 |
Metal fluoride compositions for self formed batteries
The described invention provides compositions related to an electronically insulating amorphous or nanocrystalline mixed ionic conductor composition comprising a metal fluoride composite to which an electrical potential is applied to form 1) a negative electrode, and 2) a positive electrode, wherein the negative electrode and positive electrode are formed in situ. |
| US09484593B2 |
Stack-folding type electrode assembly
The present disclosure provides a stack-folding type electrode assembly in which a plurality of full cells or bicells as unit cells is stacked on top of each other and surrounded by a second separator, each cell including a positive electrode, a negative electrode, and a first separator interposed between the positive electrode and the negative electrode, wherein a first binder is coated on at least a partial surface of the first separator, a second binder is coated on at least a partial surface of the second separator, and a content of the second binder is higher than a content of the first binder, to inhibit a loose phenomenon inside a battery, make the battery less prone to expansion, and have deformation resistance to an external impact. |
| US09484592B2 |
Battery module having structure of improved stability and high cooling efficiency
Disclosed herein is a battery module including a battery cell stack configured to have a rectangular parallelepiped structure in which two or more plate-shaped battery cells, each of which has electrode terminals formed at one side thereof, are stacked and a breadth of one surface of the battery cell stack at which the electrode terminals of the battery cells are disposed is smaller than a width and a height of each major surface of the battery cell stack, a first module case bent to surround two relatively large major surfaces of the battery cell stack and one surface of the battery cell stack opposite to the surface of the battery cell stack at which the electrode terminals of the battery cells are disposed, among six surfaces of the battery cell stack and a surface, the first module case being made of a thermally conductive material that is capable of dissipating heat generated from the battery cells during charge and discharge of the battery cells, and a second module case bent to surround side surfaces of the battery cell stack adjacent to the two major surfaces of the battery cell stack and the surface of the battery cell stack at which the electrode terminals of the battery cells are disposed, the second module case being fastened to the first module case, the second module case being provided with through holes, through which the electrode terminals of the battery cells protrude outward, the second module case being made of an electrically insulative material. |
| US09484589B1 |
Microbial fuel cell with sediment agitator
A microbial fuel cell comprising: an anode; an anode chamber configured to house the anode and an oxygen-reduced, nutrient-rich solution from a sediment bottom of a natural water body, wherein the anode chamber shields the anode from surrounding oxygen-rich water; a cathode disposed outside the anode chamber in the oxygen-rich water and electrically coupled in series to the anode via an electrical load; and an agitator configured to periodically agitate the sediment bottom to increase the quantity of nutrients in the nutrient-rich solution. |
| US09484588B2 |
Compound, composition including compound, composite formed therefrom, electrode using composition or composite, composite membrane using composite, and fuel cell including at least one selected from electrode and composite membrane
A compound including a cage-type structure of silsesquioxane wherein a group represented by Formula 1 or a salt thereof is directly linked to at least one silicon atom of the silsesquioxane, a composition including the compound, a composite formed therefrom, electrodes and an electrolyte membrane that include the composite, a method of preparing the compound, and a fuel cell including the electrodes and the electrolyte membrane. wherein in Formula 1, n is 1 or 2. |
| US09484577B2 |
Positive electrode materials for lithium ion batteries and process for preparing the same
Provided are a positive electrode material for lithium ion batteries and a process for preparing the same. The positive electrode material for lithium ion batteries comprises a composite positive electrode material consists of LiCoO2 and an auxiliary positive electrode material, the general formula of the auxiliary positive electrode material is LiCo1-x-yNixMnyO2, wherein 0 |
| US09484576B2 |
Particle-based silicon electrodes for energy storage devices
Electrodes, energy storage devices using such electrodes, and associated methods are disclosed. In an example, an electrode for use in an energy storage device can comprise porous disks comprising a porous material, the porous disks having a plurality of channels and a surface, the plurality of channels opening to the surface; and a structural material encapsulating the porous disks; where the structural material provides structural stability to the electrode during use. |
| US09484573B2 |
Composite anode of lithium-ion batteries
The present invention provides a composite anode for a battery comprising a copper current collector working electrode, at least one anode material comprising at least one of a carbon, a silicon, a conductive agent, and combinations thereof, wherein at least one anode material is deposited on a surface of the copper current collector working electrode to form the composite anode for a battery. An electrophoretic method for making this anode is provided. A lithium-ion battery having the composite anode is disclosed. |
| US09484569B2 |
Electrochemical slurry compositions and methods for preparing the same
Embodiments described herein generally relate to semi-solid suspensions, and more particularly to systems and methods for preparing semi-solid suspensions for use as electrodes in electrochemical devices such as, for example batteries. In some embodiments, a method for preparing a semi-solid electrode includes combining a quantity of an active material with a quantity of an electrolyte to form an intermediate material. The intermediate material is then combined with a conductive additive to form an electrode material. The electrode material is mixed to form a suspension having a mixing index of at least about 0.80 and is then formed into a semi-solid electrode. |
| US09484566B2 |
Battery pack
A battery pack includes a plurality of secondary batteries, each including a first electrode terminal and a second electrode terminal protruding from a cap plate, and a plurality of busbars, each electrically coupling first electrode terminal of one of the secondary batteries and the second electrode terminal of an adjacent one of the secondary batteries, wherein the busbars and the second electrode terminals are forcibly deformed to be coupled to each other, and wherein the busbars are welded to the first electrode terminals. |
| US09484564B2 |
Electrical energy storage
An electric energy storage device for an electric vehicle, which storage device including at least one battery module having a plurality of especially flat and substantially plate-shaped battery cells which are electrically connected to one another and which are arranged next to one another or one above the other between at least two pressure plates in at least one stack. At least one battery cell and/or the battery module is surrounded by a plastic structure. |
| US09484559B2 |
Battery cell assembly
A battery cell assembly having first and second frame members is provided. The first frame member has a first rectangular ring-shaped body and a first coupler portion. The first coupler portion has a first tab member with a first metal trim clip member coupled thereto. The second frame member has a second rectangular ring-shaped body and a second coupler portion. The second coupler portion has first and second substantially flat walls and first and second peripheral wall portions defining an interior region. The second substantially flat wall has an aperture extending therethrough. The first metal trim clip member is disposed through the aperture and into the interior region of the second coupler portion, and engages an inner surface of the second substantially flat wall to couple the second frame member to the first frame member. |
| US09484558B2 |
Battery cell and battery module using the same
A battery cell and a battery module using the same that allow the battery cell to be extended without a limit in the number of battery cells is provided. The battery cell includes a body, at least one rail installed in the body, and at least one rail groove formed on the other surface of the body where the rail is not installed. |
| US09484555B2 |
Organic light emitting display device including a non-light emitting region, light emitting region and photochromic layer
An organic light emitting display device includes a substrate having a non-light emitting region and a light emitting region, a photochromic layer in a path of light that is emitted from the light emitting region and a light blocking layer on the photochromic layer, wherein the light blocking layer comprises a plurality of light blocking patterns that are spaced from each other, the light blocking patterns overlap the light emitting region, and a space between adjacent light blocking patterns exposes the non-light emitting region. |
| US09484554B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus that has high-resolution and high-brightness includes a substrate comprising a major surface; an insulating layer disposed over the substrate and comprising a first inclined surface which is inclined with respect to the major surface and faces away from the substrate; a reflective first pixel electrode disposed over the first inclined surface and configured to cover a portion of the first inclined surface; a first intermediate layer disposed over the first pixel electrode and comprises a light emission layer; and a reflective opposite electrode disposed over the first intermediate layer. |
| US09484550B2 |
Light-emitting element display device
A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer. |
| US09484549B2 |
Display device
A display device includes a first substrate including a display area and a non-display area, the display area including a pixel including a first electrode, a light emission layer, and a second electrode; a sealing member facing the first substrate; and a first conducting member in the display area, the first conducting member being coupled to the first electrode, where the sealing member includes: a first conductive layer coupled to the first conducting member; an insulating layer on the first conductive layer; and a second conductive layer on the insulating layer, the second conductive layer being coupled to the second electrode. |
| US09484541B2 |
Organic electroluminescent materials and devices
A compound having a formula M(LA)x(LB)y(LC)z, where ligand LA is ligand LB is and ligand LC is is disclosed. In the structure of M(LA)x(LB)y(LC)z, M is a metal; x is 1, or 2; y and z are 0, 1, or 2; X1, X2, X3, X4, X5, X6, X7, and X8 are each independently C or N; rings C and D are each independently a 5 or 6-membered carbocyclic or heterocyclic ring; two adjacent RB form a six-member aromatic carbocyclic or heterocyclic ring E fused to ring B and, when ring E is heterocyclic, the only heteroatom is nitrogen; and ring E can be further substituted by RE. Additionally, any adjacent substituents R11, R12, RB, RC, RD, RE, R1, R2, R3, R4, R′ and R″ are optionally joined to form a ring. Formulations and devices that include the compound of formula M(LA)x(LB)y(LC)z, are also described. |
| US09484537B2 |
Organic photo diode with dual electron blocking layers
Embodiments of forming an image sensor with an organic photodiode are provided. The organic photodiode uses dual electron-blocking layers formed next to the anode of the organic photodiode to reduce dark current. By using dual electron-blocking layers, the values of highest occupied molecular orbital (HOMO) for the neighboring anode layer and the organic electron-blocking layer are matched by one of the dual electron-blocking layers to form a photodiode with good performance. The values of the lowest occupied molecular orbital (LOMOs) of the dual electron-blocking layers are selected to be lower than the neighboring anode layer to reduce dark current. |
| US09484533B2 |
Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells
A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO. |
| US09484531B2 |
Perpendicular magnetic anisotropy BCC multilayers
A magnetic material includes a cobalt layer between opposing iron layers. The iron layers include iron and are body-centered cubic (BCC), the cobalt layer comprises cobalt and is BCC or amorphous, and the magnetic material has a perpendicular magnetic anisotropy (PMA). |
| US09484528B2 |
Memory element and memory apparatus
A memory element includes a layered structure: a memory layer having a magnetization direction changed depending on information, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer. |
| US09484524B2 |
Piezoelectric compositions
Piezoelectric compositions are provided wherein mechanical and piezoelectric properties can be separately modulated. Preferred compositions include resin blends that comprise: (a) a piezoelectrically active polymer and (b) a matrix polymer, methods of making, and use of such resin blends. Advantages of preferred resin blends of the invention can include high piezoelectricity, mechanical strength and flexibility, convenient fabrication process, and high sensitivity at high temperatures. |
| US09484522B2 |
Piezoelectric energy harvester device with curved sidewalls, system, and methods of use and making
The present invention relates to an energy harvester device, which includes an elongate, planar resonator beam comprising a piezoelectric material and side walls extending between first and second ends; a base connected to the resonator beam at the first end with the second end being freely extending from the base as a cantilever; and a mass attached to the second end of the resonator beam. The side walls are continuously curved within the plane of the resonator beam. Also disclosed are a system containing the device, and methods of using and making the device. |
| US09484517B2 |
Seebeck/peltier bidirectional thermoelectric conversion device using nanowires of conductive or semiconductive material
The invention relates to Seebeck/Peltier bidirectional thermoelectric conversion devices and in particular to devices employing nanowires of conductive or semiconductive material defined on a substrate by common planar technologies. |
| US09484515B2 |
Semiconductor light emitting module comprising an exposed plate surface
Provided are a semiconductor light emitting module and a method of manufacturing the same, which allow achieving high luminance light emission as well as lightweight and compact features. In a semiconductor light emitting module (101), a projecting portion (202) serving as a reflecting member is formed on a metal thin plate (102) to surround a semiconductor light emitting element (104). The semiconductor light emitting element (104) is connected to a printed board (103) by using a wire (201), for example. The projecting portion (202) is formed by pressing and bending the metal thin plate (102) from a back surface, for example, to surround the element and to be higher than the semiconductor light emitting element (104). |
| US09484514B2 |
Light-emitting device
A light-emitting device including: a base; light-emitting elements arranged on the base at intervals in an array along a predetermined direction of the base; and conductive-wiring parts formed on first and second sides of the array of the light-emitting elements on the base. The conductive-wiring parts are discretely formed along the predetermined direction of the base, each of the conductive-wiring parts relaying electrical connection between the light-emitting elements, and the number of the conductive-wiring parts arranged per light-emitting element on each of the first and second sides of the array of the light-emitting elements is two or more. |
| US09484509B2 |
Lighting device and method of manufacturing the same
In a first aspect of the present invention, a lighting device includes a light-emitting element, a frame including a phosphor that can be excited by light emitted from the light-emitting element, the frame having an inner side surface surrounding the light-emitting element and an outer side surface being positioned outside the inner side surface that demarcates a quadrilateral area, and a light-transmitting resin arranged in the quadrilateral area demarcated by the inner side surface of the frame and sealing the light-emitting element that is positioned inside the quadrilateral area, and the light-transmitting resin being further provided in contact with an outer side surface of the frame. In some embodiments, it is disclosed that the light-transmitting resin provided in contact with the outer side surface of the frame may include a diffuser. |
| US09484507B2 |
Light emitting device
A light emitting device comprises a package having a recess; a light emitting element mounted in the recess of the package; a light transmissive member provided above the light emitting element; a sealing resin that seals the recess of the package; and a fluorescent material contained in the sealing resin. The fluorescent material is distributed to a side of the light emitting element in a greater amount than to above the light emitting element, a side surface of the light emitting element is exposed to the sealing resin, and a portion of the light transmissive member protrudes from the sealing resin. |
| US09484506B2 |
LED display and manufacturing method thereof
A manufacturing method of a LED display is provided. A temporary substrate is provided, wherein the temporary substrate has a first adhesive layer and a plurality of first, second and third LED chips mounted on the first adhesive layer. A first transparent substrate is provided, the transparent substrate has a plurality of pixels disposed thereon, and each of the pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel respectively surrounded by a light-insulating structure. Then, the temporary substrate and the first transparent substrate are bonded together, such that each of the first, second and third LED chips is correspondingly mounted in each of the first sub-pixels, the second sub-pixels and the third sub-pixels. After that, the temporary substrate is removed. A LED display manufactured by said method is also provided. |
| US09484493B2 |
Rectifying unit, a light emitting diode device, and the combination thereof
A light emitting diode device includes a substrate; a first conducting terminal and a second conducting terminal receiving the alternative current signal; a first and a third light-emitting diode groups disposed on the substrate including a plurality of light emitting diodes electrically connecting with the first conducting terminal and the second conducting terminal and emitting light during the positive half power cycle; a second and the third light-emitting diode groups disposed on the substrate including a plurality of light emitting diodes electrically connecting with the first conducting terminal and the second conducting terminal and emitting light during the negative half power cycle; wherein one light emitting diode in the first light-emitting diode group includes more than three conductive connecting points to electrically connect to the second light-emitting diode group and the third light-emitting diode group. |
| US09484490B2 |
Epitaxy substrate, method for producing an epitaxy substrate and optoelectronic semiconductor chip comprising an epitaxy substrate
An epitaxy substrate (11, 12, 13) for a nitride compound semiconductor material is specified, which has a nucleation layer (2) directly on a substrate (1) wherein the nucleation layer (2) has at least one first layer (21) composed of AlON with a column structure. A method for producing an epitaxy substrate and an optoelectronic semiconductor chip comprising an epitaxy substrate are furthermore specified. |
| US09484486B2 |
Pin diode and manufacturing method thereof, and x-ray detector using pin diode and manufacturing method thereof
Provided herein is a PIN diode, a manufacturing method thereof, an x-ray detector using the PIN diode, and a manufacturing method thereof, the PIN diode manufacturing method according to an embodiment of the present disclosure including forming a lower electrode layer, and forming a lower electrode by etching the lower electrode layer; depositing a PIN layer for formation of a PIN structure above the lower electrode, and depositing an upper electrode layer for formation of the upper electrode above the PIN layer; forming a photo resist pattern above the upper electrode layer, and forming the upper electrode by etching the upper electrode layer having the photo resist pattern as a mask; forming the PIN structure by etching the PIN layer; etching an edge area of the upper electrode having the photo resist pattern as a mask; and removing the photo resist pattern. |
| US09484485B2 |
Solar cell, manufacturing method therefor, solar-cell module, and manufacturing method therefor
Provided is a solar cell including a photoelectric conversion section having a first principal surface and a second principal surface, and a collecting electrode formed on the first principal surface of photoelectric conversion section. The photoelectric conversion section includes a semiconductor-stacked portion including a semiconductor junction, a first electrode layer which is a transparent electrode layer formed on the first principal surface side of the semiconductor-stacked portion, and a second electrode layer formed on the second principal surface side of the semiconductor-stacked portion. The collecting electrode includes a first electroconductive layer and a second electroconductive layer. In the manufacturing method, an insulating layer is formed on the first electrode layer, and the electrode layer exposed to the surface of the insulating layer-non-formed region is removed to eliminate a short circuit between the first and second electrode layers. The second electroconductive layer is formed by plating. |
| US09484471B2 |
Compound varactor
Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein. |
| US09484470B2 |
Method of fabricating a GaN P-i-N diode using implantation
A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region |
| US09484468B2 |
Thin film transistor and manufacturing method thereof, array substrate, and display apparatus
The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. The thin film transistor of the present invention comprises a gate, a gate insulation layer, a semiconductor active region, and a source and a drain connected with the semiconductor active region, and further comprises a surface charge transfer layer in contact with the semiconductor active region, the surface charge transfer layer is located above or below the semiconductor active region, and is used for causing the semiconductor active region to generate a large number of holes or electrons therein without changing the lattice structure of the semiconductor active region. In the thin film transistor, charge transfer occurs between the semiconductor active region and the surface charge transfer layer so that the doped semiconductor active region is formed, thus the performance of the thin film transistor is significantly improved. |
| US09484466B2 |
Thin film transistor
A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value. |
| US09484458B2 |
Semiconductor device including first and second trenches having substantially equal depths
A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates. |
| US09484457B2 |
Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines
A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime. |
| US09484456B2 |
Semiconductor device and manufacturing method of the same
A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. |
| US09484455B2 |
Isolation NLDMOS device and a manufacturing method therefor
An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole. |
| US09484452B2 |
Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate. A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm. |
| US09484451B2 |
MOSFET active area and edge termination area charge balance
A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson. |
| US09484449B2 |
Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers
Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both. |
| US09484447B2 |
Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region. |
| US09484445B2 |
Semiconductor device and semiconductor device manufacturing method
An n-type low lifetime adjustment region is provided in a portion inside an n− type drift region deeper than the bottom surface of a termination p-type base region or p-type guard ring from a substrate front surface, separated from the termination p-type base region and the p-type guard ring. The carrier lifetime of the n-type low lifetime adjustment region is shorter than the carrier lifetime of the n− type drift region. Because of this, it is possible to provide a reverse blocking IGBT such that it is possible to suppress both a high temperature reverse leakage current and an increase in turn-off loss, while suppressing deterioration in the trade-off relationship between the turn-off loss and the on-state voltage. |
| US09484437B2 |
Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region. |
| US09484436B2 |
Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region. |
| US09484434B2 |
Inducement of strain in a semiconductor layer
Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces. |
| US09484433B2 |
Method of manufacturing a MISFET on an SOI substrate
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. |
| US09484432B2 |
Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired. |
| US09484430B2 |
Back-end transistors with highly doped low-temperature contacts
A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. |
| US09484428B2 |
Non-planar exciton transistor (BiSFET) and methods for making
A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer. |
| US09484427B2 |
Field effect transistors having multiple effective work functions
Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions. |
| US09484423B2 |
Crystalline multiple-nanosheet III-V channel FETs
A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed. |
| US09484422B2 |
High-voltage metal-oxide semiconductor transistor
The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate. |
| US09484421B2 |
Semiconductor device
A semiconductor device according to an embodiment includes a nitride semiconductor layer, a plurality of source electrodes provided on the nitride semiconductor layer, a plurality of drain electrodes, a plurality of gate electrodes, a first interconnection having a first distance from the nitride semiconductor layer and electrically connecting the source electrodes, a second interconnection electrically connecting the gate electrodes, and a third interconnection having a third distance from the nitride semiconductor layer and electrically connecting the drain electrodes. Each of the drain electrodes are provided between the source electrodes. Each of the gate electrodes are provided between each of the source electrodes and each of the drain electrodes. The third distance is larger than the first distance. |
| US09484420B2 |
Thin film transistor substrate, liquid crystal display having same, and method of manufacturing the same
A display apparatus includes a thin film transistor substrate, a substrate facing the thin film transistor substrate, and a liquid crystal layer. The thin film transistor substrate includes an insulating substrate, a gate electrode disposed on a surface of the insulating substrate, a gate insulating layer covering the gate electrode, a semiconductor layer disposed on the gate insulating layer, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode. One of the source electrode and the drain electrode is spaced apart from the gate electrode in a plan view. The gate electrode includes a side surface inclined with respect to the surface of the insulating substrate and is partially overlapped with a portion of the source electrode or the drain electrode in a direction perpendicular to the side surface of the gate electrode. |
| US09484419B2 |
Oxide thin film, method for post-treating oxide thin film and electronic apparatus
Provided are an oxide thin film, a method for post-treating an oxide thin film and an electronic apparatus. An oxide thin film is an oxide thin film with a single layer including a metal oxide, and the physical properties of the oxide thin film may change in the thickness direction thereof. |
| US09484418B2 |
Semiconductor device
The semiconductor device includes a substrate, a first GaN field effect transistor, a second GaN field effect transistor, and a GaN diode. The first GaN field effect transistor is disposed on or above the substrate, and the first GaN field effect transistor is a depletion mode field effect transistor. The second GaN field effect transistor is disposed on or above the substrate, and the second GaN field effect transistor is an enhancement mode field effect transistor. The GaN diode is disposed on or above the substrate. The first GaN field effect transistor, the second GaN field effect transistor, and the GaN diode are disposed on or above a same side of the substrate and electrically connected to each other. |
| US09484417B1 |
Methods of forming doped transition regions of transistor structures
Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region. |
| US09484416B2 |
Silicon carbide substrate, semiconductor device and methods for manufacturing them
A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and oxygen atoms are present in the one main surface at a ratio of not less than 3 at % and not more than 30 at %. |
| US09484415B2 |
Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region. |
| US09484410B2 |
Lateral MOS power transistor having front side drain electrode and back side source electrode
A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed. |
| US09484405B1 |
Stacked nanowire devices formed using lateral aspect ratio trapping
A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings. |
| US09484403B2 |
Boron rich nitride cap for total ionizing dose mitigation in SOI devices
A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. |
| US09484398B2 |
Metal-insulator-metal (MIM) capacitor
There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack. |
| US09484396B2 |
Array substrate, method for manufacturing the same, display device and electronic product
The present disclosure provides an array substrate, including a plurality of sub-pixel regions arranged in a matrix form. Each sub-pixel region may at least include a first thin film transistor (TFT) and a second thin film transistor. The first thin film transistor may include a first gate electrode, a first source electrode and a first drain electrode. The second thin film transistor may include a second gate electrode, a second source electrode and a second drain electrode. The first gate electrode and at least one of the second source electrode and the second drain electrode may be provided on a same layer. The second gate electrode and at least one of the first source electrode and the first drain electrode may be provided on a same layer. The second gate electrode and the first source electrode may be integrated together. |
| US09484395B2 |
Method of manufacturing organic light emitting display panel
The present invention relates to a method of manufacturing an organic light emitting display panel. The method includes forming a light shielding layer on a substrate, forming a first oxide semiconductor and a second oxide semiconductor on the light shielding layer, and forming a gate insulating layer and a gate overlapping a portion of the first oxide semiconductor and a whole of the second oxide semiconductor. The method further includes performing an etching so that the portion of the first oxide semiconductor has conductivity, forming a first contact hole in the light shielding layer and forming a second contact hole in the first oxide semiconductor, forming a driving power line connected to the light shielding layer through the first contact hole, and forming source/drain electrodes connected to the first oxide semiconductor through the second contact hole. |
| US09484394B2 |
Display device and electronic apparatus
A display device includes a first substrate including an organic layer forming region, and an organic layer non-forming region which is provided on an outer side of the organic layer forming region; and a first partitioning wall which is provided between the organic layer forming region and the organic layer non-forming region on the first substrate. |
| US09484393B2 |
Array substrate of a display device, manufacturing method thereof
An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises a base substrate and a thin-film transistor (TFT) unit, a color filter and a planarization protective layer disposed on the base substrate. The planarization protective layer is electrically connected with a drain electrode of the TFT unit and is conductive. The array substrate has the advantages of simplifying the layer structures of the array substrate, reducing the manufacturing difficulty of the array substrate, and improving the production yield of the array substrate. |
| US09484392B2 |
Flat panel display having low reflective black matrix and method for manufacturing the same
A flat panel display having a low reflective black matrix and a method for manufacturing the same are provided. The flat panel display includes a substrate having an open area and a non-open area; a hazy layer disposed in the non-open area on the inner surface of the substrate; a black matrix stacked on the hazy layer; a driving element disposed in the non-opening area; and a display element disposed in the open area and driven by the driving element. |
| US09484387B2 |
Manufacturing method of semiconductor device and semiconductor device
A method of manufacturing a stacked semiconductor device having two or more wafers may include forming a conductor on an upper wafer, the conductor configured to electrically connect input terminals together that have no input protection circuit against ESD; forming front side micro-bumps on a front side of the upper wafer, the front side micro-bumps configured to electrically connect to back side micro-bumps on the upper wafer; forming a TSV structure, the TSV structure configured to facilitate electrical connections between the front and the back side of the upper wafer; forming back side micro-bumps on the back side of the upper wafer, the back side micro-bumps configured to electrically connect with front side micro-bumps on the lower wafer; stacking the upper wafer on the lower wafer; and separating the conductor such that each of the input terminals are electrically independent from other ones of the input terminals. |
| US09484384B2 |
Array substrate of X-ray sensor and method for manufacturing the same
An array substrate of an X-ray sensor and a method for manufacturing the same are provided, the method comprising a step of forming a thin-film transistor element and a photodiode sensor element, wherein the step of forming the thin-film transistor element comprises: forming a gate electrode (1001) on an base substrate (1000) by a mask process; depositing a gate insulating layer (1005) on the base substrate (1000) on which the gate electrode (1001) is formed; the step of forming the photodiode sensor element comprises: forming an ohmic contact layer (1002) on the base substrate (1000) through the same mask process while forming the gate electrode (1001); forming a semiconductor layer (1003) and a transparent electrode (1004) through a mask process on the substrate (1000) on which the ohmic contact layer (1002) is formed; depositing the gate insulating layer on the base substrate on which the semiconductor layer (1003) and the transparent electrode (1004) are formed while depositing the gate insulating layer (1005) on the base substrate (1000) on which the gate electrode (1001) is formed. A gate pattern and an ohmic contact layer are formed through the same mask process, and a passivation layer substitutes a channel blocking layer to reduce the number of the mask processes and simplify the manufacturing process and improve throughput and yield of the product. |
| US09484381B2 |
Display device and method for driving display device
A display device includes a pixel which includes a first photosensor portion having a first photodiode for detecting visible light, which is provided together with a display element portion; and a pixel which includes a second photosensor portion having a second photodiode for detecting infrared rays, which is provided together with another display element portion. The second photosensor portion detects infrared rays included in external light, and selects an imaging element and adjusts sensitivity in accordance with the amount of infrared rays detected by the second photosensor portion. |
| US09484379B2 |
Rear-face illuminated solid state image sensors
A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit. |
| US09484376B2 |
Semiconductor isolation structure and manufacturing method thereof
The present disclosure provides a method for manufacturing a semiconductor isolation structure, including providing a substrate with a top surface; forming a patterned mask over the top surface; forming a trench through the patterned mask in the substrate by a directional etch comprising nitrogen-containing substance, wherein an aspect ratio of the trench is formed to be greater than about 18, and a ratio of a width of a narrowest portion and a width of a widest portion of the isolation region is formed to be greater than about 0.7; and filling the trench with insulating materials. The present disclosure also provides an image sensing device, including a radiation sensing region with a first isolation region separating adjacent radiation detecting units and a peripheral region, wherein an aspect ratio of the first isolation region is greater than about 18. |
| US09484373B1 |
Hard mask as contact etch stop layer in image sensors
An image sensor includes a semiconductor material with a photodiode disposed in the semiconductor material, and a transfer gate disposed adjacent to an edge of the photodiode. A dielectric layer is also disposed between the semiconductor material and the transfer gate. A hard mask is disposed in an encapsulation layer and lateral bounds of the hard mask are coextensive with lateral bounds of the transfer gate. A first contact trench extends through the encapsulation layer and through the dielectric layer and contacts the semiconductor material. A second contact trench extends through the encapsulation layer and through the hard mask and contacts the transfer gate. |
| US09484371B2 |
Solid-state image pickup device and method of driving the same
An image sensor comprising a semiconductor substrate with a plurality of photoelectric conversion elements and a charge-voltage conversion element. The plurality of photoelectric conversion elements further includes at least a first photoelectric conversion element and a second photoelectric conversion element. The charge-voltage conversion element is shared by the first and second photoelectric conversion elements. The image sensor further includes a first charge accumulation element adjacent to the first photoelectric conversion element and at least a portion of the first charge accumulation element overlaps a charge accumulation region of the first photoelectric conversion element. The image sensor also includes a second charge accumulation element adjacent to the second photoelectric conversion element and at least a portion of the second charge accumulation element overlaps a charge accumulation region of the second photoelectric conversion element. Each of the plurality of photoelectric conversion is configured to receive light entered from a first surface of the semiconductor substrate. The first and second charge accumulation elements are formed on a second surface of the semiconductor substrate and the second surface is opposed to the first surface. |
| US09484367B2 |
Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics
A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. |
| US09484366B2 |
Photodiode array
A photodiode array has a plurality of photodetector channels formed on an n-type substrate having an n-type semiconductor layer, with a light to be detected being incident to the photodetector channels. The array comprises: a p−-type semiconductor layer on the n-type semiconductor layer of the substrate; resistors is provided to each of the photodetector channels and is connected to a signal conductor at one end thereof; and an n-type separating part between the plurality of photodetector channels. The p−-type semiconductor layer forms a pn junction at the interface between the substrate, and comprises a plurality of multiplication regions for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels. |
| US09484365B2 |
Semiconductor device including switch electrically connected to signal line
To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed. |
| US09484363B2 |
Liquid crystal display and method of manufacturing the same
A liquid crystal display and a method of manufacturing the same are provided. The liquid crystal display includes an insulating substrate, a gate electrode formed on the insulating substrate, an oxide semiconductor layer formed on the gate electrode, an etch stopper formed on the oxide semiconductor layer in a channel area, a common electrode formed on the insulating substrate, source and drain electrodes separated from each other on the etch stopper and extending to an upper portion of the oxide semiconductor layer, a passivation layer formed on the etch stopper, the common electrode, the source and drain electrodes, and a pixel electrode formed on the passivation layer and connected to the drain electrode. |
| US09484361B2 |
Array substrate, manufacturing method thereof, display panel and display device
The present disclosure provides an array substrate, a manufacturing method thereof, a display panel and a display device. A base substrate of the array substrate or a buffer layer on the base substrate is provided with a plurality of recessed sections, each recessed section is provided with at least one inclined surface, and a thin film transistor (TFT) is arranged at the inclined surface of each recessed section. The recessed sections are divided into at least two types. In the recessed sections of different types, angles between a horizontal surface of the array substrate and the inclined surfaces on which the TFTs are arranged are different from each other. |
| US09484359B2 |
MOSFET with work function adjusted metal backgate
An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. |
| US09484355B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure. |
| US09484353B1 |
Memory device and method for fabricating the same
A memory device includes a first insulating layer, a second insulating layer, an isolation layer, a floating gate electrode, a control gate electrode, a channel layer and a tunneling oxide layer. The second insulating layer is disposed adjacent to and substantially parallel with the first insulating layer to form an interlayer space there between. The isolation layer is disposed in the interlayer space to form a non-straight angle with the first insulating layer, and divides the interlayer space into a first recess and a second recess. The floating gate electrode is disposed in the first recess. The control gate electrode is disposed in the second recess. The channel layer is disposed on an opening surface of the first recess and forms a non-straight angle with the first insulating layer. The tunneling oxide layer is disposed between the channel layer and the floating gate electrode. |
| US09484348B2 |
Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion. |
| US09484347B1 |
FinFET CMOS with Si NFET and SiGe PFET
A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin. |
| US09484346B2 |
Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure includes a semiconductor layer having a first and a second surface, and an interlayer dielectric (ILD) defining a first metal gate and a second metal gate over the first and second surface, respectively. The first and second metal gate include a first SAC hard mask and a second SAC hard mask, respectively, wherein the first the second SAC hard mask have opposite stress to channel regions underneath the first and second metal gate, respectively. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming metal gate recesses, forming metal gates and SAC hard masks in the metal gate recesses, respectively. |
| US09484343B2 |
Insulated gate bipolar transistor with a free wheeling diode
A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n− semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated. |
| US09484339B2 |
Smart semiconductor switch
A semiconductor device may comprise a semiconductor substrate, which is doped with dopants of a first doping type and includes a semiconductor layer adjoining a top surface of the semiconductor substrate, the semiconductor layer being doped with dopants of a second doping type; a MOS transistor being integrated in the first semiconductor region; and a protection circuit electrically connected to a portion of the first semiconductor layer and the gate electrode and being configured to charge the gate electrode dependent on a current passing from the first semiconductor layer to a drain electrode of the MOS transistor. |
| US09484335B2 |
Semiconductor device with buried bitline and method for fabricating the same
A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls. |
| US09484334B2 |
Semiconductor device and method of forming directional RF coupler with IPD for additional RF signal processing
A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property. |
| US09484333B2 |
Multi-chip module with stacked face-down connected dies
A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate. |
| US09484331B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate. |
| US09484327B2 |
Package-on-package structure with reduced height
To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window. |
| US09484326B2 |
Apparatuses having stacked devices and methods of connecting dice stacks
Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths. |
| US09484324B2 |
Method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate. |
| US09484322B1 |
Semiconductor packages with sliding interconnect structure
A semiconductor package includes a first substrate including a plurality of first connecting portions disposed thereon, a second substrate disposed on a portion of the first substrate to be adjacent to the first connecting portions and including a plurality of conductive contact rails disposed thereon, and a plurality of conductive cantilevers respectively placed in contact with surfaces of the conductive contact rails so that one end portion of each conductive cantilever is electrically coupled to one of the first connecting portions and the other end portion slides along one of the conductive contact rails. |
| US09484316B2 |
Semiconductor devices and methods of forming thereof
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced. |
| US09484315B2 |
Chip structure having bonding wire
A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy. |
| US09484314B2 |
Word line hook up with protected air gap
A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word lines, and forming a dummy structure directly opposite an air gap between neighboring word lines. Subsequently, the contact pad structures are cut into individual contact pads by a contact pad cut that intersects the dummy structure. |
| US09484312B2 |
Inductor shielding structure, integrated circuit including the same and method of forming the integrated circuit
An inductor shielding structure includes a first conductive layer including a plurality of first conductive lines having a first width and a plurality of second conductive lines having a second width. The inductor shielding structure further includes a second conductive layer over the first conductive layer. The second conductive layer includes at least one third conductive line having a third width and a plurality of fourth conductive lines having a fourth width. Each conductive line of the at least one third conductive line is parallel to each conductive line of the plurality of first conductive lines. Each conductive line of the plurality of fourth conductive lines is parallel to each conductive line of the plurality of second conductive lines. The first width is different from the second width, or the third width is different from the fourth width. |
| US09484308B2 |
Semiconductor device
A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation. |
| US09484304B2 |
Semiconductor device and method for producing same
In order to prevent the detachment of a film which is a constituent part of an interlayer-insulating film, and to prevent a decline in the device properties of a semiconductor device, a semiconductor device is provided with an interlayer-insulating film having, in this order, a carbon-containing silicon nitride (SiCN) film, a first silicon nitride film, and a silicon oxide film or a carbon-containing silicon oxide (SiOC) film. |
| US09484300B2 |
Device resulting from printing minimum width semiconductor features at non-minimum pitch
Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape. |
| US09484294B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device of the present invention includes a bonding target and an electrode terminal bonded to the bonding target. The electrode terminal and the bonding target are bonded by ultrasonic bonding at a bonding surface to be subjected to bonding. The electrode terminal includes a penetrating hollow part surrounded on at least two sides by the bonding surface. |
| US09484293B2 |
Semiconductor devices with close-packed via structures having in-plane routing and method of making same
The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided. |
| US09484290B2 |
Electronic system with a composite substrate
A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame. |
| US09484288B2 |
Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion. |
| US09484287B2 |
Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. |
| US09484285B2 |
Interconnect structures for wafer level package and methods of forming same
A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die. |
| US09484282B2 |
Resin-sealed semiconductor device
There is provided a resin-sealed semiconductor device (BGA type semiconductor device) whose heat dissipating characteristic is improved, so that it is prevented from deteriorating in reliability. This BGA type semiconductor device includes a wiring substrate on a predetermined area on which a semiconductor chip is mounted; a plurality of metal bumps that are formed to be arranged at predetermined intervals in an area of the substrate different from the area on which the semiconductor chip is mounted; and a sealing resin layer that covers at least the semiconductor chip. Each of the plurality of metal bumps is covered with the sealing resin layer described above, with a part thereof exposed at a top face of the sealing resin layer. |
| US09484281B2 |
Systems and methods for thermal dissipation
A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package. |
| US09484277B2 |
Materials, structures and methods for microelectronic packaging
Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening. |
| US09484273B2 |
Apparatus for measuring impurities on wafer and method of measuring impurities on wafer
Provided are an apparatus for measuring impurities on a wafer and a method of measuring impurities on a wafer. The apparatus includes: a wafer aligning device for aligning a wafer; a loading robot for moving and loading the aligned wafer; a rotation stage for rotating the loaded wafer; a scan robot for holding a natural oxide layer etching solution for the wafer and a metallic impurity recovery solution; and a container for receiving a predetermined etching solution and a recovery solution, wherein the scan robot removes an oxide layer on an edge region of the wafer. |
| US09484272B2 |
Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer. |
| US09484269B2 |
Structure and method to control bottom corner threshold in an SOI device
Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure. |
| US09484268B2 |
Semiconductor device and production method
The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. |
| US09484265B2 |
Structure and method for semiconductor device
A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other. |
| US09484264B1 |
Field effect transistor contacts
A first field effect transistor (FET) device includes a first gate over a first channel region of a first fin arranged on a substrate, a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and a conductive material in the first cavity to define a first contact and a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact. |
| US09484256B1 |
Pure boron for silicide contact
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2. |
| US09484251B1 |
Contact integration for reduced interface and series contact resistance
Methods of lightly implanting platinum, iridium, osmium, erbium, ytterbium, dysprosium, and gadolinium in semiconductor material in shallow depths by plasma-immersion ion implantation (PIII) and/or pulsed PIII are provided herein. Methods include depositing a liner layer prior to masking and implanting features to form n-type and p-type semiconductors and implanting materials through the liner layer. Methods are suitable for integration schemes involving fabrication of fin-type field effect transistors (FinFETs). |
| US09484249B1 |
Method of manufacturing semiconductor device
A technique capable of suppressing a variation in a characteristic of a semiconductor device includes: (a) polishing a substrate including: a first insulating film having a first groove; and a first metal film formed in the first groove and on the first insulating film; (b) forming a second insulating film on the substrate after performing (a); (c) polishing the second insulating film; (d) measuring a thickness distribution of the second insulating film on the substrate after performing (c); and (e) forming a third insulating film having a thickness distribution different from that of the second insulating film measured in (d) to compensate for a thickness distribution of a stacked insulating film including the second insulating film and the third insulating film. |
| US09484248B2 |
Patternable dielectric film structure with improved lithography and method of fabricating same
A method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating. The inorganic antireflective coating is vapor deposited and contains atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. At least one interconnect pattern is then formed within the at least one patternable low-k material. Next, the at least one patternable low-k material containing the at least one interconnect pattern is cured. |
| US09484243B2 |
Processing chamber with features from side wall
A processing chamber having a chamber housing with a top and sidewalls is provided. The processing chamber has a seal for connecting the sidewalls of the chamber housing to a top of a lower chamber below the processing chamber. A substrate holder is attached to the sidewalls of the chamber housing. Further, a wafer lift ring supported by a side arm extending through the sidewalls has at least three posts each having at least one finger, the top of the fingers defining a first wafer handoff plane. The lower chamber has at least one lowest wafer support that defines a second wafer handoff plane where the height between the first wafer handoff plane and the second wafer handoff plane is not greater than a maximum vertical stroke of a transfer arm that is configured to transfer a wafer from the first wafer handoff plane and the second wafer handoff plane. |
| US09484242B2 |
Fluid pressure cylinder
A fluid pressure cylinder includes a displacement member, which is displaceable on an end side of a body, and a connecting body, which is connected to a piston rod of a cylinder unit, is inserted via a spring in a block body of the displacement member. A suction rod is connected substantially in parallel with the connecting body and a buffer rod connected to the connecting body. In addition, in a state where downward displacement of the block body is restricted, when additional loads are applied, the buffer rod is displaced relatively with respect to the block body in opposition to an elastic force of the spring, whereby an interval in a radial direction between a bushing and the buffer rod is enlarged. |
| US09484236B2 |
Joining method and joining system
This joining method of joining a target substrate and a support substrate includes: an adhesive coating operation that includes coating the target substrate or the support substrate with an adhesive; an adhesive removing operation that includes supplying a solvent for removing the adhesive onto an outer peripheral portion of the target substrate or the support substrate, which is coated with the adhesive in the adhesive coating operation, to thereby remove the adhesive on the outer peripheral portion; and a joining operation that includes pressing and joining the target substrate and the support substrate together, in which the adhesive on the outer peripheral portion is removed in the adhesive removing operation, and the support substrate coated with no adhesive, or pressing and joining the support substrate, in which the adhesive on the outer peripheral portion is removed in the adhesive removing operation, and the target substrate coated with no adhesive. |
| US09484227B1 |
Dicing in wafer level package
A method includes placing a first device die and a second device die over a carrier, with a scribe line between the first device die and the second device die. The first device die and the second device die are encapsulated with an encapsulating material, which has a portion in the scribe line. The method further includes forming a dielectric layer over the encapsulating material, performing a first die-saw to form a first trench in the scribe line, performing a second die-saw to form a second trench in the scribe line, and performing a third die-saw on the scribe line to separate the first device die from the second device die. |
| US09484226B2 |
Methods for controlling warpage in packaging
A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages. |
| US09484223B2 |
Coreless packaging substrate and method of fabricating the same
A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed. |
| US09484218B2 |
Post ion implant stripper for advanced semiconductor application
The present invention relates to a substantially water-free photoresist stripping composition. Particularly, the present invention relates to a substantially water-free photoresist stripping composition useful in removing the photoresist after ion-implant process, comprising: (a) an amine, (b) an organic solvent A, and (c) a co-solvent, wherein the composition is substantially water-free (<3 wt % H2O). The present invention also provides a process for post-ion implantation stripping by using the composition of the present invention. |
| US09484214B2 |
Systems and methods for improving wafer etch non-uniformity when using transformer-coupled plasma
A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one. |
| US09484213B2 |
Processing gas diffusing and supplying unit and substrate processing apparatus
A processing gas diffusing and supplying unit is provided in a substrate processing unit including a processing chamber for accommodating a substrate. The processing gas diffusing and supplying unit comprises a main body; a plate supported by the main body and having a plurality of gas supply holes; a partition wall; an internal space having a first and a second space partitioned by the partition wall; a first and a second opening respectively communicating with the first and the second space while facing the plate, first and a second space being connected to a first and a second processing gas introducing pipe of the processing chamber, respectively; and a first and a second shielding portion respectively installed in the first and the second space and having a surface facing the first and the second opening. |
| US09484210B2 |
Semiconductor die singulation method
In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid. |
| US09484205B2 |
Semiconductor device having self-aligned gate contacts
A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact. |
| US09484204B2 |
Transistor and method for forming the same
Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening. |
| US09484203B2 |
Methods of manufacturing semiconductor devices
In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate. |
| US09484202B1 |
Apparatus and methods for spacer deposition and selective removal in an advanced patterning process
Embodiments herein provide apparatus and methods for performing a deposition and a patterning process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for depositing and patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has a first group of openings defined therebetween, selectively treating a first portion of the spacer layer formed on the substrate without treating a second portion of the spacer layer, and selectively removing the treated first portion of the spacer layer. |
| US09484199B2 |
PECVD microcrystalline silicon germanium (SiGe)
Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius. |
| US09484190B2 |
Showerhead-cooler system of a semiconductor-processing chamber for semiconductor wafers of large area
Proposed is a showerhead-cooler system of a semiconductor-processing chamber with uniform distribution of plasma density. The showerhead has a plurality of through gas holes that are coaxial with respective channels of the gas-feeding cooler plate. On the gas inlet side, the though passages of the showerhead are provided with unequal conical nozzles characterized by a central angle that decreases from the peripheral part of the showerhead to the showerhead center. Such design provides uniformity of plasma density. Furthermore, in order to protect the walls of the nozzle and the walls of the gas holes from erosion that may be caused by the hollow-cathode phenomenon, these areas are coated with a thin protective coating that is resistant to electrical breakdown and chemical corrosion. |
| US09484188B2 |
Individual beam pattern placement verification in multiple beam lithography
Methods and systems for verification of a mark written on a target surface during a multiple beam lithography process, and for verifying beam position of individual beams on the target surface based on mark verification are disclosed. A mark can be verified by scanning an optical beam over the mark and measuring the reflected optical beam and the position of the target with respect to the optical beam. By comparing the intensity of the reflected light as a function of distance over the mark with reference mark data representing an intended definition of the mark, and any deviation between the measured representation and the reference mark data are determined. If any deviation deviate more than the predetermined limit, incorrectly positioned beams can be verified from the data. |
| US09484186B2 |
Modeling and correcting short-range and long-range effects in E-beam lithography
Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent. |
| US09484181B2 |
Charged particle beam apparatus and trajectory correction method in charged particle beam apparatus
There is provided a charged particle beam apparatus that includes a trajectory monitoring unit which is disposed above an objective lens (14) and which includes an optical element (12) having a lens action and a trajectory correcting deflector (10). An applied voltage and an excitation current of the optical element (12) are set to zero after a trajectory correction of a primary charged particle beam (30). Accordingly, the lens action and an aberration of the optical element (12) have no influence on resolution. |
| US09484179B2 |
X-ray tube with adjustable intensity profile
An X-ray tube includes an emitter, and an electrode assembly. The emitter is configured to emit an electron beam toward a target. The electrode assembly includes at least one electrode having a bias voltage with respect to the emitter. At least one electrode of the electrode assembly is a segmented electrode including a plurality of segments. The plurality of segments includes a first member and a second member. The first member is configured to have a first bias voltage and the second member is configured to have a second bias voltage that is different from the first bias voltage. |
| US09484176B2 |
Advanced penning ion source
This disclosure provides systems, methods, and apparatus for ion generation. In one aspect, an apparatus includes an anode, a first cathode, a second cathode, and a plurality of cusp magnets. The anode has a first open end and a second open end. The first cathode is associated with the first open end of the anode. The second cathode is associated with the second open end of the anode. The anode, the first cathode, and the second cathode define a chamber. The second cathode has an open region configured for the passage of ions from the chamber. Each cusp magnet of the plurality of cusp magnets is disposed along a length of the anode. |
| US09484168B2 |
DC current switching apparatus, electronic device, and method for switching an associated DC circuit
Exemplary embodiments are directed to a direct current switching apparatus including at least a first mechanical switching device which is suitable to be positioned along an operating path of an associated DC circuit and includes a fixed contact and a corresponding movable contact which can be actuated between a closed position and an open position along the operating path, wherein an electric arc can ignite between the contacts under separation. The switching apparatus includes an electronic circuit having a semiconductor device which is suitable to be positioned along a secondary path and connected in parallel with the first mechanical switching device. The electronic circuit can be configured to commute the flow of current from the operating path to the secondary path and extinguish an electric arc ignited when the movable contact separates from the fixed contact when the first mechanical switching device fails to extinguish the same. |
| US09484158B2 |
Graphene-ionic liquid composites
Method of making a graphene-ionic liquid composite. The composite can be used to make elec-trodes for energy storage devices, such as batteries and supercapacitors. Dis-closed and claimed herein is method of making a graphene-ionic liquid com-posite, comprising combining a graphene source with at least one ionic liquid and heating the combination at a temperature of at least about 130 ° C. |
| US09484157B2 |
Method for preparing solid electrolyte comprising porous thin film and dye-sensitized solar cell using the same
Disclosed is a solid electrolyte for a dye-sensitized solar cell, which includes a three-dimensional porous thin film made of a hydrophilic polymer material, and a dye-sensitized solar cell using the same. More particularly, the present invention provides a high-efficient dye-sensitized solar cell, in which polymer nanofibers having high specific surface area are used in an electrolyte layer to effectively induce an increase in photocurrent, thereby increasing the amount of electrolyte impregnated. When the porous film prepared by the method of the present invention is used as a solid electrolyte for a dye-sensitized solar cell, a process of forming an electrolyte inlet and sealing the inlet is not required, which simplifies the entire process, compared to an existing dye-sensitized solar cell using a liquid electrolyte. |
| US09484156B2 |
Stack capacitor having high volumetric efficiency
An improved capacitor and method of making an improved capacitor is set forth. The capacitor has planer anodes with each anode comprising a fusion end and a separated end and the anodes are in parallel arrangement with each anode in direct electrical contact with all adjacent anodes at the fusion end. A dielectric is on the said separated end of each anode wherein the dielectric covers at least an active area of the capacitor. Spacers separate adjacent dielectrics and the interstitial space between the adjacent dielectrics and spacers has a conductive material in therein. |
| US09484151B2 |
Method of producing R-T-B sintered magnet
A method for producing a sintered R-T-B based magnet includes providing at least one sintered R-T-B based magnet material (where R is a rare-earth element and T is Fe or Fe and Co); providing RH diffusion sources that include a heavy rare-earth element RH (which is Dy and/or Tb) and 30 to 80 mass % of Fe and that have a particle size between 53 μm and 5600 μm; arranging the magnet material and the RH diffusion sources in a process vessel so that some of the RH diffusion sources are in contact with the magnet material; performing an RH diffusion process by heat treating in an inert ambient at a pressure of 5000 Pa or less and at a temperature of 800° C. to 1000° C.; and separating the RH diffusion sources from the magnet material. |
| US09484150B2 |
Multi-mode power amplifying circuit, and multi-mode wireless transmission module and method thereof
A multi-mode power amplifying circuit, and a multi-mode wireless transmission module and method thereof are provided. The multi-mode wireless transmission module includes the multi-mode power amplifying circuit and an antenna. In the multi-mode power amplifying circuit and the antenna, a first power amplifier is electrically connected between a signal input end and a first impedance matching circuit, and an output end of the first impedance matching circuit is electrically connected to the antenna. A second power amplifier is electrically connected to the signal input end, and a second impedance matching circuit is electrically connected between the second power amplifier and the first impedance matching circuit. A switching circuit is electrically connected to an input end of the second impedance matching circuit. The switching circuit switches on-off corresponding to an operation of the first power amplifier and an operation of the second power amplifier. |
| US09484148B1 |
Power system for ground-based machines
A method for distributing energy to a group of ground-based machines. The energy is supplied to the group of ground-based machines through a pattern of inductive power transfer lines physically associated with a ground in a work area. Operations are performed with the group of ground-based machines in the work area. The group of ground-based machines moves in the work area without following a path based on the inductive power transfer lines. |
| US09484147B2 |
Wired-wireless combined power transmission apparatus and the method using the same
Disclosed are a wired-wireless combined power transmission apparatus and a method using the same. The wired-wireless combined power transmission apparatus includes a rectifying unit converting an AC input signal into a DC signal, a transformer unit transforming a size of the input signal, which has been converted into the DC signal, into a predetermined size, a wireless power transmission unit receiving the signal transformed by the transformer unit to wirelessly transmit power, and a wired power supply unit receiving the signal transformed by the transformer unit to supply power through a cable. The advantages and disadvantages of the wired power transmission apparatus and the wireless power transmission apparatus are supplemented to each other, so that the power conversion efficiency and the versatility are improved. |
| US09484145B2 |
Converter
A converter includes a transformer module, a primary side circuit module, and a secondary side circuit module. The transformer module includes a magnetic core group and a winding. The winding includes a primary winding and a secondary winding, and is further installed on the magnetic core group. The primary side circuit module is coupled to the primary winding. The secondary side circuit module is coupled to the secondary winding. The primary side circuit modules or the secondary side circuit module has overlapping vertical projection area on a first plane with the winding, and the first plane is a plane in a horizontal direction of the winding. |
| US09484144B2 |
Transformer assembly structure
A transformer assembly structure includes a transformer and a carrying seat. The transformer includes a bobbin, a winding coil assembly and a magnetic core assembly. The winding coil assembly includes a primary winding coil and a secondary winding coil. The carrying seat includes a main body and a first lateral wing. The main body has an edge. The first lateral wing includes a first positioning structure. The edge of the main body of the carrying seat is located at an inner side of an outer edge of the magnetic core assembly. The outlet part of the primary winding coil is managed and positioned by the first positioning structure. |
| US09484141B2 |
Compact triangular core transformer
A three-phase stacked triangular transformer core is provided. The transformer has three legs and six yoke parts therebetween, wherein the legs include stacked laminations. In a cross-sectional plane perpendicular to a central transformer core axis, the stacked laminations are oriented in substantially radial direction, and each leg has two leg halves, wherein each leg half has a plurality of outer corners facing a corresponding leg half of a neighboring leg. For each of the leg halves the plurality of outer corners lie on a respective straight line within a lateral tolerance, and for each leg half the straight line defined by this leg half and the straight line defined by the corresponding leg half of the neighboring leg are parallel. |
| US09484140B2 |
System and method for treating an amorphous metallic ribbon
A method and a system for continuously in-line annealing a forwarding ferromagnetic amorphous alloy ribbon in a curved shape to improve its magnetic properties without causing the ribbon to become brittle and which operates at significant high ribbon feeding rates. The amorphous alloy ribbon is fed forward, tensioned and guided along a path at a preset feeding rate and is heated at a point along the path at a rate greater than 103° C./sec to a temperature to initiate a thermal treatment. Then the ribbon is initially cooled at a rate greater than 103° C./sec until the thermal treatment ends. During the thermal treatment, a series of mechanical constraints is applied on the ribbon until the amorphous alloy ribbon adopts a specific shape at rest after the thermal treatment is ended. After the initial cooling, the amorphous alloy ribbon is subsequently cooled at a sufficient rate to a temperature that will preserve the specific shape. |
| US09484139B2 |
Reactor, converter, and power converter apparatus
The present invention provides a reactor with which a sensor for measuring the physical quantity (temperature or the like) of the reactor and an external apparatus can be connected to each other in a stable manner. The reactor 1A of the present invention includes a coil 2, a magnetic core 3 at which the coil 2 is disposed, and a case 4 storing a combined product 10 made up of the coil 2 and the magnetic core 3. The case 4 includes a bottom plate portion and a side wall portion 41 surrounding the combined product 10. The side wall portion 41 is made of an insulating resin. A connector hooking portion 44 on which a connector portion 72, which is coupled via a line 71 to a sensor such as a temperature sensor for measuring the physical quantity of the reactor 1A is hooked is integrally molded with the side wall portion 41 by the resin structuring the side wall portion 41. Allowing the connector portion 72 to be hooked on the connector hooking portion 44 and fixed thereto, the connector portion 72 is held by the case 4 in a stable manner, and with the reactor 1A, the connector portion 72 and the connector portion of an external apparatus can be connected to each other in a stable manner. |
| US09484138B2 |
Nano-patterned system and magnetic-field applying device thereof
A nano-patterned system comprises a vacuum chamber, a sample stage and a magnetic-field applying device. The magnetic-field applying device comprises a power supply, magnetic poles, and a magnetic-field generation device having a magnetic conductive soft iron core and a coil connected to the power supply and wound on the soft iron core to generate a magnetic field. The soft iron core is a semi-closed frame structure and the magnetic poles are respectively disposed at the two ends of the semi-closed frame structure. The sample stage is inside the vacuum chamber. The magnetic poles are opposite one another inside the vacuum chamber with respect to the sample stage. The coil and soft iron core are outside the vacuum chamber. The soft iron core leads the magnetic field generated by the coil into the vacuum chamber. The magnetic poles locate a sample on the sample stage and apply a local magnetic field. |
| US09484135B2 |
Chip component and method of producing the same
[Subject] To provide a highly-reliable and small-size chip component, e.g., a chip resistor having an accurate resistance value.[Solution] The chip resistor (10) includes: a substrate (11); a plurality of resistor elements each having a resistive film portion (20) provided on the substrate (11) and an aluminum-containing interconnection film portion (21) provided in contact with the resistive film portion (20); electrodes (12, 13) provided on the substrate (11); and a plurality of fuses (F) each having an aluminum-containing interconnection film portion integral with the aluminum-containing interconnection film portion of the resistor element and disconnectably connecting the resistor element to the electrodes (12, 13).[Effect] The resistance of the chip resistor can be adjusted at a desired resistance value by selectively disconnecting desired ones of the fuses. Since the fuses are formed in a minute layout pattern from an aluminum-containing interconnection film, the processing accuracy is improved in the disconnecting step. |
| US09484132B2 |
Coaxial cables with shaped metallic conductors
A coaxial cable that has a cable core is encased in a polymeric layer. The cable core is enclosed with a pair of semi-circular-profile shaped conductors. A layer of polymer is extruded over the shaped conductors. A pair of armor wire layers is cabled about the layer of polymer to form the coaxial cable. |
| US09484128B2 |
Noise suppression cable
A noise suppression cable includes an insulated wire, an internal magnetic tape layer including a resin layer and a magnetic material layer formed on one surface of the resin layer, the internal magnetic tape layer being spirally wound on a periphery of the insulated wire in a first direction along a longitudinal direction of the cable so as to allow the magnetic material layer of the internal magnetic tape layer to face outside, and an external magnetic tape layer including a resin layer and a magnetic material layer formed on one surface of the resin layer, the external magnetic tape layer being spirally wound on a periphery of the internal magnetic tape layer in a second direction different from the first direction along the longitudinal direction of the cable so as to allow the magnetic material layer of the external magnetic tape layer to face inside. |
| US09484127B2 |
Differential signal transmission cable
A differential signal transmission cable includes a pair of conductors arranged to be distant from each other and parallel to each other, an insulator covering the pair of conductors, the insulator having a transversal cross section including a width in a minor axis direction and a width in a major axis direction greater than the width in the minor axis direction, and an outer periphery shape having curved lines, and a shield conductor wound around the insulator, the shield conductor including a seam or an overlapping region along a longitudinal direction of the insulator. |