| Document | Document Title |
|---|---|
| US09450652B2 |
Radio communication system, transmitter, receiver, elevator control system, and substation facility monitoring system
The radio communication system includes a radio transmitter which performs up-sampling on an information signal, and performs modulation on a carrier wave using the sampled information signal to transmit the modulated carrier wave, and a radio receiver which receives transmission waves transmitted from the radio transmitter, and demodulates the information signal. The radio transmitter includes a transmission processing unit that generates the transmission waves, and a transmission unit that rotates polarized waves of the transmission waves with a predetermined rotation frequency, and wirelessly transmits the transmission waves, and the transmission processing unit copies the sampled information signal, multiplies the copied information signals by predetermined weighting factors, and generates the transmission waves by assigning the information signals on a time axis such that the copied information signals are respectively transmitted with different polarization angles. |
| US09450651B2 |
Inductive structures with improved common mode transient immunity
In a first inductive structure, a first data coil includes: a first portion for conducting a first common mode current in a first direction; and a second portion for conducting a second common mode current in a second direction opposite the first direction. The first and second portions of the first data coil are connected at a first node. In a second inductive structure, a second data coil includes: a first portion for conducting a third common mode current in the first direction; and a second portion for conducting a fourth common mode current in the second direction. The first and second portions of the second data coil are connected at a second node galvanically isolated from the first node. The first, second, third and fourth common mode currents are induced by a common mode transient. |
| US09450643B2 |
Method and apparatus for relaying messages in a PLC network
A method for relaying messages in a PLC network including a relay node and at least two end nodes attached to the relay node, the method including at the relay node receiving respective first probing messages from the at least two end nodes; processing the respective first probing messages to generate respective first feedback messages; broadcasting the respective first feedback messages to the at least two end nodes; wherein the first probing messages are formed as orthogonal signals and received substantially simultaneously in a first time slot, and wherein the first feedback messages are formed as orthogonal signals and broadcast substantially simultaneously in a second time slot. |
| US09450637B2 |
Method and apparatus for managing interference in a communication device
A system that incorporates teachings of the present disclosure may include, for example, a matching network including a tunable reactance circuit configured to be coupled to at least one of a transmitter portion and a receiver portion of a communication device, wherein the tunable reactance circuit is adjustable to a plurality of tuning states, and wherein the determination of a tuning state is based on parameters associated with a detected interference. Additional embodiments are disclosed. |
| US09450635B2 |
Cableless connection apparatus and method for communication between chassis
Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links. |
| US09450632B1 |
Portable electronic device docking station
A portable electronic device docking station adapted for use in a vehicle provides a securement mechanism, electrical power connection, and communication synchronization system to enable hands-free use of the portable electronic device while attached thereto. The docking station also enables communication with other electronic devices GPS function. The station enables a user to exercise command and control of any synchronized device. |
| US09450630B2 |
Methods and devices for displaying multiple subscriber identity module card slots information
A method for displaying SIM card slot information for use in a device including M SIM card slots, each of which may have a SIM card inserted therein or no SIM card inserted therein. The method includes the following steps. A set of predetermined rules are first determined by the device. Statuses of the M SIM card slots corresponding to the set of predetermined rules are then acquired. Information regarding N of the M SIM card slots are displayed on a display unit of the device according to the set of predetermined rules determined by the current associated network and the acquired statuses of the M SIM card slots, where N |
| US09450629B2 |
Systems and methods for controlling local oscillator feed-through
A method for controlling local oscillator (LO) feed-through in a direct transmitter includes detecting a signal level corresponding to LO feed-through in a radio frequency (RF) signal that is output by a direct transmitter. Responsive to detecting the signal level corresponding to LO feed-through, DC offset levels are modified for an in-phase (I) signal and/or a quadrature-phase (Q) signal in the direct transmitter. |
| US09450628B2 |
Receiver and transmitter receiver system
A receiver for receiving messages from a transmitter includes a controller and a driver stage for providing a supply voltage to the transmitter based on a control signal. The controller is configured to provide the control signal to compensate for changes of the supply voltage caused by a modulation of the current consumption of the transmitter, such that the supply voltage remains in a predefined range. Furthermore, the controller is configured to evaluate a series of succeeding values of the control signal to derive a message generated by the transmitter by modulating its current consumption. |
| US09450626B2 |
Sawless architecture for receivers
An apparatus including: at least one differential amplifier configured to amplify a radio frequency signal; a mixer configured to mix the radio frequency signal from the at least one differential amplifier with a local oscillator signal; and a low-pass filter coupled to the mixer, the low-pass filter includes a capacitor and at least one variable resistor configured to tune the low-pass filter. |
| US09450622B2 |
Circuit and method for providing a radio frequency signal
A circuit for generating a radio frequency signal includes an amplifier configured to provide a radio frequency signal, the radio frequency signal being based on a baseband signal and a power supply configured to provide a variable supply voltage to the amplifier. A predistortion circuit is configured to modify the baseband signal; and a control circuit configured to control an operation mode of the predistortion circuit depending on a bandwidth of a radius of the baseband signal. |
| US09450621B2 |
Digital predistortion processing method and system
A digital predistortion processing method and system comprises extracting from a predistortion coefficient parameter table a predistortion parameter corresponding to an input signal, so as to predistort the input signal and obtain a forward transmission signal; amplifying the power of the forward transmission signal to obtain an output signal; acquiring the output signal to obtain a feedback signal; delaying a predetermined number of sampling points so as to acquire the forward transmission signal and obtain a reference signal; conducting synchronization-related calculation on the reference signal and the feedback signal, and calibrating the feedback signal; training a predistortion coefficient according to the reference signal and the calibrated feedback signal; and forming the predistortion coefficient parameter table according to the predistortion coefficient and the amplitude of the input signal. The present invention can delay a predetermined number of sampling points for a transmission signal, thus greatly improving radio frequency index (ACPR). |
| US09450620B1 |
Fast indirect antenna control
A digital interface and control module and a multi-function digital bus for use in a wireless radio frequency receiver, transmitter, or transceiver that communicates over a millimeter-wave band at multi-gigabit speeds. The control module provides a low power, low cost, small form factor, and low pin-count solution for high-speed control of a multi-gigabit radio frequency circuitry. The control module may be used to steer an antenna array for beamforming including selecting different antennas and different phases in compliance with IEEE 802.11ad/WiGig specifications. The control module may also be used for individually controlling variable gain amplifiers and low noise amplifiers and for phase shift controls, gain settings, and other controls. |
| US09450617B2 |
Distribution and replication of erasure codes
Example apparatus and methods selectively replicate some erasure codes associated with a message and selectively distribute, without replicating, other erasure codes associated with the message. The message may have k symbols and n erasure codes may have been generated for the message, n>=k. In one embodiment, erasure codes that store plaintext information from the message (e.g., un-encoded symbols) may be replicated (e.g., sent to all devices using erasure codes associated with the message) while erasure codes that do not store plaintext information may be distributed (e.g., selectively moved to less than all devices) without being replicated. Some (e.g., less than k) erasure codes that do not store plaintext information may be stored unencrypted in the cloud. The generator matrix will not be stored in the cloud. |
| US09450615B2 |
Multi-bit error correction method and apparatus based on a BCH code and memory system
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein. |
| US09450613B2 |
Apparatus and method for error correction and error detection
A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix. |
| US09450612B2 |
Encoding method and system for quasi-cyclic low-density parity-check code
A method and system are provided. The method includes applying a quasi-cyclic matrix M to an input vector X− of encoded data to generate a vector Y. The method further includes applying a matrix Q to the vector Y to generate a vector Z. The method also includes recursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I*. The encoded data includes quasi-cyclic low-density parity-check code. The identity matrix variant I* is composed of Toeplitz sub-matrices. |
| US09450611B2 |
Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). |
| US09450604B1 |
Elastic data packer
This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking device or other computing apparatus. Each data unit in the group may only have values for fields in a master set. The described systems are particularly suited for hardware-level processing of groups of sparsely-populated data units, in which a large number of the data units have values for only a small number of the fields. In an embodiment, non-value carrying fields in a data unit are compressed based on a compression profile selected for the data unit. The compression profile indicates, for each master field, whether the compressed data unit includes a value for that field. Non-value carrying fields are omitted from the compressed data unit. The compression profile also permits compression of value-carrying fields using variable-width field lengths specified in the profile. |
| US09450602B2 |
Efficiently query compressed time-series data in a database
A query of time series data stored in a database is received that specifies at least one value. The database includes (i) an index table specifying groups of segments of compressed time series data with corresponding ranges each having a lowest value and a highest value, and (ii) a segments table specifying individual segments of compressed time series data. Thereafter, using the index table, at least one group for which the specified at least one value falls within the corresponding range is identified. The segments table is then queried for the segments corresponding to the identified at least one group to generate a new segments table specifying at least one segment. Next, the at least one segment specified by the new segments table is decompressed. Data responsive to the query within the decompressed at least one segment is then identified using the specified at least one value. |
| US09450601B1 |
Continuous rounding of differing bit lengths
A system and method are disclosed for encoding numbers in a way that improves the accuracy and efficiency of one or more computing devices working with the transmitted/stored encoded numbers. When the encoded value is missing one or more bits after transmission or storage, the remaining bits of the encoded value will be optimally rounded up or down for the number of bits actually received. |
| US09450599B1 |
Current digital-to-analog converter reducing flicker noise
A current DAC circuit includes a reference current source, a current mirror, a decoder, and one or more current DAC units. The reference current source provides a reference current to a first node. The current mirror includes first and second PMOS transistors configured to provide a copy current generated by copying the reference current to a second node and coupled, at respective drains, to separate nodes. The current mirror may reduce noise of the first and second PMOS transistors through swapping the separate nodes to which the respective drains of the first and second PMOS transistors are connected periodically according to first and second clock signals. The decoder generates one or more enable signals based on a data input signal. One or more current DAC units generate separate positive currents and negative currents based on the copy current and separate enable signals of the one or more enable signals, respectively. |
| US09450598B2 |
Two-stage digital down-conversion of RF pulses
A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth. A stream of second stage I/Q quadrature samples has an optimal signal to noise ratio and allows accurate estimation of RF pulse parameters (magnitude, phase and frequency) by means of a second I/Q signal processor and/or by storing second I/Q data for subsequent processing and analysis. |
| US09450597B1 |
Hardware based compressive sampling ADC architecture for non-uniform sampled signal recovery
A back end-circuit for randomized non uniform and alias-free subsampling, comprising: an analog-to-digital converter (ADC) configured for sampling an input signal at random non uniform times; a compressive sensing processor, coupled to the ADC, to recover a sparse spectral representation of the input signal; and a Fourier transformer for converting the sparse spectral representation to a time sampled representation of the input signal. |
| US09450594B2 |
Time difference adders, time difference accumulators, sigma-delta time-to-digital converters, digital phase locked loops and temperature sensors
A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference. |
| US09450593B2 |
Dither-less error feedback fractional-n frequency synthesizer systems and methods
A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error. |
| US09450592B2 |
Frequency control system with dual-input bias generator to separately receive management and operational controls
Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode. |
| US09450590B2 |
Clock distribution network for multi-frequency multi-processor systems
Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock. |
| US09450589B2 |
Clock generation system with dynamic distribution bypass mode
In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage. |
| US09450585B2 |
Selecting four signals from sixteen inputs
An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer. |
| US09450584B2 |
Semiconductor device
A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node. |
| US09450583B2 |
Input/output circuit with high voltage tolerance and associated apparatus
An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage. |
| US09450582B2 |
Programmable buffer system
A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources. |
| US09450576B2 |
Switching device having a good isolation characteristic, method for improving the isolation characteristic of a switching device
A switching device having a good isolation characteristic is disclosed. The switching device comprises a switch unit and a control unit, wherein the control unit is connected to a power supply terminal, and connected to the switch unit via a control line and a power line. The control unit comprises a voltage regulator unit that is electrically connected to the power supply terminal and the power line of the switch unit. When the switch unit enters standby mode, the control unit provides an isolation voltage to the switch unit to effectively enhance the isolation characteristic of the switching device in the standby mode. |
| US09450573B2 |
Input/output circuit
A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal. |
| US09450571B2 |
Data and clock signal voltages within an integrated circuit
An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10. |
| US09450568B1 |
Bias circuit having second order process variation compensation in a current source topology
A bias circuit includes second order process variation compensation in a current source topology having a compensation transistor operating in saturation mode as a current source. An additional compensation transistor is biased to operate in a linear mode to provide an active resistor to vary a control voltage applied to the saturation mode compensation transistor and widen the range of sourced control current, thus widening the achievable range of the control voltage applied to the biasing transistor to produce a predetermined level of bias current despite process variations. The additional compensation transistor has been shown to be able to compensate for another approximately 20-25% of the induced variations leaving less than approximately 10% and preferably less than 5% variation in the bias current from the predetermined level at certain bias conditions and over typical fabrication process variations. |
| US09450567B2 |
Noise removing circuit and current sensing unit including the same
A noise-removing circuit includes a first capacitor to charge a first voltage supplied to a first node during a first period in which a first switching control signal is supplied, a second capacitor to charge a second voltage supplied to a third node during the first period, a third capacitor to charge the first voltage during a second period in which a second switching control signal is supplied, and to charge the second voltage charged in the second capacitor as a third voltage during a third period in which a third switching control signal is supplied, a fourth capacitor to charge the second voltage during the second period, and to charge the first voltage charged in the first capacitor as a fourth voltage during the third period, and a differential amplifier to output a voltage difference between the third voltage and the fourth voltage. |
| US09450560B2 |
Wireless transceiver with function of adjustment for frequency-band matching and the adjusting method therefor
The present invention is related to a wireless transceiver with function of adjustment for frequency-band matching and the adjusting method therefor, mainly comprising a plurality of transmitting circuits, a plurality of receiving circuits, a frequency-band matching adjustment circuit, and a radio-frequency signal transceiving end. In this connection, the transmitting circuits and/or the receiving circuits are connected to the radio-frequency signal transceiving end via the frequency-band matching adjustment circuit. Impedance in the frequency-band matching adjustment circuit may be adjusted on the basis of the frequency-band of a RF signal, when (before) the RF signal is transmitted or received, such that high impedance or low impedance is presented in the frequency-band matching adjustment circuit with respect to the frequency-band of the received or transmitted RF signal. Thereby, loss of RF signal in reception or transmission is reduced. |
| US09450554B2 |
Electronic device and method for adjusting volume
An electronic device and volume adjusting method detect ambient light and generate corresponding intensity signals via a sensor. Programs in a storage device, executed by at least one processor, cause the at least one processor to receive and sample light intensity signals and determine whether the ambient light level is changing. Time passing is counted if the ambient light level is changing, until the ambient light level stops changing. The counting of time stops when ambient light level stops changing and the counted time period is compared with a preset time period, a longer time period causes a volume adjusting command to be sent to a playback output device. |
| US09450547B2 |
Semiconductor package having an isolation wall to reduce electromagnetic coupling
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented. |
| US09450544B2 |
Pre-distortion method, associated apparatus and non-transitory machine readable medium
A pre-distortion method includes: receiving an input data; and obtaining a pre-distortion output by inputting the input data into a pre-distortion function, wherein the pre-distortion function is determined according to a following power amplifier; and multiplying a reciprocal of a pre-distortion ratio of the output of the power amplifier to the input data by the output of the power amplifier. A pre-distortion apparatus includes a receiver, a pre-distortion unit and a gain compensating unit. The receiver is utilized for receiving an input data. The pre-distortion unit is utilized for obtaining a pre-distortion output by inputting the input data into a pre-distortion function, wherein the pre-distortion function is determined according to a following power amplifier. The gain compensating unit is utilized for multiplying a reciprocal of a pre-distortion ratio of the output of the power amplifier to the input data by the output of the power amplifier. |
| US09450542B2 |
Preamplifier, optical receiver, optical termination device, and optical communication system
A current bypass circuit that passes part of a photocurrent output from a photodetector is connected to an input terminal of a current-to-voltage conversion amplifier circuit. A voltage obtained by level conversion of an output voltage by a voltage level conversion circuit is input into the current bypass circuit so that the current bypass circuit is turned on at a photocurrent that is smaller than the photocurrent at which a diode connected in parallel to a feedback resistor of the current-to-voltage conversion amplifier circuit is turned on. Consequently, the current-to-voltage conversion gain is switched in three stages according to the intensity of the photocurrent corresponding to an optical signal level. |
| US09450541B2 |
Systems and methods related to linear and efficient broadband power amplifiers
Systems and methods related to linear and efficient broadband power amplifiers. A power amplifier (PA) system can include an input circuit configured to receive a radio-frequency (RF) signal and split the RF signal into a first portion and a second portion. The PA system can further include a Doherty amplifier circuit including a carrier amplification path coupled to the input circuit to receive the first portion and a peaking amplification path coupled to the input circuit to receive the second portion. The PA system can further include an output circuit coupled to the Doherty amplifier circuit. The output circuit can include a balance to unbalance (BALUN) circuit configured to combine outputs of the carrier amplification path and the peaking amplification path to yield an amplified RF signal. |
| US09450539B2 |
Communications based adjustments of an offset capacitive voltage
A parallel amplifier and an offset capacitance voltage control loop are disclosed. The parallel amplifier has a parallel amplifier output, which is coupled to an envelope tracking power supply output via an offset capacitive element. The offset capacitive element has an offset capacitive voltage. The offset capacitance voltage control loop regulates the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis. |
| US09450536B2 |
Inspection apparatus and inspection method
An inspection apparatus includes an irradiation part that emits plural pieces of pulse light having different wavelengths to irradiate a multi-junction type solar cell; a wavelength setting part that sets the wavelengths of the plural pieces of pulse light with which the multi-junction type solar cell is irradiated by the irradiation part; and a detection part that detects an electric field intensity of an electromagnetic wave emitted from the multi-junction type solar cell in response to the plural pieces of pulse light with which the multi-junction type solar cell is irradiated by the irradiation part. The irradiation part includes a delay element that delays a time the multi-junction type solar cell is irradiated with the pulse light by a time Δt11 relative to the pulse light. |
| US09450535B2 |
Solar powered satellite system
A solar powered satellite system is provided. A power control system, for example, of the solar powered satellite system may include, but is not limited to, a first interface configured to receive a power signal from the satellite receiver, a voltage converter electrically coupled to the first interface, the voltage converter configured to reduce a voltage of the power signal received from the satellite receiver to a predetermined voltage, a second interface configured to receive a power signal from the solar panel assembly, a third interface configured to be coupled to at least one power consumer of a satellite dish, and a source selection circuit electrically coupled to the voltage converter, the solar panel assembly and the third interface, the source selection circuit configured to output a selected power signal based upon a comparison between the predetermined voltage and a voltage of the power signal from the solar panel assembly. |
| US09450530B2 |
Control for multi-phase induction motor
A method of controlling operation of a multi-phase induction motor may include transmitting a low-speed operation signal by a master computer to a control signal board for low-speed operation of the motor; the control signal board receiving the low-speed operation signal, and in response to the low-speed operation signal, the control signal board sensing that the master computer is not simultaneously transmitting a high-speed operation signal, and in response to receiving the low-speed operation signal and not simultaneously receiving the high-speed operation signal, closing contactors in a power section to transmit power to the motor for low-speed operation, whereby the motor is connected to a source of multi-phase power and operates at low-speed; and the control signal board transmitting a first feedback signal to the master computer that the motor is connected to the source of multi-phase power and is running at low speed. |
| US09450528B2 |
Sensorless control apparatus for synchronous motor and inverter apparatus
According to one embodiment, a sensorless control apparatus for a synchronous motor, includes a PWM processing unit which pulse-width-modulates a three-phase voltage command, and thereby generates a gate command for an inverter, a high-frequency voltage calculator which obtains a high-frequency voltage component included in an output of the PWM processing unit or an equivalent output value, a high-frequency current calculator which obtains a high-frequency current component included in a current response value from a synchronous motor driven by the inverter, and an estimated angle calculator which calculates an estimated phase angle indicative of an estimated value of an angle of rotation of the synchronous motor, based on a plurality of pairs each including the high-frequency voltage component and the high-frequency current component which respectively include cosine components or sine components at an equal frequency, the pairs obtained for at least two different frequencies. |
| US09450523B2 |
Motor drive apparatus
To suppress a ripple contained in current flowing into a DC power supply during one-pulse control in a motor drive apparatus receiving electric power from the DC power supply. A motor drive apparatus 1 includes an inverter control device (10) provided with a one-pulse control mode in which, during one electrical angle cycle, a positive rectangular pulse voltage and a negative rectangular pulse voltage are applied, as gate drive signals, to a switching element corresponding to each phase. When performing the one-pulse control mode, the inverter control device (10) gradually increases or reduces a duty in a predetermined phase angle width at rising and falling edges of the rectangular wave voltage. |
| US09450515B2 |
Method for controlling inverter apparatus by detecting primary-side output and inverter apparatus thereof
A control method for an inverter apparatus is provided. The inverter apparatus includes a direct current to direct current (DC/DC) converter and a direct current to alternating current (DC/AC) converter. An output side of the DC/DC converter is coupled to an input side of the DC/AC converter. The control method includes the following steps: outputting a DC power from the output side of the DC/DC converter; receiving the DC power from the input side of the DC/AC converter, and generating an AC power from an output side of the DC/AC converter according to the DC power; and detecting the DC power, and accordingly controlling an operation of the DC/AC converter. |
| US09450514B2 |
Method and apparatus for minimising a circulating current or a common-mode voltage of an inverter
The present disclosure discloses a method and an apparatus implementing the method for minimizing a circulating current of parallel-connected inverters. The method can include, for at least one parallel-connected inverter, measuring a common-mode voltage of the inverter, and controlling a cycle length of the switching cycle on the basis of the common-mode voltage. |
| US09450513B2 |
Control circuit and control method for inverter circuit, and control circuit and control method for power conversion circuit
A control circuit controls the inverter circuit in one of the non-master-slave inverters connected in parallel in a power system. The control circuit includes: a target parameter controller for generating a compensation value for adjusting a target parameter to the target value; a cooperative correction value generator for generating a correction value for cooperating with another of the inverters; a PWM signal generator for generating a PWM signal based on a correction compensation value obtained by adding the correction value to the compensation value; a weighting unit for weighting the correction compensation value; and a communication unit for communicating with other inverters. The communication unit transmits the weighted correction compensation value to the other inverters. The cooperative correction value generator generates the correction value using an operation result based on the weighted correction compensation value and a reception compensation value received by the communication unit from the other inverters. |
| US09450509B2 |
Power conversion apparatus
A power conversion apparatus comprises a first converter connected to a second converter. The first converter includes a first capacitor and the second converter includes a second capacitor connected in series to a third capacitor. The capacitors are each connected in parallel with a respective resistor. The power conversion apparatus also includes a bypass switch connected in parallel to the first converter and in series to the second converter. A control module is configured to control a single-phase output voltage by operation of the first converter, the second converter, and the bypass switch. |
| US09450508B2 |
Modular switch for an electrical converter, electrical converter, as well as method for operating an electrical converter
Described is a modular switch for an electrical converter. The modular switch is provided with a first series circuit including a first controllable power semiconductor component and a first diode as well as with a second series circuit including a second diode and a second controllable power semiconductor. The connecting point between the first power semiconductor component and the first diode forms a first terminal and the connecting point between the second diode and the second power semiconductor component forms a second terminal of the modular switch. Also provided is a capacitor, wherein the first series circuit and the second series circuit and the capacitor are switched parallel to each other. |
| US09450501B2 |
Matrix converter having first and second commutation controllers
A matrix converter includes a power converter and a controller. The power converter includes bidirectional switches each having a controllable conducting direction. The bidirectional switches are disposed between input terminals and output terminals. The input terminals are respectively coupled to phases of an AC power source. The output terminals are respectively coupled to phases of a load. The controller controls the bidirectional switches. A first commutation controller performs commutation control when the conducting direction is unidirectional. A second commutation controller performs the commutation control when the conducting direction is bidirectional. A selector selects between the first commutation controller and the second commutation controller to perform the commutation control based on a state of an output current from the power converter. |
| US09450494B1 |
Inductive compensation based control of synchronous rectification switch
An electronic device includes a synchronous rectification circuit having an actively controlled switching element through which resonant current flows during operation. The actively controlled switching element is disposed in a package which adds stray inductance to a main current path of the synchronous rectification circuit. The electronic device also includes a fixed inductor magnetically coupled to the stray inductance or an additional inductance in series with the stray inductance so that the fixed inductor is not in the main current path of the synchronous rectification circuit and change in current through the inductance to which the fixed inductor is magnetically coupled induces a reference voltage at the fixed inductor which is in phase with a zero crossing point of the resonant current at different switching frequencies of the actively controlled switching element. A corresponding method of controlling the electronic device is also described. |
| US09450493B2 |
Voltage generating apparatus for stably controlling voltage
A negative bias circuit outputs a DC voltage of a negative polarity. A positive bias circuit outputs a DC voltage of a positive polarity. The DC voltage of the positive polarity is used, for example, as a transfer voltage, and the DC voltage of the negative polarity is used as a cleaning voltage for cleaning toner. A cycle of the clock signal in a period during which the DC voltage of the first polarity is output is longer than a cycle of the clock signal in the period during which the voltage supplied to the load transits from the DC voltage of the first polarity to the DC voltage of the first polarity. |
| US09450491B2 |
Circuits and methods providing three-level signals at a synchronous buck converter
A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor. |
| US09450483B2 |
Apparatus and method for controlling inverter by measuring each phase current
An apparatus and a method for controlling an inverter are disclosed. The apparatus determines a 3-phase current by receiving a 2-phase current from a leg-shunt resistor arranged at an emitter terminal of a lower switching element in an inverter unit of an inverter, and determines whether there is an abnormality generated in the 3-phase current, to correct the abnormality in the current. |
| US09450482B2 |
Fault recovery for multi-phase power converters
A fault recovery method for multi-phase power converters enables delivery of reduced output power of as much as 66% of normal power in the event of a shorted power switch component. The need for redundant power converters in conventional multi-phase space power systems is reduced, if not eliminated. Fault recovery includes 1) detecting a shorted power switch fault; 2) providing short circuit current protection; 3) providing isolation of the shorted power switch; and 4) reconfiguring the remaining undamaged power switches. |
| US09450480B2 |
RF switching converter with ripple correction
This disclosure relates generally to radio frequency (RF) switching converters and RF amplification devices that use RF switching converters. In one embodiment, an RF switching converter includes a switching circuit operable to receive a power source voltage, a switching controller configured to switch the switching circuit so that the switching circuit generates a pulsed output voltage from the power source voltage, and an RF filter configured to convert the pulsed output voltage into a supply voltage, wherein the RF filter includes a decoupling capacitor configured to receive the supply voltage. The switching controller is configured to generate a ripple correction current that is injected into the decoupling capacitor such that the decoupling capacitor filters the ripple correction current. The decoupling capacitor outputs the ripple correction current such that the ripple correction current reduces a ripple variation in a supply current level of a supply current resulting from the supply voltage. |
| US09450476B2 |
Electric drive unit
An electric drive unit (100) of the invention includes the electric motor (1) and the control apparatus (20) that is disposed on an axis line of a rotation shaft (2) of the electric motor (1) and controls the driving of the electric motor (1). The electric motor (1) has a motor terminal (13) extending parallel to an axial direction of the rotation shaft (2) toward the control apparatus (20) and a slit (13a) is provided to the motor terminal (13) at an end on a side of the control apparatus (20). The control apparatus (20) has a motor connection terminal (34) provided on a line extended from the motor terminal (13) and connected to the motor terminal (13). The slit (13a) in the motor terminal (13) is press-fit and fixed to the motor connection terminal (34). |
| US09450475B2 |
Methods and apparatus for a motor
Methods and apparatus for a motor generally comprise a motor shell, a drive unit, a motor electronics assembly configured to operate the drive unit, and a shaft coupled to the drive unit. The drive unit may comprise an axial design configured to increase the efficiency of the system. The motor may be totally enclosed, the shaft may be sealed using a labyrinth seal, and the motor electronics assembly may be contained within the motor shell. The motor may comprise shapes and materials to promote cooling by air flow and thermal conduction. The motor may further comprise a touch-sensitive interface, may operate at high speed in response to a signal, and may provide a single location for the connection of all inputs. A motor according to the present invention may have improved operating characteristics. |
| US09450474B2 |
Active cooling of a motor
A motor, comprising an electronics housing, a stator having a stator bushing, and a rotor. The motor can be fastened to a fastening wall by means of the stator bushing. The motor according to the invention has an air conducting element and an air conveying element. The air conveying element is connected to the rotor in a rotationally fixed manner. The air conducting element surrounds the stator bushing and forms a flow space between the air conducting element and an outer circumference of the stator bushing. The flow space is open on the side of the electronics housing in the direction of the fastening wall through at least one flow gap. The air conducting element opens with an intake opening via a sealing gap in a rotor-side throughflow opening of the air conducting element. |
| US09450471B2 |
Brushless DC motor power tool with combined PCB design
A power tool with a combined printed circuit board (PCB) that reduces internal wiring of the power tool and provides a large amount of air flow to internal components. In some instances, the combined PCB has a surfboard shape and includes a motor control unit and power switching elements (Field Effect Transistors or FETs). The combined surfboard PCB is located above the trigger, but below the motor and drive mechanism. In other instances, the combined PCB has a doughnut shape and is located coaxially with a motor shaft. The combined PCB may be positioned between a doughnut-shaped control PCB and the motor. |
| US09450468B2 |
L-shaped sheet metal cooling jacket with baffles and integrated power electronics
An electric machine includes a pair of substantially aligned sheet metal housing sections each including a substantially “L” shaped portion, at least one cooling channel being formed at an axial end between the two sections, and a plurality of power electronics components engaged with at least one of the housing sections adjacent the axial end cooling channel. An embodiment includes a stator, a pair of housing sections enclosing the stator, power electronics components positioned at an axial end of the electric machine for controlling operation of the electric machine, and a coolant flow path that includes a power electronics cooling channel formed at the axial end between the housing sections. A method includes forming an axial end cooling channel between two sheet metal housing sections, and positioning power electronics components at the axial end along the cooling channel, whereby heat from the electronics components is transferred to the cooling channel. |
| US09450465B2 |
Continuous stator winding wound on bobbins
In a method for producing a stator winding of a stator, an auxiliary element is positioned with its central axis in alignment with a central axis of the stator. Bobbins are arranged on the auxiliary element in uniformly spaced-apart relationship around the central axis of the auxiliary element, and a circuit carrier is arranged on the auxiliary element radially inside the bobbins. Coils are formed by winding a conductor wire for each phase of the stator winding onto a corresponding one of the bobbins and routed via the circuit carrier to another one of the bobbins of this phase and wound thereon. Each of the bobbins is pivoted with the coils about a pivot so as to enable the bobbins to pivot up onto radially outwardly protruding stator teeth of the stator from radially outside. |
| US09450461B2 |
Rotating electrical machine, for starter
A rotating electric machine comprising a rotor (2) comprising a body (34) on the periphery of which are installed conductors (36) forming the winding, and a stator (3) positioned around the rotor (2) comprising a magnetized structure extending along a circumference of the stator (3). The body (34) of the rotor (2) is made partially of plastic, in the region of the teeth which conventionally separate the notches near the air gap, on the periphery of the armature. A modified structure of magnets of Halbach type is made with magnets of NdFeB type to reduce the thickness of the stator (3), to increase the radius (R2) of the rotor (2) so as to position all the conductors (36) on the periphery of the body (34) of the rotor (2) on one and the same layer at a diameter of maximum value. |
| US09450460B2 |
Electric generator for a wind power installation
The invention relates to an electrical generator comprising a stator which has windings lying in grooves formed by metal sheets and which has a predetermined diameter and a predetermined depth. The metal sheets form a laminated core which is penetrated by threaded bolts, the front and rear end of the laminated core being mounted on a ring of the stator. According to the invention, an additional mounting point for the laminated core is formed on the stator ring, said mounting point being located approximately in the center of the stator ring. |
| US09450455B2 |
Magnetic resonance power transmitter and magnetic resonance power receiver
A magnetic resonance power transmitter of a magnetic resonance wireless power transmission system includes a resonance coil, an alternating current power source configured to cause the resonance coil to generate an alternating current, and a frequency changer configured to change, based on communication data, a frequency of the alternating current that the alternating current power source causes the resonance coil to generate. |
| US09450453B2 |
Uninterruptible power supply system with energy feedback to chargers and sinusoidal output
An uninterruptible power supply (UPS) system with energy feedback to chargers and sinusoidal output charges a battery pack through a first charger under a mains mode. Under a battery mode, the UPS boosts DC voltage outputted from the battery pack to a higher voltage level through a DC-to-DC conversion module, converts the DC voltage to a sinusoidal AC voltage through a DC-to-AC conversion module, and supplies the sinusoidal AC voltage to a load. When the load has energy storage elements and discharged energy occurs in a power supply loop, a micro-controller unit can control the discharged power to charge the battery pack through a second charger, thereby solving the issue of the discharged power from the energy storage elements of the load and enhancing the operational efficiency of the UPS. |
| US09450450B2 |
Method and apparatus for efficient fuel consumption
A method for efficient fuel consumption comprises recharging batteries or operating a device carrying out a task, with an engine through an electrical connection. The method also includes monitoring at least one of (i) current in the electrical connection, (ii) voltage of the batteries, and (iii) length of time of the recharging or task, to determine if the recharging has reach a preselected endpoint or the task has been completed. The method further includes generating a signal through a communication link to cause the engine to stop operating by: (a) preventing operation of a spark plug, (b) preventing delivery of fuel to the engine, or (c) preventing delivery of oxygen to the engine. |
| US09450446B2 |
Connector-free magnetic charger/winder
A method and apparatus for charging an electronic device include rotating a magnetically attractable element, or element, within the electronic device. Rotating a magnet external to the electronic device simultaneously rotates the element. Rotating the element causes an electrically generating device, such as a generator, to create an electric charge in the electronic device. The electric charge may be used to power the electrically generating device, or the electric charge may be transmitted to an internal power supply in order to charge another component or components. In another embodiment, the external magnet may wind a spring inside a device. |
| US09450444B2 |
Charging apparatus
A charging apparatus includes: a charging unit configured to perform a contactless charging operation for a placed external device; a detector configured to detect a position of a placed object; a determining unit configured to determine that the placed object is an external device compatible with the charging unit; and a control unit configured to control the charging unit such that, during the contactless charging operation for an external device compatible with the charging unit, the charging operation for the external device being charged is restricted when an object that is determined by the determining unit not to be an external device compatible with the charging unit, has been placed within a predetermined distance from the charging unit. |
| US09450443B2 |
Management of high-voltage lithium-polymer batteries in portable electronic devices
The disclosed embodiments provide a system that manages use of a battery corresponding to a high-voltage lithium-polymer battery in a portable electronic device. During operation, the system monitors a cycle number of the battery during use of the battery with the portable electronic device, wherein the cycle number corresponds to a number of charge-discharge cycles of the battery. If the cycle number exceeds one or more cycle number thresholds, the system modifies a charging technique for the battery to manage swelling in the battery and use of the battery with the portable electronic device. |
| US09450440B2 |
High capacity batteries with on-demand fast charge capability
An embodiment provides an apparatus, including: apparatus components; a battery pack comprising a high charge rate cell component, the battery pack supplying power to one or more of the apparatus components; a processor; and a memory device accessible to the processor and storing code executable by the processor to: apply a normal rate of charge to a cell component of the battery pack; accept user input to switch the normal rate of charge to a second rate of charge which is higher than the normal rate of charge; and apply the second rate of charge to the high charge rate cell component based on the user input. Other aspects are described and claimed. |
| US09450437B2 |
Capacitor circuit for arrays of power sources such as microbial fuel cells
An electronic circuit to increase voltages from one or more energy sources. The electronic circuit can include a first set of capacitors and a second set of capacitors, and a first set of switches associated with the first set of capacitors and a second set of switches associated with the second set of capacitors. Also included is at least one energy source and an external load. The first and second set of capacitors, first and second set of switches, the at least one energy source, and the external load are arranged and connected such that the first set of capacitors is connected to the at least one energy source in parallel while the second set of capacitors is connected to the external load in series, and vice versa. |
| US09450436B2 |
Active power factor corrector circuit
In accordance with an embodiment, a circuit includes a direct current (DC) output configured to be coupled to a rechargeable battery and a power factor corrector circuit coupled to the DC output, where the power factor corrector circuit includes a controller, and where the controller is configured to determine a switching frequency of the power factor corrector circuit in accordance with a battery charging curve of the rechargeable battery. |
| US09450432B1 |
Portable mirror charger
A combined portable charger and mirror is provided that can store and deliver energy to charge portable electronic devices without accessing external power sources and that also functions as a portable illuminated vanity mirror. The charger enables users of portable equipment and devices (e.g., cellular telephone, cameras, tablets, computers, etc.) to carry additional stored energy to extend the device's use time. The combined portable charger and vanity mirror includes a housing comprised of a top casing and a bottom casing coupled to each other, a reflective mirror coupled to the top casing, a rechargeable battery within the housing, one or more illuminated lights adjacent to the mirror, a light indicator configured to provide a visual indication of the battery charge level, and a communication interface for transmitting electrical current from the battery to one or more electronic devices. The combined charger further includes a power switch configured to place the charger in an active charging mode or inactive non-charging mode. |
| US09450429B2 |
Woman's accessory smartphone battery charger
A compact mirror for use with woman's cosmetics includes a smartphone battery charging system integrated therein. A connection interface, such as, for example, a USB interface, is in electrical communication with an internal rechargeable battery pack. Upon connection of a smartphone via the connection interface, the user can charge their smartphone device. When the internal rechargeable battery is exhausted, an external charger is connected to the connection interface to recharge the same. One or more indicators provide visual indication of the charging status of the internal battery and/or the connected smartphone. |
| US09450423B2 |
Wireless power transmission apparatus
Disclosed is a wireless power transmission apparatus. The wireless power transmission apparatus includes a mounting member, an upper transmission coil on the mounting member, a lower transmission coil under the mounting member, a first terminal connected with an outer connection part of the upper transmission coil and an inner connection part of the lower transmission coil, and a second terminal connected with an inner connection part of the upper transmission coil and an outer connection part of the lower transmission coil. The upper transmission coil and the lower transmission coil are bilaterally symmetrical to each other about a central axis between the first and second terminals. |
| US09450421B2 |
Wireless non-radiative energy transfer
Described herein are embodiments of a source high-Q resonator, optionally coupled to an energy source, a second high-Q resonator, optionally coupled to an energy drain that may be located a distance from the source resonator. A third high-Q resonator, optionally coupled to an energy drain that may be located a distance from the source resonator. The source resonator and at least one of the second resonator and third resonator may be coupled to transfer electromagnetic energy from said source resonator to said at least one of the second resonator and third resonator. |
| US09450419B2 |
Combined power supply and input/output system with boost capability
A combined power and input/output system for an electronic device includes a host system; a target system operably coupled to the host system via a combined power and I/O line; and a power boost circuit in the target system for enabling a higher voltage target device. |
| US09450418B2 |
Power supply device, method for controlling the power supply device, and electronic apparatus
Provided are a power supply device capable of producing a highly-accurate supply voltage at low power consumption, a method for controlling the power supply device, and an electronic apparatus in which the power supply device is incorporated. The power supply device includes a first power supplying part and a second power supplying part which has less output current capacity than the first power supplying part does. The power supply device is configured to control the voltage value of the second voltage produced in the second power supplying part in order to make the first voltage produced in the first power supplying part equal to the second voltage produced in the second power supplying part. |
| US09450410B2 |
Surge suppression system for medium and high voltage
A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units included various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid. |
| US09450403B1 |
Electro-optic terminal protection system with matching stub
Apparatus for protecting a device from transients. The apparatus includes a switching network and a transmission line electrically connecting an input to an output. The switching network includes a stub connected near the input with a detector at the other end, a switch, and a communication path therebetween. The detector detects a transient and communicates with the switch. The switch then actuates to place a low impendence across the output of the transmission line, thereby attenuating the transient. The switching network has a switching time that equals the sum of the times to detect the transient at the input, transmit a signal corresponding to the detection to the switch, and actuate the switch. The input signal travels from the input to the output along the transmission line, which has a propagation delay. The propagation delay is greater than the stub propagation time plus the switching time of the switch network. |
| US09450402B1 |
Electrostatic discharge protection circuitry with reduced capacitance
Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. Integrated circuits may include input-output pins that are coupled to the ESD protection circuitry. The ESD protection circuitry may include diode circuits, a control circuit, and a power clamp circuit. Each diode circuit may have a first terminal that is coupled to a respective input-output pin and a second terminal that is coupled to a shared ESD control line. The control circuit may supply a boosted voltage onto the control line to reverse bias the diode circuits during normal operation while the power clamp is turned off. During an ESD event, the power clamp may be turned on to sink current from the diode circuits. The power clamp may include a transistor having a substrate that is forward biased to improve transistor drive strength during the ESD event and that is reverse biased to reduce leakage during normal operation. |
| US09450401B2 |
Controlling a thermally sensitive over-current protector
A method for controlling a thermally sensitive over-current protector is described. A battery current is monitored. It is then determined whether or not the monitored current has exceeded a predetermined threshold during the entirety of a predetermined time interval. If yes, then a current source is signaled to raise its current, so as to increase the heat being generated by a heating element that is being driven by the current source thereby tripping the thermally sensitive over-current protector. Other embodiments are also described and claimed. |
| US09450398B2 |
Protection circuit for electronic system
Damages to the rectifying MOSFET in the secondary side of voltage converters are reduced or eliminated by inserting intermediary steps between detecting a dropping in the converter output voltage VCC and activating the under voltage lock out (UVLO) circuitry. During the intermediary steps, the timing for switching off the MOSFET is advanced to prevent the current flow in the MOSFET from reversing its direction. |
| US09450396B2 |
DC current interruption system able to open a DC line with inductive behaviour
The invention pertains to a DC current interruption system able to open a DC line with inductive behavior, comprising a primary mechanical breaker (S0), a secondary mechanical breaker (S1) and an electronic overvoltage protection circuit (B1, B2) comprising at least one transistor. The DC current interruption system of the invention furthermore comprises an electronic opening system (72, 76) comprising a passive circuit able to auto-bias the electronic protection circuit (B1, B2) upon the opening of said primary mechanical breaker (S0), so as to trigger a switching of said at least one transistor (M1, M2, IG1) making it possible to limit the voltage and the current in the DC line, total interruption of said DC line being obtained by subsequent opening of said secondary mechanical breaker (S1). |
| US09450394B2 |
Method, circuit breaker and switching unit for switching off high-voltage DC currents
A high voltage DC circuit breaker includes a semiconductor switching assembly in series with a mechanical switch. When the semiconductor switching assembly is switched off due to a current fault, a residual current flowing through arresters of the semiconductor switching assembly is switched off by the mechanical switch. A capacitor arranged parallel to the mechanical switch leads to passive resonance effects, which in turn induce current zero crossings in its arc. The current zero crossings allow for reliable extinguishing of the arc. The mechanical switch can be an AC circuit breaker. |
| US09450390B1 |
Electrical box cover
An electrical box cover including a body for securing a plurality of electrical connections therein, a cover having a door, the door having a first end with at least one male hinge, at least one female hinge attached to the cover, and wherein the at least one male hinge is removably connected with the at least one female hinge to selectively open and close the door. |
| US09450386B2 |
Vertical-mount electrical power distribution plugstrip
A vertical-mount electrical power distribution plugstrip comprises a long, thin plugstrip body with several power outlet plugs distributed along the length of one face. A power input cord is provided at one end, and this supplies operating power to each of the power outlet plugs through individual relay control. |
| US09450385B2 |
Subsea switchgear
A subsea switchgear is provided. The subsea switchgear includes a first power input for receiving electric power from a power source and a second power input for receiving electric power from a power source. It further includes a power distribution bus and a first circuit breaker coupled between the first power input and the power distribution bus. The first circuit breaker is configured to be capable of disconnecting the first power input from the power distribution bus. A second circuit breaker is further coupled between the second power input and the power distribution bus. The second circuit breaker is configured to be capable of disconnecting the second power input from the power distribution bus. |
| US09450382B2 |
Spark plug for an internal combustion engine
Spark plug for an internal combustion engine, having a center electrode and a ground electrode arranged in radial direction around the center electrode, wherein an annular spark gap is formed between the center electrode and the ground electrode for igniting a fuel mixture by means of an electric ignition spark developing between the center electrode and the ground electrode, and wherein the ground electrode is contoured in such a way that particles reaching the region of the ground electrode can be removed from the spark gap under the influence of gravitational force. |
| US09450379B2 |
Quantum dot SOA-silicon external cavity multi-wavelength laser
A hybrid external cavity multi-wavelength laser using a QD RSOA and a silicon photonics chip is demonstrated. Four lasing modes at 2 nm spacing and less than 3 dB power non-uniformity were observed, with over 20 mW of total output power. Each lasing peak can be successfully modulated at 10 Gb/s. At 10−9 BER, the receiver power penalty is less than 2.6 dB compared to a conventional commercial laser. An expected application is the provision of a comb laser source for WDM transmission in optical interconnection systems. |
| US09450374B2 |
Pump laser architecture and remotely pumped raman fiber amplifier laser guide star system for telescopes
There is provided a system for remote pumping of a Raman fiber amplifier comprising a pump laser located remotely from the Raman fiber amplifier and a laserhead and one or more optical fibers to optically couple the high power pump light from the remote pump laser to the Raman fiber amplifier where a seed laser light is amplified wherein the pump laser for producing a high power laser light of a predetermined pump wavelength comprises a first fiber laser emitting light at the predetermined pump wavelength and one (second) or two (third) laser emitting light at a wavelength lower than the predetermined pump wavelength and multiplexed with light from the first laser into an optical fiber providing Raman gain at the predetermined pump wavelength to convert the second (and optionally also the third) laser light to light at the predetermined pump wavelength. |
| US09450372B1 |
Wavelength tunable semiconductor laser
A tunable semiconductor laser incorporates a light generating structure in which light is generated and amplified by stimulated emission. The generated light is evanescently coupled into a first resonator of a first resonant optical reflector where the light is reflected back and forth between two end mirrors. A portion of this light, which is characterized by a series of resonant wavelengths, is evanescently coupled back into the light generating structure. One or more of the resonant wavelengths can be changed by modifying an optical path length of the first resonator. The tunable semiconductor laser further includes a second resonant optical reflector having a second resonator. The second resonator interacts with the light generating structure in a manner similar to the first resonator. A desired beat wavelength can be obtained by modifying the optical path length in one or both resonators. |
| US09450371B2 |
Mode-locked multi-mode fiber laser pulse source
A laser utilizes a cavity design which allows the stable generation of high peak power pulses from mode-locked multi-mode fiber lasers, greatly extending the peak power limits of conventional mode-locked single-mode fiber lasers. Mode-locking may be induced by insertion of a saturable absorber into the cavity and by inserting one or more mode-filters to ensure the oscillation of the fundamental mode in the multi-mode fiber. The probability of damage of the absorber may be minimized by the insertion of an additional semiconductor optical power limiter into the cavity. |
| US09450367B2 |
Amplifier device and method for amplifying laser pulses
A laser pulse amplifier device (100) includes an amplifying cavity (10) comprising an amplifying laser gain medium (11) and multiple cavity mirrors (12.1 to 12.7) spanning a cavity light path (13), wherein the amplifying cavity (10) is configured for an amplification of laser pulses (1) circulating along the cavity light path, and a multi-pass amplifier (20) being optically coupled with the amplifying cavity (10) and comprising multiple deflection mirrors (22) spanning a multipass light path (23), wherein the multi-pass amplifier (20) is configured for a post-amplification of laser pulses (2) coupled out of the amplifying cavity (10), wherein the amplifying cavity (10) and the multi-pass amplifier (20) are arranged such that the laser gain medium (11) of the amplifying cavity (10) is included as an active medium in the multi-pass light path (23) of the multi-pass amplifier (20). Furthermore, a method of amplifying laser pulses is described. |
| US09450358B2 |
Floating bus bar and connector within chassis and powered slide rails
Technology is provided for a powered slide rail. The powered slide rail includes an outer segment including a first elongate conductor, a middle segment slidably nested with the outer segment that includes a second elongate conductor, and a first conductive element connected to the second elongate conductor and positioned for sliding contact with the first elongate conductor. An inner segment is slidably nested with the middle segment and includes a second conductive element positioned for sliding contact with the second elongate conductor. |
| US09450357B2 |
Module type power distribution unit having a multi socket module for selectively supplying different kinds of power
A module type PDU for different power supply is provided. The PDU includes: a base configured to transmit different kinds of power; and a multi socket module connected with the base to transmit one kind of power to devices plugs of which are connected to the multi socket module. Accordingly, double power supply can be achieved through a single PDU and thus a PDU installing cost can be reduced, and, as the number of PDUs is reduced, electric equipments can be simplified. |
| US09450356B1 |
Power outlet and power outlet assembly having the same
A power outlet for electrical connection with a plurality of electrical wires includes a plurality of limiting frames, a plurality of conductive terminals each having an abutment plate inserted into a respective limiting frame and spaced apart from a first side wall thereof for accommodating therebetween a core wire portion of the respective electrical wire, and a plurality of fasteners each being operable to extend through a second side wall of the respective limiting frame to push the abutment plate of a respective conductive terminal to move toward the first side wall of the respective limiting frame for tightly clamping the core wire portion of the respective electrical wire between the first side wall and the abutment plate. |
| US09450355B2 |
USB plug connector and method for manufacturing the same
A USB plug connector (100) includes an insulative housing (1) having a main portion (11) and a tongue portion (12), a number of contacts (2), and a metal shell (3). The tongue portion has an upper surface (16), a lower surface (17), a pair of lateral surfaces (18), and a frontal vertical surface (121). A pair of recesses (122) is defined on both sides of the upper surface and the lower surface. An interspace (181) is defined between each lateral surface of the tongue portion and the main portion. The metal shell includes a front wall (31), a pair of horizontal walls (32), and a pair of vertical walls (34). Each vertical wall includes a rigid beam (342) inserted in the interspace and a pair of wing portions (343) received in the recesses. A method for manufacturing the USB plug connector is also disclosed. |
| US09450354B2 |
Dual orientation connector and assembly of the same
An electrical connector includes an insulative housing with a base and a mating tongue extending forwardly in a front-to-rear direction from the base, the mating tongue defining a first surface and a second surface opposite to each other. A plurality of contact strips is disposed around the outer surface of the mating tongue of the insulative housing, each contact strip is stamped from a metal sheet and defines a first contacting section exposed upon the first surface and arranged along a transverse direction perpendicular to the front-to-rear direction, and a second contacting section exposed upon the second surface and arranged along the transverse direction. |
| US09450353B2 |
Multipole jack comprising a main body inserted within a case
A multipole jack includes a main body and a case. The substantially cylindrical main body includes terminal bases which make contact with electrodes of a multipole plug. Connecting ends of the terminal bases are led out from the main body. The main body is attached to the substantially bottomed cylindrical resin case through an opening of the case. Inner ends of extension terminals which protrude from side walls of the case and are insert-molded are electrically connected to the connecting ends of the corresponding terminal bases. Therefore, it is possible to further increase a battery size of an electronic device in which a multipole jack is provided by decreasing an entire length of the multipole jack, and to meet the demand for reducing the size of a multipole jack by reducing the length of terminals. |
| US09450351B2 |
Standard antenna interface
An RF interconnection module includes a housing having a perimeter, a capacitive coupling, and a float gasket disposed about the perimeter of the housing. When the housing is mounted in an opening, the float gasket is positioned between the housing and the opening. The float gasket may be made of an elastomer material and may include a plurality of outwardly extending ribs for movable securing the gasket in the opening. In addition, a mount assembly includes a bracket assembly attachable to a tower-mounted equipment and at least one jumper cable having at least one ohmic connector for connecting to the tower-mounted equipment and at least one capacitive connector. The capacitive connector may comprise an RF interconnection module mounted on the bracket assembly. The bracket assembly may be adjustable to accommodate tower mounted equipment of various sizes. |
| US09450347B2 |
Power cord
A power cord includes a plug having blades configured to be inserted into blade insertion holes of an electrical outlet, respectively. The power cord further includes thermal sensors provided for the blades one each. When a temperature detected with any of the thermal sensors is higher than a prescribed temperature, electric power is stopped from being supplied to a load from the blades. |
| US09450345B2 |
Connector assembly with flexible circuit board
The invention relates to an electrical connector (1), comprising a plurality of terminals (4), and a circuit board (7). The circuit board (7) comprises a plurality of traces for electrically connecting the terminals (4) with a plurality of pads (11). The pads (11) can electrically connect strands from a cable with the traces. The circuit board (7) further comprises a vertical connecting portion (8) for connecting the terminals (4) with the traces, and a first horizontal connecting portion (10) with pads (11), wherein the first horizontal connecting portion (10) is physically connected to the vertical connecting portion (8). According to the invention the circuit board (7) comprises a second horizontal connecting portion (10) with pads (11). |
| US09450344B2 |
High speed, high density electrical connector with shielded signal paths
A modular electrical connector with separately shielded signal conductor pairs. The connector may be assembled from modules, each containing a pair of signal conductors with surrounding partially or fully conductive material. Modules of different sizes may be assembled into wafers, which are then assembled into a connector. Wafers may include lossy material. In some embodiments, shielding members of two mating connectors may each have compliant members along their distal portions, such that, the shielding members engage at points of contact at multiple locations, some of which are adjacent the mating edge of each of the mating shielding members. |
| US09450343B2 |
Differential signal connector capable of reducing skew between a differential signal pair
A differential signal connector includes a plurality of pairs of signal contacts, a plurality of ground contacts, and an insulating housing holding the signal contacts and the ground contacts. On a first connection side for connection to a connection partner, the ground contacts are arranged on both sides of each pair of signal contacts so that a contact array of a fixed pitch is formed. On a second connection side for connection to a board, the ground contacts are arranged spaced apart from each other in a first row, while the pairs of signal contacts, which are adjacently arranged on both sides of the ground contact on the first connection side, are arranged so as to be allocated in a second row and a third row located on both sides of the first row so that the pairs of signal contacts are arranged zigzag on the second connection side. |
| US09450339B2 |
Ground contacts for reduced-length connector inserts
Connector inserts having a high signal integrity and low insertion loss by shielding signal contacts. One example may provide one or more ground contacts between a front opening and signal pins of a connector insert. These ground contacts may have sufficient lever arm to provide a good contact to a corresponding contact in a connector receptacle. To avoid excessive length in the connector insert, embodiments of the present invention may stack a portion of the ground contact above the signal contacts in the connector insert. To reduce excessive capacitance that would otherwise reduce signal impedance, one or more openings may be formed in the ground contacts. To prevent signal contacts from shorting to a shield through this opening, the opening may be covered by tape. The ground contacts may be positioned to avoid encountering power contacts in the receptacle when the insert is inserted into the receptacle. |
| US09450333B2 |
Buffering apparatus for messengered cables
A tensile-force buffering apparatus interposes a physical structure and a drop clamp having a messenger of an input drop cable secured thereto. The tensile-force buffering apparatus includes an outer housing defining an elongate inner cavity and a retainer, and a spring-strut assembly. The spring-strut assembly includes a central shaft, a retention member at a first end of the central shaft, and a coil spring disposed about the central shaft. The spring-strut assembly is received in the cavity of the outer housing, and the retention member is held by the retainer while a load compressing the coil spring is less than a predetermined threshold load. The retention member is released from the outer housing when the load compressing the coil spring reaches the predetermined threshold load, thereby effecting separation of the spring-strut assembly from the outer housing. |
| US09450328B2 |
Cable fixing means
The invention relates to a cable retainer (1) for mechanically retaining a cable (10) on a cable outlet, comprising a cable outlet connection piece (2), a sealing element (3) and a pressure element (4), wherein the pressure element (3) can be screwed onto the cable outlet connection piece (2) using a thread (2.1, 3.1) and in this way squeezes the sealing element (3) together between the cable output connector (2) and the pressure element (4). By means of detents (4.2) on the pressure element (4) and detents (2.2) on the cable outlet connection piece (2) that cooperates therewith, a release of the threads (2.1, 3.1) screwed together is prevented. |
| US09450326B2 |
Data cable connector module for assembly to cable with a fixation element for positioning and fixing of cable conductors of a multi core cable
A data cable connector module with a fixation element for positioning and fixation of cable conductors of a multi core cable, with: conductor receiving units with conductor guide and connection openings for bent IDCs, IDC receiving units for fixation of connected IDCs with contact openings; a centric metallic shield star which shields each conductor pair and is electrically conductively connected with the housing of the fixation element; and a detachably connectable, changeable contact module with a metal housing, an isolation socket for receiving bent slide contacts with connector ends for connection to a circuit board which connects the slide contacts and the module plug-in contacts, a front connector face for external connectors; and a fixation element connector face with in at least one end isolator block guided module plug-in contacts. The fixation element and the contact module are electrically conductively connectable with the IDCs. |
| US09450325B1 |
Power socket structure
A power socket structure comprises a base seat, a top lid, a safety gate and an elastic component, wherein the base seat includes a first electrode and a second electrode, the safety gate can be movably placed on a supportive platform of the base seat, the top lid has a first plug-in hole and a second plug-in hole, and the top lid covers the base seat such that the safety gate is located between the top lid and the base seat, and the gate body of the safety gate masks the first electrode and the second electrode at the normal position. In addition, the safety gate includes a first slope and a second slope, so that, in case any one of the first plug-in hole or the second plug-in hole is inserted, it can sway about the rolling component of the safety gate acting as the center thereby maintaining the relationship of masking the first electrode and the second electrode. Thus, only when the electric power plug is correctly inserted can it be possible to push the safety gate away from the normal position to an application position via the first slope. |
| US09450322B2 |
Electrical contact having tines with edges of different lengths
The present invention relates to electrical contacts having tines with uneven edges to provide increased contact normal force and decreased peak stress. The socket electrical contact contains a socket body that includes a base defining a longitudinal axis and tines extending from the base at spaced-apart locations around the circumference of the base. The tines extend from the base in the direction of the axis to define a pin reception zone between the tines. Each tine contains two opposing edges that have different lengths and a blunt tip. |
| US09450317B2 |
Connector of electronic device and electronic device having the same
A connector of an electronic device and an electronic device having the same are provided. The connector of an electronic device may includes a mold fixed on a main board of the electronic device; a first connection pin having a first connecting portion protruded to one surface of the mold; and a second connecting portion separated from the mold and an extension that connects the second connecting portion and the mold. |
| US09450311B2 |
Polarization dependent electromagnetic bandgap antenna and related methods
A rotationally polarized antenna includes a radiating element that is held in a skewed orientation with respect to an underlying polarization-dependent electromagnetic band gap (PDEBG) structure. The radiating element and the PDEBG structure are both housed within a conductive cavity. The radiating element, the PDEBG structure, and the cavity are designed together to achieve an antenna having improved operational characteristics (e.g., an enhanced circular polarization bandwidth, etc.). In some embodiments, the antenna may be implemented as a flush mounted or conformal antenna on an outer surface of a supporting platform. |
| US09450310B2 |
Surface scattering antennas
Surface scattering antennas provide adjustable radiation fields by adjustably coupling scattering elements along a wave-propagating structure. In some approaches, the scattering elements are complementary metamaterial elements. In some approaches, the scattering elements are made adjustable by disposing an electrically adjustable material, such as a liquid crystal, in proximity to the scattering elements. Methods and systems provide control and adjustment of surface scattering antennas for various applications. |
| US09450307B2 |
Flexible planar inverted F antenna
A flexible inverted “F” antenna (PIFA) is shown. The flexible PIFA is not only applicable to flat surfaces, but it can be applied to curved surfaces, both convex and concave, without degrading performance. The flexible PIFA can also be used close to living bodies or to a metal surface without detuning. The flexible PIFA is formed from a flexible printed circuit board (PCB) having a metal layer on one side and over which a cover layer is positioned. The flexible PCB is folded, on its reverse side, around a flexible dielectric element with the covered metal layer facing outward to form a metal conducting service, an impedance matching stub and a ground plate. An adhesive layer forms a portion of the ground plate that is not in contact with the dielectric element. This adhesive layer is applied against the desired surface. A coaxial cable is electrically coupled to corresponding feed and ground tabs at the short circuit plate portion of the flexible PIFA. |
| US09450303B2 |
Antenna structure
An antenna structure includes a radiation module and a metal board. The radiation module has a first coil unit and a second coil unit. The first coil unit is coupled to the second coil unit. The first coil unit and the second coil unit have opposite direction of current. The metal board is disposed at one side of the radiation module. The metal board has an enclosed slot which has a first slot portion and a second slot portion. |
| US09450299B2 |
Resonant embedded antenna
A planar antenna, such as included as a portion of a printed circuit board assembly, can include a first conductive layer comprising a feed conductor and a patch. The planar antenna can include a second conductive layer comprising a reference conductor, a first arm defined by a first arm length and a first arm width, and a second arm located parallel to the first arm and defined by a second arm length and a second arm width. The first and second arms can be respectively coupled to the reference conductor, and at least a portion of the first arm and at least a portion of the second arm can overlap with a footprint of the patch projected vertically from a plane of the first conductive layer onto a plane of the second conductive layer. |
| US09450296B2 |
Antenna structure and wireless communication device using the same
An antenna structure includes a feed end, a first radiator plate, a second radiator plate, a third radiator plate, a first ground end, and a second ground end. The first radiator plate and the third radiator plate are coupled to the feed end. The second radiator plate is coupled to the first radiator plate. The first ground end and the second ground end are disposed on the third radiator plate and are spaced from the first ground end. The first ring portion is coupled to the first radiator plate, the second radiator plate, and the third radiator plate. |
| US09450293B2 |
Wireless communication device
A wireless communication device includes a housing and an antenna. The housing is made of metal and defines a conductive chamber. The chamber includes a bottom wall, two opposite first side walls, and two opposite second side walls connecting to the first side walls, the first side walls and the second side walls surrounding around the bottom wall. The antenna comprises a radiating body, a feed end, and a ground end. The radiating body is suspended above the chamber and distanced from the conductive chamber in such a way that the antenna functions in a resonance mode with the conductive chamber, in operating at the required frequencies. The feed end and ground end extend from the radiating body and are connected to one of the second side walls. |
| US09450291B2 |
Multiband slot loop antenna apparatus and methods
A multiband slot loop antenna apparatus, and methods of tuning and utilizing the same. In one embodiment, the antenna configuration is used within a handheld mobile device (e.g., cellular telephone or smartphone). The antenna comprises two radiating structures: a ring or loop structure substantially enveloping an outside perimeter of the device enclosure, and a tuning structure disposed inside the enclosure. The ring structure is grounded to the ground plane of the device so as to create a virtual portion and an operating portion. The tuning structure is spaced from the ground plane, and includes a plurality of radiator branches effecting antenna operation in various frequency bands; e.g., at least one lower frequency band and three upper frequency bands. On one implementation, a second lower frequency band radiator is effected using a reactive matched circuit coupled between a device feed and a radiator branch. |
| US09450287B2 |
Broadband antenna and wireless communication device employing same
Broadband antenna for wireless communication device is disclosed. The broadband antenna includes a grounding portion, a feeding portion, a connecting portion, a first radiation body connected to an end of the connecting portion, and second radiation body connected to another end of the connecting portion opposite to the first radiating body. The first radiating body and the second radiating body are symmetrical to each other with respect to the connecting body. The feeding portion is connected to an end of the first radiating body away from the second radiating body, the grounding portion is connected to an end of the second radiating body away from the first radiating body. |
| US09450286B1 |
Systems, devices, and methods for stabilizing an antenna
Systems, methods, devices and apparatus are disclosed that include a chassis mount adapted to be attached to a vehicle and an antenna mount adapted to receive a satellite antenna. Further, the systems, methods, devices and apparatus that include a gyroscopic stabilizer attached to the antenna mount configured to convert vibrational torque applied to the antenna mount into a linear displacement of the antenna mount using one or more gyroscopes, each gyroscope having a control moment. In addition, the systems, methods, devices and apparatus that include a linear displacement spring attachment device connecting the antenna mount to the chassis mount and configured to provide a restoring force in opposition to the linear displacement. |
| US09450285B2 |
Attachment of deep drawn resonator shell
The apparatus includes a base having a hole in a top surface, a fastener having a longitudinal section with the longitudinal section extending into the hole, and a shell. The shell has a connecting section connecting a first lateral surface section and a second lateral surface section. At least a portion of the first lateral surface section extends into the hole. The second lateral surface section extends away from the top surface of the base. The connecting section is disposed between the top surface of the base and a portion of the fastener. The connecting section has a first section and a second section, and the first section has a non-linear cross-section. The apparatus further includes a washer disposed between the portion of the fastener and the connecting section, and a portion of the washer engages the first section of the connecting section. |
| US09450284B2 |
Resonance based cable compensation
A system for resonance based cable compensation includes a first switch with a first terminal for connecting a first connection of a cable having a resonant circuit on an end of the cable opposite the first switch. The system also includes a second terminal for connecting a second connection of a cable that has its first connection connected to the first terminal. A logic component is operatively connected to control the first switch to selectively apply voltage pulses across the first and second terminals to generate a resonance signal in a cable connected to the terminals in order to compensate for equivalent cable capacitance. |
| US09450283B2 |
Power device and a method for controlling a power device
An RF power device that includes a transistor with a compact impedance transformation circuit, where the transformation circuit includes a lumped element CLC analog transmission line and an associated embedded directional bilateral RF power sensor that is inductively coupled to the transmission line to provide detection of direct and reflected power independently with high directivity. |
| US09450279B2 |
Components and circuits for output termination
A lossy electrical-signal transmission line having first and second ends, the transmission line being configured such that: its characteristic impedance at the first end has a first value; its characteristic impedance at the second end has a second value, lower than the first value; and its series resistance measured from its first end to its second end is within a given range of the difference between said first and second values. |
| US09450277B2 |
Systems for recycling volatile battery sources
The invention is directed to systems and methods for the recycling of lithium ion batteries or the like. The system methods include comminution and destruction of used batteries, controlling the explosive reaction of the battery components during processing, and processing the materials into a suitable form for sampling and recycling. |
| US09450276B2 |
Thermal gap pad for a prismatic battery pack
A battery pack includes at least one voltaic cell module. A substrate is mechanically coupled to the module and configured to receive excess heat therefrom. A section of an electrically insulating thermal gap pad is arranged between the module and the substrate. The pad includes a dielectric sheet supporting a deformable layer. |
| US09450273B2 |
Electrolyte and secondary battery
Secondary batteries capable of improving cycle characteristics are provided. The secondary battery includes a cathode, an anode, and an electrolytic solution. A separator provided between the cathode and the anode is impregnated with the electrolytic solution. The electrolytic solution contains a solvent and an electrolyte salt. The solvent contains a cyclic compound having a disulfonic acid anhydride group (—S(═O)2—O—S(═O)2—) and at least one of a nitrile compound. Compared to a case that the solvent does not contain both the cyclic compound having the disulfonic acid anhydride group and succinonitrile or a case that that the solvent contains at least one thereof, chemical stability of the electrolytic solution is improved. Thus, even if charge and discharge are repeated, electrolytic solution decomposition is inhibited. |
| US09450269B2 |
Nonaqueous electrolyte secondary battery
A prismatic nonaqueous electrolyte secondary battery includes a flat winding electrode assembly formed by winding an elongated positive and negative electrodes with an elongated separator interposed therebetween, and an outer body storing the flat winding electrode assembly and a nonaqueous electrolyte. The positive electrode includes a positive electrode substrate exposed portion formed along a longitudinal direction. The negative electrode includes a negative electrode substrate exposed portion formed along a longitudinal direction. The nonaqueous electrolyte contains at least one of a lithium salt having an oxalate complex as an anion and lithium difluorophosphate (LiPF2O2) at the time of making the nonaqueous electrolyte secondary battery. The flat winding electrode assembly has eight or more layers of a winding portion formed only of the separator in its central portion. This battery can allow a nonaqueous electrolyte having a high viscosity to easily penetrate the inside of a flat winding electrode assembly. |
| US09450268B2 |
Method for producing and apparatus for producing secondary battery
A production apparatus is equipped with a supply unit which has a cassette member 50 for bearing a predetermined number of positive electrode plates or negative electrode plates, and which batchwise supplies a plurality of positive electrode plates 5 or negative electrode plates 6 placed on the cassette member 50 to respective electrode plate conveying trays 19 of an electrode plate conveying member 20. |
| US09450266B2 |
Bipolar secondary battery
A battery main body housed in a case comprises one laminated body composed of a plurality of bipolar electrodes laminated with an electrolyte layer therebetween or comprises a plurality of laminated bodies connected in series. A positive electrode current collecting plate and a negative electrode current collecting plate each having one surface joined to the inner peripheral surface of the case and the other surface joined to one end of the battery main body respectively extend to the outside of the case. By providing a cutoff mechanism for cutting off an electrical connection between the positive electrode current collecting plate and the negative electrode current collecting plate via the battery main body according to an expansion deformation of the case, a current path in a bipolar secondary battery is interrupted when the short-circuit current occurs, thereby protecting the bipolar secondary battery from a short-circuit current. |
| US09450262B2 |
Fluoroionomers dispersions having a low surface tension, low liquid viscosity and high solid content
The invention pertains to a process for manufacturing certain (per)fluoroionomer liquid compositions, comprising, inter alia, at least one of fluorination and treatment with a polar solvent, to the liquid compositions therefrom having an improved solids content/surface tension/liquid viscosity compromise, to the use of the same for manufacturing composite membranes and to composite membranes obtainable therefrom. |
| US09450260B2 |
Method for inferring temperature in an enclosed volume
A method for inferring temperature in an enclosed volume containing a fuel/oxidant mixture, the method comprises placing at least one wire in the enclosed volume. The at least one wire having an identifiable property wherein the identifiable property of the at least one wire changes from a first identifiable state at a temperature below the auto-ignition temperature of the fuel/oxidant mixture to a second identifiable state at a temperature above the auto-ignition temperature of the fuel/oxidant mixture, and determining if the identifiable property of the at least one wire has changed from the first identifiable state to the second identifiable state and hence if the temperature in the enclosed volume is above the auto-ignition temperature of the fuel/oxidant mixture. |
| US09450253B2 |
Fuel cell
In a fuel cell having a cell structure in which a gas flow passage is formed by an expanded metal, a bond portion connecting a mesh of the expanded metal stands partially upright in a position where a bond length is shortened so as to form a part of a strand portion. Hence, in an opening formed by the mesh of the expanded metal, a surface area on which front and rear openings overlap in a direction increases when seen from an direction. Thus, a sectional area of gas flow passages constituted by a continuum in the direction of the openings overlapping in the direction increases. As a result, a gas flow flows without making repeated narrow turns, leading to a reduction in gas pressure loss. |
| US09450249B2 |
Non-aqueous electrolyte secondary battery and method for producing same
Provided is a non-aqueous electrolyte secondary battery in which the effect achieved by adding an oxalate complex compound is suitably exhibited and which can achieve battery characteristics during normal usage and resistance to overcharging at high levels. This battery is provided with an electrode body obtained by laminating a positive electrode having a positive electrode active material layer and a negative electrode having a negative electrode active material layer. A coating film which is derived substantially from an oxalate complex compound and which contains boron atoms and/or phosphorus atoms is formed on the negative electrode active material layer. In addition, in the negative electrode active material layer that constitutes the electrode body, the standard deviation (σ) of resistance values, which are measured at a plurality of points at equal intervals in a line direction extending linearly from one prescribed layering surface to the layering surface on the opposite side, is 3.0 to 7.2. |
| US09450248B2 |
Active material for rechargeable lithium battery and rechargeable lithium battery including the same
An active material for a rechargeable lithium battery is provided with a non-carbon-based material on which nanofiber-shaped carbon having an oxygen-included functional group is grown. The negative active material for a rechargeable lithium battery has good conductivity and cycle life characteristics. |
| US09450246B2 |
Carbon particles for negative electrode of lithium ion secondary battery, negative electrode for lithium ion secondary battery, and lithium ion secondary battery
Disclosed are carbon particles for a negative electrode of a lithium ion secondary battery, the carbon particles having a pore volume of pores having a size of 2×10 to 2×104 Å, of 0.1 ml/g or less with respect to the mass of the carbon particles; having an interlayer distance d(002) of a graphite crystal as determined by an X-ray diffraction analysis, of 3.38 Å or less; having a crystallite size Lc in the C-axis direction of 500 Å or more; and having a degree of circularity of the particle cross-section in the range of 0.6 to 0.9. Therefore, the carbon particles for the negative electrode of the lithium ion secondary battery enables to have high capacity and have superior rapid charge characteristics, a negative electrode for a lithium ion secondary battery using the carbon particles, and a lithium ion secondary battery can be provided. |
| US09450241B2 |
Composite cathode active material, and cathode and lithium battery including the material
A composite cathode active material represented by the formula (1−x)LiM1aM2bM3cO2−xLi2M4O3, wherein M1, M2, and M3 are each independently selected from the group of titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), magnesium (Mg), zirconium (Zr), and boron (B); M4 is selected from the group consisting of manganese (Mn), titanium (Ti0, and zirconium (Zr); M1, M2, and M3 are different from one another; and 0.5 |
| US09450230B2 |
Lithium-ion secondary battery including polybenzimidazole and method of manufacturing lithium-ion secondary battery
A lithium-ion secondary battery including an electrode having a current collector and an active material layer, formed on the current collector, that contains an active material and polybenzimidazole. Also, a method of manufacturing a lithium-ion secondary battery including manufacturing an electrode having a current collector and an active material layer, formed on the current collector, that contains an active material and polybenzimidazole. |
| US09450228B2 |
Cathode active material, positive electrode for lithium ion secondary battery, and lithium ion secondary battery
A cathode active material comprising secondary particles having a plurality of primary particles of a lithium-containing composite oxide agglomerated, the lithium-containing composite oxide being represented by LixNiaCobMncMdOy (x: 1.1 to 1.7, a: 0.15 to 0.5, b: 0 to 0.33, c: 0.33 to 0.85, M: another metal element, d: 0 to 0.05, a+b+c+d=1, and y: the number of moles of oxygen atom (O) required to satisfy the valences of the metal elements), and I020/I003 in an X-ray diffraction pattern being from 0.02 to 0.3, wherein the porosity in a cross section of the secondary particles is from 5 to 20%, and the percentage of the maximum void in a cross section of the secondary particles is from 0.1 to 10%. |
| US09450227B2 |
Thermostatic valve for an electrochemical power source for use in a marine environment
A thermostatic valve, coupled to an electrochemical power source and having: a valve body; a first fluid inlet for a hot electrolytic fluid; a second fluid inlet for a cold electrolytic fluid; an outlet supplying a mixed electrolytic fluid; and regulating means for adjusting the mixing. The valve body defines a first opening, in communication with the second fluid inlet for the cold electrolytic fluid; and a second opening, in communication with the first fluid inlet for the passage of the hot electrolytic fluid; the regulating means include an adjustment baffle, interposed between the first and second openings and the outlet, and rotatably drivable to vary a useful passage section and adjust the mixing. The first and second openings are designed to mix the electrolytic fluids in different proportions, maintaining the flow rate and introduced load losses unvaried, as the rotation angle of the adjustment baffle varies. |
| US09450225B2 |
Cover for battery wiring module, and battery wiring module
A cover is provided, and a battery wiring module is provided with the cover. The cover can cover a resin protector of the battery wiring module, and the battery wiring module includes: a bus bar that electrically connects positive and negative electrode terminals of a cell group formed by arranging in a row a plurality of cells having the electrode terminals; and the resin protector that holds the bus bar. The resin protector can be deformed or moved in accordance with a variation of a pitch between the electrode terminals. The cover for the battery wiring module includes a dislocation compensating portion that compensates a dislocation of the resin protector resulting from deformation or movement thereof. |
| US09450222B2 |
Electric storage device, and vehicle mounted electric storage system
Provided is an electric storage device provided with: a positive electrode including a positive electrode substrate and a positive electrode mixture layer, the positive electrode mixture layer being formed on the positive electrode substrate and containing a positive electrode active material; a negative electrode including a negative electrode substrate and a negative electrode mixture layer, the negative electrode mixture layer being formed on the negative electrode substrate and containing a negative electrode active material; and a separator disposed between the positive electrode and the negative electrode. In the electric storage device, the separator yields a triple value of standard deviation of local air resistance, as measured within a 5-mm diameter circle, of at least 20 seconds/10 cc but not more than 350 seconds/10 cc. |
| US09450219B2 |
Battery module
A battery module including at least two battery cells, each battery cell including a terminal surface having a terminal therein, a back surface, and a side surface extending in a plane between the terminal surface and the back surface, the back surface of one battery cell facing the back surface of another battery cell such that the at least two battery cells have face-to-face back surfaces; a housing fixing the at least two battery cells together; and a mid-support between the at least two battery cells, the mid-support including at least one base portion in an interposed, adjoining relationship with the face-to-face back surfaces of the battery cells, and at least one flange portion extending in a plane parallel to the plane of the side surface. |
| US09450214B2 |
Battery pack
A battery pack, including: an electrode assembly; a pouch accommodating the electrode assembly; an electrode lead connected with the electrode assembly and extending to the outside of the pouch; a slit part through which the electrode lead penetrates and a lead cover formed in the vicinity of the slit part; and an insulator covering the pouch and at least a portion of the electrode lead. |
| US09450210B2 |
Optical thin film laminate for organic electroluminescent display element, production method thereof, organic electroluminescent display element and display device
An organic electroluminescent display element, an optical thin film laminate and a production method thereof are disclosed. The optical thin film laminate comprises a circular polarizer film layer, a protection film layer provided on the light incidence side of the circular polarizer film layer, an adhesive layer provided on the light output side of the circular polarizer film layer, and a moisture and oxygen resistant film layer; wherein the moisture and oxygen resistant film layer is provided between the light output side of the circular polarizer film layer and the adhesive layer, and/or, between the light incidence side of the circular polarizer film layer and the protection film layer. |
| US09450209B2 |
Light-emitting element, light-emitting device, and display device
A light-emitting element with which a reduction in power consumption and an improvement in productivity of a display device can be achieved is provided. A technique of manufacturing a display device with high productivity is provided. The light-emitting element includes an electrode having a reflective property, and a first light-emitting layer, a charge generation layer, a second light-emitting layer, and an electrode having a light-transmitting property stacked in this order over the electrode having a reflective property. The optical path length between the electrode having a reflective property and the first light-emitting layer is one-quarter of the peak wavelength of the emission spectrum of the first light-emitting layer. The optical path length between the electrode having a reflective property and the second light-emitting layer is three-quarters of the peak wavelength of the emission spectrum of the second light-emitting layer. |
| US09450208B2 |
Organic electroluminescence display device
An organic electroluminescence display device according to the invention includes a TFT substrate, a retroreflective body formed on the TFT substrate so as to correspond to each of pixels, a plurality of organic electroluminescence elements formed on the retroreflective bodies so as to correspond to the pixels, and a pixel separation film adapted to section the pixels, and the pixel separation film is formed in an area corresponding to an area between a boundary between the pixels adjacent to each other and an outer periphery of the retroreflective body. |
| US09450197B2 |
Flexible display apparatus
A flexible display apparatus includes a plurality of pixels on a display area of a flexible substrate. A pad area is on a non-display area of the flexible substrate. A driving integrated circuit is electrically connected to the pad area. A support layer is on a surface of the flexible substrate opposite to a surface facing the driving integrated circuit. An adhesion layer attaches the support layer to the substrate. The adhesion layer has a first thickness in an area corresponding to the driving integrated circuit, and a second thickness in another area. The second thickness is less than the first thickness. |
| US09450196B2 |
Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device includes a first substrate; a conductive line formed on a first surface of the first substrate; an organic light emitting diode and an encapsulation layer on the conductive line; a second substrate on the encapsulation layer; a conductive pad connected to the conductive line and arranged in a through hole passing through the first substrate; and a driving circuit unit on a second surface opposite the first surface of the first substrate and connected to the conductive pad. |
| US09450195B2 |
Organic electroluminescent materials and devices
Phosphorescent metal complexes comprising a pendant redox-active metallocene are disclosed. These complexes are useful as emitters for phosphorescent OLEDs. |
| US09450193B2 |
Compound for organic photoelectric device and organic photoelectric device including the same
A compound for an organic photoelectric device, the compound being represented by the following Chemical Formula (“CF”) 1: |
| US09450192B2 |
Carbazole derivative and organic electroluminescent devices utilizing the same and fabrication method thereof
The present invention provides a carbazole derivative of formula (I) for an organic electroluminescent device: wherein Y represents a heteroatom selected from N, O, P, S, or a bicyclic or tricyclic heterocyclic ring; and Ar1 and Ar2 each independently represent an alkyl or aryl substituted or unsubstituted aromatic hydrocarbon, or an alkyl or aryl substituted or unsubstituted heterocyclic aromatic hydrocarbon. |
| US09450188B2 |
Carbazole derivative, light-emitting element material and organic semiconductor material
An object is to provide a novel carbazole derivative that has an excellent carrier-transport property and can be suitably used for a transport layer or as a host material of a light-emitting element. Another object is to provide an organic semiconductor material and a light-emitting element material each using the carbazole derivative. As the carbazole derivative that can achieve the above objects, a carbazole derivative in which a carbazolyl group whose either 2- or 3-position of carbazole is substituted by the 4-position of a dibenzothiophene skeleton or a dibenzofuran skeleton is bonded to aromatic hydrocarbon that has 14 to 70 carbon atoms and includes a condensed tricyclic ring, a condensed tetracyclic ring, a condensed pentacyclic ring, a condensed hexacyclic ring, or a condensed heptacyclic ring has been able to be synthesized. |
| US09450184B2 |
Multilayer-stacked resistive random access memory device
A multilayer-stacked resistive random access memory device includes: first and second electrode layers; a resistive oxide layer which is electrically coupled to the first and second electrode layers, which exhibits resistive switching characteristics and which includes a metal oxide containing a first metal selected from the group consisting of W, Ti, Zr, Sn, Ta, Ni, Ag, Cu, Co, Hf, Ru, Mo, Cr, Fe, Al, and combinations thereof; and a sulfide layer contacting the resistive oxide layer and including a metal sulfide that contains a second metal that is the same as the first metal. |
| US09450182B2 |
Self-aligned memory cell contact
In various embodiments, a memory storage element for storing two or more bits of information is formed by connecting two resistive change elements in series whereby the first resistive change element is made of a first material and the second resistive change element is made of a second material and the melting point of the first resistive change element material is greater than the melting point of the second resistive change element material such that the set and reset states of the two elements can be written and read. |
| US09450180B1 |
Structure and method to reduce shorting in STT-MRAM device
A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode. |
| US09450178B2 |
Magnetoresistive sensor, related manufacturing method, and related electronic device
A method for manufacturing a magnetoresistive sensor may include the following steps: forming a trench structure in a substrate, wherein the step of forming the trench structure comprises performing a wet etching process on a substrate material member, wherein the trench structure has a first side, a second side, and a third side, wherein the second side is connected through the first side to the third side, wherein the second side is at a first obtuse angle with respect to a side of the substrate, and wherein the third side is at a second obtuse angle with respect to the side of the substrate; forming a first magnetic element on the first side of the trench structure; forming a second magnetic element on the second side of the trench structure; and forming a third magnetic element on the third side of the trench structure. |
| US09450176B2 |
Rectifying device, transistor, and rectifying method
A rectifying device includes: a one-dimensional channel (18) formed with a semiconductor, electrons traveling through the one-dimensional channel; an electrode (26) that applies an effective magnetic field generated from a spin orbit interaction to the electrons traveling through the one-dimensional channel by applying an electric field to the one-dimensional channel, the effective magnetic field being in a direction intersectional to the direction in which the electrons are traveling; and an external magnetic field generating unit (38) that generates an external magnetic field in the one-dimensional channel. |
| US09450174B2 |
Piezoelectric element
Poly(α-amino acid) which contain: (A) a glutamic acid γ-ester unit represented by formula (I): and (B) one or more kinds of units selected from a glutamic acid γ-ester unit represented by formula (II), an alanine unit, a phenylalanine unit and an Nε-benzyloxycarbonyllysine unit, represented by formula (III), and a glutamic acid γ-ester unit represented by formula (IV) can be dissolved in various solvents and are useful for preparing piezoelectric elements which exhibit superior piezoelectricity. |
| US09450169B2 |
Omni-directional shear-horizontal wave magnetostrictive patch transducer and method of winding coil
Provided is a transducer. The transducer includes a permanent magnet that generates a magnetostatic field, a patch disposed below the permanent magnet and formed of a material that deforms according to a magnetic field, an insulator disposed on a top surface of the patch, and a coil wound around the patch and the insulator in a certain form and allowing a magnetomotive field to be induced on the patch according to an applied current. The wound coil has a form in which directions of the magnetostatic field generated by the permanent magnet and the magnetomotive field generated by winding the coil are orthogonal to each other. |
| US09450164B2 |
High voltage busing for cryogenics applications
An electrical bushing is disclosed for use in high voltage cryogenic applications. The bushing including first and second bushing portions and an electrical conductor disposed longitudinally within the portions. The electrical conductor has a first terminal extending from the first bushing portion and a second terminal extending from the second bushing portion. The first terminal is configured to couple to a first electrical element at ambient temperature, and the second terminal is configured to couple to a second electrical element at cryogenic temperature. The first and second bushing portions comprise a base insulator material, while the first bushing portion further comprises an environmental protection layer disposed over the base insulator portion. |
| US09450161B2 |
Method of manufacturing a light-emitting device by sintering conductive pastes
A method of manufacturing a light-emitting device, includes: disposing a first conductive paste on a substrate and sintering the first conductive paste to forma first bonding layer; disposing a second conductive paste on a semiconductor light-emitting element and sintering the second conductive paste to form a second bonding layer; polishing surfaces of the first bonding layer and the second bonding layer; and causing a third conductive paste to intervene between the first bonding layer and the second bonding layer and sintering the third conductive paste to bond the first bonding layer and the second bonding layer together. |
| US09450160B2 |
Reflecting resin sheet, light emitting diode device and producing method thereof
A reflecting resin sheet provides a reflecting resin layer at the side of a light emitting diode element. The reflecting resin sheet includes a release substrate and the reflecting resin layer provided on one surface in a thickness direction of the release substrate. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be capable of being in close contact with the light emitting diode element. |
| US09450159B2 |
Light-emitting diode package and method for manufacturing same
Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity. |
| US09450158B2 |
Epoxy resin composition for optical semiconductor device, and lead frame for optical semiconductor device, encapsulation type optical semiconductor element unit and optical semiconductor device each obtainable by using the epoxy resin composition
An optical semiconductor device includes a metal lead frame including first and second plate portions, an optical semiconductor element mounted on the metal lead frame, and a reflector provided around the optical semiconductor element. A material for the reflector is an epoxy resin composition containing: (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) at least one of a carboxylic acid and water. Components (C) and (D) are present in a total proportion of 69 to 94 wt % based on the amount of the overall epoxy resin composition, and the component (E) is present in a proportion of 4 to 23 mol % based on the total amount of the components (B) and (E). The resin composition has a higher glass transition temperature, and is excellent in moldability and blocking resistance and substantially free from warpage. |
| US09450157B2 |
Ultraviolet light emitting device using metal non-bondable amorphous fluororesin molding compound
An ultraviolet light emitting device having high quality and high reliability is provided by preventing deterioration of electrical characteristics which is associated with an ultraviolet light emission operation and caused by a sealing resin. The ultraviolet light emitting device is an ultraviolet light emitting device including: an ultraviolet light emitting element (2) formed of a nitride semiconductor; and an ultraviolet-transparent sealing resin (3) covering the ultraviolet light emitting element (2), wherein at least a specific portion (3a) of the sealing resin (3), which is in contact with pad electrodes (18) and (17) of the ultraviolet light emitting element (2), is a first type amorphous fluororesin, and a terminal functional group of a polymer or a copolymer that forms the first type amorphous fluororesin is a nonreactive terminal functional group which is not bondable to a metal that forms the pad electrodes (16) and (17). |
| US09450156B2 |
Package of light emitting diode and method for manufacturing the same
Provided is a package of a light emitting diode. The package according to an embodiment includes a package of a light emitting diode, the package comprising: a base layer including an entire top surface that is substantially flat; a light emitting diode chip on the base layer; a lead frame electrically connected to the light emitting diode chip; and a reflective coating layer comprising titanium oxide, wherein a top surface of the reflective coating layer is substantially parallel to a top surface of the base layer, and wherein ends of the reflective coating layer and base layer are aligned with each other. |
| US09450154B2 |
Method for fabricating microstructure to generate surface plasmon waves
A method for fabricating a microstructure to generate surface plasmon waves comprises steps of: preparing a substrate, and using a carrier material to carry a plurality of metallic nanoparticles and letting the metallic nanoparticles undertake self-assembly to form a microstructure on the substrate, wherein the metallic nanoparticles are separated from each other or partially agglomerated to allow the microstructure to be formed with a discontinuous surface. The present invention fabricates the microstructure having the discontinuous surface by a self-assembly method to generate the surface plasmon waves, thus exempts from using the expensive chemical vapor deposition (CVD) technology and is able to reduce the time and cost of fabrication. The present invention also breaks the structural limitation on generation of surface plasmon waves to enhance the effect of generating the surface plasmon waves. |
| US09450148B2 |
Optical device having mesas
An optical device and method for fabricating an optical device. The optical device comprising: a semiconductor material comprising an active layer configured to emit light when an electrical current is applied to the device and/or to generate an electrical current when light is incident on the active layer, wherein the semiconductor material comprises a first surface and an opposed second surface, from which light is emitted from and/or received by the device, and wherein the first surface defines a first structure comprising the active layer and configured to reflect light emitted from the active layer toward the second surface and/or to reflect light received by the device toward the active layer, and the second surface defines a second structure configured to permit light incident on the second surface at an angle outside a critical angle range to the planar normal to pass therethrough. |
| US09450146B2 |
Light-emitting device, light-emitting device package, and light unit
A light-emitting device, according to one embodiment, comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer which is underneath the first conductive semiconductor layer, and a second conductive semiconductor layer which is underneath the active layer; a first electrode which is arranged under the light-emitting structure and is electrically connected to the second conductive semiconductor layer; a reflection layer which is arranged inside the second conductive semiconductor layer and arranged apart from the first electrode and the active layer; and a second electrode which is electrically connected to the first conductive semiconductor layer. |
| US09450144B2 |
Plant illumination device and method
An improved method to produce artificial light for plant cultivation, an illumination device with a semiconductor light emission solution and device suited for plant cultivation in a greenhouse environment are described. The best mode is considered to be a lighting device with binary alloy quantum dots (110, 120, 130, 140, 150, 160) made by colloidal methods to produce a size distribution of quantum dots that produces an emission spectrum similar to the photosynthetically active radiation (PAR) spectrum. The methods and arrangements allow more precise spectral tuning of the emission spectrum for lights used in plant (310, 311) cultivation. Therefore unexpected improvements in the photomorphogenetic control of plant growth, and further improvements in plant production are realized. |
| US09450140B2 |
Thin film deposition apparatus and method of manufacturing organic light-emitting display apparatus using the same
A thin film deposition apparatus used to manufacture large substrates on a mass scale and that allows high-definition patterning, and a method of manufacturing an organic light-emitting display apparatus using the same, the apparatus includes a loading unit fixing a substrate onto an electrostatic chuck; a deposition unit including a chamber maintained in a vacuum state and a thin film deposition assembly disposed in the chamber, separated from the substrate by a predetermined distance, to deposit a thin film on the substrate fixed on the electrostatic chuck; an unloading unit separating the substrate on which a deposition process is completed, from the electrostatic chuck; a first circulation unit sequentially moving the electrostatic chuck on which the substrate is fixed, to the loading unit, the deposition unit, and the unloading unit; and a second circulation unit returning the electrostatic chuck separated from the substrate to the loading unit from the unloading unit, wherein the first circulation unit passes through the chamber when passing through the deposition unit. |
| US09450139B2 |
Manufacturing method of semiconductor film, manufacturing method of semiconductor device, and manufacturing method of photoelectric conversion device
A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed. |
| US09450138B2 |
Photovoltaic cell and photovoltaic cell manufacturing method
A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body. |
| US09450133B2 |
Photosensor and display device
Thin film transistors including an oxide semiconductor containing indium, gallium, and zinc are easily arranged in a matrix over a large substrate and have small characteristic variations. With amplifier circuits and driver circuits of display elements which include the thin film transistors including an oxide semiconductor containing indium, gallium, and zinc with small characteristic variations, intensity distribution of light received by the photodiodes arranged in a matrix is converted into electrical signals with high reproducibility and output, and the display elements arranged in a matrix can be uniformly driven. |
| US09450131B1 |
Rollable and accordian foldable refractive concentrator space solar array panel
A rollable and accordion foldable refractive lens concentrator flexible solar array blanket structure assembly for a spacecraft/satellite application consisting of at least one or more rows of electrically interconnected solar cells and at least one or more rows of deployable elongated refractive lenses elevated and aligned from the top surface of the solar cells. The entire blanket assembly, inclusive of lenses and solar cell substrates, kinematically deploys by unrolling or unfolding the assembly for its stowed package configuration, and the final tensioning of the blanket assembly produces an aligned assembly where the solar cell substrate subassembly and the lens subassembly are coplanar. Deployment of the integrated blanket assembly (with refractive lenses) is directly coupled through the unrolling or the accordion unfolding deployment kinematics of the concentrator blanket assembly. |
| US09450124B1 |
Fabrication methodology for optoelectronic integrated circuits
A method of forming an integrated circuit employs a plurality of layers supported on a substrate that include i) n-type contact layer, ii) a p-type modulation doped quantum well structure (MDQWS) above the n-type contact layer, iii) n-type MDQWS above the p-type MDQWS, and iv) p-type contact layer(s) above the n-type MDQWS. A feature for a thyristor is defined by a mesa at the p-type contact layer of iv). A first layer of metal is deposited on the feature, which is then etched for at least one other device. Additional layer(s) of metal is deposited on the feature to form cumulative metal layers, which are etched away to form a set of mesas and corresponding electrodes for the thyristor. The cumulative metal layers that cover the feature and contact the mesa at the p-type contact layer of iv) are patterned to form an anode electrode of the thyristor. |
| US09450123B2 |
Thermo-tunneling design for quantum well photovoltaic converter
A design of a quantum well region that allows faster and more efficient carrier collection in quantum well solar cells. It is shown that for a quantum well material system displaying a negligible valence band offset, the conduction band confinement energies and barrier thicknesses can be designed to favor a sequential thermionic promotion and resonant tunneling of electrons to the conduction band continuum resulting in faster carrier collection rates than for a conventional design. An evaluation of the proposed design in the context of devices incorporating GaAs/GaAsN quantum wells shows a collection of all photo-generated carriers within several to tenths of ps (10−12 s) from deep quantum wells rather than several ns, as it is the case for conventional designs. The incorporation of the proposed design in single and multijunction solar cells is evaluated with efficiency enhancements. |
| US09450116B2 |
Thin film solar cell and manufacturing method therefor
In the present invention, in order to achieve a point contact, a thin film solar cell has a thin film light absorbing layer (3) disposed between a transparent conducive film (4) and a back-side metal electrode layer (2), and at the interface between the back-side metal electrode layer (2) and the light absorbing layer (3), the thin film solar cell is provided with a nanoparticle dispersion layer (5) including nanoparticles (6, 6 . . . ), where at least the surface of the nanoparticles is an insulator. |
| US09450113B2 |
Alignment for metallization
Forming a metal layer on a solar cell. Forming a metal layer can include placing a patterned metal foil on the solar cell, where the patterned metal foil includes a positive busbar, a negative busbar, a positive contact finger extending from the positive busbar, a negative contact finger extending from the negative busbar, and a metal strip, and one or more tabs. The positive and negative busbars and the positive and negative contact fingers can be connected to one another by the metal strip and tabs. Forming the metal layer can further include coupling the patterned metal foil to the solar cell and removing the metal strip and tabs. Removing the metal strip and tabs can separate the positive and negative busbars and contact fingers. |
| US09450111B2 |
Schottky barrier diode
A Schottky barrier diode includes a substrate, a buffer layer formed on the substrate, an upper layer formed on the buffer layer, a first electrode layer formed on the upper layer as an anode of the Schottky barrier diode, a second electrode layer formed on the upper layer as a cathode of the Schottky barrier diode, and a first n-type doping region formed in the upper layer and under the first electrode layer, and contacting the first electrode layer. An edge of the first n-type doping region and an edge of the first electrode layer are separated by a first predetermined distance at a first direction at which the first electrode layer faces the second electrode layer. |
| US09450109B2 |
MEMS devices and fabrication methods thereof
A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate. |
| US09450104B2 |
Semiconductor device and manufacturing method thereof
The semiconductor device includes an oxide semiconductor film having a first region and a pair of second regions facing each other with the first region provided therebetween, a gate insulating film over the oxide semiconductor film, and a first electrode overlapping with the first region, over the gate insulating film. The first region is a non-single-crystal oxide semiconductor region including a c-axis-aligned crystal portion. The pair of second regions is an oxide semiconductor region containing dopant and including a plurality of crystal portions. |
| US09450102B2 |
Semiconductor device and method for manufacturing the same
Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2. |
| US09450101B2 |
Thin film transistor, array substrate and display apparatus
A thin film transistor, comprising: a substrate; a first electrode formed on the substrate; a first insulation layer formed on the first electrode; a gate electrode formed on the first insulation layer; a second insulation layer formed on the gate electrode; an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and a second electrode formed on the active layer and electrically connected to the first electrode through the active layer, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode. |
| US09450097B2 |
Methods for doping Fin field-effect transistors and Fin field-effect transistor
A method of doping a fin field-effect transistor includes forming a plurality of semiconductor fins on a substrate wherein each semiconductor fin of the plurality of semiconductor fins has a top surface and sidewalls. The method includes forming a gate stack over the top surface and sidewalls of each semiconductor fin. The method includes removing a portion of a first semiconductor fin exposed by the gate stack. The method includes growing a first stressor region connected to a remaining portion of the first semiconductor fin. The method includes exposing a second semiconductor fin to a deposition process to form a dopant-rich layer comprising an n-type or a p-type dopant on the top surface and the sidewalls of the second semiconductor fin. The method includes diffusing the dopant from the dopant-rich layer into the second semiconductor fin using an annealing process. |
| US09450095B1 |
Single spacer for complementary metal oxide semiconductor process flow
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures. |
| US09450091B2 |
Semiconductor device with enhanced mobility and method
In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. |
| US09450090B2 |
Semiconductor memory device having an electrically floating body transistor
An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. |
| US09450088B2 |
High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09450086B2 |
Semiconductor device
To enhance a semiconductor device. A semiconductor device has a plurality of p+-type semiconductor regions disposed between the mutually adjacent two gate trenches, in a cell region. The p+ type semiconductor regions are disposed spaced apart from each other, in plan view, in a p-type body layer in a portion positioned between the mutually adjacent two gate trenches. Any of a p-type impurity concentration in each of the p+ type semiconductor regions is higher than the p-type impurity concentration in the p-type body layer. |
| US09450084B2 |
Wide band gap semiconductor device
A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band gap of a semiconductor material is wider than that of silicon, a circuit that limits a current when a main transistor is short circuited is provided, and the main transistor that mainly serves to pass a current, a sensing transistor that is connected in parallel to the main transistor and detects a microcurrent proportional to a current flowing in the main transistor, and a lateral MOSFET that controls a gate of the main transistor on the basis of an output of the sensing transistor are formed on the same semiconductor. |
| US09450082B2 |
Integrated termination for multiple trench field plate
A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain drift region. The vertical MOS transistor has chamfered corners; each chamfered corner extends across at least five of the drain trenches. A RESURF termination trench surrounds the drain trenches, separated from sides and ends of the drain trenches by distances which are functions of the drain trench spacing. At the chamfered corners, the termination trench includes external corners which extend around an end of a drain trench which extends past an adjacent drain trench, and includes internal corners which extend past an end of a drain trench which is recessed from an adjacent drain trench. The termination trench is separated from the drain trenches at the chamfered corners by distances which are also functions of the drain trench spacing. |
| US09450081B2 |
High voltage GaN transistor
A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2. |
| US09450080B2 |
Method for manufacturing semiconductor device
The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film. |
| US09450079B2 |
FinFET having highly doped source and drain regions
A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. |
| US09450078B1 |
Forming punch-through stopper regions in finFET devices
In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device. |
| US09450071B2 |
Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices
Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer. |
| US09450070B2 |
Method for manufacturing a silicon semiconductor substrate including a diffusion layer prior to forming a semiconductor device thereon
A method for manufacturing a silicon semiconductor substrate including a diffusion layer prior to forming a semiconductor device thereon, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 μm or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an atmosphere consisting of oxygen or oxygen and at least one of argon, helium, or neon, followed by a second heat treatment performed in an atmosphere comprised of nitrogen or nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs. |
| US09450068B2 |
Method for manufacturing silicon carbide semiconductor device
In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed. |
| US09450067B2 |
Semiconductor devices comprising aluminum oxide
A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide overlies the dielectric material in a first region of the structure. A second region of the structure includes a first titanium nitride portion overlying the dielectric material, magnesium over the first titanium nitride portion, and a second titanium nitride portion over the magnesium. Methods of forming the semiconductor structure including aluminum oxide are also disclosed. |
| US09450066B2 |
Vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer and method of forming a VMGFET
Methods for forming a vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer are described. The methods include providing a process of making VMGFET devices without critical alignment of masks between sequential etch and diffusion steps. The oxide layer of the SOI wafer is used for a self-limiting etch stop layer and for a sacrificial layer to form an insulating layer between a gate electrode and a substrate. The proper location of the gate electrode with respect to the source and drain junctions is insured by using a silicon gate structure as a mask layer for the diffusion process for defining the source and drain junctions. |
| US09450063B2 |
Semiconductor device and method
A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer. |
| US09450060B2 |
Method of manufacturing a silicon carbide semiconductor device
A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided. |
| US09450052B1 |
EEPROM memory cell with a coupler region and method of making the same
An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation. |
| US09450050B2 |
Lateral super junctions with high substrate breakdown and build in avalanche clamp diode
This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance. |
| US09450049B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material. |
| US09450048B2 |
Semiconductor device and manufacturing method and operating method for the same
A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high voltage threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high voltage threshold voltage channel region is formed in the first well and extending down from the surface of the substrate. |
| US09450040B2 |
Organic light emitting diode display
An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line and for transferring a data signal, a driving voltage line crossing the scan line and for transferring a driving voltage, a switching thin film transistor coupled to the scan line and the data line, a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor, and an organic light emitting diode (OLED) coupled to a driving drain electrode of the driving thin film transistor, wherein a driving semiconductor layer of the driving thin film transistor is bent and in a plane substantially parallel to the substrate. |
| US09450039B2 |
Organic light emitting display apparatus and method of manufacturing the same
An organic light emitting display apparatus and a method of manufacturing the same are disclosed. The organic light emitting display apparatus includes, for example, a bus electrode, an insulating layer covering the bus electrode and having a bus electrode hole exposing at least a part of the bus electrode, a pixel electrode formed on the insulating layer and electrically coupled with the bus electrode, a pixel defining layer exposing a part of the pixel electrode and a part of the bus electrode, a first intermediate layer on the pixel defining layer and the pixel electrode, the first intermediate layer having a first opening to expose the part of the bus electrode, an emission layer disposed on the first intermediate layer, and an opposite electrode to correspond to the pixel electrode and the bus electrode and contacting the bus electrode through the first opening and the bus electrode hole. |
| US09450038B2 |
Flexible display
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. |
| US09450036B2 |
Semiconductor device and method of driving the semiconductor device
Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109). |
| US09450035B2 |
Organic light emitting display device and method for manufacturing the same
The organic light emitting display device includes a flexible substrate, a thin-film transistor on the flexible substrate, a first anode on the thin-film transistor, a second anode on the same plane with the first anode and spaced apart from the first anode so as to surround the first anode, an organic light emitting layer on the first anode and the second anode, and a cathode on the organic light emitting layer. The second anode includes an opening where the first anode is encompassed therein. The shape of the first anode and the second anode and arrangement thereof reduces a segment length of an anode in a bending direction of the organic light emitting display device, and, thus, occurrence of cracks in the anode can be minimized. |
| US09450033B2 |
Organic light emitting diode (OLED) display apparatus having light sensing function
An organic light emitting diode (OLED) display apparatus having an optical sensing function is provided. The OLED display apparatus may photograph an external object by sensing input light from the external object that passes through an imaging pattern included in a display panel. |
| US09450025B2 |
Resistive memory device and method of operating resistive memory device
A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line. |
| US09450024B2 |
Field effect transistor constructions and memory arrays
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers. |
| US09450022B1 |
Memristor devices and fabrication
A method for fabricating a digital memristor crossbar array includes applying a protective layer on at least a portion of a memristive layer. A method for fabricating an analog memristor crossbar array includes providing a self-aligning first electrode layer. An analog memristor includes a memristive layer bar arranged to self-align said second electrode on said memristive layer along its length. |
| US09450020B2 |
Multiple-bits-per-cell voltage-controlled magnetic memory
Voltage controlled magneto-electric tunnel junctions and memory devices are described which provide efficient high speed voltage switching of non-volatile magnetic devices (MeRAM) at high cell densities. A multi-bit-per-cell (MBPC) MeRAM is described which requires only a single transistor to write and read two data bits from the one MBPC MeRAM cell. |
| US09450013B2 |
Low noise CdHgTe photodiode array
A planar photodiode array including a useful layer made of CdxHg1-xTe. The useful layer includes at least two superimposed doped layers, each interface between two doped layers forming a single PN junction; the useful layer has at least one separation region, extending from the upper face of the useful layer, and separating at least two useful volumes while going through the PN junction; and beyond a predetermined depth in the useful layer, the average cadmium concentration in the useful volumes is less than the average cadmium concentration in the separation region. |
| US09450010B2 |
Light receiving elements for photoelectric conversion and capacitor elements for charge storing in joined substrates
Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film. |
| US09450009B2 |
Solid-state imaging device and camera system
There is provided a solid-state imaging device including a wafer in which a guard ring with conductivity in an insulation film layered on a first conductivity type substrate is formed between an edge portion of at least a first chip, out of the first chip and a second chip of a layered chip, and a scribe line region, at least two second conductivity type layers are formed at an interval within a region corresponding to the guard ring, in the first conductivity type substrate, and the guard ring includes a first guard ring part connected to one of the second conductivity type layers on a chip edge portion side, and a second guard ring part connected to another one of the second conductivity type layers on a scribe line side. |
| US09450007B1 |
Integrated circuit with reflective material in trenches and related methods
An IC may include a substrate and a layer, and an array of GMAPDs in the layer. The layer may have trenches extending between adjacent GMAPDs. The IC may include an optically reflective material within the trenches. The optically reflective material may also be electrically conductive. For example, the optically reflective material may comprise a metal. Also, the trenches may be arranged in a honeycomb pattern. |
| US09450005B2 |
Image pickup device and image pickup apparatus
An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section. |
| US09450003B2 |
Solid-state imaging device, method of manufacturing solid-state imaging device and electronic apparatus
A solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof, an electric-charge holding region in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out, and a transfer gate having a complete transfer path through which the electric charge accumulated in the photoelectric conversion element is completely transferred into the electric-charge holding region, and an intermediate transfer path through which the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined charge amount is transferred into the electric-charge holding region. The complete transfer path and the intermediate transfer path are formed in different regions. |
| US09450002B2 |
Detecting apparatus and detecting system
A detecting apparatus formed on a substrate, includes a plurality of pixels arranged in a matrix, and a signal line electrically connected to the pixels. Each of the pixels includes a sensing element that converts radiant ray or light to electric charges, an amplification thin film transistor that outputs an electric signal based on an amount of the electric charges, a capacitor that holds an electric signal output by the amplification thin film transistor, and a transfer thin film transistor that transfers an electric signal held in the capacitor to the signal line. |
| US09450001B2 |
Method and system for detecting light and designing a light detector
A light detection system which comprises an active region between a back contact layer and a front contact layer is disclosed. The active region comprises a quantum well structure having a quantum well between quantum barriers, wherein the quantum well comprises foreign atoms that induce an excited bound state at an energy level which is above an energy level characterizing the quantum barriers. |
| US09450000B2 |
Photodiode of high quantum efficiency
A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed. |
| US09449997B2 |
Electro-optical device, electronic apparatus, and method for manufacturing electro-optical device
An electro-optical device includes an element substrate main body, a first capacitance electrode that is arranged above the element substrate main body, and has a first metal film and a second metal film which is stacked onto the first metal film, a first protective insulating film that is arranged so as to cover a side wall of the first metal film, and expose at least a portion of a side wall of the second metal film, a dielectric film that is arranged throughout the side wall of the second metal film which is exposed from the first protective insulating film, and over the second metal film, and a second capacitance electrode that is arranged throughout the dielectric film on the second metal film, and over the dielectric film which is arranged in the side wall of the second metal film exposed from the first protective insulating film. |
| US09449986B1 |
3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings
A memory device includes a cell region including a channel region extending to be perpendicular to an upper surface of a substrate, a plurality of gate electrode layers stacked on the substrate adjacently to the channel region, a peripheral circuit region including a first active region disposed in the vicinity of the cell region, a second active region having an area larger than an area of the first active region, a plurality of first contacts connected to the first active region, and a plurality of second contacts connected to the second active region. A distance between the plurality of first contacts is less than that between the plurality of second contacts. |
| US09449981B2 |
Three dimensional NAND string memory devices and methods of fabrication thereof
A method includes forming an amorphous or polycrystalline semiconductor material over at least a portion of a sidewall of a front side opening and within front side recesses in a stack of alternating first and second material layers, forming a layer of a metal material over at least a portion of the sidewall of the front side opening and adjacent to the semiconductor material within the front side recesses; annealing the metal material and the semiconductor material within the front side recesses to form a large grain polycrystalline or single crystal semiconductor material charge storage region within each of the front side recesses by a metal induced crystallization process, and forming a tunnel dielectric layer and semiconductor channel in the front side opening. Following the metal induced crystallization process, at least a portion of the metal material is located between the charge storage regions and the second material layers. |
| US09449980B2 |
Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure
The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage during states without electrical bias between a semiconductor channel and charge storage elements. The tunneling dielectric includes a layered stack including at least, from outside to inside, a dielectric metal oxide layer and a silicon oxide layer. Upon application of electrical bias for programming or erasing, the band gap structure of the tunneling dielectric provides a lower tunneling barrier than an ONO stack of a comparable effective oxide thickness. Additionally, due to higher capacitive coupling to the channel with high-k metal oxide layer(s) in the tunneling dielectric, the efficiency of program, erase and read operations can be improved. During a zero-bias state, the tunneling dielectric can provide a higher energy barrier than the ONO stack, thereby providing enhanced data retention than the ONO stack. |
| US09449979B2 |
Ferroelectric memory device and fabrication process thereof, and methods for operation thereof
A new form of a solid-state non-volatile memory cell is presented. The solid-state memory cell comprises a series of different layers of ferroelectric materials, semiconductors, ferroelectric semiconductors, metals, and ceramics, and oxides. The memory device stores information in the direction and magnitude of polarization of the ferroelectric layers. Additionally, a method is presented for storing multiple bits of information in a single memory cell by allowing partial polarization of a single ferroelectric layer and stacking of multiple ferroelectric functional units on top of each other. Additionally, a technique for reading and writing said memory cell is presented. Additionally, the memory cell design allows for the formation of Schottky barriers which act to improve functionality and increase resistance. Additionally, a method is presented for depositing textured lithium niobate thin films. |
| US09449978B2 |
Semiconductor devices including a recessed access device and methods of forming same
A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides. |
| US09449977B2 |
Semiconductor devices and methods for fabricating the same
A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern. |
| US09449975B1 |
FinFET devices and methods of forming
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region. |
| US09449974B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer. |
| US09449973B2 |
Semiconductor device
A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line. |
| US09449971B2 |
Methods of forming FinFETs
An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin. |
| US09449968B2 |
Method for manufacturing a semiconductor device and a semiconductor device
A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel region and a drift zone between the source region and the drain region. The source and drain regions are arranged along a first direction parallel to the main surface. Gate trenches and a gate electrode are formed in the gate trenches. The gate trenches have a distance corresponding to a width d1 of the channel region, where d1≦2*ld and ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode. An auxiliary trench formed in the main surface extends in a second direction intersecting the first direction. The source region is formed using a doping method that introduces dopants via a sidewall of the auxiliary trench. |
| US09449963B2 |
Gate structure with hard mask structure formed thereon and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure. |
| US09449960B2 |
Electrostatic discharge protection structure
Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region. |
| US09449956B2 |
Optical apparatus
An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided on the substrate 1 and spaced apart from each other in a direction x, a light-transmitting resin 4 covering the light-receiving element 3, a light-transmitting resin 5 covering the light-emitting element 2, and a light-shielding resin 6 covering the light-transmitting resin 4 and the light-transmitting resin 5. The wiring pattern 8 includes a first light-blocking portion 83 interposed between the light-shielding resin 6 and the substrate 1 and positioned between the light-receiving element 3 and the light-emitting element 2 as viewed in x-y plane. The first light-blocking portion 83 extends across the light-emitting element 2 as viewed in the direction x. |
| US09449952B2 |
Accessing or interconnecting integrated circuits
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools. |
| US09449949B2 |
Method for manufacturing semiconductor device and semiconductor device
A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate. |
| US09449947B2 |
Semiconductor package for thermal dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks. |
| US09449943B2 |
Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate. |
| US09449931B2 |
Pillar bumps and process for making same
Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. |
| US09449930B2 |
Semiconductor devices and package substrates having pillars and semiconductor packages and package stack structures having the same
A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar. |
| US09449929B2 |
Semiconductor device and layout design system
In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval. |
| US09449928B2 |
Layer arrangement
A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer. |
| US09449925B2 |
Integrated passive devices
A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization. |
| US09449921B1 |
Voidless contact metal structures
Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void. |
| US09449917B2 |
Method of forming an inductor with magnetic material
In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. |
| US09449916B2 |
Radio-frequency integrated circuits including inductors and methods of fabricating the same
A radio-frequency integrated circuit (RFIC) includes a substrate, an N-type deep well region disposed in an upper region of the substrate and having a top surface coplanar with a top surface of the substrate, an inductor disposed over the N-type deep well region; and an insulation layer disposed between the inductor and the N-type deep well region, wherein the inductor is electrically insulated from the N-type deep well region by the insulation layer. |
| US09449915B2 |
Semiconductor device and method of manufacturing the same
Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric layer is located on the substrate. The dielectric layer has a plurality of openings, and side walls of the openings have concave-and-convex profile. |
| US09449912B1 |
Integrated circuit (IC) card having an IC module and reduced bond wire stress and method of forming
An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE. |
| US09449909B2 |
Method of forming a package substrate
In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail. |
| US09449908B2 |
Semiconductor package system and method
A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. |
| US09449907B2 |
Stacked semiconductor chips packaging
Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate. |
| US09449904B2 |
Semiconductor device
A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode. |
| US09449899B2 |
Semiconductor package with heat spreader
A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. |
| US09449898B2 |
Semiconductor device having backside interconnect structure through substrate via and method of forming the same
A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. |
| US09449896B2 |
Device comprising a three-dimensional integrated structure with simplified thermal dissipation, and corresponding fabrication method
A device includes a support, a three-dimensional integrated structure above the support, and a lateral encapsulation region arranged around the structure. The lateral encapsulation region includes first channels configured to make it possible to circulate a cooling fluid. |
| US09449893B2 |
Semiconductor module
A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion. |
| US09449891B1 |
Proximity switch fabrication method using angled deposition
A method involves applying a voltage to a first conductive surface and a second conductive surface separated by a conductive surface gap of a distance greater than the distance required to produce a tunneling current between the first and second conductive surfaces when the voltage is applied, and using angled deposition to deposit conductive material on the first and second conductive surfaces to narrow the conductive surface gap until a tunneling current appears across the first and second conductive surfaces responsive to the applied voltage. |
| US09449888B2 |
Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path. |
| US09449886B2 |
Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region. |
| US09449884B1 |
Semiconductor device with trench epitaxy and contact
A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench. |
| US09449882B1 |
Semiconductor device and manufacturing method thereof
In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed. |
| US09449879B2 |
Method of severing a semiconductor device composite
A method of severing a semiconductor device composite includes a carrier having a main surface and a semiconductor layer sequence arranged on the main surface including forming a separating trench in the semiconductor device composite by a first laser cut such that the separating trench only partially severs the semiconductor device composite in a vertical direction running perpendicular to the main surface, and severing the semiconductor device composite completely along the separating trench with a severing cut with a laser. |
| US09449878B2 |
Wafer processing method
A wafer processing method includes a cut groove forming step of positioning, from a back side of the substrate, a cutting blade to an area corresponding to a division line to form cut grooves in such a manner that the cutting blade does not reach a functional layer and part of a substrate is left, and a functional layer cutting step of performing irradiation with a laser beam along the division lines formed in the functional layer forming a wafer to perform ablation processing for the functional layer and cut the functional layer. In the cut groove forming step, the cut grooves are formed along the division lines in such a manner that an uncut part is left in a peripheral area of the wafer. |
| US09449871B1 |
Hybrid airgap structure with oxide liner
A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and a metal liner lines the copper filled trenches. An oxide liner lines the metal liner and covers the dielectric layer. One or more airgaps are formed between the copper filled trenches in areas in which the oxide liner was not present on the dielectric layer. A cap layer is formed on top of the one or more airgaps, the copper filled trenches, and portions of the oxide liner. |
| US09449870B2 |
Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other. |
| US09449868B2 |
Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films
A method of forming a photonic device that comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The method may further include forming a top diode material and an active diode region between the top and bottom diode materials. |
| US09449865B2 |
Electrostatic clamp, lithographic apparatus and method
The present invention provides a method for containing unwanted electric charge that accumulates on the surface of the dielectric of an electrostatic clamp. One source of such charge is found to be from the triple points where conductive interconnect lines 28 and conductive burl coatings 26 contact the surface of the dielectric 20. These triple points are potted by means of an insulating material 29 such that any emitted electrons are contained. While the interconnect lines 28 are completely covered, in the case of the conductive burl coating 26 although the burl 25 cannot be completely covered by the insulating material, the triple point is moved to a region where there is no or at least only low electric field whereby there is no or only little emission of electrons. |
| US09449863B2 |
Device for aligning and pre-fixing a wafer
A device for aligning and prefixing a flat substrate on a carrier substrate for the further processing of the substrate. The device includes aligning means for aligning a substrate's outside contour relative to a carrier substrate's outside contour by engaging the substrate's outside contour. The alignment of the substrate is carried out along a substrate plane E that is parallel to a contact surface of the substrate. Attaching means is provided for at least partial prefixing of the aligned substrate on the carrier substrate. |
| US09449859B2 |
Multi-gas centrally cooled showerhead design
A method and apparatus for chemical vapor deposition and/or hydride vapor phase epitaxial deposition are provided. The apparatus generally include a lower bottom plate and an upper bottom plate defining a first plenum. The upper bottom plate and a mid-plate positioned above the upper bottom plate define a heat exchanging channel. The mid-plate and a top plate positioned above the mid-plate define a second plenum. A plurality of gas conduits extend from the second plenum through the heat exchanging channel and the first plenum. The method generally includes flowing a first gas through a first plenum into a processing region, and flowing a second gas through a second plenum into a processing region. A heat exchanging fluid is introduced to a heat exchanging channel disposed between the first plenum and the second plenum. The first gas and the second gas are then reacted to form a film on a substrate. |
| US09449858B2 |
Transparent reflector plate for rapid thermal processing chamber
The present invention generally relates to methods and apparatus for processing substrates. Embodiments of the invention include apparatuses for processing a substrate comprising a ceramic reflector plate, which may be optically transparent. The reflector plate may include a reflective coating and be part of a reflector plate assembly in which the reflector plate is assembled to a baseplate. |
| US09449857B2 |
Substrate processing apparatus and substrate processing method
A substrate processing apparatus is provided including: a liquid processing unit that processes a substrate with a processing liquid; a carry-in port formed in the liquid processing unit and configured to carry-in the substrate in a dry-state before the substrate is processed with the processing liquid; a carry-out port formed in the liquid processing unit and configured to carry-out the substrate in a wet-state after completing the liquid processing; a supercritical dry processing unit that performs a dry processing for the substrate using a supercritical fluid; a first substrate transport unit that transports the substrate in a dry-state before the substrate is processed with the processing liquid to the carry-out port of the liquid processing unit; and a second substrate transport unit that transports the substrate in a wet-state after completing the liquid processing from the carry-out port of the liquid processing unit to the supercritical dry processing unit. |
| US09449854B2 |
Semiconductor device and method of manufacturing the same
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained.As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth. |
| US09449853B2 |
Method for manufacturing semiconductor device comprising electron trap layer
A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted. |
| US09449851B2 |
Local doping of two-dimensional materials
This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material. |
| US09449847B2 |
Method for manufacturing a semiconductor device by thermal treatment with hydrogen
A semiconductor device is manufactured by forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer. This includes forming a porous area at a surface of a semiconductor body that includes a porous structure in the porous area, forming the semiconductor layer on the porous area by epitaxial growth so as to have a thickness in a range of 5 μm to 200 μm, and forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer by ion implantation. After forming the semiconductor regions, hydrogen is introduced into the porous area by a thermal treatment, activating a reallocation of pores and causing cavities to be generated. The semiconductor layer is separated from the semiconductor body along the porous area. After the separation, rear side processing is applied to the semiconductor layer. |
| US09449841B2 |
Methods and systems for chemical mechanical polish and clean
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions. |
| US09449837B2 |
3D chip-on-wafer-on-substrate structure with via last process
Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate. |
| US09449835B2 |
Methods of forming features having differing pitch spacing and critical dimensions
Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer. |
| US09449834B2 |
Method of fabricating semiconductor devices including PMOS devices having embedded SiGe
A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom. |
| US09449833B1 |
Methods of fabricating self-aligned FETS using multiple sidewall spacers
A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material. |
| US09449831B2 |
Oxide-nitride-oxide stack having multiple oxynitride layers
An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer. |
| US09449827B2 |
Metal semiconductor alloy contact resistance improvement
Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element. |
| US09449820B2 |
Epitaxial growth techniques for reducing nanowire dimension and pitch
Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing an SOI wafer having an SOI layer separated from a substrate by a BOX, wherein the SOI layer includes Si; patterning at least one nanowire in the SOI layer, wherein the at least one nanowire as-patterned has a square cross-sectional shape with flat sides; growing epitaxial SiGe on the outside of the at least one nanowire using an epitaxial process selective for growth of the epitaxial SiGe on the flat sides of the at least one nanowire; removing the at least one nanowire selective to the epitaxial SiGe, wherein the epitaxial SiGe that remains includes multiple epitaxial SiGe wires having been formed in place of the at least one nanowire that has been removed. |
| US09449816B2 |
Method for producing graphene oxide with tunable gap
A method of fabricating a graphene oxide material in which oxidation is confined within the graphene layer and that possesses a desired band gap is provided. The method allows specific band gap values to be developed. Additionally, the use of masks is consistent with the method, so intricate configurations can be achieved. The resulting graphene oxide material is thus completely customizable and can be adapted to a plethora of useful engineering applications. |
| US09449810B2 |
Advanced ultra low k SiCOH dielectrics prepared by built-in engineered pore size and bonding structured with cyclic organosilicon precursors
Disclosed herein is an ultra-low dielectric (k) film and methods of making thereof. A ultra-low k film has a covalently bonded network comprising atoms of silicon, oxygen, carbon, and hydrogen, a cyclotrisilane structure, and a plurality of pores having a pore size distribution (PSD) of less than about 1.1 nanometers (nm). The ultra-low k film has a k value of less than about 2.4 and at least about 28 atomic percent of carbon. |
| US09449809B2 |
Interface adhesion improvement method
The present disclosure describes methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer. |
| US09449808B2 |
Apparatus for advanced packaging applications
The embodiments disclosed herein pertain to novel methods and apparatus for removing material from a substrate. In certain embodiments, the method and apparatus are used to remove negative photoresist, though the disclosed techniques may be implemented to remove a variety of materials. In practicing the disclosed embodiments, a stripping solution may be introduced from an inlet to an internal manifold, sometimes referred to as a cross flow manifold. The solution flows laterally through a relatively narrow cavity between the substrate and the base plate. Fluid exits the narrow cavity at an outlet, which is positioned on the other side of the substrate, opposite the inlet and internal manifold. The substrate spins while in contact with the stripping solution to achieve a more uniform flow over the face of the substrate. In some embodiments, the base plate includes protuberances which operate to increase the flow rate (and thereby increase the local Re) near the face of the substrate. |
| US09449804B2 |
Dual field multipole converging ion guides, hyperbolic ion guides, and related methods
An ion guide generates a first RF field of Nth order where N is an integer equal to or greater than 2, and a second RF field of 2Nth order superimposed on the first RF field. The first and second RF fields may be generated by respective first and second sets of electrodes. Another ion guide may include a converging entrance section followed by an exit section. The converging section may have a hyperbolic profile. A hyperbolic profile may be presented by electrodes having a twisted configuration relative to an ion guide axis. |
| US09449798B2 |
Plasma processing device, printing apparatus, printing system, computer program product, and method for manufacturing printed material
A plasma processing device includes a plasma processing unit that performs plasma processing on a predetermined area on a target recording medium at least two times; and a control unit that sets a plasma energy amount used by the plasma processing unit to perform a first plasma processing on the predetermined area of the target recording medium as a first energy amount and sets a plasma energy amount used by the plasma processing unit to perform a second plasma processing on the predetermined area as a second energy amount smaller than the first energy amount. |
| US09449797B2 |
Component of a plasma processing apparatus having a protective in situ formed layer on a plasma exposed surface
A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component. The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer. |
| US09449795B2 |
Ceramic showerhead with embedded RF electrode for capacitively coupled plasma reactor
A showerhead assembly for a substrate processing system includes a back plate connected to a gas channel. A face plate is connected adjacent to a first surface of the back plate and includes a gas diffusion surface. An electrode is arranged in one of the back plate and the face plate and is connected to one or more conductors. A gas plenum is defined between the back plate and the face plate and is in fluid communication with the gas channel. The back plate and the face plate are made of a non-metallic material. |
| US09449792B2 |
Charged particle beam writing apparatus, aperture unit, and charged particle beam writing method
A charged particle beam writing apparatus according to an embodiment includes: a beam emitter configured to emit a charged particle beam; an aperture having an opening portion through which the charged particle beam emitted by the beam emitter passes; an aperture beam tube being provided on a surface of the aperture and functioning as a thermally conductive member having thermal conductivity; and a heater provided on a surface of the aperture beam tube and configured to supply heat to the aperture via the aperture beam tube. |
| US09449786B2 |
Charged particle radiation device and specimen preparation method using said device
The present invention enables a sample to be observed in a clean state directly after preparation of a final observation surface when preparing a sample for observing a material that is sensitive to heat. The present invention is a method of preparing a sample using a charged particle beam device including a microprobe having a cooling mechanism, a first sample holder having a mechanism for retaining a sample in a cooled state, and a stage into which the microprobe and the first sample holder can be introduced, the method including cutting a bulk-shaped sample piece from the sample on the first sample holder retained in a cooled state; adhering the sample piece to a distal end of the microprobe that is cooled to a fixed temperature and transferring the sample piece to a second sample holder for thin film observation retained in a cooled state, which is different from the first sample holder, within a vacuum chamber of the charged particle beam device; separating the sample piece that has been transferred to the second sample holder from the microprobe and thin film processing the sample piece to a thickness that is less than the thickness during cutting; and observing the sample piece after the thin film processing. |
| US09449785B2 |
Workpiece transport and positioning apparatus
An automated workpiece processing apparatus including a processing section including a processing module configured for processing a workpiece at a process location, a transport module including a first shuttle stage, a second shuttle stage independent of the first stage, and an end effector connected to at least one of the first and second stages, the end effector being configured to hold and transport the workpiece into and out of the processing module, and having a range of motion, defined by a combination of the first and second stage, extending from a workpiece holding station outside the processing module to the processing location inside the processing module so the end effector defines a processing stage of the processing module, and an automated loading and transport section including a load port module through which workpieces are loaded into the automated loading and transport section, and being communicably connected to the transport module. |
| US09449783B2 |
Enhanced barrier for liquid metal bearings
The present disclosure is directed towards the prevention of high voltage instabilities within X-ray tubes. For example, in one embodiment, an X-ray tube is provided. The X-ray tube generally includes a stationary member, and a rotary member configured to rotate with respect to the stationary member during operation of the X-ray tube. The X-ray tube also includes a liquid metal bearing material disposed in a space between the shaft and the sleeve, a seal disposed adjacent to the space to seal the liquid metal bearing material in the space, and an enhanced surface area material disposed on a side of the seal axially opposite the space and configured to trap within the enhanced surface area material liquid metal bearing material that escapes the seal. |
| US09449777B2 |
Circuit breaker arrangement and power distribution unit
A circuit breaker arrangement in supply of electric power has advantageous applications especially in power distribution units which supply DC power to electrical devices. Electromechanical circuit breakers are commonly used for circuit protection. They have a disadvantage of fixed tripping conditions, which can only be changed by changing the circuit breaker component. This is solved by providing a circuit breaker arrangement which has an electromechanical circuit breaker with a first, fixed tripping condition, and an additional circuit, which monitors the output current and mechanically trips the circuit breaker if the current exceeds a second tripping condition. This way, it is possible to use the first tripping condition of the electromechanical circuit breaker and/or a second, controllable tripping condition. |
| US09449776B2 |
Circuit breaker with input load increasing means
A circuit breaker comprises a switching mechanism that including a linkage with a drive joint that is mounted to be rotatable around a rotation axis by a driving force, wherein, during the ON operation, an axis formed by the rotation axis and the point of action of the driving force makes an acute angle with the line of action of the driving force, so that the drive joint causes the tangential force of the driving force to act as input load, at least one hinge part of the linkage is configured in a way that the connecting pin is movably hinged to the long hole-shaped hinge hole, and at least one hinge part of the linkage causes the tangential force to increase by changes in the acute angle as the connecting pin moves from a first side of the long hole-shaped hinge hole to a second side. |
| US09449775B2 |
Thermal trip device, switching device, thermal magnetic circuit breaker and method for protecting an electrical circuit from damage
A thermal trip device of a thermal magnet circuit breaker is disclosed for protecting an electrical circuit from damage by overload. A switching device including such a thermal trip device is also disclosed, for interrupting a current flow. Further, a thermal magnetic circuit breaker is disclosed for protecting an electrical circuit from damage caused by overload or short circuit, including at least such a switching device. Further, a method is disclosed, for protecting an electric circuit from damage by overload by way of a thermal trip device of a thermal magnet circuit breaker. |
| US09449773B2 |
Seismic actuator
An actuator that includes a shelf having a pivot cone, a first member, a second member, a trigger pin and a trigger lever latch. The first member includes a weight, a first shaft extending upwardly from the weight and through an opening in the pivot cone, and a first plate affixed to the first shaft. The first plate is supported by the pivot cone. The second member includes a second plate resting on the first plate and a second shaft extending upwardly from the second plate. The trigger lever latch includes a first portion connected to the second shaft and a second portion extending upwardly at an angle away from the first portion. The trigger pin has an engagement surface. The trigger pin is movable between an operational state and a tripped state. The second end of the trigger lever latch is engaged with the engagement surface. |
| US09449770B2 |
Shimless button assembly for an electronic device
Embodiments of the present disclosure are directed to a shimless button assembly. According to such embodiments, a shimless button assembly includes a button component and a switch mechanism. The button component includes a compressible member that is configured to expand and contract in order to occupy a volume of space between the button component and the switch mechanism. The volume of space between the button component and the switch mechanism may be caused by differing tolerances between the various components of the button assembly, such as, for example, the button component and the switch mechanism. |
| US09449768B2 |
Stabilization techniques for key assemblies and keyboards
Key stabilization techniques for a key assembly or keyboard are provided. In one embodiment, a key assembly includes a keycap having a touch surface for receiving a press force that moves the keycap from an unpressed position toward a pressed position. The key assembly also includes a base having a planar-translation effecting mechanism supporting the keycap to guide the keycap in the press direction and the second direction as the keycap moves from the unpressed position toward the pressed position. A key stabilization mechanism positioned in the keycap, the base or both the keycap and the base configured to the stabilize the keycap so that the touch surface remains substantially planar while the keycap moves from the unpressed position toward the press position to resist tilt of the keycap and rotation of the keycap about an axis in the press direction as keycap moves toward the pressed position. |
| US09449765B2 |
Energy storage device, method of manufacturing same, and mobile electronic device containing same
An energy storage device comprises a first porous semiconducting structure (510) comprising a first plurality of channels (511) that contain a first electrolyte (514) and a second porous semiconducting structure (520) comprising a second plurality of channels (521) that contain a second electrolyte (524). In one embodiment, the energy storage device further comprises a film (535) on at least one of the first and second porous semiconducting structures, the film comprising a material capable of exhibiting reversible electron transfer reactions. In another embodiment, at least one of the first and second electrolytes contains a plurality of metal ions. In another embodiment, the first and second electrolytes, taken together, comprise a redox system. |
| US09449760B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, and length-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A Si content ratio is higher in a boundary portion between the outer portion and the inner portion. A relationship expressed by T1/(L0−L1)≦5.98 is satisfied when a minimum dimension in the length direction of the body is denoted by L0, a minimum dimension in the thickness direction of the multilayer unit is denoted by T1, and a minimum dimension in the length direction of the multilayer unit is denoted by L1. |
| US09449754B2 |
Coil constructions for improved inductive energy transfer
An inductor coil for an inductive energy transfer system includes multiple layers of a single wire having windings that are interlaced within at least two of the multiple layers such that both an input end and an output end of the wire enter and exit the coil on a same side of the coil. The input end and the output end of the wire may abut one another at the location where the input and output wires enter and exit the inductor coil. The wire can include one or more bundles of strands and the strands in each bundle are twisted around an axis extending along a length of the wire, and when there are at least two bundles, the bundles may be twisted around the axis. At least one edge of the inductor coil can be formed into a variety of shapes, such as in a curved shape. |
| US09449750B2 |
Electrical transformer assembly
A support frame for an electrical transformer assembly, comprising two loop-shaped parts, each loop-shaped part having a plurality of limbs, each limb having a peripheral recessed portion in which a primary electrical coil is mountable, and at least one secondary coil is mountable in piggyback on the primary electrical coil, one limb of each loop-shaped part having a straight section. The frame also includes an adjustable attaching means for attaching one of the loop-shaped parts with respect to the other loop-shaped part and adjusting a distance therebetween, so that only the straight sections are adjacent and form a central leg, the central leg being for receiving a magnetic core distinct from the attaching means. The frame provides a means and a method to efficiently secure adjacent windings in a circular core transformer kernel. |
| US09449746B2 |
Methods of manufacturing planar transformers
Planar transformers, and corresponding methods of manufacturing planar transformers are disclosed. The planar transformers include circuit layers that reduce termination losses on at least one of the circuit layers. The circuit layers are stacked together in a first direction and include at least first and second circuit layers. The first and second circuit layers each include an electrically conductive trace forming at least one winding having a first termination portion and a second termination portion that are separated by a gap. The gaps of the first and second circuit layers are offset relative to each other in a second direction different from the first direction. The circuit layers may further include a third circuit layer, which includes an electrically conductive trace having a grounded portion that is disposed adjacent to at least one of the gaps of the first and second circuit layers. |
| US09449745B2 |
Reactor, reactor-use coil component, converter, and power converter apparatus
A reactor 1A of the present invention includes a sleeve-like coil 2, a magnetic core 3 disposed inside and outside the sleeve-like coil 2 to form a closed magnetic path, and a case 4A storing the coil 2 and the magnetic core 3. At least part of the magnetic core 3 (herein, an outer core portion 32 provided on the outer circumferential side of the coil 2) is formed by a composite material containing magnetic substance powder and resin. The case 4A is formed by a bottom plate portion 40 and a wall portion 41 each being an independent member. In the reactor 1A, the coil 2 and the bottom plate portion 40 that is made of a non-magnetic metal material are integrally retained by a resin mold portion 21 formed by an insulating resin. Since the resin mold portion 21 fixes the coil 2 and the bottom plate portion 40, the heat of the coil 2 can be efficiently transferred to the installation target. Accordingly, the reactor 1A has an excellent heat dissipating characteristic. |
| US09449737B2 |
Dynamic application cable assembly and method for making the same
A cable and flange assembly has at least one cable and at least one flange. The cable has an armor, a jacket and at least one conductor element therein. The flange includes a flange body, an armor retainer and a grommet holder. The armor of the cable is configured to be secured to the flange via the armor retainer. |
| US09449735B2 |
Molded article of polyolefin-based resin expanded beads
An electrostatic dissipating molded article having a surface resistivity of 1×105 to 1×1010Ω and obtained by in-mold molding of multi-layered polyolefin-based resin expanded beads each having an polyolefin-based resin expanded core layer and a polyolefin-based resin cover layer which covers the polyolefin-based resin expanded core layer and which is formed from a polyolefin-based resin (A), a polymeric antistatic agent (B) of a block copolymer of a polyether block and a polyolefin block, and an electrically conductive carbon black (C), the components (A) to (C) being present in a specific proportion. |
| US09449732B2 |
Charge transport film, method for producing the same, and light-emitting element and photoelectric conversion element using the same
The present invention provides a charge transport film which is prepared through subjecting a coating film including at least one charge transporting agent to an atmospheric pressure plasma treatment, wherein electron transfer between the charge transport film and a substance that contacts with the charge transport film is promoted, and deterioration in performance due to diffusion and mixing or crystallization of low molecular weight components, such as a charge transporting agent, incorporated in a cured film is suppressed also in the case of film formation by a wet method, and which exhibits excellent charge transportability and stability over time; a production method with good productivity; and a light-emitting element and photoelectric conversion element equipped with the charge transport film, the atmospheric pressure plasma treatment being preferably a treatment that applies plasma, which is generated using a plasma generating apparatus and conveyed using an inert gas, to the coating film. |
| US09449726B2 |
100Mo compounds as accelerator targets for production of 99mTc
Methods of synthesizing 100Mo2C and 99mTcO4− are disclosed. Methods of 100Mo2C generation involve thermally carburizing 100MoO3. Methods of 99mTcO4 generation involve proton bombardment of 100Mo2C in a cyclotron. Yields of 99mTcO4 can be increased by sintering 100Mo2C prior to bombardment. The methods also include recycling of 100Mo2C to form 100MoO3. SPECT images obtained using 99mTcO4 generated by the disclosed methods are also presented. |
| US09449717B2 |
Memory built-in self-test for a data processing apparatus
A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact. |
| US09449716B2 |
Circuit board having bypass pad
An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. |
| US09449715B2 |
Semiconductor device having capability of generating chip identification information
A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit. |
| US09449714B2 |
Flexible interrupt generation mechanism
In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table. |
| US09449711B2 |
Shift register circuit and shading waveform generating method
A shift register circuit and a shading waveform generating method are disclosed. The shift register circuit includes plural stages of shift registers. Each stage of the shift register includes an output transistor, an input unit and a gate-shading circuit. The output transistor is configured for generating an output signal of the stage of the shift register. The input unit is configured for controlling a voltage level on a gate terminal of the output transistor. The gate-shading circuit includes a first switch, a second switch and a third switch. The first switch is configured for outputting a control signal. The second switch is configured for pulling down the voltage level on the gate terminal of the output transistor according to the control signal. The third switch is configured for pulling down a level on an output terminal of the output transistor according to the control signal. |
| US09449709B1 |
Volatile memory and one-time program (OTP) compatible memory cell and programming method
A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell. |
| US09449708B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array configured having NAND strings arranged therein; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to apply a verify voltage to a selected word line, apply a read pass voltage that renders conductive an unselected memory cell regardless of cell data to an unselected word line, and apply a bit line voltage of a certain value to a selected bit line, thereby executing a write verify operation that determines whether a selected memory cell has a desired threshold voltage or not. The control circuit is configured capable of changing a voltage value of the bit line voltage based on a position of the selected word line among the plurality of word lines relative to the NAND string. |
| US09449707B2 |
Systems and methods to mitigate program gate disturb in split-gate flash cell arrays
A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source. A second memory cell (150/152 or 158/160) having a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source. A source control circuit (102) that, during programming of the first memory cell, outputs a first voltage to the source of the first memory cell and keeps the source of the second memory cell floating. |
| US09449705B2 |
Programming schemes for multi-level analog memory cells
A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits. |
| US09449702B1 |
Power management
According to an embodiment of the invention there may be provided a method for measuring, by a power measurement circuit of a memory controller, a power consumption of a flash memory unit coupled to the memory controller to provide power measurements; wherein the memory controller further may include a read circuit, a write circuit, an erase circuit and a processor. |
| US09449698B1 |
Block and zone erase algorithm for memory
Techniques are provided for erasing a memory device. In one aspect, different zones of a block can be separately erased and subject to a verify test. Erase parameters can be optimized for each zone, so that endurance is improved. If one zone is found to be too slow to erase, it can be marked as being bad while other zones remain available for use. In another aspect, the zone-based erase occurs after a block based erased when a criterion is met, such as the block-based erase being too slow or failing to complete within an allowable number of program loops. The zone-based erase can occur after the block-based erase in the same erase operation, or in a subsequent, new erase operation. |
| US09449697B2 |
Semiconductor memory device and manufacturing method thereof
A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD). |
| US09449695B2 |
Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of memory controller
A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss. |
| US09449686B2 |
Resistive memory device, resistive memory system and method of operating the resistive memory device
A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address. |
| US09449684B2 |
Storage control device, storage device, information processing system, and storage control method
Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected. |
| US09449682B2 |
Reading a multi-bit value from a memory cell
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing. |
| US09449681B2 |
Pre-charging a data line
A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal. |
| US09449679B2 |
Memory devices and control methods thereof
A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells. |
| US09449674B2 |
Performing logical operations using sensing circuitry
Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry. |
| US09449672B2 |
DRAM memory interface
It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and—each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line. |
| US09449671B2 |
Techniques for probabilistic dynamic random access memory row repair
Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed. |
| US09449670B2 |
Bit-line sense amplifier, semiconductor memory device and memory system including the same
A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation. |
| US09449660B2 |
Sampling circuit module, memory control circuit unit, and method for sampling data
A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal. |
| US09449659B2 |
Multiple data channel memory module architecture
The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations. |
| US09449658B2 |
Semiconductor apparatus
A semiconductor apparatus includes a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to precharge the first data line to a level of a first voltage or a second voltage. |
| US09449652B2 |
Systems and devices including multi-transistor cells and methods of using, making, and operating the same
A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated. |
| US09449650B2 |
Memory module
A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers. |
| US09449647B2 |
Temporal alignment of video recordings
Methods and apparatus are provided to establish temporal alignment of media clips. In an example embodiment, first and second media clips each contain an audio portion and the method comprises: determining an estimated global offset between the first and second clips; choosing a first test region of the first clip and identifying a corresponding second test region in the second clip based at least in part on the estimated global offset. The first and second test regions are compared to determine a local offset. |
| US09449646B2 |
Methods and systems for media file management
Methods and systems for media file management are provided. A music file including music samples is provided. The music file is analyzed to calculate a gain for each music sample. At least one valley point is detected based on the gains of the respective music samples. A first and a second specific valley points are selected from the detected valley point, and respectively setting the first and second specific valley points as a start and an end of a music segmentation. Media data is generated for media files in the electronic device based on the music segmentation. |
| US09449645B2 |
Video compilation greeting system and method
A video compilation greeting system which allows a number of collaborators to provide video segments for use in a combined video greeting or presentation. The video is submitted by the individual invitee collaborators and is automatically reformatted by the system into the desired format. The original organizer, who may optionally also be a collaborator, has several options for further customizing the final video product, such as adding credits or personalized messages at the end of the main feature, or titles and graphics to the beginning of the video. The final result is a video greeting to a recipient comprising multiple video submissions into a single video output. |
| US09449640B2 |
Media device turntable
An assembly can include a base; and a turntable rotatably coupled to the base where the turntable can include an optical port, a mount that positions an electronic device with respect to the optical port and at least one waveguide operatively coupled to the optical port. |
| US09449639B2 |
Medium transporting unit and medium processing apparatus
A holding mechanism is operable to hold a top medium from a plurality of plate-shaped media accommodated in a stacker in a stacked manner. A transport arm supports the holding mechanism. The transport arm is provided with a separation mechanism operable to separate a second medium positioned just below the top medium which is held by the holding mechanism. |
| US09449638B2 |
Controlling the transport of a tape within a tape transport system
A control device for controlling the transport of a tape within a tape transport system, the tape transport system having a head being operable to read data from and/or write data to the tape, an outboard reel and an inboard reel, wherein the tape is moveable from the outboard reel to the inboard reel in forward direction or from the inboard reel to the outboard reel in reverse direction, wherein the control device is adapted to generate control signals to control the velocity of the outboard reel and the velocity of the inboard reel as a function of a primary velocity of the tape at the head and a secondary velocity of the tape at the inboard reel and/or a secondary velocity of the tape at the outboard reel. |
| US09449634B2 |
Magnetic recording medium fabrication method
A method of fabricating a magnetic recording medium by sequentially forming a magnetic recording layer, a protection layer, and a lubricant layer on a stacked body, includes forming the lubricant by depositing a first lubricant on the stacked body after forming the protection layer, by vapor-phase lubrication deposition, without exposing the stacked body to atmosphere, and depositing a second lubricant on the stacked body after depositing the first lubricant, by vapor-phase lubrication deposition, without exposing the stacked body to atmosphere. The first lubricant has a lower molecular mass and a higher chemical polarity than those of the second lubricant. |
| US09449633B1 |
Smooth structures for heat-assisted magnetic recording media
A recording medium having improved signal-to-noise ratio (SNR) capabilities and head-disk interface characteristics includes an etched smoothened underlayer, over which the recording layer is grown. One mechanism for increasing the SNR is by growing more columnar magnetic grain structures within the recording layer, which is facilitated by a smoother underlayer template. |
| US09449631B2 |
Slider for magnetic recording system
Systems and methods for tuning seed layer hardness in components of magnetic recording systems are described. One such system includes a substrate including a component of a magnetic recording system, a first deposition source configured to deposit a seed layer material on a portion of a top surface of the substrate at a first angle, and a second deposition source configured to deposit a carbon material including sp3 carbon bonds on the portion of the top surface at a second angle not equal to the first angle, where the first deposition source and the second deposition source deposit the seed layer material and the carbon material, respectively, simultaneously. The component can be a slider or a magnetic medium. |
| US09449629B2 |
Resistive temperature sensors for improved asperity, head-media spacing, and/or head-media contact detection
A sensor supported by a head transducer has a temperature coefficient of resistance (TCR) and a sensor resistance. The sensor operates at a temperature above ambient and is responsive to changes in sensor-medium spacing. Conductive contacts connected to the sensor have a contact resistance and a cross-sectional area adjacent to the sensor larger than that of the sensor, such that the contact resistance is small relative to the sensor resistance and negligibly contributes to a signal generated by the sensor. A multiplicity of head transducers each support a TCR sensor and a power source can supply bias power to each sensor of each head to maintain each sensor at a fixed temperature above an ambient temperature in the presence of heat transfer changes impacting the sensors. A TCR sensor of a head transducer can include a track-oriented TCR sensor wire for sensing one or both of asperities of the medium. |
| US09449628B2 |
Quasi-statically oriented, bi-directional tape recording head
In one general embodiment, an apparatus includes a magnetic head. The magnetic head has a first array of data transducers, a second array of data transducers spaced from the first array, and a third array of data transducers positioned between the first and second arrays. The magnetic head is positionable between a first position and a second position, where the longitudinal axis of the third array is positively or negatively angled relative to a line oriented perpendicular to an intended direction of tape travel thereacross when positioned towards the respective positions. Outer data transducers of the third array are about aligned with outer data transducers of the second array when the magnetic head is positioned towards the first position. The outer data transducers of the third array are about aligned with outer data transducers of the first array when the magnetic head is positioned towards the second position. |
| US09449621B1 |
Dual free layer magnetic reader having a rear bias structure having a high aspect ratio
A magnetic read apparatus has an air-bearing surface (ABS) and includes a read sensor and a rear magnetic bias structure. The read sensor includes first and second free layers, a spacer layer and a rear surface opposite to the ABS. The spacer layer is nonmagnetic and between the first and second free layers. The read sensor has a track width in a cross track direction parallel to the ABS. The rear magnetic bias structure magnetically biases the read sensor a stripe height direction perpendicular to the ABS. The read sensor is between the ABS and the rear magnetic bias structure. The rear magnetic bias structure has a width in the cross track direction and a length in the stripe height direction. The length is greater than the width. The width of the rear magnetic bias structure is substantially equal to the track width of the read sensor. |
| US09449612B2 |
Systems and methods for speech processing via a GUI for adjusting attack and release times
Systems and methods described herein modify audio content on an electronic device. Embodiments can be configured to detect a mode of the electronic device to determine whether the device is in a telephone mode; receive a speech signal from a speech source while the device is in the telephone mode; and process the speech signal to improve the perceived quality of the speech at a recipient when the electronic device is in a telephone mode; wherein processing the speech signal to improve the perceived quality of the speech comprises, decreasing the signal level of audio content outside of a determined frequency band relative to the signal level of the audio content within the determined frequency band; and wherein the determined frequency band is a frequency band associated a vocal range of the anticipated speech content. The electronic device further includes a graphical user interface which allows a user to adjust any or all audio parameters including very high frequency attack or release times. |
| US09449608B2 |
Low delay modulated filter bank
The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems. |
| US09449607B2 |
Systems and methods for detecting overflow
A method for detecting overflow on an electronic device is described. The method includes determining a linear predictive coding synthesis filter gain. The method further includes determining whether overflow is detected based on the linear predictive coding synthesis filter gain and a fixed codebook gain. The method further includes determining a scaling factor if overflow is detected. |
| US09449598B1 |
Speech recognition with combined grammar and statistical language models
Features are disclosed for performing speech recognition on utterances using a grammar and a statistical language model, such as an n-gram model. States of the grammar may correspond to states of the statistical language model. Speech recognition may be initiated using the grammar. At a given state of the grammar, speech recognition may continue at a corresponding state of the statistical language model. Speech recognition may continue using the grammar in parallel with the statistical language model, or it may continue using the statistical language model exclusively. Scores associated with the correspondences between states (e.g., backoff arcs) may be determined according to a heuristically or based on test data. |
| US09449588B2 |
Single container-based portable drum kit
A drum kit container is configured to house various compartments sufficient to stow all of the equipment needed by a drummer in setting up a drum kit. One compartment is sized to house a relatively small bass drum, with an acoustic chamber formed behind this compartment and used to improve the sound of a small bass drum so that it sounds more like a larger bass drum as generally used in performance. |
| US09449586B2 |
Keyboard device
A keyboard device includes: key units each including a coupler and white or block keys coupled to the coupler at their rear ends; and a key frame assembled to the key frame and supporting the couplers stacked on each other. The coupler of one of the key units is provided with a hook having an engaging portion. The coupler of each of at least one other key unit has a through hole at a position corresponding to the hook. The key frame has a through hole at a position corresponding to the hook. The couplers of the key units are secured on the key frame using the engaging portion in a state in which the hook extends through the through hole of the coupler of each of the at least one other key unit and the through hole of the key frame. |
| US09449577B2 |
Display device having synchronization unit and driving method thereof
Disclosed is a display device that may include a first data driver and a second data driver, each checking availability of a data transmission with a timing controller upon receiving a power voltage; a synchronization unit that outputs a power management signal when both the first and second data drivers become available for their data transmission with the timing controller; and a power module that supplies a high-potential voltage to the first and second data drivers in response to the power management signal output from the synchronization unit. |
| US09449574B2 |
LCD overdriving using difference between average values of groups of pixels between two frames
In a video voltage comparator circuit, an average of first video voltages applied to pixel electrodes of pixels in the second-half rows in a k-th frame period (k is a natural number) is compared with an average of second video voltages applied to pixel electrodes of pixels in the first-half rows in a (k+1)th frame period for each row. In an overdrive voltage switching circuit, when a difference obtained from the comparison in the video voltage comparator circuit is greater than or equal to a threshold value, the overdrive voltage in the (k+1)th frame period is switched to a first overdrive voltage, and when the difference obtained from the comparison in the video voltage comparator circuit is less than the threshold value, the overdrive voltage in the (k+1)th frame period is switched to a second overdrive voltage lower than the first overdrive voltage. |
| US09449569B2 |
Liquid crystal display device and method for driving liquid crystal display device
A liquid crystal display device capable of consuming less power and a method for driving the liquid crystal display device are provided. The liquid crystal display device includes a pixel portion, a light supply portion sequentially supplying lights of a plurality of hues to the pixel portion, a counter counting the number of frame periods, a signal generator determining timing of inverting the polarity of an image signal every plural consecutive frame periods by using data on the number of frame periods counted by the counter, and a controller inverting the polarity of the image signal in accordance with the timing. A plurality of pixels are provided in the pixel portion. The image signal whose polarity is inverted every plural frame periods is input to the plurality of pixels. |
| US09449568B2 |
Liquid crystal display monitor and source driver and control method thereof
A liquid crystal display (LCD) monitor including an LCD display panel for displaying a frame, a timing controller for generating a polarity control signal and a latch signal, and a driving circuit including a plurality of source drivers, each of the plurality of source drivers including a comparison unit for comparing a common electrode voltage with a first and a second reference voltages to generate a comparison result, an enabling unit for generating an enabling signal according to the comparison result, a source driving signal and a reset signal, a horizontal dot inversion control unit for generating a horizontal dot inversion control signal according to the enabling signal, and a polarity control unit for generating a polarity inversion control signal and the reset signal according to the enabling signal, the polarity control signal and the latch signal. |
| US09449562B2 |
Display apparatus having a micro-electro-mechanical system
A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other. |
| US09449561B1 |
Light sensor obstruction detection
An ambient light sensor may be used to measure ambient light in an environment that surrounds a device. The measured ambient light may be used to adjust display settings employed by the device, and thereby improve a user experience during interaction with the device in the environment. During use of the device that includes an ambient light sensor, the ambient light sensor may become obscured (blocked, covered, etc.) by a user's finger, a cover, dirt, and/or by another object that obstructs the ambient light sensor's ability to detect light from the environment. Various techniques may be used to determine obstruction of the ambient light sensor. In some embodiments, changes in display settings may be compared to measured changes in ambient light to determine whether a light sensor is obstructed. In some embodiments, use of a second light sensor may validate whether a first light sensor is obstructed. |
| US09449560B2 |
Organic light emitting display for sensing degradation of organic light emitting diode
An organic light emitting display includes a display panel including a plurality of pixels, each of the plurality of pixels including an organic light emitting diode (OLED) and a driving thin film transistor (TFT) to control an emission amount of the OLED, the plurality of pixels connected to respective sensing lines; and at least one sensing unit connected to a corresponding one of the pixels through the respective sensing line, the at least one sensing unit configured to sense an amount of carriers accumulated in a parasitic capacitor of the OLED of the corresponding one of the pixels when a driving current flows in the OLED, the at least one sensing unit thereby sensing a degradation of the OLED. |
| US09449559B2 |
Display device and driving apparatus thereof
In a data driving apparatus, a DAC converts digital data output from a holding latch into an analog data voltage. An operational amplifier operates as a buffer which outputs the analog data voltage of the DAC to the signal line during a display period and operates as a comparator which compares the voltage of the signal line with the analog data voltage of the DAC during a sensing period. In addition, a sensing controller controls the holding latch to change the data stored in the holding latch according to a comparison value of the comparator. |
| US09449553B2 |
Organic light emitting display
An organic light emitting display (OLED) is disclosed. The OLED includes a storage capacitor formed in a first region of the substrate, a thin film transistor formed in a second region of the substrate, a first data line capacitor formed in a third region of the substrate, an organic light emitting diode formed on the storage capacitor and the thin film transistor, and a second data line capacitor formed on the data line capacitor. |
| US09449550B2 |
Organic light emitting diode display device
An organic light emitting diode (OLED) display device minimizes a threshold voltage variation of a drive transistor in a pixel circuit, increases an aperture ratio, and minimizes power consumption by applying a same range of data voltages to respective pixels. The OLED display device includes a first capacitor electrically connected between a first node and a power supply line; and a second capacitor electrically connected between the first node and a second node, wherein capacitances of the first and second capacitors are different from each other and adjustable. |
| US09449548B2 |
Organic light emitting display device and method for driving thereof
An organic light emitting display device for displaying 2D and 3D image, the organic light emitting display device including a scan driver for supplying a scan signal to a plurality of scan lines; a data driver for supplying a data signal to a plurality of data lines; a plurality of pixels that located at crossing regions of the scan lines and the data lines for controlling a current flowing from a first power driver to a second power driver via an organic light emitting diode; a data processor for classifying data supplied from outside as 2D or 3D data, and for producing 2D or 3D; and a timing controller for transmitting 2D or 3D data supplied from the data processor to the data driver, wherein the timing controller is configured to set the pixels in a non-emission state during a scan period. |
| US09449542B2 |
Gate driving circuit, array substrate and display device
The present disclosure discloses a gate driving circuit including multi-stage shift registers, and an output side switch element which is controlled by the second clock signal to be turned on or off. The output side switch element is located between an input terminal and an output terminal of each stage shift register. An output terminal of the (N+2)-th stage shift register is coupled to a reset terminal of the N-th stage shift register. |
| US09449541B2 |
Self illuminated shaped and two-sided signage for printed graphics
Self illuminated back and front lit shaped and two-sided signage. The signage includes a turning film having a structured surface for redirecting light and a diffuser providing for diffusion. The shape of the signage from a viewer's perspective provides the content, such as letters, to be conveyed to the viewer. Two-sided signage includes two signs arranged back-to-back, each including a turning film having a structured surface for redirecting light, a diffuser providing for diffusion, and a printed graphic. In the two-sided signage, the turning films receive light from an ambient light source and direct the light via the structured surfaces toward viewers of the two graphics in order to passively illuminate the signage. The two-sided signage can be shaped to provide content via the shape and graphics. |
| US09449539B2 |
Simulated neon sign
A lighted sign has a front side and a back side, and includes a planar substrate and a light source. The light source is substantially coplanar with the substrate. A distressed area reflector is formed on the substrate and redirects light from the light source out of the planar substrate. The lighted sign also includes a cover layer disposed adjacent the planar substrate toward the front side and a linear graphic that is printed on the cover layer. |
| US09449538B2 |
Display system, display process and engagement feature
A display system, a display process, and an engagement feature are disclosed. The display system includes a first display arrangement, a second display arrangement, and a flexible support extending from the first display arrangement to the second display arrangement. The first display arrangement engages the second display arrangement by movement of the flexible support. |
| US09449528B1 |
Guided system for resetting embedded anxious and traumatic reactions
A method facilitates a participant to reduce or eliminate anxiety over-reactions. A program application is used to collect, assess and store responses from inquiry of said participant's history of significant events. The participant is given a set of directions. The participant is presented with a significant temperature change to said participant's body or a portion thereof for a period of time while using said directions and a means for recording data from sensors or from said participant. |
| US09449524B2 |
Dynamic role-based instructional symbiont for software application instructional support
The disclosure provides a computer-based learning system that minimizes the “distance” between applications (for which instructions are provided) and the instructions themselves. That is, the instructional material provided is dynamically integrated with a “state” of one or more applications, which constantly change as a user interacts with the application. Further, the instructional information is visually presented within a common screen, window, or focus region as the application, in a minimally intrusive manner. For example, the instruction window can be an overlay that is designed to “hide from” or to avoid obscuring application content of particular interest to a user. Various techniques can be used to ensure the instructions are provided unobtrusively, including use of transparency settings to make instructions legible, resizing techniques, variable shading, font size/contrast/style adjustments, and the like. |
| US09449523B2 |
Systems and methods for narrating electronic books
A narration session between a plurality of participants can be set up to allow participants to collaboratively narrate an electronic book. Information can be transmitted to each participant so that the views of the participants remain in sync. Visual cues can also be transmitted to notify a participant of text that is to read aloud and audio snippets of read text are collected to form a narration file. Participants without access rights to the electronic book can be granted temporary rights. |
| US09449520B2 |
System and method for verifying viewing of multimedia rendering of investigator meeting prefatory to clinical trial participation
A system and method providing passive verification of participant—typically a physician—exposure to Material equivalent to attendance at an Investigator Meeting prefatory to Clinical Trial is taught. The invention provides for rendering media capture of Investigator Meeting education into computer deliverable sessions, and further into segments, where segments are the product of randomly generated visual requests to which participant need provide response in some prescribed time interval to confirm visual attention to Material. To ensure participant visual exposure to Material, during computer mediated display of Material, visual prompts appear at random points in the display. For any successful participant response, session advances, and in absence of successful response, display of Material resets to last successful response point in Material. In an alternate embodiment, groups of viewers may be tracked corresponding to a group viewing of Material. The system provides real-time tracking of completion of visual exposure to Investigator Meeting Material and enables Clinical Trial sponsor to dynamically update enrolled participant data, and actively encourage physician completion of Investigator Meeting equivalent attendance, so as to expedite Clinical Trial launch. |
| US09449519B2 |
Driving assistance device
A speed zone computation unit that computes a speed zone of a host vehicle; a target speed computation unit that computes a target speed of the host vehicle based on a speed zone; a driving assistance starting point computation unit that computes a driving assistance starting point determined by a state of the host vehicle at the time when a driving assistance is started; and a target speed modification unit that modifies a target speed, when the driving assistance starting point is within the speed zone, are included. The target speed computation unit sets a speed lower than the speed zone in the reference position as the target speed. The target speed modification unit sets a value higher than a value computed by the target speed computation unit as a new target speed, in speed in the reference position. |
| US09449508B2 |
Filtering road traffic condition data obtained from mobile data sources
Techniques are described for assessing road traffic conditions in various ways based on obtained traffic-related data, such as data samples from vehicles and other mobile data sources traveling on the roads, as well as in some situations data from one or more other sources (such as physical sensors near to or embedded in the roads). The assessment of road traffic conditions based on obtained data samples may include various filtering and/or conditioning of the data samples, and various inferences and probabilistic determinations of traffic-related characteristics from the data samples. In some situations, the filtering of the data samples includes identifying data samples that are inaccurate or otherwise unrepresentative of actual traffic condition characteristics, such as data samples that are not of interest based at least in part on roads with which the data samples are associated and/or that otherwise reflect vehicle locations or activities that are not of interest. |
| US09449505B2 |
Traffic congestion prediction method and traffic congestion prediction device
Provided is a traffic congestion prediction method which is able to perform a prediction process using floating information with higher accuracy. The traffic congestion prediction method includes: a step of receiving information by a prediction device; a step of predicting a route of each floating car based on the current position information and destination information received; a step of calculating, for the each floating car, a first passing time group which is a set of respective passing times at a plurality of predetermined spots on the route predicted; a step of calculating the number of existing floating cars per link based on the first passing time group, if any of a plurality of floating cars exists on the link at a predetermined time; and a step of calculating a second passing time group by use of the number of existing floating cars and a predetermined calculation technique. |
| US09449504B2 |
Code sequence control of infrared blaster
A code sequence relayed to an infrared blaster is monitored. If the code sequence approaches a violating sequence, the infrared blaster is controlled to emit infrared light with a corrected sequence that does not express the violating sequence. If the code sequence does not approach the violating sequence, the infrared blaster is controlled to emit infrared light with the code sequence. |
| US09449500B2 |
System and method for optimized appliance control
In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state. |
| US09449498B2 |
Wireless communication network power optimization for control of industrial equipment in harsh environments
In certain embodiments, a system includes a master node device. The master node device includes communication circuitry configured to facilitate communication with a welding power supply unit via a long-range communication link, and to facilitate wireless communication with one or more welding-related devices via a short-range wireless communication network. The master node device also includes control circuitry configured to manage power consumption of on-board batteries of the master node device and the one or more welding-related devices. |
| US09449496B2 |
System for convergence of alarms from medical equipment
A device for processing alarms includes a processor and a computer-readable medium storing instructions which, when executed by the processor, cause the processor to perform various operations. The operations include receiving a first alarm from a first diagnostic device and determining a location associated with a first user. When the location associated with the first user is determined to be proximate to a device, the operations further include presenting a first verbal alert indicating that the first diagnostic device is presenting the first alarm. When the location associated with the first user is determined to be not proximate to the device, the operations further include sending a first notification message to a first mobile device of the first user indicating that the first diagnostic device is presenting the first alarm. |
| US09449495B1 |
Crash detection and severity classification system implementing emergency assistance
A crash detection system is disclosed that utilizes a mobile computing device to detect a vehicular accident via one or more sensors integrated into the mobile computing device. The system monitors the sensor metrics measured by one or more sensors and generates an event sensor profile that may include the plurality of sensor metrics and additional status data, such as an indication of whether the mobile computing device was located within a vehicle when the event occurred. By comparing the plurality of sensor metrics to other crash sensor metrics, a determination may be made whether the event requires emergency assistance, which may be confirmed by determining whether the data included in the event sensor profile meets one or more exception conditions. If the event requires emergency assistance and an exception condition is not met, the mobile computing device may place a call to the appropriate emergency response personnel. |
| US09449493B2 |
Burglar alarm control
Apparatus is described for use with a burglar alarm that includes a detector configured to detect activity and to generate an activity-detection signal in response thereto. A sensor monitors a resting surface and generates a signal in response thereto. A control unit identifies a correspondence between (a) the activity-detection signal, and (b) the signal that is generated by the sensor. The control unit inhibits the burglar alarm from being triggered, in response to the correspondence. Other applications are also described. |
| US09449490B2 |
Automated security system for structures
Disclosed are various embodiments for providing security to a structure. A network of security devices may be accessed and/or controlled by one or more monitoring devices, wherein each of the one or more monitoring devices are configured to monitor one or more signals emitted by one or more security devices. In response to a signal received from at least one of the security devices indicating a breach of the structure, a compartmentalization of the structure may be initiated, wherein the compartmentalization comprises initiating a lockdown of the structure utilizing at least one of the one or more security devices. |
| US09449489B2 |
Apparatus and method for providing a task reminder based on user location
Providing a reminder of a task to be performed at a task location includes receiving location information identifying a location of a user via a mobile communication device associated with the user, receiving information that identifies a task, receiving information that identifies a task location, and providing a reminder for the task based on a current location of the user and on a comparison of an estimated probability of the user traveling in a trajectory leading toward the task location and an estimated probability of the user traveling in a trajectory leading away from the task location. |
| US09449488B2 |
Object recognition and notification
Methods, systems, and apparatus are provided for determining the presence or absence of an object within a vehicle based on sensor signals and selectively providing notification to a user of the same. |
| US09449487B1 |
Pet communication and tracking system
The pet communication and tracking system is a collar adapted for use with pets. The pet communication and tracking system comprises a location module for determining the location of the pet, and a communication module that allows a pet owner to determine the location of their pet as well. The pet communication and tracking system will also notify users when their pet leaves a predetermined geographic location. The pet communication and tracking system comprises a collar, a location module, a communication module, a logic module, and a power source. |
| US09449479B2 |
Security system
Known security systems issue an audible and/or visible alarm to alert all those local to a secured article that the article has been compromised. However, for various reasons, passers-by do not respond to such an alarm/alert. According to the present invention, if an intruder interferes with a secured article, a sensor may detect an event associated with an article being interfered with and/or compromised. This detection will trigger (via a processor) an alarm condition, and a transceiver will send an alarm signal to a monitoring device over a communication network; however, no indication of the alarm condition is detectable outside the housing by means other than via the alarm signal. In this way, an intruder compromising an article is not alerted to detection of the event by the sensor. Therefore, authorities may be summoned to apprehend the intruder without the intruder being provided with the opportunity to escape. |
| US09449473B2 |
Method for awarding the value of winning tickets dispensed by a vending machine
The value of winning tickets dispensed by a vending machine to patrons who purchased the winning tickets are awarded using selection buttons on the vending machine that provide a first option to immediately redeem the value of a winning ticket at the vending machine, and a second option to defer immediate redemption of the value of a winning ticket. The tickets are preprinted with game content and are associated with a deal of tickets that includes at least some predetermined winning tickets. |
| US09449471B2 |
Gaming device having a re-triggering symbol bonus scheme
A gaming device having a bonus scheme wherein a combination of bonus symbols trigger a bonus game and any one of the bonus symbols in the bonus game provides a player with an award. The award may be an extension of the bonus game by providing the player with additional spins or games. Also, the award may modify the combination and type of bonus symbols needed to enter the bonus game. Furthermore, the award may modify the award values in the bonus game. Therefore, a combination of bonus symbols triggers the bonus game and also triggers the gaming device to provide bonus awards in the bonus game. The re-triggering symbol award bonus scheme changes the probability of winning for the player and therefore creates a higher level of excitement and enjoyment of the game. |
| US09449466B2 |
Networked hybrid gaming system
A networked gaming system is provided, including an entertainment software controller connected by a network to a game world controller, the entertainment software controller constructed to: present a first presentation of a skill-based game; transmit a player action of the skill-based game; receive a modified game status update; present a second presentation based on the modified update; the game world controller connected by the network to a game server, the game world controller constructed to: receive the player action; generate a wager; transmit the wager; receive a wager result; transmit, to a game server, the player action; receive a game state update based on the player action; generate the modified game state update; and transmit, to the entertainment software controller, the modified game state update; and the real world controller connected to the game world controller, and constructed to: receive the wager; and provide a wager result. |
| US09449464B2 |
Gaming system, gaming device, and method providing a game having an obstacle board with falling symbols
A gaming system providing a falling symbol obstacle board game. The gaming system displays a symbol starting position, a plurality of symbol ending positions, and a plurality of obstacles. The gaming system selects one of a plurality of symbols, displays the symbol moving from the symbol starting position into one of the symbol ending positions along one of a plurality of symbol paths through the obstacles, and displays the symbol at the symbol ending position at the end of the symbol path. The gaming system repeats selecting symbols, displaying the symbol moving from the symbol starting position to a symbol ending positions along a symbol path, and displaying the symbol at the symbol ending position at the end of the symbol path until a termination condition is satisfied, after which the gaming system determines whether any winning combinations of the symbols are displayed at the symbol ending positions. |
| US09449459B2 |
Method of gaming, a gaming system and a game controller
A method includes monitoring game outcomes generated for one or more players of a plurality of linked gaming machines. Instances of one or more special symbols occurring in the generated game outcome are identified. A counter for each of the one or more special symbols based on instances of one or more special symbols occurring in the game outcome, is incremented. In response to a trigger condition, one or more special symbols are allocated to one or more of the linked gaming machines for modifying a game outcome generated for a player of the linked gaming machine, to provide a new game outcome for each of the one or more players of linked gaming machines to which the special symbols are allocated. The number of special symbols allocated is based on a value of the accumulating counter. |
| US09449455B2 |
Wagering game with override award when threshold is exceeded
A gaming method of conducting a wagering game includes receiving, via one or more input devices, an input indicative of a wager, displaying, via one or more display devices, a plurality of symbols to indicate a randomly selected outcome of a wagering game in a display area, and determining, via at least one of one or more processors, one or more award amounts for the randomly selected outcome. The one or more award amounts are based on the wager and the symbols of the randomly selected outcome. The method further includes determining an aggregate award amount based on the one or more award amounts, comparing the aggregate award amount to a predetermined threshold amount, awarding the aggregate award amount if the aggregate award amount is less than the predetermined threshold amount, and awarding an override-award amount if the aggregate award amount is greater than the predetermined threshold amount. |
| US09449443B2 |
Logging access attempts to an area
Logging events associated with accessing an area includes recording an event associated with accessing the area to provide an event recording and authenticating at least the event recording to provide an authenticated recording. Recording an event may include recording a time of the event. Recording an event may include recording a type of event. The event may be an attempt to access the area. Recording an event may include recording credentials/proofs used in connection with the attempt to access the area. Recording an event may include recording a result of the attempt. Recording an event may include recording the existence of data other than the credentials/proofs indicating that access should be denied. Recording an event may include recording additional data related to the area. Authenticating the recording may include digitally signing the recording. Authenticating at least the event recording may include authenticating the event recording and authenticating other event recordings to provide a single authenticated recording. |
| US09449440B2 |
Wireless crash survivable memory unit
A recorder for a vehicle comprises a crash survivable memory unit, which includes a first antenna assembly including a first resonant element configured for near field data communications and to receive near field power transmissions, and a crash protected memory assembly that operatively communicates with the first antenna assembly. One or more protective layers surround the first antenna assembly and the memory assembly. A second antenna assembly is external to the crash survivable memory unit. The second antenna assembly includes a second resonant element, which is configured for near field data communications with the first resonant element and for near field power transmissions to the first resonant element. The second antenna assembly is adapted to receive information related to vehicle operations and to configure the information for wireless transmission to the first antenna assembly for recording in the memory assembly. |
| US09449439B2 |
Battery state display system
A battery state display system includes: a plurality of electric vehicles, each of the plurality of electric vehicles being configured to be driven by a battery containing battery fluid; and a display terminal. The display terminal includes: a communication unit configured to communicate with the plurality of electric vehicles; a display configured to display an image including a state of the battery of each of a plurality of electric vehicles on the display of the display terminal; and a processor configured to: control the display terminal to display on the display a battery state indication for each of the electric vehicles, the battery state indication including: a charge state indication representing a charge state of the battery; and a fluid amount indication relating to an amount of the battery fluid of the battery. |
| US09449435B2 |
Accelerometer and voltage based key-on and key-off detection
A device may receive a first type of measurement associated with a vehicle and receive a second type of measurement associated with a power source connected to the vehicle. The second type of measurement may be different than the first type of measurement. The device may determine a key-on or a key-off status of the vehicle based on the first type of measurement and the second type of measurement without communicating with a vehicle diagnostic system associated with the vehicle. The key-off status may correspond to an engine of the vehicle being powered off and the key-on status may correspond to the engine of the vehicle being powered on. The device may initiate communications with the vehicle diagnostic system based on determining the key-on status. |
| US09449434B2 |
Electrically actuatable module of a motor vehicle and method for identifying an electrically actuatable module of a motor vehicle
The invention relates to an electrically actuatable assembly of a motor vehicle having at least one component comprising a non-volatile memory. The component has base functionality characteristic for the component and required for the operation of the assembly. The memory comprises a memory region not utilized for realizing the base functionality of the component, in said memory region is stored a characteristic value that identifies the assembly with a predetermined probability. Furthermore, the characteristic value can be read out from the memory region of the component. Finally, the invention describes a method for identifying such an electrically actuatable assembly. |
| US09449432B2 |
System and method for identifying faces in unconstrained media
Methods and systems for facial recognition are provided. The method includes determining a three-dimensional (3D) model of a face of an individual based on different images of the individual. The method also includes extracting two-dimensional (2D) patches from the 3D model. Further, the method includes generating a plurality of signatures of the face using different combinations of the 2D patches, wherein the plurality of signatures correspond to respective views of the 3D model from different angles. |
| US09449428B2 |
Method for generating an environment map
An environment map representative of lighting information of a real environment. As to enhance the impression of immersion into a virtual environment, the method comprises the steps of acquisition at real time of an image representative of a partial lighting information of said real environment from a digital optical acquisition device, said image comprising a plurality of pixels; and estimation of said environment map by extrapolation of at least a part of said pixels of said image, the extrapolation comprising the application of a first value corresponding to the mean value of the pixels of said image to at least a first part of the environment map. |
| US09449421B2 |
Method and apparatus for rendering image data
Provided is a rendering method and apparatuses for rendering image data. The rendering method includes generating a primitive list by performing geometry processing on a current tile to be rendered; determining whether the current tile is identical to a previous tile from among tiles included in a previously rendered frame; and in response to the previous tile being identical to the current tile, generating an image of the current tile by re-using an image of the previous tile. |
| US09449417B1 |
Artistic simulation of curly hair
Techniques are disclosed for stably simulating stylized curly hair that address artistic needs and performance demands, both found in the production of feature films. To satisfy the artistic requirement of maintaining a curl's helical shape during motion, a hair model is developed based upon an extensible elastic rod. A method is provided for stably computing a frame along a hair curve for stable simulation of curly hair. The hair model introduces a new type of spring for controlling the bending and twisting of a curl and another for maintaining the helical shape during extension. The disclosed techniques address performance concerns often associated with handling hair-hair contact interactions by efficiently parallelizing the simulation. A novel algorithm is presented for pruning both hair-hair contact pairs and hair particles. The method can be used on a full length feature film and has proven to be robust and stable over a wide range of animated motion and on a variety of hair styles, from straight to wavy to curly. |
| US09449415B2 |
Method and system for presenting educational material
Method and system for presenting a lesson plan having a plurality of keyframes is provided. The method includes initializing a fixed variable for a first keyframe; detecting an input from a user at an interactive display device; correlating the input with a gesture from a gesture set and one or more of database domains from among a plurality of database domains; displaying an image at the interactive display device when all mutable variables for the first keyframe content are determined based on the input; manipulating the image using a gesture associated with the displayed image and any associated database domains; and transitioning to a next keyframe using animation. |
| US09449409B2 |
Graphical indicators in analog clock format
Some aspects relate to display of a plurality of graphical indicators on a display, each of the plurality of graphical indicators associated with a respective time interval, wherein, for each of the plurality of graphical indicators, a length of the displayed graphical indicator represents a value of a metric associated with the respective time interval of the graphical indicator, wherein first ends of each of the plurality of graphical indicators substantially trace an arc of a circle, and wherein, for each graphical indicator, a position of the first end of the graphical indicator on the arc of the circle indicates the respective time interval associated with the graphical indicator. |
| US09449408B2 |
Visualizing high-cardinality data
A method of visualizing high-cardinally data is provided. A graph is presented on a display. The graph includes a first axis, a second axis, and a plurality of value markers. The first axis includes a minimum value and a maximum value and the second axis includes a plurality of category values. A selection indicator identifying selection of a first value marker of the plurality of value markers is received. The first value marker indicates a value for a category value of the plurality of category values. A second plurality of category values is determined based on the category value. The graph and a second graph are presented on the display. The second graph includes a third axis, a fourth axis, and a second plurality of value markers. The third axis includes a second minimum value and a second maximum value. |
| US09449405B2 |
Systems and methods to display dependencies within a graph of grouped elements
According to some embodiments, for a set of elements a plurality of dependencies between source elements and target elements may be determined. It may also be determined that a first subset of elements are associated with a first group and that a second subset of the elements are associated with a second group. A first grouping shape, representing the first group, may be displayed on a user interface along with a second grouping shape representing the second group. Moreover, within the second grouping shape indications of the second subset of elements may be displayed. A dependency line may be displayed between the first grouping shape and the second grouping shape based on a dependency between a particular element in first subset and a particular element in the second subset, and the dependency line may intersect the second grouping shape at an intersection point. A dependency line may also be displayed from the intersection point to the indication representing the particular element in the second subset. |
| US09449401B2 |
System, method and article of manufacture for decompressing digital camera sensor data
A system, method, and article of manufacture for decompressing a bit stream of compressed data representing a plurality of image blocks. A plurality of bits of compressed input data relating to AC codes are retrieved from the bit stream and a first decoding operation executed to generate first output data. If sufficient space for the first output data exists, the first output data is outputted. Otherwise, a second decoding operation generates second output data. The first decoding operation includes performing a look-up in a look-up table based on the input data. A pointer is retrieved from a data segment that corresponds to the input data and a routine corresponding to the retrieved pointer is executed. The payload of the data segment is processed in the executed routine to generate the first output data. |
| US09449393B2 |
Apparatus and method for plane detection
A plane detection apparatus for detecting at least one plane model from an input depth image. The plane detection apparatus may include an image divider to divide the input depth image into a plurality of patches, a plane model estimator to calculate one or more plane models with respect to the plurality of patches including a first patch and a second patch, and a patch merger to iteratively merge patches having a plane model a similarity greater than or equal to a first threshold by comparing plane models of the plurality of patches. When a patch having the plane model similarity greater than or equal to the first threshold is absent, the plane detection apparatus may determine at least one final plane model with respect to the input depth image using previously merged patches. |
| US09449384B2 |
Method for registering deformable images using random Markov fields
A method registers a source image with a target image, wherein the images are deformable, by first measuring dissimilarity between the source image and the target image. The dissimilarity minimized using a discrete energy function. At multiple scales, multi-scale Markov random field registration is applied to the source and target images to determine a deformation vector field. Then, the target image is warped according to the deformation field vector to obtain a warped target mage registered to the source image. |
| US09449383B2 |
Determination of a physically-varying anatomical structure
The present invention relates to a data processing method for providing variation data which describe a physically-varying anatomical structure, in particular an indiscernible anatomical structure, in particular a non-enhancing tumor, comprising the steps of: providing second image data which describe a second image of a region of an anatomical body, wherein the region includes a second anatomical part which includes the physically-varying anatomical structure; providing first image data which represent a first image of the same region, wherein said same region includes a first anatomical part which does not include the physically-varying anatomical structure or which includes the physically-varying anatomical structure in a different physical state than in the second anatomical part; providing position change data which describe positional changes of corresponding image elements between the first image and the second image, on the basis of the first and second image data; and providing the variation data on the basis of the position change data. |
| US09449373B2 |
Modifying appearance of lines on a display system
A computer-implemented method of modifying image data is presented. The method entails detecting a triggering pattern based on colors and saturation values of a group of pixels, wherein at least one of the pixels includes a plurality of subpixels, and wherein the triggering pattern includes at least a portion of one of a diagonal line and a vertical line. The method changes the image data for a specific subpixel in the group of pixels, wherein the specific subpixel is located in or adjacent to the diagonal line or the vertical line. Alternatively, the method entails detecting a border between saturated-color subpixels and non-saturated-color subpixels, and adding luminance to white subpixels at the border. A display system configured to execute the above methods and a computer-readable medium storing instructions for executing the above methods are also presented. |
| US09449370B2 |
Detecting exposure quality in images
Systems, methods and computer readable media for exposure quality detection are described. In some implementations, a method can include computing an overall image exposure score for an image. The method can also include determining one or more face regions in the image. The method can further include computing a face region exposure score for each face region. The method can also include combining the overall image exposure score and each face region exposure score to generate an exposure quality score for the image. |
| US09449367B2 |
Parallel processor for providing high resolution frames from low resolution frames
Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame. |
| US09449366B2 |
Bayer-consistent raw scaling
A system and method for scaling an image includes receiving raw image data comprising input pixel values which correspond to pixels of an image sensor; and filtering pixels according to a Bayer-consistent ruleset. The system and method may also include outputting scaled image data as output pixel values, which correspond to subgroups of the input pixel values. The Bayer-consistent ruleset includes a set of filter weights and a series of scaling rules. The Bayer-consistent ruleset results in a scaled image having a high degree of Bayer-consistency. |
| US09449365B2 |
Personalized scaling of graphical indicators
Some aspects relate to reception from a user, via a sensor, first data indicative of activity of the user, determination of one or more values of a metric based on the first data, determination of a display scale based on the one or more values, reception from the user, via the sensor, second data indicative of activity of the user over a time interval, determination of a second value of the metric based on the second data, generation of a first graphical indicator representing the second value based on the display scale and the second value, and display of the first graphical indicator on a display. |
| US09449358B2 |
Arrangements for increasing detection confidence
In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed. |
| US09449357B1 |
Geometric enumerated watermark embedding for spot colors
The present invention relate generally to digital watermarking spot colors. A process color approximation can be used for a spot color, and chrominance watermarking can be performed to insert a watermark. These techniques are particularly suitable for product packaging, color brochures, etc. |
| US09449350B2 |
Prompting service
Computer-readable media, systems, and methods are provided for prompting a customer of a service to submit digital content to the service in order to generate an online compilation. Input from the customer may be received in response to communications from the service. Temporal preference information may then be extracted from the input by determining time periods at which the customer most commonly provides the input in response to the communications. Based on the time periods at which the customer most commonly provides input, a prompting scheme may be derived, where the prompting scheme governs scheduling an automatic distribution of subsequent communications to the customer at the time periods at which the customer most commonly provides the input. The subsequent communications may then be distributed to the customer in accordance with the prompting scheme. |
| US09449347B2 |
Method and apparatus for processing receipts
Systems and methods of processing expense receipts are provided. Images of expense receipts are received from a user device. The images are processed to obtain receipt information. A list of user expenses is generated based on the receipt information. |
| US09449346B1 |
System and method for programmatically accessing financial data
Systems and methods for programmatic access of external financial service systems. An application proxy instance is created that simulates an application of an external financial service system. A normalized account request is received for financial data of the external financial service system for a specified account. The normalized account request is provided by an external financial application system by using a financial data API of the financial platform system. Responsive to the normalized account request, communication is negotiated with the external financial service system by using the application proxy instance to access the requested financial data from the external financial service system by using a proprietary Application Programming Interface (API) of the external financial service system. The financial data is provided to the external financial application system as a response to the normalized account request. |
| US09449344B2 |
Dynamically retraining a prediction model based on real time transaction data
Various embodiments of systems and methods to dynamically retrain prediction models based on real time transaction data are described herein. In one aspect, real time application data and status data associated with an entity are obtained. The obtained application data is inputted to a prediction model to produce an assessment of a risk. The obtained status data with the assessed risk are compared. When the obtained payment status data does not match the determined risk, the prediction model is retrained. |
| US09449342B2 |
System and method for visualization of items in an environment using augmented reality
In various example embodiments, a system and method for visualization of an item in an environment using augmented reality is provided. In example embodiments, environment image data containing an image of an environment is received from a client device. A selection of an item that is under consideration for purchase and placement into an indicated location of the environment is received. An item image of the selected item is scaled to a scale that is based on dimensions determined from the environment image data for the environment. The scaled item image is augmented into the image of the environment at the indicated location to generate an augmented reality image. |
| US09449339B2 |
Recommendations based on usage and resource consumption data
An electronic device may generate use related information and resource consumption related information corresponding to each of used applications used in the electronic device. The use related information and the resource consumption related information may then be transmitted to a remote applications manager, which may analyze the information to generate, based on the analysis, specially tailored application recommendations. The application recommendations may list one or more other applications, newly available or offered, which may be recommended for download to and/or use in the electronic device. The analysis of the use and the resource consumption information may comprise ranking the used applications, such as based on use patterns and/or resource consumption, and/or classification of the used applications, such as based on application type. Generating the application recommendations may comprise correlating used applications, based on classification and/or ranking, with similar applications that may be recommended. |
| US09449334B1 |
Systems and methods for providing targeted advertising and content delivery to mobile devices
Systems and methods are described for providing targeted content delivery, including advertising, to mobile devices. A content organization and distribution system may be configured to receive content from a plurality of publishers and provide targeted content to a plurality of users having mobile devices, where the mobile devices are connected to the content organization and distribution system through a plurality of carriers. The provided content may be based on one or more user customization criteria. |
| US09449330B2 |
Self-serve API for game mechanics tool
Game mechanics may be incorporated into a web site, mobile site, and/or app using an automated access, self-serve platform. A user interface may be generated based on input provided by or on behalf of a publisher of a site and/or app. The user interface may be configured to be incorporated with the site and/or app. An economy governing game mechanics associated with the user interface may be defined. The user interface may be provided for integration with the site and/or app. Integration of the user interface with the site and/or app may provide the game mechanics to the site and/or app. In some implementations, generating the user interface may include generating, at a gamification server, a widget configured to provide the user interface, the site and/or app being provided by a site server, the gamification server being separate and distinct from the site server. |
| US09449329B2 |
Enterprise architecture system and method
A method for costing a web service operable for querying one or more data sources, the method including calculating the cost of operating the web service, measuring web service usage data using one or more service metrics, wherein the one or more service metrics include at least one derived service metric, choosing at least one service metric from the one or more service metrics, wherein one or more of the at least one chosen service metrics is a derived service metric, calculating the cost of the web service based on the at least one chosen service metric, and charging for usage of the web service based upon the calculated cost of the web service. |
| US09449328B2 |
System for encoding customer data
A system for transforming customer data includes a network interface and a processor. The network interface communicates a request for customer data associated with a particular geographical area. It also receives a customer profile code associated with the customer data, wherein the customer profile code comprises a first code segment and a second code segment. It further receives first and second rules associated with the customer profile code. The processor transforms the first and second code segments into customer data using the rules. It further analyzes the particular geographical area using the customer data. |
| US09449326B2 |
Web site accelerator
A web site accelerator system includes a web asset migrator storing web assets in a data repository according to categories specified in a predetermined schema. The system also includes a web asset configurer matching rules stored in the data repository with attributes associated with an online user. The rules each specify a condition and a web asset stored in the data repository to provide to the online visitor if the condition is satisfied. The system also includes a rules optimizer modifying the rules based on captured online behavior. |
| US09449324B2 |
Reducing TV licensing costs
A TV with various licensable components including, e.g., an ATSC demodulator requests a license for a component upon detection of a physical condition implicating use of the component, such as plugging a cable into a particular port, or upon receipt of a user-input command requiring use of the component, such as a request to autoscan channels. |
| US09449318B2 |
Systems and methods for providing payment hotspots
Systems and methods are provided for facilitating payments between users of the system such as person-to-person payments using a payment hotspot. A payment hotspot or payspot may be generated by a first user device of a first user to facilitate a transfer of funds between the first user and the second user. The payspot may be a virtual payment portal that allows secure payment between the users without either of the users having to provide identifying information to the other user. The payspot may be accessed by the second user based on the proximity of a second user device of the second user to the first user device or the first user may provide an identification code of the payspot to the second user. The second user may access the payspot by communicating with a payment server with the second user device, through the first user device. |
| US09449305B2 |
Method of organizing a database according to an event for a web-based conference collaboration tool with dynamic content and roles
A conference collaboration system has a server connected to a network and configured to generate a page view requested by a client device over the network and provide dynamic content associated with the requested page view for display on the device; and a database configured to store the dynamic content, update the dynamic content in response to commands from the server, and provide the dynamic content to the server in response to requests from the server, wherein the dynamic content is associated with a plurality of services, each shown in a page view, and the dynamic content and the services are associated with a conference. The server can determine an authorization level of a user interacting with the client device and provide a page view and dynamic content in response to the authorization level, and the dynamic content is updated or created in response to or for actions during the conference. |
| US09449302B1 |
Generating personalized websites and newsletters
A system and method for generating a membership profile for a personalized website is disclosed. An online services provider uses the interest engine to generate a questionnaire and polls. A new user provides responses that include answers to the questionnaire and polls. A profile engine generates a membership profile based on the answers. A newsletter engine generates personalized newsletter information including a number of users that provided each answer. In response to an online services provider selecting the recipients for the newsletter, the newsletter engine either generates the newsletter and transmits it to the recipients or the newsletter engine transmits the contact information to the online services provider. |
| US09449298B2 |
Managing complex dependencies in a file-based team environment
Techniques managing complex dependencies in a file-based team environment are provided. A software module is represented as an object. The object is defined via a file. The file includes relationships, and some of the relationships define dependencies to other objects. In some cases, attributes for the object are also included in the file and are defined via references to still other objects. The relationships and the attributes are carried with the object via the file. |
| US09449296B2 |
Management of pharmacy kits using multiple acceptance criteria for pharmacy kit segments
A pharmacy kit is managed by defining multiple rules for determining whether a segment of a pharmacy kit is satisfactorily stocked, selecting at least one rule among the multiple rules according to a kit stocking contingency, an prompting a user to stock the segment of the pharmacy kit according to the selected at least one rule. |
| US09449292B1 |
System, method, and computer program for automatic high level testing project planning
A system, method, and computer program product are provided for automatic high level testing project planning. In use, information associated with at least one testing project to be planned is received, the information including a plurality of project attributes associated with the at least one testing project. Additionally, one or more test planning rules are identified based on the received information, the one or more rules including rules generated utilizing data associated with a plurality of previously performed testing projects. Further, one or more test planning conclusions applicable for the at least one testing project are determined based on the one or more test planning rules and the received information. Moreover, the one or more test planning conclusions are output utilizing at least one user interface. |
| US09449290B1 |
Product and service purchase-cycle tracking
Systems and methods for using wireless communication devices to track the effects of advertising are described herein. In some embodiments, a method includes representing the identity of an advertising impression, that is, a specific advertisement, with an impression code. According to exemplary embodiments, the advertising impression is directed to at least one commodity, such as one or more products and services. The method may also further include receiving the impression into a computer-readable memory of a wireless communication device. The method further includes detecting the wireless communication device, and then providing the impression code during the purchase of the commodity. The method continues with obtaining the identity of the advertising impression from the impression code. The method additionally includes creating a transaction record, wherein transaction record includes the advertising impression identity and an identity of the commodity, and storing the transaction record in a database. |
| US09449286B2 |
Machine learning apparatus and method with time-point information indicating the time point in a unit period
A machine learning apparatus includes an analytical information storage unit that stores therein two or more pieces of analytical information each associating input/output information used for machine learning with time-point information indicating a time point of the input/output information, an analysis-object-set specifying unit that specifies an analysis object set containing a unit-period input-output set being a set of pieces of the input/output information corresponding to pieces of the time-point information indicating the time point in a unit period and an amount of the pieces of the input/output information of the set being dependent on a period between the time point of the unit periods and a specific time point, and a machine learning unit that performs machine learning by using the pieces of the input/output information contained in the analysis object set. |
| US09449276B2 |
Graphical model-driven system for knowledge management tools
According to one embodiment of the disclosure, a graphical model-driven system includes a graphical knowledge pattern system coupled to a modeler interface. The graphical knowledge pattern system has a graphical knowledge pattern library for the storage of a plurality of graphical knowledge patterns that are configured to classify information according to one or more information related criteria. The modeler interface is operable to receive a request for information from the user interface and retrieve information from one or more knowledge based systems according to one or more information related criteria of a particular graphical knowledge pattern. |
| US09449272B2 |
Doppler effect processing in a neural network model
A method of frequency discrimination associated with the Doppler effect is presented. The method includes mapping a first signal to a first plurality of frequency bins and a second signal to a second plurality of frequency bins. The first signal and the second signal corresponding to different times. The method also includes firing a first plurality of neurons based on contents of the first plurality of frequency bins and firing a second plurality of neurons based on contents of the second plurality of frequency bins. |
| US09449270B2 |
Implementing structural plasticity in an artificial nervous system
Methods and apparatus are provided for implementing structural plasticity in an artificial nervous system. One example method for altering a structure of an artificial nervous system generally includes determining a synapse in the artificial nervous system for reassignment, determining a first artificial neuron and a second artificial neuron for connecting via the synapse, and reassigning the synapse to connect the first artificial neuron with the second artificial neuron. Another example method for operating an artificial nervous system, generally includes determining a synapse in the artificial nervous system for assignment; determining a first artificial neuron and a second artificial neuron for connecting via the synapse, wherein at least one of the synapse or the first and second artificial neurons are determined randomly or pseudo-randomly; and assigning the synapse to connect the first artificial neuron with the second artificial neuron. |
| US09449266B2 |
Method and apparatus for tracking transported items using RFID tags
A method and apparatus for tracking transported items using RFID tags are provided. A tote for transporting RFID tagged items includes a body capable of enclosing one or more RFID tagged items. RF reflective and/or absorbent material is positioned to inhibit RF signals from reaching the enclosed RFID tagged items from outside the body. A portion of a wall of the tote or a sleeve for insertion into the tote can be free of reflective and/or absorbent material to allow RF signals to be sent into, and exit, the tote. The RF reflective and/or absorbent material can be provided with or without texture. |
| US09449262B2 |
Image processing apparatus and method for controlling image processing apparatus
An image processing apparatus includes an image processing unit configured to perform image processing, a storage unit configured to be capable of storing an application program installed in the image processing apparatus, a first determination unit configured to determine whether the application program had ever been installed in the image processing apparatus, and a control unit configured to selectively control the image processing unit to be operable and control the image processing unit not to operate according to the determination by the first determination unit if an error has occurred in the storage unit. |
| US09449260B2 |
Constructing and using support vector machines
Methods and systems are described for building and using a support vector machine for classifying a new sample. Training samples of one class or another class are used to build the machine by mapping the angle space to a set of angle vectors and, for each angle vector, finding candidate hyperplanes that are orthogonal to a vector at the angle vector and radiating from an origin point to the hyperplane. An optimal pair of candidate hyperplanes at one of the angle vectors is selected on the basis of the distance between the pair and the number of samples between them. The selection may be based on hard margin or soft margin approaches. A matrix-based implementation is presented. New training samples may be added, removed, or reclassified without requiring recalculation of the entire support vector machine. |
| US09449257B2 |
Dynamically reconstructable multistage parallel single instruction multiple data array processing system
The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations. In particularly, such a system can be dynamically reconfigured as an SOM neural network at a low cost of area, and the neural network supports high level of image processing such as a high speed online neural network training and image feature recognition, and completely overcomes a defect that a high level of image processing can't be done by pixel-level parallel processing array in the existing programmable vision chips and parallel vision processors, and facilitates an intelligent and portable real time on-chip vision image system with a complete function at low device cost and low power consumption. |
| US09449254B1 |
Adaptive environment targeting
Systems and methods provide adapted content to a visitor to a physical environment. An example method receives an image of a visitor to an environment. A visitor portion of the image is distinct from an environment portion of the image. The method detects one or more shapes in the visitor portion of the image using an automatic shape detection technique and defines an approximate boundary of the one or more shapes using a mask. The one or more shapes can be shapes of the visitor's clothing items. The method then calculates an attribute for an area of the image within the mask and identifies electronic content based on the attribute for the area of the image within the mask. The attribute can be a color attribute for the area such as a median color or a dominant color. The method provides the identified electronic content for display in the environment. |
| US09449244B2 |
Methods for in-scene atmospheric compensation by endmember matching
Methods are provided for automatically performing atmospheric compensation of a multi or hyper spectral image. One method comprises transforming at least two endmembers extracted from an image into at-ground reflectance. The transformation may be approximate and/or only in certain spectral bands in order to reduce processing time. A matching component is then located in a spectral library for each of the at least two extracted endmembers. Gain and offset values are then calculated using the at least two matched extracted endmember and spectral library component pairs. At least part of the image is then compensated using the calculated gain and offset values. Another method uses at least one endmember extracted from the image and a black level. Methods for atmospheric compensation using water vapor content of pixels are also provided. In addition, methods for shadow correction of hyper and multi spectral images are provided. |
| US09449234B2 |
Displaying relative motion of objects in an image
In a method for visualizing motion of an object in an image, at least two images, including a first image and a second image, wherein each of the at least two images includes an object are received. One or more processors determine a first distance value for the object in the first image and a second distance value for the object in the second image, wherein each distance value is based on a distance between the object and an image capturing device. One or more processors compare the first distance value to the second distance value to determine a difference between the first distance value and the second distance value. One or more processors generate an indication based on the determined difference between the first distance value and the second distance value. |
| US09449232B2 |
Systems and methods for generating bookman video fingerprints
Systems and methods for replacing original media bookmarks of at least a portion of a digital media file with replacement bookmarks is described. A media fingerprint engine detects the location of the original fingerprints associated with the portion of the digital media file and a region analysis algorithm characterizes regions of media file spanning the location of the original bookmarks by data class types. The replacement bookmarks are associated with the data class types and are overwritten or otherwise are substituted for the original bookmarks. The replacement bookmarks then are subjected to a fingerprint matching algorithm that incorporates media timeline and media related metadata. |
| US09449228B1 |
Inferring locations from an image
Systems and methods are disclosed for determining the location where an image was captured. In general, a device such as a smartphone may capture one or more images from a location, such as images of buildings, street signs and the like, and a central system may compare the submitted images to images in an image library to identify matches. The location of the match may then be provided back to the smartphone. |
| US09449225B2 |
Low power hardware algorithms and architectures for spike sorting and detection
A neuronal recording system featuring a large number of electrodes and a portable wireless front-end integrated circuit for signal processing for low-power spike detection and alignment. The system is configured as a Neuroprocessor and introduces hardware architectures for automatic spike detection and alignment algorithms. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communications to a host computer. Some of the algorithms are based on principal component analysis (PCA). Others employ a novel Integral Transform. The algorithms execute autonomously, but require off-line training and setting of computational parameters. Pre-recorded neuronal signals evaluate the accuracy of the proposed algorithms and architectures: The recorded data are processed by a standard PCA spike sorting software algorithm, as well as by the several hardware algorithms, and the outcomes are compared. |
| US09449219B2 |
System and method for activity monitoring
A system for activity monitoring includes a tracking component, an activity identification component, a procedural component, and a notification component. The tracking component tracks an individual and one or more objects in a work area using a three-dimensional tracking system. The activity identification component identifies an activity of the individual and any of the one or more objects that are affected by the activity. The procedural component determines whether the activity violates one or more procedural rules pertaining to one or more of the individual, the work area, and the one or more objects. The notification component provides a notification of a violation. |
| US09449218B2 |
Large venue surveillance and reaction systems and methods using dynamically analyzed emotional input
Certain example embodiments relate to large venue surveillance and reaction systems and/or methods that take into account both subjective emotional attributes of persons having relations to the large venues, and objective measures such as, for example, actual or expected wait times, current staffing levels, numbers of customers to be serviced, etc. Pre-programmed scenarios are run in real-time as events stream in over one or more electronic interfaces, with each scenario being implemented as a logic sequence that takes into account at least an aspect of a representation of an inferred emotional state. The scenarios are run to (a) determine whether an incident might be occurring and/or might have occurred, and/or (b) dynamically determine a responsive action to be taken. A complex event processing engine may be used in this regard. The analysis may be used in certain example embodiments to help improve customer satisfaction at the large venue. |
| US09449213B2 |
Anti-shock relief print scanning
One or more techniques, devices and/or systems are disclosed for mitigating a perceived electrical sensation for a relief print scanning device. A current determination component can be used to identify an electrical current configuration that provides a mitigated electrical sensation to the user, for use with an electroluminescent-based relief print scanning device. The electrical current configuration can be identified using one or more image characteristics of a relief print image, which is captured by the devices using the current configuration. A current adjusting component, can be operably coupled with the current determination component, and may be used to adjust the current configuration, where the adjustment can be based on current adjustment data that is provided by the current determination component, based on the image characteristics. |
| US09449207B2 |
RFID reader device and antenna device
An RFID reader device and an antenna device have a first antenna implemented as a near-field antenna, wherein the first antenna has a first dual strip line. The first antenna has a first strip line and a second strip line. The first strip line and the second strip line may be implemented in the form of open loops. The first strip line may be implemented inside the open loop of the second strip line. |
| US09449203B2 |
Card reader with power efficient architecture that includes a power supply and a wake-up circuit
These and other objects of the present invention are achieved in a card reader with a read head positioned in a housing. The read head is configured to be coupled to a mobile device and has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. A power supply is coupled to wake-up electronics and a microcontroller. An output jack is adapted to be inserted in a port of the mobile device and deliver an output jack signal to the mobile device. |
| US09449202B2 |
Localizing tagged assets in a configurable monitoring device system
In a tag communication system, a method includes determining range information representative of a distance between two tags, and estimating parameter information representative of backscatter signals of a marker tag and an asset tag. A tag is localized according to the range information and the parameter information to provide a localized tag. The range information is determined according to a beacon signal. The system includes a plurality of beacon signals and the method further includes determining the range information according to at least two of the beacon signals. A logical operation is performed on the range information of the two beacon signals. A further beacon signal has a plurality of signal ranges and the range information is determined according to the signal ranges. A logical operation is performed on the range information of the signal ranges. |
| US09449199B2 |
Feature enablement within a printer
In one embodiment, an apparatus that removably connects to a first printer is validated, the validating including comparing first data stored within the apparatus to second data stored within the first printer. A first feature is enabled within the first printer utilizing third data stored within the apparatus. The apparatus is restricted such that the apparatus is no longer operable to enable the first feature within a printer other than the first printer. |
| US09449197B2 |
Pooling entropy to facilitate mobile device-based true random number generation
A mobile device operating system pools any available entropy. The resulting entropy pool is stored in device memory. When storing entropy in memory, preferably memory addresses are randomly allocated to prevent an attacker from capturing entropy that might have already been used to create a random number. The stored entropy pool provides a readily-available entropy source for any entropy required by the operating system or device applications. Then, when a cryptographic application requests a true random number, the operating system checks to determine whether the pool has available entropy and, if so, a portion of the entropy is provided to enable generation (e.g., by a TRNG) of a true random number that, in turn, may then be used for some cryptographic operation. After providing the entropy, the operating system clears the address locations that were used to provide it so that another entity cannot re-use the entropy. |
| US09449196B1 |
Security data path verification
A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design. |
| US09449192B1 |
Magnetic stripe reader tamper protection
A technique for tamper protection of incoming data signal to an electronic device is disclosed. An intentional interference signal is generated and modulated onto the incoming data signal as one composite input signal, to prevent unauthorized acquisition of valid data from the incoming data signal. The magnitude of the interference signal is adjusted to correspond to the magnitude of the incoming data signal, thereby preventing an attacker from properly differentiating the two different signals and/or decoding the valid data from the composite input signal. Once the composite input signal is safely received within the device, the interference signal can be filtered out in either analog mode or digital mode. |
| US09449191B2 |
Device, system and method for securing and comparing genomic data
The present disclosure presents methods, systems, and devices for encrypting and comparing genomic data. The comparison of genomic data allows the owner of the data to ensure security of the data even when the party conducting the comparison is beyond the control of the owner of the data. The encryption of the genomic data enables the transmission, storage, and use of the genomic data in a secure media. |
| US09449188B2 |
Integration user for analytical access to read only data stores generated from transactional systems
The technology disclosed preserves the tenant specificity and user specificity of the tenant data by associating user IDs to complementary special IDs referred to as the integration user(s). In particular, it combines the traceability of user actions, the integration of security models and the flexibility of a service ID into one integration user(s). |
| US09449183B2 |
Secure file drawer and safe
An online file storage system comprising individual secure file drawers and safes is disclosed for securely storing and sharing confidential files. The system comprises a web-based user interface, tools for setting up server-side encryption method and client-side encryption method, tools for synchronizing encryption between different computers, tools for uploading files, tools for tracking files, tools for granting the right of access to files to the owners of other safes, and tools for generating authenticity certificates for proving the upload time and the substance of the files in a future time. |
| US09449177B1 |
General protocol for proactively secure computation
Described is a system for proactively secure multi-party computation (MPC). Secret shares representing data are constructed to perform computations between a plurality of parties modeled as probabilistic polynomial-time interactive turing machines. A number of rounds of communication where the plurality of parties jointly compute on the secret shares is specified. Additionally, a threshold of a number of the plurality of parties that can be corrupted by an adversary is specified. The secret shares are periodicially refreshed and reshared among the plurality of parties before and after computations in each of the rounds of communication. The data the secret shares represent is proactively secured. |
| US09449172B2 |
Memory arrangement and method for detecting an attack on a memory arrangement
According to various embodiments, a memory arrangement is described having a first bit line, a first precharge device for precharging the first bit line to a precharged state, a second bit line, a second precharge device for precharging the second bit line to a precharged state, a memory control apparatus that is set up to interrupt the precharging of the first bit line by the first precharge device for memory access and to interrupt the precharging of the second bit line by the second precharge device for the memory access, a memory access apparatus that is set up to follow the interruption of the precharging of the first bit line and the interruption of the precharging of the second bit line by performing the memory access and reading the state of the second bit line, and a detector that is set up to take the state of the second bit line as a basis for detecting an attack on the memory arrangement. |
| US09449171B2 |
Methods, systems, and computer readable mediums for providing supply chain validation
Methods, systems, and computer readable mediums for providing supply chain validation are disclosed. According to one exemplary embodiment, a method for validating a computing system comprises receiving, from a source entity and via an out of band delivery, validation information for validating the computing system, wherein the validation information is derived from one or more components of the computing system. The method also includes determining, using the validation information and reference information associated with the computing system, whether a configuration of the computing system has been modified and, in response to determining that the configuration of the computing system has been modified, generating information about a system modification. |
| US09449169B2 |
Block storage virtualization on commodity secure digital cards
One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage. |
| US09449167B2 |
Method and system for securely accessing different services based on single sign on
An embodiment for securely accessing services of a service provider based on single sign on. The user device is authenticated by an authentication server if the computed hash of the first random number r is same as the received hash of the first random number r sent by a user device. Thereafter, the second random number y, the user id and an element Q are encrypted using a service provider password and send to the service provider. The user device computes a first discrete exponential function Z using the element Q and the second random number y and sends along with the user id to the service provider. The service provider computes a second discrete exponential function Z′ using the element Q and the second random number y received from the authentication server and provides the user device access to the services if Z is equal to Z′. |
| US09449165B2 |
System and method for wireless proximity-based access to a computing device
Disclosed herein is a system and method for wireless proximity-based access to a computing system, which in accordance with certain aspects of an embodiment of the invention includes a small, portable, person-carried or personal-item-carried (e.g., by attachment to a user's key's, purse, knapsack, etc.) wireless transmitter that serves as a “key,” and a wireless receiver configured for attachment to the computing system that serves as a “lock.” The lock may comprise, for example, a USB device that both wirelessly communicates with the key to detect its physical proximity, and communicates with the computer access software that is native on the computing system (e.g., standard WINDOWS username and password authentication processes) to either allow or disallow such computer access software from allowing access to the computing system based upon the physical proximity of the key to the lock. |
| US09449163B2 |
Electronic device and method for logging in application program of the electronic device
A method for logging in to an application program of an electronic device presets a plurality groups of account information of the application program, and presets fingerprints corresponding the plurality of groups of account information in a storage device. When the application program is executed and a user interface of the application program is displayed, the method receives fingerprint data input. When the received fingerprint data matches one of the fingerprints, the method further confirms a group of account information corresponding to the matched fingerprint, and logs in to the application program using the confirmed account information. |
| US09449162B2 |
Portable storage device using fingerprint recognition, and control method thereof
Disclosed is a portable storage device including a fingerprint sensor, a fingerprint data processing unit, a data repository, a data processing unit and the like. The fingerprint data processing unit outputs a fingerprint matching signal when fingerprint information received from the fingerprint sensor matches authentication fingerprint information of the fingerprint data repository. If the fingerprint matching signal is received from the fingerprint data processing unit, the data processing unit retrieves a data requested by the user terminal from the data repository, converts the retrieved data into a read-only data and transmits the read-only data to the user terminal. |
| US09449160B1 |
Methods and systems of adding a user account to a device
A method of adding a user account to an unassociated device may include detecting, by an associated device that is associated with a user account, an audio signal broadcast by an unassociated device that is not associated with the user account, where the audio signal includes a token. The method may include sending the token to a computing device associated with a service provider of the user account, receiving, by the associated device, a command, determining that the received command is an authorization command, and in response to determining that the received command is an authorization command, sending one or more authorization instructions to the computing device. The one or more authorization instructions may instruct the computing device to send one or more credentials associated with the user. |
| US09449157B2 |
Mechanisms to secure data on hard reset of device
Mechanisms to secure data on a hard reset of a device are provided. A hard reset request is detected on a handheld device. Before the hard reset is permitted to process an additional security compliance check is made. Assuming, the additional security compliance check is successful and before the hard reset is processed, the data of the handheld device is backed up to a configurable location. |
| US09449156B2 |
Using trusted devices to augment location-based account protection
An authentication process receives information identifying a user, a device used by the user and a location in which the device is being used. That authentication process determines whether the location is among a set of familiar locations stored about the user for a service being accessed. If the location is not among the set of familiar locations, then the user is not authenticated. A desirable user experience can be obtained by using information about any existing relationship, such as a synchronization relationship, between the device and the service established at a prior familiar location. Instead of challenging a user whose device is in an unfamiliar location, the authentication process determines whether the device has a relationship established with the service. If the device has a relationship established with the service, then the set of familiar locations is updated to include the location in which the device is being used. |
| US09449155B2 |
Environmental condition identifying type license consumption system and method, and function providing server and program
A license consumption system includes an information device on which application software operates based on a given license; and a function providing server which grants the license to the information device. The function providing server stores the license and an operating condition for granting the license, when attempting to start the application software, the information device transmits to the function providing server a licensing request of the application software and an operating environment of the information device, and the function providing server compares an operating condition of the application software corresponding to the requested license with the operating environment of the information device, and grants the license to the information device when the operating environment satisfies the operating condition. |
| US09449154B2 |
Method and apparatus for granting rights for content on a network service
Techniques for granting rights for content on a social network to multiple users include determining first data. It is also determined to associate a first user identifier and at least a second user identifier with the first data. It is further determined to grant a right for the first data to a first user identified by the first user identifier and at least a second user identified by the second user identifier. |
| US09449150B2 |
Combination treatment selection methods and systems
Methods, computer program products, and systems are described that include accepting at least one attribute of at least one individual, querying at least one database at least partly based on the at least one attribute, selecting from the at least one database at least one prescription medication and at least one artificial sensory experience to address the at least one attribute of at least one individual, and/or presenting an indication of the at least one prescription medication and the at least one artificial sensory experience at least partly based on the selecting from the at least one database at least one prescription medication and at least one artificial sensory experience to address the at least one attribute of at least one individual. |
| US09449147B2 |
Method and system for patient-specific modeling of blood flow
Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing at least a portion of the patient's heart based on the patient-specific data. The at least one computer system may be further configured to create a physics-based model relating to a blood flow characteristic of the patient's heart and determine a fractional flow reserve within the patient's heart based on the three-dimensional model and the physics-based model. |
| US09449143B2 |
Ancestral-specific reference genomes and uses thereof
Ancestry has a significant impact on the major and minor alleles found in each nucleotide position within the genome. Due to mechanisms of inheritance, ancestral-specific information contained within the genome is conserved within members of an ancestry. For this reason, individuals within a specific ancestry are more likely to share alleles in their genomes with other members of the same ancestry. Functionally, the combination of alleles at all positions within a group of individuals defines that group as having a common ancestry. Moreover, the aggregation of differences between alleles at all positions distinguishes one ancestry from another. The genomic similarities and differences between ancestries provides a mechanism to generate reference genomes that are specific for each ancestry. Reference genomes that are specific to an ancestry can be used to increase the accuracy of whole genome sequencing, DNA-based diagnostics and therapeutic marker discovery and in a variety of real-world DNA-based applications. |
| US09449142B2 |
System and method for modeling supervisory control of heterogeneous unmanned vehicles through discrete event simulation
A system and method for modeling supervisory control of heterogeneous unmanned vehicles through discrete event simulation is provided. Generally, the system contains a memory and a processor configured by the memory to perform the steps of: simulating events in the system; simulating arrival processes for the events in the system; simulating how long a human operator takes to respond to the simulated events in the system, where the time that the human operator takes to respond to a simulated event is referred to as a service time; and prioritizing the events to be handled by the human operator, wherein the system models human operator involvement in the unmanned vehicle system. |
| US09449141B2 |
Systems and methods for generating orthotic device models from user-based data capture
A method for generating an orthotic device is disclosed. The method includes receiving data from a client device of a patient, the data comprising patient information and image data representative of a body part of the patient. The method further includes generating, based on the image data, three-dimensional model data representative of the body part, and generating parametric CAD model data of the orthotic device based on the three-dimensional model data and the patient information. The parametric CAD model data is transmitted to a three-dimensional printer, wherein the three-dimensional printer is to generate the orthotic device based on the parametric CAD model data. |