| Document | Document Title |
|---|---|
| US09294111B2 |
Remote media IMS sessions
A system and method is provided for remote session control of IP Multimedia Subsystem (IMS) sessions. A remote media flow may be established as part of an origination process wherein the controller UE requests that the media flow is established on a remote media UE as part of the origination request. A remote media flow may also be established as part of a termination process wherein the controller UE identified in the termination request identifies a remote media UE on which a remote media is to be established. Embodiments also allow for the session control to be transferred from a first device to a second device, while maintaining one or more media flows on the first device. |
| US09294107B2 |
Phase locked loop circuit, phase locked loop module, and phase locked loop method
Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply. |
| US09294104B2 |
Phase-locked loop circuit with improved performance
A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number. |
| US09294102B2 |
Method for adjusting an excitation frequency of an oscillating circuit of a corona ignition device
A method for setting adjusting frequency of an electric oscillating circuit of a corona ignition device. The circuit is excited with a starting value (f1) of the excitation frequency and a reference value (IR) of a frequency-dependent variable is measured. The excitation frequency is incrementally changed. After every increment a value (I) of the frequency-dependent variable is measured and it is determined whether the measured value (I) deviates significantly from the reference value (IR). Depending upon the measured value (I) relative to the reference value, the value (f) of the excitation frequency is either set as the new starting value (f1) or stored as a boundary value. Further incremental changes to the excitation frequency are made in one of two directions and further comparisons of the values I and IR are performed. Ultimately, the excitation frequency can be set to a mean value between first and second boundary values. |
| US09294100B2 |
Frequency tuning system and method for finding a global optimum
A generator and method for tuning the generator are disclosed. The method includes setting the frequency of power applied by the generator to a current best frequency and sensing a characteristic of the power applied by the generator. A current best error based upon the characteristic of the power is determined, and the frequency of the power at the current best frequency is maintained for a main-time-period. The frequency of the power is then changed to a probe frequency and maintained at the probe frequency for a probe-time-period, which is less than the main-time-period. The current best frequency is set to the probe frequency if the error at the probe frequency is less than the error at the current best frequency. |
| US09294099B2 |
Hybrid synchronous/asynchronous counter
A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters. |
| US09294091B1 |
Method and apparatus for providing a differential output driver with a cross-coupled cell
An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges. |
| US09294086B2 |
Stage circuit and scan driver using the same
A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node. |
| US09294078B1 |
Voltage-driver circuit with dynamic slew rate control
A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal. |
| US09294077B2 |
Method and circuit for injecting a precise amount of charge onto a circuit node
A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node. |
| US09294075B2 |
Semiconductor device
To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node. |
| US09294074B2 |
Physiological signal denoising
Physiological signals are denoised. In accordance with an example embodiment, a denoised physiological signal is generated from an input signal including a desired physiological signal and noise. The input signal is decomposed from a first domain into subcomponents in a second domain of higher dimension than the first domain. Target subcomponents of the input signal that are associated with the desired physiological signal are identified, based upon the spatial distribution of the subcomponents. A denoised physiological signal is constructed in the first domain from at least one of the identified target subcomponents. |
| US09294073B2 |
CMOS RF switch device and method for biasing the same
According to certain aspects, a method includes determining whether to amplify a radio frequency (RF) signal by a first gain achievable by a first circuit or a second gain achievable by a second circuit, amplification of the first and second circuits respectively configured to be turned on or off by first and second switches, the first switch in the on state and the second switch in the off state resulting in the RF signal being amplified by the first gain, and the first switch in the off state and the second switch in the on state resulting in the RF signal being amplified by the second gain; and applying or inducing application of a first bias voltage or a second bias voltage to an isolated well of the first switch upon determination that the RF signal is to be amplified by the first gain or the second gain, respectively. |
| US09294070B2 |
Duplexer with balun
A duplexer is proposed with a substrate which has at least one patterned metallization plane and on which, at least to some extent, a transmission path (TX) and a reception path (RX) are arranged, both of which are connected to an antenna connection (ANT). The duplexer comprises a transmission filter (TXF) which is arranged in the transmission path (TX) and which has a first acoustic wave filter (BAW1) with one or more resonators. Furthermore, the duplexer (DPL) comprises a reception filter (RXF) which is arranged in the reception path (RX) on the antenna side and which has a second acoustic wave filter (BAW2) with one or more resonators and also a single-ended output. In addition, the duplexer comprises, in the reception path (RX), a balun (BL) which is connected downstream of the reception filter (RXF) and the output of which delivers a balanced signal and which is in the form of an LC circuit, wherein at least one inductance and/or at least one capacitance of the balun (BL) are implemented in the patterned metallization plane of the substrate. |
| US09294065B2 |
Reactance filter comprising suppression in the stop band and duplexer component
A reactance filter comprising suppression in the stop band comprises an input connection for applying an input signal, an output connection for outputting an output signal, at least series resonator, which is connected in a signal path between the input connection and the output connection, a parallel resonator, which is connected between the signal path and a connection in order to apply a reference potential, and an inductor, which is connected in series to the parallel resonator. A capacitor is connected by means of one connection between the at least one parallel resonator and the inductor and by means of the additional connection to the output connection. By connecting the reactance filter as a transmission filter in a duplexer component, the isolation in the receiving band of the duplexer component can be improved. |
| US09294064B2 |
Bandpass filter implementation on a single layer using spiral capacitors
A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines. |
| US09294063B1 |
Digital input circuit and method for high voltage sensors
A digital input circuit includes a series connection of a current limiter and a switch having a switch control input coupled between a signal input and ground, and a logic level shifter coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output. A digital input method includes coupling an input signal to ground with a current limiter by closing an electronic switch, providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage and opening the electronic switch after the output signal is latched. |
| US09294061B2 |
Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver. |
| US09294056B2 |
Scalable periphery tunable matching power amplifier
A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. |
| US09294055B2 |
Circuit and method for biasing a gallium arsenide (GaAs) power amplifier
A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage. |
| US09294052B2 |
Personal computer to output audio in a non-operative state
According to one embodiment, an electronic apparatus includes a terminal, an amplifier, a speaker, a power supply circuit and a first controller. The terminal configured to input an audio signal from an external device. The amplifier configured to amplify the audio signal. The speaker configured to output sound corresponding to the audio signal which is amplified by the amplifier. The power supply circuit configured to supply power to the amplifier. The first controller configured to control the power supply circuit to continue the supply of the power, when the electronic apparatus is in a non-operative state. |
| US09294049B2 |
Fast-settling capacitive-coupled amplifiers
Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations. |
| US09294046B2 |
RF power amplifier with PM feedback linearization
Circuitry, which includes a package interface, an RF amplification circuit, and a closed-loop phase linearization circuit, is disclosed. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal to generate the amplified RF signal, such that an intermediate RF signal is generated during amplification of the RF signal. The closed-loop phase linearization circuit endogenously establishes a target phase of the amplified RF signal using the RF signal. Further, the closed-loop phase linearization circuit applies a phase-shift to the intermediate RF signal based on a difference between the target phase and a measured phase, which is representative of a phase of the amplified RF signal, wherein the phase-shift reduces phase distortion in the amplified RF signal. |
| US09294043B2 |
Apparatus and methods for calibrating envelope trackers
Apparatus and methods for envelope tracking calibration are provided. In one embodiment, a power amplifier system includes a power amplifier, an envelope tracker that generates the power amplifier's supply voltage, a power detector, and a calibration module. The envelope tracker includes an envelope shaping table generated at a desired gain compression and a scaling module that scales an amplitude of an envelope signal. The power detector measures the power amplifier's output power, and the calibration module provides calibration data to the scaling module to change the scaling of the envelope signal's amplitude. The calibration module sets the calibration data to a first value corresponding to a supply voltage level associated with substantially no gain compression, and reduces the supply voltage level by changing the calibration data until the power detector indicates that the gain compression of the power amplifier is about equal to the desired gain compression. |
| US09294038B2 |
Power amplifier transistor characteristic stabilization during bias switching
Communications equipment including communications equipment for wireless communications may benefit from power amplifier transistors having stabilized characteristics. For example, certain power amplifier transistors may benefit from having their characteristics stabilized during bias switching. An apparatus can include a power amplifier device. The apparatus can also include a voltage or current input to the power amplifier device. An input voltage or current to the voltage or current input can be configured to be controlled according to scheduled transmission in a slot. The apparatus can also include a gate bias insertion circuit provided at the bias input. The gate bias insertion circuit can be configured to provide a reduced input voltage or current as a power amplifier bias. The reduced input voltage or current can be configured to correspond to a threshold of a transistor of the power amplifier when transmission is not scheduled in a slot. |
| US09294034B2 |
Measurement device for texture size, manufacturing system for solar cell, and manufacturing method for solar cell
A manufacturing method for a solar cell, wherein after a texture is formed on a principal surface of a substrate, infrared light in a predetermined wave number range is applied to a portion, on which the texture is formed, of the principal surface, a wave number at a specified transmission detection rate of the infrared light transmitted through the substrate and detected is acquired, the Tx size of the substrate is calculated on the basis of the acquired wave number using a previously obtained relationship between the wave number at the specified transmission detection rate and the Tx size, and when the calculated Tx size is within a reference value range, a collecting electrode is formed on the principal surface. |
| US09294030B2 |
Method of PWM regulation of a continuous current electric motor
A method of PWM regulating a motor through a half-bridge drive stage includes sampling the motor current to obtain sampled values during driving intervals or during current decay intervals, and comparing a last sampled value with a current threshold. The motor is coupled in a slow decay electrical path for the duration of a current decay interval if the last sampled value does not exceed the current threshold. Otherwise the motor is coupled in a fast decay electrical path for a portion of the duration of the current decay interval, and is coupled in the slow decay electrical path for a remaining part of the duration of the same current decay interval. |
| US09294026B2 |
Method of operating a power generation system
A method of operating a power generation system includes operating a power generation system to generate an electric power output. At least a portion of the electric power output is dissipated in a flow battery by charging the flow battery using the portion of the electric power output and self-discharging the flow battery. |
| US09294023B2 |
Method or system for minimizing the impact of back EMF sampling for motor resistance profiling
A method of determining when to utilize a back EMF sampling method for motor resistance profiling in at least one DC motor, the method including the steps of analyzing a parameter prior to initializing the back EMF sampling method, and upon a determination that the analyzed parameter is within a defined range, initializing the back EMF sampling method. |
| US09294021B2 |
Control device, driving device, and image forming apparatus
A control device includes a motor driving unit that supplies electric power to a motor according to a magnetic-pole-phase signal output from the motor; and a rotational-position detecting unit that converts the magnetic-pole-phase signal into a rotational-position detection signal and outputs the rotational-position detection signal. The rotational-position detection signal indicates a rotation amount and a rotation direction of an output shaft of the motor and has a higher resolution than the magnetic-pole-phase signal. |
| US09294011B2 |
Method and apparatus for sensing underwater signals
Methods and apparatuses are disclosed that assist in sensing underwater signals in connection with geophysical surveys. One embodiment relates to a transducer including a cantilever coupled to a base. The cantilever may include a beam and a first coupling surface angularly oriented from the beam, and the base may include a second coupling surface angularly oriented from the beam and substantially parallel to the first coupling surface of the cantilever. The transducer may further include a sensing material coupled between the first coupling surface of the cantilever and the second coupling surface of the base. |
| US09294007B2 |
Gate driving circuit and inverter having the same
There is provided an inverter including: an inverter unit including at least one inverter arm having a plurality of switches, and switching the input power according to control to output an alternating current power; at least one driving unit including at least one high voltage gate driving unit having a plurality high voltage gate drivers connected to one another in series between an input terminal of an instruction signal instructing a switching control of an inverter unit and an output terminal of a control signal controlling switching of the inverter unit to control switching driving of a high side switch and including at least one low voltage gate driver to control switching driving of a low side switch; and at least one bootstrap unit charging/discharging and dividing a voltage generated at the time of switching the plurality of switches according to switching control of the driving unit. |
| US09294005B2 |
Method and apparatus for detecting AFE filter capacitor degradation
Methods and systems are disclosed for detecting capacitor degradation in an input filter of an active front end power conversion system in which voltage and current sensing is performed to determine sequence component impedance asymmetry to detect filter capacitor degradation according to the value of an off-axis admittance matrix component for Delta or Y-connected filter capacitor banks without sensitivity to voltage unbalance, and with the capability to identify particular degraded capacitor locations based on individual impedance values. |
| US09294003B2 |
Transformer-less unified power flow controller
A power control device includes a first terminal, a second terminal connected to a transmission line, a first cascade multilevel inverter (CMI) and a second CMI. The first CMI is connected to the second terminal. The second CMI connected in series between the first terminal and the second terminal. |
| US09293999B1 |
Automatic enhanced self-driven synchronous rectification for power converters
Systems and methods for providing a self-driven synchronous rectification circuit for an active-clamp forward converter which includes automatically enhancing synchronous MOSFETs and maximizing input voltage range. The gate signals for the synchronous MOSFETs are derived from a unipolar magnetic coupling signal instead of a bipolarized magnetic coupling signal. The unipolar signal is retained for fully enhanced driving of the MOSFETs at low line voltage and the unipolar signal is automatically converted to a bipolar signal at high line amplitude due to line variance to maximize input voltage range by utilizing non-polarized characteristics of the MOSFET gate-to-source voltage (Vgs). The circuit permits efficient scaling for higher output voltages such as 12 volts DC or 15 volts DC, without requiring extra windings on the transformer of the forward converter. |
| US09293998B2 |
Buck-flyback converter
A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side. |
| US09293996B2 |
Method and apparatus for integrated cable drop compensation of a power converter
An integrated circuit controller includes a switching control circuit coupled to output a drive signal to control switching of a switch to regulate an output power of a power converter to be coupled to a distribution network. An oscillator is coupled to output a clock signal coupled to be received by the switching control circuit. The switching control circuit is coupled to output the drive signal in response to the clock signal. A cable drop compensator is coupled to output a compensated reference voltage signal coupled to be received by the switching control circuit in response to a switching signal from the switching control circuit. The switching signal is representative of the drive signal. The cable drop compensator is coupled to adjust the compensated reference voltage signal proportionately to a load current to compensate for a distribution voltage across the distribution network. |
| US09293995B2 |
Method and apparatus for power driving
Aspects of the disclosure provide a power circuit to provide electric energy with control and protection for driving a load, such as a light emitting diode (LED) array, and the like. The power circuit includes a converter, a voltage feedback module, a current feedback module and a controller. The converter is configured to receive electric energy from an energy source and to deliver the electric energy for driving the load. The voltage feedback module is configured to generate a first feedback signal based on a voltage of the delivered electric energy. The current feedback module is configured to generate a second feedback signal based on a current of the delivered electric energy. The controller is configured to receive the first feedback signal and the second feedback signal, and to control the converter to receive and deliver the electric energy based on the first feedback signal and the second feedback signal. |
| US09293988B2 |
Current mode PWM boost converter with frequency dithering
A current mode PWM converter configured to maintain a duty ratio of a driving signal for driving a boost circuit boosting an input voltage to an output voltage when a frequency of a clock signal for generating the driving signal is varied. |
| US09293985B2 |
Method of reducing input current distortion in a rectifier
A method is disclosed for reducing input current harmonic distortion in a Vienna-type active rectifier that includes the steps of sensing voltage values from upper and lower halves of a DC bus associated with the rectifier, determining an average of the sensed voltage values, calculating upper and lower scale factors by dividing the sensed voltage values with the averaged sensed voltage value, rescaling a reference signal from a controller using the upper and lower calculated scale factors, and forward feeding the rescaled reference signal from the controller to a pulse width modulator to obtain a gate driver signal for power semiconductor switches of the rectifier. |
| US09293982B2 |
Switching power supply
In some aspects of the invention, a switching power supply can include a control circuit that conducts feedback control of a pulse width of a driving signal for switching the switching element according to an output voltage and settle the output voltage to a specified voltage level; a frequency reducing circuit that is disposed in the control circuit and reduces a frequency of the driving signal for switching the switching element upon detection of an overload state and limits an output current; and an initial state setting circuit that sets the control circuit to an overload detecting state for a predetermined period of time in a startup period of the control circuit. The initial state setting circuit can pull down a control voltage for a soft start signal for soft starting to the ground potential to inhibit generation of the driving signal and pulls up a feedback voltage signal. |
| US09293976B2 |
Stepping motor and system thereof
A stepping motor includes a housing, a stator assembly, a rotor, and a sensor portion. The stator assembly is disposed inside the housing. The rotor is rotatably disposed inside the stator assembly and includes a rotation shaft, and opposite ends of the rotation shaft are supported by the housing. The sensor portion is disposed inside the housing and detects a magnetic field of the rotor. |
| US09293975B2 |
Actuator, optical scanner, and image forming apparatus
An actuator includes: a movable portion that can oscillate around an oscillation axis; a connection portion that extends from the movable portion and is torsionally deformed in accordance with oscillation of the movable portion; and a support portion that supports the connection portion. The movable portion forms a cross shape in a plan view from a thickness direction of the movable portion. |
| US09293972B2 |
Apparatus for forming insulation for electrical components
Embodiments of an apparatus for forming insulation for an electrical component are provided herein. In one embodiment an apparatus for forming an insulation for an electrical component may include an actuator to pull an electrical component in a substantially linear direction, wherein the actuator is configured to move the electrical component in at least one direction relative to the substantially linear direction; a material source configured to provide a material to one or more surfaces of the electrical component as the electrical component is moved proximate the material source, wherein the material comprises at least a portion of an insulation; and a plurality of movable dies having inner surfaces disposed such that the material conforms to the one or more surfaces of the electrical component as the electrical component is moved through the plurality of movable dies. |
| US09293967B2 |
Device for guiding air in a suction system for a rotary electrical machine
The invention relates to a guidance device (10) of a suction system, said suction system being designed to suck up the dust generated by a brush (1) rubbing against a rotary element (2) in a rotary electrical machine, the guidance device (10) being designed in such a way as to concentrate a stream of air (F) generated by the suction system, near the end of the brush that is in contact with the rotary element (2). The guidance device defines at least one suction chamber (12) shaped so that it opens towards the rotary element, said at least one chamber having walls extending in a longitudinal direction so that said assembly is shaped so as to surround part of a brush near said end. The invention also relates to a suction system comprising such a guidance device. |
| US09293965B2 |
Apparatus, system, and method for cooling an electric motor
An apparatus for providing a coolant to a stator and a rotor of an electric motor in a vehicle having a coolant pump is provided. The apparatus includes a base defining a plurality of first openings through at least one of which the coolant is flowable to the stator. The apparatus also includes at least one wall extending from the base to define a cavity configured to receive the coolant from the coolant pump. The apparatus further includes at least one first raised member within the cavity that extends from the base. The at least one first raised member defines at least one second opening substantially aligned with one of the first openings to form a first passageway through which the coolant is flowable to the rotor. The apparatus may be located above the electric motor such that the coolant is flowable by gravity to the stator and/or the rotor. |
| US09293959B2 |
Apparatus to support superconducting windings in a rotor of an electomotive machine
An apparatus (structure) is provided to support a superconductor winding (61) of an electromotive machine. One or more elongated loops (74) and appropriate support structure (120) may be arranged to provide radial and tangential support to the superconducting winding (61). The elongated loops may be made of a material substantially resistant to heat flow. An axially-extending base assembly (100) may be arranged to anchor loops (74) with respect to the rotor core at a proximate end (76) of the elongated loops. A cradle (80) may be configured to define a recess (82) to receive the superconductor winding and to support the elongated loops at a distal end (78) of the loops. |
| US09293954B2 |
Rotor of motor and fan driving motor including rotor
Provided are a rotor of a motor capable of attaining a high-speed rotation by appropriately dispersing a stress exerted on a flux barrier portion while reducing a leakage of magnetic flux, and a fan driving motor including the rotor. A second inner wall surface is greater than a first inner wall surface in length in a cross-section perpendicular to a rotational axis (C). A side wall surface has a flux barrier wall surface extending from each of both ends of the second inner wall surface in the cross-section perpendicular to the rotational axis (C), the flux barrier wall surface extending outward relative to the second inner wall surface in an extending direction of the second inner wall surface and more distant from an outer edge of a rotor as it goes from the second inner wall surface toward the first inner wall surface in the cross-section perpendicular to the rotational axis (C). |
| US09293946B2 |
Systems and methods for uninterruptible power supplies with bidirectional power converters
Electrical power systems and methods using bidirectional power converters to provide, among other functions, uninterruptible power supplies for loads such as cell towers. The power-packet-switching power converter can be connected, for example, to a photovoltaic array, batteries, and a critical load such as a cell tower. An AC generator can also be connected in order to power the cell tower and/or to charge the batteries as needed. Green energy utilization is maximized, power conversion efficiency is increased, and system costs are decreased, by having only a single power conversion stage for all conversions. |
| US09293945B2 |
System and method for converting electric power, and apparatus and method for controlling the system
Disclosed is technology regarding a system and a method for power conversion, particularly technology for converting power, which is supplied from a plurality of power supply sources, using a plurality of power conversion modules. A plurality of power conversion modules, which can process all of various types of supplied power, are used to convert power according to the type of supplied power. An intermediate connection unit, which can selectively connect the power supply sources and the power conversion modules, is used so that, when one of the power conversion modules has a problem, another power conversion module is used instead to guarantee stable power supply. This construction makes the power processing path flexible and enhances system stability because, even if one of the power conversion modules malfunctions, power conversion can continue through another path. |
| US09293944B2 |
Systems and methods for providing power to one or more loads in a circuit
Disclosed are various embodiments for a power stage that can drive various types of loads. The power stage includes a first capacitor and a second capacitor that are coupled to the load. The power stage also includes switches that are operable in a first power stage state and a second power stage state. When the switches are in the first power stage state, the first capacitor discharges to the load, and the second capacitor charges. When the switches are in the second power stage state, the second capacitor discharges to the load, and the first capacitor charges. |
| US09293942B2 |
Multi-tapped inductively-coupled charging system
An apparatus for wirelessly charging an energy storage element is disclosed. The apparatus includes a coil, a set of capacitors, a set of switches and a rectifier. The coil, which has multiple taps, is capable of being energized by a charger via inductive coupling. The capacitors are connected to the coil at various taps. The switches selectively connect the rectifier to at least one of the capacitors to charge the energy storage element that is connected to the rectifier. |
| US09293941B2 |
Charger and charging apparatus
A reduction in breakdown voltage and mechanical deterioration of an electrode plate of a rechargeable battery are suppressed, and a charging time is shortened.There is provided a charger 10 which charges a rechargeable battery, comprising: a first output unit which outputs a first voltage; a second output unit which outputs a second voltage having a predetermined voltage value different from that of the first voltage; a charge control unit 16 which inputs the first voltage and the second voltage, alternately outputs these voltages, and supplies them to the rechargeable battery as charging voltages; a charged-amount detection unit 14 which measures a charged amount of the rechargeable battery; and an output control unit 15 which carries out control in such a manner that an output time of the first voltage and/or the second voltage in the charge control unit 15 is prolonged as the charged amount increases. |
| US09293938B2 |
Charging control device to prevent supplied power from exceeding contract demand
When a communication control unit (14) in this charging control device (1) receives an inhibition command sent by a power monitoring device (2), the communication control unit instructs a signal processing unit (10) to lower a current capacity (an upper limit for a charging current). The signal processing unit (10) reduces the duty ratio of a pilot signal. As a result, the charging power supplied to an electric vehicle (200) decreases, thus making it possible to prevent the supplied power from exceeding a contract demand and minimize problems stemming from the charging of a rechargeable battery. |
| US09293934B2 |
Battery charging method and mobile terminal
Embodiments of the present invention provide a battery charging method, related to the field of electronic technologies and invented to shorten the charging time. The method includes: determining, by a mobile terminal, a specification parameter of a battery to be charged; determining, by the mobile terminal, a charging parameter corresponding to the specification parameter according to the determined specification parameter; and charging, by the mobile terminal, the battery to be charged according to the determined charging parameter. Embodiments of the present invention also provide a corresponding mobile terminal. The present invention is applicable to charging of a mobile terminal. |
| US09293932B2 |
Vehicle including a charging port and a light emitter
In a vehicle, a lamp for illuminating a charging connector is provided in a charging port, and lighting and extinction of the lamp are controlled by a light emission controller. The light emission controller causes the lamp to emit light when an outer door is opened. Further, the lamp is extinguished after detecting that the outer door has been closed, the vehicle is traveling at a predetermined speed, an ignition switch has been switched ON, a door locking operation has been performed, or charging has begun. |
| US09293929B2 |
Wireless power transmitter
A wireless power transmitter includes a body having a coil module therein, and configured to transmit power in a wireless manner, a blowing module configured to cool the coil module by moving a fluid by convection and a guide module extending from the blowing module to outside of the body such that the fluid from the blowing module is discharged to outside of the body after cooling the coil module. The coil module has a shape corresponding to an outer circumference of the coil module partially or wholly. |
| US09293927B2 |
Inductively coupled power and data transmission system
An inductively coupled power and data transmission system include a main power source, apparel having an electrical conductor in electrical communication with the main power source, the apparel having a first inductively couplable power and data transmission sub-system to regulate power to the primary coil or coils and transmission of power and data by the primary coil or coils and reception of data by the primary coil or coils, and an independent device having a second inductively couplable power and data transmission sub-system so as to regulate reception of power and data by the secondary coil or coils and transmission of data from a secondary processor by the secondary coil or coils. The first and second primary coils transfer said power and data during inductive coupling, at electromagnetic radiation frequencies, between the first primary coil or coils and the secondary coil or coils. |
| US09293926B2 |
Plasma processing systems having multi-layer segmented electrodes and methods therefor
Methods and apparatus for plasma processing of a substrate to improve process results are proposed. The apparatus pertains to multi-layer segmented electrodes and methods to form and operate such electrodes. The multi-layer segmented electrode includes a first layer comprising a first plurality of electrode segments, whereby electrode segments of the first plurality of electrode segments spatially separated from one another along a first direction. There is also included a second layer comprising a second plurality of electrode segments, whereby the second layer is spatially separated from the first layer along a second direction perpendicular to the first direction and whereby at least two segmented electrodes of the first plurality of electrode segments are individually controllable with respect to one or more electrical parameters. |
| US09293924B2 |
Electrical phase synchronization
The electrical phase synchronization technology includes a system, a method, and/or components thereof. In some examples, the electrical phase synchronization system includes an electrical power transmission network having a plurality of transmission lines and a plurality of electrical power generation devices. Each electrical power generation device includes an electrical power source and a control unit. |
| US09293918B2 |
Powerline pulse position modulated three-phase transmitter apparatus and method
An electrical control system consisting of two or more electrical transmitting devices each capable of transmitting synchronized messages consisting of electrical pulses to devices connected to one or more of the three phases of the AC power lines in a typical three phase power system. The synchronized transmitters are each connected to neutral and to one or more of the three phases, A, B, and C, or across two of the phases, of different circuit breaker panels in a typical three phase power system, and are capable of transmitting messages to one or more of the three phases. The transmissions from the two or more transmitters are synchronized such that the transmitted pulses from each transmitter are transmitted at the same time to produce a message that can be received correctly at any receiving device connected to any of the connected circuit breaker panels. |
| US09293916B2 |
Sequentially operated modules
Method, modules and a system formed by connecting the modules for controlling payloads. An activation signal is propagated in the system from one module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to an external power source such as AC power. |
| US09293915B2 |
Electric power control device and electric power control system using same
A controller installed at each consumer side comprises: a power generation amount acquisition unit acquiring the amount of electricity that has been generated in a solar cell; a power selling amount acquisition unit acquiring the amount of electricity for sale that has been allowed to flow into an electric power system by reverse power flow, among the electricity generated in the solar cell; and a power selling suppression control unit configured to set a threshold value for the amount of the electricity for sale, as proportional to the amount of the generated electricity acquired by the power generation amount acquisition unit, and configured to suppress the reverse power flow into the electric power system so that the amount of the electricity for sale is set to the threshold value or less. |
| US09293913B2 |
ESD protection component and method for manufacturing ESD protection component
An ESD suppressor is configured including first and second discharge electrodes arranged as separated from each other, and a discharge inducing portion kept in contact with the first and second discharge electrodes so as to connect mutually opposed portions of the first and second discharge electrodes to each other. The discharge inducing portion contains metal particles. The first and second discharge electrodes are located on the coil side with respect to the discharge inducing portion when viewed in a stack direction of a plurality of insulator layers. An element body has a cavity portion located so as to cover the whole of the discharge inducing portion when viewed in the stack direction from the coil side. The cavity portion is in contact with the mutually opposed portions of the first and second discharge electrodes and with the discharge inducing portion. |
| US09293909B2 |
Passive circuit for improved failure mode handling in power electronics modules
A power electronics module for enhancing short circuit failure mode (SCFM) transitions. The module is adapted to disconnect a gate unit from the module using a first switch, upon a failure of at least one of a plurality of semiconductor chips during which the failed chip enters an SCFM, and connect a passive circuit arrangement, including at least one capacitor and at least one resistor, to the module using a second switch. The passive circuit arrangement is adapted to switch on at least one of the remaining non-failed semiconductor chips. |
| US09293908B2 |
Method of measurement for detecting a fault of a three-phase zone
Method for protecting an electrical energy distribution box, the electrical energy distribution box comprising a set of distribution bars intended to be connected between a generator and loads, each of the bars being able to transfer at least a part of the electrical energy passing through it to at least one other bar of the set of bars. According to this method, the incoming and outgoing currents of a single distribution bar are measured and a fault in the set of bars is detected on the basis of the currents measured in the said bar. |
| US09293907B2 |
Protective device for load circuit
A load circuit protective device calculates increasing temperature of wire of a load circuit with a first predetermined sampling period (dt1) determined by a clock signal for normal operation when a semiconductor relay (Q1) is on to estimate the temperature of the wire. The temperature of the wire is therefore estimated with high accuracy. Moreover, when the semiconductor relay (Q1) is off, the load circuit protective device calculates decreasing temperature of the wire of the load circuit with a second predetermined sampling period (dt2) to estimate the temperature of the wire. The second predetermined sampling period (dt2) is determined by a clock signal for power-saving operation and is longer than the first predetermined sampling period (dt1). Accordingly, the calculation times of the temperature can be reduced, and the power consumption is therefore reduced. |
| US09293904B2 |
Electric wire drawout part structure
An electric wire drawout part structure so that the cover can be easily unlocked and the pipe body can be positioned without using a jig is provided. An electric wire drawout part structure including a housing, a cover which covers an opening part of the housing except an electric wire drawout part, electric wires which are drawn out from the electric wire drawout part, and a pipe body which accommodates and protects the electric wires, wherein, the cover is provided with an unlocking and positioning part for unlocking the cover from the housing and positioning the pipe body. |
| US09293903B2 |
Electrical junction box
A convenient electrical juncture box will be used to repairing a broken household electrical wire, or to connect new wires to multiple locations. It provides all components that need for repairing job in a package. The package will include a conductor unit installed on a base structure, a cover box to enclose the entire electrical circuitry, two nails for securing the electrical juncture box to the wooden beam, and four screws for attaching the cover box to the base structure. The electrical juncture box can be mounted on a wooden beam in an open space such as the attic, crawlspace of a frame or similar structure. |
| US09293899B2 |
Transition splice for cable routing system
The present invention is directed toward a transition splice that joins a cable tray and cable basket to form a cable routing system. The cable tray and cable basket each include a plurality of longitudinal wires and a plurality of transverse wires. An end transverse wire of the cable basket is positioned adjacent to an end transverse wire of the cable tray. A plurality of the longitudinal wires of the cable tray and the cable basket are aligned to form a pathway. The transition splice is secured to an end of the cable tray and to an end of the cable basket to maintain the pathway for routing cables thereon. |
| US09293897B2 |
Panelboard and electrical power distribution system
An electrical power distribution system or panelboard that includes a hollow central body with at least one insulated bus bar and a top non-energized metal mounting surface. A plurality of connection points are distributed along the bus bar for electrical device connections. The connection points are contained inside molded plastic holes or wells, and are electrically connected to the main bus bar. Electrical device connections are accomplished via connectors plugged into the holes or wells. The attachment of electrical devices of various sizes and configurations may be accommodated through the use of spacers. |
| US09293889B1 |
Seeded Raman amplifier in a nested configuration for generating a 1240 nm laser
A third-order Stokes signal at the desired output wavelength of 1240 nm and a zeroth-order Stokes pump wavelength at 1066 nm are seeded into a Raman amplifier comprised of two nested resonators tuned to the first-order Stokes line at 1118 nm and second-order Stokes line at 1176 nm, respectively. The pump wavelength is first amplified and then sequentially converted into the first and second-order Stokes wavelengths as the light traverses the nested resonators. The desired third-order Stokes output wavelength is then amplified by the second-order Stokes wavelength as it propagates through the outermost resonator. Each Raman resonator includes a photosensitive Raman fiber located between a pair of Bragg gratings. The linewidths of the various Stokes orders can be controlled through adjusting the resonant bandwidths of the Raman resonators by offsetting, through heating, the reflectivity bandwidths of each pair of Bragg gratings respectively located in the Raman resonators. |
| US09293888B2 |
Method and apparatus for high-power raman beam-combining in a multimode optical fiber
According to an embodiment of the disclosure, a system for producing a higher power laser beam is provided. The system includes an optical fiber having a length. The optical fiber is configured to receive inputs from multiple laser pumps and an input from a Stokes seed laser pump. The optical fiber has a core that is doped. The core, when viewed from a cross-section of the optical fiber, has a higher concentration of doping at a location near an axis of the optical fiber than a location further from the axis of the optical fiber. The optical fiber is also configured to convert pump power to Stokes power along the length of the optical fiber when subjected to a Stimulated Raman Scattering (SRS) process. |
| US09293887B2 |
Chip-based laser resonator device for highly coherent laser generation
A highly-coherent chip-based laser generating system includes a disk resonator incorporating a wedge structure fabricated from a silicon dioxide layer of a chip. The disk resonator is operable to generate a highly-coherent laser from a low-coherence optical pump input provided at an optical power level as low as 60 μW. The disk resonator is fabricated with sub-micron cavity size control that allows generation of a highly-coherent laser using a controllable Stimulated Brillouin Scattering process that includes matching of a cavity free-spectral-range to a Brillouin shift frequency in silica. While providing several advantages due to fabrication on a chip, the highly-coherent laser produced by the disk resonator may feature a Schawlow-Townes noise level as low as 0.06 Hz2/Hz (measured with the coherent laser at a power level of about 400 μW) and a technical noise that is at least 30 dB lower than the low-coherence optical pump input. |
| US09293879B2 |
Brush holder apparatus, brush assembly, and method
Devices and methods of use for brush holder assemblies are disclosed. Brush holder assemblies including a mounting block and a brush holder are disclosed. Also illustrated is a brush holder assembly including a first portion in sliding engagement with a second portion. In some embodiments the brush holder includes a channel, such that at least a portion of the mounting block is disposed within the channel of the brush holder. |
| US09293877B2 |
Interface adapter
An apparatus for use with a first RJ-type female receptacle having an open, plug receiving end and an internal cavity, the first RJ-type female receptacle designed to receive a corresponding first modular mating RJ-type male plug, the apparatus having: a housing having a front face, a top wall, a bottom wall and side walls defining an opening formed within the front face; and the apparatus received in the first RJ-type female receptacle, and the opening dimensioned to receive a second modular mating RJ-type male plug, wherein the second modular mating RJ-type male plug is dimensioned smaller than the first modular mating RJ-type male plug. |
| US09293876B2 |
Techniques for configuring contacts of a connector
Systems and methods for configuring contacts of a first connector includes detecting mating of a second connector with the first connector and in response to the detection, sending a command over one of the contacts and waiting for a response to the command. If a valid response to the command is received, the system determines the orientation of the second connector. The response also includes configuration information for contacts in the second connector. The system then configures some of the other contacts of the first connector based on the determined orientation and configuration information of the contacts of the second connector. |
| US09293871B2 |
Electrical plug and associated electrical assembly
An electric plug (200) adapted to be plugged into a socket outlet (100) delivering an electrical signal having at least one characteristic adapted to vary in a determined range of values and including identification elements arranged to communicate or to co-operate with the electric plug to generate a pilot signal representative of the electrical signal delivered by the socket outlet, includes: reader elements (230) adapted to receive the pilot signal issued by the identification elements, and to supply the pilot signal to the electric plug; and verification elements (280) adapted to detect a spurious signal not issued by the identification elements (130), and to block forwarding of the pilot signal when such a spurious signal is detected, or to forward an alert signal to the electric plug when such a signal is detected. An electrical assembly including such an electric plug and a socket outlet are also described. |
| US09293870B1 |
Electronic control module having a cover allowing for inspection of right angle press-fit pins
An electronic control module which has a housing, a cavity formed as part of the housing, and a connector. The control module also includes a plurality of pins, and a portion of the housing is integrally formed around the pins such that a first end of each of the pins are part of the connector, and a second end of each of the pins is located in the cavity. The control module also has a cover with a large portion and a small portion. A sealant is disposed between part of the cover and the housing to provide a seal between the cover and the housing. The small portion of the cover is bendable relative to the large portion to allow an inspection of the pins after the pins are press-fitted into the circuit board as the cover is connected to the housing. |
| US09293868B2 |
Attachment ring for attaching a shield of a cable to a shell
An electrical connector includes a cable having a shield, a shell and an attachment ring for attaching the shield to the fitting. The shell extends between a mating end and a cable end. The shell has a fitting at the cable end. The shell has a cavity receiving an end of the cable through the fitting. The attachment ring is received inside the shield and the fitting. The attachment ring presses the shield outward against an inner surface of the fitting. The shield may be positioned radially inside of the fitting and the attachment ring may be positioned radially inside of the shield. A radially outer edge of the attachment ring may impart an outward radial load onto the shield. |
| US09293867B2 |
Cable portion including a coupling device for connecting subscriber lines to a databus line
A cable portion comprising a databus line (54) having one or more subscriber lines (52) connected thereto by a coupler device. The databus line and the subscriber line(s) each comprise a twisted pair of conductors protected by shielding. The coupler device comprises a coupler (53) providing data transmission between the two parts of the databus line and between the databus line and the subscriber line(s), and connectors (56A, 56B, 58) serve to connect the databus line with the subscriber line(s) in reversible manner. The coupler device presents weight of less than 70 g and is held by means of a fastener collar that enables the cable portion to be put into place in particularly practical manner in order to constitute a data transmission circuit. |
| US09293861B2 |
Apparatus for cutting off fibre mats
The present subject matter concerns a method and an apparatus for cutting fiber mats where the cutting is effected with a mechanical automatic tool, where cutting of the fiber mat is effected so that the cut surface on the fiber mat can be varied from an angle greater than 0° to an angle less than 180° in relation to both surfaces on the fiber mat, where it is the variable position of the fiber mat relative to the direction of movement and cutting of the cutting tool that determines the angle of the cut. A fiber mat may be cut with a cut which is particularly adapted to the specific piece of fiber mat which is cut. It is thus possible to have a production where various requirements to cut faces in the fiber mats can be met. |
| US09293860B1 |
Connector for a vehicle
A connector and connector system for a vehicle, as well as a method of operating the connector, are provided. The connector includes a connector housing that has slide holes formed at both ends of a receiving surface and extending in the longitudinal direction of the connector housing. A slide bar is mounted slideably in the longitudinal direction of the connector housing, with an end inserted in the slide holes. A lever is mounted at the other end of the slide bar and has one end turnably coupled to the receiving surface of the connector housing. The lever is configured to pivot in a height direction of the connector housing, press the slide bar further into the slide holes and fix a counter connector to the connector housing, when being turned. |
| US09293859B2 |
Grooved connectors with retaining mechanisms
A connector is disclosing with a housing having a housing groove and a shaft with a pin groove. A spring may be located in either the housing groove or the pin groove. To prevent or limit the spring from popping out from the groove where it is positioned, a reduced entrance is provided. The connector may be used in a holding application, a latching application, or both a holding with latching application. |
| US09293856B2 |
Connector assembly
A connector assembly includes a housing (1) in which a wire-side terminal (2) is held, and which is fitted to a mounting hole formed in a casing 5 of a mating device to be connected, and a sealing member (3) which is attached to a groove part (16) formed in an outer peripheral part (11) of the housing thereby to keep an interior of the casing liquid tight. The sealing member (3) includes a convex part (33) formed in a curved part thereof, by protruding in a width direction from its peripheral edge part in a shape of an 10 annularly continued band. The groove part (16) includes a concave part (18) formed by denting a groove wall (16b), corresponding to the convex part (33). The convex part (33) and the concave part (18) are engaged with each other. |
| US09293852B2 |
Electrical terminal assembly
An electrical terminal assembly includes a base and a spring member. The base defines an axis and includes a plurality of base beams deflectable toward the axis. The spring member has a main portion that is disposed over the base, and a plurality of spring beams that extend from the main portion. The spring beams bias the base beams toward the axis. The main portion of the spring member is made from a folded blank having a first edge that is permanently secured to a second edge such that the edges cannot be pulled apart from one another. |
| US09293850B2 |
High power electrical connector contact
A high power, single pole male electrical connector with a reduced surface area contact is disclosed. The male connector is configured for insertion into a female connector of standard design. The reduced surface area of the contact region of the male connector results in less surface contact between the male and female connectors. |
| US09293846B2 |
Thin connector having a first connector slidably superimposed on a second connector
A thin connector comprises a first connector having a flat plate shape and a second connector having a flat plate shape superimposed on and fitted with each other, the first connector including first contacts arrayed in a direction, each first contact being provided with a first contact portion, the second connector including second contacts arrayed in a same direction as the direction in which the first contacts are arrayed, each second contact being provided with a second contact portion, each first contact having a spring portion which extends in a direction obliquely crossing the direction in which the first contacts are arrayed and on which the first contact portion is formed. |
| US09293845B2 |
Mezzanine receptacle connector
A mezzanine receptacle connector includes a housing having a mating end configured to be mated with a mezzanine header connector and a mounting end configured to be mounted to a circuit board. The mating end is opposite the mounting end and includes a plurality of contact cavities configured to receive associated header contacts of the mezzanine header connector. Receptacle contacts are received in corresponding contact cavities of the housing. Each receptacle contact has a main contact and a sub-contact extending from the main contact. The main contact defines a first mating interface and the sub-contact defines a second mating interface. The first and second mating interfaces of each receptacle contact are configured to directly engage the same header contact of the mezzanine header connector at different points of contact. |
| US09293844B2 |
Four-post terminal block with through posts
A terminal block, terminal board and terminal board assembly for terminating and testing railroad wires. The terminal block comprises a plurality of through-posts, allowing wiring and other components to be attached on posts on first and/or second sides of the terminal block. A surge protection component, control test link, and first wiring may be pre-installed on one side of the terminal block and terminal board, providing for quick installation prior to installing the terminal board assembly in the field. The through-posts also simplify the mounting of the terminal block to the terminal board, and the grounding for the terminal board. |
| US09293841B2 |
Mechanical lug with dovetail interlock feature
The present invention is directed to a mechanical lug with interlocking features that secures an electrical conductor. The mechanical lug has a main body and a mounting tongue extending from the main body. The main body includes an inner flange and an outer flange. The inner flange has a horizontal member and an interlocking member with angled pockets. The outer flange has hooks with a tapered face positioned in the angled pockets of the interlocking member of the inner flange thereby forming a dovetail interlock. |
| US09293840B2 |
Wire connector having a wire holder with an abutting portion and a protecting portion
A wire connector is described that suppresses the cutting of wires accidentally. The wire connector 1 includes a wire holder 6 that holds at least two wires, a contact 7A that electrically connects the two wires and a body 4 that holds the wire holder. The wire holder 6 includes first and second end faces 24 and 26, and a wire holding portion 25 that includes first and second holding portions 32, 33, 34 and 36. On the first end face 24, at portions of circumferential edge portions of the openings 34c and 36d of the second holding portions 34 and 36, protecting portions 23 that project from the first end face 24 and protect the wires are provided. |
| US09293838B2 |
Aluminum cable provided with crimping terminal
A crimping portion includes a first crimping portion including a conductor crimping portion and a conductor enveloping portion that is integrally connected to the conductor crimping portion and envelops a portion of a conductor in the vicinity of an insulating covering portion, and a second crimping portion that is separate from the first crimping portion and crimped to the insulating covering portion in the vicinity of the conductor. A gap between the first crimping portion and the second crimping portion is sealed with a sealer, and thus the first crimping portion and the second crimping portion are integrally interconnected to each other. |
| US09293837B2 |
Wireless communication apparatus
A wireless communication apparatus includes a first antenna, an antenna driving circuit, a first medium, a second medium, and a second antenna. The antenna driving circuit drives the first antenna. The first medium is electrically connected between the first antenna and the antenna driving circuit. The second medium and the first medium are in energy coupling. The second antenna is electrically connected with the second medium. |
| US09293836B2 |
Antenna apparatus
According to one embodiment, an antenna apparatus includes a concave curved reflector, a radiator arranged in a focal position of the reflector to perform at least one of transmission of two linearly polarized waves toward a concave surface of the reflector and reception of the waves from the concave surface, the two linearly polarized waves being crossed orthogonally to each other, and a structural unit configured to support the radiator at the focal position. The unit includes a main body protruding from a rear surface of the reflector into a radiation space defined by the concave surface at a position on the concave surface, the position being apart from two linear polarization planes defined by the two linearly polarized waves. |
| US09293833B2 |
Low impedance slot fed antenna
A low impedance slot fed antenna with a slot and an element configured to resonate is depicted. The orientation of the slot is configured so that a slot current is not opposed to a return current associated with the element. This helps decrease coupling between the slot and the element, which can benefit high Q antennas. |
| US09293832B2 |
Broadband antenna feed array
A microwave antenna suitable for monopulse radar applications is operable over a broad frequency band. The antenna uses a horn with two walls. Each wall includes two ridges that extend into an inner region of the horn near the horn's base and then taper into the wall surfaces. The horn is coupled to two ridged waveguide sections with the ridges of the waveguide sections matched to opposed pairs of the horn ridges. The antenna may be coupled to electronics via standard waveguides. In many embodiments, dimensions of the waveguides coupled to the horn are smaller (to provide a small array spacing) than dimensions of the standard waveguides with a tapered waveguide section providing a transition. In one embodiment, the antenna operates with frequencies from 5.25 to 10.5 GHz. |
| US09293828B2 |
Antenna system with tuning from coupled antenna
Electronic devices may include radio-frequency transceiver circuitry and antenna structures. The antenna structures may form a dual arm inverted-F antenna and an additional antenna such as a monopole antenna sharing a common antenna ground. The antenna structures may have three ports. A first antenna port may be coupled to an inverted-F antenna resonating element at a first location and a second antenna port may be coupled to the inverted-F antenna resonating element at a second location. A third antenna port may be coupled to the additional antenna. An adjustable component may be coupled to the first antenna port to tune the inverted-F antenna. The inverted-F antenna may be near-field coupled to the additional antenna so that the inverted-F antenna may serve as a tunable parasitic antenna resonating element that tunes the additional antenna. |
| US09293819B2 |
Antenna apparatus and mobile terminal having the same
An antenna apparatus includes: a first member ground-connected to a ground of a printed circuit board (PCB); a second member spaced from the first member in parallel, and configured to capacitive coupling-feed the first member so as to transmit and receive signals of a first frequency band; and a third member extending from the second member by a prescribed length, so as to have a bandwidth extending up to a second frequency band adjacent to the first frequency band. |
| US09293818B2 |
Intra-pericardial medical device
An intra-pericardial medical device is provided that comprises a lead body having a proximal portion, a distal end portion, and an intermediate portion extending between the proximal portion and the distal end portions. An intra-pericardial medical device further includes the control logic housed with the lead body and an energy source housed within the lead body. A stimulus conductor is included and extends along the lead body. An electrode is joined to the stimulus conduct near the distal end portion, where the electrode configured to deliver stimulus pulses. A telemetry conductor is provided within the lead and extends from the proximal portion and along the intermediate portion of the lead body. The telemetry conductor is wound into a series of coil groups to form inductive loops for at least one of receiving and transmitting radio frequency (RF) energy. |
| US09293817B2 |
Stacked array antennas for high-speed wireless communication
Array antennas for wireless transmission having an array of emitters/receivers that are compactly arranged above an antenna feed and ground plate. These high gain devices may be configured to operate in any appropriate band, such as the 5.15 to 5.85 GHz band and/or the 2.40-2.48 GHz band. The antenna emitters are arranged in a separate plane (or planes) above an antenna feed connecting the emitting elements to the radio circuitry. The antenna feed is positioned between the emitters and a ground plane. The antenna array may be configured to operate with both horizontal and vertical polarization. The apparatuses may be configured for low impedance mismatch and may have a high gain relative to a very small and compact overall shape. |
| US09293814B2 |
Hearing aid with an antenna
A hearing aid includes a housing, and a hearing aid assembly accommodated in a housing, the hearing aid assembly having a first antenna element configured for emission of an electromagnetic field, and a second antenna element comprising a first section and a parasitic antenna element, wherein the first antenna element, the first section, and the parasitic antenna element are configured so that a total electromagnetic field emitted from the hearing aid assembly is substantially the same irrespective of whether the housing is worn in its operational position on a right hand side or a left hand side of a user. |
| US09293812B2 |
Radar antenna assembly
A radar antenna assembly includes a microstrip patch, a hybrid coupler, a phase shifter, and a power divider. The microstrip patch is configured to emit a radar signal. The radar signal is characterized by a transmitted polarization of the radar signal. The transmitted polarization is influenced by a first transmit signal received at a first port of the microstrip patch and a second transmit signal received at a second port of the microstrip patch. The hybrid coupler is configured to orthogonally combine a first input signal and a second input signal to output the first transmit signal and the second transmit signal. The phase shifter is operable to vary the phase of the second input signal relative to the first input signal. The power divider is configured to divide unequally a source signal so the amplitudes of the first input signal and the second input signal are substantially equal. |
| US09293800B2 |
RF transmission line disposed within a conductively plated cavity located in a low mass foam housing
An electrical structure having a foam housing is set forth. The foam housing includes an interior surface forming a conductive cavity adapted to carry energized waveforms therethrough. An electrical component of the electrical structure is integrally formed with the interior surface as the foam housing of the structure is assembled. |
| US09293797B2 |
RF switch with transformer and switching method thereof
A radio frequency (RF) switch with a transformer and a switching method thereof are provided. The RF switch includes a transmitting end transformer having a primary side connected to a transmitting end and a secondary side connected to an antenna; and a receiving end transformer having a primary side connected to the antenna and a secondary side connected to a receiving end. In a transmission mode, the transmitting end transformer is tuned on, and, in a reception mode, the receiving end transformer is turned on. Accordingly, since switching is performed based on transformers rather than transistors connected in series, the RS switch, which can achieve high linearity and low insertion loss as well as high isolation, can be implemented. |
| US09293796B2 |
Metal-air battery with dual electrode anode
This disclosure describes metal air battery devices with an anode structure having a plurality of electrodes. An anode is disclosed having a metal source as well as a current collector that together function as an active, reversible, working anode. The source is used for metal-ions that are stripped and stored in the current collector. At this point the current collector contains the metal-ions to be propagated through the rest of the device. Metal-ions may be stripped from and deposited on the current collector, while metal-ions may only be stripped from the source. Upon use of the device metal-ions may be lost to the system for a variety of reasons. To counteract the loss of metal-ions, the current collector is replenished of metal-ions from the source. |
| US09293792B2 |
Self-activated draining system
A method of managing leakage of liquid inside a battery system comprises: containing leaking liquid in a non-liquid sensitive region of the battery system so as to protect internal electrical components of the battery system from coming in contact with the leaking liquid; and in direct response to the leakage, expunging the leaking liquid from the battery system. A drain device includes: a body with a port therethrough, the body configured to be positioned in a wall of a container; means for opening the port in response to a first liquid contacting the drain device on an inside of the container; and means for resisting ingress into the container by a second liquid that contacts the drain device on an outside of the container. |
| US09293790B2 |
High voltage rechargeable magnesium batteries having a non-aqueous electrolyte
A rechargable magnesium battery having an non-aqueous electrolyte is provided. The properties of the electrolyte include high conductivity, high Coulombic efficiency, and an electrochemical window that can exceed 3.5 V vs. Mg/Mg+2. The use of the electrolyte promotes the electrochemical deposition and dissolution of Mg without the use of any Grignard reagents, other organometallic materials, tetraphenyl borate, or tetrachloroaluminate derived anions. Other Mg-containing electrolyte systems that are expected to be suitable for use in secondary batteries are also described. |
| US09293786B1 |
Solid organic electrolytes
Solid, or highly viscous, organic electrolytes consisting of alkylimidazolium cation with alkyl, PEGylated and fluorinated side chains of different molecular weights were synthesized and characterized (cf. chemical structures in Schemes 1 and 2). The PEGylated/fluorinated imidazolium iodide is a solid organic electrolyte that has a conductivity of about 2×10−5 S/cm at 30° C. The ionic conductivity could be significantly increased (1.11×10−4 S/cm at 30° C. and S/cm at 2.88×10−3 at 90° C.) by blending the PEGylated/fluorinated imidazolium iodide with another solid electrolyte, 1-ethyl-3-methylimidazolium iodide (EtMImI). The PEGylated imidazolium iodides synthesized in the present work have conductivities in the range 1.6×10−4 S/cm to 2×10−4 S/cm at 30° C. and viscosities in the range 620 cP to 720 cP at 30° C. The iodide counter ion in the present electrolytes supplies the anion for the I−/I3− redox mediators for DSSCs. Therefore, the organic electrolytes of the present invention can be used even without the addition of inorganic salts such as LiI or KI. We found that the addition of an organic solid electrolyte, EtMImI, resulted in an increase in the ionic conductivity of the PEGylated/fluorinated imidazolium iodides, whereas the addition of the inorganic LiI led to a decrease in ionic conductivity. All the electrolytes are thermally stable until high temperatures (250° C. to 300° C.). |
| US09293785B2 |
Lithium ion secondary battery, vehicle, and battery mounting device
A lithium ion secondary battery includes a flat wound electrode body including a positive electrode sheet and a negative electrode sheet that are wound while interposing therebetween separators into a flat shape, and a battery case. In the flat wound electrode body, a central portion has a more constricted shape than end portions by pressing toward a winding axis in a short-side direction and each end portion includes an end-portion positive electrode sheet, an end-portion negative electrode sheet, and end-portion separators, and a core member arranged more inward than them. With tensile forces generated by pressing of the central portion in a central-portion positive electrode sheet, central-portion negative electrode sheet, and central-portion separators, the end-portion positive electrode sheet, end-portion negative electrode sheet, and end-portion separators are in pressure contact with each other and press the outer surfaces of the core member. |
| US09293783B2 |
Electrode for secondary battery, preparation thereof, and secondary battery and cable-type secondary battery comprising the same
The present disclosure provides a sheet-form electrode for a secondary battery, comprising a current collector; an electrode active material layer formed on one surface of the current collector; a conductive layer formed on the electrode active material layer and comprising a conductive material and a binder; and a first porous supporting layer formed on the conductive layer. The sheet-form electrode for a secondary battery according to the present disclosure has supporting layers on at least one surfaces thereof to exhibit surprisingly improved flexibility and prevent the release of the electrode active material layer from a current collector even if intense external forces are applied to the electrode, thereby preventing the decrease of battery capacity and improving the cycle life characteristic of the battery. |
| US09293782B2 |
Winder for electrode assembly of rechargeable battery and electrode assembly manufacturing method using the same
An exemplary embodiment provides a winder for an electrode assembly of a rechargeable battery capable of improving productivity by shortening a winding cycle. A winder for an electrode assembly of a rechargeable battery according to an exemplary embodiment includes: a nip roll catching and feeding a positive plate and a negative plate, and a separator; a rotor disposed below the nip roll to rotate; and a plurality of winding cores arranged in the rotor at a regular interval in a rotation direction of the rotor to rotate and move forward or backward from the rotor, wherein the center of the nip roll, the center of any one winding core among the plurality of winding cores, and one surface of an electrode assembly of another winding core which is winding-completed form a straight line. |
| US09293780B2 |
Sulfonated poly(phenylene sulfide sulfone nitrile) and membrane for fuel cell thereof
The present invention provides sulfonated poly(phenylene sulfide sulfone nitrile) and a polymer electrolyte membrane thereof. In particular, the present invention provides sulfonated poly(phenylene sulfide sulfone nitrile) having a triple bond at its both ends and a polymer electrolyte membrane with superior mechanical properties prepared by heating sulfonated poly(phenylene sulfide sulfone nitrile) and forming cross-links between ends of sulfonated poly(phenylene sulfide sulfone nitrile). |
| US09293775B2 |
Compact safety type fuel cell system
This invention provides a compact safety type fuel cell system, including an enclosure and the electronic control system, electric isolation board, gas isolation board, fuel cell stack system, hydrogen delivery device installed in the enclosure. The electric isolation board divides the inside of the enclosure into electronic control system space and fuel cell stack working space, the gas isolation board divides the fuel cell stack working space into hydrogen side space and air inlet space, the air inlet space and the air inlet port of the fuel cell stack system are connected, the fuel cell stack system enclosure connects with the gas isolation board hermetically. This invention achieves electric isolation in a limited space and the effective isolation between air and hydrogen, which can directly replace the lead-acid cell system on battery-powered forklift being widely used now, requires no forklift redesign due to such problems as insufficient placing space, etc. and facilitates upgrading. |
| US09293772B2 |
Gradient porous electrode architectures for rechargeable metal-air batteries
A cathode for a metal air battery includes a cathode structure having pores. The cathode structure has a metal side and an air side. The porosity decreases from the air side to the metal side. A metal air battery and a method of making a cathode for a metal air battery are also disclosed. |
| US09293766B2 |
Lithium nickel cobalt manganese composite oxide cathode material
A lithium nickel cobalt manganese composite oxide cathode material includes a plurality of secondary particles. Each secondary particle consists of aggregates of fine primary particles. Each secondary particle includes lithium nickel cobalt manganese composite oxide, which is expressed as LiaNi1-b-cCobMncO2. An average formula of each secondary particle satisfies one condition of 0.9≦a≦1.2, 0.08≦b≦0.34, 0.1≦c≦0.4, and 0.18≦b+c≦0.67. The lithium nickel cobalt manganese composite oxide has a structure with different chemical compositions of primary particles from the surface toward core of each of the secondary particles. The primary particle with rich Mn content near the surface and the primary particle with rich Ni content in the core of the secondary particle of the lithium nickel cobalt manganese composite oxide cathode material have provided the advantages of high safety and high capacity. |
| US09293763B2 |
Silicon oxide, making method, negative electrode, lithium ion secondary battery, and electrochemical capacitor
Particulate silicon oxide having a Cu content of 100-20,000 ppm, an Fe content of 20-1,000 ppm, an Al content of up to 1,000 ppm, an average particle size of 0.1-30 μm, and a BET specific surface area of 0.5-30 m2/g is used as negative electrode material in constructing a nonaqueous electrolyte secondary battery. The secondary battery is improved in cycle performance while maintaining the high battery capacity and low volume expansion of silicon oxide. |
| US09293762B2 |
Anode material including nanofibers for a lithium ion cell
An anode material for a galvanic element, in particular a lithium-ion cell. To improve the current density and thermal stability of galvanic elements, the anode material includes nanofibers made of a metal, a metal alloy, a carbon-metal oxide composite material, a carbon-metal alloy composite material, a conductive polymer, a polymer-metal composite material, a polymer-metal alloy composite material or a combination thereof. The nanofibers may be in the form a nanofiber netting, a nonwoven and/or a network and may be connected to a current conductor. |
| US09293756B2 |
Rechargeable battery
A rechargeable battery including an electrode assembly including a first electrode, a second electrode, and a separator between the first electrode and the second electrode; a case containing the electrode assembly; a cap plate covering an opening of the case; and an external short circuit assembly on the cap plate and including: a cover on the cap plate; and a terminal plate on the cover and coupled to the cover. |
| US09293753B2 |
Porous membrane for secondary battery, slurry for secondary battery porous membrane and secondary battery
The porous membrane according to the present invention comprises non-conductive particles, a binder, and a water-soluble polymer, and is characterized in that: the three dimensions of the non-conductive particles, namely the length (L), thickness (t), and width (b), are such that the length (L) is 0.1 to 0 μm, the ratio (b/t) of the width (b) and the thickness (t) is 1.5 to 100; the binder is a copolymer containing (meth)acrylonitrile monomer units and (meth)acrylic acid ester monomer units; and the water-soluble polymer contains sulfonic acid groups, and has a weight average molecular weight of 1000 to 15000. The slurry for a porous membrane according to the present invention is characterized by being formed by dispersing the non-conductive particles, the binder, and the soluble polymer, in water. Thus, the present invention provides: a porous membrane that can be formed into a thin film, has an excellent sliding property, and generates few particles; and a slurry for porous membranes which is capable of producing porous membrane easily and quickly, and has excellent storage stability. |
| US09293752B2 |
Multilayer porous membrane and production method thereof
The present invention provides a multilayer porous membrane having both high safety and practicality, especially as a separator for a non-aqueous electrolyte battery and comprising a porous layer containing an inorganic filler and a resin binder on at least one surface of a polyolefin resin porous membrane, wherein the porous layer simultaneously satisfies the following (A) to (C): (A) the inorganic filler has an average particle diameter of 0.1 μm or more and 3.0 μm or less, (B) a ratio of an amount of the resin binder to a total amount of the inorganic filler and the resin binder is 1% or more and 8% or less in terms of volume fraction, and (C) a ratio of a layer thickness of the porous layer to a total layer thickness is 15% or more and 50% or less. |
| US09293749B2 |
Heat-resistant and high-tenacity ultrafine fibrous separation layer, method for manufacturing same, and secondary cell using same
Provided is an ultrafine fibrous porous separator with heat resistance and high-strength and a manufacturing method thereof, which enables mass-production of a heat-resistant and high-strength ultrafine fibrous separator by using an air-electrospinning (AES) method, and to a secondary battery using the same. The method of manufacturing a heat-resistant and high-strength ultrafine fibrous porous separator includes the steps of: air-electrospinning a mixed solution of 50 to 70 wt % of a heat-resistant, polymer material and 30 to 50 wt % of a swelling polymer material, to thereby form a porous web of a heat-resistant ultrafine fiber in which the heat-resistant polymer material and the swelling polymer material are consolidated in an ultrafine fibrous form; performing drying to control a solvent and moisture that remain on the surface of the porous web; and performing thermal compression on the dried porous web at a temperature of between 170° C. and 210° C. so as to obtain the separator. |
| US09293746B2 |
Methods and systems for supporting a battery
A battery support includes a base having an upper surface and a lower surface, a spine extending downwardly from and axially along the base such that at least a portion of the base is cantilevered from the spine, and at least one rib extending downwardly from the base and laterally from the spine. The upper surface is sized to support a battery thereon. |
| US09293743B2 |
Battery pack
Provided is a battery pack. The battery pack may prevent a center of a protective circuit module from being bent by external impacts during or after a process of manufacturing a battery pack. The battery pack includes a bare cell from which an electrode terminal protrudes, a circuit module disposed above the electrode terminal, a positive temperature coefficient (PTC) unit disposed between the bare cell and the circuit module, the PTC unit being electrically connected to the bare cell and the circuit module, and an electrode lead plate having one side contacting the electrode terminal and the other side contacting the PTC unit, the electrode lead plate having a top surface contacting a bottom surface of the circuit module. |
| US09293741B1 |
Mechanical conditioning by bead blasting lithium iodine cell case
Bead blasting the inner, contact surface of an electrochemical cell casing to render the inner surface thereof essentially contamination free and suitable as a current collector, is described. The casing is preferably of stainless steel and houses the alkali metal-halogen couple in a case-positive configuration. |
| US09293739B2 |
Process and materials for making contained layers and devices made with same
There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer including a fluorinated material and having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation having a wavelength greater than 300 nm, resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from the unexposed areas resulting in a first layer having a patterned priming layer, wherein the patterned priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid deposition on the patterned priming layer on the first layer. The priming layer includes an aromatic amine compound and a photoinitiator. |
| US09293730B2 |
Flexible organic light emitting diode display and manufacturing method thereof
A flexible organic light emitting diode (OLED) display according to an exemplary embodiment includes: a substrate; an organic light emitting diode (OLED) layer provided on the substrate; and a thin film encapsulation layer provided on the OLED layer. The thin film encapsulation layer includes a plurality of laminated inorganic layers, at least one inorganic layer of the plurality of inorganic layers includes a plurality of inorganic layer patterns that are disposed to be spaced apart from each other on a plane, and an organic layer is formed between the plurality of inorganic layer patterns. |
| US09293729B2 |
Organic light emitting diode display package with sealant and adhesive reinforcing member
An organic light emitting diode display may include a display substrate including an organic light emitting diode, a sealing member facing the display substrate to cover the organic light emitting diode, a sealant positioned between the display substrate and the sealing member and bonding the display substrate and the sealing member, and a reinforcing member positioned at an outer surface of the sealant and a space between the display substrate and the sealing member, in which shear stress and hardness of the reinforcing member are a function of a sum of thicknesses of the display substrate and the sealing member. |
| US09293724B2 |
Light-emitting element, light-emitting device, display device, and electronic apparatus
Disclosed herein is a light-emitting element, including: a cathode; an anode; and a light-emitting unit, in which the light-emitting unit includes a first light-emitting layer, an intermediate layer, a second light-emitting layer, and a third light-emitting layer, which are laminated from the anode side to the cathode side, in which each of the second and third light-emitting layers is configured to contain a luminescent material, a host material, and an assist dopant material, in which the intermediate layer is configured to contain the host material and the assist dopant material, and in which, when the concentrations of the assist dopant materials contained in the second light-emitting layer, the third light-emitting layer, and the intermediate layer are respectively expressed by CAssist(EML2), CAssist(EML3), and CAssist(IML), the following Relational Expression (A) is satisfied: CAssist(IML)>CAssist(EML2)≧CAssist(EML3) (A). |
| US09293719B2 |
Semiconductor device, method of manufacturing the same, and electronic apparatus
A semiconductor device includes: a gate electrode; an organic semiconductor film forming a channel; and a pair of source-drain electrodes formed on the organic semiconductor film, the pair of source-drain electrodes each including a connection layer, a buffer layer, and a wiring layer that are laminated in order. |
| US09293718B2 |
Diketopyrrolopyrrole polymers and small molecules
The present invention relates to polymers, comprising a repeating unit of the formula (I), and compounds of formula (II), wherein Y, Y15, Y16 and Y17 are independently of each other a group of formula (a) characterized in that the polymers and compounds comprise silicon-containing solubilizing side chains and their use as organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers and compounds according to the invention are used in organic field effect transistors, organic photovoltaics and photodiodes. |
| US09293713B2 |
Arylamine compound
An arylamine compound including: a partial structure shown in formula (1-1) or (1-2), wherein either X or Y is one of leaving substituents and the other is a hydrogen atom; either (X1, X2) or (Y1, Y2) is one of the leaving substituents respectively and the other is the hydrogen atom respectively; each of Q1, Q2, Q3, Q4, Q5, and Q6 is selected from the hydrogen atom, a halogen atom, organic substituents other than the leaving substituents, and an atomic bonding to link with an adjacent arylamine group respectively; and adjacent two substituents selected from Q1, Q2, Q3, Q4, Q5, and Q6 may be linked together to form the ring which may be a part of an arylamine group. |
| US09293710B2 |
Organic light-emitting diode
An organic light-emitting diode including a buffer layer including an amine-based compound. |
| US09293708B2 |
Regioregular pyridal[2,1,3]thiadiazole π-conjugated copolymers for organic semiconductors
A method of regioselectively preparing a pyridine-containing compound is provided. In particular embodiments, the method includes reacting halogen-functionalized pyridal[2,1,3]thiadiazole with organotin-functionalized cyclopenta[2,1-b:3,4-b′]dithiophene or organotin-functionalized indaceno[1,2-b:5,6-b′]dithiophene. Also provided is a method of preparing a polymer. The method includes regioselectively preparing a monomer that includes a pyridal[2,1,3]thiadiazole unit; and reacting the monomer to produce a polymer that includes a regioregular conjugated backbone section, wherein the section includes a repeat unit containing the pyridal[2,1,3]thiadiazole unit. A polymer that includes a regioregular conjugated backbone section, and electronic devices that include the polymer, are also provided. |
| US09293706B2 |
Method for encapsulating an organic light emitting diode
Methods for encapsulating OLED structures disposed on a substrate using a soft/polymer mask technique are provided. The soft/polymer mask technique can efficiently provide a simple and low cost OLED encapsulation method, as compared to convention hard mask patterning techniques. The soft/polymer mask technique can utilize a single polymer mask to complete the entire encapsulation process with low cost and without alignment issues present when using conventional metal masks. Rather than utilizing a soft/polymer mask, the encapsulation layers may be blanked deposited and then laser ablated such that no masks are utilized during the encapsulation process. |
| US09293704B2 |
Memory device and method of manufacturing memory device
According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel. |
| US09293700B2 |
Nonvolatile memory cell and nonvolatile memory device including the same
According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film. |
| US09293699B1 |
Method to make RF switches and circuits with phase-change materials
A radio frequency switch includes a first transmission line, a second transmission line, a first electrode electrically coupled to the first transmission line, a second electrode electrically coupled to the second transmission line, and a phase change material, the first transmission line coupled to a first area of the phase change material and the second transmission line coupled to a second area of the phase change material. When a direct current is sent from the first electrode to the second electrode through the phase change material, the phase change material changes state from a high resistance state to a low resistance state allowing transmission from the first transmission line to the second transmission line. The radio frequency switch is integrated on a substrate. |
| US09293698B2 |
Magnetoresistive structure having a metal oxide tunnel barrier and method of manufacturing same
In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material. |
| US09293697B2 |
Efficiently injecting spin-polarized current into semiconductors by interfacing crystalline ferromagnetic oxides directly on the semiconductor material
A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material. |
| US09293696B2 |
Magnetic memory and shift register memory
According to one embodiment, a magnetic memory includes a first magnetic unit, a first magnetic layer, a first recording/reproducing element, a first electrode, and a second electrode. The first magnetic unit extends in a first direction. The first magnetic unit includes a plurality of magnetic domains arranged in the first direction. The first magnetic unit has a columnar configuration having a hollow portion. The first magnetic layer is connected to a first end portion of the first magnetic unit, the first magnetic layer extends in a direction intersecting the first direction. The first recording/reproducing element is provided in contact with the first magnetic layer. The first electrode is electrically connected to the first magnetic layer. The second electrode is connected to a second end portion of the first magnetic unit on a side opposite to the first end portion. |
| US09293695B2 |
Magnetoresistive element and magnetic random access memory
According to one embodiment, a magnetoresistive element comprises a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, a second nonmagnetic layer, and a third magnetic layer. The first magnetic layer has a variable magnetization direction. The second magnetic layer has an invariable magnetization direction and includes a nonmagnetic material film and a magnetic material film. The first nonmagnetic layer is arranged between the first magnetic layer and the second magnetic layer. The second nonmagnetic layer is arranged on a surface of the second magnetic layer. The third magnetic layer is arranged on a surface of the second nonmagnetic layer. The second nonmagnetic layer is in contact with the nonmagnetic material film included in the second magnetic layer. |
| US09293694B2 |
Magnetoresistive random access memory cell with independently operating read and write components
A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack. Two detailed memory cells are proposed: in one proposed cell, the data storage layer is independent from but kept close to the sensing TMR stack, whose magnetization orientation affects magnetization configuration within the free layer of the TMR stack, therefor ultimately affects the output potential of the stack; in the other proposed cell, the perpendicular-anisotropy data storage layer is the free layer of the sensing TMR stack, whose magnetization state will directly affect the output potential of the stack when sensing current passes through. |
| US09293689B2 |
Method of manufacturing a piezoelectric micro energy harvester
A piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode. |
| US09293687B1 |
Passivation and alignment of piezoelectronic transistor piezoresistor
A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device. |
| US09293684B2 |
Electronic part comprising acoustic wave device
An electronic component has a mounting board having a mounting surface, a SAW device mounted on the mounting surface, and a sealing part covering the SAW device and filled between the SAW device and the mounting surface. The SAW device has an element substrate, an excitation electrode provided on a major surface of the element substrate and a cover covering the excitation electrode. SAW device is mounted on the mounting surface so as to make top surfaces of the cover face the mounting surface. The sealing part contains a resin and insulating fillers having a coefficient of thermal expansion lower than that of the resin. The content of the fillers differs between an area (for example AR1) including at least a portion of an area between the cover and the mounting surface and other areas (for example AR2 and AR3). |
| US09293681B2 |
Electrocaloric material
Provided is an electrocaloric material formed of a crystal represented by the composition formula Hf1-xAlxOy (where 0.071≦x≦0.091 and y≠0). |
| US09293675B2 |
Semiconductor light-emitting device and method of manufacturing the same
A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. |
| US09293674B2 |
Light emitting device including light emitting element, outer connection electrodes and resin layer
A semiconductor device has a light emitting element, and a resin layer; the light emitting element includes a semiconductor laminated body in which a first semiconductor layer and a second semiconductor layer are laminated in sequence, a second electrode connected to the second semiconductor layer on an upper surface of the second semiconductor layer that forms an upper surface of the semiconductor laminated body, and a first electrode connected to the first semiconductor layer on an upper surface of the first semiconductor layer in which a portion of the second semiconductor layer on one surface of the semiconductor laminated body is removed and a portion of the first semiconductor layer is exposed; and the resin layer is configured to cover at least a side surface of the light emitting element, and an upper surface of the resin layer is lower than the upper surface of the semiconductor laminated body. |
| US09293671B2 |
Optoelectronic component and method for producing an optoelectronic component
An optoelectronic component comprising an optoelectronic semiconductor chip (104) having a contact side (106) and a radiation coupling-out side (108) situated opposite; a chip carrier (102), on which the semiconductor chip (104) is applied via its contact side (106); a radiation conversion element (110) applied on the radiation coupling-out side (108); and a reflective potting compound (112), which is applied on the chip carrier (102) and laterally encloses the semiconductor chip (104) and the radiation conversion element (110); wherein the potting compound (112) adjoins an upper edge of the radiation conversion element (110) in a substantially flush fashion, such that a top side of the radiation conversion element (110) is free of the potting compound (112). |
| US09293666B2 |
Method of manufacturing light emitting device
There is provided a method of manufacturing a light emitting device which includes preparing a light emitting element emitting excitation light and a substrate on which the light emitting element is disposed. A fluoride phosphor is provided to absorb excitation light emitted from the light emitting element to emit visible light, and is represented by Chemical Formula (1). The fluoride phosphor is disposed on at least one of the light emitting element and the substrate, wherein Chemical Formula (1): AxMFy:Mn4+ (wherein 2≦x≦3 and 4≦y≦7, A is at least one element selected from the group consisting of Li, Na, K, Rb, and Cs, and M is at least one element selected from the group consisting Si, Ti, Zr, Hf, Ge, and Sn). |
| US09293661B2 |
Support for an optoelectronic semiconductor chip, and semiconductor chip
A support for an optoelectronic semiconductor chip includes a support body with a first main face and a second main face opposite the first main face, at least one electrical plated-through hole extending from the first main face to the second main face and formed in the support body, and an insulating layer arranged on the first main face, the insulation layer covering the electrical plated-through hole only in regions. |
| US09293652B2 |
Optoelectronic semiconductor chip having reduced strain between different constituent materials of the chip
An optoelectronic semiconductor chip includes a semiconductor layer stack including a nitride compound semiconductor material on a carrier substrate, wherein the semiconductor layer stack includes an active layer that emits an electromagnetic radiation, the semiconductor layer stack being arranged between a layer of a first conductivity and a layer of a second conductivity, the layer of the first conductivity is adjacent a front of the semiconductor layer stack, the layer of the first conductivity electrically connects to a first electrical connection layer covering at least a portion of a back of the semiconductor layer stack, and the layer of the second conductivity type electrically connects to a second electrical connection layer arranged at the back. |
| US09293650B2 |
Light output device having an array of cavities with different refractive index within the encapsulation layer
A light output device and manufacturing method in which an array of LEDs (34) is embedded in an encapsulation layer (32). An array of cavities (30) (or regions of different refractive index) is formed in the encapsulation layer (32). The cavities/regions (30) have a density or size that is dependent on their proximity to the light emitting diode (34) locations, in order to reduce hot spots (local high light intensity areas) and thereby render the light output more uniform over the area of the device. |
| US09293646B2 |
Method of manufacture for nitride semiconductor light emitting element, wafer, and nitride semiconductor light emitting element
In a method of manufacture for a nitride semiconductor light emitting element including: a monocrystalline substrate; and an AlN layer; and a first nitride semiconductor layer of a first electrical conductivity type; and a light emitting layer made of an AlGaN-based material; and a second nitride semiconductor layer of a second electrical conductivity type, a step of forming the AlN layer includes: a first step of supplying an Al source gas and a N source gas into the reactor to generate a group of AlN crystal nuclei having Al-polarity to be a part of the AlN layer on the surface of the monocrystalline substrate; and a second step of supplying the Al source gas and the N source gas into the reactor to form the AlN layer, after the first step. |
| US09293640B2 |
Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip
In at least one embodiment, the method is designed to produce an optoelectronic semiconductor chip. The method includes at least the following steps in the stated sequence: A) providing a growth substrate with a growth side, B) depositing at least one nucleation layer based on AlxGa1-xOyN1-y on the growth side, C) depositing and structuring a masking layer, D) optionally growing a GaN-based seed layer in regions on the nucleation layer not covered by the masking layer, E) partially removing the nucleation layer and/or the seed layer in regions not covered by the masking layer or applying a second masking layer on the nucleation layer or on the seed layer in the regions not covered by the masking layer, and F) growing an AlInGaN-based semiconductor layer sequence with at least one active layer. |
| US09293638B2 |
Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system can include a driver and at least one SST module electrically coupled to the driver. Each SST module can include an SST and a sense resistor. The sense resistors of each SST module can have at least substantially similar resistance values. The SSTs of the SST modules can be coupled in parallel across an SST channel to the driver, and the sense resistors of the SST modules can be coupled in parallel across a sense channel to the driver. The driver can be configured to measure a sense resistance across the sense resistors and deliver a current across the SSTs based on the sense resistance. |
| US09293637B2 |
Light emitting element and display device including a light-emitting region having ridge stripe structures
A light-emitting element includes a light-emitting region which is made from a stacked structure configured from a first compound semiconductor layer, an active layer, and a second compound semiconductor layer, and a light propagation region which is made from the stacked structure, extends from the light-emitting region, and has a light-emitting end surface. The light-emitting region is configured from a ridge stripe structure and ridge stripe adjacent portions positioned at both sides of the ridge stripe structure, and when a thickness of the second compound semiconductor layer in the ridge stripe adjacent portions is set to d1, a thickness of the second compound semiconductor layer in the light propagation region is set to d2, and a thickness of the second compound semiconductor layer in the ridge stripe structure is set to d3, d3>d2>d1 is satisfied. |
| US09293635B2 |
Back junction back contact solar cell module and method of manufacturing the same
The present invention relates to cost effective production methods of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections. |
| US09293633B2 |
Cover for protecting solar cells during fabrication
A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed. |
| US09293629B2 |
Optoelectronic component and method for operating an optoelectronic component
An optoelectronic component includes a carrier on which at least one first light-emitting semiconductor chip and one first light-absorbing semiconductor chip connected antiparallel to the at least one first light-emitting semiconductor chip, at least one second light-emitting semiconductor chip and one second light-absorbing semiconductor chip connected antiparallel to the at least one second light-emitting semiconductor chip, wherein the semiconductor chips are arranged on the carrier such that light from each light-emitting semiconductor chip falls on at least one of the light-absorbing semiconductor chips not connected to the respective light-emitting semiconductor chip, and the light-absorbing semiconductor chips are formed as protection diodes. |
| US09293627B1 |
Sub-wavelength antenna enhanced bilayer graphene tunable photodetector
The integration of bilayer graphene with an absorption enhancing sub-wavelength antenna provides an infrared photodetector capable of real-time spectral tuning without filters at nanosecond timescales. |
| US09293624B2 |
Methods for electroless plating of a solar cell metallization layer
A method for forming a contact region for a solar cell is disclosed. The method includes depositing a paste composed of a first metal above a substrate of the solar cell, curing the paste to form a first metal layer, electrolessly plating a second metal layer on the first metal layer and electrolytically plating a third metal layer on the second metal layer, where the second metal layer electrically couples the first metal layer to the third metal layer. The method can further include electrolytically plating a fourth metal layer on the third metal layer. |
| US09293621B2 |
System for generating photovoltaic power
The present invention relates to a system for generating photovoltaic power. The system for generating photovoltaic power is characterized by including: a light collection part shaped like a dome bulged outward and having a light condenser lens unit for condensing incident light rays; a light diffusion part having a light diffusion lens unit for diffusing the light rays collected by the light collection part; and a solar panel for receiving the light rays diffused by the light diffusion part. |
| US09293617B2 |
Copolymer of phase change material for thermal management of PV modules
The present invention relates to phase change materials (PCMs) which may be used with photovoltaic (PV) modules. More specifically, solid/solid PCMs having a polyolefin backbone polymer and a crystallizable side chain are provided. Preferably, the solid/solid PCM has a copolymer backbone having a polyolefin repeating unit, and the crystallizable side chains are grafted onto the copolymer backbone. Most preferably, the copolymer is poly(ethylene-co-glycidyl methacrylate) (PE-co-GMA), and polyethylene glycol (PEG) is the crystallizable side chain. Photovoltaic modules and backsheets for photovoltaic modules having solid/solid PCMs are also provided. |
| US09293615B2 |
Low-bandgap, monolithic, multi-bandgap, optoelectronic devices
Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments. |
| US09293613B2 |
Method for preparing CIS compounds and thin layer, and solar cell having CIS compound thin layer
A method for preparing a CIS (Cu—In—Se) compound includes (S1) producing a plurality of first composite particles having an indium selenide outer layer physically coupled to at least a part of a copper selenide seed particle surface or a plurality of second composite particles having a copper selenide outer layer physically coupled to at least a part of an indium selenide seed particle surface; and (S2) making a CIS compound by thermally treating composite particles selected from the group consisting of the first composite particles, the second composite particles and their mixtures. This method may prevent loss of selenium, which inevitably requires selenium environment, and also improves dispersion, coupling and reaction uniformity for the formation of a CIS compound. |
| US09293610B2 |
Easy-adhesive for solar cell rear surface protection sheet, solar cell rear surface protection sheet, and solar cell module
To overcome a problem in related art and to provide an easy-adhesive having an excellent adhesive property and an excellent adhesive durability for a solar cell rear surface protection sheet, a solar cell rear surface protection sheet, and a solar cell module formed by using the solar cell rear surface protection sheet. An easy-adhesive for a solar cell rear surface protection sheet according to the present invention exhibits a specific glass transition temperature, a specific number average molecular weight, and a specific hydroxyl value. Further, the easy-adhesive for a solar cell rear surface protection sheet contains a (meth)acrylic-based copolymer (A) that contains a carbon-carbon double bond in a side chain at a specific rate, and a polyisocyanate compound (B) at a specific rate. |
| US09293606B2 |
Semiconductor device with seal ring with embedded decoupling capacitor
A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss. |
| US09293600B2 |
Semiconductor element, display device, method for manufacturing semiconductor element, and method for manufacturing display device
A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion. |
| US09293597B2 |
Oxide semiconductor device
Disclosed is a technique for suppressing fluctuation of device characteristics in thin film transistors using an oxide semiconductor film as a channel layer. In a thin film transistor using an oxide semiconductor film as a channel layer (4), said channel layer (4) is configured from an oxide semiconductor having as main materials a zinc oxide and tin oxide with introduced group IV elements or group V elements, wherein the ratio (A/B) of the impurity concentration (A) of the group IV elements or group V elements contained in the channel layer (4) and the impurity concentration (B) of the group III elements contained in the channel layer (4) satisfies A/B≦1.0, and ideally A/B≦0.3. |
| US09293595B2 |
Semiconductor device and manufacturing method thereof
A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask. |
| US09293593B2 |
Self aligned device with enhanced stress and methods of manufacture
A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer. |
| US09293591B2 |
Tunnel field effect transistor (TFET) with lateral oxidation
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials. |
| US09293590B2 |
Semiconductor device
A semiconductor device of stable electrical characteristics, whose oxygen vacancies in a metal oxide is reduced, is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a first metal oxide film over the gate insulating film, a source electrode and a drain electrode which are in contact with the first metal oxide film, and a passivation film over the source electrode and the drain electrode. A first insulating film, a second metal oxide film, and a second insulating film are stacked sequentially in the passivation film. |
| US09293589B2 |
Semiconductor device and method for manufacturing semiconductor device
A highly reliable semiconductor device including a transistor using an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a first insulating layer is formed in contact with the oxide semiconductor layer, and an oxygen doping treatment is performed thereon, whereby the first insulating layer is made to contain oxygen in excess of the stoichiometric composition. The formation of the second insulating layer over the first insulating layer enables excess oxygen included in the first insulating layer to be supplied efficiently to the oxide semiconductor layer. Accordingly, the highly reliable semiconductor device with stable electric characteristics can be provided. |
| US09293582B2 |
Hybrid fin field-effect transistor structures and related methods
Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. |
| US09293580B2 |
Lightly doped source/drain last method for dual-epi integration
An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. |
| US09293579B2 |
Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. |
| US09293574B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers of n-type above the second nitride semiconductor layer and located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode above one of the two third nitride semiconductor layers and a second ohmic electrode above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer. The second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including p-type impurities identical to those in the p-type nitride semiconductor layer. |
| US09293569B2 |
Bipolar transistor
A bipolar junction transistor is provided with an emitter region, an oxide region, a base region and a collector region. The base region is located between the emitter region and the oxide region and has a junction with the emitter region and an interface with the oxide region. An at least partially conductive element such as metal or silicon is positioned to overlap with at least part of the junction between the base region and the emitter region, thereby forming a gate. The gate also overlaps with at least part of the interface between the base region and the oxide region. When a suitable bias voltage is applied to the gate, the gain of the transistor can be increased. |
| US09293564B2 |
Semiconductor device manufacturing method
A method of manufacturing a semiconductor device includes forming a first parallel pn layer; depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a step that further includes forming a second parallel pn layer by selectively introducing second-conductivity-type impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed in a depth direction to regions of the first parallel pn layer in which second-conductivity-type semiconductor regions are formed; and forming a local insulating film on a surface of the first semiconductor layer in a termination structure portion so that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity regions. The method may further include diffusing the first second conductivity type impurity regions in a second heat treatment. |
| US09293553B2 |
Graphene electrodes for electronic devices
A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such as solar cells, can be constructed using graphene as the cathode material. |
| US09293551B2 |
Integrated multiple gate length semiconductor device including self-aligned contacts
A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer. |
| US09293548B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode. |
| US09293547B2 |
NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps
According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode. |
| US09293546B2 |
Vertical tunneling negative differential resistance devices
The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry. |
| US09293545B2 |
Semiconductor device
A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased. |
| US09293542B2 |
Methods of forming semiconductor devices and FinFETs
Methods of forming semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less. The method includes forming a group III-V material over the group III material. |
| US09293539B2 |
Nitride semiconductor epitaxial wafer and nitride semiconductor device
A nitride semiconductor epitaxial wafer includes a substrate, and a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including a (002) plane in an upper surface thereof. An in-plane dispersion of a full width half maximum (FWHM) of an X-ray rocking curve in the (002) plane or a (100) plane of the nitride semiconductor layer is not more than 30%. The wafer is not less than 100 μm in thickness and not less than 50 mm in diameter. |
| US09293538B2 |
Diode having trenches in a semiconductor region
An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. |
| US09293537B2 |
High performance strained source-drain structure and method of fabricating the same
A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour. |
| US09293534B2 |
Formation of dislocations in source and drain regions of FinFET devices
Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices. |
| US09293532B2 |
Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. |
| US09293531B2 |
Semiconductor component comprising micro-bridges for adjusting a tensile strain state and method for the production thereof
A tensile strain state in semiconductor components is adjusted. A pretensioned (tensile strain) layer is applied to a substrate (FIG. 1, (A)). Bridge structures (FIG. 1, (B)) are introduced in the layers by lithography and etching. The bridges are connected to the layer on both sides and are thus continuous. The geometric shape of the bridges, formed with a cross-section modulation, is determined by the windows (FIG. 1 (C)) in the layer. When the substrate is etched selectively, the bridge is undercut through the windows. The geometric structuring of the cross-section (FIG. 1, (D)) causes a redistribution of the originally homogeneous strain when the bridges are detached from the substrate, with the larger cross-sections relaxing at the expense of the smaller cross-sections, where the pretension is increased. Only a multiplication of stresses (or strain) originally present in the sample is possible, with the multiplication factor determined by lengths, widths and depths, and/or the relationships thereof. |
| US09293529B2 |
Semiconductor device with an array of lamellas and a micro-electro-mechanical resonator
A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide. |
| US09293528B2 |
Field-effect semiconductor device and manufacturing therefor
A power semiconductor device includes a semiconductor body having a first surface and including an active area including n-type semiconductor regions and p-type semiconductor regions, the n-type semiconductor regions alternating, in a direction substantially parallel to the first surface, with the p-type semiconductor regions. The semiconductor body further includes a peripheral area surrounding the active area and including a low-doped semiconductor region having a first concentration of n-dopants lower than a doping concentration of n-dopants of the n-type semiconductor regions, and at least one auxiliary semiconductor region having a concentration of n-dopants higher than the first concentration and a concentration of p-dopants higher than the first concentration. |
| US09293525B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion. |
| US09293524B2 |
Semiconductor device with a field ring edge termination structure and a separation trench arranged between different field rings
A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region. |
| US09293523B2 |
Method of forming III-V channel
Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap. |
| US09293522B2 |
Method of manufacturing capacitor and display apparatus including the same
Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks. |
| US09293518B2 |
Thin film transistor, and organic light-emitting display device therewith
A thin film transistor includes a gate electrode on a substrate, the gate electrode including a wire grid pattern, an active layer on the substrate, a gate insulating film between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer. |
| US09293515B2 |
Organic light-emitting display device and method of manufacturing the same
An organic light-emitting display device and a method of manufacturing the organic light-emitting display device. The organic light-emitting display device is a dual emission display capable of displaying differing images on either side of the display, and includes a facing electrode that is selectively deposited in the first area but not in the second area, the selectivity being brought about by a varying an underlying material having differing adhesive forces with the material of the facing electrode. In addition, the underlying materials of the facing electrode and other intermediate layers of the organic light emitting diode device provide extra distance between the organic light emitting layer and a reflective electrode, so that exciton quenching is reduced, resulting in improved light emitting efficiency. |
| US09293514B2 |
Organic light emitting diode display
An organic light emitting diode (OLED) display includes a scan line, a data line, a driving voltage line, a switching transistor, a driving transistor and an OLED. The scan line is formed on a substrate to transmit a scan signal. The data line and the driving voltage line, intersecting the scan line, transmit a data signal and a driving voltage, respectively. The switching transistor, electrically coupled to the scan line and the data line, includes a switching semiconductor layer, a switching gate electrode, and a gate insulating layer having a first thickness. The driving transistor, electrically coupled to the switching drain electrode, includes a driving semiconductor layer, a driving gate electrode and a gate insulating layer having a second thickness. The OLED is electrically coupled to the driving drain electrode. The data line and the driving voltage line are formed with different layers from each other. |
| US09293512B2 |
Device and method for improving AMOLED driving
Devices and methods for increasing the aperture ratio and providing more precise gray level control to pixels in an active matrix organic light emitting diode (AMOLED) display are provided. By way of example, one embodiment includes disposing a gate insulator between a gate of a driving thin-film transistor and a gate of a circuit thin-film transistor. The improved structure of the display facilitates a higher voltage range for controlling the gray level of the pixels, and may increase the aperture ratio of the pixels. |
| US09293511B2 |
Methods for achieving improved color in microencapsulated electrophoretic devices
A method for manufacturing a full color, reflective display includes the steps of depositing a first plurality of electrophoretic display elements in substantial registration with a first electrode and a second plurality of electrophoretic display elements in substantial registration with a second electrode. The electrophoretic display elements include a capsule containing a species of particles dispersed in a suspending fluid. The selective deposition of the display elements can be achieved by ink-jet printing methods, screen printing methods or other printing methods. In some embodiments the electrodes are printed onto the substrate before selective deposition of the display elements, while in other embodiments the substrate is provided having the electrodes already disposed on it. In still other embodiments, the sequence of printing of electrodes and electrophoretic display elements can be varied. |
| US09293509B2 |
Small-grain three-dimensional memory
The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor. |
| US09293507B2 |
Electronic device and method for fabricating the same
An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate. |
| US09293506B2 |
Detection apparatus, detection system, and method for manufacturing detection apparatus
A detection apparatus includes a plurality of pixels and a plurality of signal wires arranged on a substrate, in which each of the plurality of pixels includes a switch element arranged on the substrate and a conversion element arranged on the switch element, the conversion element includes a first electrode which is arranged on the switch element and electrically connected to the switch element and a semiconductor layer arranged over a plurality of the first electrodes, and a plurality of the switch elements is electrically connected to the plurality of signal wires, and the detection apparatus further includes a constant potential wire which is supplied with a constant potential, in which the first electrode is electrically connected to the constant potential wire in apart of pixels among the plurality of pixels. |
| US09293505B2 |
System and method for black coating of camera cubes at wafer level
A method for black coating camera cubes at wafer level includes expanding the gap between individual diced camera cubes of the wafer by stretching tape securing the diced camera cubes. The method includes applying a black coating layer to the stretched camera cubes, laser trimming undesired portions of the black coating layer, and removing the undesired portions of the black coating layer. |
| US09293503B2 |
Solid-state imaging device, method for driving the same, method for manufacturing the same, and electronic device
A solid-state imaging device includes a photoelectric conversion section configured to generate photocharges and a transfer gate that transfers the photocharges to a semiconductor region. A method for driving a unit pixel includes a step of accumulating photocharges in a photoelectric conversion section and a step of accumulating the photocharges in a semiconductor region. A method of forming a solid-state imaging device includes implanting ions into a well layer through an opening in a mask, implanting additional ions into the well layer through an opening in another mask, and implanting other ions into the well layer through an opening in yet another mask. An electronic device includes the solid-state imaging device. |
| US09293499B2 |
Semiconductor light detecting element having silicon substrate and conductor
A semiconductor light detecting element is provided with a silicon substrate having a semiconductor layer, and an epitaxial semiconductor layer grown on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and conductors provided on a surface of the epitaxial semiconductor layer. A photosensitive region is formed in the epitaxial semiconductor layer. Irregular asperity is formed at least in a surface opposed to the photosensitive region in the semiconductor layer. The irregular asperity is optically exposed. |
| US09293498B2 |
Solid-state imaging element and electronic device
The present disclosure relates to a solid-state imaging element and an electronic device capable of suppressing occurrence of a dark current and acquiring higher image quality.The solid-state imaging element includes a high-concentration diffusion layer configured to serve as a connection portion by which a wiring is connected to a semiconductor substrate, and a junction leak control film formed to cover a surface of the diffusion layer. Also, to connect the wiring to the diffusion layer, a width of an opening formed in an insulation film stacked on the semiconductor substrate is greater than a width of the diffusion layer. Further, in a charge accumulation portion configured to accumulate a charge generated by a photoelectric conversion portion generating the charge according to an amount of received light, the junction leak control film is also used as a capacitor film of the charge accumulation portion. Furthermore, a stack structure in which a silicon oxide or low interface state oxide film is formed is included between the diffusion layer and the junction leak control film. The present technology can be applied to, for example, a CMOS image sensor. |
| US09293491B2 |
Polarization image sensor and endoscope
A polarization image sensor includes: photodiodes arranged on an image capturing plane; a color mosaic filter in which color filters in multiple different colors are arranged to face the photodiodes; an optical low-pass filter which covers the color mosaic filter; and polarization optical elements located closer to a light source than the optical low-pass filter is. Each polarization optical element covers an associated one of the photodiodes and makes light which is polarized in a predetermined direction in a plane that is parallel to the image capturing plane incident onto the optical low-pass filter. The color filters are arranged so that light that has passed through polarization optical elements is transmitted through an associated one of the color filters in a single color. Each color filter covers multiple photodiodes. |
| US09293490B2 |
Deep trench isolation with air-gap in backside illumination image sensor chips
An integrated circuit structure includes a semiconductor substrate, an image sensor extending from a front surface of the semiconductor substrate into the semiconductor substrate, and an isolation structure extending from a back surface of the semiconductor substrate into the semiconductor substrate, wherein the isolation structure includes an air-gap therein. An air-gap sealing layer is on a backside of the semiconductor substrate. The air-gap sealing layer seals the air-gap, wherein the air-gap sealing layer includes a portion exposed to the air-gap. |
| US09293481B2 |
Array substrate, and dual view field display device and manufacturing method thereof
An array substrate, and a dual view field display device and a manufacturing method thereof are disclosed. The array substrate includes: a plurality of pixel units defined by gate lines and data lines which intersect each other, each of the pixel units including a pixel electrode and a TFT circuit; the pixel electrode of each of the pixel units comprises at least two first pixel electrodes and at least two second pixel electrodes, which are spaced from each other; the TFT circuit of each of the pixel units comprises a first sub-TFT circuit connected to the first pixel electrodes and a second sub-TFT circuit connected to the second pixel electrodes. According to the above array substrate, a dual view barrier can be produced within the display device, and the production costs can be reduced. |
| US09293475B2 |
Display device and method of manufacturing the same
A display device includes a substrate including a first region and a second region, a gate line and a data line on the substrate, a thin film transistor on the substrate, being connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, wherein the second region has a second contact hole of which an area is larger than that of a first contact hole of the first region. |
| US09293474B2 |
Dual channel hybrid semiconductor-on-insulator semiconductor devices
Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. |
| US09293471B1 |
Semiconductor apparatus and manufacturing method of the same
A semiconductor apparatus including a first stacked structure and a second stacked structure is provided. The first stacked structure and the second stacked structure are arranged along a first direction, and extended along a second direction perpendicular to the first direction. The first stacked structure includes a first operating portion and a first supporting portion. The first operating portion and the first supporting portion are alternately arranged along the second direction. A width of the first operating portion along the first direction is smaller than a width of the first supporting portion along the first direction. |
| US09293469B2 |
Flash memory and fabrication method thereof
A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance. |
| US09293467B2 |
Reconfigurable tunnel field-effect transistors
A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region. |
| US09293462B2 |
Integrated circuits with dual silicide contacts and methods for fabricating same
Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions. |
| US09293461B2 |
Replacement metal gate structures for effective work function control
A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. |
| US09293460B2 |
ESD protection device with improved bipolar gain using cutout in the body well
An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor. |
| US09293455B2 |
Semiconductor device and manufacturing method thereof
Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer. |
| US09293452B1 |
ESD transistor and a method to design the ESD transistor
An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges. |
| US09293451B2 |
Integrated circuit electrical protection device
An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions. |
| US09293446B2 |
Low profile semiconductor module with metal film support
A low profile module is provided that has a high functionality achieved by increasing the component mounting density. In spite of achieving high functionality in a module 100 by respectively mounting components such as a semiconductor substrate 104 and chip components 105 on the two main surfaces 101a and 101b of a wiring substrate 101, the low-profile module 100 can be provided which has a high functionality as a result of increasing its component mounting density by forming a thickness Ha of a first component layer 102 formed by mounting only the semiconductor substrate 104 face down on one main surface 101a of the wiring substrate 101 so as to be smaller than the thickness of a second component layer 103 formed by mounting a plurality of chip components 105 on the other main surface 101b of the wiring substrate 101. |
| US09293444B2 |
Co-support for XFD packaging
A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. |
| US09293443B2 |
Chip stack packages, methods of fabricating the same, electronic systems including the same and memory cards including the same
A chip stack package includes a first chip disposed over a substrate, a second chip disposed over the first chip and having an overhang, and a first supporter attached to a bottom surface of the overhang of the second chip and a sidewall of the first chip. The overhang of the second chip protrudes from the sidewall of the first chip. |
| US09293442B2 |
Semiconductor package and method
A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package. |
| US09293441B2 |
Semiconductor device and method of manufacturing the same
The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device. |
| US09293436B2 |
Bonding wire to bonding pad
A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured. |
| US09293435B2 |
Semiconductor device and production method therefor
A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. |
| US09293434B2 |
Electronic device mounted on a substrate
A device includes: a substrate; and a functional element mounted, the functional element including electrodes. The substrate includes a support substrate, and includes a first seed metal, a second seed metal, and a resin component on the support substrate, the first seed metal being disposed in a section opposed to part or all of a first electrode among the electrodes, and being connected to the first electrode by plating, the second seed metal being disposed in a section opposed to part or all of a second electrode among the electrodes, and being connected to the second electrode by plating, and the resin component being disposed in a layer between the functional element and the support substrate, and fixing the functional element to the support substrate, and being provided avoiding a neighborhood of an end of the functional element among opposed side sections of the first and second seed metals. |
| US09293432B2 |
Metal contact for chip packaging structure
A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging. |
| US09293431B2 |
Integrated semiconductor device and wafer level method of fabricating the same
The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. |
| US09293429B2 |
Electronic chip comprising connection pillars and manufacturing method
An electronic chip including a semiconductor substrate (1) covered with an insulating layer (4) including metal interconnection levels (3) and interconnection pillars (10) connected to said metal interconnection levels (3), said pillars (110) forming regions (111) protruding from the upper surface of said insulating layer (4) and capable of forming an electric contact, wherein said pillars (110) have a built-in portion (115) in a housing formed across the thickness of at least said insulating layer (4). |
| US09293423B2 |
Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. |
| US09293422B1 |
Optoelectronic packages having magnetic field cancelation
A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ≧1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die. |
| US09293421B2 |
Electronic component module
An electronic component module according to the present invention is provided with an electronic component, a sealing resin that seals the electronic component, and a metal film that covers a surface of the sealing resin. The sealing resin contains filler of oxide particles. Part of the filler in the sealing resin is exposed to the surface of the sealing resin. At least the part of the filler exposed to the surface of the sealing resin includes a crack that extends from an exposed surface of the filler into an inner portion. The crack is filled with at least one metal that constitutes the metal film. |
| US09293419B2 |
Semiconductor package and semiconductor device
A semiconductor package includes a first substrate including a first surface layer where a first pad region and a second pad region are formed, the first pad region including a plurality of first pads for connection to a first IC, the second pad region including a plurality of second pads for connection to a second substrate, and a second surface layer where a third pad region including a plurality of third pads for connection to a second IC is formed, the second surface layer being formed on an opposite side of the first surface layer. The second pads surround the first pad region in at least three rows, and one or more pads included in the second pads and arranged in an inner portion are connected to one or more pads included in the first pads and to one or more pads included in the third pads. |
| US09293414B2 |
Electronic fuse having a substantially uniform thermal profile
An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias. |
| US09293411B2 |
Semiconductor device and manufacturing method of the same
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers. |
| US09293410B2 |
Semiconductor device
A semiconductor device includes a lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer sequentially stacked on a substrate. First and second lower conductive layers, which are laterally separated from each other, are provided in the lower interlayer insulating layer. First and second upper via plugs are connected to the first and second lower conductive layers, respectively, through the upper interlayer insulating layer and the first stopper layer. Further, between the first and second upper via plugs, at least one line-shaped shield via plug extends into the lower interlayer insulating layer through the first stopper layer. The shield via plug is in an electrically-floating state. |
| US09293409B2 |
Method for manufacturing a semiconductor device, and semiconductor device
According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage. |
| US09293405B2 |
Semiconductor device
A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced. |
| US09293399B2 |
Semiconductor device and electronic unit provided with the same
A semiconductor device includes first and semiconductor elements, an electroconductive support member including electroconductive elements, and a resin package. The first semiconductor element includes a first active surface and first electrodes formed on the first active surface. The second semiconductor element includes a second active surface and second electrodes formed on the second active surface. The electroconductive support member is electrically connected to the first and second semiconductor elements and support these elements. The resin package covers the first and second semiconductor elements. The second semiconductor element is located between the first semiconductor element and the electroconductive support member. The first electrodes of the first semiconductor element and the electroconductive elements are connected by wire. An electroconductive bonding material is also provided that bonds the second electrodes of the second semiconductor element and the electroconductive elements to which the wire is bonded. |
| US09293397B1 |
Power device and preparation method thereof
A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second pin, a first conductive structure connecting a second electrode at the top surface of a first semiconductor chip to a first pin, and a second conductive structure connecting a second electrode at the top surface of the second semiconductor chip to a third pin. In examples of the present disclosure, double-chip common source technique for the source electrodes of two power MOSFETs is achieved by applying a T-shape metal clip. |
| US09293396B2 |
Method for manufacturing semiconductor device, and semiconductor device
A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire. |
| US09293392B2 |
3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. |
| US09293390B2 |
Heat radiation structure for semiconductor device
A semiconductor device with improved heat radiation and improved insulation performance. The semiconductor device includes a semiconductor element, a lead frame bonded on one surface to the semiconductor element, a first insulating layer disposed on the other surface of the lead frame, and a metal base plate connected to the lead frame with the first insulating layer interposed between them, wherein an outer peripheral portion of the first insulating layer is inside an outer peripheral portion of the metal base plate, and the outer peripheral portion of the first insulating layer is covered with a second insulating layer having higher moisture resistance and higher insulation performance than the first insulating layer, the outer peripheral portion including an electric field concentrated point in an outer peripheral portion of the lead frame. |
| US09293385B2 |
RDL patterning with package on package system
An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation. |
| US09293384B2 |
Silicon nitride substrate, circuit substrate and electronic device using the same
A silicon nitride substrate comprises a substrate comprising a silicon nitride sintered body, and a plurality of granular bodies containing silicon and integrated to a principal surface of the substrate, wherein a plurality of needle crystals or column crystals comprising mainly silicon nitride are extended from a portion of the granular bodies. A brazing material is applied to a principal surface of the substrate, and a circuit member and a heat radiation member are arranged on the applied brazing material, and bonded by heating. Because of a plurality of granular bodies integrated to the principal surface of the substrate, and a plurality of the needle crystals or the column crystals extended from a portion of the granular bodies, a high anchor effect is produced so that the circuit member and the heat radiation member are firmly bonded to the silicon nitride substrate. |
| US09293376B2 |
Apparatus and method for power MOS transistor
A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region. |
| US09293373B1 |
Method for fabricating CMOS finFETs with dual channel material
A method of forming dual channel FinFETs is provided. Spaced apart first semiconductor material fins are provided in first and second device regions. A second semiconductor material fin having a lattice constant that differs from the first semiconductor material is formed in a gap located between each first semiconductor material fin and in the first and second device regions. A sacrificial structure is formed on each of the semiconductor material fins and in the first and second device regions. The sacrificial structure and each second semiconductor material fin are selectively removed from the first device region to provide a first gate cavity. A first gate structure is formed in the first gate cavity. The sacrificial structure and each first semiconductor material fin are selectively removed from the second device region to provide a second gate cavity. A second gate structure is formed in the second gate cavity. |
| US09293372B2 |
Wafer processing method
A wafer has a substrate, a functional layer and division lines. The wafer is held on a chuck table with a protective member attached to the front side of the functional layer in contact with the chuck table. The height of the back side of the wafer is detected in a Z direction along each division line while moving the chuck table in an X direction. An X coordinate is recorded for each division line, as well as a corresponding Z coordinate. A cutting blade is positioned on the back side of the wafer and moved in the Z direction according to the recorded X and Z coordinates while moving the chuck table in the X direction to thereby form a cut groove having a depth not reaching the functional layer, with a part of the substrate left between the bottom of the cut groove and the functional layer. |
| US09293371B2 |
Method for processing a semiconductor workpiece with metallization
A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material. |
| US09293368B2 |
Method for removing electroplated metal facets and reusing a barrier layer without chemical mechanical polishing
A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer. |
| US09293360B2 |
Manufacturing method of semiconductor memory device with air gap isolation layers
A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer. |
| US09293359B2 |
Non-volatile memory cells with enhanced channel region effective width, and method of making same
A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches. |
| US09293352B2 |
Substrate processing method
In a substrate processing apparatus (1), a silicon oxide film on a main surface of a substrate (9) is removed in an oxide film removing part (4) and then a silylation material is applied to the main surface, to thereby perform a silylation process in a silylation part (6). It is thereby possible to lengthen the Q time from the removal of the silicon oxide film to the formation of the silicon germanium film and reduce the temperature for prebaking in the formation of the silicon germanium film. |
| US09293350B2 |
Semiconductor package system with cavity substrate and manufacturing method therefor
A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate. |
| US09293349B2 |
Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. |
| US09293346B2 |
Method for etching organic film and plasma etching device
In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and O2 gas is supplied to the processing chamber and a microwave for plasma excitation is supplied to the inside of the processing chamber to etch the organic film. |
| US09293341B2 |
Mechanisms for forming patterns using multiple lithography processes
The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer. |
| US09293340B2 |
Surface planarization method of thin film and preparing method of array substrate
A surface planarization method of thin film and a preparing method of an array substrate relate to a display field, and can solve the technical problem that the conventional dry etching severely damages the surface flatness of other film layers below the one being etched, thereby improving the display properties of the LCD. The preparing method of the array substrate comprises patterning a non-metallic layer (4) by a dry etching. And following the step of patterning a non-metallic layer (4) by the dry etching, the method further comprises performing surface planarization on a first film layer (3) to recover the first film layer (3) with a rough surface caused by the dry etching to be planar. The first film layer (3) is located below the non-metallic layer (4). |
| US09293339B1 |
Method of polishing semiconductor substrate
A process for chemical mechanical polishing of a substrate having an exposed silicon dioxide feature is provided comprising: providing a chemical mechanical polishing composition, containing, as initial components: water, a colloidal silica abrasive and a zirconyl compound; wherein a pH of the chemical mechanical polishing composition is ≦6; providing a chemical mechanical polishing pad with a polishing surface; dispensing the chemical mechanical polishing composition onto the polishing surface of the chemical mechanical polishing pad in proximity to an interface between the chemical mechanical polishing pad and the substrate; and, creating dynamic contact at the interface between the chemical mechanical polishing pad and the substrate; wherein the substrate is polished. |
| US09293338B2 |
Semiconductor packaging structure and method
A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals. |
| US09293337B2 |
Semiconductor device and method for fabricating the same
A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment. |
| US09293335B2 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. |
| US09293334B2 |
N metal for FinFET and methods of forming
An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer. |
| US09293328B2 |
Semiconductor device structures comprising a polymer bonded to a base material and methods of fabrication
Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures. |
| US09293322B2 |
Optimized method for fabricating patterns of III-V semiconductor material on a semiconductor substrate
A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miox of width L, of height hox with a distance S between masking patterns; growth of patterns MiIII-V of III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height hc, the growth step comprising: determining growth rates v100 and v110 at right angles to the face of the III-V material, defining ratio R=v100/v110; determining the angle of dislocations θ of the III-V material relative to the plane of the substrate; determining the critical minimum height hc by the equation: h c = h ox - S × tan ( θ ) tan ( θ ) R - 1 with R being determined to be greater than tan(θ). |
| US09293319B2 |
Removal of metal
Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent. |
| US09293312B2 |
Identifying the occurrence and location of charging in the ion path of a mass spectrometer
A method is described for identifying the occurrence and location of charging of ion optic devices arranged along the ion path of a mass spectrometer. The method includes repeatedly performing a sequence of introducing a beam of discharge ions to a location on the ion path, and subsequently measuring the intensities of opposite-polarity sample ions delivered to a mass analyzer, with the discharge ions being delivered to a location further downstream in the ion path at each successive sequence. |
| US09293306B2 |
Methods of manufacturing large-area sputtering targets using interlocking joints
In various embodiments, joined sputtering targets are formed at least in part by spray deposition of the sputtering material and/or welding. |
| US09293302B2 |
Method for processing a gas and a device for performing the method
A method and device for processing a gas by forming microwave plasmas of the gas. The gas that is to be processed is set in a two or three co-axial vortex flow inside the device and exposed to a microwave field to form the plasma in the inner co-axial vortex flow, which subsequently is expelled as a plasma afterglow through an outlet of the device. |
| US09293298B2 |
Defect discovery and inspection sensitivity optimization using automated classification of corresponding electron beam images
Various embodiments for classifying defects detected on a wafer are provided. One method includes acquiring an electron beam image generated by a defect review tool for a location of a defect detected on a wafer by a wafer inspection tool. The method also includes determining a classification of the defect based on at least the electron beam image and without input from a user. The method may also include feeding back the classification results to the wafer inspection tool and optimizing the parameters of the tool to maximize sensitivity to the defects of interest. |
| US09293297B2 |
Correlative optical and charged particle microscope
A Correlative Light and Electron Microscope (CLEM) is equipped with a TEM column and a light microscope fitted between the pole shoes of the objective lens of the TEM. To enlarge the acceptance solid angle for enhanced sensitivity a truncated lens is used. It is noted that this does not imply that the lens shows astigmatism (it is not a cylindrical lens).Using the light microscope, a first image is made with the sample in a first direction. This image will show in one direction a higher (diffraction limited) resolution than in the direction perpendicular thereto, due to the different NA of the lens in the two directions. By rotating the sample and making a second image, a combined image can be formed showing a better resolution than either of the images in the direction where they show a low NA. |
| US09293295B2 |
Ion implantation apparatus, final energy filter, and ion implantation method
A final energy filter includes a first adjustment electrode portion, an intermediate electrode portion, and a second adjustment electrode portion. The final energy filter further includes a power supply unit. The power supply unit is configured such that it applies the voltages separately to the first adjustment electrode portion, the intermediate electrode portion, and the second adjustment electrode portion. The power supply unit applies voltages to an upstream auxiliary electrode portion, a deflection electrode portion and a downstream auxiliary electrode portion, respectively, such that the energy range of ion beam in a first region between the upstream auxiliary electrode portion and the deflection electrode portion is approximately equal to that in a second region between the deflection electrode portion and the downstream auxiliary electrode portion. |
| US09293293B2 |
Electron gun and charged particle beam device having an aperture with flare-suppressing coating
The objective of the present application is to suppress the occurrence of flares and to reduce the amount of secondary electrons arising at an aperture provided to the lead-out electrode of an electron gun. By coating a thin film having a low rate of secondary electron emission such as carbon onto the aperture of a lead-out electrode closest to an electron source in an electron gun, it is possible to reduce the amount of secondary electrons arising. Secondary electrons arising at the lead-out electrode, are reduced, and so as a result, flare is reduced. By incorporating two apertures to the lead-out electrode, and applying to the two apertures a potential that is equipotential to the lead-out electrode, it is possible to eliminate an electric field from seeping from under to over the lead-out electrode. Secondary electrons arising when an electron beam impacts the lead-out electrode cease to incur force in the direction of passage from the lead-out electrode, and consequently there is a reduction in flares. |
| US09293290B2 |
Spare-fuse holding structure
A spare-fuse holding structure holds a spare fuse including a pair of terminals exposed on both sides of a fuse resin main body serving as a resin main part of the spare fuse in a resin housing chamber. The spare-fuse holding structure includes a resin guide portion configured to guide, when the spare fuse is inserted into the resin housing chamber in a manner inclined with respect to the insertion direction, the spare fuse into the resin housing chamber while changing a posture of the spare fuse in the insertion direction by coming into contact with the fuse resin main body to prevent the pair of terminals from coming into contact with resin walls forming the resin housing chamber. |
| US09293287B2 |
Overcurrent relay and molded case circuit breaker with the same
An overcurrent relay and a molded case circuit breaker (MCCB) including the same are provided. The MCCB includes: a switching mechanism unit; an overcurrent relay; a trip mechanism, wherein the overcurrent relay includes: a case body; a case cover coupled to the case body; a control unit installed within the case body and having an electronic circuit board; and a plurality of setting knobs disposed to be spaced apart from one another on the electronic circuit board, having an indication unit exposed to the outside to indicate a current reference value and a trip operation time marked on the case cover, respectively, and configured to be rotatable, respectively. |
| US09293280B2 |
Mixture of hydrofluoroolefine and hydrofluorocarbide to improve the internal ARC resistance in medium and high voltage electric apparatus
The invention relates to the use of a mixture of a hydrofluoroolefin and a hydrofluorocarbon, optionally combined with another fluorinated gas, as an electrical insulation medium and/or an electric arc extinguishing medium in a medium-voltage electrical apparatus. The invention also relates to a medium- or high-voltage electrical apparatus in which such a mixture provides electrical insulation and/or electric arc extinguishing. |
| US09293273B2 |
Tap changer with vacuum interrupters
The invention relates to a tap changer having vacuum interrupters for switching over between winding taps of a tapped transformer without interruption. The tap changer according to the invention having vacuum interrupters is based on the general idea of combining the functionalities of at least one conventional vacuum switching contact which switches under load and a further mechanical switching means according to the prior art in just one single vacuum interrupter with two separately moving contact systems. |
| US09293272B1 |
Fuse to circuit breaker adapter
A circuit breaker adapter is disclosed for use in a fuse holder therein replacing a blade type fuse. The adapter includes a housing and a modified circuit breaker where pronged terminals are pivotally attached conductive articulable extensions. The housing is a contiguous block of material that receives the modified circuit breaker and gripping clips of the fuse holder. The housing has a center chute shaped section that holds the circuit breaker. In particular, the inside of the housing has a pair of accessible open cavities to receive the extensions similar to many fuses. The circuit breaker literally plugs into sockets on the housing, and the extensions are rotated outward into one of the accessible open cavities. The adapter may be placed into the fuse holder. |
| US09293269B2 |
Ultracapacitor tolerating electric field of sufficient strength
In one aspect, energy storage devices and methods are disclosed that include (preferably in order): a cationic electrode cover layer, a cationic electrode, a cationic exchange polymer electrolyte layer, a separation dielectric layer, an anionic exchange polymer electrolyte layer, an anionic electrode, and an anionic electrode cover layer. In certain embodiments, the device is configured to be initially placed in an ionized state, and optionally, can be configured to be further charged to store energy in an electrostatic mode. In another aspect, ionic solid dielectric materials, energy storage devices including ionic solid dielectric materials, and methods of making and using such materials and devices are disclosed herein. |
| US09293267B1 |
Thin-film electro devices based on derivatized poly (benzo-isimidazobenzophenanthroline) ladder polymers
A method for making electronic devices based on derivatized ladder polymer poly(benzo-isimidazobenzophenanthroline) (BBL) including photovoltaic modules and simple thin film transistors in planar and mechanically flexible and stretchable constructs. |
| US09293259B2 |
Multilayer ceramic electronic component including electrode lead out portions having different lengths
There is provided a multilayer ceramic electronic component, including a ceramic body including dielectric layers, and having first and second main surfaces, first and second side surfaces and first and second end surfaces; first and second internal electrodes having overlap regions forming a capacitance part, the first internal electrodes having a first lead out portion to be exposed to the first side surface, and being alternately laminated with the second internal electrodes while being insulated therefrom, the second internal electrodes having a second lead out portion; first and second external electrodes connected to the first and second lead out portions, respectively; and an insulating layer formed on the first side surface, wherein a length of the first lead out portion is longer than that of the second lead out portion and the capacitance part has different distances from the first side surface. |
| US09293254B2 |
Heated capacitor and method of forming the heated capacitor
A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer. |
| US09293252B2 |
R-T-B sintered magnet manufacturing method
[Problem] To provide a heavy rare-earth element RH diffusion process that contributes greatly to mass production.[Solution] A method for producing a sintered magnet includes the steps of: providing a sintered R-T-B based magnet body; providing an RH diffusion source which is made of at least one of a fluoride, an oxide and an oxyfluoride that each include Dy and/or Tb; loading the sintered R-T-B based magnet body and the RH diffusion source into a process chamber so that the magnet body and the diffusion source are movable relative to each other and are readily brought close to, or into contact with, each other; and performing an RH diffusion process in which the sintered R-T-B based magnet body and the RH diffusion source are heated to a processing temperature of 800° C. through 950° C. while being moved either continuously or discontinuously in the process chamber. |
| US09293249B2 |
Motorcycle ignition coil assembly
In accordance with one embodiment, an ignition coil assembly includes an ignition coil cover, a boot, and an ignition coil. The ignition coil cover includes a plurality of fins, an opening, and a channel. The boot includes a slotted opening and a centralized orifice and is configured to be disposed within the opening of the ignition coil cover. The ignition coil includes a seat and a tab. The ignition coil is configured to be disposed within the centralized orifice. The seat is capable of supporting the ignition coil within the centralized orifice of the boot. The tab is configured to be inserted into the slotted opening and the channel when the ignition coil is disposed within the centralized office and the boot is disposed within the opening. |
| US09293246B1 |
Magnetic component with integrated component circuit board
A component printed circuit board is provided between a magnetic component and a main printed circuit board. The magnetic component includes a device such as an inductor or transformer and includes a bobbin for winding one or more coils and a magnetically permeable core. Terminal pins protrude from the bobbin toward the main printed circuit board and provide electrical connection between the magnetic component and the main printed circuit board. The component printed circuit board includes component vias positioned to accept one or more of the terminal pins allowing the terminal pins to be used for electrical connection to both the component printed circuit board and the main printed circuit board. One or more component traces or shielding layers are disposed on the component printed circuit board. Each component trace provides an electrical connection between two or more terminal pins passing through the component printed circuit board. |
| US09293244B2 |
Magnetic material and coil component using the same
A magnetic material constituted by a grain compact 1 obtained by shaping metal grains 11 and then heat-treating them in an oxidizing ambience, wherein the metal grains 11 are made of a Fe—Cr—Si alloy and their FeMetal/(FeMetal+FeOxide) ratio as measured before shaping by XPS, with respect to the sum of integral values at the peaks of 709.6 eV, 710.7 eV and 710.9 eV, or FeOxide, and peak integral value at 706.9 eV, or FeMetal, is 0.2 or more. |
| US09293241B2 |
Communication cable
The present invention relates generally to cables suitable for use in plenum applications. In particular, the present invention relates to coaxial cables suitable for use in plenum applications (which exhibit flame spread and smoke generation properties that comply with industry standards, e.g., UL 910 or NFPA 262) without compromising electrical performance. The cable has two or more layers of insulation where the inner layer is made of a material having a high melt flow index and the outer layer is made of a material having a low melt flow index. |
| US09293240B2 |
Low inductance electrical transmission cable
An electrical transmission cable is provided with low inductance properties capable of carrying high current loads with a more uniform heating or loss profile. The low inductance properties of the cable lead to lower current losses resulting in a cooler and more efficient operation of the cable even at higher alternating current (AC) frequencies. Higher current loads are accommodated by a plurality of conductor bundles configured as braided wire strands that are separated and joined into like conductors prior to termination. Equal lengths of the insulated wire strands within the conductor bundles contribute to uniform heating along the length of the inventive cable embodiments. Uniform operating temperature is manifest as more uniform current transmission across the various strands of an inventive cable. In addition, the more equal weave position for all the wire strands making up each braided wire bundle tends to induce cancellation of inductive effects. |
| US09293239B2 |
Semi-solid balanced audio cable
The present disclosure describes implementations of audio cables including a conductor spirally wrapped in a non-conductive thread to centrally position the conductor within a channel comprising mostly air, reducing propagation delay and self-inductance compared to cables utilizing non-air dielectric materials that completely surround the conductor. A balanced audio cable includes a radially symmetric filler comprising a plurality of arms forming a corresponding plurality of channels. The cable also includes a plurality of conductors, each approximately centered within a corresponding channel. The cable further includes a plurality of non-conductive threads, each spirally wrapped around a conductor of the plurality of conductors. In some implementations, the cable also includes a jacket surrounding the filler, conductors, and threads. |
| US09293238B1 |
Acoustic-sensing underwater tow cable
An acoustic-sensing underwater tow cable includes a cable core for transmission of power/signals there along, a first jacket encasing the cable core, and discrete regions of carbon nanotubes affixed to the first jacket. The carbon nanotubes at each of the discrete regions define an acoustic sensor. A second jacket encases each acoustic sensor and any electrical conductors coupled thereto. |
| US09293236B2 |
Lithium—manganese composite oxide, secondary battery, and electric device
The amount of lithium ions that can be received and released in and from a positive electrode active material is increased, and high capacity and high energy density of a secondary battery are achieved. Provided is a lithium-manganese composite oxide represented by LixMnyMzOw, where M is a metal element other than Li and Mn, or Si or P, and y, z, and w satisfy 0≦x/(y+z)<2, y>0, z>0, 0.26≦(y+z)/w<0.5, and 0.2 |
| US09293225B2 |
Semiconductor devices and semiconductor systems including the same
Semiconductor device includes a first data input/output (I/O) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad, a second data I/O portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad, and a connection portion suitable for electrically connecting the first and second pads to each other in a test mode. Related semiconductor systems are also provided. |
| US09293222B2 |
Shift register
Disclosed is a shift register capable of stably generating an output even when the threadhold voltage of a pull-down switching element is raised due to degradation of the pull-down switching element. The shift register includes a plurality of stages each comprising a node controller comprising an inverter to control a voltage at a reset node in accordance with a voltage at a set node, and an output unit to output a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node. The shift register further includes an inverter voltage controller for controlling a high-level inverter voltage supplied to each inverter of the stages based on the voltage at at least one reset node in at least one of the stages. |
| US09293217B2 |
Non-volatile memory program algorithm device and method
A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold. |
| US09293212B2 |
Nonvolatile semiconductor memory device including a plurality of NAND strings in a memory cell array
A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell provided in a ROM area, a first read voltage to a first selected word line, and apply a first read pass voltage lower than a second read pass voltage to a first non-selected word line, thus allowing for the ROM area reading operation of reading a threshold voltage set in the first selected memory cell. The control circuit is configured to apply, when reading data of a second selected memory cell provided in a normal storage area, a second read voltage to a second selected word line, and apply the second read pass voltage to a second non-selected word line, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell. |
| US09293211B2 |
Semiconductor device and method of operating the same
A semiconductor memory device includes a memory cell, a page buffer including a first and a second switching devices coupled in common to a sensing node coupled to the memory cell through a bit line and a first and a second sensing latch units coupled to the sensing node, respectively, through the first and the second switching devices, and a control logic suitable for transferring a first and a second sensing signals, respectively, to the first and the second switching devices when a threshold voltage of the memory cell is reflected on the sensing node through the bit line during a verification operation. The first and the second switching devices are turned on or off, respectively, in response to the first and the second sensing signals, and data are sensed by the first and the second sensing latch units. |
| US09293210B2 |
Multi-level cell memory device and operating method thereof
According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch. |
| US09293209B2 |
Semiconductor memory device performing read retry mode and operating method of the same
An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less. |
| US09293208B2 |
Semiconductor memory apparatus and method for reading data from the same
A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state. |
| US09293206B2 |
Memory system including nonvolatile memory device and erase method thereof
An erase method of a three-dimensional nonvolatile memory device may include receiving an erase command, applying an erase voltage to perform an erase operation to a selected memory region in response to the erase command, suspending the erase operation by cutting off the erase voltage after a specific time has elapsed from when the erase voltage is applied, receiving a resume command after a reference time has elapsed from when the erase operation is suspended, and applying the erase voltage to the memory region for the specific time according to the resume command. |
| US09293202B2 |
Path isolation in a memory device
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed. |
| US09293199B2 |
Phase-change memory cells
A phase-change memory cell for storing information in a plurality of programmable cell states. The memory cell includes: a phase-change material located between a first electrode and a second electrode for applying a read voltage to the phase-change material to read a programmed cell state; and an electrically-conductive component extending in a direction between the first and second electrodes in contact with the phase-change material and arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than an amorphous phase of the phase-change material in any of the plurality of programmable cell states, said current path having a length dependent on a size of said amorphous phase, wherein a volume of the electrically-conductive component is greater than about half that of said phase-change material. |
| US09293194B2 |
Programming and erasure schemes for analog memory cells
A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of the memory cells in accordance with the set parameter. |
| US09293191B1 |
Apparatuses and methods for multi-memory array accesses
Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array. |
| US09293185B2 |
Apparatus including a capacitor-less memory cell and related methods
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor. |
| US09293183B2 |
Magnetoresistive random access memory
A magnetoresistive random access memory includes a memory cell line in which memory cells are formed and write bit lines. The memory cell line 1 includes a magnetic recording layer, magnetization fixed layers, reference layers, spacer layers, and nMOS transistors. The spacer layer and the reference layer are located between the magnetization fixed layer and the magnetization fixed layer). The magnetization fixed layers have a magnetization fixed to a direction opposite to that of a magnetization of the magnetization fixed layers. The reference layers also have a fixed magnetization direction. The nMOS transistor is provided between the write bit line and the magnetization fixed layer. |
| US09293182B2 |
Random access memory architecture for reading bit states
An architecture and method includes providing an oscillatory signal through each magnetic tunnel junction (MTJ), or in a line adjacent each MTJ, in a magnetoresistive random access memory array. A rectified signal appearing across each MTJ is measured and compared to a reference signal for determining the state of the MTJ. |
| US09293181B2 |
Block selection circuit and semiconductor device having the same
A block selection circuit and a semiconductor device having the same may include a row decoder which includes a high voltage generating circuit configured to output a block selection voltage in response to upper addresses, switching circuits configured to receive the block selection voltage and a precharge high voltage, and forward the block selection voltage through one of the switching circuits that is selected in response to selection signals, and pass transistor groups configured to select a memory block in response to the forwarded block selection voltage. |
| US09293179B2 |
Multiple power domain circuit and related method
A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit. |
| US09293176B2 |
Power management
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include providing a clock signal, counting primary clock cycles of the clock signal in a counter, monitoring an indication of high current demand for each die of the multi-die package, and determining a total unit consumption of current. The method may further include pausing an access operation for a particular die of the multi-die package at a designated point, and resuming the access operation if a value of the total unit consumption is less than or equal to a unit limit when a count value of the counter matches an assigned counter value of the particular die. |
| US09293175B2 |
Semiconductor memory and voltage output measuring method of the semiconductor memory
A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage. |
| US09293174B2 |
Semiconductor device
To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch. |
| US09293165B2 |
Thermally assisted magnetic recording head with magnetic circuit parallel to substrate
A recording head has a near field light (NF light) generator generating NF light on a generator end surface that irradiates a magnetic recording (MR) medium; a main magnetic pole including a pole end surface facing an air bearing surface (ABS) that emits magnetic flux to the MR medium from the pole end surface; and a return shield having a shield end surface facing the ABS, that is magnetically linked with the main magnetic pole, and absorbs magnetic flux from the MR medium at the shield end surface. The pole end surface and the shield end surface are on the same side of the generator end surface in the down track direction, and are close to each other in the track crossing direction. A center line in the down track direction of the generator end surface extends between opposing sides of the pole end surface and the shield end surface. |
| US09293162B1 |
Actuator comb having a stepped inner bore
A head stack assembly (HSA) having an actuator comb with a stepped inner bore may have an upper portion of the inner bore with a first diameter that is greater than the diameter of a lower portion of the inner bore. Therefore, little friction and resistance is encountered when force fitting a pivot-bearing assembly into the upper portion of the stepped inner bore, thereby avoiding surface damage and the generation of unwanted debris particles. The HSA may further comprise a plurality of tolerance rings to couple the actuator comb with the pivot-bearing assembly, such as one tolerance ring positioned below the step feature and one tolerance ring positioned above and seated on the step feature of the comb inner bore. |
| US09293161B1 |
Iron-oxidized hard disk drive enclosure cover
An iron-oxidized hard disk drive (HDD) cover has an inner surface that is substantially free of un-oxidized or pure metallic iron, fabricated by baking a stainless steel cover and thereby oxidizing the cover surface of iron. Because the cover is iron-oxidized, a costly nickel-plating process may be foregone while a “Fe smear” problem may be significantly reduced. Such an iron-oxidized cover is especially beneficial for, though not limited to, use as an inner cover in a sealed HDD. |
| US09293158B2 |
Apparatus having tunnel magnetoresistive sensor for contact recording
Various embodiments relate to an apparatus having an array of sensors sharing a common media-facing surface, each sensor having an active sensing region, magnetic shields flanking the active sensing region, and gaps between the active sensing region and the magnetic shields. At least one of the gaps includes an electrically conductive layer having a refractory material. Other embodiments relate to an apparatus having a sensor with an active sensing region, magnetic shields flanking the active sensing region, and gaps between the active sensing region and the magnetic shields. At least one of the gaps includes an electrically conductive layer having a modified region at a media facing side thereof, the modified region being at least one of nonconductive and mechanically hardened. |
| US09293156B2 |
Substrates for thin-film magnetic heads, magnetic head sliders, and hard disk drive devices
An AlTiC-based substrate suitable for a thin-film magnetic head is provided. The Al2O3—TiC based substrate for a thin-film magnetic head including an Al2O3 phase and a TiC phase, wherein a c-axis lattice constant of the Al2O3 phase is 12.992 Å or more and 12.998 Å or less, and a lattice constant of the TiC phase is 4.317 Å or more and 4.325 Å or less. |
| US09293155B2 |
Substrates for thin-film magnetic heads, magnetic head sliders, and hard disk drive devices
An AlTiC-based substrate suitable for a thin-film magnetic head is provided. The Al2O3—TiC based substrate for a thin-film magnetic head including an Al2O3 phase and a TiC phase, wherein a c-axis lattice constant of the Al2O3 phase is 12.985 Å or more and 12.992 Å or less, and a lattice constant of the TiC phase is 4.297 Å or more and 4.325 Å or less. |
| US09293154B2 |
Substrates for thin-film magnetic heads, magnetic head sliders, and hard disk drive devices
An AlTiC-based substrate suitable for a thin-film magnetic head is provided. The Al2O3—TiC based substrate for a thin-film magnetic head including an Al2O3 phase and a TiC phase, wherein a c-axis lattice constant of the Al2O3 phase is 12.992 Å or more and 12.998 Å or less, and a lattice constant of the TiC phase is 4.297 Å or more and 4.315 Å or less. |
| US09293153B2 |
Method and system for preserving data of a storage device
A method and system for preserving data of a storage device are disclosed. In one embodiment, the method includes determining a number of times data is written to a first track in a first region of a storage medium, and rewriting data from a second track that is adjacent to the first track in the first region if the number of times data is written to the first track in the first region exceeds a first predetermined threshold. The method further includes determining a number of times data is rewritten to the second track in the first region, and relocating data from the second track in the first region to a second region of the storage medium if the number of times data is rewritten to the second track in the first region exceeds a second predetermined threshold. |
| US09293150B2 |
Smoothening the information density of spoken words in an audio signal
A portion of an audio signal is identified corresponding to a spoken word and its phonemes. A set of alternate spoken words satisfying phonetic similarity criteria to the spoken word is generated. A subset of the set of alternate spoken words is also identified; each member of the subset shares the same phoneme in a similar temporal position as the spoken word. A significance factor is then calculated for the phoneme based on the number of alternates in the subset and on the total number of alternates. The calculated significance factor may then be used to lengthen or shorten the temporal duration of the phoneme in the audio signal according to its significance in the spoken word. |
| US09293148B2 |
Reducing noise in a shared media session
A method for reducing noise in a shared media session. An indication is received from one or more of the participants in the shared media session. If the received indication is a first indication that indicates a background noise is present in the shared media session, the following steps are performed: a first counter is incremented for each of the first indications received from one or more of the plurality of participants, it is determined whether a background noise is present in the shared media session if the first counter exceeds a first threshold, an the shared media session is selectively muted such that the background noise is reduced if the background noise is determined to be present in the shared media session. |
| US09293139B2 |
Voice controlled wireless communication device system
A wireless communication device that accepts recorded audio data from an end-user. The audio data can be in the form of a command requesting user action. The audio data is reduced to a digital file in a format that is supported by the device hardware. The digital file is sent via wireless communication to at least one server computer for further processing. The command includes a unique device identifier that identifies the wireless communication device. The server computer determines required additional processing for the command based on the unique device identifier. The server computer constructs an application command based on the processed command, and transmits the application command to the wireless communication device. The application command includes at least one instruction that causes a corresponding application on the wireless communication device to execute the application command. |
| US09293138B2 |
Storing state information from network-based user devices
Network-based services may be provided to a user through the user of a speech-based user device located within a user environment. The speech-based user device may accept speech commands from a user and may also interact with the user by means of generated speech. Operating state of the speech-based user device may be provided to the network-based service and stored by the service. Applications that provide services through the speech-based interface may request and obtain the stored state information. |
| US09293137B2 |
Apparatus and method for speech recognition
Apparatus for speech recognition includes a recognition unit configured to recognize a speech signal and to generate a first recognition result, a transmitting unit that transmits at least one of the speech signal and a recognition feature to a server, a receiving unit that receives a second recognition result from the server, a result generating unit configured to generate a third recognition result, a result storage unit that stores the third recognition result and a dictionary update unit configured to update the client recognition dictionary. |
| US09293136B2 |
Multiple recognizer speech recognition
The subject matter of this specification can be embodied in, among other things, a method that includes receiving audio data that corresponds to an utterance, obtaining a first transcription of the utterance that was generated using a limited speech recognizer. The limited speech recognizer includes a speech recognizer that includes a language model that is trained over a limited speech recognition vocabulary that includes one or more terms from a voice command grammar, but that includes fewer than all terms of an expanded grammar. A second transcription of the utterance is obtained that was generated using an expanded speech recognizer. The expanded speech recognizer includes a speech recognizer that includes a language model that is trained over an expanded speech recognition vocabulary that includes all of the terms of the expanded grammar. The utterance is classified based at least on a portion of the first transcription or the second transcription. |
| US09293135B2 |
Countermeasures for voice recognition deterioration due to exterior noise from passing vehicles
Mitigating disruption to a voice recognition system in a vehicle caused by a passing source of noise is provided. Sensors sense an approaching truck or the like that is likely to disrupt operation of the in-vehicle voice recognition system. Countermeasures are initiated to mitigate the disruption. |
| US09293134B1 |
Source-specific speech interactions
A speech system may be configured to operate in conjunction with a stationary base device and a handheld remote device to receive voice commands from a user. Voice commands may be directed either to the base device or to the handheld device. When performing automatic speech recognition (ASR), natural language understanding (NLU), dialog management, text-to-speech (TTS) conversion, and other speech-related tasks, the system may utilize various models, including ASR models, NLU models, dialog models, and TTS models. Different models may be used depending on whether the user has chosen to speak into the base device or the handheld audio device. The different models may be designed to accommodate the different characteristics of audio and speech that are present in audio provided by the two different components and the different characteristics of the environmental situation of the user. |
| US09293133B2 |
Improving voice communication over a network
Systems and methods for improving communication over a network are provided. A system for improving communication over a network, comprises a detection module capable of detecting data indicating a problem with a communication between at least two participants communicating via communication devices over the network, a management module capable of analyzing the data to determine whether a participant is dissatisfied with the communication, wherein the management module includes a determining module capable of determining that the participant is dissatisfied, and identifying an event causing the dissatisfaction, and a resolution module capable of providing a solution for eliminating the problem. |
| US09293132B2 |
Dynamic geo-fencing for voice recognition dictionary
There is a provided a mobile electronic device and a computer-implemented method. The method includes: receiving, by an electronic device, location parameters comprising a location of the electronic device, a direction of travel of the electronic device and a speed of the electronic device; configuring, by the electronic device, a dynamic geo-fenced area based on the location parameters, wherein the dynamic geo-fenced area surrounds the location of the electronic device; retrieving, by the electronic device, a Voice Recognition (VR) dictionary subset comprising data associated with the dynamic geo-fenced area from a VR dictionary, wherein the data comprises a broadcast station name and a broadcast frequency associated with the broadcast station name; and performing voice recognition using the VR dictionary subset. |
| US09293130B2 |
Method and system for robust pattern matching in continuous speech for spotting a keyword of interest using orthogonal matching pursuit
A method for speech recognition, the method includes: extracting time-frequency speech features from a series of reference speech elements in a first series of sampling windows; aligning reference speech elements that are not of equal time span duration; constructing a common subspace for the aligned speech features; determining a first set of coefficient vectors; extracting a time-frequency feature image from a test speech stream spanned by a second sampling window; approximating the extracted image in the common subspace for the aligned extracted time-frequency speech features with a second coefficient vector; computing a similarity measure between the first and the second coefficient vector; determining if the similarity measure is below a predefined threshold; and wherein a match between the reference speech elements and a portion of the test speech stream is made in response to a similarity measure below a predefined threshold. The said reference speech elements correspond to a keyword of interest, wherein Simultaneous Orthogonal Matching Pursuit (SOMP) is used in their alignment. |
| US09293128B2 |
Active noise control with compensation for acoustic leak in personal listening devices
An acoustic noise cancellation (ANC) process is performed during in-the-field use of a personal listening audio device, using a control filter to produce anti-noise by the device. The process includes computing an S_hat filter that estimates a signal path between an earpiece speaker of the device and an error microphone that are at a user's ear. A response associated with the computed S_hat filter is compared to a predetermined response that is stored in the device. The control filter is adjusted in accordance with the comparison. Other embodiments are also described and claimed. |
| US09293114B2 |
Liquid crystal display apparatus, method of driving liquid crystal display apparatus, and electronic apparatus
A liquid crystal display apparatus includes: a detection unit that detects the luminance of a backlight unit; and a controller that controls a voltage of a counter electrode, shared by pixels, based on a detection result of the detection unit. |
| US09293113B2 |
Image processing apparatus and control method thereof
An image processing apparatus includes a storage unit configured to store respective profiles representing visual characteristics of each of a plurality of persons; and a correction unit configured to perform color correction processing on image data on the basis of the plurality of profiles corresponding to the plurality of persons stored in the storage unit. |
| US09293112B2 |
Mobile terminal and control method thereof
A mobile terminal and a control method are provided. The mobile terminal includes: a display unit configured to output first screen information corresponding to a first application; and a controller configured to switch the first screen information to second screen information different from the first screen information output to the display unit in response to a first control command, and output a first graphic object representing the first application to at least a region of the display unit, wherein the controller outputs the first screen information corresponding to the first application again to the display unit in response to a second control command. |
| US09293108B2 |
Transmission apparatus and system of using the same
A transmission system includes a transmission apparatus, a first electronic device and a second electronic device electrically connected to one another. The first electronic includes a composite driver, a first application program, a first display image and a virtual display device. The first composite driver emulates the virtual display device according to the first display image. The second electronic device includes a second application program and a second display image. The transmission interface includes a transmission controller and two transmission interfaces. The two transmission interfaces are connected to the first electronic device and the second electronic device, respectively. When the first application program transmits output data corresponding to the virtual display device via the two transmission interfaces and the transmission controller to the second application program, a virtual display image corresponding to the first display image is presented on the second display image. |
| US09293103B2 |
Display device, and method for driving same
A display device including a display panel and repeating a scanning period during which the display panel is scanned and a pause period during which the display panel is not scanned. A scanning period and a pause period are set successively to a preceding frame out of two consecutive frames. A pause period is set to an entire period of a subsequent frame out of the two consecutive frames. |
| US09293102B1 |
Display having vertical gate line extensions and minimized borders
A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length. |
| US09293101B2 |
Liquid crystal display including pixels arranged in columns
A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines. |
| US09293096B2 |
Image display device, and image display method used for same
An image display device is provided which is capable of improving reproducibility of a white color. An RGB video signal is converted by a gamma converting section into three color luminance values and the maximum luminance value and minimum luminance value of the three color luminance values are calculated by a Min/Max calculating section. The first four color luminance values are calculated by an RGB luminance calculating section. A scaling factor is calculated by a scaling factor calculating section based on the first four color luminance values and the maximum luminance value. The second four color luminance values are calculated by an RGBW scaling luminance calculating section based on the first four color luminance values and on the scaling factor. An RGBW video signal corresponding to a gray level value of four color is generated by a reverse gamma converting section. |
| US09293094B2 |
Liquid crystal display device and driving method thereof
The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17). |
| US09293089B2 |
Display driving method
A method of driving an electrowetting display device for displaying images. The display device has a plurality of display elements arranged in an active matrix. The matrix has rows and columns. A specific display element is addressed by applying a voltage to the display elements along the column of the specific display element and selecting the row of the specific display element. The method includes determining a first group of rows where the voltages to be applied to the display elements in a predefined column or group of columns are within a first range smaller than a range over which the voltage is controllable; and selecting the rows in the first group consecutively. |
| US09293084B2 |
Organic EL display device
An object of the present invention is to, in an organic EL display device in which an initialization voltage is applied, extend the time period usable to write a video voltage as compared with the conventional art. In order to achieve this object, the organic EL display device includes a plurality of pixels each including an organic EL element; a plurality of video lines that supply a video voltage to each of the plurality of pixels; a plurality of scanning lines that supply a scanning voltage to each of the plurality of pixels; a unit that supplies a selection scanning voltage concurrently to an N number of scanning lines among the plurality of scanning lines, and supplies an initialization voltage to each of the plurality of video lines, in a k'th scanning period; and a unit that supplies a selection scanning voltage sequentially to the N number of scanning lines, and supplies video voltages to each of the plurality of video lines, in (k+1)th through (k+N)th scanning periods respectively. N is an integer of 2 or greater (2≦N) and k is any positive integer. |
| US09293079B2 |
Control of ambient and stray lighting in a head mounted display
A head mounted display (HMD) for viewing a virtual environment generally include a flat display (FD), lenses for focusing on the FD, and a housing to enclose the FD and lenses. The housing is generally opaque to block out all external light, so the viewer only sees light from the FD. By making a portion or all of the housing translucent or transparent, ambient light and other external light can be seen by the viewer, providing additional visual cues and a larger perceived field of view. Additionally, other people can see light from the FD. The lenses are configured to view the FD and parts of the translucent housing. |
| US09293076B2 |
Dot inversion configuration
This disclosure provides systems, methods and apparatus for an arrangement of pixels and interconnects in a display. In one aspect, polarities of pixels may be in a dot inversion configuration, or checkerboard pattern, to reduce the visibility of flicker. Various interconnect alternatively couple between modules in different columns or rows to provide dot inversion. |
| US09293075B2 |
Display apparatus and control method thereof
A display apparatus and a control method thereof are provided. The display apparatus includes: a communication interface configured to receive a video signal by using a preset setting value; a sensor configured to generate a test signal for checking whether the display apparatus is abnormal in order to sense an abnormality of the display apparatus; a controller configured to adjust a setting value of the communication interface in response to an abnormality of the display apparatus not being sensed; and a display configured to display the video signal received by the communication interface, the setting value of which has been adjusted. |
| US09293073B2 |
Testing system
Disclosed is a testing system, which includes a thin film transistor substrate. The thin film transistor substrate includes a plurality of thin film transistors and a plurality of connecting pads. Each of the thin film transistors includes a first electrode, a second electrode, and a third electrode. The thin film transistor substrate further includes a testing pad. One of the first electrode and the second electrode of each of the thin film transistors is electrically connected with one of the connecting pads. The third electrode and the other one of the first electrode and the second electrode of each of the thin film transistors are electrically connected with the testing pad. The testing system of the present invention is capable of decreasing the cost of the testing system and the complexity of disposed circuits. |
| US09293071B2 |
Graphic panel assembly
A graphic panel assembly includes a graphic holder. The graphic holder includes a base having an upper support portion for coupling to a graphic and a lower support portion including an aperture. The graphic holder also includes a hardware assembly. The hardware assembly includes a bored rod having a threaded exterior and a threaded interior and a magnetic foot fixedly mated to the threaded interior of the bored rod. The threaded exterior is positioned within the aperture located in the lower support portion of the base. The bored rod is rotatable within the aperture to adjust a distance between the base and the magnetic foot. |
| US09293069B2 |
Labeling band assembly and method of forming thereof
A method of forming an elastic labeling band. The method includes covering a central portion of a web of tag material with a release agent, advancing the web of tag material longitudinally and disposing a layer of molten elastomer over the advancing web of tag material, including over the release agent on the central portion thereof. The layer of molten elastomer is disposed over the web of tag material so that the elastomer bonds only to those portions of the web not covered with the release agent. The method includes curing the elastomer to define, with the web bonded thereto, an advancing web assembly, and separating a longitudinal segment from the web assembly to define an elastic labeling band. |
| US09293064B2 |
Simulated medical device
A simulated medical device may include a visual display, a processor, a memory, a switch connected to a power supply, a body housing the visual display, the processor, the memory, and the switch, and a simulated probe coupled to the body. The body is configured to receive internally at least a portion of the simulated probe. The switch is configured to provide a supply of power to the processor when the at least a portion of the simulated probe is external to the body and to disconnect the supply of power to the processor if the at least a portion of the simulated probe is inserted in the body. The processor is configured to cause the visual display to display at least a first simulated medical value in response to receiving the supply of power at the processor and after a time duration indicated by a simulated acquisition time. |
| US09293062B2 |
Apparatus and methods for corrective guidance of eating behavior after weight loss surgery
Apparatuses and methods for corrective guidance of eating behavior of a patient equipped with a gastric restriction device. The apparatus provides continuous monitoring or one or more parameters related to food passing through the gastric restriction device. Each monitored parameter is processed to provide a visual indication of the current eating behavior. The visual indication is used as input to the patient or a caregiver to modify the eating behavior. In some embodiments, the apparatus includes an emergency relief mechanism that automatically relieves excess pressure developing in the gastric restriction device. In some embodiments, the apparatus is enabled to deliver an appetite suppressant to modify the eating behavior. |
| US09293051B2 |
Methods and systems for displaying a vertical profile for an aircraft procedure with nonuniform scaling
Methods and systems are provided for presenting procedure information for a vertical profile on a display device associated with an aircraft. A method comprises displaying a first segment of the plurality of segments comprising a vertical profile with a first vertical scale and a first horizontal scale, wherein the first horizontal scale is based on a first distance associated with the first segment. The method further comprises displaying a second segment of the plurality of segments with the first vertical scale and a second horizontal scale, wherein the second horizontal scale is based on a second distance associated with the second segment. The first horizontal scale and the second horizontal scale are not equal. In this manner, the vertical profile has a nonuniform horizontal scale and a uniform vertical scale across segments. |
| US09293050B2 |
System and method for tactical viewing of datalink messages
An alerting system and method for producing tactical views of datalink messages is provided. The system comprises a datalink application processor configured to receive and decode an uplink datalink message. The datalink application processor includes a datalink message manager. The system also includes a control processor in operative communication with the datalink application processor and configured to communicate with the datalink message manager. A display unit is in operative communication with the control processor and is configured to show the uplink datalink message. The control processor is configured receive message data from the datalink message manager and output the message data to the display unit to generate an annunciation of the datalink message. The datalink message manager is configured to output display data for generating the datalink message in full based on a single forward field of view interaction by a user with the display unit. |
| US09293046B2 |
Vehicle rearward travel control device and method using lateral and rear detection areas
A travel control device includes a side obstacle detection unit, a rearward movement preparation detection unit, a warning unit, and a suppression unit. The side obstacle detection unit divides a range from a lateral side to a rear side of a vehicle into plural detection angle areas, and detects, for each of the plural detection angle areas, an obstacle entering the detection angle area and a distance to the obstacle. The warning unit provides warning about the obstacle. The suppression unit suppresses the warning by the warning unit, if the rearward movement preparation detection unit detects the vehicle preparing to move rearward and the detection angle area in which the obstacle is detected shifts from the rear side to the lateral side. |
| US09293039B2 |
Estimating time travel distributions on signalized arterials
A system is provided for estimating time travel distributions on signalized arterials. The system may be implemented as a network service. Traffic data regarding a plurality of travel times on a signalized arterial may be received. A present distribution of the travel times on the signalized arterial may be determined. A prior distribution based on one or more travel time observations may also be determined. The present distribution may be calibrated based on the prior distribution. |
| US09293033B2 |
Wireless fuel sensor system
A method for generating sensor data is presented. A number of wireless power signals is sent to a group of sensor units. A number of wireless data collection signals is sent to the group of sensor units after the number of wireless power signals have been sent to the group of sensor units. Sensor data in a number of wireless response signals is received from the group of sensor units. |
| US09293017B2 |
Image processing sensor systems
An image processing sensor system functions as a standalone unit to capture images and process the resulting signals to detect objects or events of interest. The processing significantly improves selectivity and specificity of detection objects and events. |
| US09293015B2 |
Electrical stimulation haptic feedback interface
A haptic drive circuit for an electrical muscle stimulation electrode has an input for receiving a haptic signal based on a haptic effect from a haptic effects processor. The drive circuit contains logic for generating a electrical muscle stimulation current based on the haptic signal. An electrode in contact with a user's skin receives the electrical muscle stimulation current, causing a haptic effect by contraction and relaxation of muscles near the electrode. |
| US09293013B2 |
Line keno and keno drawn ball position pays
A method of providing a keno game for plays with duplicate draws is provided. A keno game including a keno game board having a first predetermined number of keno board spots is displayed. A player selection of a second predetermined number of keno board spots is received. Drawn balls for a plurality of ball sets are determined. The determined drawn balls are displayed with one or more paylines overlaying at least some of the drawn balls in the plurality of ball sets. A player award based at least in part on evaluation of each payline is calculated. |
| US09293012B2 |
Individual ball draw keno
A method of providing a keno game includes, but is not limited to any of the combination of: displaying a keno board having a first predetermined number of keno board spots; receiving a player selection of a second predetermined number of keno board spots; selecting a first plurality of drawn balls; and calculating a player award in part based on data associated with the first plurality of drawn balls, wherein at least two of the drawn balls in the first plurality of drawn balls are duplicates. |
| US09293006B2 |
Gaming apparatus and systems with a bonus scheme triggered by a threshold featured event
An embodiment of the present invention provides a bonus scheme associated with a gaming process that is a feature event. With reference to the embodiment illustrated in FIG. 3, a gaming process is conducted at Steps S3 to S5, the outcome of which determines a gaming process win value. At Step S7 the gaming process win value is compared to a threshold value and, if the gaming process win value is less than, or equal to the threshold value, a bonus prize is awarded to the player at Step S9. |
| US09293005B2 |
Gaming system and method providing a plurality of different player-selectable wager alternatives when a credit balance is less than a designated wager amount and greater than or equal to a lowest eligible credit balance
Various embodiments of the present disclosure provide a gaming system and method providing a plurality of different player-selectable wager alternatives if a credit balance of a player is less than a designated wager amount (such as a cost to cover a play of a wagering game or a maximum wager amount for the play of the wagering game) and greater than or equal to a lowest eligible credit balance (such as 1 credit). Generally, selecting one of the different wager alternatives when the player's remaining credit balance is less than the designated wager amount and greater than or equal to the lowest eligible wager amount enables the player to utilize the player's remaining credit balance (or any suitable portion thereof) in a manner that is different than, separate from, and in addition to wagering on one or more plays of the wagering game. |
| US09293003B2 |
Secondary game
In various embodiments, a secondary player may make a bet that pays based on aggregate data from multiple games of primary players. |
| US09293002B2 |
Pre-authorized casino credit instrument
A casino credit access instrument comprises a source of funds for a player, such as for placing wagers to play casino-style games or to purchase other goods or services. The instrument defines a period of timed during which credit may be accessed up to a predetermined amount, defines a redemption period during which any accessed credit may be re-paid, and defines settlement terms if the instrument is not redeemed. Credit may be granted based upon financial collateral, which collateral may be executed upon to settle the instrument. The instrument provides a convenient source of funding for player at low risk to the casino or other lender. |
| US09293001B2 |
Transient or persistent game play in wagering games
According to one example embodiment disclosed herein, a wagering game is operated on a first platform, wherein the first platform is capable of supporting all or fewer than all of a plurality of game assets associated with the wagering game, and further wherein the wagering game is capable of receiving a wager. The wagering game is operated on a second platform that is capable of supporting all or fewer than all of the plurality of game assets. A player may accumulate one or more player assets while the wagering game is played on the first platform. At least one of the accumulated player assets is transferred to the play of the wagering game on the second platform, wherein at least one capability of the first platform is different from a corresponding capability on the second platform. |
| US09292997B2 |
Modifying presentation of three-dimensional, wagering-game content
A wagering game system and its operations are described herein. In some embodiments, the operations can include presenting wagering game content via an autostereoscopic display of a wagering game machine. The operations can further include determining a degree change in a position of a chair connected to the wagering game machine. In some examples, the change in the position occurs in accordance with an event from the wagering game content. The operations can further include altering an autostereoscopic presentation of the wagering game content proportional to the change in the position of the chair. |
| US09292996B2 |
Distributed side wagering methods and systems
Various techniques are disclosed for facilitating side wagering activities conducted at a casino which includes a casino gaming network. In at least one embodiment, the gaming network includes a plurality of gaming devices, including a first gaming device. A side wager request may be received for placing a first side wager relating to a first target. In at least one embodiment, the first target may be selected from a group of possible targets which, for example, may include, but are not limited to one or more of the following (or combination thereof): casino players, game tables, electronic gaming devices (EGDs), game themes, game denominations, game paytables, etc. An identity of a first player associated with generating the first side wager request may be determined. A first side wager session may be automatically initiated. |
| US09292993B2 |
Method for automated planogram programming in a vending machine
Automatic planogram programming for a glass front snack or cold drink vending machine is accomplished using tray, product and price barcodes, each preferably a different type of barcode. Trays within the vending machine are labeled with unique barcodes, and a set of price barcodes for predetermined prices is provided together with a USB-connected scanner. The barcode label affixed to any tray is scanned by the route driver. The UPC/EAN barcodes on products are then scanned for each selection progressing across the tray, together with a price barcode for the first selection and each subsequent selection having a different price from the prior selection on the tray. Planogram data for the tray may be reviewed and corrected on a customer interface display for the vending machine before moving on to another tray, with the trays programmed in any order. The planogram for the entire vending machine is quickly and accurately programmed. |
| US09292989B2 |
Temperature activated changes to light absorption and emission characteristics for security articles
Disclosed are security articles and methods and systems for authenticating security articles through the application if temperature related stimuli. Carefully synthesized nanostructures are formed to exhibit a large number of defect states within the bulk of the nanostructure. The large number of surface defects create a plurality of electron trap states below the conduction band of the composition and/or a plurality of hole states above the valance band such that excitations are induced by small changes in energy at or around kT. In this manner, a security article formed using the synthesized nanostructures produces measurable changes in spectral output based on small changes in temperature at or about room temperature. This allows the security article to be verified at high speeds with low power requirements for induced temperature change. |
| US09292983B2 |
Detectible indication of an electric motor vehicle standby mode
Systems and methods are provided for detecting that an electric motor drive vehicle (e.g., an electric scooter or motorbike) is idling based on one or more of sensed parameters indicative of the idling state. These sensed parameters may include one or more of, alone or in any combination, a sensed throttle position, at least one sensed electrical characteristic of a traction electric motor, a power converter, or an electrical storage device of the vehicle, and a sensed rate of rotation of a drive shaft of the traction electric motor or of a wheel drivably coupled to the traction electric motor. Upon detecting that the vehicle is in an idling state, a controller of the vehicle enters into a standby mode. In the standby mode, a relatively small amount of electrical power is supplied to the traction electric motor to cause a vibration of the motor to alert a driver that the vehicle is ON in the standby mode and is ready to be driven. Additionally, an audible and/or visual indication may be issued in the standby mode to further alert the driver that the vehicle is ON and ready to be driven. |
| US09292982B1 |
Systems and methods for mobile mileage tracking
A system and method allows a user to connect a mobile device, such as a smartphone, to a vehicle in order to track and record driving mileages incurred for a trip. Once a connection is established, the system and method automatically begins mileage tracking. Upon termination of the connection, the system and method sums up the tracked mileages to calculate a total mileage for the trip. The system and method then displays the total mileage for the trip to the user. |
| US09292979B2 |
Systems and methods for managing fault codes
Various embodiments of the present invention provide systems and methods for managing fault codes triggered by one or more vehicles during operation. In general, various embodiments of the invention involve recording and analyzing fault codes triggered during a particular time period while a vehicle is in operation. As a result of the analysis, various embodiments of the invention may set a state for each of the identified fault codes, the state indicating a level of action to address the identified fault code. In particular embodiments, the states may be one of a caution state indicating one or more components or sub-systems of the vehicle should be monitored, a critical state indicating one or more components or sub-systems of the vehicle should be repaired, or an environmental state indicating failure or potential failure of one or more components or sub-systems of the vehicle may affect one or more environmental conditions. |
| US09292976B2 |
Efficiency gauge for plug-in electric vehicle
A user interface for a vehicle may include an information display configured to display an efficiency gauge having an efficiency indicator. The position of the efficiency indicator may correspond to a range per full charge value. The range per full charge value may be calculated based on an amount of usable energy per full charge for an energy storage device and a distance-based energy consumption rate. An instantaneous energy consumption rate may be used to calculate an instantaneous range per full charge value. Similarly, an average energy consumption rate may be used to calculate an average range per full charge value. The efficiency gauge may include an instantaneous efficiency indicator corresponding to an instantaneous range per full charge value, an average efficiency indicator corresponding to an average range per full charge value, or both. |
| US09292975B2 |
System and method for monitoring vibration data
A system and method are provided for monitoring vibration data. A vehicle, for example, may include at least one engine component, a sensor coupled to the at least one engine component and configured to monitor a vibration of the at least one engine component, and a processor communicatively coupled to the sensor, the processor configured to determine a plurality of envelope spectrums based upon vibration data from the sensor, determine fault frequencies for each of the at least one engine component based upon a rotating speed of each of the at least one components, and monitor each envelope spectrum for changes at the determined fault frequencies. |
| US09292973B2 |
Automatic variable virtual focus for augmented reality displays
The technology provides an augmented reality display system for displaying a virtual object to be in focus when viewed by a user. In one embodiment, the focal region of the user is tracked, and a virtual object within the user focal region is displayed to appear in the focal region. As the user changes focus between virtual objects, they appear to naturally move in and out of focus as real objects would in a physical environment. The change of focus for the virtual object images is caused by changing a focal region of light processing elements in an optical path of a microdisplay assembly of the augmented reality display system. In some embodiments, a range of focal regions are swept through at a sweep rate by adjusting the elements in the optical path of the microdisplay assembly. |
| US09292961B1 |
System and method for detecting a structural opening in a three dimensional point cloud
A method for detecting an opening in a structure represented by a three-dimensional point cloud may include the steps of: (1) creating a three-dimensional point cloud map of a scene, the three-dimensional point cloud map including a plurality of points representing a ground plane and the structure upon the ground plane, (2) identifying an absence of points within the plurality of points representing the structure, and (3) determining whether the absence of points represents the opening in the structure. |
| US09292960B2 |
Random accessible lossless parameter data compression for tile based 3D computer graphics systems
A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. The multiple byte data is divided into individual bytes and bytes with corresponding byte positions relating to each vertex are grouped together to form a plurality of byte blocks. |
| US09292958B2 |
Image processing system, game system, image processing method, image processing apparatus and recording medium
An example system includes: a field arrangement unit for positioning a field object in a three-dimensional virtual space; a viewpoint setting unit for setting a viewpoint in the virtual space so as to have an overhead viewpoint with respect to the field object; a scrolling unit for moving the viewpoint or the field object so as to change an area of the field object included in a range of vision on the basis of the viewpoint set by the viewpoint setting unit; a field deformation unit for deforming a shape of the field object such that a front side of the range of vision becomes flat while a back side of the range of vision is curved in a direction away from the viewpoint in accordance with a movement performed by the scrolling unit; and an image processing unit for generating a two-dimensional image displayed on a display unit. |
| US09292957B2 |
Portable virtual characters
Described herein are methods, systems, apparatuses and products for portable virtual characters such as virtual characters. One embodiment provides a method for providing a virtual character, including: storing, in device memory, a listing of at least one mobile device having at least one device component selected from the group consisting of an accelerometer, a camera, and a microphone; and transferring, using a processor, to a mobile device information to permit an instantiation of a mobile device version of a virtual character on the mobile device, the instantiation of the virtual character on the mobile device including at least one virtual character attribute matching the at least one device component selected from the group consisting of an accelerometer, a camera, and a microphone. Other embodiments are disclosed and claimed. |
| US09292955B1 |
Sequencing of animations in software applications
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for defining a sequence of animations for changing visible and non-visible values of objects. One or more programmatic calls is received, the calls including animations and sequencing for their performance. Consecutive frames of the animations are displayed according to the animations and the sequencing defined in the programmatic calls. Non-displayed properties of the objects in the animations are changed in coordination with the displaying of the consecutive frames. |
| US09292952B2 |
Task manager and method for managing tasks of an information system
Information about a device may be emotively conveyed to a user of the device. Input indicative of an operating state of the device may be received. The input may be transformed into data representing a simulated emotional state. Data representing an avatar that expresses the simulated emotional state may be generated and displayed. A query from the user regarding the simulated emotional state expressed by the avatar may be received. The query may be responded to. |
| US09292946B2 |
X ray computer tomography apparatus and image processing apparatus
An X-ray computer tomography apparatus includes at least one X-ray tube generating X-rays, first detector elements (energy integrating type) and second detector elements (photon counting type) detecting an intensity and spectrum of the X-rays transmitted through the object respectively, at least one data acquisition circuit acquiring first projection data and second projection data smaller in data amount than the first projection data detected by the first and second detector elements respectively, an arithmetic circuit computing a minimum value of a cost function based on the first and second projection data by executing an iterative reconstruction algorithm, and reconstruction circuit reconstructing an image of the object based on the first and second projection data, which correspond to the minimum value of the cost function. |
| US09292944B2 |
System and method for computing an image
Disclosed are a system and method for computing a picture. Instead of loading a file that contains the image from memory, the present invention provides for a system and method for opening and retaining a procedural recipe and a small set of instructions that can be executed to compute a picture. The picture can be computed very quickly using a GPU (graphics processing unit), and can be made to move on demand. When a part of the image is needed to composite, that part is computed using a fragment program on the GPU using the procedural recipe and a specially written fragment program into a temporary VRAM buffer. After it is computed and composited, the buffer containing the result of the fragment program may be discarded. |
| US09292943B2 |
Automatic method of setting a desktop background color and electronic device for using the same
An automatic method of setting a desktop background color is disclosed. The method is used for setting a desktop background color of an electronic device such that the desktop background color corresponds to a color of a protective cover, wherein a cover body of the protective cover for covering a touch screen of the electronic device has a conducting area and a non-conducting area. The method includes the following steps: receiving protective cover information generated by the touch screen touching the conducting area; determining whether the protective cover information is in accordance with one of a plurality of preset protective cover information stored in the electronic device; if the protective cover information is in accordance with one of the plurality of preset protective cover information, setting the desktop background color displayed by the touch screen according to color information corresponding to the preset protective cover information. |
| US09292937B2 |
Opt-keyframe reconstruction for robust video-based structure from motion
A non-keyframe reconstruction technique is described for selecting and reconstructing keyframes that have not yet been included in a reconstruction of an input image sequence to provide a better reconstruction in a structure from motion (SFM) technique. The technique may, for example, be used in an adaptive reconstruction algorithm implemented by a general SFM technique. This technique may add and reconstruct non-keyframes to a set of keyframes already generated by an initialization technique and reconstructed by adaptive and optimization techniques for iteratively selecting and reconstructing additional keyframes. Camera motion and intrinsic parameters may be computed for non-keyframes by optimizing a cost function. Output of the non-keyframe reconstruction technique may include at least camera intrinsic parameters and Euclidean motion parameters for the images in the input image sequence. |
| US09292936B2 |
Method and apparatus for determining location
A computer-implemented method and apparatus for determining location, the method comprising: receiving a first sequence of kinematic values related to a route of an image appearing in captured pictures; receiving a second sequence of kinematic values related to a series of readings from at least one inertial sensor received from a mobile device; determining a matching measure between the first sequence of kinematic values and the second sequence of kinematic values; and associating an identifier associated with the mobile device with a location determined from the captured pictures. |
| US09292932B2 |
Three dimension measurement method, three dimension measurement program and robot device
A three-dimensional measurement method three-dimensionally restores an edge having a cross angle close to parallel to an epipolar line. Edges e2L, e3L and e4L on the same plane of a work are selected, and among these edges, at least two edges e2L and e4L residing in a predetermined angle range with reference to the cross angle of 90° crossing the epipolar line are three-dimensionally restored by a stereo method. Then, a three-dimensional plane P1 including these three-dimensionally restored e2L and e4L is found, and the edge e3L residing beyond a predetermined angle range with reference to the cross angle of 90° crossing the epipolar line is projected to this three-dimensional plane P1, thus three-dimensionally restoring the edge e3L. |
| US09292926B1 |
Depth map generation
Depth maps are generated from two or more of images captured with a conventional digital camera from the same viewpoint using different configuration settings, which may be arbitrarily selected for each image. The configuration settings may include aperture and focus settings and/or other configuration settings capable of introducing blur into an image. The depth of a selected image patch is evaluated over a set of discrete depth hypotheses using a depth likelihood function modeled to analyze corresponding images patches convolved with blur kernels using a flat prior in the frequency domain. In this way, the depth likelihood function may be evaluated without first reconstructing an all-in-focus image. Blur kernels used in the depth likelihood function and are identified from a mapping of depths and configuration settings to the blur kernels. This mapping is determined from calibration data for the digital camera used to capture the two or more images. |
| US09292924B2 |
Method and device for monitoring a spatial region
A first and a second image recording unit, which are arranged at a defined distance from one another, are provided for monitoring a spatial region. The spatial region has at least one structure having a plurality of substantially parallel edges. A number of reference marks are arranged at the structure. A first image of the spatial region is recorded by means of the first image recording unit. A second image is recorded by means of the second image recording unit. A number of reference distances between the image recording units and the reference marks are determined. A structure position of the structure is determined on the basis of the reference distances. Moreover, a number of object positions are determined on the basis of the first and second images, wherein each object position represents the spatial distance of an object relative to the image recording units. Depending on the object positions, a switching signal is generated. |
| US09292921B2 |
Method and system for contrast inflow detection in 2D fluoroscopic images
A method and system for contrast inflow detection in a sequence of fluoroscopic images is disclosed. Vessel segments are detected in each frame of a fluoroscopic image sequence. A score vector is determined for the fluoroscopic image sequence based on the detected vessel segments in each frame of the fluoroscopic image sequence. It is determined whether a contrast agent injection is present in the fluoroscopic image sequence based on the score vector. If it is determined that a contrast agent injection is present in the fluoroscopic image sequence, a contrast inflow frame, at which contrast agent inflow begins, is detected in the fluoroscopic image sequence based on the score vector. |
| US09292918B2 |
Methods and systems for transforming luminal images
The invention provides methods and systems for correcting translational distortion in a medical image of a lumen of a biological structure. The method facilitates vessel visualization in intravascular images (e.g. IVUS, OCT) used to evaluate the cardiovascular health of a patient. Using the methods and systems described herein it is simpler for a provider to evaluate vascular imaging data, which is typically distorted due to cardiac vessel-catheter motion while the image was acquired. |
| US09292916B2 |
Methods and systems for estimating genetic characteristics from biometric measurements
Methods and devices are disclosed for collecting fingerprint and genetic information from an individual during a single collection session. A skin site is illuminated by direct imaging of the skin site using light reflected from the illuminated skin site. A cell of the individual, such as a skin cell, is retrieved from the collection surface. |
| US09292915B2 |
Digital optical comparator
A digital optical comparator has a holder for a part under study. A light source illuminates the part and casts an Image of the part onto a camera, which is provided with a lens. The Image captured by the camera is displayed on a screen, and a drawing of the part is overlaid on the image of the part. Thus, defects in manufacturing can be easily and readily identified. In addition, a determination of whether the part is manufactured within tolerances can also be visually determined. |
| US09292914B2 |
Device for measuring critical dimension of pattern and method thereof
A device and method for measuring a critical dimension of a pattern on a display substrate is disclosed. In one aspect, the device includes a region of interest (ROI) setting unit setting a region of interest in image data, determining whether the region of interest is larger than a reference region, and generating a pattern image based on the region of interest. The device also includes a design file memory storing a plurality of design patterns, a matching unit matching the pattern image to one of design patterns, and a measurement unit measuring the critical dimension of the pattern in the pattern image. The ROI setting unit selects the image data as the pattern image and outputs the pattern image to the matching unit when the region of interest is larger than the reference region. |
| US09292913B2 |
Augmented three dimensional point collection of vertical structures
An image display and analysis system is disclosed. The image display and analysis system and method includes a system for reading an image having an object of interest. The image includes corresponding location data indicative of position and orientation of the image capturing device(s) used to capture the image. The system receives one or more selected points within the image on the object of interest, and calculates a measurement of the object of interest using pixel location, the position and orientation of the image capturing device(s), and a TGP vertical plane. |
| US09292912B2 |
Display apparatus and method for image output thereof
A display apparatus and an image output method thereof are provided. The image output method includes dividing a received image into a plurality of sub-images, correcting quality of each of the sub-images based on a contrast ratio calculated for the received image, and outputting the image by combining the corrected sub-images. Hence, the display apparatus can enhance luminance and chrominance which vary per sub-image segment in the received image. |
| US09292911B2 |
Automatic image adjustment parameter correction
Techniques are disclosed relating to modifying an automatically predicted adjustment. In one embodiment, the automatically predicted adjustment may be adjusted, for example, based on a rule. The automatically predicted adjustment may be based on a machine learning prediction. A new image may be globally adjusted based on the modified automatically predicted adjustment. |
| US09292910B2 |
Image processing apparatus, image processing method, program, printing medium, and recording medium
When obtaining subband signals by performing multiresolution decomposition on image data using a broad-sense pinwheel framelet or a pinwheel wavelet frame, having a degree, that is a set of an approximate filter with no orientation and a plurality of detail filters with respective orientations, and acquiring processed image data by the subband signals in a decomposition phase of the multiresolution decomposition, or processed image data that has been reconstructed into an image by summing the subband signals in a synthesis phase of the multiresolution decomposition, the present invention performs attenuation or amplification of the subband signals in the decomposition phase of the multiresolution decomposition that correspond to at least one of the filters. |
| US09292908B2 |
System, method, and computer program product for enhancing an image utilizing a hyper-clarity transform
A system, method, and computer program product are provided for enhancing an image utilizing a hyper-clarity transform. In use, an image is identified. Additionally, the identified image is enhanced, utilizing a hyper-clarity transform. Further, the enhanced image is returned. |
| US09292901B2 |
Handheld device and method for displaying synchronously with TV set
The present invention discloses a handheld device and a method for a handheld device to display synchronously with a TV set. The handheld device includes a display management module for converting output display data into data corresponding to a TV set screen resolution and displaying same on the TV set screen, and an output management module for converting the output display data into data corresponding to a handheld device resolution and displaying same on a handheld device screen synchronously with the TV set screen, the handheld device being connected to the TV set via an HDMI cable. A bidirectional synchronous display function is achieved in the present invention. |
| US09292900B2 |
Partition-free multi-socket memory system architecture
A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock. |
| US09292898B2 |
Conditional end of thread mechanism
A graphics processing unit, method, computer readable media, and system are described herein. The graphics processing unit includes at least one execution unit, the execution unit configured to execute a shader. The shader includes instructions that causes the execution unit to process a plurality of pixels in parallel until each of the plurality of pixels is discarded and execution of a last write instruction, and execute a conditional end of thread instruction after each of the plurality of pixels is discarded and after execution of the last write instruction, wherein execution of the conditional end of thread instruction is to terminate the thread. |
| US09292894B2 |
Content recognition and synchronization using local caching
A content fingerprint based recognition system employs local caching of portions of a fingerprint database to manage network services for identifying which programs a user's mobile device is exposed to and the timing of events within the program. The system enables background recognition and synchronization of network services in a way that consumes less device power and bandwidth. |
| US09292890B2 |
Method and system for providing case update notifications
A method and system for providing case update notifications is provided. Judicial court case updates are received via a judicial court case management system for a judicial court. At least one of the judicial court case updates is identified as being of interest to a user unaffiliated with the judicial court that is participating in the judicial court case. The user is automatically notified of the at least one judicial court case update. |
| US09292885B2 |
Method and system for providing social search and connection services with a social media ecosystem
A method and system for social media ecosystem searching. A desired person can be searched for from public search engines and social media sites directly by name and/or by unique search keywords and search categories created and publically published by the desired person, a social media index of the desired person or a social commerce connection associated with the desired person. The search results are publically viewable. However, communication with the desired person located within the social media ecosystem is via a private system in which a searcher must provide login information to privately communicate with the desired person. The private system helps ensure that social media index values and social commerce connections are properly established, recorded and updated for the desired person and provides a layer of security and privacy. The social media searching ecosystem is provided on a cloud communications network for mobile and non-mobile devices. |
| US09292884B2 |
Network-aware product rollout in online social networks
In one embodiment, a method includes accessing a social graph comprising a plurality of nodes and a plurality of edges connecting the nodes, each node corresponding to a user of an online social network, identifying a plurality of clusters in the social graph using graph clustering, providing a treatment to a first set of users based on the clusters, and determining a treatment effect treatment for the users in the first set based on a network exposure to the treatment for each user. |
| US09292879B1 |
Systems and methods for generating and presenting social markers
A social marker is generated from data about user relationships and interactions with consumer objects such as brands, products, services, or a combination thereof. The social marker provides an indicator to a target user that someone they have a relationship with has taken some action associated with the consumer object. This action may include, but is not limited to, posting a comment, a rating, a recommendation, and so forth about the consumer object. |
| US09292878B1 |
Application programming interface for audio recommendation, discovery, and presentation within a social network
A system and method for providing an application programming interface for interfacing with audio files within a social networking service are provided. The method includes receiving, at the one or more computing devices, an ordered list of social networking contacts associated with a member of the social networking service. The ordered list of social networking contacts is arranged according to a ranking of the social networking contacts. The method also includes receiving a list of audio files associated with the member of the social networking service. The method also includes receiving a set of instructions. The set of instructions is configured to be implemented with the ordered list of social networking contacts and the list of audio files. The method also includes interfacing with the ordered list of social networking contacts or the list of audio files according to the set of instructions to modify the list of audio files. |
| US09292873B1 |
Expedited acquisition of a digital item following a sample presentation of the item
An electronic service provides a sample of a media item to a user, along with a prompt. The prompt gives the user the opportunity to receive an additional part of the item substantially without further interaction with the user. The streamlined acquisition of the additional part of the media item is enabled by the user's establishment, in advance, of user identification information, payment information, and so on. |
| US09292870B2 |
System and method for point of service payment acceptance via wireless communication
A system and method for remitting payment from a consumer's credit or stored value account by digital presentations of account information are described. A merchant may create one or more merchant account at a point-of-sale service site (“POS service site”) and associate one or more merchant portable computing devices (“MPCDs”) with one or more of the merchant accounts. Each MPCD may be configured to receive customer data from a customer via one of a visual capture and a wireless communication, such as a near field communication (“NFC”) or a machine-readable optical code. The customer data may be received from an NFC-capable physical token such as an EMV card, or a virtual token presented by a customer portable computing device (“CPCD”) using a NFC or a machine-readable optical code. Each MPCD may contain a point-of-sale payment application supplied by the POS service site that may capture data representative of a consumer account from the received customer data. |
| US09292869B2 |
System and method for default payment setting
A consumer accesses a secure area of a transaction account website and provides their login information for retail websites. The transaction account issuer or a third party creates a script that logs in to the retail websites on behalf of the consumer and transmits transaction account information associated with the transaction account. The script sets the transaction account as the default payment method for the retail website. The transaction account information may be evergreen, such that whenever the transaction account information changes, the script updates the retail websites. |
| US09292868B2 |
Collaborative content evaluation
In an example embodiment, a system for evaluating published content is provided. The system includes at least one processor and a plurality of components including instructions executable by the at least one processor. The components include a reporting component and an evaluation component. The reporting component is to receive a communication from one of a plurality of users of a network-based system, the communication identifying content accessible via the network-based system as objectionable. An evaluation component is to evaluate the identified content based on a reputation value of the one of the plurality of users to determine an action to take with respect to the identified content. The reputation value is based at least in part on a history of objectionable content reporting by the one of the plurality of users. |
| US09292867B2 |
Electronic receipt system
A method includes receiving, at a user identification module of an electronic receipt system in electronic communication with a point of sale terminal, a user identifier transmitted from a mobile communication device to a near-field communication enabled communication device associated with the point of sale terminal. The method also includes verifying, by a validation module of the electronic receipt system, an enrollment status of the user identifier; and based on results of the verifying, transmitting, by a transfer module of the electronic receipt system, the user identifier and data characterizing an electronic receipt to a receipt storage module of the electronic receipt system. |
| US09292865B2 |
Dynamic keyboard for trading
Data processing systems and methods for managing transactions in auction-based trading of specialized items such as fixed income instruments are presented. The data processing system provides a highly structured trading protocol implemented through a sequence of trading paradigms. The system employs a distributed computer processing network linking together a plurality of commonly configured program-controlled workstations. The protocol and its program-controlling logic improves trading efficiency, rewards market Makers, and fairly distributes market opportunity to system users. |
| US09292859B1 |
Injecting a code into video data without or with limited human perception by flashing the code
A playlist and a digital advertisement are received. The digital advertisement is output to a screen on the basis of information in the playlist. A code is generated based on the information in the playlist and the generated code is output to the screen. The generated code is output to the screen by flashing the generated code on the screen at a predetermined flash frequency and for a predetermined flash time so that the generated code is visually imperceptible or barely detectable to a human viewer. A suitable equipped electronic device may detect the code and utilize information encoded in the code in various ways. |
| US09292858B2 |
Data collection system for aggregating biologically based measures in asynchronous geographically distributed public environments
The present invention relates to biologically and behaviorally based systems and methods for measuring audience response to a target stimulus. The systems and methods are deployable in multiple locations and may display stimuli based on location, target demographics, and combinations thereof. |
| US09292854B2 |
Method and apparatus for enabling purchasers of products to obtain return information and to initiate product returns via an on-line network connection
An electronic registration system facilitates authorized product returns. A retailer sales associate is prompted to enter individual product identification information such as an individual serial number. This individual product identification information is stored in a database, along with the date on which the product was sold and an appropriate UPC code, SKU number, or manufacturer code. A check digit algorithm may be used to verify the serial number prior to storage. A sales receipt may be imprinted with at least the date of the transaction and the serial number. When a product is returned, the retailer may cross-reference the serial number on the product with that on the receipt to verify the sales receipt. Otherwise, the database may be searched for sales information. A customer may also access a return authorization engine via the Internet to obtain return approval, an authorization number, return instructions, etc. |
| US09292851B1 |
System and method for biometric signature authorization
A system and method of obtaining and storing a signed agreement authorizing the use of a user's biometric data for the purpose of offering legal consent to agreements and transactions with one or more operators. The present invention imparts a process by which merchants and other service providers can access a verifying agreement indicating a user's intent to submit biometric data as a substitute for a written signature and the user's consent to abide by the terms and conditions of any agreements entered into by the submission of biometric data. |
| US09292850B2 |
Host capture
A system and method for processing transactions. A unique transaction identifier is generated for each transaction. Processing of the transaction utilizes the unique transaction identifier. |
| US09292846B2 |
Mobile device authorization system for concurrent submission of multiple tender types
Methods, systems, and devices are described for providing mobile device transaction approvals utilizing multiple forms of tender. An identifier of a mobile device and a request for a transaction authorization may be transmitted from a mobile device and received at a payment authority system. The payment authority system may generate a payment code for transmission to the mobile device. The payment code may be provided to a point of sale (POS) system. The POS system may transmit a transaction amount, an identifier of a merchant, and the payment code to the payment authority system. A number of forms of tender may be applied to the transaction amount. The payment authority system may generate a unified approval code applying the multiple forms of tender to the transaction. The unified approval code may be transmitted to the POS system and applied to a transaction. |
| US09292843B1 |
Advanced payment options for powered cards and devices
Advanced payment applications are provided to improve the functionality of cards and devices. For example, a user interface may be placed on a card (e.g., a physical button) or a telephonic device (e.g., a virtual button on a capacitive touch screen). Manual input provided to this user interface may, for example, cause an item purchased on credit to be paid via one or more user accounts (e.g., bank accounts) as soon as the next credit statement posts or becomes due. A user may decide to pay for an item when the next statement becomes due at a point-of-sale magnetic stripe reader by using an interface on a card to cause information to be communicated through the infrastructure indicative of a user's desire to pay the for an item when the next statement becomes due. |
| US09292842B2 |
Systems and methods for managing software licensing agreements
Systems and methods to provide licensing and licensing management to source code components. The system receives a request from a component developer for a component license. The system sends a public key, a component identifier, and licensing code to the developer and the developer embeds the public key, the component identifier, and the licensing code within the source of the component. The developer sends the embedded component to the system, which publishes the component for sale on a web site. A purchaser of the component can embed the component, API code, and a generated license key into a developed application. The API code is invoked, which activates the component within the application. The application can be sent to the system where it can be published to a web site for sale. |
| US09292840B1 |
ATM customer messaging systems and methods
Identification information for a first account holder at a financial institution is received. The first account holder is authenticated based on the identification information. A second account holder at the financial institution is identified as being known to the first account holder. Inputs are received from the first account holder to configure a message to be displayed to the second account holder. The message is displayed to the second account holder from the first account holder. |
| US09292839B2 |
System and method for personalized commands
Various embodiments of a system and method for personalized commands are described. The system and method for personalized commands may include a payment service including a command management component. Such payment service may be responsive to one or more base commands. The command management component may be configured to generate a user interface for specifying personalized commands that correspond to the base commands. The command management component may be configured to generate mapping information from the information received via the user interface. The command management component may be configured to receive one or more messages that may include commands for the payment service, including personalized commands. From the personalized commands, the command management component may be configured to determine a corresponding base commands (e.g., based on the mapping information). Once the base command is determined, the payment service may perform the base command. |
| US09292832B2 |
Collaborative intelligence and decision-making in an IoT device group
The disclosure relates to collaborative intelligence and decision-making in an Internet of Things (IoT) device group. In particular, various IoT devices in the group may be interdependent, whereby a decision that one IoT device plans may impact other IoT devices in the group. Accordingly, in response to an IoT device planning a certain decision (e.g., to transition state or initiate another action), the IoT devices in the group may collaborate using distributed intelligence prior to taking action on the planned decision. For example, a recommendation request may be sent to other IoT devices in the group, which may then analyze relationships within the group to assess potential impacts associated with the planned decision and respond to approve or disapprove the planned decision. Based on the responses received from the other IoT devices, the IoT device may then determine whether to take action on the planned decision. |
| US09292831B2 |
Monitoring data elements across multiple networks and processes
The invention described here is a computer-related method for analyzing and reporting the current status of a wide array of processes and conditions across multiple networks and systems. It employs independent software entities called “Blades” to control the retrieval, analysis and characterization of each situation, combined with a common presentation system that displays those characterizations in a simple graphical vocabulary for expressing degrees of positive and negative significance. By employing Tiles or similar independent graphical reports, shown together on the screen of a desktop computer, notebook, tablet, mobile device or wearable interactive display, the invention described here allows the user to see his or her world at a glance. |
| US09292828B2 |
Hierarchical display of project information in a collaboration environment
Providing access to project information in a virtual collaboration environment is disclosed. A credential information associated with a user of the virtual collaboration environment is received. It is determined, based at least in part on the credential information, which portion or portions of a hierarchical set of project information the user is entitled to receive. A hierarchical display that includes the portion or portions of the hierarchical set of project information that it is determined the user is entitled to receive is provided to the user via the virtual collaboration environment. |
| US09292827B2 |
Alcoholic beverage allocation machine
Various methods and systems such as in a software application are presented which may include automated purchase recommendations based on amalgamated purchase constraints (4) for business inventory maintenance, notation of events through noted event entry portals (31) for business related observation recordation, automatic facilitation of regular debut of initial suggested industry tied information (50), presentation of business performance data (65) and disparate substantially redundant business performance data (67) in a business performance display (66) for a summary review of business operations, and easy selection of inventory items (83) from a recommended hierarchical categorization of inventory items which may be used to create buying reports, ad hoc reports, and the like. |
| US09292823B2 |
Pneumatic transport delivery control
The presented inventions seek to create a verifiable and closed loop chain-of-custody for a specific transaction in a pneumatic tube transport system while allowing a sender and recipient to perform asynchronous activity. That is, one aspect the presented inventions allows a sender to securely send a carrier to a desired recipient while allowing the desired recipient to receive the secured carrier at a convenient time and/or location without tying up system resources. Another aspect improves the physical barriers between high value payloads and the unintended recipients. This is done in part by introducing randomness into the carrier delivery process such that no member of the general public or facility staff knows the location and/or delivery time of a secured carrier without having access to specific database records indicating the current location and/or delivery status of the secured carrier. |
| US09292821B2 |
System and method for transforming a component business model
Seamless transition from a Component Business Model (CBM) to a Services Oriented Architecture (SOA) is achieved by converting a tabular representation of a CBM Heat Map to a Unified Modeling Language (UML) representation, and automatically converting the UML representation of a CBM Heat Map to a first iteration of input used during the subsequent SOA solution development using Service Oriented Modeling and Architecture (SOMA). |
| US09292819B2 |
Systems and methods for identifying and delivering tailored content based upon a service dialog
The present disclosure identifies and/or delivers tailored content based upon a service dialog. For example, the systems may receive a request for tailored content, facilitate a service dialog to obtain information related to the request, and communicate a plurality of tailored content based upon the information related to the request. Further, the systems may identify tailored content based upon a consumer profile, communicate the tailored content to a web client, and/or receive a selection of the tailored content. Further still, the systems may modify a magazine (e.g., content that is presented electronically) based upon tailored content. |
| US09292814B2 |
System and method for concurrent electronic conferences
Method for scheduling and implementing an electronic meeting conducted among remotely-located users communicating with an agenda server, including: accepting a meeting agenda that includes a plurality of topics, a quorum, an identification of resources used by each topic, an identification of data used by each topic, and an identification of data produced by each topic; partitioning the meeting agenda into at least a first and second group of topics; searching for data dependencies between the first and second groups of topics; searching for resource dependencies between the first and second groups of topics; if data dependencies or resource dependencies are found between the first and second groups of topics, then repartitioning the meeting agenda until the data dependencies and resource dependencies between the first and second groups of topics are reduced below a predetermined dependency threshold; and concurrently scheduling and executing the first and second groups of topics. |
| US09292812B2 |
System and method for processing multiple mailing services orders of varying quantities and address lists
Methods and systems for processing multiple mailing services orders for print items of varying quantities include filling 3-dimensional gangs configured to receive print-ready items with print-ready items in a stack-wise manner. Individual stacks can be submitted to the system for reprint without holding up remaining items in an order. |
| US09292810B2 |
Re-factoring, rationalizing and prioritizing a service model and assessing service exposure in the service model
Provided herein are approaches to re-factor, rationalize, and prioritize a service model, and to assess service exposure in the service model. At least one approach provides: determining a granularity of one or more services of the service model; re-factoring and refining a service portfolio and a hierarchy of the service model; adapting a Service Litmus Test (SLT) and service exposure scope to the service model; applying Service Litmus Tests (SLTs) to the service model; and verifying, with each affected stakeholder associated with the service model, that the service model achieves business and technical needs based on the results of the SLTs, which include tests to make exposure decisions, including whether to expose the service or not expose the service, wherein the service represent business capabilities and are placed in the hierarchy of the service model which represents the granularity. |
| US09292808B2 |
Data management for top-down risk based audit approach
Particular embodiments generally relate to providing risk management. In one embodiment, a first risk is linked to an account group assertion in a data structure. A second risk is linked to a control objective in the data structure. Access to the first risk is granted through the account group's assertion. Access to the second risk is granted through the control objective. Risk management is then performed using the accessed first risk and second risk. |
| US09292805B2 |
Human security and survival system
The invention relates to a method and system of filling and maintaining a database containing geo-localized user data comprising the following steps: —receiving registration data from users, —generating a personalized user-environment like a dynamically generated personal WebPage; —requesting and storing of HSS-data of the registered user by means of the personal WebPage using the Internet; —maintaining the database by checking the HSS-data each time the user makes direct or indirect contact with the personal WebPage. |
| US09292803B2 |
Apparatus and method for privacy-driven moderation of metering data
According to an embodiment there is provided a system comprising an input for connecting the system to a power supply, at least one further power source, at least one power consumer, an identifying unit arranged to identify, based on information originating from within the system, an ongoing and/or future power consumption event by the at least one power consumer and a power router that comprises a controller and that is arranged to route power to the power consumer from at least one of the power supply and the at least one further power source, the power router storing rules that define at least part of the routing operation of the router. The power router is arranged to route power to an power consumer in accordance with the rules so that at least a part of the power consumed by the power consumer during the power consumption event is provided by the at least one power source, rather than through the input, in response to the identifying unit identifying a power consumption event. |
| US09292800B2 |
Statistical estimation of origin and destination points of trip using plurality of types of data sources
A method of predicting the origin and destination points of an unknown trip using a computer includes receiving an input of second marker information including the type and position of a known marker included in a second region; generating a second feature vector at each spot included in the second region on the basis of the second marker information; and predicting the probability that the respective spots included in the second region are the origin and destination points on the basis of a prediction model, which is acquired based on first marker information including the type and position of a known marker included in a first region and information on the known origin and destination points included in the first region, and the second feature vector. |
| US09292799B2 |
Global model for failure prediction for artificial lift systems
Methods and systems for predicting failures in an artificial lift system are disclosed. One method includes extracting one or more features from a dataset including time sampled performance of a plurality of artificial lift systems disposed across a plurality of different oil fields, the dataset including data from failed and normally operating artificial lift systems. The method also includes forming a learning model based on identified pre-failure signatures in the extracted features, the learning model configured to predict a failure of an artificial lift system based on observation of one of the identified pre-failure signatures in operational data received from the artificial lift system. |
| US09292790B2 |
Piecewise linear neuron modeling
Methods and apparatus for piecewise linear neuron modeling and implementing artificial neurons in an artificial nervous system based on linearized neuron models. One example method for operating an artificial neuron generally includes determining that a first state of the artificial neuron is within a first region; determining a second state of the artificial neuron based at least in part on a first set of linear equations, wherein the first set of linear equations is based at least in part on a first set of parameters corresponding to the first region; determining that the second state of the artificial neuron is within a second region; and determining a third state of the artificial neuron based at least in part on a second set of linear equations, wherein the second set of linear equations is based at least in part on a second set of parameters corresponding to the second region. |
| US09292789B2 |
Continuous-weight neural networks
A computer-based multi-layer artificial network named Continuous-weight neural network (CWNN) configured to receive an input feature set wherein the input feature set comprises a variable number of features is disclosed. A method for classifying input sets based on a trained CWNN is also disclosed. Various implementation examples are also provided. |
| US09292786B2 |
Universal balancing controller for lateral stabilization of bipedal robots in dynamic unstable environments
A robot, such as a bipedal robot, that includes three or more rigid links such as two legs and a pelvis. The robot includes joints pivotally connecting pairs of the rigid links and an actuator associated with each of the joints. The robot includes a universal balancing controller with an output feedback control module providing control signals to selectively drive the actuators to balance the robot on a support element which may be configured to provide a dynamic, unstable environment or to provide a static, stable environment. During use, the control signals are generated in response to processing of global robot data from sensors associated with the rigid links or the joints. The control signals are generated by the output feedback control module without any need for measurements of the support element or without any measurement of a dynamic environment. |
| US09292785B1 |
Goal tracking system
A goal tracking system is described. The goal tracking system can include a bracelet having numeric indicia disposed thereon representing an accomplishment or a goal such as weight loss. A button connector is adjacent to each of the numeric indicia to maintain a button-charm. The button-charm is moved from numeric indicia to numeric indicia as a corresponding goal is achieved. In one aspect, the bracelet may be used to track weight loss results, set weight loss goals, promote improved eating habits, and serve as a reminder to stay focused and motivated towards reaching weight loss goals. |
| US09292782B2 |
Adaptive NFC transceivers
Exemplary embodiments are directed to a transceiver having an adaptive matching circuit. A transceiver may include a matching circuit that is coupled to an antenna and includes an adjustable capacitor. The transceiver may further include an envelope detector coupled to the antenna and a sensor for sensing a voltage at an output of the envelope detector. |
| US09292780B2 |
Controllable RFID card
Systems and methods for providing personalized information are provided. Based on an identification of a customer through the use of a card, personalized information is selectively produced and wirelessly provided to a display such as a wireless display. The identification of the customer, as well as additional information, can be provided through the use of the card, wherein functions of the card can be enabled or disabled by the customer through the use of on-card switches, buttons, slides and/or bistable domes. |
| US09292778B2 |
Output system, output method, and output apparatus
An output system includes a terminal apparatus, an output apparatus, and an information processing apparatus that are interconnected via a network. The output system includes a unit that registers an output request for output data received from the terminal apparatus that is operated by a registering user, a unit that displays information on the registering user that has designated an outputting user operating the output apparatus as a delegate user and receives a selection of the registering user from the outputting user, a unit that receives from the output apparatus an acquisition request for the output request of the selected registering user and provides the requested output request to the output apparatus, and a unit that receives a selection of the output request from the outputting user, acquires the output data of the selected output request, and outputs the acquired output data at the output apparatus. |
| US09292776B2 |
Information processing system, printing apparatus, and information processing method
Each of controllers includes an error management section that generates an error command including an error code indicating the content of an error when the controller detects the error. A host apparatus includes a host controller. If the error command from the master controller and the error command from the slave controller are identical to each other, the host controller displays a single piece of error information on a monitor. Specifically, the single piece of error information includes the error code included in the error command and an error message corresponding to the error code. |
| US09292775B2 |
Image forming apparatus and power supply control method for switching between a main power supply and an auxiliary power supply
An image forming apparatus includes a power supply control unit that controls switching a power source to an auxiliary power supply that stores therein power from a main power supply when the main power supply is off, and to the main power supply when the main power supply is on; a detection unit that detects whether the power source is the main or the auxiliary power supply; a communication mode control unit that switches a data transfer rate from a first high-speed mode to a first low-speed mode allowing power consumption lower than the first high-speed mode when the power source is the auxiliary power supply; and a print mode control unit that switches a print speed from a second high-speed mode to a second low-speed mode allowing the power consumption lower than the second high-speed mode when the power source is the auxiliary power supply. |
| US09292774B2 |
Image forming apparatus, image forming method
An image forming apparatus comprises a printing unit that performs a double-sided print for a plurality of pages and a deletion unit that deletes data of a page that the printing unit prints. The deletion unit, in a case where a page printed last by the printing unit out of the plurality of pages is an odd page counting from the first page in a print order, does not delete but stores data of the page printed last. |
| US09292771B2 |
Image forming apparatus, and method capable of compositing color images with a unit that color-converts and then compresses each of the plurality of pieces of image data
An image forming apparatus is capable of compositing a plurality of pieces of image data. The image forming apparatus includes a color conversion and compression unit, an expansion and composition unit, and an image forming unit. The color conversion and compression unit color-converts and then compresses each of the plurality of pieces of image data in units of band data, the band data being part of the image data. The expansion and composition unit expands and composites, in units of the band data, the plurality of pieces of image data color-converted and then compressed in units of the band data by the color conversion and compression unit. The image forming unit forms an image on the basis of the band data composited by the expansion and composition unit. |
| US09292767B2 |
Decision tree computation in hardware utilizing a physically distinct integrated circuit with on-chip memory and a reordering of data to be grouped
A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface. |
| US09292766B2 |
Techniques for ground-level photo geolocation using digital elevation
Techniques for generating cross-modality semantic classifiers and using those cross-modality semantic classifiers for ground level photo geo-location using digital elevation are provided. In one aspect, a method for generating cross-modality semantic classifiers is provided. The method includes the steps of: (a) using Geographic Information Service (GIS) data to label satellite images; (b) using the satellite images labeled with the GIS data as training data to generate semantic classifiers for a satellite modality; (c) using the GIS data to label Global Positioning System (GPS) tagged ground level photos; (d) using the GPS tagged ground level photos labeled with the GIS data as training data to generate semantic classifiers for a ground level photo modality, wherein the semantic classifiers for the satellite modality and the ground level photo modality are the cross-modality semantic classifiers. |
| US09292765B2 |
Mapping glints to light sources
The technology disclosed herein provides various embodiments for mapping glints that reflect off from an object to light sources responsible for the glints. Embodiments disclosed herein are able to correctly map glints to light sources by capturing just a few images with a camera. Each image is captured while illuminating the object with a different pattern of light sources. A glint free image may also be determined. A glint free image is one in which the glints have been removed by image processing techniques. |
| US09292763B2 |
System, method, and medium for image object and contour feature extraction
A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row. |
| US09292760B2 |
Apparatus, method, and non-transitory computer-readable medium
An apparatus comprises a determination unit configured to determine, based on a region that satisfies a predetermined condition in an image as a candidate of an output target, whether to set the region as the output target; and a decision unit configured to, in a case where a plurality of regions that satisfy the predetermined condition exists in the image, decide a portion of the image including one or a plurality of regions determined, out of the plurality of regions, as the output target by said determination unit as a portion of the output target. |
| US09292758B2 |
Augmentation of elements in data content
A system and method are disclosed for processing data content. Received data content comprises a scene and includes one or more recognized objects. The recognized object(s) include various characteristics, and can be detected and tracked during content capture. The data content can then be stored, and incorporated with metadata associated with the recognized object and/or one or more other elements in the data content. User inputs can be enabled in real-time, or post-capture, to augment one or more of the elements in the stored data content, including one or more characteristics of the recognized object. The data content can then be augmented to introduce one or more augmented elements, corresponding to respective elements of the data content, into the data content based on the user inputs. |
| US09292756B2 |
Systems and methods for automated image cropping
Systems and methods in accordance with embodiments of the invention automatically crop images based upon the location of one or more regions of interest (ROIs) identified within the cropped image. In one embodiment, an image cropping application configures a processor to utilize at least one object detector to identify at least one region of interest within an image. A plurality of candidate cropped images within the image are selected and for each candidate cropped image, an output is generated by weighting each of the at least one region of interest contained within the candidate cropped image as a function of its position within the candidate cropped image. A crop location can then be selected based upon the candidate cropped image having the largest output. |
| US09292753B2 |
Parallel face detection and tracking system
The present disclosure is directed to a parallel face detection and tracking system. In general, embodiments consistent with the present disclosure may be configured to distribute the processing load associated with the detection and tracking of different faces in an image between multiple data processors. If needed, processing load balancing and/or protective features may be implemented to prevent the data processors from becoming overwhelmed. In one embodiment, a device may comprise, for example, a communication module and at least one processing module. The communication module may be configured to receive at least image information that may be processed by a plurality of data processors in the data processing module. For example, each of the data processors may be configured to detect faces in the image information and/or track detected faces in the image information based on at least one criterion. |
| US09292750B2 |
Method and apparatus for detecting traffic monitoring video
The present invention provides a method and an apparatus for detecting a traffic monitoring video. The method comprises: determining a background reference model; determining a target area image in the traffic monitoring video according to the background reference model; updating the background reference model by using the target area image; summating all target points in detection area of each frame of image in the traffic monitoring video according to the updated background reference model to obtain a total area of all the target points; segmenting the frame with the biggest total area to obtain a target area at the best position; and extracting vehicle information from the target area at the best position. By using the present invention, the accuracy of a detection result in a complex environment may be improved. |
| US09292749B2 |
Biometric matching technology
Biometric matching technology, in which a watch list is managed, multiple images of a potential suspect are accessed, and parallel pre-processing of the multiple images is controlled. Based on the pre-processing, an image of the potential suspect to use in matching against the watch list is determined and the determined image is used to search sorted biometric data included in the watch list. A subset of persons from the watch list is identified based on the search and parallel analysis of the determined image of the potential suspect against detailed biometric data associated with the subset of persons in the watch list is controlled. Based on the parallel analysis, it is determined whether the potential suspect matches a person in the watch list and a result is outputted based on the determination. |
| US09292748B2 |
Information processing apparatus and information processing method
An information processing apparatus comprises a storage module configured to store feature amounts of standard commodities; an image capturing module configured to photograph a commodity to capture an image of the commodity; an extraction module configured to extract feature amount of the commodity from the image captured by the image capturing module; a calculation module configured to calculate a similarity degree by comparing the feature amount of a standard commodity which is determined as a recognition target in setting information in which a standard commodity serving as a recognition target is set within the standard commodities stored in the storage module with the feature amount of the commodity extracted by the extraction module; and a recognition module configured to recognize a standard commodity of which the similarity degree calculated by the calculation module is greater than a threshold value as a candidate of the commodity. |
| US09292742B2 |
2D and 3D ion intensity image generating apparatus, method, and computer readable storage medium
An image generating apparatus capable of facilitating analysis of a substance having a repeating structure has: an ion intensity data acquisition portion for acquiring ion intensity data arising from the substance, the data including information about a relative intensity of each ion against mass-to-charge ratio; a mass information acquisition portion for acquiring mass information about the repeating unit of the substance; a data alignment portion for aligning the ion intensity data within each given range of mass-to-charge ratios based on the mass information about the repeating unit of the substance; and an image generation portion for generating an image based on the aligned ion intensity data. |
| US09292739B1 |
Automated recognition of text utilizing multiple images
Various embodiments enable text aggregation from multiple image frames of text. Accordingly, in order to stitch newly scanned areas of a document together, text in a respective image is recognized and analyzed using an algorithm to identify pairs of corresponding words in other images. Upon identifying a minimum number of matching pairs between two respective images, a mapping between the same can be determined based at least in part on a geometric correspondence between respective identified pairs. Based on this mapping, the recognized text of the two images can be merged by adding words of one image to the other using the matching word pairs as alignment data points. |
| US09292737B2 |
Systems and methods for classifying payment documents during mobile image processing
Systems and methods are provided for processing an image of a financial payment document captured using a mobile device and classifying the type of payment document in order to extract the content therein. These methods may be implemented on a mobile device or a central server, and can be used to identify content on the payment document and determine whether the payment document is ready to be processed by a business or financial institution. The system can identify the type of payment document by identifying features on the payment document and performing a series of steps to determine probabilities that the payment document belongs to a specific document type. The identification steps are arranged starting with the fastest step in order to attempt to quickly determine the payment document type without requiring lengthy, extensive analysis. |
| US09292736B2 |
Methods and apparatus to count people in images
Methods and apparatus to count people in images are disclosed. An example method includes analyzing frame pairs of a plurality of frame pairs captured over a period of time to identify a redundant person indication detected in an overlap region, the overlap region corresponding to an intersection of a first field of view and a second field of view; eliminating the identified redundant person indication to form a conditioned set of person indications for the period of time; grouping similarly located ones of the person indications of the conditioned set to form groups; analyzing the groups to identify redundant groups detected in the overlap region; and eliminating the redundant groups from a people tally generated based on the groups. |
| US09292729B2 |
Method and software for analysing microbial growth
A method for analysing microbial growth on a solid culture medium, the method including obtaining image data of the solid culture medium and any microbial growth, generating an associated feature vector of values obtained by applying one or more filters to the image data, using a classifier to classify each pixel in a plurality of pixels in the image data based on the associated feature vector, analysing results of pixel classifications of each said pixel to derive a microbiological assessment of the solid culture medium and any microbial growth, and outputting the microbiological assessment. |
| US09292725B2 |
Method and system for detecting 2D barcode in a circular label
The present disclosure relates to a method and system for identifying and reading a barcode on a circular label. Such method and system, in the embodiment discussed, is concretely addressed to a specific example in the engineering of a barcode reader in an electromechanical system for biological analyzes which uses cone-shaped tubes and corresponding strips of fluid containers. It is a requirement of the system that the right cone matches with the right strip. In order to avoid any human error, barcode reading system is implemented, by placing a barcode (e.g. a 2D barcode) on the cone-shaped tube and a barcode on the strip: however the particular shape of the cone poses some problems in the automatic localization and reading of the barcode on the circular label on top of the cone. An additional difficulty of the present system is that of the inclination of barcode reader with respect to the circular label carrying the code, due to the relative positioning of the various components of the machine which does not allow a straight alignment between the reader and the target. With the method according to a preferred embodiment of the present disclosure the circular label is scanned to detect the 2D barcode and it is then read, with a simplified algorithm requiring limited power and hardware resources. |
| US09292720B2 |
RFID converter module
A tag communication method includes providing a tag reader operating at a first frequency and having transmit and receive antenna ports, providing a frequency converter module having transmit and receive plugs adapted to directly mate with the transmit and receive ports, and directly mating the transmit plug with the transmit port and the receive plug with the receive port. A transmit signal at the first frequency is received from the reader by the converter module by way of the directly mated transmit plug and converted to a second frequency differing from the first frequency to provide a converted transmit signal which is transmitted to the tag. A receive signal is received from the tag at the second frequency and converted to the first frequency to provide a converted receive signal which is applied by the conversion module to the reader by way of the directly mated receive plug. |
| US09292719B2 |
RFID apparatus calibration
Calibrating an RFID apparatus includes: positioning the RFID apparatus within a distance of an RFID tag array, the RFID apparatus having an RFID antenna to detect RFID tags and at least one motion sensing device; aligning the RFID apparatus with the RFID tag array using the motion sensing device; acquiring (i) RFID tag information including signal strength using the RFID antenna to generate an RFID antenna radiation pattern that includes a region of at least one RFID tag exceeding a signal strength, and (ii) position information of the RFID tag in the RFID tag array; and determining calibration values of the RFID apparatus based on a one or more alignment differences between the acquired region of the RFID tag information and the position information of the motion sensing device; adjusting the RFID apparatus scan path data acquired from the at least one motion sensing device using the determined calibration values. |
| US09292717B2 |
Apparatus for forming and reading an identification feature and method thereof
The present invention refers to an apparatus for forming and reading an identification feature on or in an object. The apparatus comprises a formation unit for physically forming an identification feature on or in an object, at least one reading unit adapted to read the identification feature to form a signature, and a housing, wherein the formation unit and the at least one reading unit are both contained in the housing. The at least one reading unit can comprise at least two reading elements. The identification feature can comprise an identification feature based on inherent disorder. The invention also refers to a method of forming and reading an identification feature on or in an object. |
| US09292712B2 |
Method and apparatus for maintaining secure time
An exemplary method of maintaining secure time in a computing device is disclosed in which one or more processors implements a Rich Execution Environment (REE), and a separate Trusted Execution Environment (TEE). The TEE maintains a real-time clock (RTC) that provides a RTC time to the REE. A RTC offset is stored in non-volatile memory, with the RTC offset indicating a difference between the RTC time and a protected reference (PR) time. Responsive to a request from the REE to read the RTC time, a current RTC time is returned to the REE. Responsive to a request from the REE to adjust the RTC time, the RTC time and the corresponding RTC offset are adjusted by a same amount, such that the PR time is not altered by the RTC adjustment. An exemplary computing device operable to implement the method is also disclosed. |
| US09292708B2 |
Protection of interpreted source code in virtual appliances
Protection of interpreted programming language code filesystem files from access and alteration may be provided by encrypting a file to be protected in a boot sequence. Run-time examination of a virtual appliance may be deterred by hiding the boot sequence in a restricted virtual appliance platform. No shell or filesystem access may be provided. Thus, permissions on a read-only filesystem (for example) may be kept from being altered. The permissions may be set along with filesystem access control lists to prevent unauthorized examination of the source files. |
| US09292705B2 |
Management of drone operations and security in a pervasive computing environment
A method to provide negotiation control to data such that a person or entity can negotiate the use of data gathered beyond what is needed for a particular use by a third party transaction. The method also provides negotiation for the control and operation of autonomous vehicles such as drones operating in non-public space. |
| US09292704B2 |
Information processing device for detecting an illegal stored document, illegal stored document detection method and recording medium
The present invention provides an information processing device which can detect illegal authorization setting efficiently in a short period of time. The information processing device includes a database which stores electronic documents, a means for storing rank values of users of the database, a means for storing the authorization degree of an electronic document or an electronic document group and authorization degrees of respective document classes of the database, a means for analyzing the electronic documents and combining together documents having mutual similarity in a degree equal to or higher than a certain level into a similar document group, and a means for analyzing authorization degrees of respective document classes in the database with reference to the rank values of the users, and thus detecting an electronic document or an electronic document group whose authorization setting is improper. |
| US09292703B2 |
Electronic document management method
Methods of managing electronic documents that can be implemented by a server in a telecommunications network are described. One method includes a receiving step of receiving a request from a client device, said request containing at least a user identifier and an electronic document name; an obtaining step of obtaining from the document name a secret identifier of at least one field of said document; a checking step of verifying from the user identifier and the secret field identifier whether a content associated with said field may be sent to the client device in response to the request; and where appropriate a sending step of sending said content to the client device. |
| US09292700B2 |
Method and system for securing data
A method for securing user data includes the steps of: a) setting the user data as input data; b) randomly fragmenting the input data into a plurality of Atoms and randomly distributing the Atoms into an AtomPool and an AtomKey; and c) recording information about the fragmentation and the distribution of step b) into an AtomMap. |
| US09292696B1 |
System and method to anonymize data transmitted to a destination computing device
A method and system for anonymizing data to be transmitted to a destination computing device is disclosed. Data to be transmitted is received from a user computer. The data includes a plurality of fields of data. One or more fields of data are selected for anonymization. The selected one or more fields are anonymized. The data with one or more fields anonymized is transmitted to the destination computing device. |
| US09292694B1 |
Privacy protection for mobile devices
Described systems and methods allow a mobile device, such as a smartphone or a tablet computer, to protect a user of the respective device from fraud and/or loss of privacy. In some embodiments, the mobile device receives from a server a risk indicator indicative of whether executing a target application causes a privacy risk. Determining the risk indicator includes automatically supplying a test input to a data field used by the target application, the data field configured to hold a private item such as a password or a geolocation indicator. Determining the risk indicator further comprises determining whether a test device executing an instance of the target application transmits an indicator of the test input, such as the test input itself or a hash of the test input, to another party on the network. |
| US09292687B2 |
Detecting file encrypting malware
A method in a computer for detecting a file encryption attack. The computer detects an attempt to overwrite current file data of a file with new file data. The computer then compares the new file data to the current file data to obtain a measure of the difference between the current and the new file data, and if the difference exceeds a threshold, the computer considers this to identify a file encryption attack. |
| US09292686B2 |
Micro-virtualization architecture for threat-aware microvisor deployment in a node of a network environment
A micro-virtualization architecture deploys a threat-aware microvisor as a module of a virtualization system configured to facilitate real-time security analysis, including exploit detection and threat intelligence, of operating system processes executing in a memory of a node in a network environment. The micro-virtualization architecture organizes the memory as a user space and kernel space, wherein the microvisor executes in the kernel space of the architecture, while the operating system processes, an operating system kernel, a virtual machine monitor (VMM) and its spawned virtual machines (VMs) execute in the user space. Notably, the microvisor executes at the highest privilege level of a central processing unit of the node to virtualize access to kernel resources. The operating system kernel executes under control of the microvisor at a privilege level lower than a highest privilege level of the microvisor. The VMM and its spawned VMs execute at the highest privilege level of the microvisor. |
| US09292685B2 |
Techniques for autonomic reverting to behavioral checkpoints
Aspect methods, systems and devices may be configured to create/capture checkpoints without significantly impacting the performance, power consumption, or responsiveness of the mobile device. An observer module of the mobile device may instrument or coordinate various application programming interfaces (APIs) at various levels of the mobile device system and constantly monitor the mobile device (via a low power process, background processes, etc.) to identify the normal operation patterns of the mobile device and/or to identify behaviors that are not consistent with previously computed normal operation patterns. The mobile device may store mobile device state information in a memory as a stored checkpoint when it determines that the mobile device behaviors are consistent with normal operation patterns, and upload a previously stored checkpoint to a backup storage system when it determines that the mobile device behaviors are not consistent with normal operation patterns. |
| US09292682B2 |
Accessing a second web page from a dispersed storage network memory based on a first web page selection
A method begins, when a second web page is selected based on an element of a first web page, with a dispersed storage (DS) processing module determining dispersed storage network (DSN) location information for the second web page. The method continues with the DS processing module interpreting the DSN location information to request retrieval of a plurality of sets of at least a decode threshold number of encoded data slices from a DSN. The method continues with the DS processing module decoding, using a DS error coding function, a set of the plurality of sets of the least the decode threshold number of encoded data slices to reproduce an element of the second web page. |
| US09292679B2 |
Regulating access to and protecting portions of applications of virtual machines
Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed. |
| US09292669B2 |
Method and apparatus for inputting password in electronic device
A method inputs a password in an electronic apparatus. In the method, whether an authentication number input request corresponding to a password exists is determined. When the authentication number input request exists, a screen for requiring input of an authentication query number and a corresponding authentication number is displayed. Whether the input authentication number and the input authentication query number match with each other is determined. When they match with each other, relevant approval screen or a relevant function is entered. Since a specific authentication number with respect to a specific authentication query number among a plurality of authentication query numbers is used with a general number or character in a combined manner, a password may be kept safe even when exposed and so use convenience is provided. |
| US09292667B1 |
Location based community
Disclosed are various embodiments for facilitating a location based community. A location associated with a user is identified, as are point of interest in proximity to the location. A question can be received from a user that is related to a point of interest, which can be routed to other users who may be in the same or similar location or have an expertise in a particular subject matter area related to the question. |
| US09292663B2 |
Associating first and second watermarks with audio or video content
The present invention relates generally to processing audio or video content. One claim recites a system comprising: a portable device comprising storage and an electronic logic processor, the electronic logic processor configured for analyzing first content stored in said storage to detect a first class of watermarking hidden therein, the first class of watermarking comprising a link between the first content and a user, the first content further comprising a second class of watermarking, the second class of watermarking providing an indication that the first content is protected, in which the second class of watermarking is more difficult to remove from content relative to the first class of watermarking; and a software module for interacting with content files, said software module including instructions to cause an electronic logic processor to control transfer of the first content file to said portable device based on detection and interpretation of the second class of watermarking. Other claims and combinations are provided as well. |
| US09292662B2 |
Method of exploiting spare processors to reduce energy consumption
A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency. |
| US09292661B2 |
System and method for distributing rights-protected content
Various embodiments of a method and system for a content distribution mechanism. A content distribution mechanism is implemented to receive rights-protected content. Access to the rights-protected content is controlled according to a policy via a policy server. The distribution mechanism may receive an attempt to forward the rights-protected content to one or more recipients that do not currently have access to the rights-protected content. The distribution mechanism may hold the document and send a message requesting access rights to the rights-protected content for the recipient(s). In some embodiments, the distribution mechanism may send the message to a policy server. In other embodiments, the distribution mechanism may send the message to a policy administrator. Upon receiving acknowledgement that the recipient(s) have been granted access rights to the content, the distribution mechanism may forward the rights-protected content to the recipient(s). |
| US09292649B2 |
Different scaling ratio in FEOL / MOL/ BEOL
The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section. |
| US09292647B2 |
Method and apparatus for modified cell architecture and the resulting device
A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings. |
| US09292645B2 |
Layout optimization for integrated circuit design
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. |