最新美国发明专利第2016-03-08期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09282116B1	System and method for preventing DOS attacks utilizing invalid transaction statistics A method and network traffic management device to protect a network from network based attacks is disclosed. The method comprises receiving, at a network traffic management device, a plurality of requests from a plurality of client devices for one or more resources from one or more servers. The method comprises monitoring a number of server responses including an invalid transaction message for a particular client device or a particular requested resource. The method comprises comparing a ratio of invalid transactions to valid transactions for the particular client device or requested resource to a preestablished ratio threshold value. The method comprises marking the particular client device or requested resource as suspicious when the ratio exceeds the ratio threshold value. The method comprises preventing the suspicious particular client device or requested resource from being transmitted to the one or more servers when the network traffic management device detects a network attack.
US09282109B1	System and method for analyzing packets A system is provided with an interface and controller. The interface is configured to receive packets transmitted over a network between a first device and a second device. Transmitted over the network in accordance with a packet protocol, the packets include at least one packet transmitted from the first device and at least one packet transmitted from the second device. Coupled to the interface, the controller is configured to determine whether a plurality of packets have suspicious characteristics of malware and transmit the suspicious packets to an analysis environment. The analysis environment is configured to receive the plurality of packets that have suspicious characteristics of malware, modify at least a portion of these suspicious packets, and transmit at least the modified portion of the plurality of packets that have suspicious characteristics of malware to a virtual machine in accordance with a sequence of the packet protocol.
US09282108B2	Generalized certificate use in policy-based secure messaging environments Within a secure messaging environment, a determination is made that a request to send a message has been generated by a user. A message protection policy configured to process the message within the secure messaging environment is identified. The message protection policy specifies that, within the secure messaging environment, a secured digital certificate, other than a user-assigned digital certificate of the user, is configured with an associated private key to digitally sign the message on behalf of the user. Based upon the message protection policy, a determination is made to digitally sign the message using the private key of the secured digital certificate. The message is signed on behalf of the user using the private key of the secured digital certificate.
US09282104B2	Access management service system and method for controlling same, and non-transitory computer readable medium An access management service system that manages use of a service provided by a resource service system, comprises: a holding unit which holds information of a user and information of a client system in a storage unit; a determination unit which, if an authorization request for use of the service is received from the client system due to an instruction from a user having authority to use the service, determines whether a group to which the user belongs and a group to which the client system belongs match based on the information held in the storage unit; and a presentation unit which, if the determination unit determines that the groups match, presents, to the user, a screen for instructing whether or not to permit delegation of the authority of the user to the client system.
US09282103B2	Restriction lists for remote video transfer A method of granting a client device remote access to a media server after receiving a port request from a remote client device at a residential gateway through an intermediate remote access control server by opening one or more wide area network ports temporarily mapped to local area network ports, such that the remote client device can communicate with the media server through the wide area network ports, transmitting a list of the one or more wide area network ports to the remote client device through the remote access control server, receiving a media content request from the remote client device and passing the media content request to the media server through the one or more wide area network ports, and passing media content from the media server to the remote client device through the one or more wide area network ports according to one or more restriction lists.
US09282101B2	Multimedia message service method and system Disclosed is a method of sharing multimedia contents, by a server, including storing the multimedia contents, receiving an establishment request configured to establish one of a plurality of access modes for the multimedia contents from a first terminal, establishing an access mode according to the establishment request for the multimedia contents, receiving an access request for the multimedia contents stored in the server from at least one second terminal, determining whether the at least one second terminal is allowed to access the multimedia message based on the access mode, and transmitting the multimedia contents, wherein the access mode includes at least one of a private mode for access by only the first terminal, a restricted mode for access by the at least one second terminal, and a public mode for access by all terminals.
US09282100B2	Privilege separation In one implementation, an interposer library is installed on an embedded system or another type of computing system. The system may be configured to host web services or route data packets. A processor, executes processes of the system, and the interposer library intercepts data indicative of relationships of the processes. An access map is generated based on relationships of the processes of the system. The system is modified according to a set of procedures derived from the access map. The set of procedures may be derived by the processor or the access map. The set of procedures may be a minimum privilege solution that minimizes the privilege level of each process to a lowest privilege possible while maintaining the requisite functions of the process.
US09282095B2	Security and privacy enhancements for security devices A tamper-resistant security device, such as a subscriber identity module or equivalent, has an AKA (Authentication and Key Agreement) module for performing an AKA process with a security key stored in the device, as well as means for external communication. The tamper-resistant security device includes an application that cooperates with the AKA module and an internal interface for communications between the AKA module and the application. The application cooperating with the AKA module is preferably a security and/or privacy enhancing application. For increased security, the security device may also detect whether it is operated in its normal secure environment or a foreign less secure environment and set access rights to resident files or commands that could expose the AKA process or corresponding parameters accordingly.
US09282094B1	Transparent adaptive authentication and transaction monitoring Enhanced security processes are integrated into online service provider workflow activities in a transparent fashion with little or no impact on the servers. Enhanced security processes may include adaptive authentication and transaction monitoring. The enhanced security processes are partially implemented in a network device, such as a network communication device, a firewall, or a load balancing system, or a separate security device, rather than being implemented in the server systems hosting on-line websites. With such an arrangement, server software is minimally modified or rewritten, and third party software, such as security applications, remains in operation.
US09282093B2	Synchronizing credential hashes between directory services The subject disclosure is directed towards securely synchronizing passwords that are changed at a source location (e.g., an on-premises directory service) to a target location (e.g., a cloud directory service), so that the same credentials may be used to log into the source or target location, yet without necessarily having each domain controller handle the synchronization. The plaintext password is not revealed, instead using hash values computed therefrom to represent the password-related data. The target may receive a secondary hash of a primary hash, and thereby only receive and store a password blob. Authentication is accomplished by using the same hashing algorithms at the target service to compute a blob and compare against the synchronized blob. Also described are crypto agility and/or changing hashing algorithms without requiring a user password change.
US09282090B2	Methods and systems for identity verification in a social network using ratings The disclosed embodiment relates to identity verification and identity management, and in particular, to methods and systems for identifying individuals, identifying users accessing one or more services over a network, determining member identity ratings, and based on member identity ratings that restrict access to identity rating-restricted services and certain user-to-user interactions. Further, the user experience in performing identity management is simplified and enhanced as disclosed herein.
US09282087B1	System and methods for reviewing user generated content and providing authorization Systems and methods for providing authorization of user-generated content are described, including a computer-implemented method for providing content by a first user is provided, including receiving, by one or more computing devices, content from the first user, analyzing context data associated with the content received from the first user, providing the content received from the first user to an authorizer based on a result of the analyzing the context data associated with the content, and providing the content of the first user to a second user in response to receiving an authorization from the authorizer.
US09282081B2	Reduced traceability electronic message system and method An electronic messaging system and method with reduced traceability. An electronic message is separated into a message content and container (header) information. In one aspect, the message content and header information are entered by a user separately using a single display image screen having separate portions for entry of message content and header information. The separate portions do not allow visibility of content in the portions to be displayed at the same time.
US09282078B2	Managing domain name abuse A computer-implemented method for automatically responding to domain name abuse is described. The method comprises the following steps. A plurality of disparate abuse feeds are received from a plurality of service providers. Each of the service providers is configured to collect information regarding a subset of potential domain name abuse and each abuse feed comprises data identifying domain names associated with the subset of potential domain name abuse. The data is filtered to create a custom abuse feed comprising a selective portion of the plurality of disparate abuse feeds. The filtered data from the custom abuse feed is grouped into groups of data based on predefined priority levels of the filtered data. For each of the groups of data, one or more corresponding workflows is executed as a response to the potential domain name abuse, wherein the workflow includes temporarily suspending a domain associated with the potential domain name abuse.
US09282076B2	Aligning content and social network audience using analytics and/or visualization Various embodiments provide for the use of analytics to determine a number of key factors prior to a user sending a communication (e.g., an email or instant message, making an online social media post, or accepting or requesting friendship on a social media site). The analytics may determine content, subject, emotion, relationships, and other relevant details when users interact (e.g., with email or other social software). Any alerts/suggestions provided can be provided in real-time as the person types.
US09282071B1	Location based message discovery A method, computer program product, and computer system for receiving a message from a first user associated with a network, wherein the message is associated with a location. A notification is sent to a second user associated with a network that the message is available for viewing. Whether the second user is at the location is determined. A computing device associated with the second user is enabled to view only a portion of the message based upon determining that the second user is not at the location. The computing device associated with the second user is enabled to view the message in full based upon determining that the second user is at the location.
US09282068B1	Collaborative streaming of video content A system, method and various user interfaces enable visually browsing multiple groups of video recommendations. A video stream includes a group of videos to be viewed and commented by users who join the stream. Users who join a stream form a stream community. In a stream community, community members can add videos to the stream and interact collaboratively with others community members, such as chatting in real time with each other while viewing a video. With streams, a user can create a virtual room in an online video content distribution environment to watch videos of the streams and interact with others while sharing videos simultaneously. Consequently, users have an enhanced video viewing and sharing experience.
US09282065B2	Relay unit A relay unit includes a main-system switch and a sub-system switch that are connected to each other via an inter-system line, that are connected to a main-system line and a sub-system line, and that relays a frame; and control sections that control a relay operation of the main-system switch and the sub-system switch. The control sections store information on a number of connections of relay units and information on a connection priority, and select a control aspect of the relay operation of at least one of the main-system switch and the sub-system switch according to the number of connections and the connection priority.
US09282064B2	Method for processing a plurality of data and switching device for switching communication packets The invention concerns a method of processing a plurality of data packets in a packet switched communication network comprising at least one switching device (1) as well as a corresponding switching device. The switching device (1) comprises two or more sub-engines (21, . . . , 29). A control unit (7) of the at least one switching device (1) receives a data packet comprising a header (10) of a communication packet exchanged via the communication network. The control unit (7) applies at least one filter operation (50) to the header (10) and generating thereby filtered information (100). The control unit (7) maps the filtered information (100) on a hash-tag (30) according to a hash-function (300). The control unit (7) provides a tagged-header (11) by means of inserting the hash-tag (30) in the header (10) of the data packet. The control unit (7) sends the data packet to a sub-engine (24) of the two or more sub-engines (21, . . . , 29) according to the tagged-header (11) for further processing of the data packet.
US09282061B1	Systems and methods for handling ARP messages in modular network devices A system for handling address resolution protocol (ARP) messages has a plurality of communication modules for communicating via a network. Each such communication module has a separate link layer address (e.g., MAC address). Control logic in communication with each of the modules serves as an ARP proxy for the modules. Rather than using its own link layer address in the overhead of the ARP messages, the control logic uses the link layer addresses of the communication modules, thereby causing the network to learn these link layer addresses during ARP processing. Therefore, once ARP messaging between a communication module and a remote network device has been performed, the network has established a data path between the communication module and the remote network device, thereby helping to prevent or reduce message flooding when the two devices begin to communicate.
US09282057B2	Flexible stacking port A stackable device having a plurality of data ports, wherein each of the data ports is capable of operating as a regular data port or a stacking port. A first set of one or more of the data ports is specified as a first flexible stacking port, and a second set of one or more of the data ports is specified as a second flexible stacking port. Each flexible stacking port can be individually configured to operate as an actual stacking port, if required by the configuration of an associated stack. If a flexible stacking port is not configured to operate as an actual stacking port, then the data port(s) included in the flexible stacking port are available to operate as regular data port(s).
US09282056B2	Metrics and forwarding actions on logical switch partitions in a distributed network switch Techniques are provided for providing access control lists in a distributed network switch. The distributed network switch made of switch units is divided into logical switch partitions, or logical networks. Physical ports of the switch units are partitioned into logical ports, where each logical port is associated with a logical switch partition. A control point of the distributed network switch manages and assigns a service tag (S-Tag) used to identify which logical port ingress and egress frames are associated with. To generate metrics and other forwarding actions for a given logical switch partition, the control point sets up access control list (ACLs) targeting the logical port associated with the S-Tags associated with the given logical switch partition.
US09282053B1	Techniques for dynamic resource partitioning Described are techniques for partitioning resources. A plurality of resource limit ranges are specified for a plurality of tenants of a system. Each of the plurality of resource limit ranges have a lower bound and an upper bound. A plurality of current resource limits are determined. Each of the plurality of current resource limits indicate a current resource limit for one of the plurality of tenants. Each current resource limit for one of the tenants is a value included in one of the plurality of resource limit ranges specified for the one tenant. The plurality of current resource limits are dynamically determined in accordance with a current state of the system.
US09282047B2	Batching communication events Approaches for aggregating data prior to a transmission of the data to an external system are disclosed. The method includes receiving a data bag. The data bag including data packets destined to be transmitted to an external system. A timer even is then attached to the received data bag and the received data bag is temporarily stored in a data store. The timer event associated with the received data bag is then overridden based on the timer event associated with another data bag in the data store.
US09282046B1	Smoothing FIFO and methods thereof Network device and associated methods are provided. The network device includes a plurality of base-ports, each base-port coupled to a plurality of network links and each base-port includes a plurality of sub-ports configured to operate as independent ports for sending and receiving information. Each network link is coupled to a smoothing first in-first out (FIFO) memory module that is used to temporarily store information at a first clock rate and information is read from the smoothing FIFO at a second clock. A sub-port can include one network link or more than one network link for receiving information from another device. A controller module monitors the smoothing FIFO for each network link to insert or delete characters from each of the smoothing FIFO based on a sub-port configuration for maintaining an order in which information is received for the sub-port.
US09282045B2	Information processing method, information processing circuit, and information processing apparatus A method includes scheduling a packet to be transmitted to a second relay device instead of a first relay device, when a plurality of packets actually transmitted or to be transmitted under a rule, which causes the packets to dispersively pass through different relay devices when destination addresses of the packets are the same, are disproportionally transmitted to the first relay device, and the rule indicates that the packet is to be transmitted to the first relay device.
US09282044B2	System and method for routing electronic content to a recipient device A system and method for routing electronic content to a recipient device comprising a plurality of network nodes, each network node adapted to receive and forward electronic content and an activity profile server adapted to be in data communication with each network node, the activity profile server adapted to monitor the activity level of each network node and inform each network node on the congestion level of an adjacent network node; wherein each network node is adapted, on receiving the information on congestion level to store electronic content if the adjacent network node is congested and forward the electronic content to the adjacent network node if the adjacent network node is not congested is disclosed.
US09282042B2	Node in network including a plurality of nodes In a network including a plurality of nodes, a node transmits data to another node, receives data from another node, and stores a communication history between a plurality of other nodes and the node itself. When an acknowledge response to data transmitted to a first node among the plurality of other nodes is not received, the node generates a duplicate data of the transmitted data. When a duplication report indicating detection of duplicate data transmitted to a second node among the plurality of other nodes has been received from one of the plurality of other nodes, the node refers to the communication history, and identifies the first node as a cause of generation of the duplicate data. Thereafter, the node generates a check request that include a communication history between the first node and the node itself and that requests the first node to check the communication history.
US09282037B2	Table-driven routing in a dragonfly processor interconnect network A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.
US09282035B2	Directed route load/store packets for distributed switch initialization Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments include receiving, at a first switch module, a packet that includes (i) an ordered listing of Ethernet link identifiers, specifying a path to the destination switch module and (ii) payload data to be processed at the destination switch module. Embodiments determine that the first switch module is not a destination of the packet, based on the ordered listing of Ethernet link identifiers. Additionally, an Ethernet port of the first switch module on which to transmit the packet is determined based on the ordered listing of Ethernet link identifiers. Embodiments then transmit the packet to a second switch module using the determined Ethernet port of the first switch module.
US09282032B2	Distributed routing architecture A routing management component is provided for distributing routing information among a hierarchical distributed routing architecture. The routing management component can function to associate levels of the routing architecture with subsets of a network address format. The routing management component can further assign routers of the routing architecture to portions of network addresses defined at least in part by the network address format. For example, a router may be assigned to route packets addressed to a network address with a first octet between a range of values. The router management component may further distribute, to the routers of the hierarchical distributed routing architecture, sections of routing information associated with their assigned portions of network addresses. Because routing information can be distributed between various routers, the memory requirements of individual routers can be reduced comparatively to systems in which a single router maintains an entire set of forwarding information.
US09282030B2	Transport control server that calculates routing information It is intended to shorten the time required for a path recalculation and a path switching upon occurrence of a failure. A path generation unit of a transport control server (TCS) S-1 generates the normal path information in accordance with the topology information of a network and the resource information which are set. Also, the path generation unit generates in advance the backup path information for occurrence of the failure based on the prediction topology information and the prediction resource information which have been modified in accordance with a predicted failure position. The path generation unit stores the generated backup path information in a data storage unit. A path information notification unit of the TCS (S-1) notifies nodes N of the generated normal path information. A failure information acquisition unit of the TCS (S-1) detects the occurrence of the failure. If the failure information acquisition unit detects the occurrence of the failure, the path information notification unit notifies the nodes N of the backup path information stored in the data storage unit.
US09282027B1	Managing use of alternative intermediate destination computing nodes for provided computer networks Techniques are described for managing communications for a managed computer network by using a defined pool of alternative computing nodes of the managed computer network that are configured to operate as intermediate destinations to handle at least some communications that are sent by and/or directed to one or more other computing nodes of the managed computer network. For example, a manager module associated with a source computing node may select a particular alternative intermediate destination computing node from a defined pool to use for one or more particular communications from the source computing node to an indicated final destination, such as based on a configured logical network topology for the managed computer network and/or on one or more other selection criteria (e.g., to enable load balancing between the alternative computing nodes). The manager module then forwards those communications to the selected intermediate destination computing node for further handling.
US09282022B2	Forensics for network switching diagnosis A method for diagnosing performance of a network switch device includes a processor monitoring data generated by a sensor associated with a network switch device, the data related to states or attributes of the network switch device. The processor detects a determined condition in the operation of the network switch device related to the state or attribute. The processor generates an event trigger in response to detecting the determined condition and executes a forensic command in response to the event trigger. Executing the command includes sending information relevant to the determined condition for aggregation in computer storage and for analysis.
US09282010B2	Network management system A technique for communicating in a network management system is disclosed. The technique includes transferring information from an application server to a gateway that processes the information, transferring the gateway processed information from the gateway to a plurality of adapters associated with the gateway that process the gateway processed information, and transferring the adapter processed information from one of the adapters to a client.
US09282009B2	Reservation of resources and deployment of applications using an integrated development environment Systems and methods to reserve resources is provided. In exemplary embodiments, a selection of a profile from a user is received. A dynamic graphical user interface is generated, using one or more processors. The dynamic graphical user interface allows the user to configure a topology based on the selected profile. The dynamic graphical user interface provides input fields in which the user may select a resource. An indication of the selected applicable topology property for configuring the topology is received. A topology is automatically generating based in part on the selected applicable topology property.
US09282004B2	Multi-protocol storage network I/O devices and methods Systems and methods which allow for one or more input/output (I/O) ports residing on a device in a storage network environment to be reconfigured in order to communicate using different protocols are provided. Embodiments may provide for dynamic reconfiguration of an I/O port while the device including the port is deployed in the storage network. In some instances, such reconfiguration may be managed locally and/or by a remote management processing resource in the storage network. In some embodiments, reconfiguration of an I/O port to communicate in a different protocol may be implemented, either manually or automatically, based on observed traffic data.
US09282000B1	Network devices having configurable receive packet queues and related methods Method and system for configuring a port of a network device are provided. One method for a port of a network device communicating with another network device port includes reading manufacturing, license and user provided port configuration data by a processor of the network device; obtaining capabilities information for the port by the processor of the network device from an external pluggable media device; setting port configuration data based on the capabilities information obtained from the external pluggable media; executing auto-negotiation on the port, when enabled and obtaining configuration data from the other port; determining that enough data is available to set port configuration; attempting to configure the port by using a highest permissible bandwidth configuration when enough data is available to set the port configuration; and setting port configuration based on the attempt to configure the port to operate when a link connected to the port is operational.
US09281991B2	Media streaming A system and associated method for minimizing network traffic in playing a media stream with a media module running in a client computer system. The media stream is stored in a media content server. A video file of the media stream is processed to generate an audio file corresponding to the video file, such that the media module downloads and plays the audio file when the media module is invisible on a computer screen of the client computer system. When the media module becomes visible, the media module switches back to downloading and playing the video file. A current location is tracked by a location sync file stored in the media content server to synchronize the video file and the audio file.
US09281990B2	Ethernet UDP checksum compensation In the methods and devices of the present disclosure, a dummy compensation word is added to the data packet such that the UDP checksum value need not be modified from any previous value, regardless of changes to the UDP payload. Because the UDP checksum value is not modified in embodiments of the present disclosure, there is no delay waiting for a UDP checksum value to be calculated and no need for additional buffers to store the data packet contents because of UDP checksum calculations. The dummy compensation word is calculated so that the unmodified value maintained in the checksum is the checksum for the data packet including the dummy compensation word. By placing the compensation word in the data packet after the last word in the UDP payload, there is no, or very minimal, processing delay and data packet buffering hardware is significantly reduced.
US09281984B2	Application of sequence hopping and orthogonal covering codes to uplink reference signals Methods and apparatuses are provided for transmitting and receiving references signals. A method includes receiving a first cell specific parameter; receiving a second UE specific parameter; receiving a CSI; acquiring a first reference signal for a PUSCH, based on the second parameter and the CSI; acquiring a second reference signal for a PUCCH, based on the first parameter; and transmitting at least one of the first reference signal and the second reference signal. Group sequence hopping is not applied to acquire the first reference signal, if the first parameter indicates that the group sequence hopping is enabled and the second parameter indicates that the group sequence hopping is disabled. The group sequence hopping is applied to acquire the second reference signal, if the first parameter indicates that the group sequence hopping is enabled and the second parameter indicates that the group sequence hopping is disabled.
US09281982B2	Application of sequence hopping and orthogonal covering codes to uplink reference signals Methods and apparatuses are provided for transmitting and receiving references signals. A method includes receiving a first parameter and a second parameter, which are cell specific parameters; receiving a third parameter, which is a UE specific parameter; acquiring the reference signal for a physical uplink shared channel (PUSCH), based on the third parameter; and transmitting the reference signal on the PUSCH. Sequence hopping and group sequence hopping are disabled for the reference signal, regardless of values of the first parameter and the second parameter, if the third parameter indicates that the sequence hopping and the group sequence hopping are disabled. The sequence hopping includes hopping between two sequences in a group, and the group sequence hopping includes hopping among different groups.
US09281977B2	Apparatus and method for separating two phase-modulated signals having different amplitudes Provided is an apparatus and method for separating two phase-modulated signals having different amplitudes. A separation method for a phase-modulated signal may include: receiving, using a single antenna, a first received signal and a second received signal that are modulated and thereby transferred from a transmitter; calculating an attenuation level of each of the first received signal and the second received signal by dividing each of the first received signal and the second received signal into a real number portion and an imaginary number portion; calculating a difference between the first received signal and the second received signal; and separating and thereby demodulating the first received signal and the second received signal.
US09281975B1	Reducing pass-band ripple in radio-frequency (RF) filters used for pass-band filtering in a wireless communications system An electronically tunable equalizer is provided to a downlink (DL) and/or uplink (UL) signal processing path of a wireless communication unit incorporating a RF filter. The electronically tunable equalizer is pre-configured with a plurality of capacitance states, each representing a specific capacitance. The equalizer produces a different equalizer response for each of the plurality of capacitance states based on a received pass-band frequency signal. The plurality of equalizer responses is provided to the RF filter on a signaling processing path, thus affecting the RF filter's pass-band ripple. The RF filter's pass-band ripple is measured for each of the plurality of equalizer responses to determine a desired pass-band ripple. By configuring the electronically tunable equalizer to the capacitance state that produced the desired pass-band ripple, a ceramic RF filter may be used in the wireless communication unit for the benefit of lower cost and size, with reduced pass-band ripple.
US09281971B1	Vertical eye margin measurement using channel receiver equalizer Embodiments include systems and methods for determining link margins of data communications channels in a communications system. For example, an integrated circuit includes a large number of input/output (I/O) channels, each with a respective receiver system. The receiver system can include equalizer subsystems, that attempt to adapt to their respective channels (e.g., to eliminate inter-symbol interference). Embodiments manipulate filter tap weights in the equalizer subsystems to controllably close its respective data eye until a failure region is detected, indicating that a threshold I/O error rate has been exceeded. Thus, for each channel, the filter tap weights can be allowed to fully adjust to identify fully adapted values, and they can be forced into a failure region to identify failure region values. A link margin for each channel can be derived for each channel according to the difference between the fully adapted and failure region values of the filter tap weights.
US09281970B2	Error burst detection for assessing reliability of a communication link Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. In accordance with one aspect, embodiments are disclosed that facilitate assessing the probability of error bursts in receivers that include decision feedback equalizers (DFEs) and that perform non-contiguous mapping of received bits to frame bits. From this probability, calculation of a mean-time to false packet acceptance (MTTFPA) may be determined, and indication that a projected link MTTFPA is too low can be used to trigger an alert or invoke some safety mechanism. Associated operations may then be performed to ensure the link is prevented from being operated in an unsafe condition under which false packet acceptance may occur.
US09281969B2	Configurable multi-dimensional driver and receiver Embodiments of the invention are generally directed to a configurable multi-mode driver and receiver. An embodiment of a communication system includes a communication channel, and a first device and a second device coupled with the communication channel. The first device includes a driver apparatus to drive data signals on the communication channel, the driver apparatus including circuits to receive and drive the data signals, where the circuits are configurable for termination resistance of the driver circuit apparatus, and each of the plurality of circuits is comprised of one or more circuit units, the circuit units being configurable for equalization control of the driver apparatus. The second device includes a receiver to receive data signals from the communication channel as an input. Either the first device or the second device includes configurable circuit elements to provide signal reflection control for the system.
US09281966B2	Method, system and apparatus for the control of transmit diversity A method, apparatus and system for modifying a transmit diversity signal comprising receiving at least one input parameter, calculating at least one virtual parameter based on the at least one input parameter, converting the at least one virtual parameter into an actual parameter, and modifying a transmit diversity signal based on the actual parameter. Variations of the invention are possible, including mapping the input parameter to an actual parameter by various methods, for example, quantization, hysteresis and other methods. Embodiments of the invention may include an apparatus adapted to modify a transmit diversity signal comprising a processor to calculate at least one virtual parameter based on at least one input parameter, convert said at least one virtual parameter to an actual parameter, and modify said transmit diversity signal based on said actual parameter.
US09281963B2	Method and system for email search A method and system for performing email search, the said method comprising of enabling the user to find relations between emails and build network relations and to further retrieve groups based on the relations (and intersections of relations) as per the user's choice; the system comprising of giving and having the user select predetermined options for a search with a further ability to “drill-down” the results with the aid of filters to view further mails/results, and being also able to search on search results and also provide for storing user searches.
US09281959B2	Method for controlling home network device using universal web application and apparatus thereof A method of controlling a home network device by using a universal web application. In the method, the universal web application may receive control information, for controlling the home network device, from a server. A control command, which is issued to control the home network device, may be sent to a control point module by using a script application program interface (API) that is included in the received control information. Accordingly, result data that is obtained by executing the control command on the home network device may be received by the control point module.
US09281958B2	Method for providing interworking service in home network A method provides an interworking service in a home network. In view of the above, the present invention provides a method for providing an interworking service in a home network, in which servers and adaptors existing in a home network can identify with each other and servers or adaptors are not doubly connected to a device.
US09281954B2	Method and system for protocol independent multicasting in multichassis link aggregation domains A method for processing IP multicast packets in a Multichassis Link Aggregation (MLAG) domain. The method includes processing the IP multicast packet using the bridging functionality and the routing functionality implemented by each of the MLAG peers to process the IP multicast packets.
US09281950B2	Method for using intelligent router in charging system and apparatus associated therewith A method for using a charging system to account for service provided by a network element (NE) of a service provider network includes receiving an accounting request (ACR) from the NE at a router in the charging system, the ACR associated with service provided by the NE in the service provider network in conjunction with a communication session; modifying the ACR to form a modified ACR; sending the modified ACR to a charging collection function (CCF) server; receiving an accounting answer from the CCF server indicating the CCF server was not able to process the modified ACR; and resending the modified ACR to the CCF server or changing the modified ACR to form a revised ACR and sending the revised ACR to an alternate CCF server. A router associated with the method includes a service network communication module, a message processing module, and a charging system communication module.
US09281949B2	Device using secure processing zone to establish trust for digital rights management A DRM client on a device establishes trust with a DRM server for playback of digital content. The client executes in a secure execution environment, and the process includes (1) securely loading loader code from secure programmable memory and verifying it using a digital signature scheme and first key securely stored in the device; (2) by the verified loader code, loading DRM client code from the memory and verifying it using a digital signature scheme and second key included in the loader code; (3) by the verified DRM client code (a) obtaining a domain key from the memory; (b) encrypting the domain key with a device identifier using a DRM system key included in the DRM client code; and (c) sending the encrypted domain key and device identifier to the DRM server, whereby the device becomes registered to receive content licenses via secure communications encrypted using the domain key.
US09281944B2	Attribute based encryption using lattices A master public key is generated as a first set of lattices based on a set of attributes, along with a random vector. A master secret key is generated as a set of trap door lattices corresponding to the first set of lattices. A user secret key is generated for a user's particular set of attributes using the master secret key. The user secret key is a set of values in a vector that are chosen to satisfy a reconstruction function for reconstructing the random vector using the first set of lattices. Information is encrypted to a given set of attributes using the user secret key, the given set of attributes and the user secret key. The information is decrypted by a second user having the given set of attributes using the second user's secret key.
US09281938B2	Wireless communication device, wireless communication system, and receiving circuit A wireless communication device includes a first injection locked oscillator that inputs a received signal and includes a free-running frequency obtained by offsetting a frequency on a plus side relative to a half frequency of a frequency of the received signal; a second injection locked oscillator that inputs the received signal and includes a free-running frequency obtained by offsetting a frequency on a minus side relative to the half frequency of a frequency of the received signal; a phase difference detecting unit that detects a phase difference between an output signal output from the first injection locked oscillator and an output signal output from the second injection locked oscillator; a baseband processing unit that extracts a receiving frame based on the detected phase difference; and an access controlling unit that performs a medium access control based on the receiving frame.
US09281935B2	High-speed interface apparatus and deskew method thereof A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
US09281928B2	Range extension within single user, multiple user, multiple access, and/or MIMO wireless communications Range extension within single user, multiple user, multiple access, and/or MIMO wireless communications. A given communication device designed and implemented for operation in accordance with a given communication protocol, standard, and/or recommended practice operates in accordance with a down-clocked manner to effectuate operation in accordance with at least one other communication protocol, standard, and/or recommended practice. For example, first channelization may undergo down-clocking by a particular and desired ratio to generate a second channelization. As such, at least one portion of a physical layer (PHY) of a given communication device may be leveraged for use in at least one other or additional operational mode based upon the down-clocking employed. Sub-channel and/or channel adaptation may be made based upon any of a number of considerations (e.g., independently by one device, cooperatively by two or more devices, local and/or remote operating condition(s) [or changes thereof], etc.).
US09281926B2	Radio base station apparatus, mobile station apparatus and radio communication method To provide a radio base station apparatus and radio communication method capable of performing radio communications using downlink reference signal structures suitable for antenna virtualization, a radio base station apparatus (200) has a plurality of transmission antennas, generates CRSs used in demodulation of at least downlink control information, CQI-RSs generated for each of the transmission antennas used in measurement of channel quality, and DM-RSs generated for each stream used in demodulation of downlink transmission data, and multiplexes the CRSs, CQI-RSs and DM-RSs into a same transmission time unit to transmit from each of the antennas.
US09281923B2	Method for performing a HARQ process and apparatus using same A method of assigning a hybrid automatic repeat request (HARQ) process using a frequency division duplex (FDD) frame structure by a base station (BS) in a wireless communication system. The method according to one embodiment includes transmitting information related to a number of HARQ processes between the BS and a relay node (RN) to the RN. The number of the HARQ processes depends on subframes configured for transmission between the BS and the RN. The method according to the embodiment further includes assigning the HARQ processes subframes other than subframe indexes 0, 4, 5, and 9 based on the number of HARQ processes.
US09281921B2	Method and device for setting backhaul link subframe in wireless communication system having carrier aggregation technique applied thereto Disclosed in the present invention is a method for a base station to set a backhaul link subframe for a relay node in a wireless communication system, to which a carrier aggregation technique is applied. More particularly, the present invention comprises the steps of: determining one of the plurality of subframe settings as a first subframe setting for a main component carrier allocated to the relay node; composing subframe setting candidates for one or more subcomponent carriers allocated to the relay node, one the basis of the determined first subframe setting; and determining a second subframe setting for each of the one or more subcomponent carriers, using the composed subframe setting candidates, wherein a subframe aggregation according to the first subframe setting and subframe aggregations according to each of the subframe setting candidates do not overlap when downlink subframes and uplink subframes of the different component carriers are identical, and a downlink subframe aggregation according to the second subframe setting is included in a downlink subframe aggregation according to the first subframe setting.
US09281920B2	Mobile station and control information decoding method A mobile station capable of efficiently detecting control information addressed thereto, by prioritizing CRC decoding to control channel element at a candidate position, is disclosed. A mobile station (1) according to the present invention, in order to detect the control information addressed from a base station to the mobile station itself included in a downlink control channel having a plurality of control channel elements, for decoding a signal of a control channel element at a candidate position to be assigned with the control information, includes a generating unit (10) configured to generate a reception level of each of the control channel elements at the candidate position and a control unit (20) configured to prioritize the control channel elements based on the reception level and to control decoding of the signal of each of the control channel elements in order of priority.
US09281910B2	Radio broadcast receiving apparatus and broadcast frequency detection method In a radio broadcast receiving apparatus and a broadcast frequency detection method, a frequency fm at which a reception strength (an S meter value) that is equal to or greater than a threshold value Th0 and is greater than reception strengths at frequencies (fm−1) and (fm+1) adjacent to the frequency fm by one step by X or more, is detected as a broadcast reception frequency that is a frequency at which a receivable broadcast is performed. The value of X is set so that it increases with the increase in the reception strength (S meter value) at the frequency fm. As a result, a frequency at which a broadcast is performed can be more accurately detected.
US09281900B2	Wavelength-tunable burst-mode receiver An apparatus, e.g. an optical receiver, includes an optical front end and a processor. The optical front end is configured to coherently receive an input optical signal and convert the input optical signal to a digital-electrical data stream. The processor is configured to recover a data stream from the digital-electrical data stream. The processor is further configured to compare a correlation pattern of the recovered data stream with a pre-determined correlation pattern. The processor is further configured to determine, from the comparison, coefficients of a filter configured to recover data encoded on the input digital-electrical data stream.
US09281897B2	Electro-optical single-sideband modulator An electro-optical single-sideband modulator comprising: an electro-optical substrate; a bimodal optical waveguide structure formed in the substrate to support different optical modes having associated optical frequencies and optical propagation constants and comprising an optical input to receive an input optical carrier signal having an optical frequency, and a pair of optical outputs to output corresponding SSB modulated optical signals, each having an optical frequency spectrum with a single side lobe; and an electrode structure formed on the substrate to receive an input electrical modulating signal having an associated electrical frequency and electrical propagation constant, and to responsively apply an electrical field to the bimodal optical waveguide structure.
US09281891B2	Method and system of wirelessly retrieving lost content segments of broadcasted programming at a user device from another device A method and system includes a network having a plurality of nodes including a first mobile user device at a first node. The network also includes a second node. The system also includes a first mobile user device storing content in a memory, determining a lost content segment exists, generating a request for the lost content segment at the first mobile user device, communicating the request for the lost content to a second node of the network, receiving the lost segment from the second node and storing the lost content segment in the memory of the user device.
US09281889B2	Relay node apparatus for transmitting and receiving signal according to link operation mode in wireless communication system and method thereof A relay node (RN) apparatus for transmitting and receiving a signal according to a link mode in a wireless communication system and a method thereof are disclosed. A processor transmits or receives a signal to or from at least one of a base station and a terminal based on link mode information. At least one antenna receive the link mode information and transmit or receive the signal to or from at least one of the base station and the user equipment. The link mode information includes information a link mode in which the relay node apparatus will operate.
US09281888B1	Quadrature signal generator, beamforming arrangement, communication device and base station A quadrature signal generator comprises a resistor-capacitor, RC, polyphase filter and an inductor compensation arrangement. The inductor compensation arrangement comprises a first inductor connected between the first and the third output terminals, and a second inductor connected between the second and fourth output terminals. The first and second inductors are arranged to compensate for a capacitive load on the output terminals when in use. A beamforming arrangement, a communication device and a base station are also disclosed.
US09281885B2	Reordering of a beamforming matrix based on encoding Apparatuses, methods and systems for beamforming based on encoding are disclosed. One embodiment of a method includes generating a beamforming matrix, including obtaining a channel matrix of a multiple-input, multiple-output (MIMO) channel between multiple transmitter antennas and at least one receiver antenna, determining an initial beamforming matrix based on a singular value decomposition of the channel matrix, and generating, by a transceiver, a final beamforming matrix comprising reordering columns of the initial beamforming matrix for at least one sub-carrier of a multi-carrier signal, wherein the reordering of the columns is based on knowledge of encoding of a transmit signal.
US09281883B2	Signal generation method and signal generation device A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.
US09281882B2	Transmission of symbols in a MIMO environment using Alamouti based codes A method for transmitting data in a multiple-input-multiple-output space-time coded communication using a mapping table mapping a plurality of symbols defining the communication to respective antennae from amongst a plurality of transmission antennae and to at least one other transmission resource. The mapping table may comprise Alamouti-coded primary segments and may also comprise secondary segments, comprising primary segments. The primary segments in the secondary segments may be defined in accordance to an to Alamouti based code pattern applied at the segment level to define a segment-level Alamouti based code.
US09281880B2	Wireless transmission device and wireless reception device A wireless reception device is notified of whether a multi-user MIMO signal transmitted from a wireless transmission device has undergone linear precoding or non-linear precoding without increasing the amount of control information. A wireless transmission device having a plurality of transmit antennas 303, for transmitting spatially multiplexed signals to a plurality of wireless reception devices includes a group construction unit 307 configured to classify the wireless reception devices into a plurality of groups and to determine a precoding scheme for each of the groups, a selection unit 315 configured to select one group from among the groups, and a precoding unit 323 configured to precode transmit data addressed to each of wireless reception devices belonging to the selected group, using a precoding scheme determined for the selected group.
US09281876B2	Performing coordinated multipoint transmission and reception (CoMP) in a wireless communication network The present invention relates to the field of coordinated multipoint transmission and reception (CoMP) in wireless communication networks, in particular to methods, an apparatus, and a network node for use in performing coordinated data transmissions in a wireless communication network. A method for use in a network node for coordinating data transmission to user equipments in a wireless communication network, wherein the wireless communication network comprising at least two access nodes each access node having one or more antennas and being arranged to perform coordinated data transmissions to user equipments is provided. The method comprising: obtaining signal strength values associated with the one or more antennas of the at least two access nodes for a number of user equipments; arranging the number of user equipments into one or more groups of user equipments and associating each of the one or more groups of user equipments with a sub-set of the one or more antennas of the at least two access nodes based on the obtained signal strength values; and coordinating data transmission performed by the at least two access nodes to each of the one or more groups of user equipments based on the subset of the one or more antennas of the at least two access nodes associated with each group of user equipments, respectively.
US09281875B2	System and method for automatically optimizing wireless power A system transfers energy wirelessly from a source to a sink as an EM near-field according to parameters. The source includes a receive RF chain, and a receive controller. The sink includes a transmit RF chain, and a receive controller. The receive controller measures the energy received as feedback information, which is transmitted to the sink. Then, the transmit controller dynamically varies the parameters to optimized the energy received at the sink.
US09281874B2	NFC device with PLL controlled active load modulation A wireless communication device for communicating in the near-field via active load modulation. The device including an antenna configured to receive a magnetic field, a recovery device configured to recover a clock from the magnetic field, and a multiplexer configured to receive the recovered clock and a reference clock, and to output one of the recovered clock and the reference clock based on a current operational state of the wireless communication device, The wireless communication device further including a shunt regulator configured to produce the active load modulation by modulating an impedance of the wireless communication device, a phase-locked loop (PLL) configured to receive one of the recovered clock and the reference clock and to utilize the received clock to control the active load modulation, and a driver configured to contribute to the active load modulation by adjusting an amplitude of a voltage across the antenna.
US09281871B2	Wireless power transfer—near field communication enabled communication device Various configurations and arrangements of various communication devices are disclosed. Various integrated circuits that form these communication devices can be fabricated onto one or more semiconductor substrates, chips, and/or dies using a high voltage semiconductor process, a low voltage semiconductor process, or any combination thereof. Some of these high voltage and/or low voltage semiconductor process integrated circuits can be fabricated along with other high voltage and/or low voltage semiconductor process integrated circuits of other modules onto a single semiconductor substrate, chip, and/or die. This allows the low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of one module to be combined with low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of another module of the communication device.
US09281868B2	Power line communications zoning device A power line communications (PLC) network zoning device may include a housing, a power cord extending from the housing, and a plurality of power outlets mounted on the housing, the plurality of power outlets coupled to internal power lines within the housing. An isolation device disposed within the housing may transmit electrical power from the power cord to the internal power lines while isolating PLC communications traffic on the internal power lines from PLC communications traffic on the power cord. A bypass device internal to the housing may selectively transfer PLC communications traffic between the internal power lines and the power cord bypassing the isolation device.
US09281867B2	Power line communication device switchable between noise detecting and filtering functions The present invention is to provide a PLC device, which includes a power receiving port connected to a power supply for receiving a power signal and a network signal carried by the power signal; a filtering unit having a first end connected to the power receiving port; a power output port connected to a second end of the filtering unit and a load, respectively, for supplying the power signal to the load while the filtering unit filters out noise generated in the power signal by the load; a switching unit having two connecting ends connecting to the first and second ends, respectively, and a control end switchable between the two connecting ends; and a processing unit connected to the control end and including a bridge module for receiving and then transmitting the network signal to a network apparatus, and a detection module for detecting the level of the noise.
US09281866B2	Methods for enhanced power delivery to tower-mounted and other remotely-mounted remote radio heads and related systems and power cables Tower systems suitable for use at cellular base stations include a tower, an antenna mounted on the tower, a remote radio head mounted on the tower and a power supply. A power cable having a power supply conductor and a return conductor is connected between the power supply and the remote radio head. A shunt capacitance unit that is separate from the remote radio head that is electrically coupled between the power supply conductor and the return conductor of the power cable.
US09281865B2	Efficient network discovery in frequency hopping networks In one embodiment, a device in a frequency hopping communication network transmits responsive beacon messages based on adaptive types of responsive beacon message transmission based on a number of received beacon requests within a given time period: the number below a threshold results in synchronized unicast messages; the number above the threshold results in unsynchronized broadcast messages. In another embodiment, the device suppresses unsolicited beacon message transmission based on a density-aware redundancy count of other unsolicited beacon message transmissions from neighboring devices. In another embodiment, the device may transmit unsolicited beacon messages according to an adaptive interval based on stability of the network. In another embodiment, the device may suppress transmission of a beacon request to join the communication network based on a density-aware redundancy count of other beacon requests from neighboring devices, and transmits beacon requests at an adaptive interval that increases in response to each unanswered beacon request.
US09281864B2	Method and apparatus for an adaptive filter architecture A system that incorporates teachings of the subject disclosure may include, for example, a method for scanning a radio frequency spectrum for an available frequency band, selecting an available frequency band in the radio frequency spectrum even if the available frequency band is affected by radio frequency interference, measuring a signal strength in portions of the available frequency band, correlating the signal strength of each portion to generate a correlation factor, detecting radio frequency interference in the available frequency band according to the correlation factor, and generating tuning coefficient data to cause the filter apparatus to substantially suppress the radio frequency interference in the available frequency band. Other embodiments are disclosed.
US09281860B2	Wireless transmission system, wireless communication device, and wireless communication method A wireless transmission system includes: a communication unit for transmission; and a communication unit for reception. The communication units for transmission and reception are housed in a housing of the same electronic apparatus, or the communication unit for transmission is housed in a housing of first electronic apparatus and the communication unit for reception is housed in a housing of second electronic apparatus and a wireless signal transmission path enabling wireless information transmission between the communication units is formed between the communication units when the first and the second electronic apparatus are disposed at given positions to be integrated with each other. The communication unit for transmission includes a first carrier signal generating unit and a first frequency converter, and the communication unit for reception includes a second carrier signal generating unit, and a second frequency converter.
US09281855B2	Apparatus and methods for recordation of device history across multiple software emulations Apparatus and method for maintaining hardware history profiles for a software-based emulator. In one embodiment, the disclosed software-based emulator monitors the history of the actual hardware device in a secondary device history, the history of the emulated hardware is presented within a primary device history. However, the primary device history is linked to the secondary device history, and receives the device wear history therefrom. In another aspect of the present invention, wear-leveling strategies are disclosed for handling various update sizes. Unlike existing solutions which are optimized for a single SIM that receives small data updates; various embodiments of the present invention are suitable for handling varying data sizes.
US09281852B2	Method and apparatus for calibrating time alignment A method includes setting a circuit to a mode. A test tone having a first frequency is provided to the circuit for use in calibrating the circuit. A received signal is generated based on an output signal of the circuit, the received signal including a component having a second frequency that is a harmonic of the first frequency. A magnitude of the component having the second frequency in the received signal is measured. A delay of the circuit corresponding to the mode is adjusted according to the magnitude of the component.
US09281850B1	Adaptive impedance translation circuit The present invention relates to an adaptable RF impedance translation circuit that includes a first group of inductive elements cascaded in series between an input and an output without any series switching elements, a second group of inductive elements cascaded in series, and a group of switching elements that are capable of electrically coupling the first group of inductive elements to the second group of inductive elements. Further, the adaptable RF impedance translation circuit includes at least one variable shunt capacitance circuit electrically coupled between a common reference and at least one connection node in the adaptable RF impedance translation circuit, which includes control circuitry to select either an OFF state or an ON state associated with each of the switching elements and to select a capacitance associated with each variable shunt capacitance circuit to control impedance translation characteristics of the adaptable RF impedance translation circuit.
US09281848B2	Method for encoding data in bursts A process of encoding information data in a sequence of bursts ( . . . , Bi−2, Bi−1, Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (Ri) of the current burst (Bi) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi−2, Bi−1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.
US09281845B1	Layered redundancy encoding schemes for data storage Techniques for optimizing data storage are disclosed herein. In particular, methods and systems for implementing redundancy encoding schemes with data storage systems are described. The redundancy encoding schemes may be scheduled according to system and data characteristics. The schemes may span multiple tiers or layers of a storage system. The schemes may be generated, for example, in accordance with a transaction rate requirement, a data durability requirement or in the context of the age of the stored data. The schemes may be designed to rectify entropy-related effects upon data storage. The schemes may include one or more erasure codes or erasure coding schemes. Additionally, methods and systems for improving and/or accounting for failure correlation of various components of the storage system, including that of storage devices such as hard disk drives, are described.
US09281843B2	Systems and methods for reduced constraint code data processing The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. In one case a data processing system is disclosed that includes a decoder circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, where the decoder input is a codeword formed of two bit symbols, and where the decoder input is encoded to yield a last layer including at least two different entry values. In addition, the data processing system includes an inverse mapping circuit operable to remap the interim decoded output to yield an overall decoded output.
US09281842B2	Method and device for improving decoding of data received from one source by several receivers Improving decoding of a set of k data symbols received from several receivers, the data symbols being encoded by a systematic block error correcting code of dimension k and size n. The set of data symbols is received along with a corresponding subset of parity symbols, forming a partial data block comprising m symbols. A partial data block transmitted by one emitter, comprising a set of k data symbols and a subset of (m−k) parity symbols, is received from each receiver. For each received partial data block, a subset of parity symbols is generated and an item of reliability information is computed as a function of the received parity symbols and parity symbols generated from a received set of data symbols. The items of computed reliability information are compared with each other to select one received set of data bits.
US09281835B2	Method and apparatus for wide range input for an analog to digital converter A method of providing a wide range of input currents for an analog to digital converter (ADC), the method constituted of: receiving an input current; selecting one of a plurality of selectable ratios; and generating at least one sense current, the magnitudes of the at least one generated sense current and the received input current exhibiting the selected ratio, wherein the ADC is arranged to receive a voltage representation of the at least one generated sense current.
US09281834B1	N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.
US09281831B2	Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.
US09281828B2	Reference-less voltage controlled oscillator (VCO) calibration Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.
US09281827B2	Clock generator A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
US09281824B2	Clock amplitude detection In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.
US09281821B2	Time division multiplexed limited switch dynamic logic A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.
US09281817B2	Power conservation using gray-coded address sequencing A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.
US09281815B2	Electrode unit with perimeter-lengthened touch-sensing pattern for touch-sensing element located at fringes of touch panel An electrode unit on a touch-sensing element includes a first electrode and a second electrode. The first electrode includes a first conductive element; and a plurality of second conductive elements extending from the first conductive element in directions in parallel with a first direction within a specific range. The second electrode includes a third conductive element and a plurality of fourth conductive elements extending from the third conductive element in directions in parallel with a second direction within a specific range.
US09281805B2	Clock control circuit, receiver, and communication device A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.
US09281801B2	Digital filter circuit and digital filter control method A digital filter circuit and a digital filter control method are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. The digital filter circuit according to the present invention includes: an overlap addition unit for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing unit for transforming the generated block by FFT processing; a filter computation unit for performing filter processing to the transformed block; an IFFT unit for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal unit for removing M units of data from both ends of the transformed block; and a clock generation unit for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition unit, the FFT unit, the filter computation unit, the IFFT unit, and the input unit of the overlap removal unit.
US09281800B2	Resonator filter device having narrow pass-band A filter device for filtering signals via a pass-band includes series resonators connected in series between an input terminal and an output terminal, each of the series resonators having a corresponding parallel resonance frequency Fp and series resonance frequency Fs, and shunt resonators respectively connected between at least one of the series resonators and a ground voltage, each of the shunt resonators having a corresponding parallel resonance frequency Fp and series resonance frequency Fs. At least one series resonator has a corresponding series resonance frequency Fs outside the pass-band of the filter device, and at least one other series resonator has a corresponding series resonance frequency Fs inside the pass-band, and/or at least one shunt resonator has a corresponding parallel resonance frequency Fp outside the pass-band of the filter device, and at least one other shunt resonator has a corresponding parallel resonance frequency Fp inside the pass-band.
US09281796B2	Polyphase filter for mm-wave frequencies featuring symmetric layout A two-stage, passive, RC polyphase filter for mm-wave quadrature LO generation is presented. The filter features an innovative, symmetrical layout structure, which is more robust to parasitics than the conventional layout. Layout parasitics which become important at mm-wave frequencies are identified and a compensated. Impedance variations and transfer functions are evaluated considering these dominant parasitics. More than 15 dB improvement in image rejection ratio is achieved in comparison with conventional layouts. Using the inventive techniques more than 35 dB of image rejection ratio over a bandwidth of 6 GHz is demonstrated in an outphasing transmitter at 60 GHz in 40 nm CMOS.
US09281784B2	High-gain low-noise preamplifier and associated amplification and common-mode control method A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.
US09281781B2	Semiconductor apparatus, oscillation circuit, and signal processing system A semiconductor apparatus includes: first and second external terminals that are connected to respective both ends of an piezoelectric vibrator, in which the piezoelectric vibrator is externally disposed; an inverting amplifier that is disposed between the first and second external terminals; a feedback resistance that feeds back an output of the inverting amplifier to an input of the inverting amplifier; a first capacitative element that is disposed between the first external terminal and a reference voltage terminal; a first resistive element that is disposed in series with the first capacitative element; a second capacitative element that is disposed between the second external terminal and the reference voltage terminal; and a second resistive element that is disposed in series with the second capacitative element.
US09281778B2	Mounting bracket assemblies and methods A mounting bracket assembly comprises a flexible body including at least one top member and a flexible angled bottom member connected to the top member. The flexible body defines a beam insertion aperture between the top member and the bottom member. The mounting bracket assembly further comprises at least one clamp attached to the top member. The mounting bracket assembly may further comprise a threaded rod running through the at least one top member and a clamping nut securing the threaded rod to the top member such that rotating the clamping nut compresses the top member and grounds an electricity generating device such as a photovoltaic module. The mounting bracket assembly may further comprise an integral grounding device disposed adjacent the top member to electrically ground the electricity generating device.
US09281775B2	Clamping device with an electric motor The invention relates to a clamping device (1), for example swing tensioners (1), bracing elements, machine vises or block cylinders, with a movable clamping element (2) for clamping a workpiece with a defined clamping force, and with an electric motor (10) for mechanically driving the clamping element (2), also with a control unit that controls the electric motor (10). The invention provides that the control unit detects an electrical operating parameter of the electric motor (10) as a measure of the clamping force. The contact of the clamping element with the workpiece is detected in this manner. Subsequently, the electric motor (10) is then driven further by a defined number of revolutions, the number of revolutions after contact with the workpiece defining the clamping force. The invention further comprises a corresponding control method.
US09281773B2	Position sensorless step-wise freewheeling control method for switched reluctance motor A position sensorless step-wise freewheeling control method for a switched reluctance motor having dual switched-mode power converters for each phase doesn't require any additional external hardware, any rotor-position sensor, or storage of flux linkage data of the motor. After the upper and lower tubes of the main switch are switched off, and the phase of the switched reluctance motor enters into a negative voltage forced freewheeling state, the phase current is detected. When the phase current falls to a preset threshold, one of the upper or lower tubes is switched on and the phase enters into a zero voltage natural freewheeling state. When the phase current reaches a peak value, the rotor position becomes the start position of the minimum phase inductance and the rotor position is used as the switch-on position of the main switch. The upper and lower tubes are then switched on.
US09281771B2	Drive controller, image pickup apparatus, drive control method, and storage medium A drive controller includes a stepping motor capable of performing micro-step drive of a predetermined number of divisions by using an excitation current having a sine waveform, and a control unit configured to calculate a first drive pulse of the stepping motor to perform the micro-step drive, and the control unit is configured to change the first drive pulse to a second drive pulse depending on a ratio of a step phase of a predetermined phase region included in a range of the micro-step drive when performing the micro-step drive with the first drive pulse in a wobbling operation.
US09281770B2	Precision-fastening handheld cordless power tools Cordless power tools include a pistol housing having an upper portion that merges into a downwardly extending handle, a DC motor residing in the upper portion of the housing, the DC motor having a rotor that drives an output shaft; a torque transducer on board the tool in communication with the output shaft; and a dynamic motor control circuit residing in the housing in communication with the motor and torque transducer. The dynamic motor control circuit includes a Kelvin resistor in communication with the motor for measuring motor current and digital hall switches in communication with the motor for measuring motor speed. The motor current can vary by at least 100 A during operation.
US09281769B2	Electronic circuit and method for adjusting start-up characteristics of drive signals applied to an electric motor A motor control circuit and associated techniques can drive an electric motor in a start-up mode of operation followed by a normal mode of operation. The motor control circuit and techniques can receive a selection signal provided by a user that can select one of a plurality of sets of parameter values that determine characteristics of drive signals applied to the motor during the start-up mode of operation. The motor control circuit and associated techniques can synchronize operation between the start-up mode of operation and the normal mode of operation.
US09281768B2	Method and device for synchronizing a rotation speed of a rotor with a rotation field of a stator A method for synchronizing a rotation speed of a permanently excited rotor of an electric motor with a frequency of a rotation field of a sensorless commutated stator of the electric motor during a run-up procedure of the electric motor includes determining a phase position of the rotation field and a phase position of a countervoltage that is induced by the rotor in the stator in order to obtain a phase offset between the rotation field and the countervoltage. The method further includes adjusting a prevailing amplitude of one component of the rotation field using the phase offset to synchronize the rotation speed with the frequency. The amplitude of the component is increased if the rotor is lagging behind the rotation field or the amplitude of the component is reduced if the rotor is running ahead of the rotation field.
US09281766B2	Driving apparatus for analyzing apparatus Disclosed is an analyzing apparatus including a first drive part (71) for rotating a turntable (101) on which an analyzing device is set, a second drive part (72) selectively engaged with the first drive part (71) to reciprocate the analyzing device, and a third drive part (73) for relatively moving the first drive part (71) and the second drive part (72) a position where the first and second drive parts are engaged with each other and a position where the first and second drive parts are not engaged with each other. Thus in the mixing and agitation of a small amount of fluid, necessary acceleration can be obtained even in a short time.
US09281764B2	Energy harvester device for in-ear devices using ear canal dynamic motion An energy harvester device located into an in-ear device and harvesting energy from dynamic motion of the wall of the outer ear canal receiving the in-ear device therein, with an external sheath of the in-ear device generally assuming the contour of the ear canal wall. The energy harvester device has an energy harvesting module mounting on an inner portion of the in-ear device adjacent the external sheath, and is at least partially elastically deformable under a displacement of the ear canal wall to generate energy corresponding to the displacement of the wall. An energy storage module mounts onto the in-ear device and connects to the energy harvesting module to receive energy there from and supplying the stored energy to an electronic device of the in-ear device. The in-ear device having the energy harvester device therein is also part of the present invention.
US09281763B2	Row and column actuator control In one embodiment, a device is provided that includes:a plurality of actuators arranged into a plurality of rows and a plurality of columns; a plurality of row conductors corresponding to the plurality of rows; a plurality of column conductors corresponding to the plurality of columns; and a controller configured to select at least one of the actuators in a row by raising a voltage on the corresponding row conductor to couple each selected actuator to its corresponding column conductor.
US09281756B2	Power flow controller with a fractionally rated back-to-back converter A power flow controller with a fractionally rated back-to-back (BTB) converter is provided. The power flow controller provide dynamic control of both active and reactive power of a power system. The power flow controller inserts a voltage with controllable magnitude and phase between two AC sources at the same frequency; thereby effecting control of active and reactive power flows between the two AC sources. A transformer may be augmented with a fractionally rated bi-directional Back to Back (BTB) converter. The fractionally rated BTB converter comprises a transformer side converter (TSC), a direct-current (DC) link, and a line side converter (LSC). By controlling the switches of the BTB converter, the effective phase angle between the two AC source voltages may be regulated, and the amplitude of the voltage inserted by the power flow controller may be adjusted with respect to the AC source voltages.
US09281753B2	LLC converter with dynamic gain transformation for wide input and output range A resonant power converter system includes an output load and a rectifier stage that provides a DC output voltage to the output load from an AC intermediate voltage. The resonant power converter system also includes a resonant inverter stage that provides the AC intermediate voltage from a DC input voltage, wherein an inverter gain is controlled by switching between full-bridge and half-bridge topologies based on an external variable of the resonant power converter system. The resonant power converter system further includes a controller that controls the resonant power converter system. Additionally, a method of operating a power converter includes rectifying an AC intermediate voltage to provide a DC output voltage and providing the AC intermediate voltage by inverting a DC input voltage, wherein an inversion gain of the AC intermediate voltage is controlled by switching between full-bridge and half-bridge inversion topologies based on an external variable.
US09281752B2	Resonant converters with synchronous rectifier feedback A method comprises providing a resonant converter, wherein the resonant converter comprises an input switch network coupled to a power source, wherein the input switch network comprises a plurality of power switches, a resonant tank coupled to the plurality of power switches, a transformer coupled to the resonant tank and an output stage coupled to the transformer, wherein the output stage comprises a synchronous rectifier formed by a first switch and a second switch, detecting a drain voltage of the first switch, comparing the drain voltage with a predetermined voltage threshold, wherein the drain voltage is coupled to a negative input of a comparator and the predetermined voltage threshold is coupled to a positive input of the comparator, generating a logic state based upon an output of the comparator and adjusting, by a control circuit, a switching frequency of the resonant converter based upon the logic state.
US09281749B2	Multiple power supply systems and methods Aspects of the present invention include a power supply system comprising a plurality of power supplies. Each of the power supplies can include an oscillator system configured to generate a clock signal at a clock node. Each of the power supplies can include an error amplifier configured to generate an error voltage at an error amplifier output node. Each of the power supplies can also include a pulse-width modulation (PWM) generator configured to generate a PWM switching signal based on an error voltage and the clock signal. Each of the power supplies can further include a power stage configured to generate an output voltage based on the PWM switching signal.
US09281747B2	Voltage regulator control using information from a load Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, systems, and processes for controlling a voltage regulator in response to information from a load. In some implementations, transient minimizer circuitry is coupled to receive a notification signal indicating a change or an anticipated change in an electrical characteristic of the load. The transient minimizer circuitry is configured to generate a state command signal responsive to the notification signal. The state command signal indicates a state of the voltage regulator. The switching control circuitry is coupled to receive the state command signal from the transient minimizer circuitry. The switching control circuitry is configured to operate switch circuitry to control the state of the voltage regulator in accordance with the state command signal.
US09281741B2	Start-up circuit for voltage regulation circuit Among other things, techniques and systems are provided to pre-charge a node of a primary circuit, such as a voltage regulator or bandgap voltage reference, via a start-up circuit. The node is charged to a specified voltage during a pre-charge operation that occurs while the primary-circuit is powered-off. The pre-charge operation comprises discharging a voltage from the node during a first portion of the pre-charge operation and re-charging the node to the specified voltage during a second portion of the pre-charge operation. In some embodiments, the specified voltage is substantially equivalent to a switching voltage of a drive transistor of the primary circuit.
US09281738B2	Power conversion apparatus with low common mode noise and application systems thereof A power conversion circuit comprises an AC source, a power conversion unit, a filter inductor unit and a common mode noise suppression circuit. The power conversion unit has DC terminals and AC terminals. The filter inductor unit has first and second terminals, being respectively connected to the AC source and the AC terminals of the power conversion unit. The common mode noise suppression circuit has a capacitive impedance network with first and second terminals, and an impedance balancing network with first and second terminals. The second terminals of the capacitive impedance network are connected to the first terminals of the impedance balancing network, the first terminals of the capacitive impedance network are connected to the first terminals of the filter inductor unit, and the second terminals of the impedance balancing network are connected to the DC terminals of the power conversion unit.
US09281737B2	Voltage converter A voltage converter such as a DC-DC buck regulator includes a driver circuit that enables charge stored on the parasitic capacitance of a transistor switch to be transferred to a load capacitor. Hence, stored charge can be harvested for use by a load, thereby increasing efficiency of the regulator.
US09281735B2	Flux-switching linear permanent magnet machine with yokeless translator Advantageous motors, such as flux-switching linear synchronous motors (FSLSMs) are provided. In an FSLSM, all magnets can be magnetized in the same direction. In addition, an FSLSM can be yokeless and can have two stators displaced from one another by half a pole pitch. FSLSMs of the subject invention are cost-effective and provide high thrust, and can operate well even under fault conditions.
US09281734B2	Linear motor with back yoke Provided herein is a linear motor in which a back yoke can readily be mounted onto a plurality of linear motor units. The back yoke is constituted from a back yoke assembly including a surrounding portion that entirely surrounds six linear motor units. The back yoke works to form part of respective magnetic circuits of the six linear motor units. The back yoke assembly includes first and second divided assemblies and five partition wall portions. The first and second divided assemblies are each formed by press working a magnetic plate made of silicon steel.
US09281731B2	Method for maintaining a machine having a rotor and a stator Methods of precisely positioning a rotor of a machine into one or more service positions for the purpose of servicing the machine. In some embodiments, the machine includes A rotor and a stator segmented into multiple removable stator modules. During servicing, a stator-module replacement tool is precisely located in any one or more of multiple service positions corresponding to the multiple stator modules by selectively energizing the machine. In other embodiments, the machine includes a stator and a rotor having multiple removable permanent magnets corresponding respectively to multiple service positions. During servicing, the rotor is precisely located in any one or more of multiple service positions corresponding to the permanent magnets by selectively energizing the machine. A servicing control system is disclosed for controlling the excitation of a machine stator in a manner that effects precise positioning of the rotor into a selected service position.
US09281730B2	Motor driving system A motor driving system that changes a rotation speed of a motor pursuant to a speed command includes a main device including a drive circuit configured to drive the motor, an input device configured to input the speed command to the drive circuit, and a signal insulating unit configured to insulate the input device from the main device and to transmit the speed command from the input device to the drive circuit of the main device.
US09281726B2	Actuator The invention relates to an actuator for operating a positioning element. A common requirement in such actuators is that the positioning element can be decoupled from the electric motor that drives the positioning element via a transmission. In some applications the actuators are so compact that the only way to decouple the actuator is to disassemble parts of the actuator. To connect the positioning element to the electric motor again, this however requires that the whole actuator is demounted so as to ensure that the disassembled parts are properly assembled. The present invention overcomes this problem by providing an actuator comprising two toothed wheels which by mutual displacement can be brought out of mesh and which each comprises at least two toothed rims positioned with a spacing corresponding to at least the width of one toothed rim. Hence the provided actuator is very compact in that the space required for disengagement of the positioning element is practically reduced to the width of the toothed wheels. Further the construction ensures a firm mesh, making the actuator highly reliable.
US09281724B2	Rotating electrical machine including concentrated single-layer winding coil In a rotating electrical machine, the concentrated winding coil includes a single-layer coil, corresponding to one layer, wound in a first turn advancing mode with the wire forming sequential coil turns starting from one end of the insulating bobbin toward another end of the insulating bobbin and another single-layer coil, corresponding to one layer, wound in a second turn advancing mode with the wire forming turns starting from the other end of the insulating bobbin toward the one end of the insulating bobbin, with the single-layer coil and the other single-layer coil layered alternately to each other. The insulating bobbin includes a winding portion where the concentrated winding coil is formed, collars each formed at one of two ends of the winding portion and at least one projecting portion configured to disallow misalignment at a turn changeover start area in the first and second turn advancing modes.
US09281721B2	Permanent-magnet electric motor comprising a segmented stator An electric motor (1) with permanent magnets includes a rotor (4), on which permanent magnets are fastened (6), and a stator (2). The stator includes a stator structure and coils (5) installed on the stator structure. The stator structure is realized by an assembly of at least three independent stator elements (21), assembled on a baseplate (3) with no direct mechanical linkage between them. Each stator element (21) is fastened onto the baseplate (3) of the motor by an adjusted fastener (31) and at least one anti-rotation element (32). Preferably, the stator elements (21) are made of a material that is a good heat conductor and electrical insulator, such as a ceramic.
US09281717B2	Form factor swappable DC battery back-up In accordance with the present disclosure, a system and method for providing a battery back-up unit (BBU) for a rack-level power infrastructure is described. The system may include a chassis sized to fit within a commodity power supply unit (PSU) slot in a power distribution unit (PDU). A battery may be disposed within the chassis, and at least one power module coupled to the battery. The system may also include a power module controller coupled to the at least one power module, and a form-factor connector coupled to the power module controller and the at least one power module.
US09281716B2	Generator controller configured for preventing automatic transfer switch from supplying power to the selected load A power management system may include a generator controller. The generator controller may (i) operate the generator; and (ii) prohibit a transfer switch from supplying first or second power to an output of the transfer switch. In some systems, the first power may be primary power (e.g., from a primary power source such as a utility) while the second power is secondary power (e.g., from a secondary power source such as a generator). In other systems, the second power may be primary power while the first power is secondary power, or both the first and second power may be secondary power.
US09281706B2	Object detection in a wireless charging field Methods and devices are disclosed including a wireless charging method comprising transmitting a wireless charging signal, monitoring at least one of an amplitude and a phase of the wireless charging signal, determining whether the at least one of an amplitude and phase is within a predetermined range of at least one predetermined value and, if it is determined that the at least one of an amplitude and phase is not within the predetermined range of the at least one predetermined value, stopping transmission of the wireless charging signal.
US09281704B2	Method of controlling a load current, load current control device, and mobile device having the same A method of controlling a load current is provided. By the method, a battery voltage control operation is begun when a battery voltage becomes lower than a first threshold value, whether a gradient of the battery voltage is a positive gradient or a negative gradient is determined at an interval of a reference or, alternatively, predetermined control time, the load current is controlled based on the gradient of the battery voltage at an interval of the reference or, alternatively, predetermined control time, and the battery voltage control operation is finished when the battery voltage becomes higher than a second threshold value.
US09281701B2	Wireless power transfer device for charging mobile/portable devices A charging system having a charging device with a groove for receiving a mobile/portable device for charging is provided having a magnetic core located in a housing of the charging device with the magnetic core having a base and two legs that are located around the groove. A coil is wrapped around the base and a driver circuit is connected to the coil as well as to an external power source. A power receiver is located in a mobile/portable device that can be placed in the groove in the charging device. The power receiver includes a receiver magnetic core as well as a receiving coil wrapped around the receiver magnetic core for receiving an inductive current from the charging device. A charging circuit is connected to the receiving coil and adapted to be connected to the battery of the mobile/portable device for charging.
US09281696B2	Current steering circuit and current steering method for controlling branch current flowing through branch A current steering circuit for controlling a branch current flowing through a branch is provided. The branch is coupled to a first main switch. The current steering circuit includes a sensing device, a first auxiliary switch and a control unit. The sensing device is coupled to the branch and arranged for sensing the branch current to generate a sensing result. The first auxiliary switch is coupled in parallel with the first main switch. The control unit is coupled to the sensing device and the first auxiliary switch, wherein while the first main switch is turned on, the control unit generates a first switch control signal to the first auxiliary switch, and adjusts a duty cycle of the first switch control signal according to the sensing result in order to adjust the branch current.
US09281691B2	Detection for four pair powered devices A twin power sourcing equipment constituted of: a first power sourcing equipment; and a second power sourcing equipment arranged for connection to a powered device over respective power paths; the first and second power sourcing equipments arranged to: simultaneously perform detection of the powered device; and in the event that at least one of the first and second power sourcing equipments detects the presence of the powered device, alternately perform detection of the powered device to detect a signature impedance; and in the event that each of the alternate detection is indicative of the presence of the signature impedance, provide power to the powered device simultaneously by the first and second power sourcing equipment. Power is not provided to the powered device in the event that the simultaneous detection is indicative of the absence of the powered device on each of the first path and the second path.
US09281689B2	Load phase balancing at multiple tiers of a multi-tier hierarchical intelligent power distribution grid The subject specification comprises enhanced power system balance control for a multi-tier hierarchical electrical distribution network (EDN). The EDN comprises a specified number of distribution network node controller (DNNC) components employed to desirably control power system balance, data communications, and power distribution between respective tiers of the EDN to facilitate efficient power distribution. In each tier, a power system balance component (PSBC), associated with a DNNC component, can monitor power system balance, such as load phase balance, associated with multi-phase power distribution for its tier, and detect power system imbalances in that tier. A power balance correction action can be identified and executed (e.g., automatically) in response to the detected power system imbalance to rectify the imbalance, wherein the correction action can include dynamic switching of loads between phases and/or filtering of the power signal.
US09281687B2	Control system for electrical outlets A system for controlling electrical outlets includes two devices. The first device connects to a switched outlet and sends a signal to the second device when the outlet is turned on or off. The second device mimics the power state of the first device. The first device may include a socket for receiving a sensor module, which may alter the functionality of the device. For example, the device may be controlled by a remote device or it may be motion-activated, depending on the module that is connected.
US09281684B2	Interconnect device for detecting whether a vehicle on-board diagnostics (OBD) data port includes circuitry which prevents back feeding of power through the OBD data port An interconnect device is disclosed for detecting whether an vehicle on-board diagnostics (OBD) data port includes a blocking diode or equivalent. that prevents back feeding of power through the OBD data port. If a diode is detected, the interconnect device alerts the user that the power cannot be back fed through the OBD II port connector. In such a condition, an alternate means is used to preserve the data mentioned above. Specifically, an alternative power supply can be connected directly to the battery cables that will be disconnected from the battery, for example, by way of battery clamps. In this way the alternative power supply is used to preserve the data until a new battery is reconnected to the vehicle battery cables. If a diode is not detected by the interconnect device, the interconnect device displays this fact to the user. The interconnect device includes circuitry for detecting and displaying whether a diode is connected in series with a power pin of the OBD II port connector. In addition, the interconnect device includes an OBD II port connector on one end connected by way of a cable to a connector, such as a cigarette lighter connector or hardwired directly to an alternate power supply.
US09281680B2	Power switching circuit A power switching circuit includes a power semiconductor element that includes a main switching element connected in parallel with a main body diode and a sense switching element connected in parallel with a sense body diode; a reverse overcurrent detection circuit that detects an overcurrent flowing in the reverse direction out of currents flowing through a parallel-connection body of the sense switching element and the sense body diode; and a control circuit that drives the gate of the power semiconductor element; wherein when the reverse overcurrent detection circuit detects a reverse overcurrent, the control circuit controls the main switching element and the sense switching element to turn on.
US09281676B2	Adjustment device for cable management arm An adjustment device for a cable management arm includes a first support member, a second support member, and a positioning member. The first support member has a plurality of holes. The second support member is movably connected to the first support member and has a through hole. The positioning member is fixed to the second support member and has a positioning portion and a resilient section connected to the positioning portion. When in use, the positioning portion partially extends through the through hole, selectively extends through one of the holes, and then is positioned by a force of the resilient section, such that the extension-length of the second support member relative to the first support member is adjusted.
US09281675B2	Systems and methods for cable deployment of downhole equipment Systems and methods for cable deployment of downhole equipment, wherein the conductors of a power cable bear the load of the downhole equipment and jewelry, as well as the cable itself. The power cable includes a set of elongated conductors, an upper coupling and a lower coupling. The upper support coupling suspends each of the conductors from the support structure and electrically couples the conductors to a power source. The lower coupling suspends the downhole electrical equipment from the conductors and electrically couples the conductors to the downhole equipment. One embodiment uses 7075 T-6 aluminum conductors to provide a length of at least 10,000 feet, a yield stress of at least 50,000 psi and a resistance of less than 0.2 ohm/kf. The aluminum conductors are homogeneous and are non-reactive with hydrogen sulfide, so no lead sheathing is required.
US09281674B2	Method of busway construction A busway and a method of assembling the same in which a flowable, uncured epoxy is applied between insulated busbar conductors that are stacked on top of one another and inner surfaces of the busway housing into which the stacked conductors are placed to form an enclosed busway. The busbar conductors are insulated by an epoxy powder coat, which can develop pinholes during the curing of the epoxy powder. A flowable, curable dielectric material, such as epoxy, is applied between the outermost busbar conductors and the inner surfaces of the top and bottom pieces of the busway housing. Optionally, epoxy is also applied between adjacent pairs of busbar conductors, which are stacked and arranged into the housing. Pressure is applied to the housing stack, and the epoxy is allowed to cure, resulting in a busway having superior thermal performance, dielectric integrity, and mechanical strength compared to conventional busways.
US09281673B2	Deformable busbar assembly and bus bar installation method A bus bar assembly includes a deformable bus bar including a bus bar positive terminal flange, a bus bar negative terminal flange spaced-apart from the bus bar positive terminal flange and a flange connecting portion connecting the bus bar positive terminal flange and the bus bar negative terminal flange. A deformable bus bar frame includes a bus bar frame positive terminal flange carried by the bus bar positive terminal flange of the deformable bus bar and a bus bar frame negative terminal flange carried by the bus bar negative terminal flange of the deformable bus bar. A method of installing a deformable bus bar on positive and negative terminals of a battery cell is also disclosed.
US09281672B2	Electrical connectivity within architectural glazing frame systems A system for providing an electrical interface across a sealed boundary may include a frame in sealed engagement with at least a portion of a substrate. The substrate may be in communication with an electrochromic device. The system may further include first and second conduits. The first conduit may be on a first side of the substrate and a second conduit may be on a second side of the substrate. The second conduit may be in communication with the first conduit through at least one of the seal, a space between the seal and the frame, and a space between the seal and the substrate.
US09281670B2	Corrugated tube provided with passage maintenance member, and wire harness A passage restricting member is attached to a corrugated tube. This corrugated tube includes a corrugated tube, a passage maintenance member, and an attachment member. The passage maintenance member is die-molded so as to maintain a shape in which at least a portion is curved in the longitudinal direction, and the transverse cross-section is arc shaped. The passage maintenance member has an opening penetrating to the internal peripheral side and the external peripheral side. The attachment member has an internal peripheral engaging part engaging with an internal peripheral portion of a slit in the corrugated tube, an external peripheral engaging part engaging with an external peripheral portion of the opening in the passage maintenance member, and a connecting part for connecting the internal peripheral engaging part and the external peripheral engaging part while disposed in the slit and the opening.
US09281668B2	Stripping blades for cutting insulation An insulation stripping assembly for stripping insulation from a conductor. The blade assembly includes a first blade assembly and a second blade assembly. The first blade assembly has a first cutting blade, and the second blade assembly has a second cutting blade. A clenching member is provided on at least one of the first blade assembly and the second blade assembly. The clenching member is spaced from the first cutting blade and the second cutting blade. The first and second cutting blade essentially cut through the insulation and the clenching member engages the insulation to provide increased pulling force to remove the cut insulation from the conductor.
US09281666B2	Subsea electrical distribution system having redundant circuit breaker control and method for providing same A system and method for coupling electrical power subsea. The system comprises a subsea electrical distribution system having at least one modular circuit breaker assembly. The modular circuit breaker assembly is controlled by a control system that has a plurality of circuit breaker controls. Each circuit breaker is operable to be controlled by a plurality of circuit breaker controls and each circuit breaker control is operable to control a plurality of circuit breakers. Therefore, control of each circuit breaker is maintained even if one circuit breaker control fails.
US09281662B2	Spark plug A spark plug including an insulator having an axial hole, a center electrode held at one end side and a terminal electrode held at the other end side of the axial hole, an electrical connection portion electrically connecting the center electrode and the terminal electrode inside the axial hole, wherein the electrical connection portion includes a conductor including a ceramic phase and a metal wire having a spiral structure portion, wherein the metal wire has a wire diameter of 0.1 mm or greater and 0.5 mm or smaller, and wherein the spiral structure portion of the metal wire is configured such that an outer diameter thereof is 1.0 mm or greater and 3 mm or smaller, a pitch thereof is 0.3 mm or greater and 1 mm or smaller, and a height thereof is 8 mm or greater and 30 mm or smaller.
US09281661B2	Integrated optoelectronic device comprising a Mach-Zehnder modulator and a vertical cavity surface emitting laser (VCSEL) A Mach-Zehnder modulator (MZM) is horizontally integrated with a VCSEL. The horizontally-integrated MZM overcomes wavelength dependence problems of horizontally-integrated EA modulators and yet has the same advantages as horizontally-integrated EA modulators in terms of overcoming the ER and modulation range problems associated with the vertically-integrated EA and EO modulators. By overcoming these problems with the existing integrated modulators, the operation speed of the VCSEL is increased and the modulation signal range is extended to allow a wider range of modulation signals and modulation schemes, including large-signal digital modulation schemes.
US09281660B2	Surface emitting laser, surface-emitting-laser array, and image forming apparatus The present invention provides a surface emitting laser that provides a sufficient optical output and is suitable as a light source intended for electrophotographic apparatuses, and a surface-emitting-laser array and an image forming apparatus each including the surface emitting laser. The surface emitting laser includes a first stepped structure on a front surface of a front mirror. In the first stepped structure, a difference L between an optical path length in a first area and an optical path length in a second area satisfies the following expression: (¼+N)λ<\|L\|<(¾+N)λ where N is an integer.
US09281658B2	System and method for controlling collocated multiple wavelength tuned lasers Systems and methods are disclosed herein for controlling laser beams for a plurality of collocated laser assemblies. The laser beams are optimized by controlling outputs of a primary power source (current for generating a laser beam) and a secondary power source (heating device) for each of the respective laser assemblies. The states of the power supply may be cycled and modulated to provide optimal performance.
US09281649B2	Air-cooled gas lasers with heat transfer assembly and associated systems and methods Embodiments of an air-cooled gas laser with a heat transfer assembly are disclosed herein. A laser configured in accordance with one embodiment includes a laser superstructure and a laser superstructure having an opening and a cavity accessible through the opening, and an electrode assembly. The electrode assembly is configured to be received into the cavity, and includes a frame and an electrode biasedly coupled to the frame and electrically insulated therefrom.
US09281646B2	Electrical connector with additional power terminals An electrical connector comprises an insulative housing and a plurality of first conductive terminals retained in the insulative housing. The insulative housing defines a mating frame running through a front face thereof. An L-shaped mating tongue extends forwardly in the mating frame. The mating frame has two opposite inner surfaces facing to the mating tongue and spaced from the mating tongue. The first conductive terminal each includes a contacting portion arranged on a mating face of the mating tongue and a connecting portion extending out of the insulative housing. The electrical connector includes second conductive terminals disposed on both inner surface of the mating frame. The second conductive terminals are used for different-voltage power transmission. Therefore, the electrical connector not only meets the specification of SATA connector, but also provides the function of signal transmission and different-voltage power transmission.
US09281645B2	Electrical supply connector with a simplified mounting arrangement The invention relates to an electrical supply connector having a housing, a contact element on which an electrical port is formed and which is arranged so as to be displaceable inside the housing, in such manner that the contact element is displaceable between an extended position, in which the electrical port protrudes out of the housing in the area of a side surface and an electrical contact can thus be made with a conductor rail via the electrical port, and a retracted position in which the electrical port is arranged inside the housing and the electrical contact is disconnected, and an actuating element that is arranged in the area of a front cover surface on the housing and is displaceable between a release position and a coupling position, in such manner that when the actuating element moves into the coupling position it forces the contact element out of the retracted position and into the extended position thereof. The invention also relates to a system with a current conductor and an electrical supply connector.
US09281640B2	Connector A connector includes a ground pin and a signal pin. The ground pin includes a first cylindrical part, a first cylindrical terminal telescopically movable into the first cylindrical part, and a first elastic member compressible in a first central axis direction. The signal pin includes a second cylindrical part, a second cylindrical terminal telescopically movable into the second cylindrical part, and a second elastic member compressible in a second central axis direction. The signal pin is provided concentrically with the first elastic member and the first cylindrical part, and has a one-piece structure of a single metal plate. The first and the second cylindrical parts are connected to a ground line and a signal line of a board with the first and second cylindrical terminals being in contact with the board and compressed in the first and second central axis directions, respectively.
US09281639B2	Micro radio-frequency connector A micro radio-frequency connector includes an isolated body, a resilient terminal and an external terminal. The isolated body includes an accommodating slot and an inserting hole connected to the accommodating slot. The accommodating slot includes an upper inner wall and a lower inner wall opposite to each other. The resilient terminal is disposed inside the accommodating slot, and includes a fixing section, two resilient arms and a first contacting section. The fixing section is fixed to the accommodating slot. An end of the resilient arm is connected to the fixing section and contacts against the lower inner wall, the other end of the resilient arm is a free end to be separated from the lower inner wall while an external force is not applied to the first contacting section and further to contact against the lower inner wall while the external force is applied to the first contacting section.
US09281635B2	Connector and connector bar A connector includes a connecting terminal, a fixed contact, a movable plate, a movable contact provided at an end of the movable plate, a card that includes an insulator and contacts the movable plate, a button that contacts the card, an opening spring connected to the button, and a sliding operation part that controls a contact between the fixed contact and the movable contact. When the sliding operation part is moved in a first direction, the movable contact is brought into contact with the fixed contact and the connector is turned on. When the sliding operation part is moved in a second direction opposite to the first direction, the movable contact is caused to move away from the fixed contact and the connector is turned off. The sliding operation part is provided on a surface that is different from a surface on which the connecting terminal is provided.
US09281632B2	Communication jack having layered plug interface contacts A communication jack, system using the jack, and method of fabricating the jack are disclosed. The jack includes a cavity configured to accept a communication plug to form a communication connector. The jack includes a plurality of plug interface contacts that extend into the cavity such that a plug inserted into the cavity makes electrical contact with the plug interface contacts at plug/jack interfaces of the plug interface contacts. One or more of the plug interface contacts is formed from multiple conductive layers. The conductive layers are movable relative to each other at at least one end. A dielectric layer or flexible printed circuit board may be disposed between the conductive layers.
US09281628B2	Electrical connector assembly with improved contact A plug connector includes a plug housing (11) defining a receiving space (1110), a plurality of contacts retained in the plug housing, a cable (16) electrically connected with the contacts and a shielding member (15) enclosing on the plug housing to form a cavity. The contacts comprises a plurality of first contacts (12) and a plurality of second contacts (13), stiff contacting portions of the first contacts are exposed in the receiving space, and elastic contacting portions of the second contacts are exposed in the cavity for transmitting high speed signal. The shielding member is enclosing on the plug housing to form a cavity, the cavity is stacked on the receiving space. The slit is communicated with an exterior in the up-to-down direction, the plug connector further comprises an additional contact (18) received in the slit and extending beyond the bottom surface of the plug housing.
US09281624B2	Electrical connector with signal pathways and a system having the same Electrical connector including a connector body having a mating side configured to interface with an electrical component. The electrical connector also includes signal pathways extending through the connector body. The signal pathways are arranged to form pairs of signal pathways. The electrical connector also includes an impedance-control assembly having a plurality of dielectric bodies supported by the connector body. The dielectric bodies surround respective pairs of signal pathways. The dielectric bodies include a dielectric medium and gas bubbles distributed in the dielectric medium. The dielectric medium has a predetermined dielectric constant. The at least one of the gas bubbles or gas-filled particles are sized and distributed in the dielectric medium to achieve a target dielectric constant of the dielectric bodies.
US09281613B2	Battery wiring module A battery wiring module attached to a battery group formed by juxtaposing a plurality of batteries each having electrode terminals, includes: a plurality of bus bars; and a plurality of holder units made of an insulating resin and having holding portions and holding the bus bars. The holder units include: a first holder unit disposed at an end; and a second holder unit which is a holder unit other than the first holder unit. The holding portion of the second holder unit is provided with a bus bar insertion portion through which the bus bars are inserted in the direction in which the batteries are juxtaposed, and the second holding portion of the first holder unit is provided with an encompassing wall and adapted to insert the bus bars in a direction in which the first holder unit is attached to the battery group.
US09281610B2	Tray type card connector having a front cover with a sealing member Provided is a tray type card connector that is compatible with waterproof electronic devices and that can easily perform the insertion and removal of a card into/from the electronic devices. A tray type card connector includes a card tray; a housing having a tray insertion portion; a plurality of contacts arranged in the housing so as to project within the tray insertion portion; a front cover portion fitting in a casing opening portion opened at a lateral surface portion of a casing of an electronic device A, at a front end portion of the card tray; a ring-shaped cover water-sealing member made of an elastic material at an outer periphery portion of the front cover portion.
US09281606B2	Connector for automobile wiring harness A connector includes: a terminal; a housing; a rear holder; and a rubber plug. A terminal receiving chamber of the housing is provided with: a first receiving portion receiving a wire connecting portion, an electric wire connected to the wire connecting portion, and a rubber plug; a second receiving portion; and a step wall interposed between the first and second receiving portions and allowing a flange portion formed on the wire connecting portion to abut on the step wall. The rubber plug is composed of a ring-shaped packing attached to the electric wire and keeping a space between an outer peripheral wall of the electric wire and an inner wall of the first receiving portion watertight, and a resin member. The resin member is provided with a buried portion buried in the packing, and a cylinder portion extended from the buried portion and interposed between the flange and the packing.
US09281600B2	Connector with retainer having reinforced escaping portion A connector (10) includes a housing (30) with a terminal accommodating portion (31) into which a plurality of differently dimensioned terminals (20) are to be accommodated, and a retainer (60) retains the terminals (20) by being inserted through a side surface of the housing (30). The retainer (60) is moved laterally by operating an operating portion (63) and is held at a partial locking position and a full locking position by locking pieces (65) of the retainer (60) that engage locked portions (44) of the housing (30). The terminals (20) include medium terminals (20M) locked by medium locking lances (56) fit into an escaping portion (68) between the operating portion (63) and the locking pieces (65) in the retainer (60). The escaping portion (68) includes a reinforcement (69) for preventing deformation of the escaping portion (68).
US09281598B2	Contact element A contact element for making electrical contact with a contact area of a mating contact element, wherein a contact region forms at least two contact points, and wherein the two contact points are distinguished from one another in the new state in respect of the distance from the contact area of the mating contact element, so that, in the new state, a first of the contact points makes contact with the contact area and, after a defined amount of wear of the first contact point, the second contact point makes contact with the contact area.
US09281593B2	Connector which is reduced in possibility of damage due to warping of a connection object without decreasing the insertability of the connection object A connector is for connection to a plate-like connection object. The connector includes contacts, a housing holding the contacts, and an operating member for connecting the connection object to the contacts. The operating member has a pair of rotating shaft portions spaced apart from each other in a right-left direction and is rotatably supported by the housing so as to be displaceable between an initial position and a connecting position. The housing has a receiving portion which is open upward. The receiving portion is adapted to receive, from obliquely front, insertion of the connection object and to receive the operating member when the operating member is in the connecting position. The housing further has protruding portions in the rear part of the receiving portion for preventing upward warping of the connection object. The protruding portions are located between the pair of rotating shaft portions.
US09281592B2	Female connector and card edge connector A female connector has a plurality of contacts to be connected to a card member having a card edge portion with a plurality of card edge terminals formed on a substrate, and a housing disposed with contact housing portions, and the housing has a flat opening portion on one side into which the card edge portion is inserted, an insertion port on the other side, and an inner space therein communicating with the flat opening portion and disposed with the card edge portion, and the contact housing portion has at least two stages of first contact housing portions formed on one side relative to the inner space of the housing and communicating with the insertion port, and a stage of second contact housing portions formed on the other side relative to the inner space of the housing and communicating with the insertion port.
US09281590B1	Electrical connector having improved resonance An electrical connector includes an insulative housing having a longitudinal slot and at least one row of contacts retained in the housing. Each of the contacts defines a retention portion, a resilient contacting arm extending from the retention portion with a contacting portion protruding into the longitudinal slot, and a soldering tail extending out of the housing. The contacts include at least two differential pairs adjacent to each other and at least one grounding contact sandwiched therebetween in the longitudinal direction. The contacting portions of each differential pairs are closer to the mating face than the contacting portion of the grounding contact in the mating direction, which can improve resonance of the electrical connector during transferring high-speed signals.
US09281589B2	Electrical connector having better high-frequency performance An electrical connector includes an insulative housing and a plurality of conductive terminals fixed in the insulative housing. The conductive terminals includes a first terminal group, the first terminal group includes a plurality of signal terminals and a plurality of grounding terminals. The insulative housing defines a cured conductive adhesive, the cured conductive adhesive makes the grounding terminals of the first terminal group shorted to each other.
US09281584B2	Connector A connector reduced in height without reducing contact reliability. A contact of the connector includes a first spring portion that supports a contact portion, a second spring portion that supports a connection portion, and an integral connection portion that integrally connects the first spring portion and the second spring portion. The first spring portion and the second spring portion are arranged on an imaginary straight line that extends through the contact portion and is parallel to a connection direction, and the integral connection portion is made away from the imaginary straight line in a direction orthogonal to the connection direction.
US09281583B2	Electrical connector having improved insulative housing An electrical connector includes a first insulative housing having a first mating port and a second mating port arranged side by side, a plurality of first contacts retained to the first mating port, and a plurality of second contacts retained to the second mating port. The first mating port includes first and second mating tongues providing corresponding first and second mating faces opposite to each other. The second mating port defines a first strengthen arm adjacent to the first mating port to connect with the first and second mating tongues, the first contacts provide first contacting portions exposed upon both the first mating face and the second mating face.
US09281581B2	Wiring module for a battery module that has detection terminal for detecting state of electric cells A wiring module includes first detection terminals for detecting a state of electric cells, and a resin protector that retains the first detection terminals. The first detection terminals each include a first plate-shaped portion having a plate shape, and a first electric wire connecting portion continuous with the first plate-shaped portion and connected to a terminal portion of an electric wire W. The first plate-shaped portion is provided with projecting pieces for discriminating the front and back sides of the corresponding first detection terminal.
US09281579B2	Electrical connectors having leadframes An electrical connector includes a contact module having a leadframe and a dielectric frame surrounding the leadframe. The leadframe has signal conductors having transition contacts encased in the dielectric frame. The transition contacts are coplanar such that the transition contacts are arranged within a contact plane of the leadframe. The signal conductors have mating contacts extending from the corresponding transition contacts. Each of the mating contacts have a mating interface configured to be electrically connected to a corresponding mating contact of a mating connector. The mating contacts are arranged in pairs with the corresponding mating interfaces aligned in rows along corresponding row axes. Each of the pairs of mating contacts are arranged in different rows.
US09281575B2	Terminal A terminal is formed by bending a plate of electrically conductive metal and is received in a connector housing. The terminal includes a box-shaped body part, a terminal contact part provided on a front side of the body part, and an electrical wire connecting part provided on a rear side of the body part. When the plate before bending is viewed from the thickness direction, a conductor section having a cross-section having constant width and thickness extends from the terminal contact part to the electrical wire connecting part.
US09281573B2	Electrical plug connector for electrical connection by means of ultrasonic welding An electrical plug connector in the form of a solid contact pin that has a contact portion, a transition portion adjoining the contact portion, and a connection portion adjoining the transition portion for electrical connection to an electrical line by ultrasonic welding. The connection portion is formed from a first leg and a second leg and has at least one geometric wave refraction element for refracting waves during ultrasonic welding.
US09281572B2	Aperture synthesis communications system A method and apparatus are provided for improving capacity in wireless communications systems for use in areas having a high user traffic density. For reception, signals received from an antenna array are processed by performing a transformation comprising aperture synthesis to map signal content received from the antenna array to at least one element of a plurality of elements in an image plane storage to produce a time series of values for the at least one element, and then by assigning the at least one element to at least one radio access transceiver of a plurality of radio access transceivers for receiving the time series of values from the at least one element. For transmission, at least one radio access transceiver of a plurality of radio access transceivers is assigned to at least one element of a plurality of elements in an image plane storage, the assignment providing for the at least one element to receive a time series of values from the at least one radio access transceiver, and then a transformation is performed comprising antenna synthesis to map the time series of values from the at least one element to the signals for transmission by the antenna array.
US09281568B1	Apparatus and method for improving the gain and bandwidth of a microstrip patch antenna A method for improving bandwidth and gain of a microstrip patch antenna and a microstrip patch antenna are provided. The method includes forming a highly anisotropic superstrate, and positioning the highly anisotropic superstrate at a predetermined distance away from the ground plane side of the microstrip patch antenna, increasing the bandwidth of the microstrip patch antenna. The antenna provides a microstrip patch antenna having a highly anisotropic superstrate. The highly anisotropic superstrate can include a spacing layer, a dielectric material positioned on the spacing layer and a plurality of conductive strips disposed on the dielectric layer.
US09281565B2	Multi-frequency antenna A multi-frequency antenna includes a first antenna element, a second antenna element, a connection element, a third antenna element and a shorted element. The connection element is connected between the first antenna element and a neighborhood portion of the third antenna element. A feeding point is located in or nearby a first junction between the connection element and the first antenna element or located in the connection element. The shorted element is connected between the second antenna element and the grounding plane. The shorted element extends from a second junction between the second antenna element and the third antenna element to the grounding plane. The first conductive path that extends from the feeding point to the other end of the shorted element is substantially equal to a second conductive length that extends from the feeding point to the free end of the first antenna element.
US09281562B2	Apparatus with antenna and method for wireless communication An apparatus including a first port configured to couple to a first location on an antenna; a second port configured to couple to a second location on the antenna; a switch configured to switch between a first electrical configuration in which the first port is coupled to radio circuitry, and a second electrical configuration in which the second port is coupled to the radio circuitry; first reactive circuitry configured to impedance match the antenna with the radio circuitry at a first operational resonant frequency band; and second reactive circuitry, different to the first reactive circuitry, and configured to impedance match the antenna with the radio circuitry at a second operational resonant frequency band, different to the first operational resonant frequency band.
US09281558B2	High isolation electromagnetic transmitter and receiver A high isolation electromagnetic transmitter and receiver is revealed. An isolation portion, a first antenna body and a second antenna body are extended from and formed over a grounding portion. The isolation portion is extended to and formed between the first antenna body and the second antenna body. A parasitic element corresponding to the isolation portion is disposed between the first antenna body and the second antenna body. The isolation portion is T-shaped. The parasitic element is reverse T-shaped and arranged over the grounding portion. The structure is simple and able to be applied to the design of planar printed antennas. The production is easy and the cost is reduced. The volume is minimized to be used in various mini wireless mobile communication devices. No interference occurs even that the first and the second antennas are close due to good isolation.
US09281554B1	Balloon with pressure mechanism to passively steer antenna Methods and apparatus are disclosed for passively steering an antenna disposed on a balloon in a balloon network. An example balloon involves: (a) an antenna and (b) a pressure-sensitive mechanism in mechanical communication with the antenna such that a change in the balloon's altitude causes at least an element of the antenna to rotate upward or downward, a separation distance between two or more radiating elements to increase or decrease, or a separation distance between the two or more radiating elements and a reflector to increase or decrease.
US09281550B2	Wave mode converter Wave mode converters, and methods of using wave mode converters are disclosed. The wave mode converters include a radial waveguide including a generally disk-like structure to receive a radially propagating field derived from rectangular TE10 waveguide mode, and a body including a plurality of spaced apart apertures.
US09281546B2	Battery pack case having novel structure Disclosed herein is a battery pack case in which a battery module having a plurality of stacked battery cells or unit modules (‘unit cells’) is mounted, wherein the battery pack case is provided at the upper part and the lower part thereof with a coolant inlet port and a coolant outlet port, respectively, which are directed in opposite directions such that a coolant to cool the unit cells can flow from one side to the other side of the battery module in a direction perpendicular to a cell stacking direction, the battery pack case is further provided with a flow space (‘coolant introduction part’) extending from the coolant inlet port to the battery module and another flow space (‘coolant discharge part’) extending from the battery module to the coolant outlet port, and the flow channel width of the coolant introduction part and/or the flow channel width of the coolant discharge part is greater than that of each of the unit cells, thereby achieving uniform distribution of the coolant.
US09281544B2	Battery pack test system A battery pack test system is provided. The system includes a battery charging device that monitors an output voltage level of the vehicle battery pack. The system further includes a switch electrically coupled between an igniter and a voltage source. The system further includes a first video camera that generates a first plurality of images of an interior of the vehicle battery pack. The switch has a closed operational state at a first time in response to the output voltage level of a battery cell in the vehicle battery pack being greater than a threshold voltage level, to induce the igniter to generate a spark to generate a fire within an interior region of the vehicle battery pack.
US09281541B2	Nonaqueous electrolyte for secondary battery and nonaqueous-electrolyte secondary battery employing the same An object is to provide a nonaqueous electrolyte and a nonaqueous-electrolyte secondary battery which have excellent discharge load characteristics and are excellent in high-temperature storability, cycle characteristics, high capacity, continuous-charge characteristics, storability, gas evolution inhibition during continuous charge, high-current-density charge/discharge characteristics, discharge load characteristics, etc. The object has been accomplished with a nonaqueous electrolyte which comprises: a monofluorophosphate and/or a difluorophosphate; and further a compound having a specific chemical structure or specific properties.
US09281539B2	Electrical storage device including fiber electrode, and method of fabricating the same An object of the present invention is to provide a highly efficient electrical storage device that uses a fiber positive electrode and a fiber negative electrode and in which lithium ion is used as an intercalating species, and to provide a method of fabricating the electrical storage device. The electrical storage device according to the present invention includes: a fiber positive electrode including an electrically conductive fiber, the fiber having a surface on which a positive electrode active material coating is formed, the positive electrode active material coating containing a transition metal oxide represented by a chemical formula 1 which is (Li1-xAx)aMbXcOd; a fiber negative electrode including an electrically conductive fiber, the fiber having a surface on which a negative electrode active material coating is formed; a separator; and an electrolyte (in the chemical formula 1, A is at least one kind of alkali metal selected from the group consisting of Na, K, Rb, and Cs; M is at least one kind of transition metal selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Nb, Mo, Ru, Pd, Ag, Ta, W, Ce, Pr, Sm, Eu, and Pb; X is at least one kind of typical elements selected from the group consisting of B, Al, Si, P, S, Ga, and Ge; and 0
US09281536B2	Material design to enable high mid-temperature performance of a fuel cell with ultrathin electrodes A fuel cell including at least one of a hydrophilic interlayer and a flow field treated to impart hydrophilic properties is disclosed, wherein the hydrophilic interlayer and the treated flow field militate against water accumulation in ultrathin electrodes of the fuel cell, particularly for cool-start operating conditions (i.e. about 0° C. to about 60° C.).
US09281529B2	Protective edge seal having alkali metal ions for membrane ion exchange A unitized electrode assembly (10; 110; 210; 310; 410) for a fuel cell includes, in addition to an anode catalyst layer (54; 254) and a cathode catalyst layer (56; 256), a polymer electrolyte membrane (52) having an acid functional group normally including H+ ions and an edge seal (66; 166; 266, 366, 466) containing alkali metal ions in a form, concentration, and/or location for delivery and dispersion into the membrane. The edge seal of the unitized electrode assembly is proximate, and typically contacts, the peripheral edge region (68) of the membrane in ion-transfer relation therewith, and alkali metal ions leach into the membrane during fuel cell operation to provide a desired ion exchange in the membrane. The alkali metal ions contained by the edge seal may be Li+, Na+, K+, Rb+, and/or Cs+, and may be included as a dopant with the material of the edge seal during its formation, or may be included as a discrete component of the edge seal, as by an ion-doped strip of membrane material contained by the edge seal. The edge seal thus serves as a “reservoir” of the alkali metal ions for release to the polymer electrolyte membrane for increased durability.
US09281524B2	Metal air battery The invention provides a metal air battery with improved discharge characteristics compared to conventional ones. This is achieved by a metal air battery including a positive electrode layer, a negative electrode layer, and an electrolyte layer positioned between the positive electrode layer and the negative electrode layer, wherein the positive electrode layer includes an electroconductive material, a binder, and a SiO2 particle, and wherein the SiO2 particle has a specific surface area of 16.7 m2/g or less.
US09281516B2	Cathode material of lithium ion secondary battery and method for manufacturing the same A cathode material of a lithium ion secondary battery is provided, which includes a cathode active material and a glassy material coating on a surface of the cathode active material. The glassy material is capable of selectively allowing lithium ions to pass therethrough. The lithium ion secondary battery using the cathode material has the long cycle life and the high safety performance.
US09281508B2	Separator for nonaqueous secondary battery, and nonaqueous secondary battery An object of the invention is to provide a separator for a nonaqueous secondary battery, which has good adhesion to electrodes and is also capable of ensuring sufficient ion permeability even after attachment to electrodes. The separator for a nonaqueous secondary battery of the invention includes a porous substrate and an adhesive porous layer that is formed on at least one side of the porous substrate and contains a polyvinylidene-fluoride-based resin. The separator for a nonaqueous secondary battery is characterized in that the adhesive porous layer has a crystal size of 1 to 13 nm.
US09281504B2	Method for fabricating battery shell A non-contact input apparatus for computer peripheral includes an induction module and a pointing module. The induction module includes an electric supply coil and an induction element, and the pointing module includes an energy coil and a non-linear element. The electric supply coil is used to send a first oscillation signal. The energy coil receives the first oscillation signal. The non-linear element converts the first oscillation signal to be a second oscillation signal having multiple higher harmonics. The induction element generates a control signal based on the second oscillation signal.
US09281498B2	Organic EL device An organic EL device that efficiently extracts light includes an organic EL element formed by laminating a first electrode layer, functional layer, and second electrode layer on a substrate and a sealing member sealing the organic EL element. The organic EL device has a first electrode communicating part electrically connected to the first electrode layer at one side of the substrate and a second electrode communicating part electrically connected to the second electrode layer at the other side of the substrate. The organic EL device has first cross grooves crossing the organic EL element from the second electrode layer located at the one side to the second electrode layer that is located at the other side. The first cross groove is formed by removing the first electrode layer, functional layer, and second electrode layer. The sealing member and the substrate are connected outside of the first cross grooves.
US09281494B2	Display device and organic light emitting diode display A display device includes: a display substrate; a display unit formed on the display substrate and a sealing substrate affixed to the display substrate by an adhering layer that surrounds the display unit. The sealing substrate includes a composite member including a resin and a plurality of carbon fibers and an insulating member attached to the composite member. The insulating member includes a through hole. A metal film is disposed at one side of the sealing substrate, facing the display substrate; and a conductive connection portion contact the metal film through the through hole.
US09281492B2	Electro-optic device and method for manufacturing same According to the present invention, an electro-optic device comprises: a substrate which is split into a light emitting unit and a non-light emitting unit, wherein said light emitting unit is divided into a plurality of driving regions; an electrode pad which is formed in the non-light emitting unit of the substrate; and an electrode unit which comprises a plurality of supplementary electrodes each of which has one end connected to the electrode pad and has the other end connected to the centers of each of the plurality of driving regions, and transparent electrodes formed on the upper sides of the plurality of supplementary electrodes in the light emitting unit, wherein the area of each of the plurality of driving regions is set to an area in which no voltage drop occurs, and the plurality of supplementary electrodes are manufactured in the same length. Thus, according to the present invention, if power is supplied to each one end of the plurality of supplementary electrodes by using the electrode pad, the power is transmitted, at the same time, to the other ends of each of the plurality of supplementary electrodes. Therefore, the power is simultaneously supplied to each center of the plurality of driving regions regardless of the distance between the electrode pad and the driving regions. Further, as mentioned above, a voltage drop phenomenon is prevented since the light emitting unit is divided into the plurality of driving regions in which no voltage drop occurs. That is to say, uniform currents can flow on the front side of each driving region irrespective of the distance between the supplementary electrodes and the driving regions. Consequently, a large-scaled organic light emitting device which can show uniform brightness properties in the overall light emitting unit can be manufactured.
US09281485B2	Light-receiving device For simplification of a structure and a manufacturing process of an element, and reduction of manufacturing cost, the present disclosure provides a light-receiving device including: a photoelectric conversion element; and an active element, wherein the active element includes at least one of a reset element configured to reset the photoelectric conversion element, an amplifier element configured to amplify a detection signal based on the photoelectric conversion element, or a selection element configured to selectively output the detection signal based on the photoelectric conversion element, and the photoelectric conversion element and at least part of the active element are formed by using an identical organic semiconductor material or an identical high molecular functional material.
US09281479B2	Apparatus and method for fabricating organic light emitting display An apparatus for fabricating an organic light emitting display includes a chamber, a stage having a hollow portion, a displacement sensor on the stage and configured to measure a distance between the stage and a measurement target that is on or over an upper part of the stage, and a controller. The controller includes an input unit configured to receive distance information obtained by the displacement sensor, a memory unit configured to store reference distance information, a determination unit configured to compare the distance information received by the input unit with the reference distance information, and an output unit configured to output a variable control signal according to whether or not the determination unit determines that the distance information between the stage and the measurement target corresponds to the reference distance information. A method for fabricating an organic light emitting display using the apparatus is also provided.
US09281478B2	Phase change memory cell with constriction structure Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
US09281475B2	Resistive random-access memory (RRAM) with multi-layer device structure A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.
US09281468B2	Magnetic memory element The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20. Also a spin transfer torque magnetic random access memory element is disclosed having a perpendicular magnetic orientation comprising a metal underlayer on a substrate, a seed layer on the metal underlayer; the seed layer comprising alternating layers of a first metal and a second metal, a magnetic tunnel junction (MTJ) element with a perpendicular orientation including: a reference layer formed on the seed layer, a tunnel barrier layer formed on the reference layer, a storage layer formed on the tunnel barrier layer and a top electrode and a bottom electrode.
US09281463B2	Atomic layer deposition of metal-oxide tunnel barriers using optimized oxidants Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.
US09281462B2	Thermo-electric power harvesting bearing configuration A power generating bearing assembly (100) comprises a bearing subassembly (120) retained by a bearing housing (110). During operation, friction and other factors increase a temperature of the bearing assembly (100). The housing (110) can optionally include a bearing cooling passage system comprising at least one liquid cooling passage (134) formed internally therein. The liquid cooling passage (134) would be routed proximate the bearing subassembly (120) to remove heat therefrom. A thermo-generator cavity (180) extends inward from an exterior surface of the housing (110), terminating at a cavity end wall (182). The cavity (180) is formed at a location identified having a higher temperature. A Thermo-Electric Generator (TEG) (200) is inserted within the cavity (180) and thermally coupled to the end wall (182). The Thermo-Electric Generator (TEG) (200) utilizes a temperature difference between the end wall (182) and the ambient air to generated electric power. The power can be used to operate electrically powered devices, such as condition sensors (150), communication devices, and the like.
US09281461B2	Thermoelectric devices and applications for the same High performance thin film thermoelectric couples and methods of making the same are disclosed. Such couples allow fabrication of at least microwatt to watt-level power supply devices operating at voltages greater than one volt even when activated by only small temperature differences.
US09281459B2	Light-emitting device A light-emitting device includes a substrate; a stacked structure including a first type semiconductor layer positioned on the substrate, a light-emitting structure positioned on the first type semiconductor layer, and a second type semiconductor layer positioned on the light-emitting structure, wherein the stacked structure includes a depression exposing the first type semiconductor layer; a first electrode positioned on the first type semiconductor layer in the depression, the first electrode including at least one first pad and at least one first extending wire with one end connected to the first pad; a second electrode positioned on the second type semiconductor layer, the second electrode including at least one second pad and at least one second extending wire with one end connected to the second pad; wherein the distance between the first pad and the second pad is greater than 70% of the width of the light-emitting device.
US09281458B2	Optoelectronic semiconductor component and method for the production thereof An optoelectronic semiconductor device including a carrier substrate and at least one semiconductor chip arranged thereon, wherein the semiconductor chip includes an active layer that generates radiation, conductor tracks electrically contacting the semiconductor chip arranged on the carrier substrate, the semiconductor chip is enclosed in a potting material, and the potting material includes at least a first potting layer, a second potting layer and a third potting layer, which differ from one another in at least one of: their material composition, their optical properties and their chemical properties.
US09281456B2	Light emitting device and fabricating method thereof A light-emitting device includes a light-emitting element for emitting primary light, and a wavelength conversion unit for absorbing part of the primary light and emitting secondary light having a wavelength longer than that of the primary light, wherein the wavelength conversion unit includes plural kinds of phosphors having light absorption characteristics different from each other, and then at least one kind of phosphor among the plural kinds of phosphors has an absorption characteristic that can absorb the secondary light emitted from at least another kind of phosphor among the plural kinds of phosphors.
US09281454B2	Thin film light emitting diode Light emitting devices comprise a substrate having a surface and a side surface; a semiconductor structure on the surface of the substrate, the semiconductor structure having a first surface, a second surface and a side surface, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the substrate, and wherein the semiconductor structure comprises a first-type layer, a light emitting layer and a second-type layer; a first and a second electrodes; and a wavelength converting element arranged on the side surface of the semiconductor structure, wherein the wavelength converting element has an open space, and wherein the open space is a portion not covered by the wavelength converting element.
US09281452B2	Method for manufacturing a can package-type optical device, and optical device manufactured thereby The present invention relates to a method for manufacturing an optical device, and to an optical device manufactured thereby, which involve using a substrate itself as a heat-dissipating plate, and adopting a substrate with vertical insulation layers formed thereon, such that electrode terminals do not have to be extruded out from a sealed space, and thus enabling the overall structure and manufacturing process for an optical device to be simplified.According to the present invention, a method for manufacturing a can package-type optical device comprises the steps of: (a) preparing a metal plate and a metal substrate with vertical insulation layers, wherein more than one vertical insulation layer crossing the substrate from the top surface to the bottom surface thereof are formed; (b) bonding the metal plate on the top surface of the metal substrate with vertical insulation layers; (c) forming a cavity on an intermediate product that has undergone step (b) in a form of a cylindrical pit having a predetermined depth reaching the surface of said metal substrate with vertical insulation layers by passing through said metal plate and the adhesive layers formed by said bonding, wherein said cavity contains said vertical insulation layer in the bottom wall thereof; (e) connecting a wire, which electrically connects an optical device and an electrode of the optical device together, to either side of the surface of the bottom wall of the vertical insulation layers of the cavity, respectively; and (g) sealing the cavity by means of a protective plate made from a light-transmitting material; and a can cap, formed as a picture frame whose top central portion and the bottom are open and encompassing the perimeter of the protective plate.
US09281448B2	Light emitting apparatus A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.
US09281437B2	Light emitting device, and method for fabricating the same Disclosed are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, an electron blocking layer on the active layer, and a second conductive semiconductor layer on the electron blocking layer. The electron blocking layer includes a first electron blocking layer and an interrupted diffusion layer on the first electron blocking layer.
US09281435B2	Light to current converter devices and methods of manufacturing the same Light to current converter devices, such as solar cells, are disclosed. The devices may include via holes extending through the cell substrate and may include through-hole electrodes within the via holes. The through-hole electrodes may be made from one or more materials and may be hollow, partially hollow, or fully filled. Front and rear electrodes may also be formed on the device and can be made of the same or different materials as the through-hole electrode. The devices may include emitters located only on the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, or located on the top surface and full inner surface of the via holes. Processes for making light to current converter devices are also disclosed.
US09281432B2	Photoelectric conversion element, method for manufacturingthe same, optical sensor, and solar cell A photoelectric conversion element includes a PN junction formed between an N-type oxide layer and a P-type oxide layer, in which the N-type oxide layer is formed of an oxide having a perovskite structure containing titanium and strontium, a part of strontium is substituted with a +3 valence metal element or a part of titanium is substituted with a +5 valence metal element, and the amount of the metal element substituted in the N-type oxide layer is 0.01 mass % to 0.75 mass %.
US09281429B2	Module level solutions to solar cell polarization A solar cell module includes interconnected solar cells, a transparent cover over the front sides of the solar cells, and a backsheet on the backsides of the solar cells. The solar cell module includes an electrical insulator between the transparent cover and the front sides of the solar cells. An encapsulant protectively packages the solar cells. To prevent polarization, the insulator has resistance suitable to prevent charge from leaking from the front sides of the solar cells to other portions of the solar cell module by way of the transparent cover. The insulator may be attached (e.g., by coating) directly on an underside of the transparent cover or be a separate layer formed between layers of the encapsulant. The solar cells may be back junction solar cells.
US09281428B2	Mounting system for photovoltaic panels A mounting system for mounting photovoltaic panels on a support structure. The mounting system comprises photovoltaic panel frames in which the photovoltaic panels are mounted, panel support rails, and mounting brackets or cross beams for supporting the panel support rails. The panel frames have inwardly extending panel frame extensions on their back side. The panel support rails are mounted on the support structure with either pivoting brackets or cross beams. In either case, the support rails have pairs of stationary clamps and movable clamps with clamp lips that engage the panel frame extensions of the panel frames.
US09281425B2	Method for producing an optoelectronic semiconductor component and such a semiconductor component A method for producing a semiconductor component is disclosed. A carrier substrate includes a mounting region and an opening, which is formed in the mounting region of the carrier substrate. After mounting a semiconductor chip, an electrically insulating layer is applied to the carrier substrate in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate. A second opening is formed in the electrically insulating layer. An electrically conductive layer is then applied to the electrically insulating layer in such a way that the second opening is filled with the electrically conductive layer in the form of a via. A semiconductor component produced in this way is also provided.
US09281423B2	Image pickup apparatus, endoscope and image pickup apparatus manufacturing method An image pickup apparatus includes: a cover glass portion having a function of a right angle prism; an image pickup device substrate portion including an image pickup device on a first principal surface and a back-face electrode on a second principal surface, the back-face electrode being connected to the image pickup device via a through-wiring; and a bonding layer that bonds the cover glass portion and the image pickup device substrate portion that have a same outer dimension.
US09281417B1	GaN-based schottky diode having large bond pads and reduced contact resistance A semiconductor device includes a first active layer disposed over a substrate. The second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. The first electrode establishes a Schottky junction with the second active layer. The first electrode includes a first electrode pad and a first series of fingers in electrical contact with the first electrode pad. The second electrode establishes an ohmic junction with the first active layer. The second electrode includes a second electrode pad and a second series of fingers in electrical contact with the second electrode pad. The first and second series of electrode fingers form an interdigitated pattern. The first electrode pad is located over the first and second series of electrode fingers.
US09281416B2	Trench MOSFET with integrated Schottky barrier diode A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
US09281414B2	Vertical cell-type semiconductor device having protective pattern According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
US09281413B2	Enhancement mode device An enhancement mode device includes a floating gate structure. The floating gate structure includes a first bottom dielectric layer, a second bottom dielectric layer on the first bottom dielectric layer and a conductive floating gate on the second bottom dielectric layer.
US09281410B2	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device including an oxide semiconductor includes the steps of forming an oxide semiconductor film, forming a gate insulating film provided over the oxide semiconductor film, forming a gate electrode in contact with the gate insulating film, a sidewall insulating film in contact with the gate electrode, and forming a source electrode and a drain electrode in contact with the oxide semiconductor film. In the method, the gate insulating film and the sidewall insulating film are formed at a temperature at which oxygen contained in the oxide semiconductor film is inhibited from being eliminated, preferably at a temperature lower than a temperature at which oxygen contained in the oxide semiconductor film is eliminated.
US09281408B2	Semiconductor device A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
US09281402B2	Methods of fabricating fin structures There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
US09281401B2	Techniques and configurations to reduce transistor gate short defects Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.
US09281398B2	Semiconductor structure and method for manufacturing the same The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.
US09281396B2	Semiconductor device A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
US09281395B2	Semiconductor device and fabrication method thereof A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.
US09281393B2	Super junction semiconductor device and associated fabrication method A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.
US09281392B2	Charge compensation structure and manufacturing therefor A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region. In a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further includes: an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface, a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants, and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area. The first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration and are in Ohmic contact with the drain region. The second pillar regions are of a second conductivity type and in Ohmic contact with the source metallization. At least one of an outermost of the first pillar regions and an outermost of the second pillar regions forms an interface with the low-doped semiconductor region. A horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.
US09281391B2	Semiconductor device and method of manufacturing semiconductor device A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.
US09281389B2	Semiconductor device Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers.
US09281383B2	Method for fabricating a semiconductor device A method for fabricating a semiconductor device according to an embodiment, includes forming a silicon (Si) film containing carbon (C) in an upper portion thereof above a semiconductor substrate, performing element isolation of the Si film and the semiconductor substrate to make a width dimension of the Si film narrow in a first region and a width dimension of the Si film wide in a second region, after the element isolation, exposing a side face of the Si film in at least the first region, and diffusing boron (B) into the Si film from the side face of the Si film in the first region.
US09281379B1	Gate-all-around fin device A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
US09281376B2	Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
US09281372B2	Metal gate structure and manufacturing method thereof The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.
US09281364B2	Semiconductor device and method of manufacturing the same In a semiconductor substrate preparation step, a semiconductor substrate which is made of SiC and in which a first semiconductor region of a first conductivity type is formed is prepared. In a second semiconductor region forming step, a second semiconductor region is formed by implanting an impurity of a second conductivity type into a first semiconductor region through multiple ion implantation steps while varying implantation depths of the respective multiple ion implantation steps. In the second semiconductor region forming step, a dose amount of the impurity when an implantation energy of multiple ion implantation steps is the largest is smaller than a dose amount of impurity when the implantation energy is not the largest.
US09281353B2	Organic thin film transistor array substrate, method for manufacturing the same and display device According to embodiments of the present invention, there are provided an organic semiconductor array substrate, a method for manufacturing the same and a display device. The organic thin film transistor array substrate comprises a pixel structure formed on a transparent substrate; the pixel structure includes: a gate line, a data line, an organic thin film transistor, a pixel electrode, a common electrode line and a common electrode; the organic thin film transistor includes a gate electrode, a gate insulating layer, an organic semiconductor layer, a source electrode and a drain electrode; above the data line, the source electrode, the drain electrode and the pixel electrode, there are disposed in order a first bank insulating layer and a second bank insulating layer from bottom to top; and at openings and through holes of the first bank insulating layer and the second bank insulating layer, the pixel structure is formed by printing.
US09281351B2	Organic light-emitting display apparatus An organic light-emitting display apparatus may include a substrate; a thin-film transistor (TFT) disposed on the substrate, and having an active layer, a gate electrode, a source electrode and a drain electrode; a signal line formed on the same layer as the source electrode and the drain electrode; a first insulating layer covers the signal line, the source electrode, and the drain electrode; a pixel electrode formed on the first insulating layer, and electrically connected to the TFT; a pixel-defining layer formed on the first insulating layer, includes an opening exposing the pixel electrode; an intermediate layer formed on the pixel electrode, and includes a light-emitting layer; and an opposite electrode formed on the intermediate layer. The intermediate layer is formed on the pixel-defining layer so as to overlap with the signal line.
US09281350B2	Thin film transistor substrate and display An embodiment of the invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.
US09281349B2	Organic light-emitting display device The organic light emitting display device includes a substrate including a thin film transistor (TFT) formed thereon, the TFT including a first insulating layer disposed between an active layer and a gate electrode, and a second insulating layer disposed between the gate electrode and source and drain electrodes; a pad electrode including a first pad layer disposed on a same layer as that where the source and drain electrodes are formed, and a second pad layer on the first pad layer; a bonding assistant layer on the substrate; a third insulating layer on the bonding assistant layer and including a first opening; a pixel electrode disposed in the first opening and electrically coupled to one of the source and drain electrodes; and a fourth insulating layer on the pixel electrode to cover a peripheral end portion of the pixel electrode and defining a pixel through a second opening.
US09281348B2	Display panel and fabricating method thereof A display panel and a fabricating method thereof are provided, and the display panel (100) comprises: a first substrate (11); a second substrate (12), arranged parallel to the first substrate; an anode/cathode (41), formed on the first substrate; a cathode/anode (42), formed on the second substrate; a first alignment layer (31), provided on the anode/cathode and comprising a plurality of first sub-alignment layers (311) having a first alignment direction and a plurality of second sub-alignment layers (312) having a second alignment direction alternately arranged in a first direction, and a angle between the first alignment direction and the second alignment direction being 90 degrees; a second alignment layer (32), provided on the cathode/anode and comprising a plurality of third sub-alignment layers (323) having the first alignment direction and a plurality of fourth sub-alignment layers (324) having the second alignment direction alternately arranged in the first direction, and the first sub-alignment layers corresponding to the third sub-alignment layers in a position, and the second sub-alignment layers corresponding to the fourth sub-alignment layers in a position; and a light emitting layer (40), provided between the first alignment layer and the second alignment layer, which comprises a liquid crystal polymer doped with organic light emitting material and is configured to emit a polarized light.
US09281346B1	Display device A display device includes an array substrate including a display area and a non-display area, a driving circuit chip disposed on the non-display area and including a bottom surface, a top surface, a first pair of side surfaces extending in a first direction, and a second pair of side surfaces extending in a second direction perpendicular to the first direction, and first, second, and dummy bumps, each disposed on the bottom surface in a single column along the first direction, in which the dummy bumps include first and second dummy bump groups disposed between the first and second bumps along the first direction, the dummy bumps in the first dummy bump group are spaced apart from each other by a first pitch, and the dummy bumps in the second dummy bump group are spaced apart from each other by a second pitch different from the first pitch.
US09281345B2	Resistance change type memory device with three-dimensional structure According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.
US09281344B2	Magnetic memory device The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.
US09281343B2	Thin film transistor display panel and method of manufacturing the same A thin film transistor display panel includes: a gate electrode, a source electrode and a drain electrode which are included in a thin film transistor on a substrate; a data line connected to the source electrode; a pixel link member connecting the drain electrode to a pixel electrode; and a gate pad connected to the gate electrode through a gate line and including a first gate subpad, a second gate subpad and a gate pad link member, in which the pixel link member and the gate pad link member are substantially same in thickness.
US09281342B2	Light emitting device and light emitting device package A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer on the first electrode; a second electrode on the light emitting structure; and a control switch installed on the light emitting structure to control the light emitting structure.
US09281340B2	Manufacturing method for photoelectric conversion apparatus and photoelectric conversion apparatus A manufacturing method for a photoelectric conversion apparatus in which a microlens is arranged for multiple electric charge accumulation regions formed on a semiconductor substrate, includes forming a first impurity region of a first conductive type on the semiconductor substrate; and forming a second impurity region of a second conductive type that is opposite the first conductive type in a part of the first impurity region to isolate the first impurity region into multiple regions such that each of the multiple electric charge accumulation regions includes isolated first impurity regions.
US09281338B2	Semiconductor image sensor device having back side illuminated image sensors with embedded color filters A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. The radiation-sensing regions are separated by a plurality of gaps. A plurality of radiation-blocking structures is disposed over the second side of the substrate. Each of the radiation-blocking structures is aligned with a respective one of the gaps. A plurality of color filters are disposed in between the radiation-blocking structures.
US09281335B2	Alignment marks and alignment methods for aligning backside components to frontside components in integrated circuits An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes.
US09281334B2	Pickup device structure within a device isolation region A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
US09281328B2	Image sensor that includes a boundary region formed between a logic circuit region and an image-sensing element region and manufacturing method thereof According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate and element isolation portions formed to isolate the image-sensing elements, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy element isolation portions are arranged with a constant pitch in the boundary region between the image-sensing element region and the logic circuit region.
US09281326B2	Array substrate and manufacturing method thereof and display panel The invention provides an array substrate, a method for manufacturing the array substrate, and a display panel, the array substrate includes a plurality of thin film transistors, and the method includes: S1. preparing a base substrate on which sources and drains of the thin film transistors are formed; S2. forming an insulation layer on the base substrate such that the insulation layer includes spacer regions and a plurality of strip-shaped electrode regions, and every two adjacent strip-shaped electrode regions are separated from each other by the spacer region; S3. forming a spacer layer on the spacer regions of the insulation layer; S4. forming a pattern including strip-shaped electrodes on the strip-shaped electrode regions of the insulation layer; S5. peeling off the spacer layer on the spacer region. The invention can prevent every two adjacent strip-shaped electrodes from interconnecting due to etching residues, so as to improve product performance.
US09281323B2	Array substrate, display panel and display device An array substrate is disclosed. The array substrate includes a non-display region surrounding a display region. The array substrate also includes gate lines in the display region, and a gate drive circuit and a bus electrically insulated from the gate lines and a gate drive circuit in the non-display region. The gate lines extend into the non-display region and are electrically connected to the gate drive circuit, and each of the gate lines crosses the bus in a first overlap region. The array substrate also includes auxiliary electrode line segments between the bus and the display region. The auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and the auxiliary electrode line segments are disposed in either of a same conductive layer as the bus, or a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed.
US09281322B2	Thin film transistor array panel and method for manufacturing the same A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.
US09281321B2	TFT array substrate, display panel and display device A TFT array substrate includes a first electrode layer and a second electrode layer disposed below the first electrode layer. The first electrode layer includes a strip-like first electrode, and the second electrode layer is a sheet-like electrode. The strip-like first electrode includes a bent portion. The second electrode layer includes at least one opening, the opening is located below the bent portion.
US09281320B2	Array substrate and liquid crystal display apparatus having the same An array substrate includes a substrate, a switching element, a pixel electrode, and a common electrode. The substrate includes a plurality of gate lines, data lines insulated from the gate lines, and the data lines extend in a direction crossing the gate lines. The switching element is connected to the gate lines and data lines. The pixel electrode is arranged in a pixel area which is defined on the substrate, and is connected to an output electrode of the switching element. The common electrode corresponds to the pixel area and is insulated from the pixel electrode, and the common electrode has at least one first slit corresponding to the data line.
US09281318B2	Three dimensional memory structure A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.
US09281317B2	3D non-volatile memory with metal silicide interconnect A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
US09281313B2	Single poly non-volatile memory cells A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.
US09281310B2	Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
US09281309B2	Cross-hair cell wordline formation Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch.
US09281308B2	Method to tune narrow width effect with raised S/D structure A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
US09281307B2	Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.
US09281305B1	Transistor device structure A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.
US09281304B2	Transistor assisted ESD diode An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin.
US09281296B2	Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.
US09281295B2	Embedded heat spreader for package with multiple microelectronic elements and face-down connection A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate.
US09281294B2	Multi-chip semiconductor device A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other.
US09281293B2	Microelectronic packages having layered interconnect structures and methods for the manufacture thereof Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.
US09281292B2	Single layer low cost wafer level packaging for SFF SiP In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.
US09281289B2	Semiconductor device and method of manufacturing the same To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger.
US09281285B1	Input/output termination for ripple prevention Aspects of this disclosure relate to a termination circuit configured to mitigate crosstalk from a radio frequency (RF) input/output (I/O) path to a second I/O path, such as a digital I/O path. Such crosstalk can be due to coupling between adjacent bond wires, for example. The termination circuit can include a low impedance loss path, such as a series RC shunt circuit. According to certain embodiments, an electrostatic discharge (ESD) protection circuit can be in parallel with the termination circuit.
US09281284B2	System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.
US09281282B2	Substrate capable of electrostatic self-protection and manufacturing method thereof A substrate capable of electrostatic self-protection and a manufacturing method thereof, and the substrate (1) comprises: a panel area (2); and a first gate metal layer (3) and a source/drain metal layer (5) disposed on at least one side of the panel area (2). The first gate metal layer (3) and the source/drain metal layer (5) are arranged parallel to each other in a longitudinal direction and adjacent to each other; at least one tip (31) is protruded from the first gate metal layer (3) towards the source/drain metal layer (5); and/or at least one tip (31) is protruded from the source/drain metal layer (5) towards the first gate metal layer (3).
US09281272B2	Semiconductor device including conductor patterns as electrodes of a capacitive element and manufacturing method thereof The present invention is capable of suppressing a variation in the characteristics of a semiconductor device. In a conductor pattern CPA and a conductor pattern CPB arranged so as to run side by side with each other, the conductor pattern CPA is divided into a first portion P1 (A) and a second portion P2 (A), and the conductor pattern CPB is also divided into a first portion P1 (B) and a second portion P2 (B). The first portion P1 (A) of the conductor pattern CPA and the second portion P2 (B) of the conductor pattern CPB are formed by first patterning using the same first mask, while the second portion P2 (A) of the conductor pattern CPA and the first portion P1 (B) of the conductor pattern CPB are formed by second patterning using the same second mask.
US09281270B2	Method for making contact with a semiconductor and contact arrangement for a semiconductor The invention relates to a method for making contact with a semiconductor (10), and to a contact arrangement (1) for a semiconductor (10), wherein the semiconductor (10) is a really connected to a first contact partner (20) at at least one first area by the formation of a first soldering layer (30) having a predefined thickness. According to the invention, a polyimide layer (14) is applied as delimiting means on the semiconductor (10), said polyimide layer predefining the dimensions and/or the form of at least one soldering area (12) of the semiconductor (10).
US09281267B1	Semiconductor package having overhang portion A semiconductor package may include a substrate, and a structural body disposed over the substrate. The semiconductor package may include a semiconductor chip stacked over the structural body, and having an overhang portion projecting over a side surface of the structural body and overhanging out over the side surface of the structural body. The semiconductor package may include one or more bonding pads disposed on the overhang portion, and one or more wires electrically coupling the bonding pads to the substrate. The semiconductor package may include a wire fixing film attached onto the structural body, and overhanging out over the side surface of the structural body to fix the one or more wires.
US09281265B2	Packaging structure of a semiconductor device A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
US09281262B2	Semiconductor device including a structure for screening connectivity of a TSV A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.
US09281261B2	Intelligent chip placement within a three-dimensional chip stack An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a ratio of first enabled cores and first disabled cores. The IC stack device can also have a supplementary IC interfaced with the primary IC, and having a second set of cores with a second ratio of second enabled cores and second disabled cores, with the second ratio being less than the first ratio. The integrated circuit stack device can also include a cooling element located such that the primary integrated circuit is between the cooling element and the supplementary integrated circuit. The cooling element can be designed to facilitate heat dissipation of the first and second enabled cores of the primary integrated circuit and the supplementary integrated circuit.
US09281257B2	Semiconductor package including a connecting member The semiconductor package according to an exemplary embodiment in the present disclosure includes: at least one electronic device; a lead frame including a plurality of leads electrically connected to the electronic device; a lead connecting member coupled to at least one of the leads; and a molded portion sealing the electronic device and the lead connecting member.
US09281255B2	Underfill composition and semiconductor device and manufacturing method thereof To provide a solid preapplication underfill material that has excellent workability, has a high degree of freedom for solder bonding processes, and enables the formation of a solder bond with high reliability. (Resolution Means) The underfill composition of the present disclosure contains a hardened epoxy resin and has a viscosity of 1000 Pa·s or more at 30° C. The hardening epoxy resin includes a crystalline epoxy resin at not less than 50 wt % relative to an entire resin composition.
US09281252B1	Method comprising applying an external mechanical stress to a semiconductor structure and semiconductor processing tool A method includes providing a semiconductor structure. An external mechanical stress is applied to the semiconductor structure. One or more semiconductor manufacturing processes are performed while the external mechanical stress is applied to the semiconductor structure. The one or more semiconductor manufacturing processes provide one or more material layers having an intrinsic stress at the semiconductor structure. After performing the one or more semiconductor manufacturing processes, the external mechanical stress is removed from the semiconductor structure. The removal of the external mechanical stress at least partially relaxes the intrinsic stress of the one or more material layers.
US09281242B2	Through silicon via stacked structure and a method of manufacturing the same A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.
US09281240B2	Methods of manufacturing semiconductor devices In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.
US09281239B2	Biocompatible electrodes and methods of manufacturing biocompatible electrodes A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.
US09281238B2	Method for fabricating interlayer dielectric layer A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.
US09281235B2	Semiconductor packages and methods of forming the same A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
US09281230B2	Apparatus for manufacturing a hierarchical structure The present invention relates to an apparatus for massive manufacturing a hierarchical structure that can hierarchically form high performance micro units one a flexible substrate. For this purpose, an apparatus for manufacturing a hierarchical structure according to the present invention is provided to layer micro units provided on a dummy substrate that is made of a hard material on a target substrate that is made of a flexible material by releasing the micro units from the dummy substrate. The apparatus includes: a transfer stage flat-transferring the dummy substrate by supporting the same and a main roller rolling the target substrate by winding the same as the transfer stage proceeds and layering the micro unit of the dummy substrate on the target substrate.
US09281223B2	Coupling system In a transfer system for wafers, etc., a coupling chamber corresponding to a port is formed only when a transfer box comes in tight contact with an apparatus as a transfer target in the transfer box is transferred into the apparatus, so that the transfer target will be transferred into the apparatus together with the coupling chamber, thereby simplifying the structures of the transfer box and apparatus and also allowing the transfer target to be transferred into the apparatus without fail.
US09281220B2	Liquid processing apparatus, liquid processing method and storage medium Disclosed are a liquid processing device, and a liquid processing method. The liquid processing method includes a first process that includes supplying a first processing liquid to the substrate and discharging the first processing liquid within the processing space from a first discharge path, a second process that includes supplying a second processing liquid to the substrate and discharging the second processing liquid within the processing space from the second discharge path, and after stop supplying of the first processing liquid and prior to beginning of the second process, a nozzle switching operation switching from the first nozzle to the second nozzle and a discharge mechanism switching operation switching from the first discharge path to the second discharge path are performed. A longer one of a time to switch the nozzle and a time to switch the discharge mechanism is determined as a maximum preparation time and the switching operations begin at an earlier time than the completion time of the first process by the maximum preparation time or more.
US09281213B2	High precision capacitor dielectric A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.
US09281212B1	Dielectric tone inversion materials A process for patterning a hard mask material with line-space patterns below a 30 nm pitch and a 15 nm critical dimension by employing a spin-on titanium-silicon (TiSi) polymer or oligomer as a tone inversion material is provided. The spin-on TiSi material is spin-coated over a patterned OPL that includes a first pattern generated from a DSA based process. The spin-on TiSi material fill trenches within the patterned OPL to form a tone inverted pattern by removing the patterned OPL selective to the spin-on TiSi material. The inverted pattern is a complementary pattern to the first pattern, and is transferred into the underlying hard mask material by an anisotropic etch.
US09281210B2	Wet-process ceria compositions for polishing substrates, and methods related thereto Disclosed are a chemical-mechanical polishing composition and a method of polishing a substrate. The polishing composition comprises low average particle size (e.g., 30 nm or less) wet-process ceria abrasive particles, at least one alcohol amine, and water, wherein said polishing composition has a pH of about 6. The polishing composition can be used, e.g., to polish any suitable substrate, such as a polysilicon wafer used in the semiconductor industry.
US09281208B2	Methods of forming semiconductor devices using hard mask layers A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures.
US09281206B2	Semiconductor processing by magnetic field guided etching Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure.
US09281201B2	Method of manufacturing semiconductor device having metal gate A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.
US09281200B2	Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.
US09281198B2	Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.
US09281192B2	CMP-friendly coatings for planar recessing or removing of variable-height layers An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.
US09281189B2	Wafer and method of fabricating the same Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.
US09281188B2	Apparatus and method for fabricating wafer A method for fabricating a wafer according to the embodiment comprises the steps of depositing an epi layer in an epi deposition part; transferring the wafer to an annealing part connected to the epi deposition part; annealing the wafer in the annealing part; transferring the wafer to a cooling part connected to the annealing part; and cooling the wafer in the cooling part, wherein the depositing of the wafer, the annealing of the wafer and the cooling of the wafer are continuously performed. An apparatus for fabricating a wafer according to the embodiment comprises an epi deposition part; an annealing part connected to the epi deposition part; and a cooling part connected to the annealing part.
US09281187B2	Method for manufacturing nitride semiconductor device The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.
US09281186B2	Colored photovoltaic modules and methods of construction A colored photovoltaic module and method for its production, where the module includes: a photovoltaic cell; and an appearance modifying film, encapsulant or glazing; where the appearance modifying film, encapsulant or glazing includes: a light-control film; graphic material; a phosphor; a dichroic film; nano-particles; micro-dots; metal flakes; paint; an additive material for 3-D printing, Selective Laser Augmentation (SLA) or Selective Laser Sintering (SLS); or any combination thereof.
US09281183B2	Metalorganic chemical vapor deposition of oxide dielectrics on N-polar III-nitride semiconductors with high interface quality and tunable fixed interface charge A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
US09281181B2	Film forming method and recording medium for performing the method A method of manufacturing a semiconductor device includes forming a laminated film on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen and which does not contain a borazine ring skeleton, and forming a second film which contains the predetermined element and a borazine ring skeleton. The first film and the second film are laminated to form the laminated film.
US09281177B2	Methods and apparatus for cleaning semiconductor wafers An apparatus for cleaning a surface of wafer or substrate includes a plate being positioned with a gap to surface of the wafer or substrate, and the plate being rotated around an axis vertical to surface of wafer or substrate. The rotating plate surface facing surface of the wafer or substrate has grooves, regular patterns, and irregular patterns to enhance the cleaning efficiency. Another embodiment further includes an ultra sonic or mega sonic transducer vibrating the rotating plate during cleaning process.
US09281174B2	System and method for rapid evaporative ionization of liquid phase samples According to some embodiments, systems and methods for rapid evaporation of liquid phase samples are provided. The method includes directing liquid samples to a thermal evaporation ionizing device, thermally evaporating the liquid samples to create gaseous molecular ions, and directing the gaseous molecular ions to an ion analyzer to analyze and provide information regarding the chemical composition of the liquid samples.
US09281168B2	Reducing switching variation in magnetoresistive devices The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.
US09281164B2	Method and apparatus for inspection of scattered hot spot areas on a manufactured substrate One embodiment relates to a method of automated inspection of scattered hot spot areas on a manufactured substrate using an electron beam apparatus. A stage holding the substrate is moved along a swath path so as to move a field of view of the electron beam apparatus such that the moving field of view covers a target area on the substrate. Off-axis imaging of the hot spot areas within the moving field of view is performed. A number of hot spot areas within the moving field of view may be determined, and the speed of the stage movement may be adjusted based on the number of hot spot areas within the moving field of view. Another embodiment relates to an electron beam apparatus for inspecting scattered areas on a manufactured substrate. Other embodiments, aspects and features are also disclosed.
US09281161B2	Electron beam writing apparatus and electron beam writing method An electron beam writing apparatus includes: a first aperture plate that shapes an electron beam emitted from an electron gun assembly; a second aperture plate onto which an electron beam of an aperture plate image passing through the first aperture plate is projected; and a first shaping deflector and a second shaping deflector which are provided between the first aperture plate and the second aperture plate, respectively, deflect an electron beam, control an irradiation position of the aperture plate image on the second aperture plate, and determine a shot shape and a shot size. The first shaping deflector deflects an electron beam such that the aperture plate image is positioned at a determined position in accordance with a shot shape and a shot size. The second shaping deflector deflects an electron beam deflected by the first shaping deflector and controls formation of a desirable shot size.
US09281160B2	Insulation structure and insulation method An insulation structure provided among a plurality of electrodes for extraction of an ion beam from a plasma generating section is provided. The insulation structure includes an insulation member including a first part connected to a first electrode and a second part connected to a second electrode and configured to support the first electrode to the second electrode, a first cover surrounding at least a part of the first part to protect the first part from contamination particles, and a second cover surrounding at least a part of the second part to protect the second part from contamination particles. At least one of the first part and the second part is made of a machinable ceramic or a porous ceramic.
US09281158B2	X-ray emitting target and X-ray emitting device An X-ray emitting target including a diamond substrate, a first layer disposed on the diamond substrate and including a first metal, and a second layer disposed on the first layer and including a second metal whose atomic number is 42 or more and which has a thermal conductivity higher than that of the first metal. Carbide of the first metal is present at a boundary between the diamond substrate and the first layer. The target is prevented from overheating, so that output variation due to rising temperature is suppressed. Thus it is possible to emit stable and high output X-rays.
US09281154B2	Microwave introducing mechanism, microwave plasma source and microwave plasma processing apparatus The microwave introducing mechanism includes an antenna unit having a planar antenna radiating a microwave into a chamber; a tuner for performing impedance matching; and a heat dissipation device for dissipating a heat from the antenna unit. The tuner has a tuner main body including a tubular outer conductor and a tubular inner conductor to serve as a part of a microwave transmission line; slugs provided between the outer conductor and the inner conductor to be movable along a longitudinal direction of the inner conductor; and a driving device for moving the slugs. The heat dissipation device has a heat pipe configured to transfer the heat of the antenna unit from its heat input end to its heat dissipation end.
US09281152B2	Fuse with carbon fiber fusible element A fuse includes a body, a first conductive terminal coupled with a first end of the body, and a second conductive terminal coupled with a second end of the body. The body, the first conductive terminal, and the second conductive terminal define an exterior of the fuse. The fuse also includes an interruption assembly including a fusible element. The fusible element includes carbon fiber, is disposed on a conductive path between the first conductive terminal and the second conductive terminal, and is configured to break when a current through the fusible element exceeds a predetermined current.
US09281151B2	Lever arm for a shunt trip device A shunt trip device for a circuit breaker having a trip bar for tripping the circuit breaker. The device includes a housing having a slot and a bottom wall having a pivot pocket. The device also includes a lever arm having a lever projection portion and a pivot portion. The pivot portion is located in the pivot pocket to enable rotation of the lever arm in the slot about a lever rotation axis between first and second positions. When the lever arm is in the second position, the lever projection portion moves the trip bar and trips the circuit breaker. The device further includes an actuation device that moves the lever arm to the second position. The pivot portion and pivot pocket form a configuration that increases a perpendicular distance between a force generated by the actuation device and the lever rotation axis.
US09281150B2	Circuit breaker trip blocking apparatus, systems, and methods of operation Embodiments disclose a trip blocking apparatus of a circuit breaker exhibiting no trip at OFF functionality. The trip blocking apparatus effectively blocks tripping of a trip bar when the circuit breaker is in the OFF configuration. The trip blocking apparatus has a trip blocking arm and a blocking lever. A first projection of the blocking lever is configured to contact a handle arm, and a second projection is configured to interfere with the trip blocking arm to block tripping of the trip bar responsive to handle arm motion. Actuator resetting and blocking apparatus and trip blocking assemblies and methods of operating the trip blocking assembly are provided, as are other aspects.
US09281145B2	Vacuum interrupter A vacuum interrupter, including: an insulating housing; a movable end cap; a stationary end cap; a pair of movable and stationary contacts; and a pair of shields. The pair of shields is fixed on the movable end cap and the stationary end cap, respectively. The insulating housing, the movable end cap, and the stationary end cap cooperate to form a closed space. The closed space includes a movable fracture and a stationary fracture. The movable fracture is formed by the pair of movable and stationary contacts for carrying rated current and disconnecting capacitive load whereby achieving breaking performance of the vacuum interrupter. The stationary fracture is formed by the pair of shields. When the pair of stationary and movable contacts reaches a full open position, the stationary contact and the movable contact enter the pair of shields, respectively.
US09281144B2	Circuit breaker contact assembly and cam lever A contact apparatus of a circuit breaker is disclosed. The contact apparatus has an outer carrier, an inner carrier, one or more contact fingers pivotally mounted to the inner carrier, a cam lever pivotally mounted to the outer carrier, and a cam and cam profile formed on respective ones of the cam lever and inner carrier. Circuit breakers and electrical contact assemblies having the contact apparatus, and methods of operating the contact apparatus and electrical contact assemblies are disclosed, as are other aspects.
US09281143B2	Limit switch The invention relates to a limit switch comprising: a body (1) produced along a main axis (X) and containing a switching device, a head (2) that is removable and orientable with respect to the body (1) so that it can adopt several distinct angular positions about the main axis (X), said head (2) comprising actuating means arranged to act on the switching device, fixing means for fixing the limit switch to a support (S), the fixing means being arranged on the head (2) of the limit switch, the head (2) having at least two separate bearing planes, said fixing means being arranged to fix the head so that it bears against the support via one or other of its two bearing planes.
US09281140B2	Lighted switch The invention is directed to a switch comprising an LED for indicating when a connected electrical device is activated or not. In certain examples, the electrical device is a water pump. In certain examples, the invention is drawn to a circuit comprising a switch, a logic circuit, an electrical device, and an LED subcircuit, whereby the electrical device is turned on by closing the switch, and whereby the LED functions as an indicator light remaining on while the electrical device remains on, and turning off when the electrical device is turned off.
US09281139B2	Cover assembly for an electrical switch A cover assembly for a first electrical switch and a second electrical switch. The cover assembly includes an alignment plate configured to be removably coupled to the first electrical switch. The alignment plate includes a first alignment feature that receives a portion of the first electrical switch to align the alignment plate with the first electrical switch, and a second alignment feature that receives a portion of the second electrical switch to align the alignment plate with the second electrical switch and to align the second electrical switch with the first electrical switch. The assembly further includes a faceplate that is removably coupled to the alignment plate.
US09281132B2	Method for sealing a liquid within a glass package and the resulting glass package A method for sealing a liquid within a glass package and the resulting sealed glass package are described herein where the sealed glass package can be, for example, a dye solar cell, an electro-wetting display or an organic emitting light diode (OLED) display.
US09281131B2	Electrolyte-comprising polymer nanofibers fabricated by electrospinning method and high performance dye-sensitized solar cells device using same A polymer electrolyte including a polymer fiber having a nanoscale diameter, wherein the polymer fiber is fabricated by an electrospinning method and a solar cell device exhibiting high energy conversion efficiency using the same. The solid-state electrolyte comprising such nanosized polymer fiber does not need a sealing agent and further simplifies the entire process compared to a conventional dye-sensitized solar cell using liquid electrolytes. Specifically, the energy conversion efficiency of the present dye-sensitized solar cell is significantly superior to that of a dye-sensitized solar cell using a polymer film electrolyte fabricated by a spin coating method. Further, the present dye-sensitized solar cell device can be obtained by using a scattering layer and compensating the surface effect.
US09281130B2	Electrolytic solution for aluminum electrolyte capacitor, and aluminum electrolyte capacitor using the same The invention provides an electrolytic solution for an aluminum electrolyte capacitor with which there is little deterioration of the electrolytic solution properties, the sparking voltage is high, and shorting does not occur, even when the voltage used is high. The invention also provides an electrolyte (C) formed from anions of at least one phosphoric acid alkyl ester (A) and amidinium cations (B), at least one boric acid compound (F) selected from the group consisting of boric acid and boric acid esters, a C2-15 carboxylic acid (D) formed from carbon atoms, oxygen atoms, and hydrogen atoms only, and an organic solvent (E).
US09281129B2	Silicon oxide particles, making method, lithium ion secondary battery, and electrochemical capacitor Silicon oxide particles each comprising an inner portion having an iron content of 10-1,000 ppm and an outer portion having an iron content of up to 30 ppm are suitable as negative electrode active material in nonaqueous electrolyte secondary batteries. Using a negative electrode comprising the silicon oxide particles as active material, a lithium ion secondary battery or electrochemical capacitor having a high capacity and improved cycle performance can be constructed.
US09281128B2	Switchable capacitor A switchable capacitor having: a dielectric; a pair of electrodes, a first one of the electrodes having the dielectric thereon and a second, flexible one of the electrodes being suspended over the dielectric when the switchable capacitor is in an de-activated state; and top plate disposed between the dielectric and the second, flexible electrode and connected to a reference potential. When the switchable capacitor is electrostatically driven to an activated state, the second one of the electrodes contacts the top plate and when the switchable capacitor is returned to the de-activated state, charge on the top plate is discharged to the reference potential.
US09281127B2	Electronic component and method for manufacturing the same In a method for manufacturing an electronic component, when conductive paste used to form outer electrodes is applied to a component body, a side surface of the component body is subjected to an affinity-reducing process to reduce an affinity for solvent, and then an end surface of the component body is dipped into the conductive paste. Accordingly, spreading of the conductive paste stops at ridge portions of the component body, and the conductive paste is applied to a large thickness. After that, the end surface of the component body is dipped deeper into the conductive paste. Also in this step, the affinity-reducing process prevents upward spreading of the conductive paste along the side surface.
US09281125B2	Dielectric ceramic, multi-layer ceramic capacitor and method of manufacturing the same A dielectric ceramic is formed with sintered grains constituting the dielectric have an average grain size of 0.2 to 1.0 μm and an oxygen defect concentration of 0.2 to 0.5%. An acceptor element is added to the dielectric ceramic by no more than 0.5 mol per 100 mol of the primary component of BaTiO3. The oxygen defect concentration is temporarily increased by reduction and sintering, after which the oxygen defect concentration is reduced through the subsequent re-oxidization process. Crystal strain generated in the re-oxidization process increases the dielectric constant.
US09281123B2	Metalized film capacitor A metalized film capacitor includes metalized films, each of which is formed of an insulating film made of dielectric, and a vapor deposited metal electrode formed on an upper surface of the insulating film. An end of the vapor deposited metal electrode extends together with an end of the insulating film, and both the ends are connected to an electrode terminal. The vapor deposited metal electrode of the metalized film includes a center region and a low resistance section that is made of Al—Zn—Mg alloy. The low resistance section is disposed at an end of the electrode and is thicker than the center region. This metalized film capacitor has high humidity resistance.
US09281122B2	Electrode structure of a laminated metallization film capacitor An electrode structure of a laminated metallization film capacitor includes at least two laminated metallization films. Each metallization film is further disposed with a plurality of metal-uncoated curved gap strips with a certain width on the plane of section of the laminated metallization film capacitor core to separate two adjacent metal coating units partially or totally. A center of the curved gas strip is concaved with a notch. Both sides of the notch form like misaligned shoulders. A projection forms opposite to the open of the notch; in two adjacent curve gap strips. An extreme point of the projection of one curve gap strip is disposed inside the notch of the other one in any event.
US09281117B2	Magnetic core structure and electric reactor The present application discloses a magnetic core structure and an electric reactor. The magnetic core structure includes an upper cover plate and a lower cover plate which are arranged oppositely and at least one wrapping post having two ends connected to the upper cover plate and lower cover plate, respectively. A cross-sectional area of the upper cover plate and/or of the lower cover plate is larger than that of the wrapping post. The upper cover plate, the lower cover plate and the wrapping post are made of a magnetic powder core material, an amorphous material, a nanocrystalline material or a silicon steel material. Since the cross-sectional area of the upper cover plate and/or of the lower cover plate is larger than that of the wrapping post, this may bring excellent DC-Bias characteristic to an electric reactor or inductor, and make the electric reactor or inductor have lower magnetic core loss.
US09281114B2	Stator for electronic fuel injector A stator assembly for a fuel valve comprising a magnetic E-core of stacked E-shaped laminations, a plastic bobbin proportioned to surround a central leg of the core, a magnetic wire coil on the bobbin, a non-magnetic metal plate having an O-shaped profile adjacent an end of the bobbin and distal ends of central and outer legs of the E-core, the core, bobbin, coil and plate encapsulated in a block, the block having a pair of vent channels overlying portions of the plate disposed between the outer core legs and the central core leg, the plate being proportioned to pre-stress the outer core legs outwardly prior to encapsulation whereby cyclic strain on the block due to hydraulic forces imposed by high pressure fuel pulses tending to spread the outer core legs is reduced and resistance of the block to cracking due to said fuel pressure pulses is increased.
US09281107B2	Rare-earth permanent magnet and method for manufacturing rare-earth permanent magnet There are provided a rare-earth permanent magnet and a manufacturing method thereof capable of preventing deterioration of magnet properties. In the method, magnet material is milled into magnet powder. Next, a mixture is prepared by mixing the magnet powder and a binder made of long-chain hydrocarbon and/or of a polymer or a copolymer consisting of monomers having no oxygen atoms. Next, the mixture is formed into a sheet-like shape so as to obtain a green sheet. After that, the green sheet is held for a predetermined length of time at binder decomposition temperature in a non-oxidizing atmosphere so as to remove the binder by causing depolymerization reaction or the like to the binder, which turns into monomer. The green sheet from which the binder has been removed is sintered by raising temperature up to sintering temperature. Thereby a permanent magnet 1 is obtained.
US09281105B2	Permanent magnet and method of producing permanent magnet A permanent magnet has a grain structure that includes a main phase and a grain boundary phase that is primarily composed of a first metal. A second metal that enhances the coercivity of the permanent magnet and a third metal that has a lower standard free energy of oxide formation than the first metal and the second metal are diffused in the permanent magnet, and the third metal is present in the form of an oxide in the grain boundary phase.
US09281104B2	Conductive thin film comprising silicon-carbon composite as printable thermistors A method of fabricating a temperature sensing device based on printed silicon-carbon nanocomposite film is disclosed. This method includes high-crystal-quality Si nanoparticles (NPs) homogeneously mixed with carbon NPs and Si—C nanocomposites printed as negative temperature coefficient (NTC) thermistor. These mixtures of Si and C NPs are formulated into screen printing paste with acrylic polymer binder and ethylene glycol (EG) as solvent. This composite paste can be successfully printed on flexible substrates, such as paper or plastics, eventually making printable NTC thermistors quite low-cost. Si and carbon powders have size range of 10 nanometers to 100 micrometers and are mixed together with weight ratios of 100:1 to 10:1. More carbon content, higher conductivity of printed Si—C nanocomposite films keeping similar sensitivity of high-quality Si NPs. With homogeneous distribution of carbon particles in printed films, electrons can tunnel from silicon to carbon and high-conductivity carbon microclusters enhanced hopping process of electrons in printed nanocomposite film. The measured sensitivity 7.23%/° C. of printed Si—C nanocomposite NTC thermistor is approaching the reported value of 8.0-9.5%/° C. for intrinsic silicon bulk material near room temperature, with the quite low resistance of 10 kΩ-100 kΩ. This NTC thermistor is quite suitable for low-cost readout circuits and the integrated systems target to be disposable temperature sensors.
US09281103B2	Polymer locally comprising conductive areas A method for producing a conductive area in a polymer material comprises: providing a polymer layer comprising conductive particles with a density such that the polymer layer is insulating, heating the polymer material to a temperature higher than or equal to the glass transition temperature of the polymer material, compressing a portion of the polymer layer using a stamp, in order to obtain a density of conductive particles such that the portion becomes conductive, and removing the stamp from the polymer layer.
US09281097B2	Anisotropic conductive film, composition for the same, and apparatus including the same An anisotropic conductive film includes a binder part, a curing part, an initiator, and conductive particles, wherein the binder part includes at least one of a nitrile butadiene rubber (NBR) resin and a urethane resin, the anisotropic conductive film has a halogen ion content of more than 0 ppm to about 100 ppm.
US09281095B2	Alumina composite, method for manufacturing alumina composite, and polymer composition containing alumina composite For the purpose of producing an alumina composite in which the integrity between alumina and an inorganic material is further improved, a dispersion liquid preparation step, a solidification step and a burning step are performed, wherein the dispersion liquid preparation step comprises preparing a dispersion liquid in which an inorganic material such as a carbon material is homogeneously dispersed in an alumina raw material solution having an organic additive dissolved therein, the solidification step comprises drying the dispersion liquid to produce a solid raw material, and burning step comprises burning the solid raw material in a non-acidic atmosphere while contacting hydrogen chloride with the solid raw material. In this manner, an alumina composite can be produced, in which at least a portion of an inorganic material such as a carbon material is embedded in the inside of each of α-alumina single crystal particles the constitute alumina particles.
US09281083B2	Traveling wave nuclear fission reactor, fuel assembly, and method of controlling burnup therein A traveling wave nuclear fission reactor, fuel assembly, and a method of controlling burnup therein. In a traveling wave nuclear fission reactor, a nuclear fission reactor fuel assembly comprises a plurality of nuclear fission fuel rods that are exposed to a deflagration wave burnfront that, in turn, travels through the fuel rods. The excess reactivity is controlled by a plurality of movable neutron absorber structures that are selectively inserted into and withdrawn from the fuel assembly in order to control the excess reactivity and thus the location, speed and shape of the burnfront. Controlling location, speed and shape of the burnfront manages neutron fluence seen by fuel assembly structural materials in order to reduce risk of temperature and irradiation damage to the structural materials.
US09281079B2	Dynamic hard error detection An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.
US09281077B2	Shift register and display device A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element.
US09281072B2	Flash memory device and flash memory system including the same A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
US09281069B2	Method of programming a nonvolatile memory device In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.
US09281065B2	Low-power nonvolatile memory cells with select gates Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.
US09281064B2	Fast programming memory device In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
US09281059B2	Thyristor memory cell integrated circuit A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.
US09281058B2	Semiconductor memory device and a reading method thereof A semiconductor memory device may include a common source line controller configured to provide a channel current to a cell string via a common source line during a read operation and a page buffer configured to detect data stored in a selected memory cell by detecting a current of the bit line when the channel current is provided. The page buffer may selectively bias the bit line to maintain a voltage of the bit line to be the same as or higher than a reference voltage.
US09281056B2	Static random access memory and method of using the same A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.
US09281055B2	Memory sense amplifier and column pre-charger A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
US09281054B2	Technique for optimizing static random-access memory passive power consumption A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.
US09281053B2	Memory system and an apparatus A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized.
US09281051B2	Semiconductor package A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address.
US09281049B1	Read clock forwarding for multiple source-synchronous memory interfaces Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.
US09281044B2	Apparatuses having a ferroelectric field-effect transistor memory array and related method An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.
US09281043B1	Resistive memory write circuitry with bit line drive strength based on storage cell line resistance An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
US09281041B1	Delay-based read system for a magnetoresistive random access memory (MRAM) bit In one example, the disclosure is directed to a memory system comprising a control module. The memory system further includes a first circuit and a second circuit that each receives a control signal from the control module. Each circuit includes a resistor (MRAM element or a fixed resistor) and a capacitor situated between the resistor and a reference voltage. The first circuit is configured to output a data signal after the first capacitor is charged. The second circuit is configured to output a reference signal after the second capacitor is charged. The memory system further includes an arbiter configured to receive the data signal from the first circuit and the reference signal from the second circuit, determine whether the data signal arrived before the reference signal, and determine whether the MRAM is in a high or low state based on whether the data signal or the reference signal arrived first.
US09281040B2	Spin transfer torque magnetic memory device A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.
US09281039B2	System and method to provide a reference cell using magnetic tunnel junction cells An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.
US09281036B2	Memory device having an adaptable number of open rows A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.
US09281032B2	Memory timing circuit A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.
US09281030B2	Controlling timing of negative charge injection to generate reliable negative bitline voltage Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.
US09281026B2	Parallel processing computer systems with reduced power consumption and methods for providing the same A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.
US09281024B2	Write/read priority blocking scheme using parallel static address decode path A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.
US09281023B2	Single ended sensing circuits for signal lines Disclosed are single-ended sensing circuits. Each of the sensing circuits comprises at least a sense amplifier connected to a sense node, an isolation field effect transistor (FET) connected in series between the sense node and a signal line node, and a pre-charged device connected to the sense node. In order to achieve a relatively fast pre-charge of both the sense and signal line nodes and to also achieve a relatively fast and accurate sense of the sense node, the single-ended circuits further incorporate a variable reference voltage generator connected to the gate of the isolation FET for selectively applying different reference voltages to the gate during pre-charging and sensing operations, respectively, and/or a second pre-charge device connected to the signal line node for facilitating pre-charging of that signal line node.
US09281022B2	Systems and methods for reducing standby power in floating body memory devices Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
US09281016B2	3D stacked semiconductor memory devices with sense amplifier electrically connected to a selecting circuit According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.
US09281015B1	Storage media conversion device and server using the same A storage media conversion device includes a mounting bracket (100) and a holder (200). The mounting bracket (100) includes a first baseplate (110) and two corresponding side plates (120) extending perpendicularly from the first baseplate (110). The first baseplate (110) and the two side plates (120) enclose a first loading space (130). Any of the side plates (120) includes a first resilient positioning portion (150) for positioning a first size hard disk (A). A holder (200) includes a pivot shaft (210) pivotally connected to one side of the first baseplate (110), a handle (220) rotatable with respect to the pivot shaft (210), and a contact portion (230) disposed close to the pivot shaft (210). The length from the handle (220) to the pivot shaft (210) is greater than the length from the contact portion (230) to the pivot shaft (210).
US09281014B2	Image processing apparatus and computer program An image processing apparatus according to an embodiment includes: an interface configured to obtain management information that has been generated along with movie data generated; and a controller configured to generate, as a representative picture representing the movie data, image information including characters or an icon to be determined by reference to the management information. When selected by a user, the representative picture is presented on a display device in order to start playing back movie data represented by the representative picture.
US09281013B2	Systems and methods for transmission of media content A method provide a selection option to the at least one portable device, the selection option relating to selection of the first audio content and retrieving a selection from the at least one portable device based on the selection option. The method further retrieves a selection of the second audio content and synchronizing the first audio content, the second audio content, and the video content by embedding a synchronizing signal in the first audio content, the second audio content, and the video content. The method further outputs the second audio content and the video content to an output device according to the synchronizing signal. Responsive to the selection of the first audio content, the first audio content with the embedded synchronizing signal is transmitted to the least one portable device, wherein the at least one portable device outputs the first audio content according to the synchronizing signal.
US09281010B2	Timeline-based content control method and apparatus using dynamic distortion of timeline bar, and method and apparatus for controlling video and audio clips using the same A method and apparatus for controlling content based on a timeline in a timeline-based content control apparatus with a touch screen. The method includes generating and displaying a linear timeline bar on the touch screen regardless of the size of content; detecting contact on the timeline bar; nonlinearly distorting a predetermined section of the timeline bar being displayed around the touch-detected position on the timeline bar; and performing a fine search and shifting the distorted section depending on a direction of the user's touch.
US09281009B1	Data storage device employing variable size interleave written track segments A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. Data is encoded into a first number of codewords, and the first number of codewords are interleave written to a first segment of a first data track. Data is encoded into a second number of codewords, and the second number of codewords are interleave written to a second segment of the first data track. The first number of codewords is different than the second number of codewords, and a size of the first segment is different than a size of the second segment.
US09281007B2	Read channel sampling utilizing two quantization modules for increased sample bit width A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.
US09281003B2	Devices including near field transducer and adhesion layers A device including a near field transducer (NFT); a write pole; at least one dielectric material positioned between the NFT and the write pole; and an adhesion layer positioned between the NFT and the at least one dielectric material.
US09280998B1	Acidic post-sputter wash for magnetic recording media A recording medium having an outer surface relatively free of magnetic particulates is achievable by, after forming a magnetic recording layer with which magnetic contamination is associated, removing magnetic contamination from the medium by immersing the medium in an acidic water solution. For example, a post-sputter wash process utilizing a mildly acidic water solution having a pH less than around 5 may remove cobalt particle contaminants from the surface of the medium. The water solution may be acidized by introducing into deionized water a pre-diluted strong acid such as nitric acid or a weak acid such as carbonic acid.
US09280995B2	Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value.
US09280994B1	Thermally assisted magnetic recording head with optical spot-size converter attached two dimensional thin waveguide One embodiment generally relates to a magnetic recording head. The magnetic recording head has a body having an upper surface and a media bearing surface, a spot size converter disposed in the body and extending from the upper surface to the media bearing surface. The spot size converter has a core, comprising a first portion having a rectangular wall extending below the upper surface; and a second portion having a trapezoidal wall extending below the first portion. The magnetic recording head additionally has a first cladding adjacent to the spot size converter in an in-surface direction of the spot size converter, wherein the first cladding has a first refractive index lower than a refractive index of the spot size converter.
US09280990B1	Method for fabricating a magnetic writer using multiple etches A method and system provide a magnetic transducer having an air-bearing surface (ABS) location. The method includes forming a trench in the intermediate layer using a plurality of etches. A first etch substantially provides a first portion of the trench having a first sidewall angle. The second etch substantially provides a second portion of the trench having a second sidewall angle. The second sidewall angle is greater than the first sidewall angle. The second portion of the trench includes the ABS location. The method also includes providing a main pole in the trench. The main pole has a plurality of sidewalls. The sidewalls having the first sidewall angle in the first portion of the trench and the second sidewall angle in the second portion of the trench.
US09280986B2	Acoustic signal processing device and acoustic signal processing method Provided is an acoustic signal processing device for producing an output sound meeting listener's preferences by adjusting attack sound, reverberation, and noise component. The device includes: an FFT section for transforming an input audio signal from a time-domain to a frequency-domain to calculate a frequency spectrum signal and for generating a first amplitude spectrum signal and a phase spectrum signal; an attack component controller (10) for controlling an attack component of the first amplitude spectrum signal to generate a second amplitude spectrum signal; a reverberation component controller (20) for controlling a reverberation component of the first amplitude spectrum signal to generate a third amplitude spectrum signal; a first adding section (40) for synthesizing the first amplitude spectrum signal, the second amplitude spectrum signal, and the third amplitude spectrum signal to generate a fourth amplitude spectrum signal; and an IFFT section for generating an audio signal transformed from a frequency domain to a time domain based on the fourth amplitude spectrum signal and the phase spectrum signal generated by the FFT section.
US09280985B2	Noise suppression apparatus and control method thereof A noise suppression apparatus selectively uses an adaptive beamformer and fixed beamformer for each frequency. A direction of a null of the fixed beamformer is determined from a direction of a null automatically formed by the adaptive beamformer. Filter coefficients of the adaptive beamformer based on an output power minimization rule are calculated by a minimum norm method using a norm of the filter coefficients as a constraint. The above selection is made based on, for example, a depth of a null automatically formed by the adaptive beamformer in the selection.
US09280984B2	Noise cancellation method An embodiment of the invention provides a noise cancellation method for an electronic device. The method comprises: receiving an audio signal; applying a Fast Fourier Transform operation on the audio signal to generate a sound spectrum; acquiring a first spectrum corresponding to a noise and a second spectrum corresponding to a human voice signal from the sound spectrum; estimating a center frequency according to the first spectrum and the second spectrum; and applying a high pass filtering operation to the sound spectrum according to the center frequency.
US09280983B2	Acoustic echo cancellation (AEC) for a close-coupled speaker and microphone system Embodiments are directed towards providing acoustic echo cancellation in a closely-coupled microphone/speaker system. A speaker may produce an audible signal from a reference signal, which may be captured with a microphone. Full band cancellation (FBC) may modify the captured signal to suppress an echo of the reference signal caused by a direct acoustic path between the microphone and speaker. FBC may include a fixed filter and an adaptive filter. The fixed filter may modify the captured signal based on the reference signal. The adaptive filter may automatically adapt based on the captured signal and the reference signal. If a comparison of a performance of the adaptive filter and the fixed filter is above a threshold, then the fixed filter may be updated based on the adaptive filter. Subband acoustic echo cancellation may generate an output signal that suppresses residual echoes of the reference signal based on the modified signal.
US09280981B2	Method and apparatus for voice control of a mobile device A method and apparatus for voice control of a mobile device are provided. The method establishes a connection between the mobile device and a voice-control module. Responsive to establishing the connection, the mobile device enters into an intermediate mode; and the voice-control module monitors for verbal input comprising a verbal command from among a set of predetermined verbal commands. The voice-control module sends instructions to the mobile device related to the verbal command received; and the mobile device acts on the received instructions. An apparatus/voice control module (VCM) for voice control of a mobile device, wherein the VCM includes a connection module configured for establishing a connection between the VCM and the mobile device; a monitoring module configured for monitoring for a verbal command from among a set of predetermined verbal commands; and a communications module configured for sending instructions to the mobile device related to the verbal command received.
US09280980B2	Efficient encoding/decoding of audio signals A method for encoding of an audio signal comprises performing (214) of a transform of the audio signal. An energy offset is selected (216) for each of the first subbands. An energy measure of a first reference band within a low band of an encoding of a synthesis signal is obtained (212). The first high band is encoded (220) by providing quantization indices representing a respective scalar quantization of a spectrum envelope in the first subbands of the first high band relative to the energy measure of the first reference band by use of the selected energy offset. An encoder apparatus comprises means for carrying out the steps of the method. Corresponding decoder methods and apparatuses are also described.
US09280978B2	Packet loss concealment for bandwidth extension of speech signals Disclosed is a speech receiving apparatus. A low-band PLC module and a synthesis filter reconstructs a low-band speech signal of a lost frame from a previous good frame. A high-band PLC module reconstructs a high-band speech signal of the lost frame from the previous good frame. A transforming part transforms the low-band speech signal into a frequency range. A bandwidth extending part generates at least an extended MDCT coefficient as information for the high-band speech signal from the low-band speech signal transformed by the transforming part. A smoothing part smoothes the extended MDCT coefficient. An inverse transforming part inversely transforms the extended MDCT coefficient smoothed by the smoothing part to a time domain. A synthesizing part synthesizes the low-band speech signal, and the high-band speech signal which is inverse-transformed by the inverse transforming part and reconstructed, to output a wideband speech signal.
US09280976B2	Audio signal encoder An apparatus comprising: a coding rate determiner configured to determine a first coding bitrate for at least one first frame audio signal multi-channel parameter and a second coding bitrate for at least one second frame audio signal multi-channel parameter, wherein the combined first and second coding bitrate is less than a bitrate limit; a channel analyser configured to determine for a first frame the at least one first frame audio signal multi-channel parameter and configured to determine for a second frame the at least one second frame audio signal multi-channel parameter; a multi-channel parameter determiner configured to generate an encoded first frame audio signal multi-channel parameter within the first coding bitrate from the at least one first frame audio signal multi-channel parameter and configured to generate an encoded at least one second frame audio signal parameter within the second coding bitrate from the at least one second frame audio signal multi-channel parameter; and a multiplexer configured to combine the encoded at least one first frame audio signal multi-channel parameter and the encoded at least one second frame audio signal multi-channel parameter.
US09280972B2	Speech to text conversion Embodiments that relate to converting audio inputs from an environment into text are disclosed. For example, in one disclosed embodiment a speech conversion program receives audio inputs from a microphone array of a head-mounted display device. Image data is captured from the environment, and one or more possible faces are detected from image data. Eye-tracking data is used to determine a target face on which a user is focused. A beamforming technique is applied to at least a portion of the audio inputs to identify target audio inputs that are associated with the target face. The target audio inputs are converted into text that is displayed via a transparent display of the head-mounted display device.
US09280971B2	Mobile wireless communications device with speech to text conversion and related methods A mobile wireless communications device may include a housing and a wireless transceiver carried by the housing. The mobile wireless communications device may also include audio transducer carried by the housing, and a controller cooperating with the wireless transceiver to perform at least one wireless communications function. The controller may also cooperate with the at least one audio transducer to convert speech input through the audio transducer to converted text, determine a proposed modification for the converted text, and output from the audio output transducer the proposed modification for the converted text.
US09280970B1	Lattice semantic parsing A language processing system uses a lattice parser that semantically parses a command input represented by a lattice. The parser receives a hypotheses space of outputs as encoded in a lattice. Annotations of the input are projected back into the lattice and then lattice parsing is performed to rectify with the annotations. Parsing rules are applied to path fragments in the lattice. The rules that successfully parse from the start node to the end node of the lattice are used to determine whether the command input sentence invokes a specific action, and if so, what arguments are to be passed to the invocation of the action.
US09280968B2	System and method of using neural transforms of robust audio features for speech processing A system and method for processing speech includes receiving a first information stream associated with speech, the first information stream comprising micro-modulation features and receiving a second information stream associated with the speech, the second information stream comprising features. The method includes combining, via a non-linear multilayer perceptron, the first information stream and the second information stream to yield a third information stream. The system performs automatic speech recognition on the third information stream. The third information stream can also be used for training HMMs.
US09280967B2	Apparatus and method for estimating utterance style of each sentence in documents, and non-transitory computer readable medium thereof According to one embodiment, an apparatus for supporting reading of a document includes a model storage unit, a document acquisition unit, a feature information extraction, and an utterance style estimation unit. The model storage unit is configured to store a model which has trained a correspondence relationship between first feature information and an utterance style. The first feature information is extracted from a plurality of sentences in a training document. The document acquisition unit is configured to acquire a document to be read. The feature information extraction unit is configured to extract second feature information from each sentence in the document to be read. The utterance style estimation unit is configured to compare the second feature information of a plurality of sentences in the document to be read with the model, and to estimate an utterance style of the each sentence of the document to be read.
US09280964B2	Device and method for processing signals associated with sound A method and device may color or modify the tone or sound quality of audio input signals. A processor such as a DSP, may apply two or more filters to the audio input signal, each filter comprising a set of filter coefficients. The processor may combine finite impulse response (FIR) filters of the two or more filters into a power-saving filter. A speaker or sound emitter may emitting an output audio signal from the filtered audio input signal. The output audio signal has a different tone quality than that of the input audio signal.
US09280963B1	Pad generating rhythmic sound waves A pad for generating rhythmic sound waves according to an embodiment of the present disclosure comprises: at least two first patterns configured to generate a first sound wave in response to friction; and at least two second patterns configured to generate a second sound wave in response to the friction, wherein each of the first patterns is spaced and positioned in a constant distance, the at least two second patterns are positioned between the spaced first patterns, and for each of specific directions between the spaced first patterns, the first patterns and the second patterns are spaced and positioned in a different distance.
US09280962B1	Sound preview device and program Provided is a sound preview device including, in an electronic musical instrument which includes a keyboard 2 and an operation button 1 to perform tone selection or a sound setting and in which tone selection or a sound setting corresponding to a key is performed in advance by pressing the operation button 1 while pressing one of the keys in the keyboard 2, a changed state recognizing unit 3 that recognizes from a pressed key a changed state of tone selection or a sound setting determined corresponding to the key in advance, a phrase storing unit 4 in which phrases of sounds by which an influence of the changed state is easily known are stored in plural numbers according to the changed state, and a sound emitting unit 5 that emits a phrase corresponding to the changed state.
US09280961B2	Audio signal analysis for downbeats Apparatus for audio processing comprises: a beat tracking module for identifying beat time instants in an audio signal and a downbeat identifier for identifying downbeats occurring at beat time instants, each downbeat corresponding to the start of a musical bar or measure. A pattern identifier identifies two or more adjacent bars or measures containing musical characteristics which repeat within the audio signal, the pattern identifier being configured to: generate for each downbeat a plurality of scores using respective analysis methods for indicating different characteristics within the audio signal at the downbeat; combine the scores for each downbeat; and identify based on the combined scores non-adjacent downbeats that correspond to the start of a musical pattern.
US09280959B2	Practice pad for percussion instrument The present invention is directed to an apparatus providing a removable playing surface to a percussion instrument. The apparatus includes a mount assembly for fixing the apparatus to the percussion instrument and a paddle providing a playing surface. The paddle can movable between a playing position over the head of the percussion instrument and in a non-playing position away from the head of the percussion instrument.
US09280958B2	Adaptor for drum An adaptor for coupling to a drum having a drum head, shell, and rim, the rim having an outer diameter and configured to interface with a ring coupled to the drum head to hold the drum head in place on the shell, includes a monolithic body having a clip portion and an interface, the clip portion configured to extend around an outer section of the rim between a top surface of the drum head and a bottom portion of the rim, the clip portion having a clip end and the ring having an outer diameter, wherein the clip end is configured to extend to a position that is inward of the outer diameter of the ring when the clip portion is coupled to the drum; and wherein a substantial portion of the interface is configured to extend radially from the rim when the clip portion is coupled to the drum.
US09280955B2	Automatic waveform linking in an electrophoretic display controller In a linked waveform update mode, an impulse-driven, particle-based electrophoretic display may be updated using a first waveform and then automatically up-dated using a second drive scheme when the update using the first waveform finishes. The display may be automatically up-dated using a third drive scheme when the update using the second drive scheme finishes. The automatic updating using a subsequent drive scheme may be interrupted if the desired display states for the region changes after performing the first update. Waveforms may be selected using: (a) the desired display state of a pixel if the desired display state is a valid display state for the specified drive scheme, or (b) a mapped display state of the pixel if the desired display state is an invalid display state for the drive scheme.
US09280952B2	Selective display of OCR'ed text and corresponding images from publications on a client device Text is extracted from a source image of a publication using an Optical Character Recognition (OCR) process. A document is generated containing text segments of the extracted text. The document includes a control module that responds to user interactions with the displayed document. Responsive to a user selection of a displayed text segment, a corresponding image segment from the source image containing the text is retrieved and rendered in place of the selected text segment. The user can select again to toggle the display back to the text segment. Each text segment can be tagged with a garbage score indicating its quality. If the garbage score of a text segment exceeds a threshold value, the corresponding image segment can be automatically displayed instead.
US09280950B2	Display device, method for driving display device, and electronic apparatus A display device includes an illumination unit that delivers a first light, a second light and a third light. The display also includes a driving circuit that supplies a pixel with a first data signal for displaying a first image by illuminating the first light, the driving circuit supplying the pixel with a second data signal for displaying a second image by illuminating the second light, the driving circuit supplying the pixel with a third data signal for displaying a third image by illuminating the third light.
US09280945B2	Liquid crystal display device and method of driving the same An LCD device is disclosed which includes: a liquid crystal display panel in which there are a plurality of gate lines and a plurality of data lines; a data driver configured to apply data voltages to the data lines; a gate driver configured to apply gate pulses to the gate lines; and a charge share device configured to selectively perform a charge share operation by storing charges corresponding to a data voltage applied to one of the data lines during a first interval and providing the stored charges to said one or another one of the data lines during a second interval based on a comparison of first video data corresponding to said one of the data lines in the first interval with second video data corresponding to said one or another one of the data lines in the second interval.
US09280941B2	Liquid crystal display device with direct type backlight and method of driving thereof A direct type liquid crystal display device according to an embodiment of the present disclosure may enhance the brightness uniformity.
US09280940B2	Liquid crystal display device, four-color converter, and conversion method for converting RGB data to RGBW data An LCD device includes a four-color converter for converting an original RGB data into three grayscale values, executing a white balance process to the three grayscale values, and confirming a maximum value MAX (Ri, Gi, Bi) and a minimum value of the three white-balanced grayscale values Ri, Gi, and Bi, wherein, when the minimum value is greater than 0, determining that if the three data of the original RGB data are equal, and when they are equal, utilizing a formula Wo=Bi; Ro=Ri×Wo/MAX(Ri, Gi, Bi)+Ri−Wo; Go=Gi×Wo/MAX(Ri, Gi, Bi)+Gi−Wo; Bo=0 to calculate the output grayscale values Ro, Go, Bo, and Wo in the RGBW data. The device also includes a data driver for processing the RGBW data provided by the four-color converter to generate analog type data signals, a scanning driver for sequentially generating scanning signals, and an LCD panel for displaying colors.
US09280938B2	Timed sequence mixed color display In embodiments of mixed sequential color display, a light source sequentially generates different colors of light in a timed sequence. A display panel is implemented with multiple sub-pixel combinations, where each pixel of the display panel is a combination of sub-pixels that emit a color based on a color of the light that illuminates a sub-pixel combination. The emitted color from a sub-pixel combination is generated as a product of the color of the light and a combination of sub-pixel colors (to include clear and/or colored sub-pixels). The clear and/or different colored sub-pixels in a sub-pixel combination are a spatial aspect of the emitted color, and the sequentially generated different colors of light are a temporal aspect of the emitted color. The pixel combination and the light source together enhance the luminescence of the emitted color over the chrominescence of the emitted color.
US09280934B2	Electroluminescent display device with combined analog and digital driving To reduce the number of sub-frames and perform high resolution display with low power consumption, each of the pixels has a digital emission period Td and an analog emission period Ta, and is driven in a time-divided fashion in a digital manner or in an analog manner. Each of the pixels performs high resolution display when being driven in an analog manner, and performs display with low power consumption when being driven in a digital manner.
US09280930B2	Back to back pre-charge scheme A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage block for storing the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel pre-charge mechanism for pre-charging the pixel elements employing a back to back pre-charge operation applied to a row and/or column drive activated pixel element display operation. The back to back pre-charge operation signifies that during every other operating sequence a pre-charge operation is replaced by an activated pixel element display operation.
US09280929B2	Display device and method for driving the same Each pixel of a display device includes: an organic light emitting diode between a first and a second power supply; a first transistor to transmit a drive current based on data signals; a second transistor to couple a gate electrode of the first transistor to the data line in response to a scan signal; a first capacitor between the first power supply and the gate electrode of the first transistor; a light receiving element coupled to a third power supply; a second capacitor between the light receiving element and a fourth power supply; a third transistor between the data line and a first electrode of the second capacitor, the third transistor including a gate electrode coupled to a selection signal line; and a fourth transistor between the fourth power supply and the third transistor, the fourth transistor including a gate electrode coupled to the first electrode of the second capacitor.
US09280924B2	Display device and method that divides one frame period into a plurality of subframe periods and that displays screens of different colors in accordance with the subframe periods A display device that adopts a field sequential method and that is capable of achieving desired luminance while suppressing mixing of colors is provided. With respect to display of each color by a liquid crystal display device adopting a field sequential method, a period is provided for which light sources of each color remain turned on until a turning-off delay time has elapsed since an end timing of a subframe period. The turning-off delay time relating to LEDs for which an off state begins in a preceding subframe period is configured in such a way as to be shorter than a turning-on delay time relating to LEDs for which an on state begins in a succeeding subframe period. As a result, an all-off period, in which LEDs of all colors are in the off state, is provided between on periods of two colors.
US09280923B2	Display device operating in 2D and 3D display modes and method for driving the same A display device includes a first scan line, a second scan line, a third scan line, a data line, a pixel, a low color-shifting circuit, and a black zone generation circuit. In the low color-shifting circuit, a low color-shifting switch receives a third scan signal from the third scan line to selectively couple a compensating capacitor to the second sub-pixel electrode. The black zone generation circuit receives a black zone generation signal to selectively couple either the first sub-pixel electrode or the second sub-pixel electrode to a common node such that either the first sub-pixel or the second sub-pixel becomes a black zone.
US09280915B1	Spinal injection trainer and methods therefor For use in training needle techniques such as spinal anesthesia and or lumbar epidural steroid injections, a spinal model includes a complete natural bone vertebral column that is embedded in a matrix of crystal clear ballistic gel. The synthetic gel does not harbor bacteria, can be reused and does not require refrigeration. Natural bone offers significantly better image contrast over radiopaque replicas. A transparent synthetic gel matrix permits observation of needle progression by both the trainee and the trainer and provides unique opportunities for coaching and intercession to prevent poor needle placement prior to its occurrence.
US09280903B2	In-aircraft flight planning with datalink integration In one embodiment an in-aircraft system that implements a flight planning module is provided. The flight planning module is configured to display on the display unit a pending flight plan and implement a first button associated with a display of the pending flight plan. The first button, if selected, directs the one or more processing units to convert the pending flight plan to a format for sending in a datalink message, and to cause the pending flight plan to be sent to a ground station in a downlink datalink message without human input to a message applications module, the message applications module including instructions to display information corresponding to datalink messages on a display unit and to maintain a message log of datalink messages.
US09280893B2	Communication systems and methods to broadcast audio or control to a remotely located device This disclosure enables a respective user to show support to a person of interest. One configuration includes a network (e.g., phone network, Internet, etc.) configured to receive input from a respective user (e.g., family member, friend, etc.) and control a remotely located device. The remote device can be located at any suitable locations such as a gravesite of a deceased party, a hospital room in which a disabled patient resides, etc. Via input from a respective user, the respective user can control different functions of a remote target device such as audibly communicate one or more messages in a vicinity of the gravesite, control a remote device such as light source (such as a candle, light emitting diode, etc.), etc.
US09280889B2	Alert network and method for transmitting and propagating alerts An alert network is described. The alert network has a plurality of individual monitoring systems, a plurality of user terminals respectively associated with the individual monitoring systems, alert transmitters in the monitoring systems, for transmitting primary alerts to selected user terminals and/or to other monitoring systems in accordance with parameterized transmission rules, alert receivers in said terminals, and alert propagators in the terminals, capable of selectively propagating received primary alerts to other terminals and or to other monitoring systems as secondary alerts, in accordance with parameterized propagation rules. A method for transmitting and propagating alerts according to corresponding parameters in such a network is also described.
US09280886B2	Circuit monitoring device The circuit monitoring device is disclosed. The device is for monitoring circuit resistance. At configurable thresholds digital flags are triggered, the device can be used as a Security/Building management system. The device uses open technology is fully scaleable and allows programmable logic controllers to be used as security management systems. Using a soft logic option a PC could take the place of the PLC.
US09280884B1	Environmental sensor device with alarms An environmental sensor device with alarms comprises a data bus, a multitude of sensors, at least one processing unit, a communications interface, and memory. The multitude of sensors may include particle counter(s), pressure sensor(s) and/or the like. The memory is configured to hold data and machine executable instructions. The machine executable instructions are configured to cause at least one processing unit to: collect sensor data from at least one of the multitude of sensors, generate processed sensor data from the sensor data, and set alarm(s) based, at least in part on processed sensor data. The communications interface is configured to communicate the report to at least one external device.
US09280883B2	Method and apparatus for visually and audibly indicating the setup and maintenance of a system Example embodiments of the present invention relate to a method and apparatus for visually and audibly indicating the setup and maintenance of a system.
US09280880B1	Method and system for generating alternative identification payment cards A method for generating alternative identification payment cards includes: storing, in a database, a plurality of payment account numbers, wherein each payment account number is associated with a payment account; generating, by a processing device, an alternative identification number for each payment account number of the plurality of payment account numbers, wherein the alternative identification number includes at least a program identifier, a unique identifier, and a check value; generating, by the processing device, a data file including each payment account number of the plurality of payment account numbers and the generated alternative identification number for each respective payment account number; and transmitting, by a transmitting device, the generated data file for printing a plurality of payment cards.
US09280878B2	Reel band, reel assembly, and gaming machine In a reel band, the transmittance of the light emitted from a backlight is adjusted without using a sheet for decreasing the transmittance, and the reel band is decorated without resort to printing. A reel band M32 includes: a translucent base layer M320; a symbol print layer M322 laminated on an outer side of the base layer M320 with respect to a direction of a thickness of the base layer M320 to form a plurality of symbols 501; and a mesh pattern layer M321 having rough texture and laminated on a portion of the base layer which portion is different from portions on which at least the plurality of symbols 501 are formed when viewed from a direction in which the layer is laminated, the mesh pattern layer M321 including a shield area M3211 configured to attenuate applied light and a non-laminated area M3212 configured to pass applied light.
US09280877B2	Method of gaming, a game controller and a gaming system A method of gaming comprising: awarding a plurality of game rounds in response to occurrence of a trigger event; and conducting at least two of the plurality of game rounds concurrently in separate display areas.
US09280875B2	Virtual playing chips in a multiuser online game network In various embodiments, virtual currency is used within a multiplayer online game in a restricted manner.
US09280874B2	Gaming system and method employing a player-selected feature for a play of a game or using the player-selected feature to modify another feature for a subsequent play of the game Various embodiments of the present disclosure are directed to a gaming system and method providing a game employing a player-selected one of a plurality of different features. In one embodiment, the gaming system is configured to operate a game associated with a set of a plurality of different features, and enables a player to select one of the features for a play of the game. In certain instances, the gaming system provides the play of the game in accordance with the selected feature. In other instances, the gaming system provides the play of the game without the selected feature, and uses the selected feature to modify one of the other, non-selected features that has a designated relationship with the selected feature. The gaming system subsequently enables the player to select the modified feature for a subsequent play of the game.
US09280872B2	Progressive jackpot alerts in a gaming system Various embodiments are directed to a gaming system capable of providing progressive level alerts or promotions when a progressive jackpot reaches a predetermined value. In one embodiment, the user is able to register for a progressive level alert. In another embodiment, the progressive level alert is presented on an affiliated or third party website. By providing progressive jackpot amount information, the user, who may not otherwise patronize a casino, is encouraged to visit the particular casino offering games capable of awarding a progressive jackpot prize of a predetermined amount.
US09280871B2	Gaming systems with authentication token support Techniques for providing authentication functionality in a gaming system are disclosed. In one aspect, a gaming system is configured such that, at a given point during a current session of a game in progress that involves at least one user previously granted access by the system to participate in the current session, information available from an authentication token associated with the user is obtained prior to allowing the user to take a particular action in the game. A determination is made as to whether or not the user will be allowed to take the particular action in the game, based on the obtained information. The obtained information may comprise, for example, at least a portion of a one-time password generated by a hardware or software authentication token.
US09280866B2	System and method for analyzing and predicting casino key play indicators A gaming system and method is set forth which provides for the predictive analysis of gaming machine performance. In one embodiment, a user may obtain useful predictions of gaming asset performance and may determine assets which should be replaced by using Microsoft® Analysis Services as a component of a predictive.
US09280865B2	Identifying defects in a roulette wheel Systems and methods for identifying defects in a roulette wheel are described. A first trajectory of a roulette ball may be determined after launch of the roulette ball by capturing movement of the roulette ball on the roulette wheel. The roulette wheel has a region where the roulette ball orbits and spins around before the roulette ball falls into a roulette number pocket. The determining step may be repeated to determine additional trajectories, and a plurality of areas that the roulette ball avoided during travel along the trajectories may be identified. A graphical representation of the plurality of avoided areas may be generated to identify regions of the roulette wheel that include defects.
US09280863B2	Automated dispensing system for pharmaceuticals and other medical items A system for dispensing a plurality of customized doses of pharmaceuticals includes: a housing; a customer interaction station; a customized packaging station configured to selectively package individual doses of medication into customized packaging, the medications being selected responsive to input from the customer input station; and a controller connected to the customer interaction station and the customized packaging station, the controller configured to control the customized packaging based on customer input from the customer interaction station.
US09280861B2	Paper-sheet handling apparatus and paper-sheet handling method A paper-sheet handling apparatus (10) includes: a recognition unit (14) configured to obtain recognition information of a paper sheet by recognizing the paper sheet, and to obtain an image of the paper sheet so as to obtain paper-sheet information from the acquired image of the paper sheet; a reject unit (18) to which a paper sheet, which is other than a paper sheet that has been recognized as a normal paper sheet by the recognition unit (14), is sent; and a control unit (30) configured to output display information about the paper-sheet information of each paper sheet sent to the reject unit (18). The display information output by the control unit (30) is displayed on a display unit (22) disposed on the paper-sheet handling apparatus (10), or transmitted to an external apparatus (40), which is other than the paper-sheet handling apparatus (10), through an interface unit (39) so as to be displayed on a display unit disposed on the external apparatus (40).
US09280859B2	Enhanced vehicle onboard diagnostic system and method The invention includes methods and devices for an improved onboard vehicle diagnostic system. The methods and devices provide for more detailed information and presentation of diagnostic and vehicle performance data for a user. In one example, real time diagnostic and trip system performance data is gathered and displayed relative to time for improved understanding of vehicle performance and operation by a user.
US09280857B2	Dynamic uploading protocol A dynamic uploading protocol comprises an input interface configured to receive a manifest comprising a plurality of events which may be uploaded; wherein the manifest additionally comprises sensor information relating to each of the plurality of events. The system for a dynamic uploading protocol additionally comprises a processor configured to determine whether to upload additional information about each event, wherein determining whether to upload additional information about each event is based at least in part on the sensor information and contextual information. The system for a dynamic uploading protocol additionally comprises an output interface configured to request the additional information. The system for a dynamic uploading protocol additionally comprises a memory coupled to the processor and configured to provide the processor with instructions.
US09280855B2	Remote recognition processing system and method A computerized method for intelligently distributing computer processing of mail piece scan images across a plurality of mail piece scan image processors. The method can include receiving a mail piece scan image from a mail piece scan image job requestor and selecting one of a plurality of scan mail piece scan image processors to process said mail piece scan image. The mail piece scan image can be transmitted to said one of a plurality of plurality of mail piece scan image processors and a mail piece scan image processing result can be received from said one of a plurality of plurality of mail piece scan image processors. Post-processing operations can be performed based on said mail piece scan image processing result. The mail piece scan image processing result can be transmitted to said mail piece scan image processing requestor.
US09280853B2	Virtual and augmented reality Technologies are generally described for systems, devices and methods effective to implement virtual and augmented reality. In an example, a first device may send data to a second device. The first device may include a processor and a memory. The processor may receive first image data based on a first real image from a third device. The first real image may include a fourth device image that relates to a fourth device. The processor may receive second image based on a second real image from the fourth device. The processor may send the first image data to the second device. The processor may receive a first request from the second device to receive the second image data. The processor may send a second request to the fourth device for the second image data, receive the second image data, and send the second image data to the second device.
US09280851B2	Augmented reality system for supplementing and blending data A system, method, and computer program product for automatically combining computer-generated imagery with real-world imagery in a portable electronic device by retrieving, manipulating, and sharing relevant stored videos, preferably in real time. A video is captured with a hand-held device and stored. Metadata including the camera's physical location and orientation is appended to a data stream, along with user input. The server analyzes the data stream and further annotates the metadata, producing a searchable library of videos and metadata. Later, when a camera user generates a new data stream, the linked server analyzes it, identifies relevant material from the library, retrieves the material and tagged information, adjusts it for proper orientation, then renders and superimposes it onto the current camera view so the user views an augmented reality.
US09280850B2	Augmented reality system for communicating tagged video and data on a network A system, method, and computer program product for automatically combining computer-generated imagery with real-world imagery in a portable electronic device by retrieving, manipulating, and sharing relevant stored videos, preferably in real time. A video is captured with a hand-held device and stored. Metadata including the camera's physical location and orientation is appended to a data stream, along with user input. The server analyzes the data stream and further annotates the metadata, producing a searchable library of videos and metadata. Later, when a camera user generates a new data stream, the linked server analyzes it, identifies relevant material from the library, retrieves the material and tagged information, adjusts it for proper orientation, then renders and superimposes it onto the current camera view so the user views an augmented reality.
US09280848B1	Rendering images with volumetric shadows using rectified height maps for independence in processing camera rays Rendering a scene with participating media is done by generating a depth map from a camera viewpoint and a shadow map from a light source, converting the shadow map using epipolar rectification to form a rectified shadow map (or generating the rectified shadow map directly), generating an approximation to visibility terms in a scattering integral, then computing a 1D min-max mipmap or other acceleration data structure for rectified shadow map rows and traversing that mipmap/data structure to find lit segments to accumulate values for the scattering integral for specific camera rays, and generating rendered pixel values that take into account accumulated values for the scattering integral for the camera rays. The scattering near an epipole of the rectified shadow map might be done using brute force ray marching when the epipole is on or near the screen. The process can be implemented using a GPU for parallel operations.
US09280846B2	Method, apparatus, and computer-readable recording medium for depth warping based occlusion culling A method for performing occlusion queries is disclosed. The method includes steps of: (a) a graphics processing unit (GPU) using a first depth buffer of a first frame to thereby predict a second depth buffer of a second frame; and (b) the GPU performing occlusion queries for the second frame by using the predicted second depth buffer, wherein the first frame is a frame predating the second frame. In accordance with the present invention, a configuration for classifying the objects into the occluders and the occludees is not required and the occlusion queries for the predicted second frame are acquired in advance at the last of the first frame or the first of the second frame.
US09280843B1	Hybrid images for maps combining low frequency map data and high frequency satellite image data Hybrid images merge the benefits of map views and satellite images. A geographic information system includes a geographic information server and at least one database containing a plurality of map views and satellite images. A decomposition module of the geographic information server decomposes the map views and the satellite images into at least high frequency components and low frequency components. A map view and satellite image hybridization module blends the high frequency components from the map view and the high frequency components from the satellite image. Then, the hybridization module combines the low frequency components of the map view with the blended high frequency components from both the map view and the satellite image to form a hybrid image. The hybrid image can subsequently be stored in a database of the geographic information system and/or served to a client device via a network.
US09280840B2	Figure display device, figure display method and storage medium storing a figure display program A figure display device, a figure display method and a storage medium having a figure display program are described. According to one implementation, a figure display device includes a figure display section; an assumed equation input section; and a figure assumed portion discrimination display control section. The figure display section displays a figure. The assumed equation input section is used to input an assumed equation of the figure according to user operation. The figure assumed portion discrimination display control section deforms a corresponding portion of the assumed equation in the figure to match a figure portion obtained by the assumed equation, and illustrates a content represented by the assumed equation in the figure displayed with discrimination.
US09280837B2	Angiographic image acquisition system and method with automatic shutter adaptation for yielding a reduced field of view covering a segmented target structure or lesion for decreasing X-radiation dose in minimally invasive X-ray-guided interventions The present invention refers to an angiographic image acquisition system and method which can beneficially be used in the scope of minimally invasive image-guided interventions. In particular, the present invention relates to a system and method for graphically visualizing a pre-interventionally virtual 3D representation of a patient's coronary artery tree's vessel segments in a region of interest of a patient's cardiovascular system to be three-dimensionally reconstructed. Optionally, this 3D representation can then be fused with an intraoperatively acquired fluoroscopic 2D live image of an interventional tool. According to the present invention, said method comprises the steps of subjecting the image data set of the 3D representation associated with the precalculated optimal viewing angle to a 3D segmentation algorithm (S4) in order to find the contours of a target structure or lesion to be examined and interventionally treated within a region of interest and automatically adjusting (S5) a collimator wedge position and/or aperture of a shutter mechanism used for collimating an X-ray beam emitted by an X-ray source of a C-arm-based 3D rotational angiography device or rotational gantry-based CT imaging system to which the patient is exposed during an image-guided radiographic examination procedure based on data obtained as a result of said segmentation which indicate the contour and size of said target structure or lesion. The aim is to reduce the region of interest to a field of view that covers said target structure or lesion together with a user-definable portion of the surrounding vasculature.
US09280835B2	Method for coding and an apparatus based on a DC prediction value The disclosure relates to encoding and decoding image information. The encoding comprises receiving a block of pixels; determining a set of potential reference samples for the block of pixels; selecting a subset of the set of potential reference samples to be used as reference samples for the block of pixels; and using the selected reference samples to determine a DC prediction value for the block of pixels. A prediction error is determined for a pixel in the block of pixels on the basis of the DC prediction value. The decoding comprises receiving an encoded block of pixels; determining reference samples for the encoded block of pixels; and using the determined reference samples to define a DC prediction value for the block of pixels. A prediction error is received for a pixel of the encoded block of pixels. The pixel value is reconstructed on the basis of the DC prediction value.
US09280830B2	Image processing apparatus and segmentation method An image processing apparatus for extracting an area of a detection target from an image includes an image input section that acquires an image, an image generation section that generates a plurality of images with different resolutions from the image, and a segmentation section that performs segmentation using the plurality of images with the different resolutions. The segmentation section segments an image with a low resolution and then segmenting an image with a high resolution using, as a processing target area, an area in the image with the high resolution corresponding to an area near a boundary resulting from processing of the segmentation of the image with the low resolution.
US09280824B2	Vehicle-surroundings monitoring device A camera-orientation estimation unit estimates the amount of change in camera orientation on the basis of vehicle speed changes obtained from a vehicle-information acquirer. A distance-information update decision unit decides, on the basis of the amount of change in camera orientation, whether to update distance information by computing new distance information in a distance-computation unit or to update distance information using distance information stored in a distance-information memory unit. If the distance-information update decision unit has decided to update distance information by computing new distance information, a display device displays distance information that the distance-computation unit computes from a real-time image. If the distance-information update decision unit has decided to update using past stored distance information, the display device displays past distance information read from the distance-information memory unit.
US09280821B1	3-D reconstruction and registration Generating three-dimensional information can include obtaining multiple different images of an object taken by camera(s), each image having a near-planar surface depiction of the object; registering the images in two-dimensions by identifying one or more features of each image and generating a two-dimensional representation of each feature; selecting first and second images from the registered images; generating one or more correspondences between one or more features of the first and second images; estimating a camera parameter set for each of the first and second images within respective ones of the identified features; reconstructing a three-dimensional structure of the object in Euclidean space responsive to the one or more correspondences and the estimated camera parameter sets; refining the estimated camera parameter sets using the three-dimensional structure; and refining the three-dimensional structure using the refined camera parameter sets. Camera parameter sets can include a rotation matrix, translation vector, and focal length.
US09280816B2	Adaptation of a 3D-surface model to boundaries of an anatomical structure in a 3D-image data set The invention relates to the adaptation of a 3D-surface model to boundaries of an anatomical structure, especially the right ventricle. A first viewing plane is defined corresponding to a default view, especially a four chamber view. A long axis is defined. Then a second, third and optionally a fourth viewing plane are represented intersecting the axis in predefined distances from the starting point and end point thereof. On the viewing planes different markers are represented, controlled and, if required, the position thereof is adapted, especially the position of the intersection points of the axis with the second and third viewing planes, as well as the position of a characteristic line, which together with the end point of the axis spans a characteristic plane of the structure. The 3D-surface model is adapted to the structure by way of the long axis and the position of the characteristic plane.
US09280814B2	Charged particle beam apparatus that performs image classification assistance The charged particle beam apparatus automatically judges the good or bad of an observation object on the basis of information obtained from an image of the observation object on a wafer; displays a judgment result on a screen; displays the observation object, extracted from the judgment result, that requires to be corrected on the basis of the good or bad of the observation object from a user; and corrects the judgment result to the extracted and displayed observation object on the basis of an instruction from the user.
US09280813B2	Blur measurement An image is partitioned into a foreground area, a background area, and optionally a transitional area. The partitioning may be pre-defined, or it may be based on user inputs and configuration data. The partitioning may also be refined based on an initial partitioning. Blur measures are determined respectively for the partitioned areas. A blur measure for the whole image can then be determined from a weighted average of the blur measures for the partitioned areas. The blur measure for the image can be used in a video quality monitor.
US09280804B2	Rotation of an image based on image content to correct image orientation In some implementations, a method rotates images based on image content to correct image orientation. In some implementations, a method includes obtaining one or more identifications of content depicted in an image and determining a current orientation of the content depicted in the image. The current orientation is determined based on the one or more identifications of the content. An amount of rotation for the image is determined that orients the content closer to a predetermined reference orientation than to the current orientation. The image is rotated by the determined amount.
US09280802B2	Method and apparatus for storing information of a picture Disclosed are method and apparatus for storing information of a picture. The method includes presenting a picture file to be edited, which at least includes original picture data; editing the picture file with an interface engine; integrating rendering information of the edited picture file according to a preset picture file format; and storing the original picture data and the rendering information. According to the invention, the interface engine is improved, and thus may directly edit a picture in use, and integrate the rendering information of the edited picture file according to a preset picture format. Therefore, during development, it is not required to store rendering information of a picture into codes, so that no programmer is required to intervene in rendering and setting of the picture. An art-designer may directly operate on the interface engine to change rendering effects, meanwhile, final rendering effects may be observed without running a program.
US09280801B2	Method of searching for pixels in a matrix and circuit implementing the method A pixel matrix is arranged in line of pixels. Each pixel is either in a first state or in a second state. The matrix mainly contains pixels in the second state. Each line of pixels is tested in order to determine whether it contains or not a pixel in a first state. The result from this test for each line is sent into a receiver. The lines including at least one pixel in the first state are more accurately analyzed in order to determine the position of this or these pixel in the line.
US09280794B2	Providing access to documents in an online document sharing community Provided are computer program product, system, and method for providing access to documents in an online document sharing community in a network environment including a plurality of participant computers operated by participants in the online document sharing community and a storage system. Document content is processed to add search terms for the document and a document identifier to a search index accessible through a search engine over the network to participants not under an obligation of confidentiality to the owner with respect to the document. Access is provided to the content of the document to the participants in the online document sharing community. A determination is made of a publication time the document was included in the search index and made accessible to the participant computers operated by participants not under the obligation of confidentiality to the owner of the document content.
US09280789B2	Recommending native applications In one implementation, a computer-implemented method includes accessing, by a computer system, information that describes use of one or more computer-based services by a particular user from one or more computing devices that are associated with the particular user; identifying one or more native applications that are associated with the one or more services, wherein the one or more native applications are configured to be installed and executed by one or more types of mobile computing devices; determining whether to recommend the one or more native applications based on the information and one or more threshold levels of use of the one or more computer-based services; and providing, based on the determining, a recommendation that is associated with the particular user and that identifies at least one of the one or more native applications.
US09280786B2	Product-based advertising A method and a system that identify seller ads to potential buyers within a network-based commerce system are provided. The method and system may operate to receive a request including a product identification from a seller, and assign to the seller, based on a distance function and the product identification, a matching identification entry included in a set of identification entries. The request may also include financial metrics. The method and system may further include operations to identify one or more seller ads associated with the matching identification entry, as determined by a distance measured between the matching identification entry and at least one extracted identification entry extracted from a selected content page and included in the set of identification entries. The identification of the one or more seller ads may also be determined by a relevance function based on the financial metrics.
US09280783B2	System and method for providing customized on-line shopping and/or manufacturing A system and method for providing a customized on-line shopping interface and/or manufacturing is disclosed. The system uses customer's computer, location, URL, IP address, email domain, embedded promotion code, or other predetermined criteria to provide special product offerings and pricing for a particular class or subclass of customers. If an unauthorized user attempts to access the system, a series of screens containing non-customized pricing is presented to the intruder so as not to alert the intruder that he or she has reached the restricted content. Based on the authentication information, automated manufacturing processes and equipment may be utilized to produce the customized products.
US09280782B1	Deal based communications via multiple channel options Architectures and techniques are described to provide a number of options to exchange information related to deals via a plurality of channels. Each of the communication channels may be utilized to exchange communications about different aspects of acquiring and redeeming deals. The channel options may be related to categories of computing devices, operating systems executed by computing devices, one or more sites, various forms of communication, client device applications, etc. A service provider that offers deals on behalf of merchants may determine one or more options for each communication channel with respect to merchants offering deals and with respect individuals that may participate in deals offered by the service provider. After determining the channel options for a deal offered by a particular merchant and for individuals designated to receive information about the deal, communications with respect to the deal may be exchanged over the channels via certain channel options.
US09280781B1	Referral system and method A system comprising a referral acceptor; a referral coordinator coupled to the referral acceptor; a referral calculator coupled to the referral calculator; and an input/output (I/O) device coupled to the referral coordinator. The referral acceptor is configured to accept a referral card. The referral card has a referrer identifier which identifiers a referrer of a holder of the referral card.
US09280772B2	Security token for mobile near field communication transactions Devices, systems, and methods are disclosed which relate to an NFC-enabled security token that is removably coupled to a mobile device. The security token may be provisioned with the information by the mobile device, then decoupled from the mobile device and used to authenticate the user or perform a transaction at a POS terminal equipped with an NFC reader. The security token includes logic for user-controlled restrictions on allowable purchases, such as payment limits, timeouts, vendor identifiers, allowed purchases, and location-based restrictions. The security token is further equipped with “self-destruct” security features, such as deactivating itself or erasing any sensitive information upon being unable to contact the mobile device for a specified duration, or being subject to an unauthorized or restricted transaction, until such time as it is re-coupled to the mobile device.
US09280771B2	Secure personal information profile A method, programmed medium and system are provided for implementing a prebuilt and encrypted personal identification information (PII) profile which resides only on a user's computer and is prevented from being permanently stored in a server's database. When a user visits a web site and creates a new account, the site submits a request to query the user's profile using an extension to the HTTP protocol. The user is prompted by the user's browser to grant the site permission to do so and the site automatically uploads a non-personal identifying number (ID) to the user's system to create an account. User-selected fields of the PII are transmitted to the server for processing a user-requested transaction. All personal information remains on the user's computer within the user's encrypted PII profile and is deleted at the server after the completion of the requested transaction.
US09280770B2	Secure point of sale presentation of a barcode at an information handling system display Unauthorized copying of a transaction barcode is prevented by including a sensed condition or other publicly-accessible data with the transaction barcode for use as a comparison with the publicly accessible data determined at a barcode reader. If the sensed condition included in the transaction barcode indicates that the transaction barcode was generated for a different transaction, then the barcode reader invalidates the transaction. For instance, if the barcode was generated too distant in time, position, or sequential transactions, then the barcode reader invalidates the transaction barcode as an unauthorized copy of a transaction barcode generated for a different transaction.
US09280769B2	Mobile commerce payment system A mobile commerce system and components thereof are provided in which multiple wireless mobile communications devices (mobile devices) each has a unique electronic identification and processing circuit capable of encrypting data utilizing an encryption key and a first software application providing connectivity to commercial webpage servers for purposes that include the conduct of selected transactions involving a payment for goods or services. Each mobile device is independently enabled to conduct financial transactions in real time by communication with a financial institution. Each mobile device further has a second software application termed mobile payment application adapted to interact with the first application to receive data as to a payment required to conclude a transaction conducted by way of a commercial webpage server. The mobile payment application initiates an instruction to the financial institution to make a payment to a payee designated by way of such data wherein the instruction is encrypted utilizing the unique electronic identification and processing circuit.
US09280768B2	Payment systems and methodologies A transaction system including at least two transaction communicators, at least one of which is a mobile communicator, at least one of the at least two transaction communicators having sequential visually sensible indicia generation functionality operative to generate a time sequence of indicia which provides at least transaction data and at least one of the at least two transaction communicators having sequential visually sensible indicia receiving functionality and transaction data extraction functionality capable of extracting at least the transaction data from the time sequence of particular indicia, whereby a time sequence of indicia which provides at least transaction data is transmitted from one of the at least two transaction communicators to another of the at least two transaction communicators.
US09280766B2	Cascading definition and support of EDI rules Electronic data interchange (EDI) documents are validated by creating an inventory of all rules, dynamically adjusting the inventory based upon entity specific rules derived from a plurality of companion guides, determining a profile containing pointers to select rules in the inventory for each companion guide and storing the profile for each companion guide in a storage. A runtime checker can then be used to check a received EDI document with a corresponding rule set, forward the EDI document if the EDI document matches its current rule set and return the EDI document if the EDI document does not match its current rule set. EDI rules may be enforced, for example, by determining entity-specific rules from corresponding companion guides, by expressing each rule in a neutral and machine readable format, by classifying the rules and/or by creating an inventory of rules and pointers to entity-specific rules.
US09280763B2	Method and system of automating data capture from electronic correspondence In some embodiments, electronic data may be automatically captured to provide a user with a universal Internet identity and e-mail address, comprehensive e-mail filtering and forwarding services, and e-receipt identification and data extraction. Detailed user e-mail preferences data stored at a central server may be selectively altered such that incoming correspondence is redirected in accordance with the user's preferences. Computer program code at the central server may parse incoming e-mail header information and data content, selectively extract data from identified types of correspondence, and forward the extracted data in accordance with the user's preferences. Additional computer program code may manipulate the extracted data in accordance with format requirements and display the manipulated data to a user in a desired format.
US09280761B2	Systems and methods for improved interactive content sharing in video communication systems Systems and methods for interactively sharing and annotating visual information over a communication network between at least a first and a second endpoint are disclosed. The system includes a display coupled to the first endpoint and a user interaction device coupled to the first endpoint and associated with the display, wherein the first endpoint is configured to: receive visual information from, and transmit visual information to, at least the second endpoint over the communication network; show visual information received from at least the second endpoint on the display; obtain a copy of the visual information shown on the display when instructed by the user interaction device; add an annotation, if any, as indicated by the user interaction device; and transmit the annotated copy to the second endpoint.
US09280757B2	Automated inventory management A method comprising determining an inventory exception inference associated with a product, determining an inventory inspection directive for the product based, at least in part, on the inventory exception inference, receiving the inspected inventory state data based, at least in part, on the inventory inspection directive, and determining that an actual inventory exception exists for the product based, at least in part, on the inspected inventory state data is disclosed.
US09280756B2	Managing individual item sequencing from a storage area to a packing station in a materials handling facility Various embodiments of a system and method for managing shipment release from a storage area in a materials handling facility are described. Embodiments may include a system configured to determine that a shipment including multiple units is expected to be conveyed from a storage area to a packing station in a materials handling facility. The system may also be configured to evaluate each respective unit of the shipment according to one or more criteria related to physical characteristics of the unit in order to generate an order in which the units of the shipment are to be provided to the packing station. The system may also be configured to generate an instruction to provide the units of the shipment to the packing station according to the generated order.
US09280753B2	Translating a language in a crowdsourced environment Program code on one or more computers receives a request from a first end-user to join a crowdsourced network of language translators (crowdsourced network). The program code determines the first end-user is a registered member of the crowdsourced network. The program code adds the first end-user as a language translator within the crowdsourced network. The program code receives from a second end-user a request for language translation service to translate plain text from the second end-user. The program code selects one of the language translators from the crowdsourced network who is qualified to perform the language translation service requested. The program code generates an interactive chat session to connect the language translator selected with the second end-user, wherein the language translator selected translates the plain text, via the interactive chat session that allows plain text to be translated at least more frequently than on an hourly basis.
US09280752B2	Method, system and computer-readable medium for E-form information extraction template creation Certain example embodiments described herein relate to techniques for enabling a business process model (BPM) to be transparent (in whole or in part) from the source of data that triggers it. More particularly, certain example embodiments relate to techniques enabling transparent composition and decomposition of e-form data from one or more e-form formats into data that is directly usable by a Business Process Model Engine. Information from an e-form may, for example, be used in a business process, e.g., after a template or document type is created that represents the e-form in a format that the BPM Engine understands, and the e-form may be transparently composed into and decomposed out from the business data in certain example embodiments.
US09280751B2	Methods and systems for validating real time network communications Methods and systems for managing network communications are described. An example resource management system includes a communications manager configured to access information regarding communication protocols used by corresponding broker systems and to provide message translations based on an origin and/or destination of the message to be transmitted. A message processor is coupled to the communications manager and is configured to serialize incoming and/or outgoing broker messages and to facilitate queuing of incoming and outgoing message traffic with broker systems. A communications configurer is configured to track one or more communication attributes of broker systems and changes thereto to ensure communications between the resource management systems are broker systems are conducted in accordance with the communication attributes of the broker systems. A communications rules provider is configured to determine which broker system is to be communicated with in order to fulfill a resource request.
US09280749B1	Determining an attribute of an online user using user device data A computer-implemented method for determining an attribute for an online user of a candidate computing device is provided. The method implemented uses a host computing device. The method includes identifying a first set of model data including device data from a plurality of model computing devices including location data and access data, and a plurality of categories for an attribute of a population segment including an online user. Each category defines a segment of the attribute. The method further includes training a classification model by the host computing device with at least the first set of model data and the plurality of categories. The method also includes identifying device data associated with the candidate computing device. The method further includes applying the device data of the candidate computing device to the classification model to determine a category of the plurality of categories for the online user.
US09280746B2	Posterior probability of diagnosis index The likelihood of a disorder can be determined using a variety of techniques. One or more exhibited symptoms may be obtained for a patient. The likelihood that each symptom will be exhibited for the disorder can be computed, and a posterior probability of the disorder given the exhibited symptoms can be computed from the likelihood of the symptoms. Based on the resulting posterior probability of the disorder, a more accurate determination can be made of whether the patient is suffering from the disorder.
US09280744B2	System and method for optimal power flow analysis A method determines a power flow of a power grid by optimizing an objective function representing an operation of the power grid using a spatial branch and bound (BB) framework for determining iteratively upper and lower bounds of the objective function. During the optimization, the lower bounds are determined using a semi-definite programming (SDP) relaxation of an optimal power flow (OPF) problem.
US09280735B2	Data processing apparatus that processes information based on data processing in connection with user information An image formation apparatus configured to execute print processing, includes an information storage configured to store print-limit information and notification-destination information set for each user. The print-limit information includes at least one of a print condition and a limit on a printable amount. A user-information acquisition unit is configured to acquire print-instructing-user information, which is information on a print-instructing user instructing a print-executing user to execute printing. An information-acquisition unit is configured to acquire, from the information storage, the print-limit information and the notification-destination information corresponding to the print-instructing-user information acquired by the user-information acquisition unit, and a notification unit is configured to notify the print-instructing user of a result of print control by the print controller, based on the notification-destination information acquired by the information-acquisition unit.
US09280734B2	Image forming apparatus that performs highly-accurate calibration, calibration program, and calibration system An image forming apparatus includes a print device, a tone correction unit, a peripheral light quantity drop detecting unit, and a color value correction unit. The tone correction unit corrects a tone characteristic of the print device based on color values of a plurality of color patches of each of a reference chart and a test chart in an image. The image is generated by simultaneously taking a reference sheet and a test sheet by an imaging device. The reference chart is drawn on the reference sheet. The test chart is printed on the test sheet by the print device. The peripheral light quantity drop detecting unit detects the amount of the peripheral light quantity drop in each of the patches based on the positions and luminances of the plurality of reference regions in the image and the positions of the patches in the image.
US09280732B2	Printing device, printing control method and recording medium capable of interruption printing with high security A LAN control unit receives print data from a client device or the like. An input job storage unit registered on a hard disk a series of PDL commands included in the print data received. An input job queue management unit registers print job specifying information specifying a print job represented by the print data received to the end of an input job queue. A PDL interpretation/execution unit successively executes from the head of the series of PDL commands stored on the hard disk device. When it is determined that the PDL command that has been executed is a re-execution unnecessary command, the PDL interpretation/execution unit overwrites the PDL command stored on the hard disk with a NOP command.
US09280730B2	Printing apparatus and method of controlling the same, and storage medium There are provided a printing apparatus which holds a job, determines whether attribution information of a sheet to be used by the stored job is registered for a sheet storage unit, judges whether a sheet exists in a sheet storage unit to be used by the job, and notifies a result of the determination and a result of the judgment.
US09280727B2	Information processing unit, printing control method for printer driver, and computer program product A information processing unit includes: a control unit configured to control operation processing of individual units through a user interface; a print set value storage unit configured to store a print set value that is set by operation of an operation unit on a basic setting screen displayed on a display unit on which setting relating to the color printing is performed at a basic level and a print detail set value that is set by operation of the operation unit on a detail setting screen as another dialog on which the setting is performed at a detail level under operation control of the control unit; and a print data creating unit configured to create print data of the color printing based on the print set value and the print detail set value under operation control of the control unit.
US09280725B2	Information processing apparatus, information processing method, and non-transitory computer readable medium An information processing apparatus includes a network creating unit that creates a network in which respective characters of plural character recognition results are represented as nodes, and in which nodes of adjacent character images are connected with a link, a first determining unit that determines a first candidate boundary in the network, a second determining unit that determines a second candidate boundary different from the first candidate boundary in the network, and an extracting unit that extracts, as to-be-searched objects, plural candidate character strings from a set of candidate character strings each formed of nodes between the first candidate boundary and the second candidate boundary.
US09280724B2	Pose classification apparatus and method A pose classification apparatus is provided. The apparatus includes a first image analyzer and a second image analyzer configured to estimate a body part for each pixel of an input image including a human body, a body part decider configured to calculate reliabilities of analysis results of the first image analyzer and the second image analyzer, and configured to decide the body part for each pixel of the input image based on the calculated reliabilities, and a pose estimator configured to estimate a pose of the human body included in the input image, based on the decided body part for each pixel.
US09280712B2	Apparatus and method for recognizing a lane An apparatus for recognizing a lane is provided. The apparatus performs a near-field white line recognition process and calculates road parameters (lane position, lane inclination, lane curvature and lane width) near the vehicle. The road parameters are calculated using the extended Kalman filter. In the calculation, the calculated lane curvature is used as a lane curvature to be included in predicted values. The apparatus outputs the calculated road parameters to a warning/vehicle-control apparatus.
US09280710B1	Bus detection for an autonomous vehicle Methods and systems are provided that may allow an autonomous vehicle to discern a school bus from image data. An example method may include receiving image data indicative of a vehicles operating in an environment. The image data may depict sizes of the vehicles. The method may also include, based on relative sizes of the vehicles, determining a vehicle that is larger in size as compared the other vehicles. The method may additionally include comparing a size of the determined vehicle to a size of a school bus and based on the size of vehicle being within a threshold size of the school bus, comparing a color of the vehicle to a color of the school bus. The method may further include based on the vehicle being substantially the same color as the school bus, determining that the vehicle is representative of the school bus.
US09280705B2	Image quality evaluation method, system, and computer readable storage medium based on an alternating current component differential value Disclosed is a picture quality evaluation method that evaluates the quality of a second image based on alternating current component measurements for a pixel set in a first image and alternating current component measurements for a pixel set in a second image in the same location as the pixel set in the first image.
US09280704B2	Communicating wireless pairing information for pairing an electronic device to a host system During a pairing procedure between an electronic device and a host system, the host system may output audiovisual data that communicates wireless pairing information. The electronic device may detect the audiovisual data and determine the wireless pairing information by processing the audiovisual data that it detects. The wireless pairing information may facilitate pairing the electronic device to the host system in accordance with the short-range wireless communication protocol.
US09280703B2	Apparatus and method for tracking hand Disclosed are an apparatus for tracking a location of a hand, includes: a skin color image detector for detecting a skin color region from an image input from an image device using a predetermined skin color of a user; a face tracker for tracking a face using the detected skin color image; a motion detector for setting a ROI using location information of the tracked face, and detecting a motion image from the set ROI; a candidate region extractor for extracting a candidate region with respect to a hand of the user using the skin color image detected by the skin color image detector and the motion image detected by the motion detector; and a hand tracker for tracking a location of the hand in the extracted candidate region to find out a final location of the hand.
US09280700B2	Method and apparatus for online signature verification using proximity touch A method and apparatus for verifying an input signature are provided. The method includes generating signature data based on a real touch event and a proximity touch event that occur on a touch input unit of and apparatus, extracting a feature of the input signature based on the signature data, and determining whether to authenticate the input signature based on a similarity between the feature of the input signature and a corresponding feature of a previously stored reference signature.
US09280698B2	Image processing apparatus, method, and program An image processing apparatus, a method, and a program for allowing cells to be quantitatively observed. A computer obtains a cell membrane image obtained by performing fluorescent observation on a cell membrane of a cell serving as a sample and a tricellular tight junction (tTJ) image obtained by performing fluorescent observation on a protein localized in a tTJ of the cell. The computer derives the size of area of a region of the cell by identifying the region of each cell from the cell membrane image, derives the size of area of the region of the protein localized in the cell from the tTJ image, and dividing the obtained size of area of the region of the protein by the size of area of the region of the cell, thus calculating an index of adhesion strength of the cells. The invention can be applied to an observation system.
US09280697B2	Authentication device including template validation and related methods An authentication device may include a housing and a finger sensor carried by the housing and including first processing circuitry and a finger sensing area coupled thereto. The first processing circuitry may be configured to generate finger image data based upon a finger positioned adjacent the finger sensing area, and generate and store a first template based upon the finger image data. The authentication device may include second processing circuitry carried by the housing and configured to obtain the finger image data from the first processing circuitry. The second processing circuitry may be configured to generate a second template based upon the finger image data. The first processing circuitry may further be configured to obtain the second template from second processing circuitry, and validate the second template against the first template.
US09280694B2	Decoding machine-readable optical codes with aesthetic component Techniques are provided for decoding machine-readable optical codes that have an aesthetic component that is integrated into the codes themselves. In this manner, the machine-readable optical codes can be designed to be aesthetically pleasing and/or can convey information to human viewers, and can even be disguised so that they do not appear to be machine-readable optical codes at all. Such information can be (but need not be) distinct from the information encoded for reading by a machine, even when the information is integrated into the code itself. The techniques described herein can be applied to any type of machine-readable optical code.
US09280692B2	Method and RFID reader for evaluating a data stream signal in respect of data and/or collision A method for evaluating, by an radio frequency identification reader (1), a data stream signal (DS) in respect of data and/or collision, comprises comparing the data stream signal (DS) with at least one threshold level, particularly a data bit level and/or a collision level, and evaluating the results of the comparison, wherein both the threshold level and its adaptation speed (α(n)) are adapted in dependence of the course of the data stream signal (DS) and/or the course of said threshold level.
US09280690B2	Writing apparatus, writing system, and writing method A writing apparatus to which an external writing unit is connected comprises a writing unit that write, to a write object provided to a conveyed item, identification information thereof; a first reading unit in downstream side in a conveying direction than the writing unit, that reads identification information from the write object; a determination unit that determines whether the read identification information is consistent with identification information having to be written to the write object; and a notification unit configured to, when it is determined that identification information written to a first write object and read by the first reading unit is inconsistent with identification information having to be written to the first write object, notify the external writing unit of recovery information including the identification information having to be written to the first write object and/or a write content thereof.
US09280688B2	Apparatus and method for limiting and analyzing stress corrosion cracking in pressurized water reactors A method to assess and predict pressurized water stress corrosion cracking in operational nuclear power plants and the effect of adding zinc compounds into a reactor coolant system of the nuclear power plant.
US09280680B2	Photobook with augmented social capability Method and system for providing an augmented photobook that includes at least one interactive feature. An image of a symbology printed on a page of a photobook is captured, and address information contained therein is decoded. A web browser of an electronic device is directed to a website identified by the address information, and additional information related to the photobook is received from a remote computing device associated with the website. The additional information related to the photobook is displayed on the electronic device. Additionally, a level of access to the website is determined for a user of the electronic device. A user request to transmit new content to the website is received it is determined whether the level of access corresponds to permission rights for the website. If the level of access corresponds to the permission rights then the new content is transmitted and aggregated at the website.
US09280674B2	Information processing apparatus and method of controlling same An information processing apparatus includes a memory and a processor coupled to the memory and configured to receive an instruction to transfer a first application to an execution environment, detect a second application that shares a resource with the first application, the resource being information used upon executing the first application and the second application, provide information for causing a user to determine whether to prohibit transferring the second application to the execution environment when the second application is detected, and invalidate a state in which the second application shares the resource with the first application when instruction to prohibit transferring the second application to the execution environment is received.
US09280673B2	Selectively allowing execution of a control command associated with a page description language in an image forming apparatus Disclosed is an image forming apparatus that connects to a device. The image forming apparatus includes a storage unit that stores, for each types of page description languages for describing printing data, permission information indicating whether execution of a control command described in the corresponding page description language is allowed; a receiving unit that receives the control command transmitted from the device; a determination unit that determines whether the execution of the control command is allowed for the image forming apparatus, based on the permission information being stored in the storage unit; and a controller that controls the image forming apparatus. When the execution of the image forming apparatus is disallowed for the image forming apparatus, the controller prevents the image forming apparatus from executing the control command.
US09280671B2	Semiconductor device and encryption key writing method A semiconductor device includes a CPU, an EEPROM, and a ROM. The ROM includes an encryption area and a non-encryption area and the encrypted firmware is stored in the encryption area. The semiconductor device includes a decrypter which holds the encryption key, decrypts the encrypted firmware, and supplies the decrypted firmware to the CPU. The EEPROM includes a system area to which an access from the CPU is forbidden in a user mode. The encryption key is divided into split keys of plural bit strings, and stored in the distributed address areas in the system area. An encryption key reading program which is not encrypted is stored in the non-encryption area of the ROM. Executing the encryption key reading program, the CPU reads and reconfigures plural split keys stored in the EEPROM in a distributed manner to restore the encryption key and supplies the restored encryption key to the decrypter.
US09280669B2	Systems, methods and computer readable media for calculating a security index of an application hosted in a cloud environment The present invention provides a method and system for calculating a security index of an application hosted in a cloud environment. The application is mapped to a cloud service provider of the cloud environment, and a set of security controls and a set of security metrics applicable for the application are identified. The set of security controls and the set of security metrics are encapsulated into a security profile object by a security control module. A set of values of the set of security metrics are retrieved from the cloud service provider, by a cloud probe module, and the security index of the application is calculated.
US09280656B2	Device and method for providing security channel interface A security channel interface providing device is provided. The device includes a sensor unit that comprises at least two sensors configured to sense a motion of a user, and a control unit that determines whether or not at least two sensing values sensed by the sensors satisfy a security channel interface activation condition, and activates or inactivates a security channel interface according to a result of the determination. When the security channel interface is activated, the control unit provides a security channel to the user.
US09280655B2	Application authentication method and electronic device supporting the same A method for operating an electronic device is provided. The method includes executing, by a processor of the electronic device operable in a first mode (e.g. a trusted execution environment (TEE)) or a second mode (e.g. a non-trusted execution environment (NTEE)), wherein the first mode is more secure than the second mode; receiving, by the processor operating in the first mode, data or information related to a first software program stored in a first memory region; and authenticating, by the processor operating in the first mode, at least a portion of the data or information using a second software program stored in a second memory region.
US09280653B2	Security access method for automotive electronic control units A system and method for employing a mechanism for unlocking a vehicle ECU. The ECU stores a unique ECU identification value that identifies the particular ECU and a secure server stores the ECU identification value and a unique ECU security key value, where the identification value identifies the security key value in the server, and where the secure server stores the unique ECU identification value and the unique security key value for many ECUs. A service tool that wants to gain access to the ECU for software reprogramming or service requests the ECU identification value and a challenge from the ECU and sends them to the secure server, which then identifies the security key value associated with that ECU identification value and the response for the challenge. The secure server then sends the response to the service tool, which provides it to the ECU to unlock it for programming.
US09280652B1	Secure device unlock with gaze calibration An unlock procedure for an electronic device can be based at least in part upon a determined gaze direction or viewing location of a user. During a device unlock process, the user can be directed to follow an element or path on a display element with the user's eyes. Image information captured of the user during this process can be used to correlate the user's eye position in the image with the corresponding gaze location on the device, in order to calibrate the gaze tracking in a way that is substantially transparent to the user. Further, certain devices can also utilize captured image information during the unlock process to authenticate the user using a process such as iris recognition or retinal scanning. Such an approach enables secure access to the device without requiring the user to manually enter identifying information, and re-authentication can be performed without distracting the user.
US09280649B2	Apparatus and method for detecting an object from an image A user detecting apparatus includes: a memory; and a processor that executes a procedure, the procedure including: obtaining a first image and a second image, extracting a user-associated area from the first image according to a given condition, dividing the user-associated area into a plurality of areas, storing a histogram of each of the plurality of areas in the memory, detecting from the second image a corresponding area that corresponds to an area that is one of the plurality of areas and has a first reference histogram according to similarity, and changing a reference histogram used for a third image from the first reference histogram to a second reference histogram.

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